1*53ee8cc1Swenshuai.xi #ifndef __HDLC_IOCTL_H__ 2*53ee8cc1Swenshuai.xi #define __HDLC_IOCTL_H__ 3*53ee8cc1Swenshuai.xi 4*53ee8cc1Swenshuai.xi 5*53ee8cc1Swenshuai.xi #define GENERIC_HDLC_VERSION 4 /* For synchronization with sethdlc utility */ 6*53ee8cc1Swenshuai.xi 7*53ee8cc1Swenshuai.xi #define CLOCK_DEFAULT 0 /* Default setting */ 8*53ee8cc1Swenshuai.xi #define CLOCK_EXT 1 /* External TX and RX clock - DTE */ 9*53ee8cc1Swenshuai.xi #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */ 10*53ee8cc1Swenshuai.xi #define CLOCK_TXINT 3 /* Internal TX and external RX clock */ 11*53ee8cc1Swenshuai.xi #define CLOCK_TXFROMRX 4 /* TX clock derived from external RX clock */ 12*53ee8cc1Swenshuai.xi 13*53ee8cc1Swenshuai.xi 14*53ee8cc1Swenshuai.xi #define ENCODING_DEFAULT 0 /* Default setting */ 15*53ee8cc1Swenshuai.xi #define ENCODING_NRZ 1 16*53ee8cc1Swenshuai.xi #define ENCODING_NRZI 2 17*53ee8cc1Swenshuai.xi #define ENCODING_FM_MARK 3 18*53ee8cc1Swenshuai.xi #define ENCODING_FM_SPACE 4 19*53ee8cc1Swenshuai.xi #define ENCODING_MANCHESTER 5 20*53ee8cc1Swenshuai.xi 21*53ee8cc1Swenshuai.xi 22*53ee8cc1Swenshuai.xi #define PARITY_DEFAULT 0 /* Default setting */ 23*53ee8cc1Swenshuai.xi #define PARITY_NONE 1 /* No parity */ 24*53ee8cc1Swenshuai.xi #define PARITY_CRC16_PR0 2 /* CRC16, initial value 0x0000 */ 25*53ee8cc1Swenshuai.xi #define PARITY_CRC16_PR1 3 /* CRC16, initial value 0xFFFF */ 26*53ee8cc1Swenshuai.xi #define PARITY_CRC16_PR0_CCITT 4 /* CRC16, initial 0x0000, ITU-T version */ 27*53ee8cc1Swenshuai.xi #define PARITY_CRC16_PR1_CCITT 5 /* CRC16, initial 0xFFFF, ITU-T version */ 28*53ee8cc1Swenshuai.xi #define PARITY_CRC32_PR0_CCITT 6 /* CRC32, initial value 0x00000000 */ 29*53ee8cc1Swenshuai.xi #define PARITY_CRC32_PR1_CCITT 7 /* CRC32, initial value 0xFFFFFFFF */ 30*53ee8cc1Swenshuai.xi 31*53ee8cc1Swenshuai.xi #define LMI_DEFAULT 0 /* Default setting */ 32*53ee8cc1Swenshuai.xi #define LMI_NONE 1 /* No LMI, all PVCs are static */ 33*53ee8cc1Swenshuai.xi #define LMI_ANSI 2 /* ANSI Annex D */ 34*53ee8cc1Swenshuai.xi #define LMI_CCITT 3 /* ITU-T Annex A */ 35*53ee8cc1Swenshuai.xi #define LMI_CISCO 4 /* The "original" LMI, aka Gang of Four */ 36*53ee8cc1Swenshuai.xi 37*53ee8cc1Swenshuai.xi typedef struct { 38*53ee8cc1Swenshuai.xi unsigned int clock_rate; /* bits per second */ 39*53ee8cc1Swenshuai.xi unsigned int clock_type; /* internal, external, TX-internal etc. */ 40*53ee8cc1Swenshuai.xi unsigned short loopback; 41*53ee8cc1Swenshuai.xi } sync_serial_settings; /* V.35, V.24, X.21 */ 42*53ee8cc1Swenshuai.xi 43*53ee8cc1Swenshuai.xi typedef struct { 44*53ee8cc1Swenshuai.xi unsigned int clock_rate; /* bits per second */ 45*53ee8cc1Swenshuai.xi unsigned int clock_type; /* internal, external, TX-internal etc. */ 46*53ee8cc1Swenshuai.xi unsigned short loopback; 47*53ee8cc1Swenshuai.xi unsigned int slot_map; 48*53ee8cc1Swenshuai.xi } te1_settings; /* T1, E1 */ 49*53ee8cc1Swenshuai.xi 50*53ee8cc1Swenshuai.xi typedef struct { 51*53ee8cc1Swenshuai.xi unsigned short encoding; 52*53ee8cc1Swenshuai.xi unsigned short parity; 53*53ee8cc1Swenshuai.xi } raw_hdlc_proto; 54*53ee8cc1Swenshuai.xi 55*53ee8cc1Swenshuai.xi typedef struct { 56*53ee8cc1Swenshuai.xi unsigned int t391; 57*53ee8cc1Swenshuai.xi unsigned int t392; 58*53ee8cc1Swenshuai.xi unsigned int n391; 59*53ee8cc1Swenshuai.xi unsigned int n392; 60*53ee8cc1Swenshuai.xi unsigned int n393; 61*53ee8cc1Swenshuai.xi unsigned short lmi; 62*53ee8cc1Swenshuai.xi unsigned short dce; /* 1 for DCE (network side) operation */ 63*53ee8cc1Swenshuai.xi } fr_proto; 64*53ee8cc1Swenshuai.xi 65*53ee8cc1Swenshuai.xi typedef struct { 66*53ee8cc1Swenshuai.xi unsigned int dlci; 67*53ee8cc1Swenshuai.xi } fr_proto_pvc; /* for creating/deleting FR PVCs */ 68*53ee8cc1Swenshuai.xi 69*53ee8cc1Swenshuai.xi typedef struct { 70*53ee8cc1Swenshuai.xi unsigned int dlci; 71*53ee8cc1Swenshuai.xi char master[IFNAMSIZ]; /* Name of master FRAD device */ 72*53ee8cc1Swenshuai.xi }fr_proto_pvc_info; /* for returning PVC information only */ 73*53ee8cc1Swenshuai.xi 74*53ee8cc1Swenshuai.xi typedef struct { 75*53ee8cc1Swenshuai.xi unsigned int interval; 76*53ee8cc1Swenshuai.xi unsigned int timeout; 77*53ee8cc1Swenshuai.xi } cisco_proto; 78*53ee8cc1Swenshuai.xi 79*53ee8cc1Swenshuai.xi /* PPP doesn't need any info now - supply length = 0 to ioctl */ 80*53ee8cc1Swenshuai.xi 81*53ee8cc1Swenshuai.xi #endif /* __HDLC_IOCTL_H__ */ 82