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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvDMD_common.h 98 /// @brief DVBC Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 /*! \defgroup Demod Demod interface 103 104 105 Peripheral functions are controlled by each DEMOD standard 106 107 <b>Features</b> 108 109 - Registers read/write. 110 - I2C, RF/IF, TS and SSPI control. 111 112 <b>ATSC Interface brief</b> 113 ATSC is the demodulator of supporting 8VSB and J83B standard. 114 Receive RF signal from Tuner and transmit demodulated data to TS module. 115 116 <b>Features</b> 117 118 - Support 8VSB and J83B standard. 119 - Pass A74 SPEC. 120 - Pass the field stream. 121 122 <b> ATSC Block Diagram: </b> \n 123 \image html drvDMD_ATSC_pic01.png 124 125 <b> Operation Code Flow: </b> \n 126 -# Initialize ATSC parameters and load DEMOD FW 127 -# Enable DEMOD state machine 128 -# Monitor lock status 129 130 <b>DTMB interface brief</b> 131 DTMB is the demodulator of supporting DTMB(6/7/8/9M) standard. 132 Receive RF signal from Tuner and transmit demodulated data to TS module. 133 134 <b>Features</b> 135 136 - Support DTMB(6/7/8/9M) standard. 137 - Pass CHINA SPEC. 138 - Pass the field stream. 139 140 <b> DTMB Block Diagram: </b> \n 141 \image html drvDMD_DTMB_pic01.png 142 143 <b> Operation Code Flow: </b> \n 144 -# Initialize DTMB parameters and load DEMOD FW 145 -# Enable DEMOD state machine 146 -# Monitor lock status 147 148 *! \defgroup COMMON COMMON interface (drvDMD_common.h) 149 * \ingroup Demod 150 151 *! \defgroup COMMON_BASIC COMMON basic control 152 * \ingroup COMMON 153 */ 154 155 #ifndef _DRV_DMD_COMMON_H_ 156 #define _DRV_DMD_COMMON_H_ 157 158 #ifdef __cplusplus 159 extern "C" 160 { 161 #endif 162 163 164 //------------------------------------------------------------------------------------------------- 165 // Driver Capability 166 //------------------------------------------------------------------------------------------------- 167 168 169 //------------------------------------------------------------------------------------------------- 170 // Macro and Define 171 //------------------------------------------------------------------------------------------------- 172 #define USE_UTOPIA2P0 173 174 //------------------------------------------------------------------------------------------------- 175 // Type and Structure 176 //------------------------------------------------------------------------------------------------- 177 typedef enum 178 { 179 _QPSK = 0x0, 180 _16QAM = 0x1, 181 _64QAM = 0x2, 182 _UNKNOW_QAM = 0xff, 183 }DMD_CONSTEL; 184 185 typedef enum 186 { 187 _CR1Y2 = 0x0, 188 _CR2Y3 = 0x1, 189 _CR3Y4 = 0x2, 190 _CR5Y6 = 0x3, 191 _CR7Y8 = 0x4, 192 _UNKNOW_CR = 0xff, 193 }DMD_CODERATE; 194 195 typedef struct 196 { 197 float power_db; 198 MS_U8 sar3_val; 199 }DMD_RFAGC_SSI; 200 201 typedef struct 202 { 203 float power_db; 204 MS_U8 agc_val; 205 }DMD_IFAGC_SSI; 206 207 typedef struct 208 { 209 float attn_db; 210 MS_U8 agc_err; 211 }DMD_IFAGC_ERR; 212 213 typedef struct 214 { 215 DMD_CONSTEL constel; 216 DMD_CODERATE code_rate; 217 float p_ref; 218 }DMD_SSI_DBM_NORDIGP1; 219 220 typedef struct 221 { 222 DMD_CONSTEL constel; 223 DMD_CODERATE code_rate; 224 float cn_ref; 225 }DMD_SQI_CN_NORDIGP1; 226 227 typedef struct 228 { 229 DMD_RFAGC_SSI *pRfagcSsi; 230 MS_U16 u16RfagcSsi_Size; 231 DMD_IFAGC_SSI *pIfagcSsi_LoRef; 232 MS_U16 u16IfagcSsi_LoRef_Size; 233 DMD_IFAGC_SSI *pIfagcSsi_HiRef; 234 MS_U16 u16IfagcSsi_HiRef_Size; 235 DMD_IFAGC_ERR *pIfagcErr_LoRef; 236 MS_U16 u16IfagcErr_LoRef_Size; 237 DMD_IFAGC_ERR *pIfagcErr_HiRef; 238 MS_U16 u16IfagcErr_HiRef_Size; 239 }DMD_SSI_TABLE; 240 241 typedef struct _s_I2C_Interface_func 242 { 243 MS_BOOL (*I2C_WriteBytes)(MS_U16 u16BusNumSlaveID, MS_U8 u8addrcount, MS_U8* pu8addr, MS_U16 u16size, MS_U8* pu8data); 244 MS_BOOL (*I2C_ReadBytes)(MS_U16 u16BusNumSlaveID, MS_U8 u8AddrNum, MS_U8* paddr, MS_U16 u16size, MS_U8* pu8data); 245 }s_I2C_Interface_func; 246 247 248 //------------------------------------------------------------------------------------------------- 249 // Function and Variable 250 //------------------------------------------------------------------------------------------------- 251 //------------------------------------------------------------------------------------------------- 252 /// Register DEMOD bank address 253 /// @ingroup COMMON_BASIC 254 /// @return TRUE : succeed 255 /// @return FALSE : fail 256 //------------------------------------------------------------------------------------------------- 257 DLL_PUBLIC MS_BOOL MDrv_DMD_PreInit(void); 258 //------------------------------------------------------------------------------------------------- 259 /// Enable RF AGC Tristate 260 /// @ingroup COMMON_BASIC 261 /// @param bEnable \b IN: Enable as TRUE 262 /// @return : NULL 263 //------------------------------------------------------------------------------------------------- 264 DLL_PUBLIC void MDrv_DMD_RFAGC_Tristate(MS_BOOL bEnable); 265 //------------------------------------------------------------------------------------------------- 266 /// Enable IF AGC Tristate 267 /// @ingroup COMMON_BASIC 268 /// @param bEnable \b IN: Enable as TRUE 269 /// @return : NULL 270 //------------------------------------------------------------------------------------------------- 271 DLL_PUBLIC void MDrv_DMD_IFAGC_Tristate(MS_BOOL bEnable); 272 //------------------------------------------------------------------------------------------------- 273 /// Get TS clock rate 274 /// @ingroup COMMON_BASIC 275 /// @param fTS_CLK \b OUT: the pointer to TS clock rate 276 /// @return TRUE : succeed 277 /// @return FALSE : fail 278 //------------------------------------------------------------------------------------------------- 279 // DLL_PUBLIC MS_BOOL MDrv_DMD_TS_GetClockRate(float *fTS_CLK); 280 //------------------------------------------------------------------------------------------------- 281 /// ts output clock frequency and phase configure 282 /// @ingroup COMMON_BASIC 283 /// @param u8cmd_array \b IN: the pointer to TS clock configuration 284 /// @return TRUE : succeed 285 /// @return FALSE : fail 286 //------------------------------------------------------------------------------------------------- 287 DLL_PUBLIC MS_BOOL MDrv_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array); 288 //------------------------------------------------------------------------------------------------- 289 /// read register data 290 /// @ingroup COMMON_BASIC 291 /// @param u32Reg \b IN: register address 292 /// @param u8Value \b OUT: the pointer to register data 293 /// @return TRUE : succeed 294 /// @return FALSE : fail 295 //------------------------------------------------------------------------------------------------- 296 DLL_PUBLIC MS_BOOL MDrv_DMD_ReadReg(MS_U32 u32Reg, MS_U8 *u8Value); 297 //------------------------------------------------------------------------------------------------- 298 /// write register data 299 /// @ingroup COMMON_BASIC 300 /// @param u32Reg \b IN: register address 301 /// @param u8Value \b IN: register data 302 /// @return TRUE : succeed 303 /// @return FALSE : fail 304 //------------------------------------------------------------------------------------------------- 305 DLL_PUBLIC MS_BOOL MDrv_DMD_WriteReg(MS_U32 u32Reg, MS_U8 u8Value); 306 //------------------------------------------------------------------------------------------------- 307 /// write register data for more than one byte 308 /// @ingroup COMMON_BASIC 309 /// @param u32Reg \b IN: register address 310 /// @param u8Value \b IN: the pointer to data 311 /// @param u8Length \b IN: length of data 312 /// @return TRUE : succeed 313 /// @return FALSE : fail 314 //------------------------------------------------------------------------------------------------- 315 // DLL_PUBLIC MS_BOOL MDrv_DMD_WriteRegs(MS_U32 u32Reg, MS_U8 *u8Value, MS_U8 u8Length); 316 //------------------------------------------------------------------------------------------------- 317 /// Change I2C channel 318 /// @ingroup COMMON_BASIC 319 /// @param ch_num \b IN: I2C channel number 320 /// @return TRUE : succeed 321 /// @return FALSE : fail 322 //------------------------------------------------------------------------------------------------- 323 // DLL_PUBLIC MS_BOOL MDrv_DMD_I2C_Channel_Change(MS_U8 ch_num); 324 //------------------------------------------------------------------------------------------------- 325 /// Set I2C channel 326 /// @ingroup COMMON_BASIC 327 /// @param ch_num \b IN: I2C channel number 328 /// @return TRUE : succeed 329 /// @return FALSE : fail 330 //------------------------------------------------------------------------------------------------- 331 // DLL_PUBLIC MS_BOOL MDrv_DMD_I2C_Channel_Set(MS_U8 ch_num); 332 //------------------------------------------------------------------------------------------------- 333 /// Initialize SSPI interface 334 /// @ingroup COMMON_BASIC 335 /// @param u8DeviceNum \b IN: SSPI device number 336 /// @return TRUE : succeed 337 /// @return FALSE : fail 338 //------------------------------------------------------------------------------------------------- 339 // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_Init(MS_U8 u8DeviceNum); 340 //------------------------------------------------------------------------------------------------- 341 /// MIU write data more than one byte per SSPI interface 342 /// @ingroup COMMON_BASIC 343 /// @param u32Addr \b IN: register address 344 /// @param pdata \b IN: the pointer to data 345 /// @param u16Size \b IN: length of data 346 /// @return TRUE : succeed 347 /// @return FALSE : fail 348 //------------------------------------------------------------------------------------------------- 349 // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_MIU_Writes(MS_U32 u32Addr, MS_U8 *pdata, MS_U16 u16Size); 350 //------------------------------------------------------------------------------------------------- 351 /// MIU read data more than one byte per SSPI interface 352 /// @ingroup COMMON_BASIC 353 /// @param u32Addr \b IN: register address 354 /// @param pdata \b IN: the pointer to data 355 /// @param u16Size \b IN: length of data 356 /// @return TRUE : succeed 357 /// @return FALSE : fail 358 //------------------------------------------------------------------------------------------------- 359 // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_MIU_Reads(MS_U32 u32Addr, MS_U8 *pdata, MS_U16 u16Size); 360 //------------------------------------------------------------------------------------------------- 361 /// MIU write data per SSPI interface 362 /// @ingroup COMMON_BASIC 363 /// @param u16Addr \b IN: register address 364 /// @param data \b IN: register data 365 /// @return TRUE : succeed 366 /// @return FALSE : fail 367 //------------------------------------------------------------------------------------------------- 368 // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_RIU_Write8(MS_U16 u16Addr, MS_U8 data); 369 //------------------------------------------------------------------------------------------------- 370 /// MIU read data per SSPI interface 371 /// @ingroup COMMON_BASIC 372 /// @param u16Addr \b IN: register address 373 /// @param pdata \b out: register data 374 /// @return TRUE : succeed 375 /// @return FALSE : fail 376 //------------------------------------------------------------------------------------------------- 377 // DLL_PUBLIC MS_BOOL MDrv_DMD_SSPI_RIU_Read8(MS_U16 u16Addr, MS_U8 *pdata); 378 379 #ifdef __cplusplus 380 } 381 #endif 382 383 384 #endif // _DRV_DVBC_H_ 385 386