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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file apiHDMITx.h 98 /// @brief HDMITx Interface 99 /// @author MStar Semiconductor Inc. 100 /// 101 /// CL351033++: 102 /// Add CEC function for STB 103 /// CL310477++: 104 /// Open analog setting for the different board condition 105 /// CL309397++: 106 /// Modify apiHDMITx prototype for NDS 107 /// CL308729++: 108 /// Fix AVMUTE problem while HDCP is on 109 /// CL299817++: 110 /// i. Add I2C timeout mechanism in EDID and HDCP 111 /// ii. Add SET_AVMUTE API to avoid transition garbage noise while timing changed ]]> 112 /// CL288415++: 113 /// Add SRM DSA Signature Checking function 114 /// CL283331++: 115 /// Fix HDMI v1.3 deep color mode output unstable problem 116 /// CL282607++: 117 /// i. Fix YUV422 / YUV444 bugs 118 /// ii. Add MApi_HDMITx_GetHdcpKey() to get HDCP key from external storage. 119 /// CL276751++: 120 /// Modify HDMI / HDCP state mechine for NDS 121 /// CL275230++: 122 /// i. MApi_HDMITx_GetRxDCInfoFromEDID() to get Rx's deep color information from EDID 123 /// ii. MApi_HDMITx_SetHDMITxMode_CD() to set output mode and deep color setting 124 /// CL266666++: 125 /// Add event report for NDS 126 /// CL263961++: 127 /// Add CEC init and checkbuffer for NDS 128 /// CL260934++: 129 /// Add some customized APIs for NDS 130 /// CL259645++: 131 /// i. Remove EDID header check. If header is wrong, force to DVI output 132 /// ii. Add force output mode "MApi_HDMITx_ForceHDMIOutputMode()" 133 /////////////////////////////////////////////////////////////////////////////////////////////////// 134 135 #ifndef _API_HDMITX_H_ 136 #define _API_HDMITX_H_ 137 138 #include "MsTypes.h" 139 //#include "halHDMITx.h" 140 //#include "drvHDMITx.h" 141 //#include "regHDMITx.h" 142 143 144 145 #ifdef __cplusplus 146 extern "C" 147 { 148 #endif 149 150 151 //------------------------------------------------------------------------------------------------- 152 // Macro and Define 153 //------------------------------------------------------------------------------------------------- 154 155 156 //------------------------------------------------------------------------------------------------- 157 // Type and Structure 158 //------------------------------------------------------------------------------------------------- 159 #define MSIF_HDMITX_LIB_CODE {'H','D','M','I'} 160 #define MSIF_HDMITX_LIBVER {'0','0'} 161 #define MSIF_HDMITX_BUILDNUM {'2','0'} 162 #define MSIF_HDMITX_CHANGELIST {'0','0','6','7','7','7','7','2'} 163 #define HDMITX_API_VERSION /* Character String for DRV/API version */ \ 164 MSIF_TAG, /* 'MSIF' */ \ 165 MSIF_CLASS, /* '00' */ \ 166 MSIF_CUS, /* 0x0000 */ \ 167 MSIF_MOD, /* 0x0000 */ \ 168 MSIF_CHIP, \ 169 MSIF_CPU, \ 170 MSIF_HDMITX_LIB_CODE, /* IP__ */ \ 171 MSIF_HDMITX_LIBVER, /* 0.0 ~ Z.Z */ \ 172 MSIF_HDMITX_BUILDNUM, /* 00 ~ 99 */ \ 173 MSIF_HDMITX_CHANGELIST, /* CL# */ \ 174 MSIF_OS 175 176 typedef enum 177 { 178 HDMITX_DVI = 0, // DVI without HDCP 179 HDMITX_DVI_HDCP = 1, // DVI with HDCP 180 HDMITX_HDMI = 2, // HDMI without HDCP 181 HDMITX_HDMI_HDCP = 3, // HDMI with HDCP 182 } HDMITX_OUTPUT_MODE; 183 184 typedef enum 185 { 186 HDMITX_SEND_PACKET = 0x00, // send packet 187 HDMITX_CYCLIC_PACKET = 0x04, // cyclic packet by frame count 188 HDMITX_STOP_PACKET = 0x80, // stop packet 189 } HDMITX_PACKET_PROCESS; 190 191 typedef enum 192 { 193 HDMITX_NULL_PACKET = 0x00, 194 HDMITX_ACR_PACKET = 0x01, 195 HDMITX_AS_PACKET = 0x02, 196 HDMITX_GC_PACKET = 0x03, 197 HDMITX_ACP_PACKET = 0x04, 198 HDMITX_ISRC1_PACKET = 0x05, 199 HDMITX_ISRC2_PACKET = 0x06, 200 HDMITX_DSD_PACKET = 0x07, 201 HDMITX_HBR_PACKET = 0x09, 202 HDMITX_GM_PACKET = 0x0A, 203 204 HDMITX_VS_INFOFRAME = 0x81, 205 HDMITX_AVI_INFOFRAME = 0x82, 206 HDMITX_SPD_INFOFRAME = 0x83, 207 HDMITX_AUDIO_INFOFRAME = 0x84, 208 HDMITX_MPEG_INFOFRAME = 0x85, 209 } HDMITX_PACKET_TYPE; 210 211 typedef enum 212 { 213 HDMITX_VIDEO_CD_NoID = 0, // DVI mode 214 HDMITX_VIDEO_CD_24Bits = 4, // HDMI 8 bits 215 HDMITX_VIDEO_CD_30Bits = 5, // HDMI 10 bits 216 HDMITX_VIDEO_CD_36Bits = 6, // HDMI 12 bits 217 HDMITX_VIDEO_CD_48Bits = 7, // HDMI 16 bits 218 } HDMITX_VIDEO_COLORDEPTH_VAL; 219 220 typedef enum 221 { 222 HDMITX_VIDEO_COLOR_RGB444 = 0, 223 HDMITX_VIDEO_COLOR_YUV422 = 1, 224 HDMITX_VIDEO_COLOR_YUV444 = 2, 225 HDMITX_VIDEO_COLOR_YUV420 = 3, 226 } HDMITX_VIDEO_COLOR_FORMAT; 227 228 typedef enum 229 { 230 HDMITX_RES_640x480p =0, 231 HDMITX_RES_720x480i = 1, 232 HDMITX_RES_720x576i = 2, 233 HDMITX_RES_720x480p = 3, 234 HDMITX_RES_720x576p = 4, 235 HDMITX_RES_1280x720p_50Hz = 5, 236 HDMITX_RES_1280x720p_60Hz = 6, 237 HDMITX_RES_1920x1080i_50Hz = 7, 238 HDMITX_RES_1920x1080i_60Hz = 8, 239 HDMITX_RES_1920x1080p_24Hz = 9, 240 HDMITX_RES_1920x1080p_25Hz = 10, 241 HDMITX_RES_1920x1080p_30Hz = 11, 242 HDMITX_RES_1920x1080p_50Hz = 12, 243 HDMITX_RES_1920x1080p_60Hz = 13, 244 HDMITX_RES_1920x2205p_24Hz = 14, 245 HDMITX_RES_1280X1470p_50Hz = 15, 246 HDMITX_RES_1280X1470p_60Hz = 16, 247 HDMITX_RES_3840x2160p_24Hz = 17, 248 HDMITX_RES_3840x2160p_25Hz = 18, 249 HDMITX_RES_3840x2160p_30Hz = 19, 250 HDMITX_RES_3840x2160p_50Hz = 20, 251 HDMITX_RES_3840x2160p_60Hz = 21, 252 HDMITX_RES_4096x2160p_24Hz = 22, 253 HDMITX_RES_4096x2160p_25Hz = 23, 254 HDMITX_RES_4096x2160p_30Hz = 24, 255 HDMITX_RES_4096x2160p_50Hz = 25, 256 HDMITX_RES_4096x2160p_60Hz = 26, 257 HDMITX_RES_MAX = 27, 258 } HDMITX_VIDEO_TIMING; 259 260 typedef enum 261 { 262 HDMITX_VIC_NOT_AVAILABLE = 0, 263 HDMITX_VIC_640x480p_60_4_3 = 1, 264 HDMITX_VIC_720x480p_60_4_3 = 2, 265 HDMITX_VIC_720x480p_60_16_9 = 3, 266 HDMITX_VIC_1280x720p_60_16_9 = 4, 267 HDMITX_VIC_1920x1080i_60_16_9 = 5, 268 HDMITX_VIC_720x480i_60_4_3 = 6, 269 HDMITX_VIC_720x480i_60_16_9 = 7, 270 HDMITX_VIC_720x240p_60_4_3 = 8, 271 HDMITX_VIC_720x240p_60_16_9 = 9, 272 HDMITX_VIC_2880x480i_60_4_3 = 10, 273 HDMITX_VIC_2880x480i_60_16_9 = 11, 274 HDMITX_VIC_2880x240p_60_4_3 = 12, 275 HDMITX_VIC_2880x240p_60_16_9 = 13, 276 HDMITX_VIC_1440x480p_60_4_3 = 14, 277 HDMITX_VIC_1440x480p_60_16_9 = 15, 278 HDMITX_VIC_1920x1080p_60_16_9 = 16, 279 HDMITX_VIC_720x576p_50_4_3 = 17, 280 HDMITX_VIC_720x576p_50_16_9 = 18, 281 HDMITX_VIC_1280x720p_50_16_9 = 19, 282 HDMITX_VIC_1920x1080i_50_16_9 = 20, 283 HDMITX_VIC_720x576i_50_4_3 = 21, 284 HDMITX_VIC_720x576i_50_16_9 = 22, 285 HDMITX_VIC_720x288p_50_4_3 = 23, 286 HDMITX_VIC_720x288p_50_16_9 = 24, 287 HDMITX_VIC_2880x576i_50_4_3 = 25, 288 HDMITX_VIC_2880x576i_50_16_9 = 26, 289 HDMITX_VIC_2880x288p_50_4_3 = 27, 290 HDMITX_VIC_2880x288p_50_16_9 = 28, 291 HDMITX_VIC_1440x576p_50_4_3 = 29, 292 HDMITX_VIC_1440x576p_50_16_9 = 30, 293 HDMITX_VIC_1920x1080p_50_16_9 = 31, 294 HDMITX_VIC_1920x1080p_24_16_9 = 32, 295 HDMITX_VIC_1920x1080p_25_16_9 = 33, 296 HDMITX_VIC_1920x1080p_30_16_9 = 34, 297 HDMITX_VIC_2880x480p_60_4_3 = 35, 298 HDMITX_VIC_2880x480p_60_16_9 = 36, 299 HDMITX_VIC_2880x576p_50_4_3 = 37, 300 HDMITX_VIC_2880x576p_50_16_9 = 38, 301 HDMITX_VIC_1920x1080i_50_16_9_1250_total = 39, 302 HDMITX_VIC_1920x1080i_100_16_9 = 40, 303 HDMITX_VIC_1280x720p_100_16_9 = 41, 304 HDMITX_VIC_720x576p_100_4_3 = 42, 305 HDMITX_VIC_720x576p_100_16_9 = 43, 306 HDMITX_VIC_720x576i_100_4_3 = 44, 307 HDMITX_VIC_720x576i_100_16_9 = 45, 308 HDMITX_VIC_1920x1080i_120_16_9 = 46, 309 HDMITX_VIC_1280x720p_120_16_9 = 47, 310 HDMITX_VIC_720x480p_120_4_3 = 48, 311 HDMITX_VIC_720x480p_120_16_9 = 49, 312 HDMITX_VIC_720x480i_120_4_3 = 50, 313 HDMITX_VIC_720x480i_120_16_9 = 51, 314 HDMITX_VIC_720x576p_200_4_3 = 52, 315 HDMITX_VIC_720x576p_200_16_9 = 53, 316 HDMITX_VIC_720x576i_200_4_3 = 54, 317 HDMITX_VIC_720x576i_200_16_9 = 55, 318 HDMITX_VIC_720x480p_240_4_3 = 56, 319 HDMITX_VIC_720x480p_240_16_9 = 57, 320 HDMITX_VIC_720x480i_240_4_3 = 58, 321 HDMITX_VIC_720x480i_240_16_9 = 59, 322 HDMITX_VIC_1280x720p_24_16_9 = 60, 323 HDMITX_VIC_1280x720p_25_16_9 = 61, 324 HDMITX_VIC_1280x720p_30_16_9 = 62, 325 HDMITX_VIC_1920x1080p_120_16_9 = 63, 326 HDMITX_VIC_1920x1080p_100_16_9 = 64, 327 HDMITX_VIC_3840x2160p_24_16_9 = 93, 328 HDMITX_VIC_3840x2160p_25_16_9 = 94, 329 HDMITX_VIC_3840x2160p_30_16_9 = 95, 330 HDMITX_VIC_3840x2160p_50_16_9 = 96, 331 HDMITX_VIC_3840x2160p_60_16_9 = 97, 332 HDMITX_VIC_4096x2160p_24_256_135 = 98, 333 HDMITX_VIC_4096x2160p_25_256_135 = 99, 334 HDMITX_VIC_4096x2160p_30_256_135 = 100, 335 HDMITX_VIC_4096x2160p_50_256_135 = 101, 336 HDMITX_VIC_4096x2160p_60_256_135 = 102, 337 HDMITX_VIC_3840x2160p_24_64_27 = 103, 338 HDMITX_VIC_3840x2160p_25_64_27 = 104, 339 HDMITX_VIC_3840x2160p_30_64_27 = 105, 340 HDMITX_VIC_3840x2160p_50_64_27 = 106, 341 HDMITX_VIC_3840x2160p_60_64_27 = 107, 342 } HDMITX_AVI_VIC; 343 344 typedef enum 345 { 346 HDMITX_VIDEO_AR_Reserved = 0, 347 HDMITX_VIDEO_AR_4_3 = 1, 348 HDMITX_VIDEO_AR_16_9 = 2, 349 } HDMITX_VIDEO_ASPECT_RATIO; 350 351 typedef enum 352 { 353 HDMITX_VIDEO_SI_NoData = 0, 354 HDMITX_VIDEO_SI_Overscanned = 1, 355 HDMITX_VIDEO_SI_Underscanned = 2, 356 HDMITX_VIDEO_SI_Reserved = 3, 357 } HDMITX_VIDEO_SCAN_INFO; 358 359 typedef enum 360 { 361 HDMITX_VIDEO_AFD_SameAsPictureAR = 8, // 1000 362 HDMITX_VIDEO_AFD_4_3_Center = 9, // 1001 363 HDMITX_VIDEO_AFD_16_9_Center = 10, // 1010 364 HDMITX_VIDEO_AFD_14_9_Center = 11, // 1011 365 HDMITx_VIDEO_AFD_Others = 15, // 0000~ 0111, 1100 ~ 1111 366 } HDMITX_VIDEO_AFD_RATIO; 367 368 369 typedef enum 370 { 371 HDMITX_VIDEO_VS_No_Addition = 0, // 000 372 HDMITX_VIDEO_VS_4k_2k = 1, // 001 373 HDMITX_VIDEO_VS_3D = 2, // 010 374 HDMITx_VIDEO_VS_Reserved = 7, // 011~ 111 375 } HDMITX_VIDEO_VS_FORMAT; 376 377 378 typedef enum 379 { 380 HDMITX_VIDEO_3D_FramePacking = 0, // 0000 381 HDMITX_VIDEO_3D_FieldAlternative = 1, // 0001 382 HDMITX_VIDEO_3D_LineAlternative = 2, // 0010 383 HDMITX_VIDEO_3D_SidebySide_FULL = 3, // 0011 384 HDMITX_VIDEO_3D_L_Dep = 4, // 0100 385 HDMITX_VIDEO_3D_L_Dep_Graphic_Dep= 5, // 0101 386 HDMITX_VIDEO_3D_TopandBottom = 6, // 0110 387 HDMITX_VIDEO_3D_SidebySide_Half = 8, // 1000 388 HDMITx_VIDEO_3D_Not_in_Use = 15, // 1111 389 } HDMITX_VIDEO_3D_STRUCTURE; 390 391 typedef enum 392 { 393 HDMITX_EDID_3D_FramePacking = 1, // 3D_STRUCTURE_ALL_0 394 HDMITX_EDID_3D_FieldAlternative = 2, // 3D_STRUCTURE_ALL_1 395 HDMITX_EDID_3D_LineAlternative = 4, // 3D_STRUCTURE_ALL_2 396 HDMITX_EDID_3D_SidebySide_FULL = 8, // 3D_STRUCTURE_ALL_3 397 HDMITX_EDID_3D_L_Dep = 16, // 3D_STRUCTURE_ALL_4 398 HDMITX_EDID_3D_L_Dep_Graphic_Dep = 32, // 3D_STRUCTURE_ALL_5 399 HDMITX_EDID_3D_TopandBottom = 64, // 3D_STRUCTURE_ALL_6 400 HDMITX_EDID_3D_SidebySide_Half_horizontal = 256, // 3D_STRUCTURE_ALL_8 401 HDMITX_EDID_3D_SidebySide_Half_quincunx = 32768, // 3D_STRUCTURE_ALL_15 402 } HDMITX_EDID_3D_STRUCTURE_ALL; 403 404 405 typedef enum 406 { 407 HDMITx_VIDEO_4k2k_Reserved = 0, // 0x00 408 HDMITX_VIDEO_4k2k_30Hz = 1, // 0x01 409 HDMITX_VIDEO_4k2k_25Hz = 2, // 0x02 410 HDMITX_VIDEO_4k2k_24Hz = 3, // 0x03 411 HDMITx_VIDEO_4k2k_24Hz_SMPTE = 4, // 0x04 412 } HDMITX_VIDEO_4k2k_VIC; 413 414 415 typedef enum 416 { 417 HDMITX_AUDIO_FREQ_NO_SIG = 0, 418 HDMITX_AUDIO_32K = 1, 419 HDMITX_AUDIO_44K = 2, 420 HDMITX_AUDIO_48K = 3, 421 HDMITX_AUDIO_88K = 4, 422 HDMITX_AUDIO_96K = 5, 423 HDMITX_AUDIO_176K = 6, 424 HDMITX_AUDIO_192K = 7, 425 HDMITX_AUDIO_FREQ_MAX_NUM = 8, 426 } HDMITX_AUDIO_FREQUENCY; 427 428 typedef enum 429 { 430 HDMITX_AUDIO_FORMAT_PCM = 0, 431 HDMITX_AUDIO_FORMAT_DSD = 1, 432 HDMITX_AUDIO_FORMAT_HBR = 2, 433 HDMITX_AUDIO_FORMAT_NA = 3, 434 } HDMITX_AUDIO_SOURCE_FORMAT; 435 436 typedef enum 437 { 438 HDMITX_AUDIO_CH_2 = 2, // 2 channels 439 HDMITX_AUDIO_CH_8 = 8, // 8 channels 440 } HDMITX_AUDIO_CHANNEL_COUNT; 441 442 typedef enum 443 { 444 HDMITX_AUDIO_PCM = 0, // PCM 445 HDMITX_AUDIO_NONPCM = 1, // non-PCM 446 } HDMITX_AUDIO_CODING_TYPE; 447 448 //HDMITx Capability 449 typedef enum 450 { 451 E_HDMITX_CAP_SUPPORT_DVI =0, ///< return true if H/W support scaler device1 452 }EN_HDMITX_CAPS; 453 454 typedef struct 455 { 456 MS_U8 Reserved; 457 }HDMI_TX_INFO; 458 459 typedef struct 460 { 461 MS_BOOL bIsInitialized; 462 MS_BOOL bIsRunning; 463 }HDMI_TX_Status; 464 465 typedef struct 466 { 467 // HDMI Tx Current, Pre-emphasis and Double termination 468 MS_U8 tm_txcurrent; // TX current control(U4: 0x11302B[13:12], K1: 0x11302B[13:11]) 469 MS_U8 tm_pren2; // pre-emphasis mode control, 0x11302D[5] 470 MS_U8 tm_precon; // TM_PRECON, 0x11302E[7:4] 471 MS_U8 tm_pren; // pre-emphasis enable, 0x11302E[11:8] 472 MS_U8 tm_tenpre; // Double termination pre-emphasis enable, 0x11302F[3:0] 473 MS_U8 tm_ten; // Double termination enable, 0x11302F[7:4] 474 } HDMITX_ANALOG_TUNING; 475 476 typedef enum 477 { 478 E_HDCP_DISABLE = 0, // HDCP disable 479 E_HDCP_FAIL = 1, // HDCP fail 480 E_HDCP_PASS = 2, // HDCP pass 481 } HDMITX_HDCP_STATUS; 482 483 typedef enum 484 { 485 CHECK_NOT_READY = 0, 486 CHECK_REVOKED = 1, 487 CHECK_NOT_REVOKED = 2, 488 }HDMITX_REVOCATION_STATE; 489 490 typedef enum 491 { 492 HDMITX_INT_HDCP_DISABLE = 0, // HDCP disable 493 HDMITX_INT_HDCP_FAIL = 1, // HDCP fail 494 HDMITX_INT_HDCP_PASS = 2, // HDCP pass 495 HDMITX_INT_HDCP_PROCESS = 3, // HDCP processing 496 } HDMITX_INT_HDCP_STATUS; 497 498 typedef enum 499 { 500 E_UNHDCPRX_NORMAL_OUTPUT = 0, // still display normally 501 E_UNHDCPRX_HDCP_ENCRYPTION = 1, // HDCP encryption to show snow screen 502 E_UNHDCPRX_BLUE_SCREEN = 2, // blue screen 503 } HDMITX_UNHDCPRX_CONTROL; 504 505 typedef enum 506 { 507 E_HDCPRXFail_NORMAL_OUTPUT = 0, // still display normally 508 E_HDCPRXFail_HDCP_ENCRYPTION = 1, // HDCP encryption to show snow screen 509 E_HDCPRXFail_BLUE_SCREEN = 2, // blue screen 510 } HDMITX_HDCPRXFail_CONTROL; 511 512 513 typedef enum 514 { 515 HDMITX_INPUT_LESS_60MHZ =0, 516 HDMITX_INPUT_60_to_160MHZ =1, 517 HDMITX_INPUT_OVER_160MHZ =2, 518 } HDMITX_INPUT_FREQ; 519 //------------------------------------------------------------------------------------------------- 520 // Function and Variable 521 //------------------------------------------------------------------------------------------------- 522 523 524 //*********************// 525 // DVI / HDMI // 526 //*********************// 527 528 MS_BOOL MApi_HDMITx_Init(void); 529 530 // MS_BOOL MApi_HDMITx_Exit(void); 531 532 533 // HDMI Tx module On/Off 534 /* 535 Before turn on HDMI TX module, video and audio source should be prepared ready and set the following APIs first. 536 { 537 ... 538 MApi_HDMITx_TurnOnOff(TRUE); 539 // MApi_HDMITx_SetRBChannelSwap(TRUE); 540 MApi_HDMITx_SetColorFormat(HDMITX_VIDEO_COLOR_YUV444, HDMITX_VIDEO_COLOR_RGB444); 541 MApi_HDMITx_SetVideoOnOff(TRUE); 542 MApi_HDMITx_SetHDMITxMode_CD(HDMITX_HDMI, HDMITX_VIDEO_CD_24Bits); 543 MApi_HDMITx_SetVideoOutputTiming(HDMITX_RES_1920x1080p_60Hz); 544 MApi_HDMITx_Exhibit(); 545 ... 546 } 547 548 */ 549 void MApi_HDMITx_TurnOnOff(MS_BOOL state); 550 551 // HDMI packet enable or not 552 // void MApi_HDMITx_EnablePacketGen(MS_BOOL bflag); 553 554 // HDMI Tx output is DVI / HDMI mode 555 void MApi_HDMITx_SetHDMITxMode(HDMITX_OUTPUT_MODE mode); 556 557 // HDMI Tx output is DVI / HDMI mode and color depth 558 void MApi_HDMITx_SetHDMITxMode_CD(HDMITX_OUTPUT_MODE mode, HDMITX_VIDEO_COLORDEPTH_VAL val); 559 560 // HDMI Tx TMDS signal On/Off 561 void MApi_HDMITx_SetTMDSOnOff(MS_BOOL state); 562 563 // HDMI Tx TMDS control disable/enable 564 void MApi_HDMITx_DisableTMDSCtrl(MS_BOOL bFlag); 565 566 // HDMI Tx R/B channel swap 567 // void MApi_HDMITx_SetRBChannelSwap(MS_BOOL state); 568 569 // HDMI Tx Exhibit funtcion 570 void MApi_HDMITx_Exhibit(void); 571 572 // HDMI Tx force output mode 573 void MApi_HDMITx_ForceHDMIOutputMode(MS_BOOL bflag, HDMITX_OUTPUT_MODE output_mode); 574 575 // HDMI Tx force output color format 576 MS_BOOL MApi_HDMITx_ForceHDMIOutputColorFormat(MS_BOOL bflag, HDMITX_VIDEO_COLOR_FORMAT output_color); 577 578 // Get the connected HDMI Rx status 579 MS_BOOL MApi_HDMITx_GetRxStatus(void); 580 581 // Get Rx's deep color definition from EDID 582 MS_BOOL MApi_HDMITx_GetRxDCInfoFromEDID(HDMITX_VIDEO_COLORDEPTH_VAL *val); 583 584 // Get Rx's support video format from EDID 585 MS_BOOL MApi_HDMITx_GetRxVideoFormatFromEDID(MS_U8 *pu8Buffer, MS_U8 u8BufSize); 586 587 // Get Rx's data block length 588 // MS_BOOL MApi_HDMITx_GetDataBlockLengthFromEDID(MS_U8 *pu8Length, MS_U8 u8TagCode); 589 590 // Get Rx's support audio format from EDID 591 MS_BOOL MApi_HDMITx_GetRxAudioFormatFromEDID(MS_U8 *pu8Buffer, MS_U8 u8BufSize); 592 593 // Get Rx's support mode from EDID 594 MS_BOOL MApi_HDMITx_EDID_HDMISupport(MS_BOOL *HDMI_Support); 595 596 // Get Rx's ID Manufacturer Name from EDID 597 // MS_BOOL MApi_HDMITx_GetRxIDManufacturerName(MS_U8 *pu8Buffer); 598 599 600 // MS_BOOL MApi_HDMITx_GetBksv(MS_U8 *pdata); 601 602 // MS_BOOL MApi_HDMITx_GetAksv(MS_U8 *pdata); 603 604 605 // Get Rx's EDID data 606 MS_BOOL MApi_HDMITx_GetEDIDData(MS_U8 *pu8Buffer, MS_BOOL BlockIdx); 607 608 // Get Rx's supported 3D structures of specific timing from EDID 609 MS_BOOL MApi_HDMITx_GetRx3DStructureFromEDID(HDMITX_VIDEO_TIMING timing, HDMITX_EDID_3D_STRUCTURE_ALL *p3DStructure); 610 611 // This function clear settings of user defined packet 612 // void MApi_HDMITx_PKT_User_Define_Clear(void); 613 614 // This function set user defined hdmi packet 615 void MApi_HDMITx_PKT_User_Define(HDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag, 616 HDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt); 617 618 // This function let user define hdmi packet content 619 // MS_BOOL MApi_HDMITx_PKT_Content_Define(HDMITX_PACKET_TYPE packet_type, MS_U8 *data, MS_U8 length); 620 621 622 //*********************// 623 // Video // 624 //*********************// 625 626 // HDMI Tx video output On/Off 627 void MApi_HDMITx_SetVideoOnOff(MS_BOOL state); 628 // HDMI Tx video color format 629 void MApi_HDMITx_SetColorFormat(HDMITX_VIDEO_COLOR_FORMAT in_color, HDMITX_VIDEO_COLOR_FORMAT out_color); 630 // HDMI Tx video output timing 631 void MApi_HDMITx_SetVideoOutputTiming(HDMITX_VIDEO_TIMING mode); 632 // HDMI Tx video output aspect ratio 633 void MApi_HDMITx_SetVideoOutputAsepctRatio(HDMITX_VIDEO_ASPECT_RATIO out_ar); 634 // HDMI Tx video output Overscan and AFD ratio 635 // void MApi_HDMITx_SetVideoOutputOverscan_AFD(MS_BOOL bflag, HDMITX_VIDEO_SCAN_INFO out_scaninfo, MS_U8 out_afd); 636 void MApi_HDMITx_SetVideoOutputOverscan_AFD_II(MS_BOOL bflag, HDMITX_VIDEO_SCAN_INFO out_scaninfo, MS_U8 out_afd, MS_U8 A0 ); 637 void MApi_HDMITx_Set_VS_InfoFrame(HDMITX_VIDEO_VS_FORMAT vs_format, HDMITX_VIDEO_3D_STRUCTURE vs_3d, HDMITX_VIDEO_4k2k_VIC vs_vic); 638 639 //*********************// 640 // Audio // 641 //*********************// 642 643 // HDMI Tx audio output On/Off 644 void MApi_HDMITx_SetAudioOnOff(MS_BOOL state); 645 // HDMI Tx audio output sampling frequency 646 // For Uranus 647 // void MApi_HDMITx_SetAudioFrequency(HDMITX_AUDIO_FREQUENCY freq); 648 // HDMI Tx Module audio output: sampling frequency, channel count and coding type 649 // For Oberon 650 void MApi_HDMITx_SetAudioConfiguration(HDMITX_AUDIO_FREQUENCY freq, HDMITX_AUDIO_CHANNEL_COUNT ch, HDMITX_AUDIO_CODING_TYPE type); 651 // HDMI Tx get audio CTS value. 652 // MS_U32 MApi_HDMITx_GetAudioCTS(void); 653 // HDMI Tx mute/unmute audio FIFO. 654 void MApi_HDMITx_MuteAudioFIFO(MS_BOOL bflag); 655 // Set HDMI audio source format 656 void MApi_HDMITx_SetAudioSourceFormat(HDMITX_AUDIO_SOURCE_FORMAT fmt); 657 658 //void MApi_HDMITx_SetAudioFrequencyFromMad(void); 659 //*********************// 660 // HDCP // 661 //*********************// 662 663 // HDMI Tx Get HDCP key (set internal/external HDCP key) 664 // @param[in] useinternalkey: TRUE -> from internal, FALSE -> from external, like SPI flash 665 void MApi_HDMITx_GetHdcpKey(MS_BOOL useinternalkey, MS_U8 *data); 666 // HDMI Tx HDCP encryption On/Off 667 void MApi_HDMITx_SetHDCPOnOff(MS_BOOL state); 668 // This routine set HDMI Tx AVMUTE 669 void MApi_HDMITx_SetAVMUTE(MS_BOOL bflag); 670 // This routine get HDMI Tx AVMUTE status 671 MS_BOOL MApi_HDMITx_GetAVMUTEStatus(void); 672 // HDMI Tx HDCP status 673 HDMITX_HDCP_STATUS MApi_HDMITx_GetHDCPStatus(void); 674 // HDCP start Authentication 675 void MApi_HDMITx_HDCP_StartAuth(MS_BOOL bFlag); 676 // HDMI Tx Internal HDCP status 677 // HDMITX_INT_HDCP_STATUS MApi_HDMITx_GetINTHDCPStatus(void); 678 // HDMI Tx HDCP pre-status 679 // HDMITX_INT_HDCP_STATUS MApi_HDMITx_GetHDCP_PreStatus(void); 680 // HDMI video output or blank or encryption while connected with unsupport HDCP Rx 681 void MApi_HDMITx_UnHDCPRxControl(HDMITX_UNHDCPRX_CONTROL state); 682 // HDMI video output or blank or encryption while HDCP authentication fail 683 void MApi_HDMITx_HDCPRxFailControl(HDMITX_HDCPRXFail_CONTROL state); 684 // This routine to set the time interval from sent aksv to R0. 685 // MS_BOOL MApi_HDMITx_SetAksv2R0Interval(MS_U32 u32Interval); 686 // This API to get active Rx status. 687 // MS_BOOL MApi_HDMITx_IsHDCPRxValid(void); 688 // This API return revocation check state 689 // HDMITX_REVOCATION_STATE MApi_HDMITx_HDCP_RevocationKey_Check(void); 690 // This API will update revocation list (note : size 1 = 5 bytes !!!) 691 // void MApi_HDMITx_HDCP_RevocationKey_List(MS_U8 *data, MS_U16 size); 692 693 694 // Debug 695 // MS_BOOL MApi_HDMITx_GetLibVer(const MSIF_Version **ppVersion); 696 697 // MS_BOOL MApi_HDMITx_GetInfo(HDMI_TX_INFO *pInfo); 698 699 // MS_BOOL MApi_HDMITx_GetStatus(HDMI_TX_Status *pStatus); 700 701 // MS_BOOL MApi_HDMITx_HDCP_IsSRMSignatureValid(MS_U8 *data, MS_U32 size); 702 703 /** 704 * @brief set debug mask 705 * @param[in] u16DbgSwitch DEBUG MASK, 706 * 0x01: Debug HDMITX, 0x02: Debug HDCP 707 */ 708 MS_BOOL MApi_HDMITx_SetDbgLevel(MS_U16 u16DbgSwitch); 709 710 void MApi_HDMITx_SetHPDGpioPin(MS_U8 u8pin); 711 712 // Adjust HDMITx analog setting for HDMI test or compliant issue 713 void MApi_HDMITx_AnalogTuning(HDMITX_ANALOG_TUNING *pInfo); 714 715 void MApi_HDMITx_DisableRegWrite(MS_BOOL bFlag); 716 717 //*********************// 718 // CEC // 719 //*********************// 720 721 /// This routine get EDID physical address 722 void MApi_HDMITx_GetEDIDPhyAdr(MS_U8 *pdata); 723 // This routine turn on/off HDMI Tx CEC 724 void MApi_HDMITx_SetCECOnOff(MS_BOOL bflag); 725 // This routine get HDMI Tx CEC On/Off status 726 // MS_BOOL MApi_HDMITx_GetCECStatus(void); 727 // This routine force get EDID from reciver 728 MS_BOOL MApi_HDMITx_EdidChecking(void); 729 730 //*********************// 731 // RxBypassMode // 732 //*********************// 733 // MS_BOOL MApi_HDMITx_RxBypass_Mode(HDMITX_INPUT_FREQ freq, MS_BOOL bflag); 734 735 // MS_BOOL MApi_HDMITx_Disable_RxBypass(void); 736 737 738 //*************************// 739 // CHIP Capaibility // 740 //*************************// 741 // MS_BOOL MApi_HDMITx_GetChipCaps(EN_HDMITX_CAPS eCapType, MS_U32* pRet, MS_U32 ret_size); 742 743 // MS_U32 MApi_HDMITx_SetPowerState(EN_POWER_MODE u16PowerState); 744 745 #ifdef __cplusplus 746 } 747 #endif 748 749 750 #endif // _API_HDMITX_H_ 751 752