1*53ee8cc1Swenshuai.xi //<MStar Software> 2*53ee8cc1Swenshuai.xi //****************************************************************************** 3*53ee8cc1Swenshuai.xi // MStar Software 4*53ee8cc1Swenshuai.xi // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5*53ee8cc1Swenshuai.xi // All software, firmware and related documentation herein ("MStar Software") are 6*53ee8cc1Swenshuai.xi // intellectual property of MStar Semiconductor, Inc. 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MStar hereby reserves the 91*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom. 92*53ee8cc1Swenshuai.xi // 93*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 94*53ee8cc1Swenshuai.xi 95*53ee8cc1Swenshuai.xi /////////////////////////////////////////////////////////////////////////////////////////////////// 96*53ee8cc1Swenshuai.xi /// 97*53ee8cc1Swenshuai.xi /// @file drvMFC.h 98*53ee8cc1Swenshuai.xi /// @brief 99*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc. 100*53ee8cc1Swenshuai.xi /////////////////////////////////////////////////////////////////////////////////////////////////// 101*53ee8cc1Swenshuai.xi 102*53ee8cc1Swenshuai.xi #ifndef _DRV_MFC_H_ 103*53ee8cc1Swenshuai.xi #define _DRV_MFC_H_ 104*53ee8cc1Swenshuai.xi 105*53ee8cc1Swenshuai.xi 106*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 107*53ee8cc1Swenshuai.xi // Include List 108*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 109*53ee8cc1Swenshuai.xi 110*53ee8cc1Swenshuai.xi #ifdef __cplusplus 111*53ee8cc1Swenshuai.xi extern "C" 112*53ee8cc1Swenshuai.xi { 113*53ee8cc1Swenshuai.xi #endif 114*53ee8cc1Swenshuai.xi 115*53ee8cc1Swenshuai.xi #include "MsTypes.h" 116*53ee8cc1Swenshuai.xi 117*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 118*53ee8cc1Swenshuai.xi // Constant & Macro Definition 119*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 120*53ee8cc1Swenshuai.xi /// Version string. 121*53ee8cc1Swenshuai.xi #define MFC_DRV_VERSION /* Character String for DRV/API version */ \ 122*53ee8cc1Swenshuai.xi MSIF_TAG, /* 'MSIF' */ \ 123*53ee8cc1Swenshuai.xi MSIF_CLASS, /* '00' */ \ 124*53ee8cc1Swenshuai.xi MSIF_CUS, /* 0x0000 */ \ 125*53ee8cc1Swenshuai.xi MSIF_MOD, /* 0x0000 */ \ 126*53ee8cc1Swenshuai.xi MSIF_CHIP, \ 127*53ee8cc1Swenshuai.xi MSIF_CPU, \ 128*53ee8cc1Swenshuai.xi {'M','F','V','_'}, /* IP__ */ \ 129*53ee8cc1Swenshuai.xi {'0','1'}, /* 0.0 ~ Z.Z */ \ 130*53ee8cc1Swenshuai.xi {'0','1'}, /* 00 ~ 99 */ \ 131*53ee8cc1Swenshuai.xi {'0','0','1','4','0','9','4','2'}, /* CL# */ \ 132*53ee8cc1Swenshuai.xi MSIF_OS 133*53ee8cc1Swenshuai.xi 134*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 135*53ee8cc1Swenshuai.xi // Type & Structure Declaration 136*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 137*53ee8cc1Swenshuai.xi /// MFC's capability 138*53ee8cc1Swenshuai.xi 139*53ee8cc1Swenshuai.xi #define U8 MS_U8 140*53ee8cc1Swenshuai.xi #define U16 MS_U16 141*53ee8cc1Swenshuai.xi #define U32 MS_U32 142*53ee8cc1Swenshuai.xi #define S8 MS_S8 143*53ee8cc1Swenshuai.xi #define S16 MS_S16 144*53ee8cc1Swenshuai.xi #define S32 MS_S32 145*53ee8cc1Swenshuai.xi 146*53ee8cc1Swenshuai.xi typedef struct MST_MFC_DRV_SYS_INFO_s 147*53ee8cc1Swenshuai.xi { 148*53ee8cc1Swenshuai.xi //titania to URSA 149*53ee8cc1Swenshuai.xi U8 u8LVDSChannel; //Single, Dual 150*53ee8cc1Swenshuai.xi U8 u8LVDSBitNum; //8bits, 10 bits 151*53ee8cc1Swenshuai.xi U8 u8LVDSTiMode; //Thin/Ti mode scaler 40-bit2 152*53ee8cc1Swenshuai.xi U8 u8LVDSSwapMsbLsb; //ursa scaler 153*53ee8cc1Swenshuai.xi U8 u8LVDSSwap_P_N; //ursa scaler 154*53ee8cc1Swenshuai.xi U8 u8LVDSSwapOddEven; //ursa scaler 155*53ee8cc1Swenshuai.xi 156*53ee8cc1Swenshuai.xi //URSA to Panel info 157*53ee8cc1Swenshuai.xi U8 u8PanelType; //TTL, Mini_LVDS, LVDS 158*53ee8cc1Swenshuai.xi U8 u8PanelBitNum; //Panel bit number 159*53ee8cc1Swenshuai.xi U8 u8PanelChannel; //Single, Dual, Quad, Quad_LR 160*53ee8cc1Swenshuai.xi U8 u8PanelDither; 161*53ee8cc1Swenshuai.xi U8 u8PanelLVDSTiMode; //Panel TI/Thin mode 162*53ee8cc1Swenshuai.xi U8 u8PanelLVDSSwapPol; //Panel LVDS polarity swap 163*53ee8cc1Swenshuai.xi U8 u8PanelLVDSSwapCH; //LVDS chenel swap ABCD 164*53ee8cc1Swenshuai.xi U8 u8PanelLVDSSwapPair; //Panel LVDS pair swap 165*53ee8cc1Swenshuai.xi U8 u8PanelLVDSShiftPair; 166*53ee8cc1Swenshuai.xi U8 u8PanelBlankCPVC; //Panel Mini LVDS use 167*53ee8cc1Swenshuai.xi U8 u8PanelBlankOEC; //Panel Mini LVDS use 168*53ee8cc1Swenshuai.xi U8 u8PanelBlankTPC; //Panel Mini LVDS use 169*53ee8cc1Swenshuai.xi U8 u8PanelBlankSTHC; //Panel Mini LVDS use 170*53ee8cc1Swenshuai.xi 171*53ee8cc1Swenshuai.xi U16 u16HStart; //ursa scaler 172*53ee8cc1Swenshuai.xi U16 u16VStart; //ursa scaler 173*53ee8cc1Swenshuai.xi U16 u16Width; //ursa scaler 174*53ee8cc1Swenshuai.xi U16 u16Height; //ursa scaler 175*53ee8cc1Swenshuai.xi U16 u16HTotal; //ursa scaler 176*53ee8cc1Swenshuai.xi U16 u16VTotal; //ursa scaler 177*53ee8cc1Swenshuai.xi U8 u8PanelVfreq; //Panel frame rate 60Hz, 120Hz, 240Hz 178*53ee8cc1Swenshuai.xi U8 u8PanelIncVtotalFor50Hz; //Change Vtotal for DCLK 179*53ee8cc1Swenshuai.xi U8 u8PanelCSC; //LVDS CSC enable/disable 180*53ee8cc1Swenshuai.xi U16 u16MFCMemoryClk; //MFC memory clock MHz 181*53ee8cc1Swenshuai.xi U16 u16MFCMemoryType; //MFC memory type 182*53ee8cc1Swenshuai.xi U8 u8PanelGAMMA; 183*53ee8cc1Swenshuai.xi U8 u8ODMode; 184*53ee8cc1Swenshuai.xi U8 u8IPMode; 185*53ee8cc1Swenshuai.xi U8 u8Preset; 186*53ee8cc1Swenshuai.xi U8 u8MirrorMode; 187*53ee8cc1Swenshuai.xi U8 u8UseMPIF; 188*53ee8cc1Swenshuai.xi } MST_MFC_DRV_SYS_INFO_t, *PMST_MFC_DRV_SYS_INFO_t; 189*53ee8cc1Swenshuai.xi 190*53ee8cc1Swenshuai.xi void MDrv_URSA_Init(PMST_MFC_DRV_SYS_INFO_t mfcSysInfo, MS_U8 u8IsS7M); 191*53ee8cc1Swenshuai.xi void MDrv_URSA_ControlFrameLockMode(MS_U8 u8type); 192*53ee8cc1Swenshuai.xi void MDrv_URSA_SetSpreadSpectrum(MS_U16 u16KHz, MS_U16 u16Percent, MS_BOOL bEnable, MS_BOOL bMiuLVDS); 193*53ee8cc1Swenshuai.xi void MDrv_URSA_SetVFreq(MS_U16 u16Inputfreq, MS_BOOL bEnableFPLL); 194*53ee8cc1Swenshuai.xi 195*53ee8cc1Swenshuai.xi #ifdef __cplusplus 196*53ee8cc1Swenshuai.xi } 197*53ee8cc1Swenshuai.xi #endif 198*53ee8cc1Swenshuai.xi 199*53ee8cc1Swenshuai.xi #endif 200