1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // (¡§MStar Confidential Information¡¨) by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file apiHDMITx.h 98 /// @brief HDMITx Interface 99 /// @author MStar Semiconductor Inc. 100 /// 101 /// CL351033++: 102 /// Add CEC function for STB 103 /// CL310477++: 104 /// Open analog setting for the different board condition 105 /// CL309397++: 106 /// Modify apiHDMITx prototype for NDS 107 /// CL308729++: 108 /// Fix AVMUTE problem while HDCP is on 109 /// CL299817++: 110 /// i. Add I2C timeout mechanism in EDID and HDCP 111 /// ii. Add SET_AVMUTE API to avoid transition garbage noise while timing changed ]]> 112 /// CL288415++: 113 /// Add SRM DSA Signature Checking function 114 /// CL283331++: 115 /// Fix HDMI v1.3 deep color mode output unstable problem 116 /// CL282607++: 117 /// i. Fix YUV422 / YUV444 bugs 118 /// ii. Add MApi_HDMITx_GetHdcpKey() to get HDCP key from external storage. 119 /// CL276751++: 120 /// Modify HDMI / HDCP state mechine for NDS 121 /// CL275230++: 122 /// i. MApi_HDMITx_GetRxDCInfoFromEDID() to get Rx's deep color information from EDID 123 /// ii. MApi_HDMITx_SetHDMITxMode_CD() to set output mode and deep color setting 124 /// CL266666++: 125 /// Add event report for NDS 126 /// CL263961++: 127 /// Add CEC init and checkbuffer for NDS 128 /// CL260934++: 129 /// Add some customized APIs for NDS 130 /// CL259645++: 131 /// i. Remove EDID header check. If header is wrong, force to DVI output 132 /// ii. Add force output mode "MApi_HDMITx_ForceHDMIOutputMode()" 133 /////////////////////////////////////////////////////////////////////////////////////////////////// 134 135 #ifndef _API_HDMITX_H_ 136 #define _API_HDMITX_H_ 137 138 #include "MsDevice.h" 139 #include "MsTypes.h" 140 #include "MsCommon.h" 141 //#include "halHDMITx.h" 142 //#include "drvHDMITx.h" 143 //#include "regHDMITx.h" 144 145 146 147 #ifdef __cplusplus 148 extern "C" 149 { 150 #endif 151 152 153 //------------------------------------------------------------------------------------------------- 154 // Macro and Define 155 //------------------------------------------------------------------------------------------------- 156 157 158 //------------------------------------------------------------------------------------------------- 159 // Type and Structure 160 //------------------------------------------------------------------------------------------------- 161 #define MSIF_HDMITX_LIB_CODE {'H','D','M','I'} 162 #define MSIF_HDMITX_LIBVER {'0','0'} 163 #define MSIF_HDMITX_BUILDNUM {'2','0'} 164 #define MSIF_HDMITX_CHANGELIST {'0','0','6','7','7','7','7','2'} 165 #define HDMITX_API_VERSION /* Character String for DRV/API version */ \ 166 MSIF_TAG, /* 'MSIF' */ \ 167 MSIF_CLASS, /* '00' */ \ 168 MSIF_CUS, /* 0x0000 */ \ 169 MSIF_MOD, /* 0x0000 */ \ 170 MSIF_CHIP, \ 171 MSIF_CPU, \ 172 MSIF_HDMITX_LIB_CODE, /* IP__ */ \ 173 MSIF_HDMITX_LIBVER, /* 0.0 ~ Z.Z */ \ 174 MSIF_HDMITX_BUILDNUM, /* 00 ~ 99 */ \ 175 MSIF_HDMITX_CHANGELIST, /* CL# */ \ 176 MSIF_OS 177 178 typedef enum 179 { 180 HDMITX_DVI = 0, // DVI without HDCP 181 HDMITX_DVI_HDCP = 1, // DVI with HDCP 182 HDMITX_HDMI = 2, // HDMI without HDCP 183 HDMITX_HDMI_HDCP = 3, // HDMI with HDCP 184 } HDMITX_OUTPUT_MODE; 185 186 typedef enum 187 { 188 HDMITX_SEND_PACKET = 0x00, // send packet 189 HDMITX_CYCLIC_PACKET = 0x04, // cyclic packet by frame count 190 HDMITX_STOP_PACKET = 0x80, // stop packet 191 } HDMITX_PACKET_PROCESS; 192 193 typedef enum 194 { 195 HDMITX_NULL_PACKET = 0x00, 196 HDMITX_ACR_PACKET = 0x01, 197 HDMITX_AS_PACKET = 0x02, 198 HDMITX_GC_PACKET = 0x03, 199 HDMITX_ACP_PACKET = 0x04, 200 HDMITX_ISRC1_PACKET = 0x05, 201 HDMITX_ISRC2_PACKET = 0x06, 202 HDMITX_DSD_PACKET = 0x07, 203 HDMITX_HBR_PACKET = 0x09, 204 HDMITX_GM_PACKET = 0x0A, 205 206 HDMITX_VS_INFOFRAME = 0x81, 207 HDMITX_AVI_INFOFRAME = 0x82, 208 HDMITX_SPD_INFOFRAME = 0x83, 209 HDMITX_AUDIO_INFOFRAME = 0x84, 210 HDMITX_MPEG_INFOFRAME = 0x85, 211 HDMITX_HDR_INFOFRMAE = 0x87, //0x86, 212 } HDMITX_PACKET_TYPE; 213 214 typedef enum 215 { 216 HDMITX_VIDEO_CD_NoID = 0, // DVI mode 217 HDMITX_VIDEO_CD_24Bits = 4, // HDMI 8 bits 218 HDMITX_VIDEO_CD_30Bits = 5, // HDMI 10 bits 219 HDMITX_VIDEO_CD_36Bits = 6, // HDMI 12 bits 220 HDMITX_VIDEO_CD_48Bits = 7, // HDMI 16 bits 221 } HDMITX_VIDEO_COLORDEPTH_VAL; 222 223 typedef enum 224 { 225 HDMITX_VIDEO_COLOR_RGB444 = 0, 226 HDMITX_VIDEO_COLOR_YUV422 = 1, 227 HDMITX_VIDEO_COLOR_YUV444 = 2, 228 HDMITX_VIDEO_COLOR_YUV420 = 3, 229 } HDMITX_VIDEO_COLOR_FORMAT; 230 231 typedef enum 232 { 233 HDMITX_RES_640x480p =0, 234 HDMITX_RES_720x480i = 1, 235 HDMITX_RES_720x576i = 2, 236 HDMITX_RES_720x480p = 3, 237 HDMITX_RES_720x576p = 4, 238 HDMITX_RES_1280x720p_50Hz = 5, 239 HDMITX_RES_1280x720p_60Hz = 6, 240 HDMITX_RES_1920x1080i_50Hz = 7, 241 HDMITX_RES_1920x1080i_60Hz = 8, 242 HDMITX_RES_1920x1080p_24Hz = 9, 243 HDMITX_RES_1920x1080p_25Hz = 10, 244 HDMITX_RES_1920x1080p_30Hz = 11, 245 HDMITX_RES_1920x1080p_50Hz = 12, 246 HDMITX_RES_1920x1080p_60Hz = 13, 247 HDMITX_RES_1920x2205p_24Hz = 14, 248 HDMITX_RES_1280X1470p_50Hz = 15, 249 HDMITX_RES_1280X1470p_60Hz = 16, 250 HDMITX_RES_3840x2160p_24Hz = 17, 251 HDMITX_RES_3840x2160p_25Hz = 18, 252 HDMITX_RES_3840x2160p_30Hz = 19, 253 HDMITX_RES_3840x2160p_50Hz = 20, 254 HDMITX_RES_3840x2160p_60Hz = 21, 255 HDMITX_RES_4096x2160p_24Hz = 22, 256 HDMITX_RES_4096x2160p_25Hz = 23, 257 HDMITX_RES_4096x2160p_30Hz = 24, 258 HDMITX_RES_4096x2160p_50Hz = 25, 259 HDMITX_RES_4096x2160p_60Hz = 26, 260 HDMITX_RES_1600x1200p_60Hz = 27, 261 HDMITX_RES_1440x900p_60Hz = 28, 262 HDMITX_RES_1280x1024p_60Hz = 29, 263 HDMITX_RES_1024x768p_60Hz = 30, 264 HDMITX_RES_MAX, 265 } HDMITX_VIDEO_TIMING; 266 267 typedef enum 268 { 269 HDMITX_VIC_NOT_AVAILABLE = 0, 270 HDMITX_VIC_640x480p_60_4_3 = 1, 271 HDMITX_VIC_720x480p_60_4_3 = 2, 272 HDMITX_VIC_720x480p_60_16_9 = 3, 273 HDMITX_VIC_1280x720p_60_16_9 = 4, 274 HDMITX_VIC_1920x1080i_60_16_9 = 5, 275 HDMITX_VIC_720x480i_60_4_3 = 6, 276 HDMITX_VIC_720x480i_60_16_9 = 7, 277 HDMITX_VIC_720x240p_60_4_3 = 8, 278 HDMITX_VIC_720x240p_60_16_9 = 9, 279 HDMITX_VIC_2880x480i_60_4_3 = 10, 280 HDMITX_VIC_2880x480i_60_16_9 = 11, 281 HDMITX_VIC_2880x240p_60_4_3 = 12, 282 HDMITX_VIC_2880x240p_60_16_9 = 13, 283 HDMITX_VIC_1440x480p_60_4_3 = 14, 284 HDMITX_VIC_1440x480p_60_16_9 = 15, 285 HDMITX_VIC_1920x1080p_60_16_9 = 16, 286 HDMITX_VIC_720x576p_50_4_3 = 17, 287 HDMITX_VIC_720x576p_50_16_9 = 18, 288 HDMITX_VIC_1280x720p_50_16_9 = 19, 289 HDMITX_VIC_1920x1080i_50_16_9 = 20, 290 HDMITX_VIC_720x576i_50_4_3 = 21, 291 HDMITX_VIC_720x576i_50_16_9 = 22, 292 HDMITX_VIC_720x288p_50_4_3 = 23, 293 HDMITX_VIC_720x288p_50_16_9 = 24, 294 HDMITX_VIC_2880x576i_50_4_3 = 25, 295 HDMITX_VIC_2880x576i_50_16_9 = 26, 296 HDMITX_VIC_2880x288p_50_4_3 = 27, 297 HDMITX_VIC_2880x288p_50_16_9 = 28, 298 HDMITX_VIC_1440x576p_50_4_3 = 29, 299 HDMITX_VIC_1440x576p_50_16_9 = 30, 300 HDMITX_VIC_1920x1080p_50_16_9 = 31, 301 HDMITX_VIC_1920x1080p_24_16_9 = 32, 302 HDMITX_VIC_1920x1080p_25_16_9 = 33, 303 HDMITX_VIC_1920x1080p_30_16_9 = 34, 304 HDMITX_VIC_2880x480p_60_4_3 = 35, 305 HDMITX_VIC_2880x480p_60_16_9 = 36, 306 HDMITX_VIC_2880x576p_50_4_3 = 37, 307 HDMITX_VIC_2880x576p_50_16_9 = 38, 308 HDMITX_VIC_1920x1080i_50_16_9_1250_total = 39, 309 HDMITX_VIC_1920x1080i_100_16_9 = 40, 310 HDMITX_VIC_1280x720p_100_16_9 = 41, 311 HDMITX_VIC_720x576p_100_4_3 = 42, 312 HDMITX_VIC_720x576p_100_16_9 = 43, 313 HDMITX_VIC_720x576i_100_4_3 = 44, 314 HDMITX_VIC_720x576i_100_16_9 = 45, 315 HDMITX_VIC_1920x1080i_120_16_9 = 46, 316 HDMITX_VIC_1280x720p_120_16_9 = 47, 317 HDMITX_VIC_720x480p_120_4_3 = 48, 318 HDMITX_VIC_720x480p_120_16_9 = 49, 319 HDMITX_VIC_720x480i_120_4_3 = 50, 320 HDMITX_VIC_720x480i_120_16_9 = 51, 321 HDMITX_VIC_720x576p_200_4_3 = 52, 322 HDMITX_VIC_720x576p_200_16_9 = 53, 323 HDMITX_VIC_720x576i_200_4_3 = 54, 324 HDMITX_VIC_720x576i_200_16_9 = 55, 325 HDMITX_VIC_720x480p_240_4_3 = 56, 326 HDMITX_VIC_720x480p_240_16_9 = 57, 327 HDMITX_VIC_720x480i_240_4_3 = 58, 328 HDMITX_VIC_720x480i_240_16_9 = 59, 329 HDMITX_VIC_1280x720p_24_16_9 = 60, 330 HDMITX_VIC_1280x720p_25_16_9 = 61, 331 HDMITX_VIC_1280x720p_30_16_9 = 62, 332 HDMITX_VIC_1920x1080p_120_16_9 = 63, 333 HDMITX_VIC_1920x1080p_100_16_9 = 64, 334 //vvv------------------------------------------- HDMI 2.0 :: 21:9 aspect ratio 335 HDMITX_VIC_1280x720p_24_21_9 = 65, 336 HDMITX_VIC_1280x720p_25_21_9 = 66, 337 HDMITX_VIC_1280x720p_30_21_9 = 67, 338 HDMITX_VIC_1280x720p_50_21_9 = 68, 339 HDMITX_VIC_1280x720p_60_21_9 = 69, 340 HDMITX_VIC_1280x720p_100_21_9 = 70, 341 HDMITX_VIC_1280x720p_120_21_9 = 71, 342 HDMITX_VIC_1920x1080p_24_21_9 = 72, 343 HDMITX_VIC_1920x1080p_25_21_9 = 73, 344 HDMITX_VIC_1920x1080p_30_21_9 = 74, 345 HDMITX_VIC_1920x1080p_50_21_9 = 75, 346 HDMITX_VIC_1920x1080p_60_21_9 = 76, 347 HDMITX_VIC_1920x1080p_100_21_9 = 77, 348 HDMITX_VIC_1920x1080p_120_21_9 = 78, 349 HDMITX_VIC_1680x720p_24_21_9 = 79, 350 HDMITX_VIC_1680x720p_25_21_9 = 80, 351 HDMITX_VIC_1680x720p_30_21_9 = 81, 352 HDMITX_VIC_1680x720p_50_21_9 = 82, 353 HDMITX_VIC_1680x720p_60_21_9 = 83, 354 HDMITX_VIC_1680x720p_100_21_9 = 84, 355 HDMITX_VIC_1680x720p_120_21_9 = 85, 356 HDMITX_VIC_2560x1080p_24_21_9 = 86, 357 HDMITX_VIC_2560x1080p_25_21_9 = 87, 358 HDMITX_VIC_2560x1080p_30_21_9 = 88, 359 HDMITX_VIC_2560x1080p_50_21_9 = 89, 360 HDMITX_VIC_2560x1080p_60_21_9 = 90, 361 HDMITX_VIC_2560x1080p_100_21_9 = 91, 362 HDMITX_VIC_2560x1080p_120_21_9 = 92, 363 //^^^------------------------------------------- HDMI 2.0 :: 21:9 aspect ratio 364 HDMITX_VIC_3840x2160p_24_16_9 = 93, 365 HDMITX_VIC_3840x2160p_25_16_9 = 94, 366 HDMITX_VIC_3840x2160p_30_16_9 = 95, 367 HDMITX_VIC_3840x2160p_50_16_9 = 96, 368 HDMITX_VIC_3840x2160p_60_16_9 = 97, 369 HDMITX_VIC_4096x2160p_24_256_135 = 98, 370 HDMITX_VIC_4096x2160p_25_256_135 = 99, 371 HDMITX_VIC_4096x2160p_30_256_135 = 100, 372 HDMITX_VIC_4096x2160p_50_256_135 = 101, 373 HDMITX_VIC_4096x2160p_60_256_135 = 102, 374 //vvv------------------------------------------- HDMI 2.0 :: 21:9 aspect ratio 375 HDMITX_VIC_3840x2160p_24_64_27 = 103, 376 HDMITX_VIC_3840x2160p_25_64_27 = 104, 377 HDMITX_VIC_3840x2160p_30_64_27 = 105, 378 HDMITX_VIC_3840x2160p_50_64_27 = 106, 379 HDMITX_VIC_3840x2160p_60_64_27 = 107, 380 //^^^------------------------------------------- HDMI 2.0 :: 21:9 aspect ratio 381 } HDMITX_AVI_VIC; 382 383 typedef enum 384 { 385 HDMITX_VIDEO_AR_Reserved = 0, 386 HDMITX_VIDEO_AR_4_3 = 1, 387 HDMITX_VIDEO_AR_16_9 = 2, 388 HDMITX_VIDEO_AR_21_9 = 3, 389 } HDMITX_VIDEO_ASPECT_RATIO; 390 391 typedef enum 392 { 393 HDMITX_VIDEO_SI_NoData = 0, 394 HDMITX_VIDEO_SI_Overscanned = 1, 395 HDMITX_VIDEO_SI_Underscanned = 2, 396 HDMITX_VIDEO_SI_Reserved = 3, 397 } HDMITX_VIDEO_SCAN_INFO; 398 399 typedef enum 400 { 401 HDMITX_VIDEO_AFD_SameAsPictureAR = 8, // 1000 402 HDMITX_VIDEO_AFD_4_3_Center = 9, // 1001 403 HDMITX_VIDEO_AFD_16_9_Center = 10, // 1010 404 HDMITX_VIDEO_AFD_14_9_Center = 11, // 1011 405 HDMITx_VIDEO_AFD_Others = 15, // 0000~ 0111, 1100 ~ 1111 406 } HDMITX_VIDEO_AFD_RATIO; 407 408 409 typedef enum 410 { 411 HDMITX_VIDEO_VS_No_Addition = 0, // 000 412 HDMITX_VIDEO_VS_4k_2k = 1, // 001 413 HDMITX_VIDEO_VS_3D = 2, // 010 414 HDMITx_VIDEO_VS_Reserved = 7, // 011~ 111 415 } HDMITX_VIDEO_VS_FORMAT; 416 417 418 typedef enum 419 { 420 HDMITX_VIDEO_3D_FramePacking = 0, // 0000 421 HDMITX_VIDEO_3D_FieldAlternative = 1, // 0001 422 HDMITX_VIDEO_3D_LineAlternative = 2, // 0010 423 HDMITX_VIDEO_3D_SidebySide_FULL = 3, // 0011 424 HDMITX_VIDEO_3D_L_Dep = 4, // 0100 425 HDMITX_VIDEO_3D_L_Dep_Graphic_Dep= 5, // 0101 426 HDMITX_VIDEO_3D_TopandBottom = 6, // 0110 427 HDMITX_VIDEO_3D_SidebySide_Half = 8, // 1000 428 HDMITx_VIDEO_3D_Not_in_Use = 15, // 1111 429 } HDMITX_VIDEO_3D_STRUCTURE; 430 431 typedef enum 432 { 433 HDMITX_EDID_3D_FramePacking = 1, // 3D_STRUCTURE_ALL_0 434 HDMITX_EDID_3D_FieldAlternative = 2, // 3D_STRUCTURE_ALL_1 435 HDMITX_EDID_3D_LineAlternative = 4, // 3D_STRUCTURE_ALL_2 436 HDMITX_EDID_3D_SidebySide_FULL = 8, // 3D_STRUCTURE_ALL_3 437 HDMITX_EDID_3D_L_Dep = 16, // 3D_STRUCTURE_ALL_4 438 HDMITX_EDID_3D_L_Dep_Graphic_Dep = 32, // 3D_STRUCTURE_ALL_5 439 HDMITX_EDID_3D_TopandBottom = 64, // 3D_STRUCTURE_ALL_6 440 HDMITX_EDID_3D_SidebySide_Half_horizontal = 256, // 3D_STRUCTURE_ALL_8 441 HDMITX_EDID_3D_SidebySide_Half_quincunx = 32768, // 3D_STRUCTURE_ALL_15 442 } HDMITX_EDID_3D_STRUCTURE_ALL; 443 444 typedef enum 445 { 446 HDMITX_EDID_Color_RGB_444 = 1, // RGB 4:4:4 447 HDMITX_EDID_Color_YCbCr_444 = 2, // YCbCr 4:4:4 448 HDMITX_EDID_Color_YCbCr_422 = 4, // YCbCr 4:2:2 449 HDMITX_EDID_Color_YCbCr_420 = 8, // YCbCr 4:2:0 450 } HDMITX_EDID_COLOR_FORMAT; 451 452 typedef enum 453 { 454 HDMITx_VIDEO_4k2k_Reserved = 0, // 0x00 455 HDMITX_VIDEO_4k2k_30Hz = 1, // 0x01 456 HDMITX_VIDEO_4k2k_25Hz = 2, // 0x02 457 HDMITX_VIDEO_4k2k_24Hz = 3, // 0x03 458 HDMITx_VIDEO_4k2k_24Hz_SMPTE = 4, // 0x04 459 } HDMITX_VIDEO_4k2k_VIC; 460 461 462 typedef enum 463 { 464 HDMITX_AUDIO_FREQ_NO_SIG = 0, 465 HDMITX_AUDIO_32K = 1, 466 HDMITX_AUDIO_44K = 2, 467 HDMITX_AUDIO_48K = 3, 468 HDMITX_AUDIO_88K = 4, 469 HDMITX_AUDIO_96K = 5, 470 HDMITX_AUDIO_176K = 6, 471 HDMITX_AUDIO_192K = 7, 472 HDMITX_AUDIO_FREQ_MAX_NUM = 8, 473 } HDMITX_AUDIO_FREQUENCY; 474 475 typedef enum 476 { 477 HDMITX_AUDIO_FORMAT_PCM = 0, 478 HDMITX_AUDIO_FORMAT_DSD = 1, 479 HDMITX_AUDIO_FORMAT_HBR = 2, 480 HDMITX_AUDIO_FORMAT_NA = 3, 481 } HDMITX_AUDIO_SOURCE_FORMAT; 482 483 typedef enum 484 { 485 HDMITX_AUDIO_CH_2 = 2, // 2 channels 486 HDMITX_AUDIO_CH_8 = 8, // 8 channels 487 } HDMITX_AUDIO_CHANNEL_COUNT; 488 489 typedef enum 490 { 491 HDMITX_AUDIO_PCM = 0, // PCM 492 HDMITX_AUDIO_NONPCM = 1, // non-PCM 493 } HDMITX_AUDIO_CODING_TYPE; 494 495 typedef enum //C0, C1 field of AVIInfoFrame packet 496 { 497 HDMITX_COLORIMETRY_NO_DATA = 0, 498 HDMITX_COLORIMETRY_SMPTE170M, 499 HDMITX_COLORIMETRY_ITUR709, 500 HDMITX_COLORIMETRY_EXTEND, 501 HDMITX_COLORIMETRY_MAX 502 } HDMITX_AVI_COLORIMETRY; 503 504 typedef enum //EC0~EC2 filed of AVIInfoFrame packet 505 { 506 HDMITX_EXT_COLORIMETRY_XVYCC601 = 0, 507 HDMITX_EXT_COLORIMETRY_XVYCC709 = 1, 508 HDMITX_EXT_COLORIMETRY_SYCC601 = 2, 509 HDMITX_EXT_COLORIMETRY_ADOBEYCC601 = 3, 510 HDMITX_EXT_COLORIMETRY_ADOBERGB = 4, 511 HDMITX_EXT_COLORIMETRY_BT2020CYCC = 5, //mapping to ext. colorimetry format BT2020Y'cC'bcC'rc 512 HDMITX_EXT_COLORIMETRY_BT2020YCC = 6, //mapping to ext. colorimetry format BT2020 RGB or YCbCr 513 HDMITX_EXT_COLORIMETRY_BT2020RGB = 7 //mapping to ext. colorimetry format BT2020 RGB or YCbCr 514 } HDMITX_AVI_EXTENDED_COLORIMETRY; 515 516 typedef enum //YQ1, YQ2 field of AVIInfoFrame packet 517 { 518 HDMITX_YCC_QUANT_LIMIT = 0x00, 519 HDMITX_YCC_QUANT_FULL = 0x01, 520 HDMITX_YCC_QUANT_RESERVED = 0x10 521 } HDMITX_AVI_YCC_QUANT_RANGE; 522 523 //HDMITx Capability 524 typedef enum 525 { 526 E_HDMITX_CAP_SUPPORT_DVI =0, ///< return true if H/W support scaler device1 527 }EN_HDMITX_CAPS; 528 529 typedef struct DLL_PACKED 530 { 531 MS_U8 Reserved; 532 }HDMI_TX_INFO; 533 534 typedef struct DLL_PACKED 535 { 536 MS_BOOL bIsInitialized; 537 MS_BOOL bIsRunning; 538 }HDMI_TX_Status; 539 540 typedef struct DLL_PACKED 541 { 542 // HDMI Tx Current, Pre-emphasis and Double termination 543 MS_U8 tm_txcurrent; // TX current control(U4: 0x11302B[13:12], K1: 0x11302B[13:11]) 544 MS_U8 tm_pren2; // pre-emphasis mode control, 0x11302D[5] 545 MS_U8 tm_precon; // TM_PRECON, 0x11302E[7:4] 546 MS_U8 tm_pren; // pre-emphasis enable, 0x11302E[11:8] 547 MS_U8 tm_tenpre; // Double termination pre-emphasis enable, 0x11302F[3:0] 548 MS_U8 tm_ten; // Double termination enable, 0x11302F[7:4] 549 } HDMITX_ANALOG_TUNING; 550 551 typedef enum 552 { 553 E_HDCP_DISABLE = 0, // HDCP disable 554 E_HDCP_FAIL = 1, // HDCP fail 555 E_HDCP_PASS = 2, // HDCP pass 556 } HDMITX_HDCP_STATUS; 557 558 typedef enum 559 { 560 CHECK_NOT_READY = 0, 561 CHECK_REVOKED = 1, 562 CHECK_NOT_REVOKED = 2, 563 }HDMITX_REVOCATION_STATE; 564 565 typedef enum 566 { 567 HDMITX_INT_HDCP_DISABLE = 0, // HDCP disable 568 HDMITX_INT_HDCP_FAIL = 1, // HDCP fail 569 HDMITX_INT_HDCP_PASS = 2, // HDCP pass 570 HDMITX_INT_HDCP_PROCESS = 3, // HDCP processing 571 } HDMITX_INT_HDCP_STATUS; 572 573 typedef enum 574 { 575 E_UNHDCPRX_NORMAL_OUTPUT = 0, // still display normally 576 E_UNHDCPRX_HDCP_ENCRYPTION = 1, // HDCP encryption to show snow screen 577 E_UNHDCPRX_BLUE_SCREEN = 2, // blue screen 578 } HDMITX_UNHDCPRX_CONTROL; 579 580 typedef enum 581 { 582 E_HDCPRXFail_NORMAL_OUTPUT = 0, // still display normally 583 E_HDCPRXFail_HDCP_ENCRYPTION = 1, // HDCP encryption to show snow screen 584 E_HDCPRXFail_BLUE_SCREEN = 2, // blue screen 585 } HDMITX_HDCPRXFail_CONTROL; 586 587 typedef enum 588 { 589 HDMITX_INPUT_LESS_60MHZ =0, 590 HDMITX_INPUT_60_to_160MHZ =1, 591 HDMITX_INPUT_OVER_160MHZ =2, 592 } HDMITX_INPUT_FREQ; 593 594 typedef enum 595 { 596 HDMITX_HDCP_RESET = 0x01, 597 HDMITX_HDCP_WAITING_ACTIVE_RX = 0x02, 598 HDMITX_HDCP_CHECK_REPEATER_READY = 0x03, 599 HDMITX_HDCP_CHECK_R0 = 0x04, 600 HDMITX_HDCP_AUTH_DONE = 0x05, 601 HDMITX_HDCP_AUTH_FAIL = 0x06, 602 603 // bit[7:6]=00 for checking valid rx 604 HDMITX_HDCP_RX_IS_NOT_VALID = 0x00, // 00 00 605 HDMITX_HDCP_RX_IS_VALID = 0x10, // 00 01 606 HDMITX_HDCP_RX_KEY_FAIL = 0x20, // 00 10 607 HDMITX_HDCP_TX_KEY_FAIL = 0x30, // 00 11 608 HDMITX_HDCP_RX_KEY_REVOKED = 0x0F, // 00 00 11 11 609 610 // bit[7:6]=01 for repeater 611 HDMITX_HDCP_REPEATER_TIMEOUT = 0x40, // 01 00 612 HDMITX_HDCP_REPEATER_READY = 0x50, // 01 01 613 HDMITX_HDCP_REPEATER_NOT_READY = 0x60, // 01 10 614 HDMITX_HDCP_REPEATER_VALID = 0x70, // 01 11 615 616 // bit[7:6]=10 for SHA1 617 HDMITX_HDCP_REPEATER_SHA1_FAIL = 0x80, // 10 00 618 HDMITX_HDCP_REPEATER_SHA1_PASS = 0x90, // 10 01 619 620 // bit[7:6]=11 for Ri 621 HDMITX_HDCP_SYNC_RI_FAIL = 0xC0, // 11 00 622 HDMITX_HDCP_SYNC_RI_PASS = 0xD0 // 11 01 623 }HDMITX_HDCP_AUTH_STATUS; 624 625 typedef enum 626 { 627 HDMITX_CMD_NONE = 0, 628 E_HDMITX_COLOR_AND_RANGE_TRANSFORM, 629 HDMITX_CMD_COLOR_AND_RANGE_TRANSFORM, 630 HDMITX_CMD_SSC_ENABLE, 631 E_HDMITX_NDS_SET_ENC_EN, 632 HDMITX_CMD_NDS_SET_ENC_EN, 633 E_HDMITX_NDS_GET_HDCP_STATUS, 634 HDMITX_CMD_NDS_GET_HDCP_STATUS, 635 HDMITX_CMD_SET_COLORIMETRY, 636 HDMITX_CMD_GET_FULL_RX_STATUS, 637 HDMITX_CMD_TIMING_CAPABILITY_CHECK, 638 HDMITX_CMD_HDCP1XTX_CHK_RI, 639 HDMITX_CMD_GET_PANELSIZE_FROM_EDID, 640 HDMITX_CMD_GET_TMDS_STATUS, 641 HDMITX_CMD_SET_TIMING_INFO_BY_CUSTOMER, 642 HDMITX_CMD_NUMBER, 643 } HDMITX_CTRL_ID; 644 645 #define EN_HDMITX_CTRL_ID HDMITX_CTRL_ID 646 647 typedef enum //color range 648 { 649 HDMITX_QUANT_LIMIT = 0x00, 650 HDMITX_QUANT_FULL = 0x01, 651 HDMITX_QUANT_RESERVED = 0x10, 652 } HDMITX_QUANT_RANGE; 653 654 #define EN_HDMITX_QUANT_RANGE HDMITX_QUANT_RANGE 655 656 typedef struct DLL_PACKED 657 { 658 HDMITX_VIDEO_COLOR_FORMAT input_color; 659 HDMITX_VIDEO_COLOR_FORMAT output_color; 660 HDMITX_QUANT_RANGE input_range; 661 HDMITX_QUANT_RANGE output_range; 662 MS_BOOL result; 663 } HDMITX_COLOR_AND_RANGE_TRANSFORM_PARAMETERS; 664 665 typedef struct DLL_PACKED 666 { 667 MS_U32 u32StructVersion;//StructVersion Control 668 MS_U8 u8SSCEn; 669 MS_BOOL result; 670 } HDMITX_SSCENABLE; 671 672 typedef enum 673 { 674 HDMITX_SSCENABLE_STRUCTVER_NONE= 0, 675 HDMITX_SSCENABLE_STRUCTVER_1= 1, 676 HDMITX_SSCENABLE_STRUCTVER_NUM 677 }HDMITX_SSCENABLE_STRUCTVER; 678 679 typedef struct DLL_PACKED 680 { 681 MS_U32 u32StructVersion;//StructVersion Control 682 HDMITX_AVI_COLORIMETRY colorimetry; 683 MS_U8 u8Return; 684 } HDMITX_SET_COLORIMETRY; 685 686 typedef enum 687 { 688 HDMITX_SET_COLORIMETRY_STRUCTVER_NONE= 0, 689 HDMITX_SET_COLORIMETRY_STRUCTVER_1= 1, 690 HDMITX_SET_COLORIMETRY_STRUCTVER_NUM 691 }HDMITX_SET_COLORIMETRY_STRUCTVER; 692 693 typedef enum 694 { 695 HDMITX_DVIClock_L_HPD_L = 0, 696 HDMITX_DVIClock_L_HPD_H = 1, 697 HDMITX_DVIClock_H_HPD_L = 2, 698 HDMITX_DVIClock_H_HPD_H = 3, 699 } HDMITX_RX_STATUS; 700 701 typedef struct DLL_PACKED 702 { 703 MS_U32 u32StructVersion;//StructVersion Control 704 MS_U32 u32RxStatus; 705 } HDMITX_GET_FULL_RX_STATUS; 706 707 typedef struct DLL_PACKED 708 { 709 MS_U8 i_p_mode; // interlace / progressive mode 710 MS_U8 h_polarity; // Hsync polarity 711 MS_U8 v_polarity; // Vsync polarity 712 MS_U16 vs_width; // Vsync pulse width 713 MS_U16 vs_bporch; // Vsync back-porch 714 MS_U16 vde_width; // Vde active width 715 MS_U16 vs_delayline; // Vsync line delay 716 MS_U16 vs_delaypixel; // Vsync pixel delay 717 MS_U16 hs_width; // Hsync pulse width 718 MS_U16 hs_bporch; // Hsync back-porch 719 MS_U16 hde_width; // Hde active width 720 MS_U16 hs_delay; // Hsync delay 721 MS_U16 vtotal; // Vsync total 722 MS_U16 htotal; // Hsync total 723 724 725 } HDMITX_TIMING_INFO_BY_CUSTOMER; 726 727 typedef enum 728 { 729 HDMITX_GET_FULL_RX_STATUS_STRUCTVER_NONE= 0, 730 HDMITX_GET_FULL_RX_STATUS_STRUCTVER_1= 1, 731 HDMITX_GET_FULL_RX_STATUS_STRUCTVER_NUM 732 }HDMITX_GET_FULL_RX_STATUS_STRUCTVER; 733 734 typedef enum 735 { 736 HDMITX_TIMING_ERR_NONE = 0x00000000, 737 HDMITX_TIMING_ERR_CFG_ERR = 0x00000001, 738 HDMITX_TIMING_ERR_EDID_ERR = 0x00000002, 739 HDMITX_TIMING_ERR_COLOR_FMT = 0x00000004, 740 HDMITX_TIMING_ERR_COLOR_DEPTH = 0x00000008, 741 HDMITX_TIMING_ERR_TIMING = 0x00000010, 742 HDMITX_TIMING_ERR_HW_LIMIT = 0x00000020, 743 HDMITX_TIMING_ERR_SW_LIMIT = 0x00000040, 744 HDMITX_TIMING_ERR_SINK_LIMIT = 0x00000080, 745 HDMITX_TIMING_ERR_MAX = 0xFFFFFFFF 746 }HDMITX_TIMING_ERROR; 747 748 typedef struct DLL_PACKED 749 { 750 MS_U32 u32StructVersion;//StructVersion Control 751 HDMITX_OUTPUT_MODE eOutputMode; 752 HDMITX_VIDEO_TIMING eTiming; 753 HDMITX_VIDEO_COLOR_FORMAT eInColor; 754 HDMITX_VIDEO_COLOR_FORMAT eOutColor; 755 HDMITX_VIDEO_COLORDEPTH_VAL eColorDepth; 756 HDMITX_TIMING_ERROR ubRet; 757 } HDMITX_CHECK_LEGAL_TIMING; 758 759 typedef enum 760 { 761 HDMITX_CHECK_LEGAL_TIMING_STRUCTVER_NONE= 0, 762 HDMITX_CHECK_LEGAL_TIMING_STRUCTVER_1= 1, 763 HDMITX_CHECK_LEGAL_TIMING_STRUCTVER_NUM 764 }HDMITX_CHECK_LEGAL_TIMING_STRUCTVER; 765 766 typedef struct DLL_PACKED 767 { 768 MS_U32 u32StructVersion;//StructVersion Control 769 MS_U32 u32PanelWidth; 770 MS_U32 u32PanelHeight; 771 MS_U32 u32Ret; 772 } HDMITX_GET_PANELSIZE_FROM_EDID; 773 774 typedef enum 775 { 776 HDMITX_GET_PANELSIZE_FROM_EDID_STRUCTVER_NONE= 0, 777 HDMITX_GET_PANELSIZE_FROM_EDID_STRUCTVER_1= 1, 778 HDMITX_GET_PANELSIZE_FROM_EDID_STRUCTVER_NUM 779 }HDMITX_GET_PANELSIZE_FROM_EDID_STRUCTVER; 780 781 782 typedef struct DLL_PACKED 783 { 784 MS_U32 u32StructVersion;//StructVersion Control 785 MS_U32 u32TMDSStatus; 786 MS_U32 u32Ret; 787 } HDMITX_GET_TMDS_STATUS; 788 789 typedef struct DLL_PACKED 790 { 791 MS_U32 u32StructVersion;//StructVersion Control 792 HDMITX_VIDEO_TIMING u8Timing; 793 HDMITX_TIMING_INFO_BY_CUSTOMER stTimingInfo; 794 } HDMITX_SET_TIMING_INFO_BY_CUSTOMER; 795 796 typedef enum 797 { 798 HDMITX_GET_TMDS_STATUS_STRUCTVER_NONE= 0, 799 HDMITX_GET_TMDS_STATUS_STRUCTVER_1= 1, 800 HDMITX_GET_TMDS_STATUS_STRUCTVER_NUM 801 }HDMITX_GET_TMDS_STATUS_STRUCTVER; 802 803 typedef enum 804 { 805 E_CEA_EXT_TAG_VCDB = 0, //video capability data block 806 E_CEA_EXT_TAG_VSVDB = 1, //vendor-specific video data block 807 E_CEA_EXT_TAG_VDDDB = 2, //VESA display device data block 808 E_CEA_EXT_TAG_VVTBE = 3, //VESA video timing block extension 809 E_CEA_EXT_TAG_CDB = 5, //colorimetry data block 810 E_CEA_EXT_TAG_HSMDB = 6, //HDR static meta data block 811 E_CEA_EXT_TAG_420VDB = 14, //YCbCr420 video data block 812 E_CEA_EXT_TAG_420CMDB = 15, //YCbCr420 cpability map data block 813 E_CEA_EXT_TAG_VSADB = 17, //vendor-specific audio data block 814 E_CEA_EXT_TAG_IFDB = 32 //infoframe data block 815 } HDMITX_CEA_EXT_TAG_CODE; 816 817 typedef enum 818 { 819 E_CEA_TAG_CODE_AUDIO = 1, 820 E_CEA_TAG_CODE_VIDEO = 2, 821 E_CEA_TAG_CODE_VSDB = 3, 822 E_CEA_TAG_CODE_SPEAKER_ALLOCAT = 4, 823 E_CEA_TAG_CODE_VDTC = 5, //VESA display transfer characteristic data block 824 E_CEA_TAG_CODE_EXT_TAG = 7, 825 E_CEA_TAG_CODE_HFVSDB = 8 //new block in hdmi 20 826 } HDMITX_CEA_DB_TAG_CODE; 827 828 829 830 enum HDMITX_HDCP1_X74OffSET_ADDR//typedef enum 831 { 832 E_HDCP1_OFFSETADDR_Bksv = (MS_U8)0x00, 833 E_HDCP1_OFFSETADDR_RiPrime = (MS_U8)0x08, 834 E_HDCP1_OFFSETADDR_PjPrime = (MS_U8)0x0A, 835 E_HDCP1_OFFSETADDR_Aksv = (MS_U8)0x10, 836 E_HDCP1_OFFSETADDR_Ainfo = (MS_U8)0x15, 837 E_HDCP1_OFFSETADDR_An = (MS_U8)0x18, 838 E_HDCP1_OFFSETADDR_VPrime = (MS_U8)0x20, 839 E_HDCP1_OFFSETADDR_VPrimeH1 = (MS_U8)0x24, 840 E_HDCP1_OFFSETADDR_VPrimeH2 = (MS_U8)0x28, 841 E_HDCP1_OFFSETADDR_VPrimeH3 = (MS_U8)0x2C, 842 E_HDCP1_OFFSETADDR_VPrimeH4 = (MS_U8)0x30, 843 E_HDCP1_OFFSETADDR_BCaps = (MS_U8)0x40, 844 E_HDCP1_OFFSETADDR_BStatus = (MS_U8)0x41, 845 E_HDCP1_OFFSETADDR_KsvFifo = (MS_U8)0x43, 846 E_HDCP1_OFFSETADDR_DBG = (MS_U8)0xC0 847 }; //HDMITX_HDCP1x_X74OffSET_ADDR; 848 849 /*********************************************************************/ 850 /* */ 851 /* HDCP22 Relative */ 852 /* */ 853 /*********************************************************************/ 854 enum HDMITX_HDCP2_X74OffSET_ADDR//typedef enum 855 { 856 E_HDCP2_OFFSETADDR_HDCP2Version = (MS_U8)0x50, 857 E_HDCP2_OFFSETADDR_WriteMessage = (MS_U8)0x60, 858 E_HDCP2_OFFSETADDR_RxStatus = (MS_U8)0x70, 859 E_HDCP2_OFFSETADDR_ReadMessage = (MS_U8)0x80, 860 E_HDCP2_OFFSETADDR_DBG = (MS_U8)0xC0, 861 }; //HDMITX_HDCP2_X74OffSET_ADDR; 862 863 enum HDMITX_HDCP2_OPCODE//typedef enum 864 { 865 E_HDCP2_OPCODE_WRITE = (MS_U8)0x00, 866 E_HDCP2_OPCODE_READ = (MS_U8)0x01, 867 }; //HDMITX_HDCP2_OPCODE; 868 869 870 //------------------------------------------------------------------------------------------------- 871 // Function and Variable 872 //------------------------------------------------------------------------------------------------- 873 874 875 //*********************// 876 // DVI / HDMI // 877 //*********************// 878 879 MS_BOOL SYMBOL_WEAK MApi_HDMITx_Init(void); 880 881 MS_BOOL SYMBOL_WEAK MApi_HDMITx_Exit(void); 882 883 884 // HDMI Tx module On/Off 885 /* 886 Before turn on HDMI TX module, video and audio source should be prepared ready and set the following APIs first. 887 { 888 ... 889 MApi_HDMITx_TurnOnOff(TRUE); 890 MApi_HDMITx_SetRBChannelSwap(TRUE); 891 MApi_HDMITx_SetColorFormat(HDMITX_VIDEO_COLOR_YUV444, HDMITX_VIDEO_COLOR_RGB444); 892 MApi_HDMITx_SetVideoOnOff(TRUE); 893 MApi_HDMITx_SetHDMITxMode_CD(HDMITX_HDMI, HDMITX_VIDEO_CD_24Bits); 894 MApi_HDMITx_SetVideoOutputTiming(HDMITX_RES_1920x1080p_60Hz); 895 MApi_HDMITx_Exhibit(); 896 ... 897 } 898 899 */ 900 void SYMBOL_WEAK MApi_HDMITx_TurnOnOff(MS_BOOL state); 901 902 // HDMI packet enable or not 903 void SYMBOL_WEAK MApi_HDMITx_EnablePacketGen(MS_BOOL bflag); 904 905 // HDMI Tx output is DVI / HDMI mode 906 void SYMBOL_WEAK MApi_HDMITx_SetHDMITxMode(HDMITX_OUTPUT_MODE mode); 907 908 // HDMI Tx output is DVI / HDMI mode and color depth 909 void SYMBOL_WEAK MApi_HDMITx_SetHDMITxMode_CD(HDMITX_OUTPUT_MODE mode, HDMITX_VIDEO_COLORDEPTH_VAL val); 910 911 // HDMI Tx TMDS signal On/Off 912 void SYMBOL_WEAK MApi_HDMITx_SetTMDSOnOff(MS_BOOL state); 913 914 // HDMI Tx TMDS control disable/enable 915 void SYMBOL_WEAK MApi_HDMITx_DisableTMDSCtrl(MS_BOOL bFlag); 916 917 // HDMI Tx R/B channel swap 918 void SYMBOL_WEAK MApi_HDMITx_SetRBChannelSwap(MS_BOOL state); 919 920 // HDMI Tx Exhibit funtcion 921 void SYMBOL_WEAK MApi_HDMITx_Exhibit(void); 922 923 // HDMI Tx force output mode 924 void SYMBOL_WEAK MApi_HDMITx_ForceHDMIOutputMode(MS_BOOL bflag, HDMITX_OUTPUT_MODE output_mode); 925 926 // HDMI Tx force output color format 927 MS_BOOL SYMBOL_WEAK MApi_HDMITx_ForceHDMIOutputColorFormat(MS_BOOL bflag, HDMITX_VIDEO_COLOR_FORMAT output_color); 928 929 // Get the connected HDMI Rx status 930 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetRxStatus(void); 931 932 // Get Rx's deep color definition from EDID 933 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetRxDCInfoFromEDID(HDMITX_VIDEO_COLORDEPTH_VAL *val); 934 935 // Get Rx's support video format from EDID 936 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetRxVideoFormatFromEDID(MS_U8 *pu8Buffer, MS_U8 u8BufSize); 937 938 // Get vic list from EDID 939 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetVICListFromEDID(MS_U8 *pu8Buffer, MS_U8 u8BufSize); 940 941 // Get Rx's data block length 942 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetDataBlockLengthFromEDID(MS_U8 *pu8Length, MS_U8 u8TagCode); 943 944 // Get Rx's support audio format from EDID 945 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetRxAudioFormatFromEDID(MS_U8 *pu8Buffer, MS_U8 u8BufSize); 946 947 // Get Rx's support mode from EDID 948 MS_BOOL SYMBOL_WEAK MApi_HDMITx_EDID_HDMISupport(MS_BOOL *HDMI_Support); 949 950 // Get Rx's ID Manufacturer Name from EDID 951 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetRxIDManufacturerName(MS_U8 *pu8Buffer); 952 953 954 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetBksv(MS_U8 *pdata); 955 956 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetAksv(MS_U8 *pdata); 957 958 959 // Get Rx's EDID data 960 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetEDIDData(MS_U8 *pu8Buffer, MS_BOOL BlockIdx); 961 962 // Get Rx's supported 3D structures of specific timing from EDID 963 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetRx3DStructureFromEDID(HDMITX_VIDEO_TIMING timing, HDMITX_EDID_3D_STRUCTURE_ALL *p3DStructure); 964 965 // Get color format from EDID 966 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetColorFormatFromEDID(HDMITX_VIDEO_TIMING timing, HDMITX_EDID_COLOR_FORMAT *pColorFmt); 967 968 // This function clear settings of user defined packet 969 void SYMBOL_WEAK MApi_HDMITx_PKT_User_Define_Clear(void); 970 971 // This function set user defined hdmi packet 972 void SYMBOL_WEAK MApi_HDMITx_PKT_User_Define(HDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag, 973 HDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt); 974 975 // This function let user define hdmi packet content 976 MS_BOOL SYMBOL_WEAK MApi_HDMITx_PKT_Content_Define(HDMITX_PACKET_TYPE packet_type, MS_U8 *data, MS_U8 length); 977 978 979 //*********************// 980 // Video // 981 //*********************// 982 983 // HDMI Tx video output On/Off 984 void SYMBOL_WEAK MApi_HDMITx_SetVideoOnOff(MS_BOOL state); 985 // HDMI Tx video color format 986 void SYMBOL_WEAK MApi_HDMITx_SetColorFormat(HDMITX_VIDEO_COLOR_FORMAT in_color, HDMITX_VIDEO_COLOR_FORMAT out_color); 987 // HDMI Tx video output timing 988 void SYMBOL_WEAK MApi_HDMITx_SetVideoOutputTiming(HDMITX_VIDEO_TIMING mode); 989 // HDMI Tx video output timing by customer info 990 void SYMBOL_WEAK MApi_HDMITx_SetVideoOutputTimingByCustomer(HDMITX_VIDEO_TIMING mode, HDMITX_TIMING_INFO_BY_CUSTOMER timinginfo); 991 992 // HDMI Tx video output aspect ratio 993 void SYMBOL_WEAK MApi_HDMITx_SetVideoOutputAsepctRatio(HDMITX_VIDEO_ASPECT_RATIO out_ar); 994 // HDMI Tx video output Overscan and AFD ratio 995 void SYMBOL_WEAK MApi_HDMITx_SetVideoOutputOverscan_AFD(MS_BOOL bflag, HDMITX_VIDEO_SCAN_INFO out_scaninfo, MS_U8 out_afd); 996 void SYMBOL_WEAK MApi_HDMITx_SetVideoOutputOverscan_AFD_II(MS_BOOL bflag, HDMITX_VIDEO_SCAN_INFO out_scaninfo, MS_U8 out_afd, MS_U8 A0 ); 997 void SYMBOL_WEAK MApi_HDMITx_Set_VS_InfoFrame(HDMITX_VIDEO_VS_FORMAT vs_format, HDMITX_VIDEO_3D_STRUCTURE vs_3d, HDMITX_VIDEO_4k2k_VIC vs_vic); 998 999 MS_BOOL SYMBOL_WEAK MApi_HDMITx_SetAVIInfoExtColorimetry(HDMITX_AVI_EXTENDED_COLORIMETRY enExtColorimetry, HDMITX_AVI_YCC_QUANT_RANGE enYccQuantRange); 1000 1001 1002 //*********************// 1003 // Audio // 1004 //*********************// 1005 1006 // HDMI Tx audio output On/Off 1007 void SYMBOL_WEAK MApi_HDMITx_SetAudioOnOff(MS_BOOL state); 1008 // HDMI Tx audio output sampling frequency 1009 // For Uranus 1010 void SYMBOL_WEAK MApi_HDMITx_SetAudioFrequency(HDMITX_AUDIO_FREQUENCY freq); 1011 // HDMI Tx Module audio output: sampling frequency, channel count and coding type 1012 // For Oberon 1013 void SYMBOL_WEAK MApi_HDMITx_SetAudioConfiguration(HDMITX_AUDIO_FREQUENCY freq, HDMITX_AUDIO_CHANNEL_COUNT ch, HDMITX_AUDIO_CODING_TYPE type); 1014 // HDMI Tx get audio CTS value. 1015 MS_U32 SYMBOL_WEAK MApi_HDMITx_GetAudioCTS(void); 1016 // HDMI Tx mute/unmute audio FIFO. 1017 void SYMBOL_WEAK MApi_HDMITx_MuteAudioFIFO(MS_BOOL bflag); 1018 // Set HDMI audio source format 1019 void SYMBOL_WEAK MApi_HDMITx_SetAudioSourceFormat(HDMITX_AUDIO_SOURCE_FORMAT fmt); 1020 1021 //void MApi_HDMITx_SetAudioFrequencyFromMad(void); 1022 //*********************// 1023 // HDCP // 1024 //*********************// 1025 1026 // HDMI Tx Get HDCP key (set internal/external HDCP key) 1027 // @param[in] useinternalkey: TRUE -> from internal, FALSE -> from external, like SPI flash 1028 void SYMBOL_WEAK MApi_HDMITx_GetHdcpKey(MS_BOOL useinternalkey, MS_U8 *data); 1029 // HDMI Tx HDCP encryption On/Off 1030 void SYMBOL_WEAK MApi_HDMITx_SetHDCPOnOff(MS_BOOL state); 1031 // This routine set HDMI Tx AVMUTE 1032 void SYMBOL_WEAK MApi_HDMITx_SetAVMUTE(MS_BOOL bflag); 1033 // This routine get HDMI Tx AVMUTE status 1034 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetAVMUTEStatus(void); 1035 // HDMI Tx HDCP status 1036 HDMITX_HDCP_STATUS SYMBOL_WEAK MApi_HDMITx_GetHDCPStatus(void); 1037 // HDCP start Authentication 1038 void SYMBOL_WEAK MApi_HDMITx_HDCP_StartAuth(MS_BOOL bFlag); 1039 // HDMI Tx Internal HDCP status 1040 HDMITX_INT_HDCP_STATUS SYMBOL_WEAK MApi_HDMITx_GetINTHDCPStatus(void); 1041 // HDMI Tx HDCP pre-status 1042 HDMITX_INT_HDCP_STATUS SYMBOL_WEAK MApi_HDMITx_GetHDCP_PreStatus(void); 1043 // HDMI video output or blank or encryption while connected with unsupport HDCP Rx 1044 void SYMBOL_WEAK MApi_HDMITx_UnHDCPRxControl(HDMITX_UNHDCPRX_CONTROL state); 1045 // HDMI video output or blank or encryption while HDCP authentication fail 1046 void SYMBOL_WEAK MApi_HDMITx_HDCPRxFailControl(HDMITX_HDCPRXFail_CONTROL state); 1047 // This routine to set the time interval from sent aksv to R0. 1048 MS_BOOL SYMBOL_WEAK MApi_HDMITx_SetAksv2R0Interval(MS_U32 u32Interval); 1049 // This API to get active Rx status. 1050 MS_BOOL SYMBOL_WEAK MApi_HDMITx_IsHDCPRxValid(void); 1051 // This API return revocation check state 1052 HDMITX_REVOCATION_STATE SYMBOL_WEAK MApi_HDMITx_HDCP_RevocationKey_Check(void); 1053 // This API will update revocation list (note : size 1 = 5 bytes !!!) 1054 void SYMBOL_WEAK MApi_HDMITx_HDCP_RevocationKey_List(MS_U8 *data, MS_U16 size); 1055 1056 1057 // Debug 1058 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetLibVer(const MSIF_Version **ppVersion); 1059 1060 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetInfo(HDMI_TX_INFO *pInfo); 1061 1062 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetStatus(HDMI_TX_Status *pStatus); 1063 1064 MS_BOOL SYMBOL_WEAK MApi_HDMITx_HDCP_IsSRMSignatureValid(MS_U8 *data, MS_U32 size); 1065 1066 /** 1067 * @brief set debug mask 1068 * @param[in] u16DbgSwitch DEBUG MASK, 1069 * 0x01: Debug HDMITX, 0x02: Debug HDCP 1070 */ 1071 MS_BOOL SYMBOL_WEAK MApi_HDMITx_SetDbgLevel(MS_U16 u16DbgSwitch); 1072 1073 void SYMBOL_WEAK MApi_HDMITx_SetHPDGpioPin(MS_U8 u8pin); 1074 1075 // Adjust HDMITx analog setting for HDMI test or compliant issue 1076 void SYMBOL_WEAK MApi_HDMITx_AnalogTuning(HDMITX_ANALOG_TUNING *pInfo); 1077 1078 void SYMBOL_WEAK MApi_HDMITx_DisableRegWrite(MS_BOOL bFlag); 1079 1080 //*********************// 1081 // CEC // 1082 //*********************// 1083 1084 /// This routine get EDID physical address 1085 void SYMBOL_WEAK MApi_HDMITx_GetEDIDPhyAdr(MS_U8 *pdata); 1086 // This routine turn on/off HDMI Tx CEC 1087 void SYMBOL_WEAK MApi_HDMITx_SetCECOnOff(MS_BOOL bflag); 1088 // This routine get HDMI Tx CEC On/Off status 1089 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetCECStatus(void); 1090 // This routine force get EDID from reciver 1091 MS_BOOL SYMBOL_WEAK MApi_HDMITx_EdidChecking(void); 1092 1093 //*********************// 1094 // RxBypassMode // 1095 //*********************// 1096 MS_BOOL SYMBOL_WEAK MApi_HDMITx_RxBypass_Mode(HDMITX_INPUT_FREQ freq, MS_BOOL bflag); 1097 1098 MS_BOOL SYMBOL_WEAK MApi_HDMITx_Disable_RxBypass(void); 1099 1100 1101 //*************************// 1102 // CHIP Capaibility // 1103 //*************************// 1104 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetChipCaps(EN_HDMITX_CAPS eCapType, MS_U32* pRet, MS_U32 ret_size); 1105 1106 MS_U32 SYMBOL_WEAK MApi_HDMITx_SetPowerState(EN_POWER_MODE u16PowerState); 1107 1108 1109 1110 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetEdidDataBlocks(HDMITX_CEA_DB_TAG_CODE enTagCode, HDMITX_CEA_EXT_TAG_CODE enExtTagCode, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 1111 1112 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GetKSVList(MS_U8 *pu8Bstatus, MS_U8* pu8KSVList, MS_U16 u16BufLen, MS_U16 *pu16KSVLength); 1113 1114 MS_BOOL SYMBOL_WEAK MApi_HDMITx_GeneralCtrl(MS_U32 u32Cmd, void* pu8Buf, MS_U32 u32BufSize); 1115 /*********************************************************************/ 1116 /* */ 1117 /* HDCP22 Relative */ 1118 /* */ 1119 /*********************************************************************/ 1120 MS_BOOL SYMBOL_WEAK MApi_HDMITx_HDCP2AccessX74(MS_U8 u8PortIdx, MS_U8 u8OffsetAddr, MS_U8 u8OpCode, MS_U8 *pu8RdBuf, MS_U16 u16RdLen, MS_U8 *pu8WRBuff, MS_U16 u16WrLen); 1121 void SYMBOL_WEAK MApi_HDMITx_HDCP2TxInit(MS_U8 u8PortIdx, MS_BOOL bEnable); 1122 void SYMBOL_WEAK MApi_HDMITx_HDCP2TxEnableEncrypt(MS_U8 u8PortIdx, MS_BOOL bEnable); 1123 void SYMBOL_WEAK MApi_HDMITx_HDCP2TxFillCipherKey(MS_U8 u8PortIdx, MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128); 1124 1125 #ifdef __cplusplus 1126 } 1127 #endif 1128 1129 1130 #endif // _API_HDMITX_H_ 1131 1132