1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78
79 #ifndef _HAL_IRQTBL_H_
80 #define _HAL_IRQTBL_H_
81
82 #ifdef __cplusplus
83 extern "C"
84 {
85 #endif
86
87 #define E_INT_RESERVED E_INT_IRQ_FIQ_NONE
88
89 #if defined(MSOS_TYPE_LINUX)
90
91 #ifdef CONFIG_INT_SPI_MODE
92 //Set Interrupt Base Address in SPI Mode
93 #define CONFIG_IRQL_BASE_ADDRESS 0x00
94 #define CONFIG_IRQH_BASE_ADDRESS 0x10
95 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x20
96 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x30
97 #define CONFIG_FIQL_BASE_ADDRESS 0x40
98 #define CONFIG_FIQH_BASE_ADDRESS 0x50
99 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
100 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
101 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
102 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
103 #else
104 //Set Interrupt Base Address in PPI Mode
105 #define CONFIG_IRQL_BASE_ADDRESS 0x40
106 #define CONFIG_IRQH_BASE_ADDRESS 0x50
107 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x60
108 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x70
109 #define CONFIG_FIQL_BASE_ADDRESS 0x00
110 #define CONFIG_FIQH_BASE_ADDRESS 0x10
111 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x20
112 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x30
113 #define CONFIG_IRQHYPL_BASE_ADDRESS 0xC0
114 #define CONFIG_IRQHYPH_BASE_ADDRESS 0xD0
115 #endif
116
117 #elif defined(MSOS_TYPE_NOS)
118 //Set Interrupt Base Address in PPI Mode
119 #define CONFIG_IRQL_BASE_ADDRESS 0x00
120 #define CONFIG_IRQH_BASE_ADDRESS 0x10
121 #define CONFIG_FIQL_BASE_ADDRESS 0x20
122 #define CONFIG_FIQH_BASE_ADDRESS 0x30
123 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x40
124 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x50
125 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
126 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
127 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
128 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
129 #elif defined(MSOS_TYPE_NUTTX)
130 #define CONFIG_IRQL_BASE_ADDRESS 0x00
131 #define CONFIG_IRQH_BASE_ADDRESS 0x10
132 #define CONFIG_FIQL_BASE_ADDRESS 0x20
133 #define CONFIG_FIQH_BASE_ADDRESS 0x30
134 #define CONFIG_IRQEXPL_BASE_ADDRESS 0x40
135 #define CONFIG_IRQEXPH_BASE_ADDRESS 0x50
136 #define CONFIG_FIQEXPL_BASE_ADDRESS 0x60
137 #define CONFIG_FIQEXPH_BASE_ADDRESS 0x70
138 #define CONFIG_IRQHYPL_BASE_ADDRESS 0x80
139 #define CONFIG_IRQHYPH_BASE_ADDRESS 0x90
140 #else
141 #error "Unknown Platform Selection"
142 #endif
143
144 typedef enum
145 {
146 E_IRQL_START = CONFIG_IRQL_BASE_ADDRESS,
147 E_IRQ_00 = E_IRQL_START + 0,
148 E_IRQ_01 = E_IRQL_START + 1,
149 E_IRQ_02 = E_IRQL_START + 2,
150 E_IRQ_03 = E_IRQL_START + 3,
151 E_IRQ_04 = E_IRQL_START + 4,
152 E_IRQ_05 = E_IRQL_START + 5,
153 E_IRQ_06 = E_IRQL_START + 6,
154 E_IRQ_07 = E_IRQL_START + 7,
155 E_IRQ_08 = E_IRQL_START + 8,
156 E_IRQ_09 = E_IRQL_START + 9,
157 E_IRQ_10 = E_IRQL_START + 10,
158 E_IRQ_11 = E_IRQL_START + 11,
159 E_IRQ_12 = E_IRQL_START + 12,
160 E_IRQ_13 = E_IRQL_START + 13,
161 E_IRQ_14 = E_IRQL_START + 14,
162 E_IRQ_15 = E_IRQL_START + 15,
163 E_IRQL_END = E_IRQL_START + 15,
164
165 E_IRQH_START = CONFIG_IRQH_BASE_ADDRESS,
166 E_IRQ_16 = E_IRQH_START + 0,
167 E_IRQ_17 = E_IRQH_START + 1,
168 E_IRQ_18 = E_IRQH_START + 2,
169 E_IRQ_19 = E_IRQH_START + 3,
170 E_IRQ_20 = E_IRQH_START + 4,
171 E_IRQ_21 = E_IRQH_START + 5,
172 E_IRQ_22 = E_IRQH_START + 6,
173 E_IRQ_23 = E_IRQH_START + 7,
174 E_IRQ_24 = E_IRQH_START + 8,
175 E_IRQ_25 = E_IRQH_START + 9,
176 E_IRQ_26 = E_IRQH_START + 10,
177 E_IRQ_27 = E_IRQH_START + 11,
178 E_IRQ_28 = E_IRQH_START + 12,
179 E_IRQ_29 = E_IRQH_START + 13,
180 E_IRQ_30 = E_IRQH_START + 14,
181 E_IRQ_31 = E_IRQH_START + 15,
182 E_IRQH_END = E_IRQH_START + 15,
183
184 E_FIQL_START = CONFIG_FIQL_BASE_ADDRESS,
185 E_FIQ_00 = E_FIQL_START + 0,
186 E_FIQ_01 = E_FIQL_START + 1,
187 E_FIQ_02 = E_FIQL_START + 2,
188 E_FIQ_03 = E_FIQL_START + 3,
189 E_FIQ_04 = E_FIQL_START + 4,
190 E_FIQ_05 = E_FIQL_START + 5,
191 E_FIQ_06 = E_FIQL_START + 6,
192 E_FIQ_07 = E_FIQL_START + 7,
193 E_FIQ_08 = E_FIQL_START + 8,
194 E_FIQ_09 = E_FIQL_START + 9,
195 E_FIQ_10 = E_FIQL_START + 10,
196 E_FIQ_11 = E_FIQL_START + 11,
197 E_FIQ_12 = E_FIQL_START + 12,
198 E_FIQ_13 = E_FIQL_START + 13,
199 E_FIQ_14 = E_FIQL_START + 14,
200 E_FIQ_15 = E_FIQL_START + 15,
201 E_FIQL_END = E_FIQL_START + 15,
202
203 E_FIQH_START = CONFIG_FIQH_BASE_ADDRESS,
204 E_FIQ_16 = E_FIQH_START + 0,
205 E_FIQ_17 = E_FIQH_START + 1,
206 E_FIQ_18 = E_FIQH_START + 2,
207 E_FIQ_19 = E_FIQH_START + 3,
208 E_FIQ_20 = E_FIQH_START + 4,
209 E_FIQ_21 = E_FIQH_START + 5,
210 E_FIQ_22 = E_FIQH_START + 6,
211 E_FIQ_23 = E_FIQH_START + 7,
212 E_FIQ_24 = E_FIQH_START + 8,
213 E_FIQ_25 = E_FIQH_START + 9,
214 E_FIQ_26 = E_FIQH_START + 10,
215 E_FIQ_27 = E_FIQH_START + 11,
216 E_FIQ_28 = E_FIQH_START + 12,
217 E_FIQ_29 = E_FIQH_START + 13,
218 E_FIQ_30 = E_FIQH_START + 14,
219 E_FIQ_31 = E_FIQH_START + 15,
220 E_FIQH_END = E_FIQH_START + 15,
221
222 E_IRQEXPL_START = CONFIG_IRQEXPL_BASE_ADDRESS,
223 E_IRQ_32 = E_IRQEXPL_START + 0,
224 E_IRQ_33 = E_IRQEXPL_START + 1,
225 E_IRQ_34 = E_IRQEXPL_START + 2,
226 E_IRQ_35 = E_IRQEXPL_START + 3,
227 E_IRQ_36 = E_IRQEXPL_START + 4,
228 E_IRQ_37 = E_IRQEXPL_START + 5,
229 E_IRQ_38 = E_IRQEXPL_START + 6,
230 E_IRQ_39 = E_IRQEXPL_START + 7,
231 E_IRQ_40 = E_IRQEXPL_START + 8,
232 E_IRQ_41 = E_IRQEXPL_START + 9,
233 E_IRQ_42 = E_IRQEXPL_START + 10,
234 E_IRQ_43 = E_IRQEXPL_START + 11,
235 E_IRQ_44 = E_IRQEXPL_START + 12,
236 E_IRQ_45 = E_IRQEXPL_START + 13,
237 E_IRQ_46 = E_IRQEXPL_START + 14,
238 E_IRQ_47 = E_IRQEXPL_START + 15,
239 E_IRQEXPL_END = E_IRQEXPL_START + 15,
240
241 E_IRQEXPH_START = CONFIG_IRQEXPH_BASE_ADDRESS,
242 E_IRQ_48 = E_IRQEXPH_START + 0,
243 E_IRQ_49 = E_IRQEXPH_START + 1,
244 E_IRQ_50 = E_IRQEXPH_START + 2,
245 E_IRQ_51 = E_IRQEXPH_START + 3,
246 E_IRQ_52 = E_IRQEXPH_START + 4,
247 E_IRQ_53 = E_IRQEXPH_START + 5,
248 E_IRQ_54 = E_IRQEXPH_START + 6,
249 E_IRQ_55 = E_IRQEXPH_START + 7,
250 E_IRQ_56 = E_IRQEXPH_START + 8,
251 E_IRQ_57 = E_IRQEXPH_START + 9,
252 E_IRQ_58 = E_IRQEXPH_START + 10,
253 E_IRQ_59 = E_IRQEXPH_START + 11,
254 E_IRQ_60 = E_IRQEXPH_START + 12,
255 E_IRQ_61 = E_IRQEXPH_START + 13,
256 E_IRQ_62 = E_IRQEXPH_START + 14,
257 E_IRQ_63 = E_IRQEXPH_START + 15,
258 E_IRQEXPH_END = E_IRQEXPH_START + 15,
259
260 E_FIQEXPL_START = CONFIG_FIQEXPL_BASE_ADDRESS,
261 E_FIQ_32 = E_FIQEXPL_START + 0,
262 E_FIQ_33 = E_FIQEXPL_START + 1,
263 E_FIQ_34 = E_FIQEXPL_START + 2,
264 E_FIQ_35 = E_FIQEXPL_START + 3,
265 E_FIQ_36 = E_FIQEXPL_START + 4,
266 E_FIQ_37 = E_FIQEXPL_START + 5,
267 E_FIQ_38 = E_FIQEXPL_START + 6,
268 E_FIQ_39 = E_FIQEXPL_START + 7,
269 E_FIQ_40 = E_FIQEXPL_START + 8,
270 E_FIQ_41 = E_FIQEXPL_START + 9,
271 E_FIQ_42 = E_FIQEXPL_START + 10,
272 E_FIQ_43 = E_FIQEXPL_START + 11,
273 E_FIQ_44 = E_FIQEXPL_START + 12,
274 E_FIQ_45 = E_FIQEXPL_START + 13,
275 E_FIQ_46 = E_FIQEXPL_START + 14,
276 E_FIQ_47 = E_FIQEXPL_START + 15,
277 E_FIQEXPL_END = E_FIQEXPL_START + 15,
278
279 E_FIQEXPH_START = CONFIG_FIQEXPH_BASE_ADDRESS,
280 E_FIQ_48 = E_FIQEXPH_START + 0,
281 E_FIQ_49 = E_FIQEXPH_START + 1,
282 E_FIQ_50 = E_FIQEXPH_START + 2,
283 E_FIQ_51 = E_FIQEXPH_START + 3,
284 E_FIQ_52 = E_FIQEXPH_START + 4,
285 E_FIQ_53 = E_FIQEXPH_START + 5,
286 E_FIQ_54 = E_FIQEXPH_START + 6,
287 E_FIQ_55 = E_FIQEXPH_START + 7,
288 E_FIQ_56 = E_FIQEXPH_START + 8,
289 E_FIQ_57 = E_FIQEXPH_START + 9,
290 E_FIQ_58 = E_FIQEXPH_START + 10,
291 E_FIQ_59 = E_FIQEXPH_START + 11,
292 E_FIQ_60 = E_FIQEXPH_START + 12,
293 E_FIQ_61 = E_FIQEXPH_START + 13,
294 E_FIQ_62 = E_FIQEXPH_START + 14,
295 E_FIQ_63 = E_FIQEXPH_START + 15,
296 E_FIQEXPH_END = E_FIQEXPH_START + 15,
297
298 E_IRQHYPL_START = CONFIG_IRQHYPL_BASE_ADDRESS,
299 E_IRQ_64 = E_IRQHYPL_START + 0,
300 E_IRQ_65 = E_IRQHYPL_START + 1,
301 E_IRQ_66 = E_IRQHYPL_START + 2,
302 E_IRQ_67 = E_IRQHYPL_START + 3,
303 E_IRQ_68 = E_IRQHYPL_START + 4,
304 E_IRQ_69 = E_IRQHYPL_START + 5,
305 E_IRQ_70 = E_IRQHYPL_START + 6,
306 E_IRQ_71 = E_IRQHYPL_START + 7,
307 E_IRQ_72 = E_IRQHYPL_START + 8,
308 E_IRQ_73 = E_IRQHYPL_START + 9,
309 E_IRQ_74 = E_IRQHYPL_START + 10,
310 E_IRQ_75 = E_IRQHYPL_START + 11,
311 E_IRQ_76 = E_IRQHYPL_START + 12,
312 E_IRQ_77 = E_IRQHYPL_START + 13,
313 E_IRQ_78 = E_IRQHYPL_START + 14,
314 E_IRQ_79 = E_IRQHYPL_START + 15,
315 E_IRQHYPL_END = E_IRQHYPL_START + 15,
316
317 E_IRQHYPH_START = CONFIG_IRQHYPH_BASE_ADDRESS,
318 E_IRQ_80 = E_IRQHYPH_START + 0,
319 E_IRQ_81 = E_IRQHYPH_START + 1,
320 E_IRQ_82 = E_IRQHYPH_START + 2,
321 E_IRQ_83 = E_IRQHYPH_START + 3,
322 E_IRQ_84 = E_IRQHYPH_START + 4,
323 E_IRQ_85 = E_IRQHYPH_START + 5,
324 E_IRQ_86 = E_IRQHYPH_START + 6,
325 E_IRQ_87 = E_IRQHYPH_START + 7,
326 E_IRQ_88 = E_IRQHYPH_START + 8,
327 E_IRQ_89 = E_IRQHYPH_START + 9,
328 E_IRQ_90 = E_IRQHYPH_START + 10,
329 E_IRQ_91 = E_IRQHYPH_START + 11,
330 E_IRQ_92 = E_IRQHYPH_START + 12,
331 E_IRQ_93 = E_IRQHYPH_START + 13,
332 E_IRQ_94 = E_IRQHYPH_START + 14,
333 E_IRQ_95 = E_IRQHYPH_START + 15,
334 E_IRQHYPH_END = E_IRQHYPH_START + 15,
335
336 E_IRQ_FIQ_NONE = 0xFE,
337 E_IRQ_FIQ_ALL = 0xFF
338
339 } IRQFIQNum;
340
341 static MS_U16 IntEnum2HWIdx[E_INT_IRQ_MAX];
342 static MS_U16 HWIdx2IntEnum[E_IRQ_FIQ_ALL];
343
HAL_UpdateIrqTable(MS_U16 byHardwareIndex,MS_U16 bySoftwareIndex)344 static void HAL_UpdateIrqTable(MS_U16 byHardwareIndex, MS_U16 bySoftwareIndex)
345 {
346 if(bySoftwareIndex == E_INT_RESERVED)
347 {
348 IntEnum2HWIdx[bySoftwareIndex] = E_IRQ_FIQ_NONE;
349 HWIdx2IntEnum[byHardwareIndex] = E_INT_IRQ_FIQ_NONE;
350 }
351 else
352 {
353 IntEnum2HWIdx[bySoftwareIndex] = byHardwareIndex;
354 HWIdx2IntEnum[byHardwareIndex] = bySoftwareIndex;
355 }
356 }
357
HAL_InitIrqTable(void)358 static void HAL_InitIrqTable(void)
359 {
360 unsigned int dwDataCounter = 0;
361
362 for(dwDataCounter = 0; dwDataCounter < E_IRQ_FIQ_ALL; dwDataCounter ++)
363 {
364 IntEnum2HWIdx[dwDataCounter] = E_IRQ_FIQ_NONE;
365 HWIdx2IntEnum[dwDataCounter] = E_INT_IRQ_FIQ_NONE;
366 }
367
368 for(dwDataCounter = E_IRQ_FIQ_ALL; dwDataCounter < E_INT_IRQ_MAX; dwDataCounter ++)
369 {
370 IntEnum2HWIdx[dwDataCounter] = E_IRQ_FIQ_NONE;
371 }
372
373 HAL_UpdateIrqTable(E_IRQ_00, E_INT_RESERVED); //RESERVED
374 HAL_UpdateIrqTable(E_IRQ_01, E_INT_IRQ_PMSLEEP); //pm_sleep_int
375 HAL_UpdateIrqTable(E_IRQ_02, E_INT_IRQ_AEON2HI); //aeon2hi
376 HAL_UpdateIrqTable(E_IRQ_03, E_INT_IRQ_MVD); //mvd_int
377 HAL_UpdateIrqTable(E_IRQ_04, E_INT_IRQ_PS); //ps_int
378 HAL_UpdateIrqTable(E_IRQ_05, E_INT_IRQ_NFIE); //nfie_int
379 HAL_UpdateIrqTable(E_IRQ_06, E_INT_IRQ_MIIC_INT5); //miic5_int
380 HAL_UpdateIrqTable(E_IRQ_07, E_INT_IRQ_MIIC_INT4); //miic4_int
381 HAL_UpdateIrqTable(E_IRQ_08, E_INT_IRQ_SMART); //smart_int
382 HAL_UpdateIrqTable(E_IRQ_09, E_INT_IRQ_EMAC); //emac_int
383 HAL_UpdateIrqTable(E_IRQ_10, E_INT_IRQ_DISP); //disp_int
384 HAL_UpdateIrqTable(E_IRQ_11, E_INT_IRQ_MVD2MIPS); //mvd2mips_int
385 HAL_UpdateIrqTable(E_IRQ_12, E_INT_IRQ_SVD_HVD); //hvd_int
386 HAL_UpdateIrqTable(E_IRQ_13, E_INT_IRQ_EVD); //evd_int
387 HAL_UpdateIrqTable(E_IRQ_14, E_INT_IRQ_COMB); //comb_int
388 HAL_UpdateIrqTable(E_IRQ_15, E_INT_IRQ_ADCDVI2RIU); //adcdvi2riu_int
389
390 HAL_UpdateIrqTable(E_IRQ_16, E_INT_IRQ_TSP2HK); //tsp2hk_int
391 HAL_UpdateIrqTable(E_IRQ_17, E_INT_IRQ_VE); //ve_int
392 HAL_UpdateIrqTable(E_IRQ_18, E_INT_IRQ_G3D2MCU); //g3d2mcu_int
393 HAL_UpdateIrqTable(E_IRQ_19, E_INT_IRQ_DC); //dc_int
394 HAL_UpdateIrqTable(E_IRQ_20, E_INT_IRQ_GOP); //gop_int
395 HAL_UpdateIrqTable(E_IRQ_21, E_INT_IRQ_PCM); //pcm2mcu_int
396 HAL_UpdateIrqTable(E_IRQ_22, E_INT_IRQ_AU_DMA); //miic0_int
397 HAL_UpdateIrqTable(E_IRQ_23, E_INT_IRQ_MFE); //mfe_int
398 HAL_UpdateIrqTable(E_IRQ_24, E_INT_IRQ_ERROR_RESP); //error_resp_int
399 HAL_UpdateIrqTable(E_IRQ_25, E_INT_IRQEXPL_TSO); //tso_int
400 HAL_UpdateIrqTable(E_IRQ_26, E_INT_IRQ_DDC2BI); //d2b_int
401 HAL_UpdateIrqTable(E_IRQ_27, E_INT_IRQ_SCM); //scm_int
402 HAL_UpdateIrqTable(E_IRQ_28, E_INT_IRQ_VBI); //vbi_int
403 HAL_UpdateIrqTable(E_IRQ_29, E_INT_IRQ_USB); //usb_int
404 HAL_UpdateIrqTable(E_IRQ_30, E_INT_IRQ_UHC); //uhc_int
405 HAL_UpdateIrqTable(E_IRQ_31, E_INT_IRQ_USB1); //usb_int1
406
407 HAL_UpdateIrqTable(E_IRQ_32, E_INT_IRQ_UHC1); //uhc_int1
408 HAL_UpdateIrqTable(E_IRQ_33, E_INT_IRQ_USB2); //usb_int2
409 HAL_UpdateIrqTable(E_IRQ_34, E_INT_IRQ_UHC2); //uhc_int2
410 HAL_UpdateIrqTable(E_IRQ_35, E_INT_IRQ_USB3); //usb_int3
411 HAL_UpdateIrqTable(E_IRQ_36, E_INT_IRQ_UHC3); //uhc_int3
412 HAL_UpdateIrqTable(E_IRQ_37, E_INT_IRQ_MIU); //miu_int
413 HAL_UpdateIrqTable(E_IRQ_38, E_INT_IRQ_UART0); //int_uart0
414 HAL_UpdateIrqTable(E_IRQ_39, E_INT_IRQ_UART1); //int_uart1
415 HAL_UpdateIrqTable(E_IRQ_40, E_INT_IRQ_UART2); //int_uart2
416 HAL_UpdateIrqTable(E_IRQ_41, E_INT_IRQ_UART3); //int_uart3
417 HAL_UpdateIrqTable(E_IRQ_42, E_INT_IRQ_UART4); //int_uart4
418 HAL_UpdateIrqTable(E_IRQ_43, E_INT_IRQ_UART5); //int_uart5
419 HAL_UpdateIrqTable(E_IRQ_44, E_INT_IRQ_GE); //int_ge
420 HAL_UpdateIrqTable(E_IRQ_45, E_INT_IRQ_MIU_SECURITY); //security_int
421 HAL_UpdateIrqTable(E_IRQ_46, E_INT_IRQ_MSPI1); //mspi1_int
422 HAL_UpdateIrqTable(E_IRQ_47, E_INT_IRQ_MSPI0); //mspi0_int
423
424 HAL_UpdateIrqTable(E_IRQ_48, E_INT_IRQ_BDMA0); //int_bdma[0]
425 HAL_UpdateIrqTable(E_IRQ_49, E_INT_IRQ_BDMA1); //int_bdma[1]
426 HAL_UpdateIrqTable(E_IRQ_50, E_INT_IRQ_UART2MCU); //uart2mcu_intr
427 HAL_UpdateIrqTable(E_IRQ_51, E_INT_IRQ_URDMA2MCU); //urdma2mcu_intr
428 HAL_UpdateIrqTable(E_IRQ_52, E_INT_IRQ_DVI_HDMI_HDCP); //dvi_hdmi_hdcp_int
429 HAL_UpdateIrqTable(E_IRQ_53, E_INT_IRQ_MHL_CBUS_PM); //mhl_cbus_pm_int
430 HAL_UpdateIrqTable(E_IRQ_54, E_INT_IRQ_CEC); //cec_int_pm
431 HAL_UpdateIrqTable(E_IRQ_55, E_INT_IRQ_HDCP_IIC); //hdcp_iic_int
432 HAL_UpdateIrqTable(E_IRQ_56, E_INT_IRQ_HDCP_X74); //hdcp_x74_int
433 HAL_UpdateIrqTable(E_IRQ_57, E_INT_IRQ_WADR_ERR); //wadr_err_int
434 HAL_UpdateIrqTable(E_IRQ_58, E_INT_IRQ_MIIC_DMA_INT0); //miic_dma_int0
435 HAL_UpdateIrqTable(E_IRQ_59, E_INT_IRQ_MIIC_DMA_INT1); //miic_dma_int1
436 HAL_UpdateIrqTable(E_IRQ_60, E_INT_IRQ_MIIC_DMA_INT2); //miic_dma_int2
437 HAL_UpdateIrqTable(E_IRQ_61, E_INT_IRQ_MIIC_DMA_INT3); //miic_dma_int3
438 HAL_UpdateIrqTable(E_IRQ_62, E_INT_IRQ_JPD); //jpd_int
439 HAL_UpdateIrqTable(E_IRQ_63, E_INT_IRQ_EXT_GPIO_MERGE); //ext_gpio_int[7]
440
441 HAL_UpdateIrqTable(E_IRQ_64, E_INT_IRQ_DIMOND_L3_BRIDGE_INT); //miic_dma_int3
442 HAL_UpdateIrqTable(E_IRQ_65,E_INT_IRQ_PAS_PTS_INTRL_COMBINE); //jpd_int
443 HAL_UpdateIrqTable(E_IRQ_90, E_INT_IRQ_AESDMA_S_INT); //ext_gpio_int[7]
444
445 HAL_UpdateIrqTable(E_FIQ_00, E_INT_FIQ_EXTIMER0); //int_timer0
446 HAL_UpdateIrqTable(E_FIQ_01, E_INT_FIQ_EXTIMER1); //int_timer1
447 HAL_UpdateIrqTable(E_FIQ_02, E_INT_FIQ_WDT); //int_wdt
448 HAL_UpdateIrqTable(E_FIQ_03, E_INT_RESERVED); //Reserved
449 HAL_UpdateIrqTable(E_FIQ_04, E_INT_FIQ_R2TOMCU_INT0); //MB_auR2toMCU_INT[0]
450 HAL_UpdateIrqTable(E_FIQ_05, E_INT_FIQ_R2TOMCU_INT1); //MB_auR2toMCU_INT[1]
451 HAL_UpdateIrqTable(E_FIQ_06, E_INT_FIQ_DSPTOMCU_INT0); //MB_DSP2toMCU_INT[0]
452 HAL_UpdateIrqTable(E_FIQ_07, E_INT_FIQ_DSPTOMCU_INT1); //MB_DSP2toMCU_INT[1]
453 HAL_UpdateIrqTable(E_FIQ_08, E_INT_FIQ_USB); //usb_int
454 HAL_UpdateIrqTable(E_FIQ_09, E_INT_FIQ_UHC); //uhc_int
455 HAL_UpdateIrqTable(E_FIQ_10, E_INT_RESERVED); //gpio_pm_[7]
456 HAL_UpdateIrqTable(E_FIQ_11, E_INT_FIQ_HDMI_NON_PCM); //HDMI_NON_PCM_MODE_INT_OUT
457 HAL_UpdateIrqTable(E_FIQ_12, E_INT_FIQ_SPDIF_IN_NON_PCM);//SPDIF_IN_NON_PCM_INT_OUT
458 HAL_UpdateIrqTable(E_FIQ_13, E_INT_FIQ_EMAC); //emac_int
459 HAL_UpdateIrqTable(E_FIQ_14, E_INT_FIQ_SE_DSP2UP); //SE_DSP2UP_intr
460 HAL_UpdateIrqTable(E_FIQ_15, E_INT_FIQ_TSP2AEON); //tsp2aeon_int
461
462 HAL_UpdateIrqTable(E_FIQ_16, E_INT_FIQ_VIVALDI_STR); //vivaldi_str_intr
463 HAL_UpdateIrqTable(E_FIQ_17, E_INT_FIQ_VIVALDI_PTS); //vivaldi_pts_intr
464 HAL_UpdateIrqTable(E_FIQ_18, E_INT_FIQ_DSP_MIU_PROT); //DSP_MIU_PROT_intr
465 HAL_UpdateIrqTable(E_FIQ_19, E_INT_FIQ_XIU_TIMEOUT); //xiu_timeout_int
466 HAL_UpdateIrqTable(E_FIQ_20, E_INT_FIQ_DMDMCU2HK); //dmdmcu2hk_int
467 HAL_UpdateIrqTable(E_FIQ_21, E_INT_FIQ_VSYNC_VE4VBI); //ve_vbi_f0_int
468 HAL_UpdateIrqTable(E_FIQ_22, E_INT_FIQ_FIELD_VE4VBI); //ve_vbi_f1_int
469 HAL_UpdateIrqTable(E_FIQ_23, E_INT_FIQ_VDMCU2HK); //vdmcu2hk_int
470 HAL_UpdateIrqTable(E_FIQ_24, E_INT_FIQ_VE_DONE_TT); //ve_done_TT_irq
471 HAL_UpdateIrqTable(E_FIQ_25, E_INT_RESERVED); //Reserved
472 HAL_UpdateIrqTable(E_FIQ_26, E_INT_RESERVED); //Reserved
473 HAL_UpdateIrqTable(E_FIQ_27, E_INT_FIQ_IR); //ir_int
474 HAL_UpdateIrqTable(E_FIQ_28, E_INT_FIQ_AFEC_VSYNC); //AFEC_VSYNC
475 HAL_UpdateIrqTable(E_FIQ_29, E_INT_FIQ_USB2); //usb_int2
476 HAL_UpdateIrqTable(E_FIQ_30, E_INT_FIQ_UHC2); //uhc_int2
477 HAL_UpdateIrqTable(E_FIQ_31, E_INT_FIQ_DEC_DSP2MIPS); //DSP2MIPS_INT
478
479 HAL_UpdateIrqTable(E_FIQ_32, E_INT_FIQ_IR_INT_RC); //ir_int_rc
480 HAL_UpdateIrqTable(E_FIQ_33, E_INT_FIQ_AU_DMA_BUF_INT); //AU_DMA_BUFFER_INT_EDGE
481 HAL_UpdateIrqTable(E_FIQ_34, E_INT_FIQ_IR_IN); //ir_in
482 HAL_UpdateIrqTable(E_FIQ_35, E_INT_FIQ_EXTIMER2); //gpio_pm_[11]
483 HAL_UpdateIrqTable(E_FIQ_36, E_INT_FIQ_8051_TO_MIPS_VPE1); //reg_hst0to3_int
484 HAL_UpdateIrqTable(E_FIQ_37, E_INT_FIQ_8051_TO_MIPS_VPE0 ); //reg_hst0to2_int
485 HAL_UpdateIrqTable(E_FIQ_38, E_INT_FIQ_8051_TO_AEON); //reg_hst0to1_int
486 HAL_UpdateIrqTable(E_FIQ_39, E_INT_RESERVED); //Reserved
487 HAL_UpdateIrqTable(E_FIQ_40, E_INT_FIQ_AEON_TO_MIPS_VPE1 ); //reg_hst1to3_int
488 HAL_UpdateIrqTable(E_FIQ_41, E_INT_FIQ_AEON_TO_BEON ); //reg_hst1to2_int
489 HAL_UpdateIrqTable(E_FIQ_42, E_INT_FIQ_AEON_TO_8051 ); //reg_hst1to0_int
490 HAL_UpdateIrqTable(E_FIQ_43, E_INT_RESERVED); //Reserved
491 HAL_UpdateIrqTable(E_FIQ_44, E_INT_FIQ_MIPS_VPE0_TO_MIPS_VPE1); //reg_hst2to3_int
492 HAL_UpdateIrqTable(E_FIQ_45, E_INT_FIQ_BEON_TO_AEON); //reg_hst2to1_int
493 HAL_UpdateIrqTable(E_FIQ_46, E_INT_FIQ_MIPS_VPE0_TO_8051); //reg_hst2to0_int
494 HAL_UpdateIrqTable(E_FIQ_47, E_INT_RESERVED); //Reserved
495
496 HAL_UpdateIrqTable(E_FIQ_48, E_INT_FIQ_MIPS_VPE1_TO_MIPS_VPE0 ); //reg_hst3to2_int
497 HAL_UpdateIrqTable(E_FIQ_49, E_INT_FIQ_MIPS_VPE1_TO_AEON); //reg_hst3to1_int
498 HAL_UpdateIrqTable(E_FIQ_50, E_INT_FIQ_MIPS_VPE1_TO_8051); //reg_hst3to0_int
499 HAL_UpdateIrqTable(E_FIQ_51, E_INT_FIQ_USB1); //usb_int1
500 HAL_UpdateIrqTable(E_FIQ_52, E_INT_FIQ_UHC1); //uhc_int1
501 HAL_UpdateIrqTable(E_FIQ_53, E_INT_FIQ_LDM_DMA1); //ldm_dma_done_int1
502 HAL_UpdateIrqTable(E_FIQ_54, E_INT_FIQ_LDM_DMA0); //ldm_dma_done_int0
503 HAL_UpdateIrqTable(E_FIQ_55, E_INT_FIQ_AU_SPDIF_TX_CS0);//AU_SPDIF_TX_CS_INT[0]
504 HAL_UpdateIrqTable(E_FIQ_56, E_INT_FIQ_AU_SPDIF_TX_CS1);//AU_SPDIF_TX_CS_INT[1]
505 HAL_UpdateIrqTable(E_FIQ_57, E_INT_FIQ_USB3); //usb_int3
506 HAL_UpdateIrqTable(E_FIQ_58, E_INT_FIQ_UHC3); //uhc_int3
507 HAL_UpdateIrqTable(E_FIQ_59, E_INT_IRQ_PWM_RP_L); //pwm_rp_l_int
508 HAL_UpdateIrqTable(E_FIQ_60, E_INT_IRQ_PWM_FP_L); //pwm_fp_l_int
509 HAL_UpdateIrqTable(E_FIQ_61, E_INT_IRQ_PWM_RP_R); //pwm_rp_r_int
510 HAL_UpdateIrqTable(E_FIQ_62, E_INT_IRQ_PWM_FP_R); //pwm_fp_r_int
511 HAL_UpdateIrqTable(E_FIQ_63, E_INT_FIQ_SPI2FCIE); //spi2fcie_int
512
513 }
514
515 #ifdef __cplusplus
516 }
517 #endif
518
519 #endif // _HAL_IRQTBL_H_
520
521