1*53ee8cc1Swenshuai.xi //<MStar Software> 2*53ee8cc1Swenshuai.xi //****************************************************************************** 3*53ee8cc1Swenshuai.xi // MStar Software 4*53ee8cc1Swenshuai.xi // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5*53ee8cc1Swenshuai.xi // All software, firmware and related documentation herein ("MStar Software") are 6*53ee8cc1Swenshuai.xi // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7*53ee8cc1Swenshuai.xi // law, including, but not limited to, copyright law and international treaties. 8*53ee8cc1Swenshuai.xi // Any use, modification, reproduction, retransmission, or republication of all 9*53ee8cc1Swenshuai.xi // or part of MStar Software is expressly prohibited, unless prior written 10*53ee8cc1Swenshuai.xi // permission has been granted by MStar. 11*53ee8cc1Swenshuai.xi // 12*53ee8cc1Swenshuai.xi // By accessing, browsing and/or using MStar Software, you acknowledge that you 13*53ee8cc1Swenshuai.xi // have read, understood, and agree, to be bound by below terms ("Terms") and to 14*53ee8cc1Swenshuai.xi // comply with all applicable laws and regulations: 15*53ee8cc1Swenshuai.xi // 16*53ee8cc1Swenshuai.xi // 1. MStar shall retain any and all right, ownership and interest to MStar 17*53ee8cc1Swenshuai.xi // Software and any modification/derivatives thereof. 18*53ee8cc1Swenshuai.xi // No right, ownership, or interest to MStar Software and any 19*53ee8cc1Swenshuai.xi // modification/derivatives thereof is transferred to you under Terms. 20*53ee8cc1Swenshuai.xi // 21*53ee8cc1Swenshuai.xi // 2. You understand that MStar Software might include, incorporate or be 22*53ee8cc1Swenshuai.xi // supplied together with third party`s software and the use of MStar 23*53ee8cc1Swenshuai.xi // Software may require additional licenses from third parties. 24*53ee8cc1Swenshuai.xi // Therefore, you hereby agree it is your sole responsibility to separately 25*53ee8cc1Swenshuai.xi // obtain any and all third party right and license necessary for your use of 26*53ee8cc1Swenshuai.xi // such third party`s software. 27*53ee8cc1Swenshuai.xi // 28*53ee8cc1Swenshuai.xi // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29*53ee8cc1Swenshuai.xi // MStar`s confidential information and you agree to keep MStar`s 30*53ee8cc1Swenshuai.xi // confidential information in strictest confidence and not disclose to any 31*53ee8cc1Swenshuai.xi // third party. 32*53ee8cc1Swenshuai.xi // 33*53ee8cc1Swenshuai.xi // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34*53ee8cc1Swenshuai.xi // kind. Any warranties are hereby expressly disclaimed by MStar, including 35*53ee8cc1Swenshuai.xi // without limitation, any warranties of merchantability, non-infringement of 36*53ee8cc1Swenshuai.xi // intellectual property rights, fitness for a particular purpose, error free 37*53ee8cc1Swenshuai.xi // and in conformity with any international standard. You agree to waive any 38*53ee8cc1Swenshuai.xi // claim against MStar for any loss, damage, cost or expense that you may 39*53ee8cc1Swenshuai.xi // incur related to your use of MStar Software. 40*53ee8cc1Swenshuai.xi // In no event shall MStar be liable for any direct, indirect, incidental or 41*53ee8cc1Swenshuai.xi // consequential damages, including without limitation, lost of profit or 42*53ee8cc1Swenshuai.xi // revenues, lost or damage of data, and unauthorized system use. 43*53ee8cc1Swenshuai.xi // You agree that this Section 4 shall still apply without being affected 44*53ee8cc1Swenshuai.xi // even if MStar Software has been modified by MStar in accordance with your 45*53ee8cc1Swenshuai.xi // request or instruction for your use, except otherwise agreed by both 46*53ee8cc1Swenshuai.xi // parties in writing. 47*53ee8cc1Swenshuai.xi // 48*53ee8cc1Swenshuai.xi // 5. If requested, MStar may from time to time provide technical supports or 49*53ee8cc1Swenshuai.xi // services in relation with MStar Software to you for your use of 50*53ee8cc1Swenshuai.xi // MStar Software in conjunction with your or your customer`s product 51*53ee8cc1Swenshuai.xi // ("Services"). 52*53ee8cc1Swenshuai.xi // You understand and agree that, except otherwise agreed by both parties in 53*53ee8cc1Swenshuai.xi // writing, Services are provided on an "AS IS" basis and the warranty 54*53ee8cc1Swenshuai.xi // disclaimer set forth in Section 4 above shall apply. 55*53ee8cc1Swenshuai.xi // 56*53ee8cc1Swenshuai.xi // 6. Nothing contained herein shall be construed as by implication, estoppels 57*53ee8cc1Swenshuai.xi // or otherwise: 58*53ee8cc1Swenshuai.xi // (a) conferring any license or right to use MStar name, trademark, service 59*53ee8cc1Swenshuai.xi // mark, symbol or any other identification; 60*53ee8cc1Swenshuai.xi // (b) obligating MStar or any of its affiliates to furnish any person, 61*53ee8cc1Swenshuai.xi // including without limitation, you and your customers, any assistance 62*53ee8cc1Swenshuai.xi // of any kind whatsoever, or any information; or 63*53ee8cc1Swenshuai.xi // (c) conferring any license or right under any intellectual property right. 64*53ee8cc1Swenshuai.xi // 65*53ee8cc1Swenshuai.xi // 7. These terms shall be governed by and construed in accordance with the laws 66*53ee8cc1Swenshuai.xi // of Taiwan, R.O.C., excluding its conflict of law rules. 67*53ee8cc1Swenshuai.xi // Any and all dispute arising out hereof or related hereto shall be finally 68*53ee8cc1Swenshuai.xi // settled by arbitration referred to the Chinese Arbitration Association, 69*53ee8cc1Swenshuai.xi // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70*53ee8cc1Swenshuai.xi // Rules of the Association by three (3) arbitrators appointed in accordance 71*53ee8cc1Swenshuai.xi // with the said Rules. 72*53ee8cc1Swenshuai.xi // The place of arbitration shall be in Taipei, Taiwan and the language shall 73*53ee8cc1Swenshuai.xi // be English. 74*53ee8cc1Swenshuai.xi // The arbitration award shall be final and binding to both parties. 75*53ee8cc1Swenshuai.xi // 76*53ee8cc1Swenshuai.xi //****************************************************************************** 77*53ee8cc1Swenshuai.xi //<MStar Software> 78*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 79*53ee8cc1Swenshuai.xi // 80*53ee8cc1Swenshuai.xi // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81*53ee8cc1Swenshuai.xi // All rights reserved. 82*53ee8cc1Swenshuai.xi // 83*53ee8cc1Swenshuai.xi // Unless otherwise stipulated in writing, any and all information contained 84*53ee8cc1Swenshuai.xi // herein regardless in any format shall remain the sole proprietary of 85*53ee8cc1Swenshuai.xi // MStar Semiconductor Inc. and be kept in strict confidence 86*53ee8cc1Swenshuai.xi // ("MStar Confidential Information") by the recipient. 87*53ee8cc1Swenshuai.xi // Any unauthorized act including without limitation unauthorized disclosure, 88*53ee8cc1Swenshuai.xi // copying, use, reproduction, sale, distribution, modification, disassembling, 89*53ee8cc1Swenshuai.xi // reverse engineering and compiling of the contents of MStar Confidential 90*53ee8cc1Swenshuai.xi // Information is unlawful and strictly prohibited. MStar hereby reserves the 91*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom. 92*53ee8cc1Swenshuai.xi // 93*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 94*53ee8cc1Swenshuai.xi 95*53ee8cc1Swenshuai.xi #ifndef _HAL_CHIP_H_ 96*53ee8cc1Swenshuai.xi #define _HAL_CHIP_H_ 97*53ee8cc1Swenshuai.xi 98*53ee8cc1Swenshuai.xi 99*53ee8cc1Swenshuai.xi 100*53ee8cc1Swenshuai.xi #ifdef __cplusplus 101*53ee8cc1Swenshuai.xi extern "C" 102*53ee8cc1Swenshuai.xi { 103*53ee8cc1Swenshuai.xi #endif 104*53ee8cc1Swenshuai.xi 105*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 106*53ee8cc1Swenshuai.xi // Macro and Define 107*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 108*53ee8cc1Swenshuai.xi 109*53ee8cc1Swenshuai.xi typedef enum 110*53ee8cc1Swenshuai.xi { 111*53ee8cc1Swenshuai.xi E_CHIP_MIU_0 = 0, 112*53ee8cc1Swenshuai.xi E_CHIP_MIU_1, 113*53ee8cc1Swenshuai.xi E_CHIP_MIU_2, 114*53ee8cc1Swenshuai.xi E_CHIP_MIU_3, 115*53ee8cc1Swenshuai.xi E_CHIP_MIU_NUM, 116*53ee8cc1Swenshuai.xi } CHIP_MIU_ID; 117*53ee8cc1Swenshuai.xi 118*53ee8cc1Swenshuai.xi #define ARM_CLOCK_FREQ 1008000000 119*53ee8cc1Swenshuai.xi #define MIPS_CLOCK_FREQ 900000000 120*53ee8cc1Swenshuai.xi #define AEON_CLOCK_FREQ 240000000 121*53ee8cc1Swenshuai.xi #define XTAL_CLOCK_FREQ 12000000 122*53ee8cc1Swenshuai.xi 123*53ee8cc1Swenshuai.xi #define HAL_MIU0_BASE 0x00000000UL 124*53ee8cc1Swenshuai.xi #if defined(__AEONR2__) 125*53ee8cc1Swenshuai.xi #define HAL_MIU1_BASE 0x40000000UL // 1512MB 126*53ee8cc1Swenshuai.xi #define HAL_MIU2_BASE 0xC0000000UL // 127*53ee8cc1Swenshuai.xi #else 128*53ee8cc1Swenshuai.xi #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 129*53ee8cc1Swenshuai.xi #define HAL_MIU1_BASE 0x80000000UL // 1512MB 130*53ee8cc1Swenshuai.xi #define HAL_MIU2_BASE 0x100000000UL // 131*53ee8cc1Swenshuai.xi #else 132*53ee8cc1Swenshuai.xi #define HAL_MIU1_BASE 0x80000000UL // 1512MB 133*53ee8cc1Swenshuai.xi #define HAL_MIU2_BASE 0xC0000000UL // 134*53ee8cc1Swenshuai.xi #define HAL_MIU2_BASE2 0x100000000UL // 135*53ee8cc1Swenshuai.xi #endif 136*53ee8cc1Swenshuai.xi #endif 137*53ee8cc1Swenshuai.xi 138*53ee8cc1Swenshuai.xi #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 139*53ee8cc1Swenshuai.xi #define HAL_MIU0_BUS_BASE 0x20000000UL // MIU0 Low 256MB 140*53ee8cc1Swenshuai.xi #define HAL_MIU1_BUS_BASE 0x200000000UL // MIU1 Low 256MB MUJI: 0xA0000000UL 141*53ee8cc1Swenshuai.xi #define HAL_MIU2_BUS_BASE 0x300000000UL // 64 bit mapping 142*53ee8cc1Swenshuai.xi #else 143*53ee8cc1Swenshuai.xi #define HAL_MIU0_BUS_BASE 0x20000000UL 144*53ee8cc1Swenshuai.xi #define HAL_MIU1_BUS_BASE 0xA0000000UL 145*53ee8cc1Swenshuai.xi #define HAL_MIU2_BUS_BASE 0x300000000UL 146*53ee8cc1Swenshuai.xi #endif 147*53ee8cc1Swenshuai.xi 148*53ee8cc1Swenshuai.xi #if defined(__AEONR2__) 149*53ee8cc1Swenshuai.xi #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < HAL_MIU1_BASE) \ 150*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 151*53ee8cc1Swenshuai.xi else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 152*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 153*53ee8cc1Swenshuai.xi else \ 154*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} 155*53ee8cc1Swenshuai.xi 156*53ee8cc1Swenshuai.xi #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 157*53ee8cc1Swenshuai.xi {PhysAddr = Offset;} \ 158*53ee8cc1Swenshuai.xi else if (MiuSel == E_CHIP_MIU_1) \ 159*53ee8cc1Swenshuai.xi {PhysAddr = Offset + HAL_MIU1_BASE;} \ 160*53ee8cc1Swenshuai.xi else \ 161*53ee8cc1Swenshuai.xi {PhysAddr = Offset + HAL_MIU2_BASE;} 162*53ee8cc1Swenshuai.xi #else 163*53ee8cc1Swenshuai.xi 164*53ee8cc1Swenshuai.xi #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 165*53ee8cc1Swenshuai.xi #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < HAL_MIU1_BASE) \ 166*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 167*53ee8cc1Swenshuai.xi else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 168*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 169*53ee8cc1Swenshuai.xi else \ 170*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} 171*53ee8cc1Swenshuai.xi 172*53ee8cc1Swenshuai.xi #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 173*53ee8cc1Swenshuai.xi {PhysAddr = Offset;} \ 174*53ee8cc1Swenshuai.xi else if (MiuSel == E_CHIP_MIU_1) \ 175*53ee8cc1Swenshuai.xi {PhysAddr = Offset + HAL_MIU1_BASE;} \ 176*53ee8cc1Swenshuai.xi else \ 177*53ee8cc1Swenshuai.xi {PhysAddr = Offset + HAL_MIU2_BASE;} 178*53ee8cc1Swenshuai.xi #else 179*53ee8cc1Swenshuai.xi #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr >= HAL_MIU2_BASE2 && PhysAddr < 0x200000000UL) { \ 180*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE2;}} else { \ 181*53ee8cc1Swenshuai.xi if (PhysAddr < HAL_MIU1_BASE) \ 182*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 183*53ee8cc1Swenshuai.xi else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 184*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 185*53ee8cc1Swenshuai.xi else \ 186*53ee8cc1Swenshuai.xi {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} \ 187*53ee8cc1Swenshuai.xi } 188*53ee8cc1Swenshuai.xi 189*53ee8cc1Swenshuai.xi #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 190*53ee8cc1Swenshuai.xi {PhysAddr = Offset;} \ 191*53ee8cc1Swenshuai.xi else if (MiuSel == E_CHIP_MIU_1) \ 192*53ee8cc1Swenshuai.xi {PhysAddr = Offset + HAL_MIU1_BASE;} \ 193*53ee8cc1Swenshuai.xi else \ 194*53ee8cc1Swenshuai.xi {PhysAddr = Offset + HAL_MIU2_BASE;} 195*53ee8cc1Swenshuai.xi #endif 196*53ee8cc1Swenshuai.xi #endif 197*53ee8cc1Swenshuai.xi 198*53ee8cc1Swenshuai.xi #define SUPPORT TRUE 199*53ee8cc1Swenshuai.xi #define NONSUPPORT FALSE 200*53ee8cc1Swenshuai.xi 201*53ee8cc1Swenshuai.xi #define CHIP_IP_MFE SUPPORT 202*53ee8cc1Swenshuai.xi #define CHIP_IP_VE SUPPORT 203*53ee8cc1Swenshuai.xi #define CHIP_IP_AVD SUPPORT 204*53ee8cc1Swenshuai.xi #define CHIP_IP_DEMOD SUPPORT 205*53ee8cc1Swenshuai.xi #define CHIP_IP_VBI SUPPORT 206*53ee8cc1Swenshuai.xi #define CHIP_IP_VIF SUPPORT 207*53ee8cc1Swenshuai.xi #define CHIP_IP_DMX SUPPORT 208*53ee8cc1Swenshuai.xi #define CHIP_IP_CEC SUPPORT 209*53ee8cc1Swenshuai.xi #define CHIP_IP_MBX SUPPORT 210*53ee8cc1Swenshuai.xi #define CHIP_IP_SWI2C SUPPORT 211*53ee8cc1Swenshuai.xi #define CHIP_IP_BDMA SUPPORT 212*53ee8cc1Swenshuai.xi #define CHIP_IP_CPU SUPPORT 213*53ee8cc1Swenshuai.xi #define CHIP_IP_GPIO SUPPORT 214*53ee8cc1Swenshuai.xi #define CHIP_IP_HWI2C SUPPORT 215*53ee8cc1Swenshuai.xi #define CHIP_IP_IR SUPPORT 216*53ee8cc1Swenshuai.xi #define CHIP_IP_MIU SUPPORT 217*53ee8cc1Swenshuai.xi #define CHIP_IP_MPIF NONSUPPORT 218*53ee8cc1Swenshuai.xi #define CHIP_IP_MSPI SUPPORT 219*53ee8cc1Swenshuai.xi #define CHIP_IP_PM SUPPORT 220*53ee8cc1Swenshuai.xi #define CHIP_IP_PWM SUPPORT 221*53ee8cc1Swenshuai.xi #define CHIP_IP_PWS SUPPORT 222*53ee8cc1Swenshuai.xi #define CHIP_IP_RTC SUPPORT 223*53ee8cc1Swenshuai.xi #define CHIP_IP_SAR SUPPORT 224*53ee8cc1Swenshuai.xi #define CHIP_IP_URDMA SUPPORT 225*53ee8cc1Swenshuai.xi #define CHIP_IP_WDT SUPPORT 226*53ee8cc1Swenshuai.xi #define CHIP_IP_AESDMA SUPPORT 227*53ee8cc1Swenshuai.xi #define CHIP_IP_CA NONSUPPORT 228*53ee8cc1Swenshuai.xi #define CHIP_IP_PCMCIA SUPPORT 229*53ee8cc1Swenshuai.xi #define CHIP_IP_SC SUPPORT 230*53ee8cc1Swenshuai.xi #define CHIP_IP_GPD SUPPORT 231*53ee8cc1Swenshuai.xi #define CHIP_IP_JPEG SUPPORT 232*53ee8cc1Swenshuai.xi #define CHIP_IP_VDEC SUPPORT 233*53ee8cc1Swenshuai.xi #define CHIP_IP_ACE SUPPORT 234*53ee8cc1Swenshuai.xi #define CHIP_IP_DAC NONSUPPORT 235*53ee8cc1Swenshuai.xi #define CHIP_IP_DDC2BI SUPPORT 236*53ee8cc1Swenshuai.xi #define CHIP_IP_DIP SUPPORT 237*53ee8cc1Swenshuai.xi #define CHIP_IP_DLC SUPPORT 238*53ee8cc1Swenshuai.xi #define CHIP_IP_GOP SUPPORT 239*53ee8cc1Swenshuai.xi #define CHIP_IP_HDMITX NONSUPPORT 240*53ee8cc1Swenshuai.xi #define CHIP_IP_MHL SUPPORT 241*53ee8cc1Swenshuai.xi #define CHIP_IP_MVOP SUPPORT 242*53ee8cc1Swenshuai.xi #define CHIP_IP_PNL SUPPORT 243*53ee8cc1Swenshuai.xi #define CHIP_IP_XC SUPPORT 244*53ee8cc1Swenshuai.xi #define CHIP_IP_GFX SUPPORT 245*53ee8cc1Swenshuai.xi #define CHIP_IP_AUDIO SUPPORT 246*53ee8cc1Swenshuai.xi #define CHIP_IP_SERFLASH SUPPORT 247*53ee8cc1Swenshuai.xi 248*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 249*53ee8cc1Swenshuai.xi // Type and Structure 250*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 251*53ee8cc1Swenshuai.xi 252*53ee8cc1Swenshuai.xi 253*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 254*53ee8cc1Swenshuai.xi // Function and Variable 255*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 256*53ee8cc1Swenshuai.xi void CHIP_InitISR(void); 257*53ee8cc1Swenshuai.xi MS_BOOL CHIP_InISRContext(void); 258*53ee8cc1Swenshuai.xi MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb); 259*53ee8cc1Swenshuai.xi MS_BOOL CHIP_DetachISR(InterruptNum eIntNum); 260*53ee8cc1Swenshuai.xi MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum); 261*53ee8cc1Swenshuai.xi MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum); 262*53ee8cc1Swenshuai.xi MS_BOOL CHIP_EnableAllInterrupt(void); 263*53ee8cc1Swenshuai.xi MS_BOOL CHIP_DisableAllInterrupt(void); 264*53ee8cc1Swenshuai.xi MS_BOOL CHIP_DebugIRQ(InterruptNum eIntNum, IrqDebugOpt eIrqDebugOpt); 265*53ee8cc1Swenshuai.xi MS_BOOL CHIP_CompleteIRQ(InterruptNum eIntNum); 266*53ee8cc1Swenshuai.xi 267*53ee8cc1Swenshuai.xi 268*53ee8cc1Swenshuai.xi #ifdef __cplusplus 269*53ee8cc1Swenshuai.xi } 270*53ee8cc1Swenshuai.xi #endif 271*53ee8cc1Swenshuai.xi 272*53ee8cc1Swenshuai.xi #endif // _HAL_CHIP_H_ 273*53ee8cc1Swenshuai.xi 274