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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_CHIP_H_ 96 #define _HAL_CHIP_H_ 97 98 99 100 #ifdef __cplusplus 101 extern "C" 102 { 103 #endif 104 105 //------------------------------------------------------------------------------------------------- 106 // Macro and Define 107 //------------------------------------------------------------------------------------------------- 108 109 typedef enum 110 { 111 E_CHIP_MIU_0 = 0, 112 E_CHIP_MIU_1, 113 E_CHIP_MIU_2, 114 E_CHIP_MIU_3, 115 E_CHIP_MIU_NUM, 116 } CHIP_MIU_ID; 117 118 #define ARM_CLOCK_FREQ 1008000000 119 #define MIPS_CLOCK_FREQ 900000000 120 #define AEON_CLOCK_FREQ 240000000 121 #define XTAL_CLOCK_FREQ 12000000 122 123 #define HAL_MIU0_BASE 0x00000000UL 124 #if defined(__AEONR2__) 125 #define HAL_MIU1_BASE 0x40000000UL // 1512MB 126 #define HAL_MIU2_BASE 0xC0000000UL // 127 #else 128 #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 129 #define HAL_MIU1_BASE 0x80000000UL // 1512MB 130 #define HAL_MIU2_BASE 0x100000000UL // 131 #else 132 #define HAL_MIU1_BASE 0x80000000UL // 1512MB 133 #define HAL_MIU2_BASE 0xC0000000UL // 134 #define HAL_MIU2_BASE2 0x100000000UL // 135 #endif 136 #endif 137 138 #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 139 #define HAL_MIU0_BUS_BASE 0x20000000UL // MIU0 Low 256MB 140 #define HAL_MIU1_BUS_BASE 0x200000000UL // MIU1 Low 256MB MUJI: 0xA0000000UL 141 #define HAL_MIU2_BUS_BASE 0x300000000UL // 64 bit mapping 142 #else 143 #define HAL_MIU0_BUS_BASE 0x20000000UL 144 #define HAL_MIU1_BUS_BASE 0xA0000000UL 145 #define HAL_MIU2_BUS_BASE 0x300000000UL 146 #endif 147 148 #if defined(__AEONR2__) 149 #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < HAL_MIU1_BASE) \ 150 {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 151 else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 152 {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 153 else \ 154 {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} 155 156 #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 157 {PhysAddr = Offset;} \ 158 else if (MiuSel == E_CHIP_MIU_1) \ 159 {PhysAddr = Offset + HAL_MIU1_BASE;} \ 160 else \ 161 {PhysAddr = Offset + HAL_MIU2_BASE;} 162 #else 163 164 #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 165 #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < HAL_MIU1_BASE) \ 166 {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 167 else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 168 {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 169 else \ 170 {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} 171 172 #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 173 {PhysAddr = Offset;} \ 174 else if (MiuSel == E_CHIP_MIU_1) \ 175 {PhysAddr = Offset + HAL_MIU1_BASE;} \ 176 else \ 177 {PhysAddr = Offset + HAL_MIU2_BASE;} 178 #else 179 #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr >= HAL_MIU2_BASE2 && PhysAddr < 0x200000000UL) { \ 180 {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE2;}} else { \ 181 if (PhysAddr < HAL_MIU1_BASE) \ 182 {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 183 else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 184 {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 185 else \ 186 {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} \ 187 } 188 189 #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 190 {PhysAddr = Offset;} \ 191 else if (MiuSel == E_CHIP_MIU_1) \ 192 {PhysAddr = Offset + HAL_MIU1_BASE;} \ 193 else \ 194 {PhysAddr = Offset + HAL_MIU2_BASE;} 195 #endif 196 #endif 197 198 #define SUPPORT TRUE 199 #define NONSUPPORT FALSE 200 201 #define CHIP_IP_MFE SUPPORT 202 #define CHIP_IP_VE SUPPORT 203 #define CHIP_IP_AVD SUPPORT 204 #define CHIP_IP_DEMOD SUPPORT 205 #define CHIP_IP_VBI SUPPORT 206 #define CHIP_IP_VIF SUPPORT 207 #define CHIP_IP_DMX SUPPORT 208 #define CHIP_IP_CEC SUPPORT 209 #define CHIP_IP_MBX SUPPORT 210 #define CHIP_IP_SWI2C SUPPORT 211 #define CHIP_IP_BDMA SUPPORT 212 #define CHIP_IP_CPU SUPPORT 213 #define CHIP_IP_GPIO SUPPORT 214 #define CHIP_IP_HWI2C SUPPORT 215 #define CHIP_IP_IR SUPPORT 216 #define CHIP_IP_MIU SUPPORT 217 #define CHIP_IP_MPIF NONSUPPORT 218 #define CHIP_IP_MSPI SUPPORT 219 #define CHIP_IP_PM SUPPORT 220 #define CHIP_IP_PWM SUPPORT 221 #define CHIP_IP_PWS SUPPORT 222 #define CHIP_IP_RTC SUPPORT 223 #define CHIP_IP_SAR SUPPORT 224 #define CHIP_IP_URDMA SUPPORT 225 #define CHIP_IP_WDT SUPPORT 226 #define CHIP_IP_AESDMA SUPPORT 227 #define CHIP_IP_CA NONSUPPORT 228 #define CHIP_IP_PCMCIA SUPPORT 229 #define CHIP_IP_SC SUPPORT 230 #define CHIP_IP_GPD SUPPORT 231 #define CHIP_IP_JPEG SUPPORT 232 #define CHIP_IP_VDEC SUPPORT 233 #define CHIP_IP_ACE SUPPORT 234 #define CHIP_IP_DAC NONSUPPORT 235 #define CHIP_IP_DDC2BI SUPPORT 236 #define CHIP_IP_DIP SUPPORT 237 #define CHIP_IP_DLC SUPPORT 238 #define CHIP_IP_GOP SUPPORT 239 #define CHIP_IP_HDMITX NONSUPPORT 240 #define CHIP_IP_MHL SUPPORT 241 #define CHIP_IP_MVOP SUPPORT 242 #define CHIP_IP_PNL SUPPORT 243 #define CHIP_IP_XC SUPPORT 244 #define CHIP_IP_GFX SUPPORT 245 #define CHIP_IP_AUDIO SUPPORT 246 #define CHIP_IP_SERFLASH SUPPORT 247 248 //------------------------------------------------------------------------------------------------- 249 // Type and Structure 250 //------------------------------------------------------------------------------------------------- 251 252 253 //------------------------------------------------------------------------------------------------- 254 // Function and Variable 255 //------------------------------------------------------------------------------------------------- 256 void CHIP_InitISR(void); 257 MS_BOOL CHIP_InISRContext(void); 258 MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb); 259 MS_BOOL CHIP_DetachISR(InterruptNum eIntNum); 260 MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum); 261 MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum); 262 MS_BOOL CHIP_EnableAllInterrupt(void); 263 MS_BOOL CHIP_DisableAllInterrupt(void); 264 MS_BOOL CHIP_DebugIRQ(InterruptNum eIntNum, IrqDebugOpt eIrqDebugOpt); 265 MS_BOOL CHIP_CompleteIRQ(InterruptNum eIntNum); 266 267 268 #ifdef __cplusplus 269 } 270 #endif 271 272 #endif // _HAL_CHIP_H_ 273 274