xref: /utopia/UTPA2-700.0.x/mxlib/hal/curry/halCHIP.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi //<MStar Software>
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77*53ee8cc1Swenshuai.xi //<MStar Software>
78*53ee8cc1Swenshuai.xi 
79*53ee8cc1Swenshuai.xi #ifndef _HAL_CHIP_H_
80*53ee8cc1Swenshuai.xi #define _HAL_CHIP_H_
81*53ee8cc1Swenshuai.xi 
82*53ee8cc1Swenshuai.xi #ifdef __cplusplus
83*53ee8cc1Swenshuai.xi extern "C"
84*53ee8cc1Swenshuai.xi {
85*53ee8cc1Swenshuai.xi #endif
86*53ee8cc1Swenshuai.xi 
87*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
88*53ee8cc1Swenshuai.xi //  Macro and Define
89*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
90*53ee8cc1Swenshuai.xi 
91*53ee8cc1Swenshuai.xi typedef enum
92*53ee8cc1Swenshuai.xi {
93*53ee8cc1Swenshuai.xi   E_CHIP_MIU_0 = 0,
94*53ee8cc1Swenshuai.xi   E_CHIP_MIU_1,
95*53ee8cc1Swenshuai.xi   E_CHIP_MIU_2,
96*53ee8cc1Swenshuai.xi   E_CHIP_MIU_3,
97*53ee8cc1Swenshuai.xi   E_CHIP_MIU_NUM,
98*53ee8cc1Swenshuai.xi } CHIP_MIU_ID;
99*53ee8cc1Swenshuai.xi 
100*53ee8cc1Swenshuai.xi #define ARM_CLOCK_FREQ              900000000
101*53ee8cc1Swenshuai.xi #define MIPS_CLOCK_FREQ             12000000    //for FPGA Platform
102*53ee8cc1Swenshuai.xi #define AEON_CLOCK_FREQ             240000000
103*53ee8cc1Swenshuai.xi #define XTAL_CLOCK_FREQ             12000000
104*53ee8cc1Swenshuai.xi 
105*53ee8cc1Swenshuai.xi //* MIU ADDR */
106*53ee8cc1Swenshuai.xi #define HAL_MIU0_BASE               0x00000000UL
107*53ee8cc1Swenshuai.xi #if defined(__AEONR2__)
108*53ee8cc1Swenshuai.xi #define HAL_MIU1_BASE               0x40000000UL // 1512MB
109*53ee8cc1Swenshuai.xi #else
110*53ee8cc1Swenshuai.xi #define HAL_MIU1_BASE               0x80000000UL // 1512MB
111*53ee8cc1Swenshuai.xi #define HAL_MIU2_BASE               0xC0000000UL //
112*53ee8cc1Swenshuai.xi #endif
113*53ee8cc1Swenshuai.xi 
114*53ee8cc1Swenshuai.xi /* BUS ADDR */
115*53ee8cc1Swenshuai.xi #define HAL_MIU0_BUS_BASE           0x20000000UL // MIU0 Low 256MB
116*53ee8cc1Swenshuai.xi #define HAL_MIU1_BUS_BASE           0xC0000000UL // MIU1 Low 256MB
117*53ee8cc1Swenshuai.xi #define HAL_MIU2_BUS_BASE           0xE0000000UL // MIU2 Low 256MB
118*53ee8cc1Swenshuai.xi 
119*53ee8cc1Swenshuai.xi 
120*53ee8cc1Swenshuai.xi #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < HAL_MIU1_BASE) \
121*53ee8cc1Swenshuai.xi                                                         {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \
122*53ee8cc1Swenshuai.xi                                                      else \
123*53ee8cc1Swenshuai.xi                                                          {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;}
124*53ee8cc1Swenshuai.xi 
125*53ee8cc1Swenshuai.xi #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \
126*53ee8cc1Swenshuai.xi                                                         {PhysAddr = Offset;} \
127*53ee8cc1Swenshuai.xi                                                      else \
128*53ee8cc1Swenshuai.xi                                                          {PhysAddr = Offset + HAL_MIU1_BASE;}
129*53ee8cc1Swenshuai.xi 
130*53ee8cc1Swenshuai.xi #define SUPPORT TRUE
131*53ee8cc1Swenshuai.xi #define NONSUPPORT FALSE
132*53ee8cc1Swenshuai.xi 
133*53ee8cc1Swenshuai.xi #define CHIP_IP_MFE SUPPORT
134*53ee8cc1Swenshuai.xi #define CHIP_IP_VE SUPPORT
135*53ee8cc1Swenshuai.xi #define CHIP_IP_AVD SUPPORT
136*53ee8cc1Swenshuai.xi #define CHIP_IP_DEMOD SUPPORT
137*53ee8cc1Swenshuai.xi #define CHIP_IP_VBI SUPPORT
138*53ee8cc1Swenshuai.xi #define CHIP_IP_VIF SUPPORT
139*53ee8cc1Swenshuai.xi #define CHIP_IP_DMX SUPPORT
140*53ee8cc1Swenshuai.xi #define CHIP_IP_CEC SUPPORT
141*53ee8cc1Swenshuai.xi #define CHIP_IP_MBX SUPPORT
142*53ee8cc1Swenshuai.xi #define CHIP_IP_SWI2C SUPPORT
143*53ee8cc1Swenshuai.xi #define CHIP_IP_BDMA SUPPORT
144*53ee8cc1Swenshuai.xi #define CHIP_IP_CPU SUPPORT
145*53ee8cc1Swenshuai.xi #define CHIP_IP_GPIO SUPPORT
146*53ee8cc1Swenshuai.xi #define CHIP_IP_HWI2C SUPPORT
147*53ee8cc1Swenshuai.xi #define CHIP_IP_IR SUPPORT
148*53ee8cc1Swenshuai.xi #define CHIP_IP_MIU SUPPORT
149*53ee8cc1Swenshuai.xi #define CHIP_IP_MPIF NONSUPPORT
150*53ee8cc1Swenshuai.xi #define CHIP_IP_MSPI SUPPORT
151*53ee8cc1Swenshuai.xi #define CHIP_IP_PM SUPPORT
152*53ee8cc1Swenshuai.xi #define CHIP_IP_PWM SUPPORT
153*53ee8cc1Swenshuai.xi #define CHIP_IP_PWS SUPPORT
154*53ee8cc1Swenshuai.xi #define CHIP_IP_RTC SUPPORT
155*53ee8cc1Swenshuai.xi #define CHIP_IP_SAR SUPPORT
156*53ee8cc1Swenshuai.xi #define CHIP_IP_URDMA SUPPORT
157*53ee8cc1Swenshuai.xi #define CHIP_IP_WDT SUPPORT
158*53ee8cc1Swenshuai.xi #define CHIP_IP_AESDMA SUPPORT
159*53ee8cc1Swenshuai.xi #define CHIP_IP_CA NONSUPPORT
160*53ee8cc1Swenshuai.xi #define CHIP_IP_PCMCIA SUPPORT
161*53ee8cc1Swenshuai.xi #define CHIP_IP_SC SUPPORT
162*53ee8cc1Swenshuai.xi #define CHIP_IP_GPD SUPPORT
163*53ee8cc1Swenshuai.xi #define CHIP_IP_JPEG SUPPORT
164*53ee8cc1Swenshuai.xi #define CHIP_IP_VDEC SUPPORT
165*53ee8cc1Swenshuai.xi #define CHIP_IP_ACE SUPPORT
166*53ee8cc1Swenshuai.xi #define CHIP_IP_DAC SUPPORT
167*53ee8cc1Swenshuai.xi #define CHIP_IP_DDC2BI SUPPORT
168*53ee8cc1Swenshuai.xi #define CHIP_IP_DIP SUPPORT
169*53ee8cc1Swenshuai.xi #define CHIP_IP_DLC SUPPORT
170*53ee8cc1Swenshuai.xi #define CHIP_IP_GOP SUPPORT
171*53ee8cc1Swenshuai.xi #define CHIP_IP_HDMITX SUPPORT
172*53ee8cc1Swenshuai.xi #define CHIP_IP_MHL NONSUPPORT
173*53ee8cc1Swenshuai.xi #define CHIP_IP_MVOP SUPPORT
174*53ee8cc1Swenshuai.xi #define CHIP_IP_PNL SUPPORT
175*53ee8cc1Swenshuai.xi #define CHIP_IP_XC SUPPORT
176*53ee8cc1Swenshuai.xi #define CHIP_IP_GFX SUPPORT
177*53ee8cc1Swenshuai.xi #define CHIP_IP_AUDIO SUPPORT
178*53ee8cc1Swenshuai.xi #define CHIP_IP_SERFLASH SUPPORT
179*53ee8cc1Swenshuai.xi 
180*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
181*53ee8cc1Swenshuai.xi //  Type and Structure
182*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
183*53ee8cc1Swenshuai.xi 
184*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
185*53ee8cc1Swenshuai.xi //  Function and Variable
186*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
187*53ee8cc1Swenshuai.xi void    CHIP_InitISR(void);
188*53ee8cc1Swenshuai.xi MS_BOOL CHIP_InISRContext(void);
189*53ee8cc1Swenshuai.xi MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb);
190*53ee8cc1Swenshuai.xi MS_BOOL CHIP_DetachISR(InterruptNum eIntNum);
191*53ee8cc1Swenshuai.xi MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum);
192*53ee8cc1Swenshuai.xi MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum);
193*53ee8cc1Swenshuai.xi MS_BOOL CHIP_EnableAllInterrupt(void);
194*53ee8cc1Swenshuai.xi MS_BOOL CHIP_DisableAllInterrupt(void);
195*53ee8cc1Swenshuai.xi MS_BOOL CHIP_DebugIRQ(InterruptNum eIntNum, IrqDebugOpt eIrqDebugOpt);
196*53ee8cc1Swenshuai.xi MS_BOOL CHIP_CompleteIRQ(InterruptNum eIntNum);
197*53ee8cc1Swenshuai.xi 
198*53ee8cc1Swenshuai.xi 
199*53ee8cc1Swenshuai.xi #ifdef __cplusplus
200*53ee8cc1Swenshuai.xi }
201*53ee8cc1Swenshuai.xi #endif
202*53ee8cc1Swenshuai.xi 
203*53ee8cc1Swenshuai.xi #endif //_HAL_CHIP_H_
204*53ee8cc1Swenshuai.xi 
205