1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78
79 //-------------------------------------------------------------------------------------------------
80 // Include Files
81 //-------------------------------------------------------------------------------------------------
82
83 #if defined (MSOS_TYPE_ECOS)
84
85 #include <cyg/kernel/kapi.h>
86 #include "MsCommon.h"
87 #include "MsOS.h"
88 #include "halIRQTBL.h"
89 #include "halCHIP.h"
90 #include "regCHIP.h"
91 #include "asmCPU.h"
92
93 //-------------------------------------------------------------------------------------------------
94 // Driver Compiler Options
95 //-------------------------------------------------------------------------------------------------
96
97 //-------------------------------------------------------------------------------------------------
98 // Local Defines
99 //-------------------------------------------------------------------------------------------------
100 #define CHIP_LISR_MAX 2 //vector0: IRQ, vector1: FIQ, vector5: Timer INT
101
102 //-------------------------------------------------------------------------------------------------
103 // Local Structures
104 //-------------------------------------------------------------------------------------------------
105 //typedef void (*LISR_Entry) (MS_S32);
106 typedef struct
107 {
108 cyg_handle_t stIntr;
109 cyg_interrupt stIntrInfo;
110
111 } CHIP_LISR_Info;
112
113 typedef struct
114 {
115 MS_BOOL bUsed;
116 MS_BOOL bPending;
117 // MS_BOOL priority;
118 InterruptCb pIntCb;
119
120 } CHIP_HISR_Info;
121
122 //-------------------------------------------------------------------------------------------------
123 // Global Variables
124 //-------------------------------------------------------------------------------------------------
125
126 //-------------------------------------------------------------------------------------------------
127 // Local Variables
128 //-------------------------------------------------------------------------------------------------
129 static CHIP_LISR_Info _LISR_Info[CHIP_LISR_MAX];
130 static MS_BOOL _bInLISR = FALSE;
131
132 static CHIP_HISR_Info _HISR_Info[MS_IRQ_MAX];
133 static MS_BOOL _bInHISR = FALSE;
134
135 //-------------------------------------------------------------------------------------------------
136 // Debug Functions
137 //-------------------------------------------------------------------------------------------------
138
139 //-------------------------------------------------------------------------------------------------
140 // Local Functions
141 //-------------------------------------------------------------------------------------------------
142 MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum);
143
144 // -- Jerry --
145 // Leave these to be chip independent. Different chip can have the opportunities to
146 // revise the priority policy for different interrupts.
147
148 //-------------------------------------------------------------------------------------------------
149 // ISR of IRQ
150 // @param u32VectorNum \b IN: 0: IRQ 1: FIQ
151 // @param u32Data \b IN: argument 3 of cyg_interrupt_create
152 // @return ISR result
153 //-------------------------------------------------------------------------------------------------
_CHIP_LISR0(MS_U32 u32VectorNum,MS_U32 u32Data)154 static MS_U32 _CHIP_LISR0(MS_U32 u32VectorNum, MS_U32 u32Data)
155 {
156 MS_U32 u32Reg;
157 MS_U32 u32Bit;
158 IRQFIQNum eVector;
159 InterruptNum eIntNum;
160
161 u32Reg = 0;
162
163 //in interrupt context
164 _bInLISR = TRUE;
165
166 u32Reg = IRQ_REG(REG_IRQ_PENDING_H);
167 u32Reg <<= 16;
168 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L);
169
170 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
171 {
172 if(u32Bit < 16)
173 {
174 eVector = (IRQFIQNum)(u32Bit + E_IRQL_START);
175 }
176 else
177 {
178 eVector = (IRQFIQNum)((u32Bit-16) + E_IRQH_START);
179 }
180
181 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
182 CHIP_DisableIRQ(eIntNum);
183 if(_HISR_Info[eVector].bUsed)
184 {
185 _HISR_Info[eVector].bPending = TRUE;
186 }
187 u32Reg &= ~(0x01 << u32Bit);
188 }
189
190 u32Reg = 0;
191 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H);
192 u32Reg <<= 16;
193 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L);
194
195 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
196 {
197 if(u32Bit < 16)
198 {
199 eVector = (IRQFIQNum)(u32Bit + E_IRQEXPL_START);
200 }
201 else
202 {
203 eVector = (IRQFIQNum)((u32Bit-16) + E_IRQEXPH_START);
204 }
205
206 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
207 CHIP_DisableIRQ(eIntNum);
208 if(_HISR_Info[eVector].bUsed)
209 {
210 _HISR_Info[eVector].bPending = TRUE;
211 }
212 u32Reg &= ~(0x01 << u32Bit);
213 }
214
215 u32Reg = 0;
216 u32Reg = IRQHYP_REG(REG_IRQHYP_PENDING_H);
217 u32Reg <<= 16;
218 u32Reg |= IRQHYP_REG(REG_IRQHYP_PENDING_L);
219
220 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
221 {
222 if(u32Bit < 16)
223 {
224 eVector = (IRQFIQNum)(u32Bit + E_IRQHYPL_START);
225 }
226 else
227 {
228 eVector = (IRQFIQNum)((u32Bit-16) + E_IRQHYPH_START);
229 }
230
231 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
232 CHIP_DisableIRQ(eIntNum);
233 if(_HISR_Info[eVector].bUsed)
234 {
235 _HISR_Info[eVector].bPending = TRUE;
236 }
237 u32Reg &= ~(0x01 << u32Bit);
238 }
239
240 // Mask this interrupt until the DSR completes.
241 cyg_interrupt_mask(E_INTERRUPT_IRQ); //why mask INT0 -> cause can still be 1 ???
242
243 // Tell the processor that we have received the interrupt.
244 cyg_interrupt_acknowledge(E_INTERRUPT_IRQ);
245
246 _bInLISR = FALSE;
247
248 // Tell the kernel that the ISR processing is done and the DSR needs to be executed next.
249 return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
250 }
251
252 //-------------------------------------------------------------------------------------------------
253 // ISR of FIQ
254 // @param u32VectorNum \b IN: 0: IRQ 1: FIQ
255 // @param u32Data \b IN: argument 3 of cyg_interrupt_create
256 // @return ISR result
257 // @note FIQ - handle interrupt service routine in ISR
258 //-------------------------------------------------------------------------------------------------
_CHIP_LISR1(MS_U32 u32VectorNum,MS_U32 u32Data)259 static MS_U32 _CHIP_LISR1(MS_U32 u32VectorNum, MS_U32 u32Data)
260 {
261 MS_U32 u32Reg;
262 MS_U32 u32Bit;
263 IRQFIQNum eVector;
264 InterruptNum eIntNum;
265
266 //in interrupt context
267 _bInLISR = TRUE;
268
269 u32Reg = 0;
270 u32Reg = IRQ_REG(REG_FIQ_PENDING_H);
271 u32Reg <<= 16;
272 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L);
273
274 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
275 {
276 if(u32Bit < 16)
277 {
278 eVector = (IRQFIQNum)(u32Bit + E_FIQL_START);
279 }
280 else
281 {
282 eVector = (IRQFIQNum)((u32Bit-16) + E_FIQH_START);
283 }
284 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
285 CHIP_DisableIRQ(eIntNum);
286 if(_HISR_Info[eVector].bUsed)
287 {
288 _HISR_Info[eVector].bPending = TRUE;
289 }
290 u32Reg &= ~(0x01 << u32Bit);
291 }
292
293 u32Reg = 0;
294 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H);
295 u32Reg <<=16;
296 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L);
297
298 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
299 {
300 if(u32Bit<16)
301 {
302 eVector = (IRQFIQNum)(u32Bit + E_FIQEXPL_START);
303 }
304 else
305 {
306 eVector = (IRQFIQNum)((u32Bit-16) + E_FIQEXPH_START);
307 }
308 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
309 CHIP_DisableIRQ(eIntNum);
310 if(_HISR_Info[eVector].bUsed)
311 {
312 _HISR_Info[eVector].bPending = TRUE;
313 }
314 u32Reg &= ~(0x1 << u32Bit);
315 }
316
317 u32Reg = 0;
318 u32Reg = IRQHYP_REG(REG_FIQHYP_PENDING_H);
319 u32Reg <<=16;
320 u32Reg |= IRQHYP_REG(REG_FIQHYP_PENDING_L);
321
322 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
323 {
324 if(u32Bit<16)
325 {
326 eVector = (IRQFIQNum)(u32Bit + E_FIQHYPL_START);
327 }
328 else
329 {
330 eVector = (IRQFIQNum)((u32Bit-16) + E_FIQHYPH_START);
331 }
332 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
333 CHIP_DisableIRQ(eIntNum);
334 if(_HISR_Info[eVector].bUsed)
335 {
336 _HISR_Info[eVector].bPending = TRUE;
337 }
338 u32Reg &= ~(0x1 << u32Bit);
339 }
340
341 // Mask this interrupt until the ISR completes.
342 cyg_interrupt_mask(E_INTERRUPT_FIQ);
343
344 // Tell the processor that we have received the interrupt.
345 cyg_interrupt_acknowledge(E_INTERRUPT_FIQ);
346
347 _bInLISR = FALSE;
348 return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);
349 }
350
351 //-------------------------------------------------------------------------------------------------
352 // DSR of IRQ
353 // @param u32VectorNum \b IN: 0: IRQ 1: FIQ
354 // @param u32Count \b IN: # of occurrences
355 // @param u32Data \b IN: argument 3 of cyg_interrupt_create
356 // @return None
357 //-------------------------------------------------------------------------------------------------
_CHIP_HISR0(MS_U32 u32VectorNum,MS_U32 u32Count,MS_U32 u32Data)358 static void _CHIP_HISR0(MS_U32 u32VectorNum, MS_U32 u32Count, MS_U32 u32Data)
359 {
360 InterruptNum i;
361
362 _bInHISR = TRUE; //in interrupt context
363
364 // Process all pending DSRs, then enable relative IRQ again
365 // The following SW processing flow decides the priorities from high to low
366 //for loop later
367 // IRQ H
368 for(i = (InterruptNum) E_IRQL_START; i <= (InterruptNum) E_IRQL_END; i++)
369 {
370 if (_HISR_Info[i].bPending)
371 {
372 _HISR_Info[i].bPending = FALSE;
373 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
374 }
375 }
376 for(i = (InterruptNum) E_IRQH_START; i <= (InterruptNum) E_IRQH_END; i++)
377 {
378 if(_HISR_Info[i].bPending)
379 {
380 _HISR_Info[i].bPending = FALSE;
381 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
382 }
383 }
384
385 for(i = (InterruptNum) E_IRQEXPL_START; i <= (InterruptNum) E_IRQEXPL_END; i++)
386 {
387 if(_HISR_Info[i].bPending)
388 {
389 _HISR_Info[i].bPending = FALSE;
390 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
391 }
392 }
393
394 for(i = (InterruptNum) E_IRQEXPH_START; i <= (InterruptNum) E_IRQEXPH_END; i++)
395 {
396 if(_HISR_Info[i].bPending)
397 {
398 _HISR_Info[i].bPending = FALSE;
399 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
400 }
401 }
402
403 for(i = (InterruptNum) E_IRQHYPL_START; i <= (InterruptNum) E_IRQHYPL_END; i++)
404 {
405 if(_HISR_Info[i].bPending)
406 {
407 _HISR_Info[i].bPending = FALSE;
408 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
409 }
410 }
411
412 for(i = (InterruptNum) E_IRQHYPH_START; i <= (InterruptNum) E_IRQHYPH_END; i++)
413 {
414 if(_HISR_Info[i].bPending)
415 {
416 _HISR_Info[i].bPending = FALSE;
417 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
418 }
419 }
420 _bInHISR = FALSE;
421 // Allow this interrupt to occur again.
422 cyg_interrupt_unmask(E_INTERRUPT_IRQ);
423 }
424
_CHIP_HISR1(MS_U32 u32VectorNum,MS_U32 u32Count,MS_U32 u32Data)425 static void _CHIP_HISR1(MS_U32 u32VectorNum, MS_U32 u32Count, MS_U32 u32Data)
426 {
427 InterruptNum i;
428
429 _bInHISR = TRUE; //in interrupt context
430
431
432 for(i = (InterruptNum) E_FIQL_START; i <=(InterruptNum) E_IRQL_END; i++)
433 {
434 if(_HISR_Info[i].bPending)
435 {
436 _HISR_Info[i].bPending = FALSE;
437 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
438 }
439 }
440 for(i = (InterruptNum) E_FIQH_START; i <= (InterruptNum) E_FIQH_END; i++)
441 {
442 if(_HISR_Info[i].bPending)
443 {
444 _HISR_Info[i].bPending = FALSE;
445 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
446 }
447 }
448
449 for(i = (InterruptNum) E_FIQEXPL_START; i <= (InterruptNum) E_FIQEXPL_END; i++)
450 {
451 if(_HISR_Info[i].bPending)
452 {
453 _HISR_Info[i].bPending = FALSE;
454 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
455 }
456 }
457
458 for(i = (InterruptNum) E_FIQEXPH_START; i<= (InterruptNum) E_FIQEXPH_END; i++)
459 {
460 if(_HISR_Info[i].bPending)
461 {
462 _HISR_Info[i].bPending = FALSE;
463 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
464 }
465 }
466
467 for(i = (InterruptNum) E_FIQHYPL_START; i <= (InterruptNum) E_FIQHYPL_END; i++)
468 {
469 if(_HISR_Info[i].bPending)
470 {
471 _HISR_Info[i].bPending = FALSE;
472 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
473 }
474 }
475
476 for(i = (InterruptNum) E_FIQHYPH_START; i<= (InterruptNum) E_FIQHYPH_END; i++)
477 {
478 if(_HISR_Info[i].bPending)
479 {
480 _HISR_Info[i].bPending = FALSE;
481 _HISR_Info[i].pIntCb((InterruptNum) HWIdx2IntEnum[i]);
482 }
483 }
484
485 //exit interrupt context
486 _bInHISR = FALSE;
487
488 // Allow this interrupt to occur again.
489 cyg_interrupt_unmask(E_INTERRUPT_FIQ);
490 }
491
492 //-------------------------------------------------------------------------------------------------
493 // Global Functions
494 //-------------------------------------------------------------------------------------------------
495
CHIP_EnableIRQ(InterruptNum eIntNum)496 MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum)
497 {
498 MS_BOOL bRet = TRUE;
499 MS_U8 u8VectorIndex = 0;
500
501 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
502
503 if(_HISR_Info[u8VectorIndex].bUsed)
504 {
505 if (u8VectorIndex == E_IRQ_FIQ_ALL)
506 {
507 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF;
508 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF;
509 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF;
510 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF;
511 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF;
512 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF;
513 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF;
514 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF;
515
516 IRQHYP_REG(REG_IRQHYP_MASK_L) &= ~0xFFFF;
517 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF;
518 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF;
519 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF;
520 }
521 else if((u8VectorIndex >= E_IRQL_START) && (u8VectorIndex <= (MS_U8) E_IRQL_END))
522 {
523 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START));
524 }
525 else if((u8VectorIndex >= (MS_U8) E_IRQH_START) && (u8VectorIndex <= (MS_U8) E_IRQH_END))
526 {
527 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START));
528 }
529 else if((u8VectorIndex >= (MS_U8) E_IRQEXPL_START) && (u8VectorIndex <= (MS_U8) E_IRQEXPL_END))
530 {
531 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START));
532 }
533 else if((u8VectorIndex >= (MS_U8) E_IRQEXPH_START) && (u8VectorIndex <= (MS_U8) E_IRQEXPH_END))
534 {
535 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START));
536 }
537 else if((u8VectorIndex >= (MS_U8) E_IRQHYPL_START) && (u8VectorIndex <= (MS_U8) E_IRQHYPL_END))
538 {
539 IRQHYP_REG(REG_IRQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQHYPL_START));
540 }
541 else if((u8VectorIndex >= (MS_U8) E_IRQHYPH_START) && (u8VectorIndex <= (MS_U8) E_IRQHYPH_END))
542 {
543 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START));
544 }
545 else if((u8VectorIndex >= (MS_U8) E_FIQL_START) && (u8VectorIndex <= (MS_U8) E_FIQL_END))
546 {
547 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START));
548 }
549 else if((u8VectorIndex >= (MS_U8) E_FIQH_START) && (u8VectorIndex <= (MS_U8) E_FIQH_END))
550 {
551 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START));
552 }
553 else if((u8VectorIndex >= (MS_U8) E_FIQEXPL_START) && (u8VectorIndex <= (MS_U8) E_FIQEXPL_END))
554 {
555 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START));
556 }
557 else if((u8VectorIndex >= (MS_U8) E_FIQEXPH_START) && (u8VectorIndex <= (MS_U8) E_FIQEXPH_END))
558 {
559 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START));
560 }
561 else if((u8VectorIndex >= (MS_U8) E_FIQHYPL_START) && (u8VectorIndex <= (MS_U8) E_FIQHYPL_END))
562 {
563 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START));
564 }
565 else if((u8VectorIndex >= (MS_U8) E_FIQHYPH_START) && (u8VectorIndex <= (MS_U8) E_FIQHYPH_END))
566 {
567 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START));
568 }
569 }
570 else
571 {
572 bRet = FALSE;
573 }
574
575 return bRet;
576 }
577
CHIP_DisableIRQ(InterruptNum eIntNum)578 MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum)
579 {
580 MS_U8 u8VectorIndex = 0;
581
582 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
583
584 if (u8VectorIndex == E_IRQ_FIQ_ALL)
585 {
586 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF;
587 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF;
588 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF;
589 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF;
590 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF;
591 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF;
592 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF;
593 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF;
594
595 IRQHYP_REG(REG_IRQHYP_MASK_L) |= 0xFFFF;
596 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF;
597 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF;
598 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF;
599 }
600 else if((u8VectorIndex >= E_IRQL_START) && (u8VectorIndex <= (MS_U8) E_IRQL_END))
601 {
602 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START));
603 }
604 else if((u8VectorIndex >= (MS_U8) E_IRQH_START) && (u8VectorIndex <= (MS_U8) E_IRQH_END))
605 {
606 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START));
607 }
608 else if((u8VectorIndex >= (MS_U8) E_IRQEXPL_START) && (u8VectorIndex <= (MS_U8) E_IRQEXPL_END))
609 {
610 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START));
611 }
612 else if((u8VectorIndex >= (MS_U8) E_IRQEXPH_START) && (u8VectorIndex <= (MS_U8) E_IRQEXPH_END))
613 {
614 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START));
615 }
616 else if((u8VectorIndex >= (MS_U8) E_IRQHYPL_START) && (u8VectorIndex <= (MS_U8) E_IRQHYPL_END))
617 {
618 IRQHYP_REG(REG_IRQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQHYPL_START));
619 }
620 else if((u8VectorIndex >= (MS_U8) E_IRQHYPH_START) && (u8VectorIndex <= (MS_U8) E_IRQHYPH_END))
621 {
622 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START));
623 }
624 else if((u8VectorIndex >= (MS_U8) E_FIQL_START) && (u8VectorIndex <= (MS_U8) E_FIQL_END))
625 {
626 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START));
627 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START));
628 }
629 else if((u8VectorIndex >= (MS_U8) E_FIQH_START) && (u8VectorIndex <= (MS_U8) E_FIQH_END))
630 {
631 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START));
632 IRQ_REG(REG_FIQ_CLEAR_H) = (0x01 << (u8VectorIndex - E_FIQH_START));
633 }
634 else if((u8VectorIndex >= (MS_U8) E_FIQEXPL_START) && (u8VectorIndex <= (MS_U8) E_FIQEXPL_END))
635 {
636 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START));
637 IRQ_REG(REG_FIQEXP_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQEXPL_START));
638 }
639 else if((u8VectorIndex >= (MS_U8) E_FIQEXPH_START) && (u8VectorIndex <= (MS_U8) E_FIQEXPH_END))
640 {
641 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START));
642 IRQ_REG(REG_FIQEXP_CLEAR_H) = (0x01 << (u8VectorIndex - E_FIQEXPH_START));
643 }
644 else if((u8VectorIndex >= (MS_U8) E_FIQHYPL_START) && (u8VectorIndex <= (MS_U8) E_FIQHYPL_END))
645 {
646 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START));
647 IRQHYP_REG(REG_FIQHYP_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQHYPL_START));
648 }
649 else if((u8VectorIndex >= (MS_U8) E_FIQHYPH_START) && (u8VectorIndex <= (MS_U8) E_FIQHYPH_END))
650 {
651 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START));
652 IRQHYP_REG(REG_FIQHYP_CLEAR_H) = (0x01 << (u8VectorIndex - E_FIQHYPH_START));
653 }
654 return TRUE;
655 }
656
CHIP_AttachISR(InterruptNum eIntNum,InterruptCb pIntCb)657 MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb)
658 {
659 MS_U8 u8VectorIndex = 0;
660
661 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
662 _HISR_Info[u8VectorIndex].pIntCb = pIntCb;
663 _HISR_Info[u8VectorIndex].bUsed = TRUE;
664
665 return TRUE;
666 }
667
CHIP_DetachISR(InterruptNum eIntNum)668 MS_BOOL CHIP_DetachISR(InterruptNum eIntNum)
669 {
670 MS_U8 u8VectorIndex = 0;
671
672 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
673 _HISR_Info[u8VectorIndex].bUsed = FALSE;
674
675 return TRUE;
676 }
677
CHIP_InISRContext(void)678 MS_BOOL CHIP_InISRContext(void)
679 {
680 if (_bInLISR || _bInHISR)
681 {
682 return TRUE;
683 }
684 else
685 {
686 return FALSE;
687 }
688 }
689
CHIP_InitISR(void)690 void CHIP_InitISR(void)
691 {
692 MS_U32 i = 0;
693
694 HAL_InitIrqTable();
695
696 for(i = 0; i < MS_IRQ_MAX; i++)
697 {
698 _HISR_Info[i].bUsed = FALSE;
699 _HISR_Info[i].bPending = FALSE;
700 }
701
702 // Create the interrupt (0: IRQ register ISR/DSR; 1:FIQ register ISR)
703 cyg_interrupt_create(E_INTERRUPT_IRQ, 0, 0, (cyg_ISR_t *)_CHIP_LISR0, (cyg_DSR_t *)_CHIP_HISR0, &_LISR_Info[0].stIntr, &_LISR_Info[0].stIntrInfo);
704 cyg_interrupt_create(E_INTERRUPT_FIQ, 0, 1, (cyg_ISR_t*)_CHIP_LISR1, (cyg_DSR_t *)_CHIP_HISR1, &_LISR_Info[1].stIntr, &_LISR_Info[1].stIntrInfo);
705
706 // Attach the interrupt created to the vector.
707 cyg_interrupt_attach(_LISR_Info[0].stIntr);
708 cyg_interrupt_attach(_LISR_Info[1].stIntr);
709
710 // Unmask the interrupt we just configured.
711 cyg_interrupt_unmask(E_INTERRUPT_IRQ);
712 cyg_interrupt_unmask(E_INTERRUPT_FIQ);
713 }
714
715
716 //
717 // CHIP_DetectIRQSource will be called by hal_IRQ_handler() of eCospro
718 //
CHIP_DetectIRQSource(void)719 InterruptNum CHIP_DetectIRQSource(void)
720 {
721 MS_U32 u32Reg;
722
723 ////////////////////////
724 // Detect FIQ
725 ////////////////////////
726 u32Reg=0;
727
728 u32Reg = IRQ_REG(REG_FIQ_PENDING_H);
729 u32Reg <<=16;
730 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L);
731
732
733 if(u32Reg != 0)
734 {
735 return E_INTERRUPT_FIQ;
736 }
737
738 u32Reg=0;
739
740 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H);
741 u32Reg <<=16;
742 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L);
743
744
745 if(u32Reg != 0)
746 {
747 return E_INTERRUPT_FIQ;
748 }
749
750 u32Reg=0;
751
752 u32Reg = IRQHYP_REG(REG_FIQHYP_PENDING_H);
753 u32Reg <<=16;
754 u32Reg |= IRQHYP_REG(REG_FIQHYP_PENDING_L);
755
756
757 if(u32Reg != 0)
758 {
759 return E_INTERRUPT_FIQ;
760 }
761
762 ////////////////////////
763 // Detect IRQ
764 ////////////////////////
765 u32Reg=0;
766
767 u32Reg = IRQ_REG(REG_IRQ_PENDING_H);
768 u32Reg <<=16;
769 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L);
770
771 if(u32Reg != 0)
772 {
773 return E_INTERRUPT_IRQ;
774 }
775
776 u32Reg=0;
777
778 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H);
779 u32Reg <<=16;
780 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L);
781
782 if(u32Reg != 0)
783 {
784 return E_INTERRUPT_IRQ;
785 }
786
787 u32Reg=0;
788
789 u32Reg = IRQHYP_REG(REG_IRQHYP_PENDING_H);
790 u32Reg <<=16;
791 u32Reg |= IRQHYP_REG(REG_IRQHYP_PENDING_L);
792
793 if(u32Reg != 0)
794 {
795 return E_INTERRUPT_IRQ;
796 }
797
798 return E_INTERRUPT_IRQ;
799 }
800
801 #endif
802
803 #if defined (MSOS_TYPE_LINUX)
804
805 #include <fcntl.h>
806 #include <errno.h>
807
808 #include <stdlib.h>
809 #include <unistd.h>
810 #include <pthread.h>
811 #include <signal.h>
812 #include <time.h>
813 #include <limits.h>
814 #include <memory.h>
815 #include <sys/ioctl.h>
816 #include <sys/prctl.h>
817
818 #include "MsCommon.h"
819 #include "MsOS.h"
820 #include "halIRQTBL.h"
821 #include "regCHIP.h"
822 #ifdef CONFIG_ENABLE_MENUCONFIG
823 #include "autoconf.h"
824 #endif
825
826 //-------------------------------------------------------------------------------------------------
827 // Driver Compiler Options
828 //-------------------------------------------------------------------------------------------------
829
830 //-------------------------------------------------------------------------------------------------
831 // Local Defines
832 //-------------------------------------------------------------------------------------------------
833 // support 8 vector inerrupts on 4KEc
834 #define CHIP_LISR_MAX 2 //vector0: IRQ, vector1: FRQ, vector5: Timer INT
835 #define MAX_NAME 30 //max thread_name_length
836 #define SEND_ACK 0 //send ack to kernel before executing registered ISR
837
838 #ifdef CONFIG_INT_SPI_MODE
839 #define CHIP_INT_BASE 32 //vector0: IRQ, vector1: FIQ, vector5: Timer INT
840 #else
841 #define CHIP_INT_BASE 128 //vector0: IRQ, vector1: FIQ, vector5: Timer INT
842 #endif
843
844 //-------------------------------------------------------------------------------------------------
845 // Local Structures
846 //-------------------------------------------------------------------------------------------------
847 struct irq_desc
848 {
849 void *driverp;
850 void (*handler)(InterruptNum eIntNum);
851 int irqfd;
852 MS_U16 u16irq;
853 };
854
855 struct pollfd
856 {
857 int fd; /* File descriptor to poll. */
858 short int events; /* Types of events poller cares about. */
859 short int revents; /* Types of events that actually occurred. */
860 };
861
862 typedef struct
863 {
864 MS_BOOL bUsed;
865 MS_BOOL bPending;
866 MS_BOOL bEnable;
867 pthread_t ithr;
868 InterruptCb pIntCb;
869 void *pThreadParam;
870
871 } CHIP_HISR_Info;
872
873 typedef unsigned long int nfds_t;
874 extern int poll (struct pollfd *__fds, nfds_t __nfds, int __timeout);
875
876 //-------------------------------------------------------------------------------------------------
877 // Local Variables
878 //-------------------------------------------------------------------------------------------------
879 static CHIP_HISR_Info _HISR_Info[MS_IRQ_MAX];
880 static MS_BOOL _bInHISR = FALSE;
881 static MS_BOOL _bInLISR = FALSE;
882 //static MS_BOOL _bEnableAll = FALSE;
883
884 //-------------------------------------------------------------------------------------------------
885 // Debug Functions
886 //-------------------------------------------------------------------------------------------------
887
888 //-------------------------------------------------------------------------------------------------
889 // Local Functions
890 //-------------------------------------------------------------------------------------------------
891
892 // -- Jerry --
893 // Leave these to be chip independent. Different chip can have the opportunities to
894 // revise the priority policy for different interrupts.
895
896 //-------------------------------------------------------------------------------------------------
897 // ISR of IRQ
898 // @param u32VectorNum \b IN: 0: IRQ 1: FIQ
899 // @param u32Data \b IN: argument 3 of cyg_interrupt_create
900 // @return ISR result
901 //-------------------------------------------------------------------------------------------------
902 /*
903 static MS_U32 _CHIP_LISR0(MS_U32 u32VectorNum, MS_U32 u32Data)
904 {
905 return FALSE;
906 }
907 */
908
909 //-------------------------------------------------------------------------------------------------
910 // ISR of FIQ
911 // @param u32VectorNum \b IN: 0: IRQ 1: FIQ
912 // @param u32Data \b IN: argument 3 of cyg_interrupt_create
913 // @return ISR result
914 // @note FIQ - handle interrupt service routine in ISR
915 //-------------------------------------------------------------------------------------------------
916 /*
917 static MS_U32 _CHIP_LISR1(MS_U32 u32VectorNum, MS_U32 u32Data)
918 {
919 return FALSE;
920 }
921 */
922
923 //-------------------------------------------------------------------------------------------------
924 // DSR of IRQ
925 // @param u32VectorNum \b IN: 0: IRQ 1: FIQ
926 // @param u32Count \b IN: # of occurrences
927 // @param u32Data \b IN: argument 3 of cyg_interrupt_create
928 // @return None
929 //-------------------------------------------------------------------------------------------------
930 /*
931 static void _CHIP_HISR0(MS_U32 u32VectorNum, MS_U32 u32Count, MS_U32 u32Data)
932 {
933 }
934
935
936 static void _CHIP_HISR1(MS_U32 u32VectorNum, MS_U32 u32Count, MS_U32 u32Data)
937 {
938 }
939 */
940
941 //-------------------------------------------------------------------------------------------------
942 // Global Functions
943 //-------------------------------------------------------------------------------------------------
944
interrupt_thread(void * arg)945 static void *interrupt_thread(void *arg)
946 {
947 struct irq_desc *ip = (struct irq_desc *)arg;
948 int fd = ip->irqfd;
949 int err;
950 struct pollfd PollFd;
951 int irq;
952 char irq_thd_name[MAX_NAME];
953
954 //naming the irq thread
955 irq = ip->u16irq + CHIP_INT_BASE;
956 memset(irq_thd_name, '\0', sizeof(irq_thd_name));
957 snprintf(irq_thd_name, MAX_NAME - 1, "IRQThread_%d", irq);
958 prctl(PR_SET_NAME, (unsigned long) irq_thd_name, NULL, NULL, NULL);
959 memset(irq_thd_name, '\0', sizeof(irq_thd_name));
960 prctl(PR_GET_NAME, (unsigned long) irq_thd_name, NULL, NULL, NULL);
961 //printf("%s\n", irq_thd_name);
962
963 PollFd.fd = fd;
964 PollFd.events = POLLIN;
965 PollFd.revents = 0;
966
967 for(;;)
968 {
969 if(!_HISR_Info[ip->u16irq].bUsed)
970 {
971 //normal exit
972 break;
973 }
974
975
976 err = poll(&PollFd, 1, 100);
977 if (err == -1)
978 {
979 if(errno==EINTR)
980 {
981 continue;
982 }
983 else
984 {
985 printf("IRQ %d ", (ip->u16irq + CHIP_INT_BASE));
986 perror("polling error!!");
987 break;
988 }
989 }
990 else if(PollFd.revents & (0x08 | 0x10 | 0x20)) //<= we can not include poll.h so use 0x08=POLLERR 0x10=POLLHUP 0x20=POLLNVAL
991 {
992 printf("IRQ %d ",(ip->u16irq + CHIP_INT_BASE));
993 perror("polling error!!");
994 break;
995 }
996
997 if(PollFd.revents & POLLIN)
998 {
999 //after successful polling, interrupt had been disable by Kernel
1000 _HISR_Info[(IRQFIQNum)ip->u16irq].bEnable = FALSE;
1001 #if SEND_ACK == 1
1002 int enable = E_IRQ_ACK;
1003 write(fd, &enable, sizeof(enable));
1004 #endif
1005 (void)(ip->handler)((InterruptNum) HWIdx2IntEnum[ip->u16irq]);
1006 }
1007
1008
1009 }
1010
1011 return NULL;
1012 }
1013
CHIP_EnableAllInterrupt(void)1014 MS_BOOL CHIP_EnableAllInterrupt(void)
1015 {
1016 //_bEnableAll = TRUE;
1017 return TRUE;
1018 }
1019
CHIP_DisableAllInterrupt(void)1020 MS_BOOL CHIP_DisableAllInterrupt(void)
1021 {
1022 //_bEnableAll = FALSE;
1023 return TRUE;
1024 }
1025
CHIP_ProcessIRQ(InterruptNum eIntNum,IrqDebugOpt eIrqDebugOpt)1026 static MS_BOOL CHIP_ProcessIRQ(InterruptNum eIntNum, IrqDebugOpt eIrqDebugOpt)
1027 {
1028 int opt = eIrqDebugOpt;
1029 int fd;
1030 MS_U8 u8VectorIndex = 0;
1031
1032 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
1033
1034 if (_HISR_Info[u8VectorIndex].pThreadParam)
1035 {
1036 fd = ((struct irq_desc *)_HISR_Info[u8VectorIndex].pThreadParam)->irqfd;
1037 write(fd, &opt, sizeof(opt));
1038 }
1039
1040 if (eIrqDebugOpt == E_IRQ_ENABLE)
1041 {
1042 _HISR_Info[u8VectorIndex].bEnable = TRUE ;
1043 }
1044 else if (eIrqDebugOpt == E_IRQ_DISABLE)
1045 {
1046 _HISR_Info[u8VectorIndex].bEnable = FALSE ;
1047 }
1048
1049 return TRUE ;
1050 }
1051
CHIP_DebugIRQ(InterruptNum eIntNum,IrqDebugOpt eIrqDebugOpt)1052 MS_BOOL CHIP_DebugIRQ(InterruptNum eIntNum, IrqDebugOpt eIrqDebugOpt)
1053 {
1054 return CHIP_ProcessIRQ(eIntNum, eIrqDebugOpt);
1055 }
1056
CHIP_EnableIRQ(InterruptNum eIntNum)1057 MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum)
1058 {
1059 return CHIP_ProcessIRQ(eIntNum, E_IRQ_ENABLE);
1060 }
1061
CHIP_DisableIRQ(InterruptNum eIntNum)1062 MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum)
1063 {
1064 return CHIP_ProcessIRQ(eIntNum, E_IRQ_DISABLE);
1065 }
1066
CHIP_CompleteIRQ(InterruptNum eIntNum)1067 MS_BOOL CHIP_CompleteIRQ(InterruptNum eIntNum)
1068 {
1069 return CHIP_ProcessIRQ(eIntNum, E_IRQ_COMPLETE);
1070 }
1071
UTL_memset(void * d,int c,size_t n)1072 void *UTL_memset(void *d, int c, size_t n)
1073 {
1074 MS_U8 *pu8Dst = d;
1075 register MS_U32 u32Cnt = n;
1076 register MS_U32 u32Val;
1077 register MS_U32 *pu32Dst;
1078
1079 c &= 0xff;
1080
1081 while ((MS_VIRT)pu8Dst & 3 && u32Cnt)
1082 {
1083 *pu8Dst++ = (MS_U8)c;
1084 u32Cnt--;
1085 }
1086
1087 pu32Dst = (MS_U32 *)pu8Dst;
1088 u32Val = (c << 8) | c;
1089 u32Val = (u32Val << 16) | u32Val;
1090 while(u32Cnt >= 32)
1091 {
1092 pu32Dst[0]= u32Val;
1093 pu32Dst[1]= u32Val;
1094 pu32Dst[2]= u32Val;
1095 pu32Dst[3]= u32Val;
1096 pu32Dst[4]= u32Val;
1097 pu32Dst[5]= u32Val;
1098 pu32Dst[6]= u32Val;
1099 pu32Dst[7]= u32Val;
1100 pu32Dst += 8;
1101 u32Cnt -= 32;
1102 }
1103
1104 while(u32Cnt >= 4)
1105 {
1106 *pu32Dst++ = u32Val;
1107 u32Cnt -= 4;
1108 }
1109
1110 pu8Dst = (MS_U8 *)pu32Dst;
1111 while(u32Cnt)
1112 {
1113 *pu8Dst++ = (MS_U8)c;
1114 u32Cnt--;
1115 }
1116
1117 return d;
1118 }
1119
CHIP_AttachISR(InterruptNum eIntNum,InterruptCb pIntCb)1120 MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb)
1121 {
1122 int fd = 0;
1123 char name[48];
1124 struct irq_desc *idp;
1125 pthread_attr_t attr;
1126 struct sched_param schp;
1127 MS_U8 u8VectorIndex = 0;
1128
1129 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
1130
1131 idp = (struct irq_desc*) malloc(sizeof(*idp));
1132 MS_ASSERT(idp != NULL);
1133 snprintf(name, sizeof(name) - 1, "/proc/irq/%d/irq", (u8VectorIndex + CHIP_INT_BASE));
1134 //printf("name=%s\n", name);
1135
1136 fd = open(name, O_RDWR | O_EXCL);
1137 if (fd < 0)
1138 {
1139 printf("Cannot open interrupt descriptor for irq=%d ", (MS_U16)(u8VectorIndex + CHIP_INT_BASE));
1140 perror("");
1141 free(idp);
1142 return FALSE;
1143 }
1144
1145 idp->irqfd = fd;
1146 idp->u16irq = (MS_U16)u8VectorIndex;
1147 idp->driverp = &(idp->u16irq);
1148 idp->handler = (pIntCb);
1149
1150 UTL_memset(&schp, 0, sizeof(schp));
1151 schp.sched_priority = sched_get_priority_max(SCHED_FIFO);
1152
1153 pthread_attr_init(&attr);
1154 pthread_attr_setschedpolicy(&attr, SCHED_FIFO);
1155 pthread_attr_setscope(&attr, PTHREAD_SCOPE_SYSTEM);
1156 pthread_attr_setschedparam(&attr, &schp);
1157
1158 _HISR_Info[u8VectorIndex].pIntCb = pIntCb;
1159 _HISR_Info[u8VectorIndex].pThreadParam = idp;
1160 _HISR_Info[u8VectorIndex].bUsed = TRUE;
1161 _HISR_Info[u8VectorIndex].bEnable = FALSE;
1162
1163 pthread_create(&_HISR_Info[u8VectorIndex].ithr, &attr, interrupt_thread, idp);
1164
1165 return TRUE;
1166 }
1167
1168
CHIP_DetachISR(InterruptNum eIntNum)1169 MS_BOOL CHIP_DetachISR(InterruptNum eIntNum)
1170 {
1171 MS_U8 u8VectorIndex = 0;
1172
1173 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
1174
1175 if(TRUE == _HISR_Info[u8VectorIndex].bEnable)
1176 {
1177 CHIP_DisableIRQ(eIntNum);
1178 }
1179
1180 _HISR_Info[u8VectorIndex].bUsed = FALSE;
1181
1182 if(_HISR_Info[u8VectorIndex].ithr)
1183 {
1184 int ret;
1185
1186 if((ret=pthread_join(_HISR_Info[u8VectorIndex].ithr, NULL))!=0)
1187 {
1188 printf("IRQ %d ", (MS_U16)(u8VectorIndex + CHIP_INT_BASE));
1189 perror("polling thread destroy failed");
1190 }
1191 else
1192 {
1193 printf("IRQ %d polling thread destroyed\n", (MS_U16)(u8VectorIndex + CHIP_INT_BASE));
1194
1195 }
1196 _HISR_Info[u8VectorIndex].ithr = 0;
1197 }
1198
1199
1200
1201 if(_HISR_Info[u8VectorIndex].pThreadParam)
1202 {
1203 int ret;
1204
1205 if(-1 == ioctl(((struct irq_desc *)_HISR_Info[u8VectorIndex].pThreadParam)->irqfd, 137))
1206 {
1207 printf("%s.%d ioctl fail\n",__FUNCTION__, __LINE__);
1208 }
1209 if((ret = close(((struct irq_desc *) _HISR_Info[u8VectorIndex].pThreadParam)->irqfd)) == -1)
1210 {
1211 printf("IRQ %d ", (MS_U16)(u8VectorIndex + CHIP_INT_BASE));
1212 perror("polling fd close failed");
1213 }
1214 else
1215 {
1216 printf("IRQ %d polling fd closed!!\n", (MS_U16)(u8VectorIndex + CHIP_INT_BASE));
1217 }
1218 free(_HISR_Info[u8VectorIndex].pThreadParam);
1219 _HISR_Info[u8VectorIndex].pThreadParam = NULL;
1220 }
1221
1222 return TRUE;
1223 }
1224
CHIP_InISRContext(void)1225 MS_BOOL CHIP_InISRContext(void)
1226 {
1227 if (_bInLISR || _bInHISR)
1228 {
1229 return TRUE;
1230 }
1231 else
1232 {
1233 return FALSE;
1234 }
1235 }
1236
CHIP_InitISR(void)1237 void CHIP_InitISR(void)
1238 {
1239 MS_U16 i = 0;
1240
1241 HAL_InitIrqTable();
1242
1243 for(i = 0; i < MS_IRQ_MAX; i++)
1244 {
1245 _HISR_Info[i].bUsed = 0;
1246 _HISR_Info[i].bPending = 0;
1247 _HISR_Info[i].bEnable = 0;
1248 _HISR_Info[i].ithr = 0;
1249 _HISR_Info[i].pIntCb = 0;
1250 _HISR_Info[i].pThreadParam = NULL;
1251 }
1252
1253 //printf("+pthread_mutex_init\n");
1254 //pthread_mutex_init(&_HISR_Info,NULL);
1255 //printf("-CHIP_InitISR\n");
1256 }
1257
1258 #endif
1259
1260 #if defined (MSOS_TYPE_UCOS)
1261
1262 #include "MsCommon.h"
1263 #include "MsOS.h"
1264 #include "halIRQTBL.h"
1265 #include "halCHIP.h"
1266 #include "regCHIP.h"
1267 #include "asmCPU.h"
1268 #include "ucos_ii.h"
1269
1270 //-------------------------------------------------------------------------------------------------
1271 // Driver Compiler Options
1272 //-------------------------------------------------------------------------------------------------
1273
1274 //-------------------------------------------------------------------------------------------------
1275 // Local Defines
1276 //-------------------------------------------------------------------------------------------------
1277 #define CHIP_LISR_MAX 2 //vector0: IRQ, vector1: FIQ, vector5: Timer INT
1278
1279 //-------------------------------------------------------------------------------------------------
1280 // Local Structures
1281 //-------------------------------------------------------------------------------------------------
1282
1283 typedef struct
1284 {
1285 MS_BOOL bUsed;
1286 MS_BOOL bPending;
1287 InterruptCb pIntCb;
1288 } CHIP_HISR_Info;
1289
1290 //-------------------------------------------------------------------------------------------------
1291 // Global Variables
1292 //-------------------------------------------------------------------------------------------------
1293
1294 //-------------------------------------------------------------------------------------------------
1295 // Local Variables
1296 //-------------------------------------------------------------------------------------------------
1297 static CHIP_HISR_Info _HISR_Info[MS_IRQ_MAX];
1298 static MS_BOOL _bInHISR = FALSE;
1299
1300 //-------------------------------------------------------------------------------------------------
1301 // Debug Functions
1302 //-------------------------------------------------------------------------------------------------
1303
1304 //-------------------------------------------------------------------------------------------------
1305 // Local Functions
1306 //-------------------------------------------------------------------------------------------------
1307 MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum);
1308
1309 // -- Jerry --
1310 // Leave these to be chip independent. Different chip can have the opportunities to
1311 // revise the priority policy for different interrupts.
1312
1313 //
1314 // _CHIP_DetectIRQSource will be called by _CHIP_HISR0
1315 //
_CHIP_DetectIRQSource(void)1316 InterruptNum _CHIP_DetectIRQSource(void)
1317 {
1318 MS_U32 u32Reg;
1319
1320 ////////////////////////
1321 // Detect FIQ
1322 ////////////////////////
1323 u32Reg=0;
1324
1325 u32Reg = IRQ_REG(REG_FIQ_PENDING_H);
1326 u32Reg <<=16;
1327 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L);
1328
1329
1330 if(u32Reg != 0)
1331 {
1332 return E_INTERRUPT_FIQ;
1333 }
1334
1335 u32Reg=0;
1336
1337 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H);
1338 u32Reg <<=16;
1339 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L);
1340
1341
1342 if(u32Reg != 0)
1343 {
1344 return E_INTERRUPT_FIQ;
1345 }
1346
1347 u32Reg=0;
1348
1349 u32Reg = IRQHYP_REG(REG_FIQHYP_PENDING_H);
1350 u32Reg <<=16;
1351 u32Reg |= IRQHYP_REG(REG_FIQHYP_PENDING_L);
1352
1353
1354 if(u32Reg != 0)
1355 {
1356 return E_INTERRUPT_FIQ;
1357 }
1358
1359 ////////////////////////
1360 // Detect IRQ
1361 ////////////////////////
1362 u32Reg=0;
1363
1364 u32Reg = IRQ_REG(REG_IRQ_PENDING_H);
1365 u32Reg <<=16;
1366 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L);
1367
1368 if(u32Reg != 0)
1369 {
1370 return E_INTERRUPT_IRQ;
1371 }
1372
1373 u32Reg=0;
1374
1375 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H);
1376 u32Reg <<=16;
1377 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L);
1378
1379 if(u32Reg != 0)
1380 {
1381 return E_INTERRUPT_IRQ;
1382 }
1383
1384 u32Reg=0;
1385
1386 u32Reg = IRQHYP_REG(REG_IRQHYP_PENDING_H);
1387 u32Reg <<=16;
1388 u32Reg |= IRQHYP_REG(REG_IRQHYP_PENDING_L);
1389
1390 if(u32Reg != 0)
1391 {
1392 return E_INTERRUPT_IRQ;
1393 }
1394
1395 return E_INTERRUPT_IRQ;
1396 }
1397
__CHIP_HISR1(MS_U32 u32VectorNum,MS_U32 u32Data)1398 void __CHIP_HISR1(MS_U32 u32VectorNum, MS_U32 u32Data)
1399 {
1400 MS_U32 u32Reg;
1401 MS_U32 u32Bit;
1402 IRQFIQNum eVector;
1403 InterruptNum eIntNum;
1404
1405 //in interrupt context
1406 #if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
1407 OS_CPU_SR cpu_sr = 0;
1408 #endif
1409
1410 _bInHISR = TRUE; //in interrupt context
1411
1412 u32Reg = 0;
1413 u32Reg = IRQ_REG(REG_FIQ_PENDING_H);
1414 u32Reg <<= 16;
1415 u32Reg |= IRQ_REG(REG_FIQ_PENDING_L);
1416
1417 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
1418 {
1419 if(u32Bit < 16)
1420 {
1421 eVector = (IRQFIQNum)(u32Bit + E_FIQL_START);
1422 }
1423 else
1424 {
1425 eVector = (IRQFIQNum)((u32Bit-16) + E_FIQH_START);
1426 }
1427 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
1428 CHIP_DisableIRQ(eIntNum);
1429 if(_HISR_Info[eVector].bUsed)
1430 {
1431 _HISR_Info[eVector].bPending = FALSE;
1432 _HISR_Info[eVector].pIntCb((InterruptNum)eIntNum);
1433 }
1434 u32Reg &= ~(0x01 << u32Bit);
1435 }
1436
1437 u32Reg = 0;
1438 u32Reg = IRQ_REG(REG_FIQEXP_PENDING_H);
1439 u32Reg <<=16;
1440 u32Reg |= IRQ_REG(REG_FIQEXP_PENDING_L);
1441
1442 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
1443 {
1444 if(u32Bit<16)
1445 {
1446 eVector = (IRQFIQNum)(u32Bit + E_FIQEXPL_START);
1447 }
1448 else
1449 {
1450 eVector = (IRQFIQNum)((u32Bit-16) + E_FIQEXPH_START);
1451 }
1452 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
1453 CHIP_DisableIRQ(eIntNum);
1454 if(_HISR_Info[eVector].bUsed)
1455 {
1456 _HISR_Info[eVector].bPending = FALSE;
1457 _HISR_Info[eVector].pIntCb((InterruptNum)eIntNum);
1458 }
1459 u32Reg &= ~(0x1 << u32Bit);
1460 }
1461
1462 u32Reg = 0;
1463 u32Reg = IRQHYP_REG(REG_FIQHYP_PENDING_H);
1464 u32Reg <<=16;
1465 u32Reg |= IRQHYP_REG(REG_FIQHYP_PENDING_L);
1466
1467 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
1468 {
1469 if(u32Bit<16)
1470 {
1471 eVector = (IRQFIQNum)(u32Bit + E_FIQHYPL_START);
1472 }
1473 else
1474 {
1475 eVector = (IRQFIQNum)((u32Bit-16) + E_FIQHYPH_START);
1476 }
1477 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
1478 CHIP_DisableIRQ(eIntNum);
1479 if(_HISR_Info[eVector].bUsed)
1480 {
1481 _HISR_Info[eVector].bPending = FALSE;
1482 _HISR_Info[eVector].pIntCb((InterruptNum)eIntNum);
1483 }
1484 u32Reg &= ~(0x1 << u32Bit);
1485 }
1486
1487 //exit interrupt context
1488 _bInHISR = FALSE;
1489 }
1490
1491
1492
1493 //-------------------------------------------------------------------------------------------------
1494 // DSR of IRQ
1495 // @param u32VectorNum \b IN: 0: IRQ 1: FIQ
1496 // @param u32Count \b IN: # of occurrences
1497 // @param u32Data \b IN: argument 3 of cyg_interrupt_create
1498 // @return None
1499 //-------------------------------------------------------------------------------------------------
_CHIP_HISR0(MS_U32 u32VectorNum,MS_U32 u32Data)1500 void _CHIP_HISR0(MS_U32 u32VectorNum, MS_U32 u32Data)
1501 {
1502 MS_U32 u32Reg;
1503 MS_U32 u32Bit;
1504 IRQFIQNum eVector;
1505 InterruptNum eIntNum;
1506
1507 #if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
1508 OS_CPU_SR cpu_sr = 0;
1509 #endif
1510
1511 OS_ENTER_CRITICAL();
1512 if (_CHIP_DetectIRQSource()==E_INTERRUPT_IRQ)
1513 {
1514 _bInHISR = TRUE; //in interrupt context
1515
1516 u32Reg = 0;
1517 u32Reg = IRQ_REG(REG_IRQ_PENDING_H);
1518 u32Reg <<= 16;
1519 u32Reg |= IRQ_REG(REG_IRQ_PENDING_L);
1520
1521 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
1522 {
1523 if(u32Bit < 16)
1524 {
1525 eVector = (IRQFIQNum)(u32Bit + E_IRQL_START);
1526 }
1527 else
1528 {
1529 eVector = (IRQFIQNum)((u32Bit-16) + E_IRQH_START);
1530 }
1531
1532 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
1533 CHIP_DisableIRQ(eIntNum);
1534 if(_HISR_Info[eVector].bUsed)
1535 {
1536 _HISR_Info[eVector].bPending = FALSE;
1537 _HISR_Info[eVector].pIntCb((InterruptNum)eIntNum);
1538 }
1539 u32Reg &= ~(0x01 << u32Bit);
1540 }
1541
1542 u32Reg = 0;
1543 u32Reg = IRQ_REG(REG_IRQEXP_PENDING_H);
1544 u32Reg <<= 16;
1545 u32Reg |= IRQ_REG(REG_IRQEXP_PENDING_L);
1546
1547 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
1548 {
1549 if(u32Bit < 16)
1550 {
1551 eVector = (IRQFIQNum)(u32Bit + E_IRQEXPL_START);
1552 }
1553 else
1554 {
1555 eVector = (IRQFIQNum)((u32Bit-16) + E_IRQEXPH_START);
1556 }
1557
1558 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
1559 CHIP_DisableIRQ(eIntNum);
1560 if(_HISR_Info[eVector].bUsed)
1561 {
1562 _HISR_Info[eVector].bPending = FALSE;
1563 _HISR_Info[eVector].pIntCb((InterruptNum)eIntNum);
1564 }
1565 u32Reg &= ~(0x01 << u32Bit);
1566 }
1567
1568 u32Reg = 0;
1569 u32Reg = IRQHYP_REG(REG_IRQHYP_PENDING_H);
1570 u32Reg <<= 16;
1571 u32Reg |= IRQHYP_REG(REG_IRQHYP_PENDING_L);
1572
1573 while(32 != (u32Bit = MAsm_CPU_GetTrailOne(u32Reg)))
1574 {
1575 if(u32Bit < 16)
1576 {
1577 eVector = (IRQFIQNum)(u32Bit + E_IRQHYPL_START);
1578 }
1579 else
1580 {
1581 eVector = (IRQFIQNum)((u32Bit-16) + E_IRQHYPH_START);
1582 }
1583
1584 eIntNum = (InterruptNum) HWIdx2IntEnum[eVector];
1585 CHIP_DisableIRQ(eIntNum);
1586 if(_HISR_Info[eVector].bUsed)
1587 {
1588 _HISR_Info[eVector].bPending = FALSE;
1589 _HISR_Info[eVector].pIntCb((InterruptNum)eIntNum);
1590 }
1591 u32Reg &= ~(0x01 << u32Bit);
1592 }
1593
1594 _bInHISR = FALSE;
1595 }
1596 else if (_CHIP_DetectIRQSource()==E_INTERRUPT_FIQ)
1597 {
1598 __CHIP_HISR1(u32VectorNum,u32Data);
1599 }
1600 OS_EXIT_CRITICAL();
1601 }
1602
_CHIP_HISR1(MS_U32 u32VectorNum,MS_U32 u32Data)1603 void _CHIP_HISR1(MS_U32 u32VectorNum, MS_U32 u32Data)
1604 {
1605 //in interrupt context
1606 #if OS_CRITICAL_METHOD == 3 /* Allocate storage for CPU status register */
1607 OS_CPU_SR cpu_sr = 0;
1608 #endif
1609 OS_ENTER_CRITICAL();
1610 __CHIP_HISR1(u32VectorNum,u32Data);
1611 //exit interrupt context
1612 OS_EXIT_CRITICAL();
1613 }
1614
1615 //-------------------------------------------------------------------------------------------------
1616 // Global Functions
1617 //-------------------------------------------------------------------------------------------------
1618
CHIP_EnableIRQ(InterruptNum eIntNum)1619 MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum)
1620 {
1621 MS_BOOL bRet = TRUE;
1622 MS_U8 u8VectorIndex = 0;
1623
1624 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
1625
1626 if(_HISR_Info[u8VectorIndex].bUsed)
1627 {
1628 if (u8VectorIndex == E_IRQ_FIQ_ALL)
1629 {
1630 IRQ_REG(REG_IRQ_MASK_L) &= ~0xFFFF;
1631 IRQ_REG(REG_IRQ_MASK_H) &= ~0xFFFF;
1632 IRQ_REG(REG_IRQEXP_MASK_L) &= ~0xFFFF;
1633 IRQ_REG(REG_IRQEXP_MASK_H) &= ~0xFFFF;
1634 IRQ_REG(REG_FIQ_MASK_L) &= ~0xFFFF;
1635 IRQ_REG(REG_FIQ_MASK_H) &= ~0xFFFF;
1636 IRQ_REG(REG_FIQEXP_MASK_L) &= ~0xFFFF;
1637 IRQ_REG(REG_FIQEXP_MASK_H) &= ~0xFFFF;
1638
1639 IRQHYP_REG(REG_IRQHYP_MASK_L) &= ~0xFFFF;
1640 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~0xFFFF;
1641 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~0xFFFF;
1642 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~0xFFFF;
1643 }
1644 else if((u8VectorIndex >= E_IRQL_START) && (u8VectorIndex <= (MS_U8) E_IRQL_END))
1645 {
1646 IRQ_REG(REG_IRQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQL_START));
1647 }
1648 else if((u8VectorIndex >= (MS_U8) E_IRQH_START) && (u8VectorIndex <= (MS_U8) E_IRQH_END))
1649 {
1650 IRQ_REG(REG_IRQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQH_START));
1651 }
1652 else if((u8VectorIndex >= (MS_U8) E_IRQEXPL_START) && (u8VectorIndex <= (MS_U8) E_IRQEXPL_END))
1653 {
1654 IRQ_REG(REG_IRQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQEXPL_START));
1655 }
1656 else if((u8VectorIndex >= (MS_U8) E_IRQEXPH_START) && (u8VectorIndex <= (MS_U8) E_IRQEXPH_END))
1657 {
1658 IRQ_REG(REG_IRQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQEXPH_START));
1659 }
1660 else if((u8VectorIndex >= (MS_U8) E_IRQHYPL_START) && (u8VectorIndex <= (MS_U8) E_IRQHYPL_END))
1661 {
1662 IRQHYP_REG(REG_IRQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_IRQHYPL_START));
1663 }
1664 else if((u8VectorIndex >= (MS_U8) E_IRQHYPH_START) && (u8VectorIndex <= (MS_U8) E_IRQHYPH_END))
1665 {
1666 IRQHYP_REG(REG_IRQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_IRQHYPH_START));
1667 }
1668 else if((u8VectorIndex >= (MS_U8) E_FIQL_START) && (u8VectorIndex <= (MS_U8) E_FIQL_END))
1669 {
1670 IRQ_REG(REG_FIQ_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQL_START));
1671 }
1672 else if((u8VectorIndex >= (MS_U8) E_FIQH_START) && (u8VectorIndex <= (MS_U8) E_FIQH_END))
1673 {
1674 IRQ_REG(REG_FIQ_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQH_START));
1675 }
1676 else if((u8VectorIndex >= (MS_U8) E_FIQEXPL_START) && (u8VectorIndex <= (MS_U8) E_FIQEXPL_END))
1677 {
1678 IRQ_REG(REG_FIQEXP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQEXPL_START));
1679 }
1680 else if((u8VectorIndex >= (MS_U8) E_FIQEXPH_START) && (u8VectorIndex <= (MS_U8) E_FIQEXPH_END))
1681 {
1682 IRQ_REG(REG_FIQEXP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQEXPH_START));
1683 }
1684 else if((u8VectorIndex >= (MS_U8) E_FIQHYPL_START) && (u8VectorIndex <= (MS_U8) E_FIQHYPL_END))
1685 {
1686 IRQHYP_REG(REG_FIQHYP_MASK_L) &= ~(0x01 << (u8VectorIndex - E_FIQHYPL_START));
1687 }
1688 else if((u8VectorIndex >= (MS_U8) E_FIQHYPH_START) && (u8VectorIndex <= (MS_U8) E_FIQHYPH_END))
1689 {
1690 IRQHYP_REG(REG_FIQHYP_MASK_H) &= ~(0x01 << (u8VectorIndex - E_FIQHYPH_START));
1691 }
1692 }
1693 else
1694 {
1695 bRet = FALSE;
1696 }
1697
1698 return bRet;
1699 }
1700
CHIP_DisableIRQ(InterruptNum eIntNum)1701 MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum)
1702 {
1703 MS_U8 u8VectorIndex = 0;
1704
1705 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
1706
1707 if (u8VectorIndex == E_IRQ_FIQ_ALL)
1708 {
1709 IRQ_REG(REG_IRQ_MASK_L) |= 0xFFFF;
1710 IRQ_REG(REG_IRQ_MASK_H) |= 0xFFFF;
1711 IRQ_REG(REG_IRQEXP_MASK_L) |= 0xFFFF;
1712 IRQ_REG(REG_IRQEXP_MASK_H) |= 0xFFFF;
1713 IRQ_REG(REG_FIQ_MASK_L) |= 0xFFFF;
1714 IRQ_REG(REG_FIQ_MASK_H) |= 0xFFFF;
1715 IRQ_REG(REG_FIQEXP_MASK_L) |= 0xFFFF;
1716 IRQ_REG(REG_FIQEXP_MASK_H) |= 0xFFFF;
1717
1718 IRQHYP_REG(REG_IRQHYP_MASK_L) |= 0xFFFF;
1719 IRQHYP_REG(REG_IRQHYP_MASK_H) |= 0xFFFF;
1720 IRQHYP_REG(REG_FIQHYP_MASK_L) |= 0xFFFF;
1721 IRQHYP_REG(REG_FIQHYP_MASK_H) |= 0xFFFF;
1722 }
1723 else if((u8VectorIndex >= E_IRQL_START) && (u8VectorIndex <= (MS_U8) E_IRQL_END))
1724 {
1725 IRQ_REG(REG_IRQ_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQL_START));
1726 }
1727 else if((u8VectorIndex >= (MS_U8) E_IRQH_START) && (u8VectorIndex <= (MS_U8) E_IRQH_END))
1728 {
1729 IRQ_REG(REG_IRQ_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQH_START));
1730 }
1731 else if((u8VectorIndex >= (MS_U8) E_IRQEXPL_START) && (u8VectorIndex <= (MS_U8) E_IRQEXPL_END))
1732 {
1733 IRQ_REG(REG_IRQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQEXPL_START));
1734 }
1735 else if((u8VectorIndex >= (MS_U8) E_IRQEXPH_START) && (u8VectorIndex <= (MS_U8) E_IRQEXPH_END))
1736 {
1737 IRQ_REG(REG_IRQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQEXPH_START));
1738 }
1739 else if((u8VectorIndex >= (MS_U8) E_IRQHYPL_START) && (u8VectorIndex <= (MS_U8) E_IRQHYPL_END))
1740 {
1741 IRQHYP_REG(REG_IRQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_IRQHYPL_START));
1742 }
1743 else if((u8VectorIndex >= (MS_U8) E_IRQHYPH_START) && (u8VectorIndex <= (MS_U8) E_IRQHYPH_END))
1744 {
1745 IRQHYP_REG(REG_IRQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_IRQHYPH_START));
1746 }
1747 else if((u8VectorIndex >= (MS_U8) E_FIQL_START) && (u8VectorIndex <= (MS_U8) E_FIQL_END))
1748 {
1749 IRQ_REG(REG_FIQ_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQL_START));
1750 IRQ_REG(REG_FIQ_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQL_START));
1751 }
1752 else if((u8VectorIndex >= (MS_U8) E_FIQH_START) && (u8VectorIndex <= (MS_U8) E_FIQH_END))
1753 {
1754 IRQ_REG(REG_FIQ_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQH_START));
1755 IRQ_REG(REG_FIQ_CLEAR_H) = (0x01 << (u8VectorIndex - E_FIQH_START));
1756 }
1757 else if((u8VectorIndex >= (MS_U8) E_FIQEXPL_START) && (u8VectorIndex <= (MS_U8) E_FIQEXPL_END))
1758 {
1759 IRQ_REG(REG_FIQEXP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQEXPL_START));
1760 IRQ_REG(REG_FIQEXP_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQEXPL_START));
1761 }
1762 else if((u8VectorIndex >= (MS_U8) E_FIQEXPH_START) && (u8VectorIndex <= (MS_U8) E_FIQEXPH_END))
1763 {
1764 IRQ_REG(REG_FIQEXP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQEXPH_START));
1765 IRQ_REG(REG_FIQEXP_CLEAR_H) = (0x01 << (u8VectorIndex - E_FIQEXPH_START));
1766 }
1767 else if((u8VectorIndex >= (MS_U8) E_FIQHYPL_START) && (u8VectorIndex <= (MS_U8) E_FIQHYPL_END))
1768 {
1769 IRQHYP_REG(REG_FIQHYP_MASK_L) |= (0x01 << (u8VectorIndex - E_FIQHYPL_START));
1770 IRQHYP_REG(REG_FIQHYP_CLEAR_L) = (0x01 << (u8VectorIndex - E_FIQHYPL_START));
1771 }
1772 else if((u8VectorIndex >= (MS_U8) E_FIQHYPH_START) && (u8VectorIndex <= (MS_U8) E_FIQHYPH_END))
1773 {
1774 IRQHYP_REG(REG_FIQHYP_MASK_H) |= (0x01 << (u8VectorIndex - E_FIQHYPH_START));
1775 IRQHYP_REG(REG_FIQHYP_CLEAR_H) = (0x01 << (u8VectorIndex - E_FIQHYPH_START));
1776 }
1777 return TRUE;
1778 }
1779
CHIP_AttachISR(InterruptNum eIntNum,InterruptCb pIntCb)1780 MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb)
1781 {
1782 MS_U8 u8VectorIndex = 0;
1783
1784 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
1785 _HISR_Info[u8VectorIndex].pIntCb = pIntCb;
1786 _HISR_Info[u8VectorIndex].bUsed = TRUE;
1787
1788 return TRUE;
1789 }
1790
CHIP_DetachISR(InterruptNum eIntNum)1791 MS_BOOL CHIP_DetachISR(InterruptNum eIntNum)
1792 {
1793 MS_U8 u8VectorIndex = 0;
1794
1795 u8VectorIndex = (MS_U8)IntEnum2HWIdx[eIntNum];
1796 _HISR_Info[u8VectorIndex].bUsed = FALSE;
1797
1798 return TRUE;
1799 }
1800
CHIP_InISRContext(void)1801 MS_BOOL CHIP_InISRContext(void)
1802 {
1803 if (0 < OSIntNesting)
1804 {
1805 if (FALSE == _bInHISR)
1806 {
1807 printf("[%s][%d] bad status maybe\n", __FUNCTION__, __LINE__);
1808 *((int*)0)= 0;
1809 }
1810 }
1811 else
1812 {
1813 if (TRUE == _bInHISR)
1814 {
1815 printf("[%s][%d] bad status maybe\n", __FUNCTION__, __LINE__);
1816 *((int*)0)= 0;
1817 }
1818 }
1819 return _bInHISR;
1820 }
1821
CHIP_InitISR(void)1822 void CHIP_InitISR(void)
1823 {
1824 MS_U32 i = 0;
1825
1826 HAL_InitIrqTable();
1827
1828 for(i = 0; i < MS_IRQ_MAX; i++)
1829 {
1830 _HISR_Info[i].bUsed = FALSE;
1831 _HISR_Info[i].bPending = FALSE;
1832 }
1833 }
1834
1835 #endif // #if defined (MSOS_TYPE_UCOS)
1836
1837