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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_CHIP_H_ 96 #define _HAL_CHIP_H_ 97 98 99 100 #ifdef __cplusplus 101 extern "C" 102 { 103 #endif 104 105 //------------------------------------------------------------------------------------------------- 106 // Macro and Define 107 //------------------------------------------------------------------------------------------------- 108 109 typedef enum 110 { 111 E_CHIP_MIU_0 = 0, 112 E_CHIP_MIU_1, 113 E_CHIP_MIU_2, 114 E_CHIP_MIU_3, 115 E_CHIP_MIU_NUM, 116 } CHIP_MIU_ID; 117 118 //[CHIP][HAL][005] Set default CPU clock [START] 119 #define ARM_CLOCK_FREQ 1008000000 120 #define MIPS_CLOCK_FREQ 900000000 121 #define AEON_CLOCK_FREQ 240000000 122 #define XTAL_CLOCK_FREQ 12000000 123 //[CHIP][HAL][005] Set default CPU clock [END] 124 125 //[CHIP][HAL][006] Set default physical address of MIU [START] 126 #define HAL_MIU0_BASE 0x00000000UL 127 #if defined(__AEONR2__) 128 #define HAL_MIU1_BASE 0x40000000UL // 1512MB 129 #define HAL_MIU2_BASE 0xC0000000UL // 130 #else 131 #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 132 #define HAL_MIU1_BASE 0x80000000UL // 1512MB 133 #define HAL_MIU2_BASE 0x100000000UL // 134 #else 135 #define HAL_MIU1_BASE 0x80000000UL // 1512MB 136 #define HAL_MIU2_BASE 0xC0000000UL // 137 #define HAL_MIU2_BASE2 0x100000000UL // 138 #endif 139 #endif 140 141 #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 142 #define HAL_MIU0_BUS_BASE 0x20000000UL // MIU0 Low 256MB 143 #define HAL_MIU1_BUS_BASE 0x200000000UL // MIU1 Low 256MB MUJI: 0xA0000000UL 144 #define HAL_MIU2_BUS_BASE 0x300000000UL // 64 bit mapping 145 #else 146 #define HAL_MIU0_BUS_BASE 0x20000000UL 147 #define HAL_MIU1_BUS_BASE 0xA0000000UL 148 #define HAL_MIU2_BUS_BASE 0x300000000UL 149 #endif 150 //[CHIP][HAL][006] Set default physical address of MIU [END] 151 152 #if defined(__AEONR2__) 153 #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < HAL_MIU1_BASE) \ 154 {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 155 else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 156 {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 157 else \ 158 {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} 159 160 #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 161 {PhysAddr = Offset;} \ 162 else if (MiuSel == E_CHIP_MIU_1) \ 163 {PhysAddr = Offset + HAL_MIU1_BASE;} \ 164 else \ 165 {PhysAddr = Offset + HAL_MIU2_BASE;} 166 #else 167 168 #ifdef CONFIG_MIU_64BIT_DOMAIN_SEL 169 #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr < HAL_MIU1_BASE) \ 170 {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 171 else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 172 {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 173 else \ 174 {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} 175 176 #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 177 {PhysAddr = Offset;} \ 178 else if (MiuSel == E_CHIP_MIU_1) \ 179 {PhysAddr = Offset + HAL_MIU1_BASE;} \ 180 else \ 181 {PhysAddr = Offset + HAL_MIU2_BASE;} 182 #else 183 #define _phy_to_miu_offset(MiuSel, Offset, PhysAddr) if (PhysAddr >= HAL_MIU2_BASE2 && PhysAddr < 0x200000000UL) { \ 184 {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE2;}} else { \ 185 if (PhysAddr < HAL_MIU1_BASE) \ 186 {MiuSel = E_CHIP_MIU_0; Offset = PhysAddr;} \ 187 else if ((PhysAddr >= HAL_MIU1_BASE) && (PhysAddr < HAL_MIU2_BASE)) \ 188 {MiuSel = E_CHIP_MIU_1; Offset = PhysAddr - HAL_MIU1_BASE;} \ 189 else \ 190 {MiuSel = E_CHIP_MIU_2; Offset = PhysAddr - HAL_MIU2_BASE;} \ 191 } 192 193 #define _miu_offset_to_phy(MiuSel, Offset, PhysAddr) if (MiuSel == E_CHIP_MIU_0) \ 194 {PhysAddr = Offset;} \ 195 else if (MiuSel == E_CHIP_MIU_1) \ 196 {PhysAddr = Offset + HAL_MIU1_BASE;} \ 197 else \ 198 {PhysAddr = Offset + HAL_MIU2_BASE;} 199 #endif 200 #endif 201 202 #define SUPPORT TRUE 203 #define NONSUPPORT FALSE 204 205 //[CHIP][HAL][007] Set IP support list [START] 206 #define CHIP_IP_MFE SUPPORT 207 #define CHIP_IP_VE SUPPORT 208 #define CHIP_IP_AVD SUPPORT 209 #define CHIP_IP_DEMOD SUPPORT 210 #define CHIP_IP_VBI SUPPORT 211 #define CHIP_IP_VIF SUPPORT 212 #define CHIP_IP_DMX SUPPORT 213 #define CHIP_IP_CEC SUPPORT 214 #define CHIP_IP_MBX SUPPORT 215 #define CHIP_IP_SWI2C SUPPORT 216 #define CHIP_IP_BDMA SUPPORT 217 #define CHIP_IP_CPU SUPPORT 218 #define CHIP_IP_GPIO SUPPORT 219 #define CHIP_IP_HWI2C SUPPORT 220 #define CHIP_IP_IR SUPPORT 221 #define CHIP_IP_MIU SUPPORT 222 #define CHIP_IP_MPIF NONSUPPORT 223 #define CHIP_IP_MSPI SUPPORT 224 #define CHIP_IP_PM SUPPORT 225 #define CHIP_IP_PWM SUPPORT 226 #define CHIP_IP_PWS SUPPORT 227 #define CHIP_IP_RTC SUPPORT 228 #define CHIP_IP_SAR SUPPORT 229 #define CHIP_IP_URDMA SUPPORT 230 #define CHIP_IP_WDT SUPPORT 231 #define CHIP_IP_AESDMA SUPPORT 232 #define CHIP_IP_CA NONSUPPORT 233 #define CHIP_IP_PCMCIA SUPPORT 234 #define CHIP_IP_SC SUPPORT 235 #define CHIP_IP_GPD SUPPORT 236 #define CHIP_IP_JPEG SUPPORT 237 #define CHIP_IP_VDEC SUPPORT 238 #define CHIP_IP_ACE SUPPORT 239 #define CHIP_IP_DAC NONSUPPORT 240 #define CHIP_IP_DDC2BI SUPPORT 241 #define CHIP_IP_DIP SUPPORT 242 #define CHIP_IP_DLC SUPPORT 243 #define CHIP_IP_GOP SUPPORT 244 #define CHIP_IP_HDMITX NONSUPPORT 245 #define CHIP_IP_MHL SUPPORT 246 #define CHIP_IP_MVOP SUPPORT 247 #define CHIP_IP_PNL SUPPORT 248 #define CHIP_IP_XC SUPPORT 249 #define CHIP_IP_GFX SUPPORT 250 #define CHIP_IP_AUDIO SUPPORT 251 #define CHIP_IP_SERFLASH SUPPORT 252 //[CHIP][HAL][007] Set IP support list [END] 253 254 //------------------------------------------------------------------------------------------------- 255 // Type and Structure 256 //------------------------------------------------------------------------------------------------- 257 258 259 //------------------------------------------------------------------------------------------------- 260 // Function and Variable 261 //------------------------------------------------------------------------------------------------- 262 void CHIP_InitISR(void); 263 MS_BOOL CHIP_InISRContext(void); 264 MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb); 265 MS_BOOL CHIP_DetachISR(InterruptNum eIntNum); 266 MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum); 267 MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum); 268 MS_BOOL CHIP_EnableAllInterrupt(void); 269 MS_BOOL CHIP_DisableAllInterrupt(void); 270 MS_BOOL CHIP_DebugIRQ(InterruptNum eIntNum, IrqDebugOpt eIrqDebugOpt); 271 MS_BOOL CHIP_CompleteIRQ(InterruptNum eIntNum); 272 273 274 #ifdef __cplusplus 275 } 276 #endif 277 278 #endif // _HAL_CHIP_H_ 279