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93 ////////////////////////////////////////////////////////////////////////////////
94 //==============================================================================
95 // [mhal_sc.c]
96 // Date: 20081203
97 // Descriptions: Add a new layer for HW setting
98 //==============================================================================
99 #define MHAL_SC_C
100
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <asm/div64.h>
103 #else
104 #define do_div(x,y) ((x)/=(y))
105 #endif
106 #include "UFO.h"
107
108 // Common Definition
109 #include "MsCommon.h"
110 #include "MsIRQ.h"
111 #include "MsOS.h"
112 #include "mhal_xc_chip_config.h"
113 #include "utopia.h"
114 #include "utopia_dapi.h"
115 #include "xc_hwreg_utility2.h"
116 #include "xc_Analog_Reg.h"
117 #include "drvXC_IOPort.h"
118 #include "apiXC.h"
119 #include "drv_sc_display.h"
120 #include "drv_sc_isr.h"
121 #include "apiXC_Adc.h"
122 #include "apiXC_PCMonitor.h"
123 #include "apiXC_ModeParse.h"
124 #include "apiXC_Auto.h"
125 #include "drvXC_HDMI_if.h"
126 #include "mvideo_context.h"
127 #include "drv_sc_ip.h"
128 #include "mhal_dynamicscaling.h"
129 #include "mdrv_sc_dynamicscaling.h"
130 #include "drvMVOP.h"
131 #include "drvIPAUTH.h"
132 #include "drvIPAUTH.h"
133
134 #if (LD_ENABLE==1)
135 #include "mdrv_ld.h"
136 #include "mdrv_ldalgo.h"
137 #endif
138 #include "mdrv_sc_3d.h"
139 #include "drv_sc_menuload.h"
140 #include "drvXC_ADC_Internal.h"
141 #include "mhal_sc.h"
142 #if FRC_INSIDE
143 #include "mdrv_frc.h"
144 #include "mhal_frc.h"
145 #endif
146 #include "XC_private.h"
147 #include "mhal_menuload.h"
148 #include "halCHIP.h"
149 #include "drvSYS.h"
150 #include "drv_sc_scaling.h"
151 #include "drvSEAL.h"
152 #include "drvMIU.h"
153
154 #ifndef DONT_USE_CMA
155 #if (XC_SUPPORT_CMA ==TRUE)
156 #include "drvCMAPool.h"
157 #include "msos/linux/ion_uapi.h"
158 #include "msos/linux/mdrv_cma_pool_st.h"
159 #endif
160 #endif
161
162 #if (defined (ANDROID) && defined(UFO_XC_DS_PQ))
163 #include "drvPQ_Define.h"
164 #endif
165 #include <assert.h>
166 #ifdef ANDROID
167 #include <cutils/log.h>
168 #ifndef LOGE
169 #define printf(format, args...) ALOGE(format, ##args);
170 #else
171 #define printf(format, args...) LOGE(format, ##args);
172 #endif
173 #endif
174
175 #define DBG_EN 0
176 #if DBG_EN
177 #define SC_DBG(x) x
178 #define FPLL_DBG(x) x
179 #else
180 #define SC_DBG(x)
181 #define FPLL_DBG(x)
182 #endif
183 #define new_chakra
184
185 #define IS_OUTPUT_4K2K() ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width > 3000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 2000))
186
187 //==============================================================================
188 //==============================================================================
189 MS_VIRT _XC_RIU_BASE;
190 MS_VIRT _PM_RIU_BASE;
191
192 MS_VIRT _DVI_ATOP_RIU_BASE;
193 MS_VIRT _DVI_DTOP_RIU_BASE;
194 MS_VIRT _HDCP_RIU_BASE;
195 MS_VIRT _DVI_EQ_RIU_BASE;
196 MS_VIRT _ADC_DTOPB_RIU_BASE;
197
198 MS_VIRT _DDC_RIU_BASE;
199 MS_VIRT _PM_SLEEP_RIU_BASE;
200
201 MS_U32 u32DTVPatchTimer;
202 MS_BOOL bPreFDMaskStatse;
203 MS_U16 u16FDMaskCount;
204
205 #ifndef DONT_USE_CMA
206 #if (XC_SUPPORT_CMA ==TRUE)
207 MS_U32 u32CMAPatchTimer_Main ;
208 #endif
209 #endif
210
211 #ifdef UFO_XC_AUTO_DOWNLOAD
212 #define DEBUG_HDR 0
213 #define AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR 512
214 #define AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR 4944
215
216 // HDR client of auto download has these following formats, include format0 and format1.
217 //
218 // Format0:
219 //127 125 116 115 112 60 57 0
220 // | [x[2]] | [addr(10)] | 0 | [sel0(3)] | [data1] | sel1(3) | [data0] |
221 // sel0 = 1 x(52) sel1 = 1 wd0(19),wd1(19),wd2(19)
222 // sel0 = 2 x(4),wd0(16),wd1(16),wd2(16) sel1 = 2 x(9),wd0(16),wd1(16),wd2(16)
223 // sel0 = 3 x(40),wd0(12) sel1 = 3 x(45),wd0(12)
224 // sel0 = 4 idx(4),wd0(16),wd1(16),wd2(16) sel1 = 4 x(5),idx(4),wd0(16),wd1(16),wd2(16)
225 // sel: 0: disable
226 // 1: De-gamma
227 // 2: Gamma
228 // 3: TMO
229 // 4: 3D-lut
230
231 // Format1:
232 //127 125 116 115 112 60 57 0
233 // | [x[2]] | [addr(10)] | 1 | [ctrl0(3)] | [data1] | sel1(3) | [data0] |
234 // x(52) sel1 = 0
235 // idx(4),wd0(16),wd1(16),wd2(16) sel1 = 4 x(10),degam(19),gam(16),tmo(16)
236 // ctrl: bit: 114 113 112
237 // |degam|gam|tmo|
238 // sel: 0: disable
239 // 4: 3D-lut
240 //
241 // HW designer recommand using format1.
242 // These following definitions write datas of tmo/gamma/de-gamma/3d-lut separately by format1,
243 // please refer to definition of WRITE_TMO_DATA_FORMAT_1, WRITE_GAMMA_DATA_FORMAT_1, WRITE_DEGAMMA_DATA_FORMAT_1 and WRITE_3DLUT_DATA_FORMAT_1.
244 #define WRITE_TMO_DATA_FORMAT_1(baseaddr, index, value) \
245 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
246 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x09);\
247 *(baseaddr + 14) = ((*(baseaddr + 14) & 0xF0) | (((value) >> 8) & 0x0F));\
248 *(baseaddr + 15) = ((value) & 0xFF);
249
250 #define WRITE_GAMMA_DATA_FORMAT_1(baseaddr, index, value) \
251 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
252 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x0A);\
253 *(baseaddr + 14) = ((*(baseaddr + 14) & 0x0F) | (((value) << 4) & 0xF0));\
254 *(baseaddr + 13) = (((value) >> 4) & 0xFF);\
255 *(baseaddr + 12) = ((*(baseaddr + 12) & 0xF0) | (((value) >> 12) & 0x0F));
256
257 #define WRITE_DEGAMMA_DATA_FORMAT_1(baseaddr, index, value) \
258 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
259 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x0C);\
260 *(baseaddr + 12) = ((*(baseaddr + 12) & 0x0F) | (((value) << 4) & 0xF0));\
261 *(baseaddr + 11) = (((value) >> 4) & 0xFF);\
262 *(baseaddr + 10) = ((*(baseaddr + 10) & 0x80) | (((value) >> 12) & 0x7F));
263
264 #define WRITE_3DLUT_DATA_FORMAT_1(baseaddr, index, subindex, rval, gval, bval) \
265 *(baseaddr) = (((*(baseaddr)) & 0xC0) | (((index) >> 4) & 0x3F));\
266 *(baseaddr + 1) = ((((index) << 4) & 0xF0) | ((*(baseaddr + 1)) & 0x0F) | 0x08);\
267 *(baseaddr + 8) = ((*(baseaddr + 8) & 0xF1) | 0x08);\
268 *(baseaddr + 8) = ((*(baseaddr + 8) & 0x0F) | (((bval) << 4) & 0xF0));\
269 *(baseaddr + 7) = (((bval) >> 4) & 0xFF);\
270 *(baseaddr + 6) = ((*(baseaddr + 6) & 0xF0) | (((bval) >> 12) & 0x0F));\
271 *(baseaddr + 6) = ((*(baseaddr + 6) & 0x0F) | (((gval) << 4) & 0xF0));\
272 *(baseaddr + 5) = (((gval) >> 4) & 0xFF);\
273 *(baseaddr + 4) = ((*(baseaddr + 4) & 0xF0) | (((gval) >> 12) & 0x0F));\
274 *(baseaddr + 4) = ((*(baseaddr + 4) & 0x0F) | (((rval) << 4) & 0xF0));\
275 *(baseaddr + 3) = (((rval) >> 4) & 0xFF);\
276 *(baseaddr + 2) = ((*(baseaddr + 2) & 0xF0) | (((rval) >> 12) & 0x0F));\
277 *(baseaddr + 2) = ((*(baseaddr + 2) & 0x0F) | (((subindex) << 4) & 0xF0));
278
279 // The following definition clear bits of format1's ctrl & sel.
280 #define CLEAR_HDR_DATA_FORMAT_1(baseaddr) \
281 *(baseaddr + 1) = ((*(baseaddr + 1)) & 0xF8);\
282 *(baseaddr + 8) = (*(baseaddr + 8) & 0xF1);
283
284 static MS_U32 _au32_3dlut_entry_num[8] = {736, 656, 656, 576, 656, 576, 576, 512};
285 #endif
286
287
288 // Put this function here because hwreg_utility2 only for hal.
Hal_SC_init_riu_base(MS_VIRT u32riu_base,MS_VIRT u32PMriu_base)289 void Hal_SC_init_riu_base(MS_VIRT u32riu_base, MS_VIRT u32PMriu_base)
290 {
291 _XC_RIU_BASE = u32PMriu_base;
292 _PM_RIU_BASE = u32PMriu_base;
293
294
295 _DVI_ATOP_RIU_BASE = u32PMriu_base;
296 _DVI_DTOP_RIU_BASE = u32PMriu_base;
297 _HDCP_RIU_BASE = u32PMriu_base;
298 _DVI_EQ_RIU_BASE = u32PMriu_base;
299 _ADC_DTOPB_RIU_BASE = u32PMriu_base;
300
301 _DDC_RIU_BASE =u32PMriu_base;
302 _PM_SLEEP_RIU_BASE =u32PMriu_base;
303
304 }
305
306 //=========================================================//
307 // Function : Hal_SC_setfield
308 // Description:
309 //=========================================================//
Hal_SC_setfield(void * pInstance,MS_U16 reg_1D,MS_U16 reg_21,MS_U16 reg_23,SCALER_WIN eWindow)310 void Hal_SC_setfield(void *pInstance, MS_U16 reg_1D, MS_U16 reg_21, MS_U16 reg_23, SCALER_WIN eWindow )
311 {
312 //printf("reg_1D=%x, reg_21=%x, reg_23=%x\n", reg_1D, reg_21, reg_23);
313 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
314 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
315
316 if( eWindow == MAIN_WINDOW )
317 {
318 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_1D_L, (reg_1D<<8), 0xEF00);
319 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_21_L, reg_21, 0x3FFF);
320 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_23_L, (reg_23<<8), HBMASK);
321 }
322 else
323 {
324 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_1D_L, (reg_1D<<8), 0xEF00);
325 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_21_L, reg_21, 0x3FFF);
326 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_23_L, (reg_23<<8), HBMASK);
327 }
328 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_1D_L, HBMASK));
329 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_21_L, 0x3FFF));
330 // printf("%x ",SC_R2BYTEMSK(REG_SC_BK01_23_L, HBMASK));
331
332 // printf("%x ",SC_R4BYTE(REG_SC_BK01_21_L));
333 // printf("%x ",SC_R4BYTE(REG_SC_BK01_23_L));
334 }
335
336 //=========================================================//
337 // Function : Hal_SC_de_only_en
338 // Description: DE Only. HSYNC and VSYNC are ignored.
339 //#0: Disable.
340 //#1: Enable.
341 //=========================================================//
Hal_SC_de_only_en(void * pInstance,MS_BOOL benable,SCALER_WIN eWindow)342 void Hal_SC_de_only_en(void *pInstance, MS_BOOL benable, SCALER_WIN eWindow)
343 {
344 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
345 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
346
347 if(eWindow == MAIN_WINDOW)
348 {
349 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, (benable ? BIT(6):0), BIT(6));
350 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, (benable ? BIT(4):0), BIT(4)); // SW patch for HDMI switch, Auto search HST jistter mask filter force off
351 }
352 else
353 {
354 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, (benable ? BIT(6):0), BIT(6));
355 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_2F_L, (benable ? BIT(4):0), BIT(4)); // SW patch for HDMI switch, Auto search HST jistter mask filter force off
356 }
357 }
358
359 //=========================================================//
360 // Function : Hal_SC_de_direct_en
361 // Description: Digital Input Horizontal Sample Range
362 //#0: Use DE as sample range, only V position can be adjusted.
363 //#1: Use SPRHST and SPRHDC as sample range, both H and V position can be adjusted.
364 //=========================================================//
Hal_SC_de_direct_en(void * pInstance,MS_BOOL benable,SCALER_WIN eWindow)365 void Hal_SC_de_direct_en(void *pInstance, MS_BOOL benable, SCALER_WIN eWindow)
366 {
367 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
368 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
369 if(eWindow == MAIN_WINDOW)
370 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, (benable ? BIT(7):0), BIT(7));
371 else
372 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, (benable ? BIT(7):0), BIT(7));
373
374 }
375
Hal_SC_set_ficlk(void * pInstance,MS_BOOL bPreDown,SCALER_WIN eWindow)376 void Hal_SC_set_ficlk(void *pInstance, MS_BOOL bPreDown, SCALER_WIN eWindow)
377 {
378 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
379 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
380 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
381 {
382 // monaco is not needed it
383 #if 0
384 if( eWindow == MAIN_WINDOW )
385 {
386 if (bPreDown)
387 {
388 W2BYTEMSK(REG_CKG_FICLK_F2, CKG_FICLK_F2_IDCLK2, CKG_FICLK_F2_MASK); // clk_idclk2
389 }
390 else
391 {
392 W2BYTEMSK(REG_CKG_FICLK_F2, CKG_FICLK_F2_FCLK, CKG_FICLK_F2_MASK); // clk_fclk
393 }
394 }
395 else
396 {
397 if (bPreDown)
398 {
399 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_IDCLK1, CKG_FICLK_F1_MASK); // clk_idclk1
400 }
401 else
402 {
403 W2BYTEMSK(REG_CKG_FICLK_F1, CKG_FICLK_F1_FCLK, CKG_FICLK_F1_MASK); // clk_fclk
404 }
405 }
406 #endif
407 }
408 else //E_XC_DEVICE1 == psXCInstPri->u32DeviceID
409 {
410 if (bPreDown)
411 {
412 W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_IDCLK2, CKG_S2_FICLK2_F2_MASK); // clk_edclk
413 }
414 else
415 {
416 W2BYTEMSK(REG_CKG_S2_FICLK2_F2, CKG_S2_FICLK2_F2_FCLK, CKG_S2_FICLK2_F2_MASK); // clk_fclk
417 }
418 }
419 }
420
Hal_SC_set_shiftline(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)421 void Hal_SC_set_shiftline(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow )
422 {
423 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
424 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
425 if( eWindow == MAIN_WINDOW )
426 {
427 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_2F_L, (u8Val & 0x07)<<8, (BIT(10)|BIT(9)|BIT(8)));
428 }
429 else
430 {
431 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_2F_L, (u8Val & 0x03)<<13, (BIT(14)|BIT(13)));
432 }
433 }
434
Hal_SC_set_422_cbcr_swap(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)435 void Hal_SC_set_422_cbcr_swap(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
436 {
437 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
438 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
439 if(eWindow == MAIN_WINDOW)
440 {
441 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_0A_L, bEnable ? BIT(6) : 0, BIT(6));
442 }
443 else
444 {
445 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_0A_L, bEnable ? BIT(6) : 0, BIT(6));
446 }
447 }
448
Hal_SC_set_pre_align_pixel(void * pInstance,MS_BOOL bEnable,MS_U16 pixels,SCALER_WIN eWindow)449 void Hal_SC_set_pre_align_pixel(void *pInstance, MS_BOOL bEnable, MS_U16 pixels, SCALER_WIN eWindow)
450 {
451 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
452 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
453 if (bEnable)
454 {
455 if ( eWindow == MAIN_WINDOW )
456 {
457 // Enable pre align pixel for mirror mode.
458 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, BIT(15), BIT(15));
459
460 // Number of pixels need to be inserted. (U3 has 15 pixels)
461 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, pixels << 8 , 0x1F00);
462 }
463 else
464 {
465 // Enable pre align pixel for mirror mode.
466 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, BIT(15), BIT(15));
467
468 // Number of pixels need to be inserted. (U3 has 15 pixels)
469 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, pixels << 8 , 0x1F00);
470 }
471
472 }
473 else
474 {
475 if ( eWindow == MAIN_WINDOW )
476 {
477 // Disable pre align pixel for mirror mode.
478 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_2A_L, 0x00 , BIT(15));
479 }
480 else
481 {
482 // Disable pre align pixel for mirror mode.
483 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_2A_L, 0x00 , BIT(15));
484 }
485 }
486 }
487
Hal_XC_Set_FreeFRCMD(void * pInstance,MS_BOOL bEnable)488 void Hal_XC_Set_FreeFRCMD(void *pInstance, MS_BOOL bEnable)
489 {
490 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
491 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
492 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, bEnable? BIT(5) : 0, BIT(5));
493 }
494
495 // Obsolete in M10/J2/A5
Hal_SC_set_linearmem_mode(MS_BOOL bEnable,SCALER_WIN eWindow)496 void Hal_SC_set_linearmem_mode(MS_BOOL bEnable, SCALER_WIN eWindow)
497 {
498 }
499
500 // This function will return 8/10/12/14/16 field mode or 8 frame mode.
501 // Otherwise it return IMAGE_STORE_2_FRAMES
Hal_SC_GetFrameStoreMode(void * pInstance,SCALER_WIN eWindow)502 XC_FRAME_STORE_NUMBER Hal_SC_GetFrameStoreMode(void *pInstance, SCALER_WIN eWindow)
503 {
504 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
505 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
506 MS_U16 u16FrameCount = 0x00;
507 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
508 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
509 if (eWindow == MAIN_WINDOW)
510 {
511 u16FrameCount = 0x1F & SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L);
512 }
513 else
514 {
515 u16FrameCount = 0x1F & SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L);
516 }
517
518 switch( u16FrameCount) // Get field type.
519 {
520 default:
521 if (gSrcInfo[MAIN_WINDOW].bInterlace)
522 {
523 return IMAGE_STORE_4_FIELDS;
524 }
525 else
526 {
527 return IMAGE_STORE_2_FRAMES;
528 }
529 case 3:
530 return IMAGE_STORE_3_FRAMES;
531 case 4:
532 if (gSrcInfo[MAIN_WINDOW].bInterlace)
533 {
534 return IMAGE_STORE_4_FIELDS;
535 }
536 else
537 {
538 return IMAGE_STORE_4_FRAMES;
539 }
540 case 6:
541 if (gSrcInfo[MAIN_WINDOW].bInterlace)
542 {
543 return IMAGE_STORE_6_FIELDS;
544 }
545 else
546 {
547 return IMAGE_STORE_6_FRAMES;
548 }
549 case 8:
550 if (gSrcInfo[MAIN_WINDOW].bInterlace)
551 {
552 return IMAGE_STORE_8_FIELDS;
553 }
554 else
555 {
556 return IMAGE_STORE_8_FRAMES;
557 }
558 case 10:
559 return IMAGE_STORE_10_FIELDS;
560 case 12:
561 if (gSrcInfo[MAIN_WINDOW].bInterlace)
562 {
563 return IMAGE_STORE_12_FIELDS;
564 }
565 else
566 {
567 return IMAGE_STORE_12_FRAMES;
568 }
569 case 14:
570 return IMAGE_STORE_14_FIELDS;
571 case 16:
572 return IMAGE_STORE_16_FIELDS;
573
574 }
575
576 return IMAGE_STORE_UNDEFINE;
577 }
578
Hal_SC_set_wr_bank_mapping(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)579 void Hal_SC_set_wr_bank_mapping(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
580 {
581 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
582 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
583 SC_DBG(printf("Set WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
584
585 if( eWindow == MAIN_WINDOW )
586 {
587 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
588 }
589 else
590 {
591 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
592 }
593 }
594
Hal_SC_set_frcm_wr_bank_mapping(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)595 void Hal_SC_set_frcm_wr_bank_mapping(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
596 {
597 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
598 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
599 SC_DBG(printf("Set WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
600
601 if( eWindow == MAIN_WINDOW )
602 {
603 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_07_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
604 }
605 else
606 {
607 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_47_L, ((MS_U16)u8val)<<13, BIT(15)|BIT(14)|BIT(13));
608 }
609 }
610
Hal_SC_set_wr_bank_mapping_num(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)611 void Hal_SC_set_wr_bank_mapping_num(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
612 {
613 Hal_SC_set_wr_bank_mapping(pInstance, u8Val, eWindow);
614 }
615
Hal_SC_Get_WR_Bank_Mapping(void * pInstance,SCALER_WIN eWindow)616 MS_U8 Hal_SC_Get_WR_Bank_Mapping(void *pInstance, SCALER_WIN eWindow)
617 {
618 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
619 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
620 MS_U8 u8val = 0;
621
622 if( eWindow == MAIN_WINDOW )
623 {
624 u8val = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(15)|BIT(14)|BIT(13)) >> 13;
625 }
626 else
627 {
628 u8val = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(15)|BIT(14)|BIT(13)) >> 13;
629 }
630 SC_DBG(printf("Get WR bank mapping SC_BK12_07/47_L[15:13]= 0x%x\n", ((MS_U16)u8val)<<13));
631 return u8val;
632 }
633
Hal_SC_Get_WR_Bank_Mapping_Num(void * pInstance,SCALER_WIN eWindow)634 MS_U8 Hal_SC_Get_WR_Bank_Mapping_Num(void *pInstance, SCALER_WIN eWindow)
635 {
636 return Hal_SC_Get_WR_Bank_Mapping(pInstance, eWindow);
637 }
638
Hal_SC_set_csc(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)639 void Hal_SC_set_csc(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow )
640 {
641 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
642 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
643 if( eWindow == MAIN_WINDOW )
644 {
645 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, (bEnable ? BIT(3):0), BIT(3));
646 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_01_L, (bEnable ? BIT(2):0), BIT(2));
647 }
648 else
649 {
650 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_40_L, (bEnable ? BIT(3):0), BIT(3));
651 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_01_L, (bEnable ? BIT(2):0), BIT(2));
652 }
653 }
654
Hal_SC_get_ip2_csc(void * pInstance,SCALER_WIN eWindow)655 MS_BOOL Hal_SC_get_ip2_csc(void *pInstance, SCALER_WIN eWindow)
656 {
657 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
658 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
659 MS_BOOL bYUVInput;
660 if(eWindow == MAIN_WINDOW)
661 {
662 // If it has CSC, it shows it must be RGB input.
663 // Because in scaler, it must be YUV. So if input is RGB, then we need to do CSC
664 bYUVInput = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, BIT(3) ))? FALSE:TRUE;
665 }
666 else
667 {
668 bYUVInput = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_40_L, BIT(3) ))? FALSE:TRUE;
669 }
670 return bYUVInput;
671 }
672
Hal_SC_set_delayline(void * pInstance,MS_U8 u8DelayLines,SCALER_WIN eWindow)673 void Hal_SC_set_delayline(void *pInstance, MS_U8 u8DelayLines, SCALER_WIN eWindow )
674 {
675 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
676 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
677 //skip bit7, which is other usage
678 MS_U16 u16DelayLines = ((MS_U16)u8DelayLines) & 0xFF;
679 if( eWindow == MAIN_WINDOW )
680 {
681 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_1C_L, (u16DelayLines<<4), (BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)));
682 }
683 else
684 {
685 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_1C_L, (u16DelayLines<<4), (BIT(9)|BIT(8)|BIT(7)|BIT(6)|BIT(5)|BIT(4)));
686 }
687 }
688
Hal_SC_set_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)689 void Hal_SC_set_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
690 {
691 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
692 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
693 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
694 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
695
696 MS_PHY u32MinLimitAddress = 0;
697 MS_PHY u32MaxLimitAddress = 0;
698
699 #ifndef DONT_USE_CMA
700 #if (XC_SUPPORT_CMA ==TRUE)
701 #if ((HW_DESIGN_4K2K_VER == 4)||(HW_DESIGN_4K2K_VER == 6))
702 #if (defined (ANDROID))
703 if(pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].isEnable == FALSE)
704 {
705 UNUSED(u32WritelimitAddrBase);
706 UNUSED(eWindow);
707 return;
708 }
709 #endif
710 #endif
711 #endif
712 #endif
713
714 #if (HW_DESIGN_4K2K_VER == 4)
715 // in Monaco, the 4K data path need to setup the IPM write on the FRCM base, and the max/min limit region also need to change
716 if(gSrcInfo[eWindow].stCapWin.width > 3800)
717 {
718 u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
719 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
720 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
721 else
722 u32MaxLimitAddress = u32MinLimitAddress;
723 }
724 //monaco mm DS VB size always be 4k2k , mvop timing is 4k2k , 2p mode
725 else if ((pXCResourcePrivate->sthal_SC.bDynamicScalingEnable || pXCResourcePrivate->stdrvXC_Dynamicscaling._bDSForceIndexEnable[eWindow] ) &&
726 (gSrcInfo[eWindow].Status2.u16VirtualBox_Width >= 0xF00) && (gSrcInfo[eWindow].Status2.u16VirtualBox_Height>= 0x870))
727 {
728 u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
729 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
730 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
731 else
732 u32MaxLimitAddress = u32MinLimitAddress;
733 }
734 else
735 #endif
736 {
737 u32MinLimitAddress = MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
738 if((MHal_XC_GetDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDNRBufSize(pInstance, eWindow))!=0)
739 u32MaxLimitAddress = (MHal_XC_GetDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
740 else
741 u32MaxLimitAddress = u32MinLimitAddress;
742 }
743 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, MHal_XC_GetDNRBufAddress=%tx, MHal_XC_GetDNRBufSize=%tx\n", eWindow, (ptrdiff_t)(MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ), (ptrdiff_t)((MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD));
744 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, u32MinLimitAddress=%tx, u32MaxLimitAddress=%tx\n", eWindow, (ptrdiff_t)u32MinLimitAddress, (ptrdiff_t)u32MaxLimitAddress);
745
746 if(eWindow == MAIN_WINDOW)
747 {
748 /// need to disable the r/w request, when change the write limit base
749 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
750 if (IsHMirrorMode(eWindow) && IsEnableDualMode(eWindow))
751 {
752 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(4):0),BIT(4)); //F2 memory address limit enable
753 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_48_L, u32MinLimitAddress); //F2 memory min address
754 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_4A_L, u32MaxLimitAddress); //F2 memory max address
755 }
756 else
757 {
758 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(0):0),BIT(0)); //F2 memory address limit enable
759 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_40_L, u32MinLimitAddress); //F2 memory min address
760 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_42_L, u32MaxLimitAddress); //F2 memory max address
761 }
762 /// need to enable the r/w request
763 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0x00, BIT(0)|BIT(1));
764 }
765 else
766 {
767 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
768 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(1):0),BIT(1)); //F1 memory address limit enable
769 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_44_L, u32MinLimitAddress); //F1 memory min address
770 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_46_L, u32MaxLimitAddress); //F1 memory max address
771 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0x00, BIT(0)|BIT(1));
772 }
773 }
774
Hal_SC_set_frcm_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)775 void Hal_SC_set_frcm_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
776 {
777 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
778 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
779 MS_PHY u32MinLimitAddress = MHal_XC_GetFRCMBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
780 MS_PHY u32MaxLimitAddress = 0;
781
782 if((MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))!=0)
783 u32MaxLimitAddress = (MHal_XC_GetFRCMBufAddress(pInstance, eWindow) + MHal_XC_GetFRCMBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
784 else
785 u32MaxLimitAddress = u32MinLimitAddress;
786
787 if(eWindow == MAIN_WINDOW)
788 {
789 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_50_L, ((u32WritelimitAddrBase&BIT(31))?BIT(4):0),BIT(4)); //F2 memory address limit enable
790 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_64_L, u32MinLimitAddress); //F2 memory min address
791 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_66_L, u32MaxLimitAddress); //F2 memory max address
792 }
793 else
794 {
795 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_50_L, ((u32WritelimitAddrBase&BIT(31))?BIT(5):0),BIT(5)); //F1 memory address limit enable
796 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_68_L, u32MinLimitAddress); //F1 memory min address
797 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_6A_L, u32MaxLimitAddress); //F1 memory max address
798 }
799
800 }
801
Hal_SC_set_dual_write_limit(void * pInstance,MS_PHY u32WritelimitAddrBase,SCALER_WIN eWindow)802 void Hal_SC_set_dual_write_limit(void *pInstance, MS_PHY u32WritelimitAddrBase, SCALER_WIN eWindow)
803 {
804 #ifdef UFO_XC_SUPPORT_DUAL_MIU
805 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
806 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
807 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
808 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
809
810 MS_PHY u32MinLimitAddress = 0;
811 MS_PHY u32MaxLimitAddress = 0;
812
813 u32MinLimitAddress = MHal_XC_GetDualDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ;
814 if((MHal_XC_GetDualDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDualDNRBufSize(pInstance, eWindow))!=0)
815 u32MaxLimitAddress = (MHal_XC_GetDualDNRBufAddress(pInstance, eWindow) + MHal_XC_GetDualDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD - 1;
816 else
817 u32MaxLimitAddress = u32MinLimitAddress;
818
819 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, MHal_XC_GetDNRBufAddress=%tx, MHal_XC_GetDNRBufSize=%tx\n", eWindow, (ptrdiff_t)(MHal_XC_GetDNRBufAddress(pInstance, eWindow)/BYTE_PER_WORD ), (ptrdiff_t)((MHal_XC_GetDNRBufSize(pInstance, eWindow))/BYTE_PER_WORD));
820 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"eWindow=%x, u32MinLimitAddress=%tx, u32MaxLimitAddress=%tx\n", eWindow, (ptrdiff_t)u32MinLimitAddress, (ptrdiff_t)u32MaxLimitAddress);
821
822 if(eWindow == MAIN_WINDOW)
823 {
824 /// need to disable the r/w request, when change the write limit base
825 /// For SCMI0/1 use the same IPM r/w request.
826 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(0)|BIT(1), BIT(0)|BIT(1));
827 if (IsHMirrorMode(eWindow) && IsEnableDualMode(eWindow))
828 {
829 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(0):0),BIT(0)); //F2 memory address limit enable
830 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_40_L, u32MinLimitAddress); //F2 memory min address
831 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_42_L, u32MaxLimitAddress); //F2 memory max address
832
833 }
834 else
835 {
836 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_38_L, ((u32WritelimitAddrBase&BIT(31))?BIT(4):0),BIT(4)); //F2 memory address limit enable
837 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_48_L, u32MinLimitAddress); //F2 memory min address
838 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0D_4A_L, u32MaxLimitAddress); //F2 memory max address
839 }
840 /// need to enable the r/w request
841 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0x00, BIT(0)|BIT(1));
842 }
843 #endif
844 }
845
Hal_SC_set_opm_write_limit(void * pInstance,MS_BOOL bEnable,MS_BOOL bFlag,MS_U32 u32OPWlimitAddr,SCALER_WIN eWindow)846 void Hal_SC_set_opm_write_limit(void *pInstance, MS_BOOL bEnable, MS_BOOL bFlag, MS_U32 u32OPWlimitAddr, SCALER_WIN eWindow)
847 {
848 #if 0
849
850 MS_U16 u16temp = 0x00;
851 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
852 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
853
854 // Only support address of Main_Window
855 if (eWindow != MAIN_WINDOW )
856 return;
857
858 // Bit 0 ~ 24
859 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5E_L, u32OPWlimitAddr & 0xFFFF);
860 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5F_L, (u32OPWlimitAddr >> 16) & 0x1FF);
861
862 // OPW limit enable
863 if (bEnable)
864 u16temp = BIT(9);
865
866 // OPW limit flag 0: maximum 1:minimum
867 if (bFlag)
868 u16temp |= BIT(10);
869
870 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_5F_L,u16temp ,BIT(9) | BIT(10) );
871 #endif
872 }
873
Hal_SC_is_extra_req_en(void * pInstance,MS_U16 * pu16MainHStart,MS_U16 * pu16MainHEnd,MS_U16 * pu16SubHStart,MS_U16 * pu16SubHEnd)874 MS_BOOL Hal_SC_is_extra_req_en(void *pInstance,
875 MS_U16 *pu16MainHStart, MS_U16 *pu16MainHEnd,
876 MS_U16 *pu16SubHStart, MS_U16 *pu16SubHEnd)
877 {
878 MS_BOOL bEn = FALSE;
879 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
880 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
881
882 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
883 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
884
885 MS_U16 u16MainHStart, u16SubHStart;
886 MS_U16 u16MainHEnd, u16SubHEnd;
887
888 u16MainHStart = pu16MainHStart == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L) : *pu16MainHStart;
889 u16MainHEnd = pu16MainHEnd == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L) : *pu16MainHEnd;
890 u16SubHStart = pu16SubHStart == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L) : *pu16SubHStart;
891 u16SubHEnd = pu16SubHEnd == NULL ? SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L) : *pu16SubHEnd;
892
893 if( SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(1))
894 &&(((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
895 ||(psXCInstPri->u32DeviceID == 1))
896 ) // Only Legacy mode use old rule for extra enable
897 {
898 if(u16MainHStart > u16SubHStart || u16MainHEnd < u16SubHEnd)
899 {
900 bEn = FALSE;
901 }
902 else
903 {
904 bEn = TRUE;
905 }
906 }
907 else
908 {
909 bEn = FALSE;
910 }
911 #if DBG_EN
912 SC_DBG(printf("Sub=%d, MainHs=%d, SubHs=%d, MainHe=%d, SubHe=%d :: Extra=%d\n",
913 SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(1)),
914 u16MainHStart, u16SubHStart, u16MainHEnd, u16SubHEnd, bEn));
915 #endif
916 return bEn;
917
918 }
919
920 #if 0 //Dual not support switch miu select dynamicly.
921 //#ifdef UFO_XC_SUPPORT_DUAL_MIU
922 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
923 // Miu opm1 opm2 need to be switched just under Dual Mirror case, so it should be Called in runtime.
924 // This API just for swap OPM when miu select control by miu arb.
925 static void _Hal_SC_adjust_dual_miu_setting(void *pInstance, MS_PHY u32FBAddress, MS_PHY u32DualFBAddress, MS_BOOL bMirrorWithDual, MS_U16 *pu16OPMLeftMiuSel, MS_U16 *pu16OPMRightMiuSel)
926 {
927 MS_U8 u8MIUSel = 0;
928 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
929 if (u8MIUSel == 0)
930 {
931 //IPM0 OPM0 access miu0
932 *pu16OPMLeftMiuSel = 0x0;
933 }
934 else if(u8MIUSel == 1)
935 {
936 // OPM0 access miu 1
937 *pu16OPMLeftMiuSel = 0x1;
938 }
939 else if(u8MIUSel == 2)
940 {
941 // OPM0 access miu 1
942 *pu16OPMLeftMiuSel = 0x2;
943 }
944
945 _phy_to_miu_offset(u8MIUSel, u32DualFBAddress, u32DualFBAddress);
946 if (u8MIUSel == 0)
947 {
948 //IPM0 OPM0 access miu0
949 *pu16OPMRightMiuSel = 0x0;
950 }
951 else if(u8MIUSel == 1)
952 {
953 // OPM0 access miu 1
954 *pu16OPMRightMiuSel = 0x1;
955 }
956 else if(u8MIUSel == 2)
957 {
958 // OPM0 access miu 1
959 *pu16OPMRightMiuSel = 0x2;
960 }
961
962 if (bMirrorWithDual)
963 {
964 MS_U16 u16Tmp = *pu16OPMLeftMiuSel;
965 *pu16OPMLeftMiuSel = *pu16OPMRightMiuSel;
966 *pu16OPMRightMiuSel = u16Tmp;
967 }
968
969 }
970
971 #else
972 //the patch to reset the miu selection ,becuase HW always swaps the miu selection on dual or without dual.
973 static void _Hal_SC_adjust_swap_miu_setting(void *pInstance,MS_PHY u32FBAddress)
974 {
975 MS_U8 u8MIUSel = 0;
976 MS_U8 u8MIUSel_temp= 0;
977 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
978 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
979 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
980 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
981 u8MIUSel_temp = SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, BIT(4)) >> 3;
982 u8MIUSel_temp = u8MIUSel_temp | (SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, BIT(4)) >> 4);
983 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
984 if(u8MIUSel_temp != u8MIUSel)
985 {
986 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, (u8MIUSel & BIT(0)) << 4 , 0x0010);
987 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, ((u8MIUSel & BIT(1)) >> 1) << 4 , 0x0010);
988 }
989 else
990 {
991 printf("The miu has been set correctly function %s line %d parars \n",__FUNCTION__,__LINE__);
992 }
993 }
994 static void _Hal_SC_adjust_swap_miu_setting_burst(void *pInstance,MS_PHY u32FBAddress)
995 {
996 MS_U8 u8MIUSel = 0;
997 MS_U8 u8MIUSel_temp= 0;
998 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
999 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1000 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1001 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1002 u8MIUSel_temp = SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, BIT(4)) >> 3;
1003 u8MIUSel_temp = u8MIUSel_temp | (SC_R2BYTEMSK( psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, BIT(4)) >> 4);
1004 _phy_to_miu_offset(u8MIUSel, u32FBAddress, u32FBAddress);
1005 if(u8MIUSel_temp != u8MIUSel)
1006 {
1007 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_05_L, (u8MIUSel & BIT(0)) << 4 ,BIT(4));
1008 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK51_05_L, ((u8MIUSel & BIT(1)) >> 1) << 4 ,BIT(4));
1009 }
1010 else
1011 {
1012 printf("The miu has been set correctly function %s line %d parars \n",__FUNCTION__,__LINE__);
1013 }
1014 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1015 }
1016 #endif
1017 #endif
1018
_Hal_SC_fill_main_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg)1019 static void _Hal_SC_fill_main_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg)
1020 {
1021 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1022 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1023 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1024 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1025
1026 if(Hal_SC_is_extra_req_en(pInstance, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd, NULL, NULL))
1027 {
1028 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
1029 }
1030 else
1031 {
1032 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(15));
1033 }
1034
1035 //H pre-scaling
1036 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_04_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>00), 0xFFFF);
1037 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_05_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>16), 0xFFFF);
1038 //V pre-scaling
1039 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_08_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>00), 0xFFFF);
1040 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK02_09_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>16), 0xFFFF);
1041 //H post-scaling
1042 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_07_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>00), 0xFFFF);
1043 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_08_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>16), 0xFFFF);
1044 //V post-scaling
1045 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_09_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>00), 0xFFFF);
1046 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_0A_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>16), 0xFFFF);
1047
1048 //SCMI: vertical limitation
1049 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_18_L, (MS_U16)(pDBreg->u16VWritelimit), 0xFFFF);
1050 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1051 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1052
1053 //SCMI: IPM address 0
1054 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_08_L, (MS_U16)(pDBreg->u32DNRBase0>>00), 0xFFFF);
1055 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_09_L, (MS_U16)(pDBreg->u32DNRBase0>>16), 0xFFFF);
1056 //SCMI: DNR address 1
1057 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1058 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1059 //SCMI: DNR address 2
1060 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0C_L, (MS_U16)(pDBreg->u32DNRBase2>>00), 0xFFFF);
1061 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0D_L, (MS_U16)(pDBreg->u32DNRBase2>>16), 0xFFFF);
1062
1063 //SCMI: DNR offset
1064 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0E_L, (MS_U16)(pDBreg->u16DNROffset>>00), 0xFFFF);
1065 //SCMI: DNR fetch
1066 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_0F_L, (MS_U16)(pDBreg->u16DNRFetch>>00), 0xFFFF);
1067
1068 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1069
1070 //SCMI: OPM address 0
1071 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_10_L, (MS_U16)(pDBreg->u32OPMBase0>>00), 0xFFFF);
1072 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_11_L, (MS_U16)(pDBreg->u32OPMBase0>>16), 0xFFFF);
1073 //SCMI: OPM address 1
1074 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_12_L, (MS_U16)(pDBreg->u32OPMBase1>>00), 0xFFFF);
1075 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_13_L, (MS_U16)(pDBreg->u32OPMBase1>>16), 0xFFFF);
1076 //SCMI: OPM address 2
1077 // MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_14_L, (MS_U16)(pDBreg->u32OPMBase2>>00), 0xFFFF);
1078 // MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_15_L, (MS_U16)(pDBreg->u32OPMBase2>>16), 0xFFFF);
1079 //SCMI: OPM offset
1080 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_16_L, (MS_U16)(pDBreg->u16OPMOffset>>00), 0xFFFF);
1081 //SCMI: OPM fetch
1082 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_17_L, (MS_U16)(pDBreg->u16OPMFetch>>00), 0xFFFF);
1083
1084 #ifdef UFO_XC_SUPPORT_DUAL_MIU
1085 if (psXCInstPri->u32DeviceID == 0) // Dual miu just support sc0 main window for main window.
1086 {
1087 if (IsEnableDualMode(MAIN_WINDOW))
1088 {
1089 #if 0 // Dual do not support switch MIU setting Dynamic.
1090 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1091 MS_U16 u16OPMLeftMiuSel = 0;
1092 MS_U16 u16OPMRightMiuSel = 0;
1093 if(IsHMirrorMode(MAIN_WINDOW))
1094 {
1095 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1096 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], TRUE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1097 }
1098 else
1099 {
1100 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1101 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1102 }
1103
1104 // miu request0 IPM/OPM LSB
1105 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1106 // miu request0 IPM/OPM MSB
1107 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1108 // miu request1 IPM/OPM
1109 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1110 #else
1111 _Hal_SC_adjust_swap_miu_setting_burst(pInstance,pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW]);
1112 #endif
1113 #endif
1114 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_08_L, (MS_U16)(pDBreg->u32DualDNRBase0 >> 0), 0xFFFF); //F2_1 IPM base addr
1115 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_09_L, (MS_U16)(pDBreg->u32DualDNRBase0 >> 16), 0xFFFF);
1116 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_0E_L, (MS_U16)(pDBreg->u16DualDNROffset), 0x1FFF); //F2_1 IPM offset
1117 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_0F_L, (MS_U16)(pDBreg->u16DualDNRFetch), 0x1FFF); //F2_1 IPM fetch number
1118 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_10_L, (MS_U16)(pDBreg->u32DualOPMBase0 >> 0), 0xFFFF); //F2_1 OPM base addr
1119 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_11_L, (MS_U16)(pDBreg->u32DualOPMBase0 >> 16), 0xFFFF);
1120 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_16_L, (MS_U16)(pDBreg->u16DualOPMOffset), 0x1FFF); //F2_1 OPM offset
1121 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK52_17_L, (MS_U16)(pDBreg->u16DualOPMFetch), 0x1FFF); //F2_1 OPM fetch number
1122 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_28_L, (MS_U16)(pDBreg->u16DualDNRFetch + pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16DNRFetch), 0x1FFF); //F2 IPM total fetch
1123 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_29_L, (MS_U16)(BIT(15)|(pDBreg->u16DualOPMFetch + pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg.u16OPMFetch)), 0x1FFF | BIT(15)); //F2 OPM total fetch
1124
1125 }
1126 else
1127 {
1128 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_29_L, 0, BIT(15));
1129 #if 0 // Dual do not support switch MIU setting Dynamic.
1130 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1131 MS_U16 u16OPMLeftMiuSel = 0;
1132 MS_U16 u16OPMRightMiuSel = 0;
1133 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1134 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1135 // miu request0 IPM/OPM LSB
1136 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1137 // miu request0 IPM/OPM MSB
1138 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1139 // miu request1 IPM/OPM
1140 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1141 #endif
1142 #endif
1143 }
1144 }
1145 #endif
1146
1147 //PIP
1148 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00), 0xFFFF); // Write V length
1149 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1D_L, (MS_U16)(pDBreg->u16LBOffset&0xFF), 0x00FF);
1150 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1C_L, (MS_U16)(pDBreg->u16DispOffset&0xFF), 0x00FF);
1151 // if LB Offset > externded pixels of bottom A session,
1152 // there would be garbage on the left side of sub video
1153 if (pDBreg->u16LBOffset > SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, 0x00FF))
1154 {
1155 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_14_L, (pDBreg->u16LBOffset&0xFF), 0x00FF);
1156 }
1157
1158 #if defined(UFO_XC_HDR) && defined(UFO_XC_HDR_VERSION) && (UFO_XC_HDR_VERSION == 2)
1159 //HDR input DE Window info
1160 if (gSrcInfo[MAIN_WINDOW].bR_FBL)
1161 {
1162 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK79_08_L, (MS_U16)(gSrcInfo[MAIN_WINDOW].stCropWin.width>>00), 0x1FFF);
1163 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK79_09_L, (MS_U16)(gSrcInfo[MAIN_WINDOW].stCropWin.height>>00), 0x0FFF);
1164 }
1165 else
1166 {
1167 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK79_08_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0x1FFF);
1168 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK79_09_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0x0FFF);
1169 }
1170 #endif
1171
1172 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
1173 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
1174 pDBreg->u16H_CapSize |= 0x8000;
1175 else
1176 pDBreg->u16H_CapSize |= 0x0000;
1177
1178 //capture window
1179 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_04_L, (MS_U16)(pDBreg->u16V_CapStart>>00), 0xFFFF);
1180 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_05_L, (MS_U16)(pDBreg->u16H_CapStart>>00), 0xFFFF);
1181 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_06_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0xFFFF);
1182 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_07_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0xFFFF);
1183
1184 //Display window
1185 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, (MS_U16)(pDBreg->u16H_DisStart>>00), VOP_DISPLAY_HSTART_MASK);
1186 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), VOP_DISPLAY_HEND_MASK);
1187 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, (MS_U16)(pDBreg->u16V_DisStart>>00), 0xFFFF);
1188 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, (MS_U16)(pDBreg->u16V_DisEnd>>00), 0xFFFF);
1189
1190 // MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1191
1192 #if SUPPORT_2_FRAME_MIRROR
1193
1194 if( (gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber == IMAGE_STORE_2_FRAMES) && (!gSrcInfo[MAIN_WINDOW].bInterlace) && (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == 0))
1195 {
1196 // 2_frmae_mirror cannot work when UC on
1197
1198 //SCMI: DNR address 1
1199 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1200 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_1B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1201
1202 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_30_L, 0x4000,0xFFFF);// enable two frame mirror
1203
1204 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, 0x0001) == 0 )//compress mode
1205 {
1206 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, 0x20,0x00F0); // opm_ce_lcnt_inv
1207 }
1208 }
1209 else
1210 {
1211 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == BIT(15))
1212 {
1213 printf("@@ [%s,%5d] 2_frmae_mirror cannot work when UC on \n",__func__,__LINE__);
1214 }
1215
1216 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_30_L, 0x0000,0xFFFF);// disable two frame mirror
1217 }
1218 #endif
1219
1220 MS_U16 u16reg = 0;
1221 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1222 ||(psXCInstPri->u32DeviceID == 1))
1223 {
1224 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L);
1225 }
1226 else
1227 {
1228 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK33_32_L);
1229 }
1230
1231
1232 if(pDBreg->bOpmLcntInv_En)
1233 {
1234 u16reg |= BIT(5);
1235 }
1236 else
1237 {
1238 u16reg &= ~ BIT(5);
1239 }
1240
1241
1242 //monaco/muji 3D mode need control sub for some output format, or else the edge of object in the image may shake
1243 #if (HW_DESIGN_4K2K_VER == 4)
1244 E_XC_3D_OUTPUT_MODE e3DOutputFormat = MDrv_XC_Get_3D_Output_Mode(pInstance);
1245 if((e3DOutputFormat == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
1246 || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM) || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM_HW)
1247 || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF) || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF_HW)
1248 || (e3DOutputFormat == E_XC_3D_OUTPUT_FRAME_PACKING))
1249 {
1250 //Hal_SC_set_opm_lcnt_inv(pInstance, bopm_lcnt_inv, SUB_WINDOW);
1251 if(pDBreg->bOpmLcntInv_En)
1252 {
1253 u16reg |= BIT(4);
1254 }
1255 else
1256 {
1257 u16reg &= ~ BIT(4);
1258 }
1259 }
1260 #endif
1261
1262 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1263 ||(psXCInstPri->u32DeviceID == 1))
1264 {
1265 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, u16reg, 0xFFFF);
1266 }
1267 else
1268 {
1269 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK33_32_L, u16reg, 0xFFFF);
1270 }
1271 }
1272
_Hal_SC_fill_sub_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg)1273 static void _Hal_SC_fill_sub_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg)
1274 {
1275 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1276 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1277 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1278 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1279
1280 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd))
1281 {
1282 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
1283 }
1284 else
1285 {
1286 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(15));
1287 }
1288
1289 //H pre-scaling
1290 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_04_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>00), 0xFFFF);
1291 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_05_L, (MS_U16)(pDBreg->u32H_PreScalingRatio>>16), 0xFFFF);
1292 //V pre-scaling
1293 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_08_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>00), 0xFFFF);
1294 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK04_09_L, (MS_U16)(pDBreg->u32V_PreScalingRatio>>16), 0xFFFF);
1295
1296 //H post-scaling
1297 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_27_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>00), 0xFFFF);
1298 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_28_L, (MS_U16)(pDBreg->u32H_PostScalingRatio>>16), 0xFFFF);
1299 //V post-scaling
1300 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_29_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>00), 0xFFFF);
1301 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_2A_L, (MS_U16)(pDBreg->u32V_PostScalingRatio>>16), 0xFFFF);
1302
1303 //SCMI: vertical limitation
1304 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_58_L, (MS_U16)(pDBreg->u16VWritelimit), 0xFFFF);
1305 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5A_L, (MS_U16)(pDBreg->u32WritelimitBase>>00), 0xFFFF);
1306 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5B_L, (MS_U16)(pDBreg->u32WritelimitBase>>16), 0xFFFF);
1307 //SCMI: IPM address 0
1308 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_48_L, (MS_U16)(pDBreg->u32DNRBase0>>00), 0xFFFF);
1309 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_49_L, (MS_U16)(pDBreg->u32DNRBase0>>16), 0xFFFF);
1310 //SCMI: DNR address 1
1311 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4A_L, (MS_U16)(pDBreg->u32DNRBase1>>00), 0xFFFF);
1312 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4B_L, (MS_U16)(pDBreg->u32DNRBase1>>16), 0xFFFF);
1313 //SCMI: DNR address 2
1314 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4C_L, (MS_U16)(pDBreg->u32DNRBase2>>00), 0xFFFF);
1315 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4D_L, (MS_U16)(pDBreg->u32DNRBase2>>16), 0xFFFF);
1316 //SCMI: DNR offset
1317 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4E_L, (MS_U16)(pDBreg->u16DNROffset>>00), 0xFFFF);
1318 //SCMI: DNR fetch
1319 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_4F_L, (MS_U16)(pDBreg->u16DNRFetch>>00), 0xFFFF);
1320 //SCMI: OPM address 0
1321 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_50_L, (MS_U16)(pDBreg->u32OPMBase0>>00), 0xFFFF);
1322 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_51_L, (MS_U16)(pDBreg->u32OPMBase0>>16), 0xFFFF);
1323 //SCMI: OPM address 1
1324 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_52_L, (MS_U16)(pDBreg->u32OPMBase1>>00), 0xFFFF);
1325 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_53_L, (MS_U16)(pDBreg->u32OPMBase1>>16), 0xFFFF);
1326 //SCMI: OPM address 2
1327 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_54_L, (MS_U16)(pDBreg->u32OPMBase2>>00), 0xFFFF);
1328 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_55_L, (MS_U16)(pDBreg->u32OPMBase2>>16), 0xFFFF);
1329 //SCMI: OPM offset
1330 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_56_L, (MS_U16)(pDBreg->u16OPMOffset>>00), 0xFFFF);
1331 //SCMI: OPM fetch
1332 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_57_L, (MS_U16)(pDBreg->u16OPMFetch>>00), 0xFFFF);
1333 //PIP
1334 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_16_L, (MS_U16)(pDBreg->u16VLen>>00), 0xFFFF); // Write V length
1335 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1D_L, (MS_U16)((pDBreg->u16LBOffset&0xFF)<<8), 0xFF00);
1336 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_1C_L, (MS_U16)((pDBreg->u16DispOffset&0xFF)<<8), 0xFF00);
1337
1338 /// before enable ML bit mask feature, the capture size for 2P setting BK03_07[15] need to be considered
1339 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, BIT(15)))
1340 pDBreg->u16H_CapSize |= 0x8000;
1341 else
1342 pDBreg->u16H_CapSize |= 0x0000;
1343
1344 // capture window
1345 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_04_L, (MS_U16)(pDBreg->u16V_CapStart>>00), 0xFFFF);
1346 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_05_L, (MS_U16)(pDBreg->u16H_CapStart>>00), 0xFFFF);
1347 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_06_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0xFFFF);
1348 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_07_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0xFFFF);
1349
1350 //Display window
1351 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_07_L, (MS_U16)(pDBreg->u16H_DisStart>>00), 0xFFFF);
1352 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_08_L, (MS_U16)(pDBreg->u16H_DisEnd>>00), 0xFFFF);
1353 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_09_L, (MS_U16)(pDBreg->u16V_DisStart>>00), 0xFFFF);
1354 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_0A_L, (MS_U16)(pDBreg->u16V_DisEnd>>00), 0xFFFF);
1355
1356 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_5C_L, 0x0, 0x1FFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1357
1358 MS_U16 u16reg = 0;
1359 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1360 ||(psXCInstPri->u32DeviceID == 1))
1361 {
1362 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L);
1363 }
1364 else
1365 {
1366 u16reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK33_32_L);
1367 }
1368
1369 if(pDBreg->bOpmLcntInv_En)
1370 {
1371 u16reg |= BIT(4);
1372 }
1373 else
1374 {
1375 u16reg &= ~ BIT(4);
1376 }
1377
1378 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1379 ||(psXCInstPri->u32DeviceID == 1))
1380 {
1381 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK08_32_L, u16reg, 0xFFFF);
1382 }
1383 else
1384 {
1385 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK33_32_L, u16reg, 0xFFFF);
1386 }
1387 }
1388
Hal_SC_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1389 void Hal_SC_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow )
1390 {
1391 _MLOAD_ENTRY(pInstance);
1392 #ifdef UFO_XC_SUPPORT_DUAL_MIU
1393 static MS_BOOL bEnable = FALSE;
1394 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1395 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1396 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1397 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1398 #endif
1399 if( eWindow == MAIN_WINDOW )
1400 {
1401 #ifdef UFO_XC_SUPPORT_DUAL_MIU
1402 if(!IsEnableDualMode(MAIN_WINDOW) && bEnable)
1403 {
1404 MDrv_XC_wait_output_vsync(pInstance, 1, 50, eWindow);
1405 /// Before reset need to mask the XC R/W
1406 MDrv_MIU_MaskReq(0, MIU_CLIENT_SC_IPMAIN_RW);
1407 MDrv_MIU_MaskReq(1, MIU_CLIENT_SC_OPMAIN_RW);
1408 MsOS_DelayTask(1);
1409 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, 0x00, BIT(15));
1410 MsOS_DelayTask(1);
1411 MDrv_MIU_UnMaskReq(0, MIU_CLIENT_SC_IPMAIN_RW);
1412 MDrv_MIU_UnMaskReq(1, MIU_CLIENT_SC_OPMAIN_RW);
1413 MsOS_DelayTask(1);
1414 bEnable = FALSE;
1415 }
1416 #endif
1417 _Hal_SC_fill_main_sw_db_burst(pInstance, pDBreg);
1418 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1419 #ifdef UFO_XC_SUPPORT_DUAL_MIU
1420 if (IsEnableDualMode(MAIN_WINDOW))
1421 {
1422 MDrv_XC_wait_output_vsync(pInstance, 1, 50, eWindow);
1423 /// Before reset need to mask the XC R/W
1424 MDrv_MIU_MaskReq(0, MIU_CLIENT_SC_IPMAIN_RW);
1425 MDrv_MIU_MaskReq(1, MIU_CLIENT_SC_OPMAIN_RW);
1426 MsOS_DelayTask(1);
1427 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, BIT(15), BIT(15));
1428 MsOS_DelayTask(1);
1429 MDrv_MIU_UnMaskReq(0, MIU_CLIENT_SC_IPMAIN_RW);
1430 MDrv_MIU_UnMaskReq(1, MIU_CLIENT_SC_OPMAIN_RW);
1431 MsOS_DelayTask(1);
1432 bEnable = TRUE;
1433 }
1434 #endif
1435 }
1436 else
1437 {
1438 _Hal_SC_fill_sub_sw_db_burst(pInstance, pDBreg);
1439 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1440 }
1441
1442 _MLOAD_RETURN(pInstance);
1443 }
1444
Hal_SC_dual_sw_db_burst(void * pInstance,P_SC_SWDB_INFO pMainDBreg,P_SC_SWDB_INFO pSubDBreg)1445 void Hal_SC_dual_sw_db_burst(void *pInstance, P_SC_SWDB_INFO pMainDBreg, P_SC_SWDB_INFO pSubDBreg)
1446 {
1447 _MLOAD_ENTRY(pInstance);
1448
1449 _Hal_SC_fill_main_sw_db_burst(pInstance, pMainDBreg);
1450 _Hal_SC_fill_sub_sw_db_burst(pInstance, pSubDBreg);
1451 MDrv_XC_MLoad_Fire(pInstance, TRUE);
1452
1453 _MLOAD_RETURN(pInstance);
1454 }
1455
Hal_SC_sw_db(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1456 void Hal_SC_sw_db(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow )
1457 {
1458 MS_U32 u32LcentInvReg = 0;
1459 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1460 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1461 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1462 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1463
1464 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] bDynamicScalingEnable%d \n",__func__,__LINE__,pXCResourcePrivate->sthal_SC.bDynamicScalingEnable);
1465
1466 if( eWindow == MAIN_WINDOW )
1467 {
1468 if(Hal_SC_is_extra_req_en(pInstance, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd, NULL, NULL))
1469 {
1470 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, BIT(15), BIT(15));
1471 }
1472 else
1473 {
1474 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, 0, BIT(15));
1475 }
1476
1477 // H pre-scaling
1478 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_04_L, pDBreg->u32H_PreScalingRatio);
1479 // V pre-scaling
1480 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_08_L, pDBreg->u32V_PreScalingRatio);
1481 // H post-scaling
1482 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L, pDBreg->u32H_PostScalingRatio);
1483 // V post-scaling
1484 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_09_L, pDBreg->u32V_PostScalingRatio);
1485
1486 //SCMI
1487 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, pDBreg->u16VWritelimit); // Set vertical limitation
1488 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pDBreg->u32DNRBase1);
1489
1490 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, pDBreg->u32DNRBase0); // input address0
1491 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L, pDBreg->u32DNRBase1); // input address1
1492 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0C_L, pDBreg->u32DNRBase2); // input address2
1493
1494 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, pDBreg->u16DNROffset);// input Offset
1495 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, pDBreg->u16DNRFetch); // input fetch
1496 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1497
1498
1499 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L, pDBreg->u32OPMBase0); // output address0
1500 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L, pDBreg->u32OPMBase1); // output address1
1501 // SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_14_L, pDBreg->u32OPMBase2); // output address2
1502 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, pDBreg->u16OPMOffset); // output offset
1503 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, pDBreg->u16OPMFetch); // output fetch
1504
1505 #ifdef UFO_XC_SUPPORT_DUAL_MIU
1506 if (psXCInstPri->u32DeviceID == 0) // Dual miu just support sc0 main window for main window.
1507 {
1508 if(IsEnableDualMode(eWindow))
1509 {
1510 #if 0 // Dual miu do not support switch miu select dynamicly.
1511 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1512 MS_U16 u16OPMLeftMiuSel = 0;
1513 MS_U16 u16OPMRightMiuSel = 0;
1514 if(IsHMirrorMode(eWindow))
1515 {
1516 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1517 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], TRUE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1518 }
1519 else
1520 {
1521 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1522 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1523 }
1524 // miu request0 IPM/OPM LSB
1525 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1526 // miu request0 IPM/OPM MSB
1527 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1528 // miu request1 IPM/OPM
1529 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1530 #else
1531 _Hal_SC_adjust_swap_miu_setting(pInstance,pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW]);
1532 #endif
1533 #endif
1534 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_08_L, pDBreg->u32DualDNRBase0 >> 0, 0xFFFF); //F2_1 IPM base addr
1535 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_09_L, pDBreg->u32DualDNRBase0 >> 16, 0x03FF);
1536 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_0E_L, pDBreg->u16DualDNROffset, 0x1FFF); //F2_1 IPM offset
1537 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_0F_L, pDBreg->u16DualDNRFetch, 0x1FFF); //F2_1 IPM fetch number
1538 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_10_L, pDBreg->u32DualOPMBase0 >> 0, 0xFFFF); //F2_1 OPM base addr
1539 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_11_L, pDBreg->u32DualOPMBase0 >> 16, 0x03FF);
1540 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_16_L, pDBreg->u16DualOPMOffset, 0x1FFF); //F2_1 OPM offset
1541 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_17_L, pDBreg->u16DualOPMFetch, 0x1FFF); //F2_1 OPM fetch number
1542 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_28_L, pDBreg->u16DualDNRFetch + pDBreg->u16DNRFetch, 0x1FFF); //F2 IPM total fetch
1543 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, pDBreg->u16DualOPMFetch + pDBreg->u16OPMFetch, 0x1FFF); //F2 OPM total fetch
1544 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, BIT(15), BIT(15)); //Enable SCMI MIU Dual mode
1545 }
1546 else
1547 {
1548 SC_W2BYTEMSK(0, REG_SC_BK11_29_L, 0, BIT(15));
1549 #if 0 // Dual miu do not support switch miu dynamicly.
1550 #if (MIU_SEL_USE_XC_INTERNAL == FALSE)
1551 MS_U16 u16OPMLeftMiuSel = 0;
1552 MS_U16 u16OPMRightMiuSel = 0;
1553 _Hal_SC_adjust_dual_miu_setting(pInstance, pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW],
1554 pXCResourcePrivate->stdrvXC_Scaling._u32PreDualFBAddress[MAIN_WINDOW], FALSE, &u16OPMLeftMiuSel, &u16OPMRightMiuSel);
1555 // miu request0 IPM/OPM LSB
1556 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, ((u16OPMLeftMiuSel & BIT(0)) << 1)|(u16OPMLeftMiuSel & BIT(0)), BIT(1)| BIT(0));
1557 // miu request0 IPM/OPM MSB
1558 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_18_L, (u16OPMLeftMiuSel & BIT(1))|((u16OPMLeftMiuSel & BIT(1)) >> 1), BIT(1)| BIT(0));
1559 // miu request1 IPM/OPM
1560 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_19_L, (u16OPMRightMiuSel << 2)| u16OPMRightMiuSel , BIT(3)| BIT(2) | BIT(1)| BIT(0));
1561 #else
1562 _Hal_SC_adjust_swap_miu_setting(pInstance,pXCResourcePrivate->stdrvXC_Scaling._au32PreFBAddress[MAIN_WINDOW]);
1563 #endif
1564 #endif
1565 }
1566 }
1567 #endif
1568
1569 //PIP
1570 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_15_L, pDBreg->u16VLen); // Write V length
1571 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1D_L, (pDBreg->u16LBOffset&0xFF), 0xFF);
1572 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1C_L, (pDBreg->u16DispOffset&0xFF), 0xFF);
1573 // if LB Offset > externded pixels of bottom A session,
1574 // there would be garbage on the left side of sub video
1575 if (pDBreg->u16LBOffset > SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, 0xFF))
1576 {
1577 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_14_L, (pDBreg->u16LBOffset&0xFF), 0xFF);
1578 }
1579
1580 #if defined(UFO_XC_HDR) && defined(UFO_XC_HDR_VERSION) && (UFO_XC_HDR_VERSION == 2)
1581 //HDR input DE Window info
1582 if (gSrcInfo[MAIN_WINDOW].bR_FBL)
1583 {
1584 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK79_08_L, (MS_U16)(gSrcInfo[MAIN_WINDOW].stCropWin.width>>00), 0x1FFF);
1585 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK79_09_L, (MS_U16)(gSrcInfo[MAIN_WINDOW].stCropWin.height>>00), 0x0FFF);
1586 }
1587 else
1588 {
1589 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK79_08_L, (MS_U16)(pDBreg->u16H_CapSize>>00), 0x1FFF);
1590 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK79_09_L, (MS_U16)(pDBreg->u16V_CapSize>>00), 0x0FFF);
1591 }
1592 #endif
1593
1594 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
1595 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
1596 pDBreg->u16H_CapSize |= 0x8000;
1597 else
1598 pDBreg->u16H_CapSize |= 0x0000;
1599
1600 // capture window
1601 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_04_L, pDBreg->u16V_CapStart); // Capture V start
1602 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_05_L, pDBreg->u16H_CapStart); // Capture H start
1603 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, pDBreg->u16V_CapSize); // Capture V size
1604 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, pDBreg->u16H_CapSize); // Capture H size
1605
1606 //Display window
1607 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pDBreg->u16H_DisStart); // Display H start
1608 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pDBreg->u16H_DisEnd); // Display H end
1609 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pDBreg->u16V_DisStart); // Display V start
1610 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pDBreg->u16V_DisEnd); // Display V end
1611
1612 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_1C_L, 0x0, 0xFFFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1613
1614 // 2_frame_mirror setting
1615 #if SUPPORT_2_FRAME_MIRROR
1616 // 2_frmae_mirror cannot work when UC on
1617 if( (gSrcInfo[eWindow].Status2.eFrameStoreNumber == IMAGE_STORE_2_FRAMES) && (!gSrcInfo[eWindow].bInterlace) && (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == 0))
1618 {
1619 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pDBreg->u32DNRBase1); // IPM base1
1620 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0x4000, BIT(14)); // enable two frame mirror
1621
1622 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, 0x0001) == 0 )//compress mode
1623 {
1624 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, 0X20 ,0x00F0 ); // opm_ce_lcnt_inv
1625 }
1626 }
1627 else
1628 {
1629 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(15)) == BIT(15))
1630 {
1631 printf("@@ [%s,%5d] 2_frmae_mirror cannot work when UC on \n",__func__,__LINE__);
1632 }
1633
1634 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, 0x00 , BIT(14)); // disable two frame mirror
1635 }
1636 #endif
1637 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1638 ||(psXCInstPri->u32DeviceID == 1))
1639 {
1640 u32LcentInvReg = REG_SC_BK08_32_L;
1641 }
1642 else
1643 {
1644 u32LcentInvReg = REG_SC_BK33_32_L;
1645 }
1646
1647 if(pDBreg->bOpmLcntInv_En)
1648 {
1649 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(5), BIT(5));
1650 }
1651 else
1652 {
1653 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(5));
1654 }
1655
1656 //monaco/muji 3D mode need control sub for some output format, or else the edge of object in the image may shake
1657 #if (HW_DESIGN_4K2K_VER == 4)
1658 E_XC_3D_OUTPUT_MODE e3DOutputFormat = MDrv_XC_Get_3D_Output_Mode(pInstance);
1659 if((e3DOutputFormat == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
1660 || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM) || (e3DOutputFormat == E_XC_3D_OUTPUT_TOP_BOTTOM_HW)
1661 || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF) || (e3DOutputFormat == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF_HW)
1662 || (e3DOutputFormat == E_XC_3D_OUTPUT_FRAME_PACKING))
1663 {
1664 //Hal_SC_set_opm_lcnt_inv(pInstance, bopm_lcnt_inv, SUB_WINDOW);
1665 if(pDBreg->bOpmLcntInv_En)
1666 {
1667 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(4), BIT(4));
1668 }
1669 else
1670 {
1671 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(4));
1672 }
1673 }
1674 #endif
1675 }
1676 else
1677 {
1678 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL, &pDBreg->u16H_DisStart, &pDBreg->u16H_DisEnd))
1679 {
1680 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, BIT(15), BIT(15));
1681 }
1682 else
1683 {
1684 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L, 0, BIT(15));
1685 }
1686
1687 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_04_L, pDBreg->u32H_PreScalingRatio); // H pre-scaling
1688 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_08_L, pDBreg->u32V_PreScalingRatio); // V pre-scaling
1689
1690 //HVSP
1691 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_27_L, pDBreg->u32H_PostScalingRatio); // H post-scaling
1692 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_29_L, pDBreg->u32V_PostScalingRatio); // V post-scaling
1693
1694 //SCMI
1695 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_58_L, pDBreg->u16VWritelimit); // Set vertical limitation
1696 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_5A_L, pDBreg->u32WritelimitBase);
1697 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L, pDBreg->u32DNRBase0); // input address0
1698 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4A_L, pDBreg->u32DNRBase1); // input address1
1699 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4C_L, pDBreg->u32DNRBase2); // input address2
1700 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, pDBreg->u16DNROffset);// input Offset
1701 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, pDBreg->u16DNRFetch); // input fetch
1702 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L, pDBreg->u32OPMBase0); // output address0
1703 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L, pDBreg->u32OPMBase1); // output address1
1704 //SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_54_L, pDBreg->u32OPMBase2); // output address2
1705 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, pDBreg->u16OPMOffset); // output offset
1706 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, pDBreg->u16OPMFetch); // output fetch
1707 //PIP
1708 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_16_L, pDBreg->u16VLen); // Write V length
1709 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1D_L, (pDBreg->u16LBOffset&0xFF)<<8, 0xFF00);
1710 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1C_L, (pDBreg->u16DispOffset&0xFF)<<8, 0xFF00);
1711
1712 // capture window
1713 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_04_L, pDBreg->u16V_CapStart); // Capture V start
1714 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_05_L, pDBreg->u16H_CapStart); // Capture H start
1715 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, pDBreg->u16V_CapSize); // Capture V size
1716 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, pDBreg->u16H_CapSize); // Capture H size
1717
1718 //Display window
1719 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L, pDBreg->u16H_DisStart); // Display H start
1720 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L, pDBreg->u16H_DisEnd); // Display H end
1721 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L, pDBreg->u16V_DisStart); // Display V start
1722 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L, pDBreg->u16V_DisEnd); // Display V end
1723
1724 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_5C_L, 0x0, 0x1FFF); //always disable IP H mirror line offset note:ds will enable this register at vdec firmware
1725
1726 if (((psXCInstPri->u32DeviceID == 0) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
1727 ||(psXCInstPri->u32DeviceID == 1))
1728 {
1729 u32LcentInvReg = REG_SC_BK08_32_L;
1730 }
1731 else
1732 {
1733 u32LcentInvReg = REG_SC_BK33_32_L;
1734 }
1735
1736 if(pDBreg->bOpmLcntInv_En)
1737 {
1738 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, BIT(4), BIT(4));
1739 }
1740 else
1741 {
1742 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32LcentInvReg, 0x00, BIT(4));
1743 }
1744 }
1745 }
1746
1747 #if (defined (ANDROID) && defined(UFO_XC_DS_PQ))
1748 extern stDS_PQ_REG DS_REG[DS_PQ_MAX_NUM];
1749 extern MS_U16 DS_REG_CNT;
1750 #endif
Hal_SC_SWDS_AddCmd(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1751 void Hal_SC_SWDS_AddCmd(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow)
1752 {
1753 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1754 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1755 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1756 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1757
1758 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] eWindow:%d bDynamicScalingEnable%d \n",__func__,__LINE__,eWindow,pXCResourcePrivate->sthal_SC.bDynamicScalingEnable);
1759 #if (defined (ANDROID) && defined(UFO_XC_DS_PQ))
1760 MS_U16 cnt_x = 0;
1761 MS_U16 u16TempRegVal = 0;
1762 #endif
1763
1764 XC_DS_CMDCNT PSTXC_DS_CMDCNT;
1765
1766 PSTXC_DS_CMDCNT.u16CMDCNT_IPM =0;
1767 PSTXC_DS_CMDCNT.u16CMDCNT_IPS =0;
1768 PSTXC_DS_CMDCNT.u16CMDCNT_OPM =0;
1769 PSTXC_DS_CMDCNT.u16CMDCNT_OPS =0;
1770
1771 if(eWindow == MAIN_WINDOW)
1772 {
1773 if(pXCResourcePrivate->sthal_SC.bDynamicScalingEnable)
1774 {
1775 pXCResourcePrivate->sthal_SC.u8DynamicScalingNextIndex[MAIN_WINDOW] = pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[MAIN_WINDOW];
1776
1777 //Command Priority:
1778 //1.GOP
1779 //2.MVOP
1780 //3.XC
1781
1782 MS_U32 ActiveSWClearEn = 0;
1783 MS_U32 u32SW_Reset_Enable = 0;
1784 //ActiveSWClearEn enable in first DS IP command ;
1785 u32SW_Reset_Enable = 0x0400; // bit10: reg_ds_ipm_active_sel: 0:HW 1:SW
1786 ActiveSWClearEn = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK1F_17_L, 0xFFFF);
1787 ActiveSWClearEn |= u32SW_Reset_Enable;
1788
1789 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK1F_17_L,(MS_U16)(ActiveSWClearEn),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1790
1791 //XC_PRINTF("[%s,%5d] bR_FBL:%d bFBL:%d \n",__func__,__LINE__,gSrcInfo[MAIN_WINDOW].bR_FBL,gSrcInfo[MAIN_WINDOW].bFBL);
1792 //XC_PRINTF("[%s,%5d] Crop(x,y,w,h)=(%d,%d,%d,%d) \n",__func__,__LINE__,gSrcInfo[eWindow].stCropWin.x,gSrcInfo[eWindow].stCropWin.y,gSrcInfo[eWindow].stCropWin.width,gSrcInfo[eWindow].stCropWin.height);
1793 #ifdef UFO_XC_FB_LEVEL
1794 if((gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_FBL)
1795 || (gSrcInfo[MAIN_WINDOW].eFBLevel == E_XC_FB_LEVEL_RFBL_DI)
1796 )
1797 #else
1798 if((gSrcInfo[MAIN_WINDOW].bR_FBL) || (gSrcInfo[MAIN_WINDOW].bFBL))//set MVOP crop info
1799 #endif
1800 {
1801 // GET MVOP crop info first
1802 MVOP_Handle stHdl = { E_MVOP_MODULE_MAIN };
1803 MVOP_XCGetCrop stCropInfo;
1804 stCropInfo.u16XStart = gSrcInfo[eWindow].stCropWin.x;
1805 stCropInfo.u16YStart = gSrcInfo[eWindow].stCropWin.y;
1806 stCropInfo.u16XSize = gSrcInfo[eWindow].stCropWin.width;
1807 stCropInfo.u16YSize = gSrcInfo[eWindow].stCropWin.height;
1808
1809 MDrv_MVOP_GetCommand(&stHdl, E_MVOP_CMD_GET_CROP_FOR_XC, &stCropInfo, sizeof(MVOP_XCGetCrop));
1810
1811 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_START,stCropInfo.u16XStart,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0840XXXX
1812 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_START,0x2000|stCropInfo.u16YStart,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0841XXXX
1813 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_SIZE,stCropInfo.u16XSize,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0842XXXX
1814 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_SIZE,stCropInfo.u16YSize,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0843XXXX
1815 pDBreg->u16LBOffset = 0; // mvop do crop, align in 2pixel, so xc don't need crop
1816 }
1817 else
1818 {
1819 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_START,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0840XXXX
1820 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_START,0x2000,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0841XXXX
1821 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_H_SIZE,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0842XXXX
1822 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_MVOP_CROP_V_SIZE,0x0,DS_IP,DS_MVOP,&PSTXC_DS_CMDCNT); //0xFFFF000A 0843XXXX
1823 }
1824
1825 //H pre-scaling
1826 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_04_L,(MS_U16)(pDBreg->u32H_PreScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8104XXXX
1827 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_05_L,(MS_U16)(pDBreg->u32H_PreScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8105XXXX
1828 //V pre-scaling
1829 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_08_L,(MS_U16)(pDBreg->u32V_PreScalingRatio>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8108XXXX
1830 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_09_L,(MS_U16)(pDBreg->u32V_PreScalingRatio>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8109XXXX
1831 //H post-scaling
1832 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_07_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9187XXXX
1833 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_08_L,(MS_U16)(pDBreg->u32H_PostScalingRatio>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9188XXXX
1834 //V post-scaling
1835 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_09_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 9189XXXX
1836 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK23_0A_L,(MS_U16)(pDBreg->u32V_PostScalingRatio>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 918AXXXX
1837
1838 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_18_L,(MS_U16)(pDBreg->u16VWritelimit>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8918XXXX
1839
1840 if(IsVMirrorMode(MAIN_WINDOW))
1841 {
1842 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_08_L,(MS_U16)(pDBreg->u32DNRBase0>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1843 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_09_L,(MS_U16)(pDBreg->u32DNRBase0>>16),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1844 }
1845 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_0F_L,(MS_U16)(pDBreg->u16DNRFetch>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 890FXXXX
1846
1847 //H_mirror_offset
1848 if(IsHMirrorMode(MAIN_WINDOW)||IsVMirrorMode(MAIN_WINDOW))
1849 {
1850 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] VB_width:%d framNum:%d u8BitPerPixel:%d \n",__func__,__LINE__,gSrcInfo[MAIN_WINDOW].Status2.u16XCVirtualBoxWidth,MDrv_XC_TransFrameNumToFactor(pInstance,gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber, gSrcInfo[MAIN_WINDOW].bLinearMode, _FIELD_PACKING_MODE_SUPPORTED),gSrcInfo[MAIN_WINDOW].u8BitPerPixel);
1851
1852 MS_U32 H_mirror_offset;
1853 H_mirror_offset = (gSrcInfo[MAIN_WINDOW].Status2.u16XCVirtualBoxWidth * gSrcInfo[MAIN_WINDOW].u8BitPerPixel / 8 * MDrv_XC_TransFrameNumToFactor(pInstance,gSrcInfo[MAIN_WINDOW].Status2.eFrameStoreNumber, gSrcInfo[MAIN_WINDOW].bLinearMode, _FIELD_PACKING_MODE_SUPPORTED)) / BYTE_PER_WORD;
1854
1855 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_1C_L,H_mirror_offset,DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 891CXXXX
1856 }
1857 else
1858 {
1859 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_1C_L,0x0000,DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 891CXXXX
1860 }
1861
1862 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_10_L, (MS_U16)(pDBreg->u32OPMBase0>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8910XXXX
1863 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_11_L,(MS_U16)(pDBreg->u32OPMBase0>>16),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM base0 //0xFFFF0009 8911XXXX
1864 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK12_17_L,(MS_U16)(pDBreg->u16OPMFetch>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // OPM fetch //0xFFFF0009 8917XXXX
1865 //Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // V Len
1866 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
1867 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_1D_L,(MS_U16)(pDBreg->u16LBOffset&0xFF),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //LBOffset //0xFFFF0009 901DXXXX
1868 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK20_15_L, (MS_U16)(pDBreg->u16VLen>>00),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); // V Len //0xFFFF0009 9015XXXX
1869
1870 #if defined(UFO_XC_HDR) && defined(UFO_XC_HDR_VERSION) && (UFO_XC_HDR_VERSION == 2)
1871 //HDR input DE Window info
1872 if (gSrcInfo[MAIN_WINDOW].bR_FBL)
1873 {
1874 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK79_08_L,(MS_U16)(gSrcInfo[MAIN_WINDOW].stCropWin.width>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1875 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK79_09_L,(MS_U16)(gSrcInfo[MAIN_WINDOW].stCropWin.height>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1876 }
1877 else
1878 {
1879 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK79_08_L,(MS_U16)(pDBreg->u16H_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1880 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK79_09_L,(MS_U16)(pDBreg->u16V_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1881 }
1882 #endif
1883
1884 //Cap info
1885 /// before enable ML bit mask feature, the capture size for 2P setting BK01_07[15] need to be considered
1886 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, BIT(15)))
1887 pDBreg->u16H_CapSize |= 0x8000;
1888 else
1889 pDBreg->u16H_CapSize |= 0x0000;
1890
1891 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK01_06_L,(MS_U16)(pDBreg->u16V_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8086XXXX
1892 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK01_07_L,(MS_U16)(pDBreg->u16H_CapSize>>00),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);//0xFFFF0009 8087XXXX
1893
1894 //Disp info
1895 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_08_L,(MS_U16)(pDBreg->u16H_DisStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8808XXXX
1896 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_09_L,(MS_U16)(pDBreg->u16H_DisEnd),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 8809XXXX
1897 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0A_L,(MS_U16)(pDBreg->u16V_DisStart),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880AXXXX
1898 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK10_0B_L,(MS_U16)(pDBreg->u16V_DisEnd),DS_OP,DS_XC,&PSTXC_DS_CMDCNT); //0xFFFF0009 880BXXXX
1899
1900 #if (SUPPORT_KERNEL_DS == 0)//if SUPPORT_KERNEL_DS is true,this cmd will be set in kernel ds
1901 //toggle reg_ds_ipm_active_set in last DS IP command
1902 MS_U32 u32SW_Reset_IPM = 0;
1903 u32SW_Reset_IPM = 0x0100 ;//bit8 : reg_ds_ipm_active_set
1904 ActiveSWClearEn |= u32SW_Reset_IPM;
1905 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK1F_17_L,(MS_U16)(ActiveSWClearEn),DS_IP,DS_XC,&PSTXC_DS_CMDCNT);
1906 #endif
1907 #if (defined (ANDROID) && defined(UFO_XC_DS_PQ))
1908 if(DS_REG_CNT > DS_PQ_MAX_NUM)
1909 {
1910 MS_ASSERT(0);
1911 }
1912 if(eWindow != MAIN_WINDOW)
1913 {
1914 MS_ASSERT(0);
1915 }
1916 for(cnt_x = 0 ;cnt_x < DS_REG_CNT; cnt_x++)
1917 {
1918 u16TempRegVal = SC_R2BYTE(psXCInstPri->u32DeviceID, DS_REG[cnt_x].u16Addr);
1919 u16TempRegVal = (u16TempRegVal & ~DS_REG[cnt_x].u16Mask) | DS_REG[cnt_x].u16Value;
1920 Hal_SC_WriteSWDSCommand(pInstance,eWindow,DS_REG[cnt_x].u16Addr,u16TempRegVal,DS_OP,DS_XC,&PSTXC_DS_CMDCNT);
1921 }
1922 DS_REG_CNT = 0;
1923 #endif
1924 //MS_U8 u8MaxCmdCnt = pXCResourcePrivate->sthal_SC.u8DynamicScalingIndexDepth * 2;// It has two 64bit commands per MIU bus width
1925 MS_U32 u32MaxCmdCnt = pXCResourcePrivate->sthal_SC.u16DynamicScalingIndexDepth_Ext * 2;// It has two 64bit commands per MIU bus width
1926
1927 //XC_PRINTF("[%s,%5d] u16CMDCNT_IPM:%d u32MaxCmdCnt:%d \n",__func__,__LINE__,PSTXC_DS_CMDCNT.u16CMDCNT_IPM,u32MaxCmdCnt);
1928 //XC_PRINTF("[%s,%5d] u16CMDCNT_OPM:%d u32MaxCmdCnt:%d \n",__func__,__LINE__,PSTXC_DS_CMDCNT.u16CMDCNT_OPM,u32MaxCmdCnt);
1929 if(PSTXC_DS_CMDCNT.u16CMDCNT_IPM < u32MaxCmdCnt)
1930 {
1931 Hal_SC_Add_NullCommand(pInstance,MAIN_WINDOW,DS_IP,&PSTXC_DS_CMDCNT);
1932 }
1933 if(PSTXC_DS_CMDCNT.u16CMDCNT_OPM < u32MaxCmdCnt)
1934 {
1935 Hal_SC_Add_NullCommand(pInstance,MAIN_WINDOW,DS_OP,&PSTXC_DS_CMDCNT);
1936 }
1937
1938 }
1939 }
1940 }
1941
Hal_SC_SWDS_Fire(void * pInstance,P_SC_SWDB_INFO pDBreg,SCALER_WIN eWindow)1942 void Hal_SC_SWDS_Fire(void *pInstance, P_SC_SWDB_INFO pDBreg, SCALER_WIN eWindow)
1943 {
1944 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1945 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1946 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
1947 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
1948
1949 pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow]++;
1950 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] CurIdx:%d \n",__func__,__LINE__,(int)pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow]);
1951
1952 pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[eWindow] = pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex[eWindow] % DS_BUFFER_NUM_EX;
1953 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"[%s,%5d] [DS] CurIdx_Ring:%d \n",__func__,__LINE__,(int)pXCResourcePrivate->sthal_SC.u8DynamicScalingCurrentIndex_Ring[eWindow])
1954 }
1955
Hal_SC_VIP_Peaking_Setting(void * pInstance,SCALER_WIN eWindow)1956 E_APIXC_ReturnValue Hal_SC_VIP_Peaking_Setting(void *pInstance, SCALER_WIN eWindow)
1957 {
1958 UNUSED(eWindow);
1959 return E_APIXC_RET_FAIL_FUN_NOT_SUPPORT;
1960 }
1961
Hal_SC_support_source_to_ve(void * pInstance,MS_U16 * pOutputCapability)1962 E_APIXC_ReturnValue Hal_SC_support_source_to_ve(void *pInstance, MS_U16* pOutputCapability)
1963 {
1964 *pOutputCapability = E_XC_IP | E_XC_OP2 | E_XC_OVERLAP;
1965 return E_APIXC_RET_OK;
1966 }
1967
Hal_SC_set_output_capture_enable(void * pInstance,MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)1968 E_APIXC_ReturnValue Hal_SC_set_output_capture_enable(void *pInstance, MS_BOOL bEnable,E_XC_SOURCE_TO_VE eSourceToVE)
1969 {
1970 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
1971 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
1972 MS_BOOL bCaptureEna;
1973 MS_U16 u16CaptureSrc;
1974 // Current only support IP and OP2
1975 bCaptureEna = bEnable;
1976 switch(eSourceToVE)
1977 {
1978 case E_XC_VOP2:
1979 case E_XC_OVERLAP: // compatible to previous IC, overlap is before osd blending
1980 u16CaptureSrc = 0;
1981 break;
1982 case E_XC_OP2:
1983 u16CaptureSrc = 1;
1984 break;
1985 case E_XC_BRI:
1986 u16CaptureSrc = 3;
1987 break;
1988 default:
1989 u16CaptureSrc = 0;
1990 bCaptureEna = FALSE;
1991 break;
1992 }
1993
1994 if(bCaptureEna)
1995 {
1996 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(11), BIT(11)); // Disable
1997 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, u16CaptureSrc<<4, BMASK(7:4)); // Disable
1998 }
1999 else
2000 {
2001 //DIP and VE Opcapture both need enable this bit, so dont disable it.
2002 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0, BIT(11)); // Disable
2003 }
2004 return E_APIXC_RET_OK; // Support Scaler OP -> VE
2005 }
2006
2007 /******************************************************************************/
2008 ///Set output DE window size
2009 ///@param pstWindow \b IN
2010 ///- pointer to window information
2011 /******************************************************************************/
Hal_SC_set_de_window(void * pInstance,XC_PANEL_INFO * pPanel_Info)2012 void Hal_SC_set_de_window(void *pInstance, XC_PANEL_INFO *pPanel_Info)
2013 {
2014 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2015 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2016 #ifdef new_chakra
2017 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, pPanel_Info->u16HStart); // DE H start
2018 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, pPanel_Info->u16HStart + pPanel_Info->u16Width - 1); // DE H end
2019 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pPanel_Info->u16VStart); // DE V start
2020 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pPanel_Info->u16VStart + pPanel_Info->u16Height - 1); // DE V end
2021 #else
2022 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L, pPanel_Info->u16HStart); // DE H start
2023 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L, pPanel_Info->u16HStart + pPanel_Info->u16Width - 1); // DE H end
2024 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L, pSrcInfo->u8DE_V_Start); // DE V start
2025 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L, pSrcInfo->u16DE_V_End); // DE V end
2026 #endif
2027 }
2028
Hal_SC_get_disp_de_window(void * pInstance,MS_WINDOW_TYPE * pWin)2029 void Hal_SC_get_disp_de_window(void *pInstance, MS_WINDOW_TYPE *pWin)
2030 {
2031 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2032 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2033 pWin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_04_L);
2034 pWin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_06_L);
2035 pWin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_05_L) - pWin->x + 1;
2036 pWin->height= SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_07_L) - pWin->y + 1;
2037 }
2038
Hal_SC_Get_DNRBase0(void * pInstance,SCALER_WIN eWindow)2039 MS_PHY Hal_SC_Get_DNRBase0(void *pInstance, SCALER_WIN eWindow)
2040 {
2041 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2042 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2043 if(eWindow == MAIN_WINDOW)
2044 {
2045 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L); // input address0
2046 }
2047 else
2048 {
2049 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L); // input address0
2050 }
2051 }
2052
Hal_SC_Get_DNRBase1(void * pInstance,SCALER_WIN eWindow)2053 MS_PHY Hal_SC_Get_DNRBase1(void *pInstance, SCALER_WIN eWindow)
2054 {
2055 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2056 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2057 if(eWindow == MAIN_WINDOW)
2058 {
2059 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L); // input address1
2060 }
2061 else
2062 {
2063 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4A_L); // input address1
2064 }
2065 }
2066
Hal_SC_Get_OPMBase0(void * pInstance,SCALER_WIN eWindow)2067 MS_PHY Hal_SC_Get_OPMBase0(void *pInstance, SCALER_WIN eWindow)
2068 {
2069 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2070 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2071 if(eWindow == MAIN_WINDOW)
2072 {
2073 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L); // output address0
2074 }
2075 else
2076 {
2077 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L); // output address0
2078 }
2079 }
2080
Hal_SC_Get_OPMBase1(void * pInstance,SCALER_WIN eWindow)2081 MS_PHY Hal_SC_Get_OPMBase1(void *pInstance, SCALER_WIN eWindow)
2082 {
2083 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2084 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2085 if(eWindow == MAIN_WINDOW)
2086 {
2087 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L); // output address1
2088 }
2089 else
2090 {
2091 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L); // output address1
2092 }
2093 }
2094
Hal_SC_Get_FRCMBaseAddr(void * pInstance,MS_U8 u8id,SCALER_WIN eWindow)2095 MS_PHY Hal_SC_Get_FRCMBaseAddr(void *pInstance, MS_U8 u8id,SCALER_WIN eWindow)
2096 {
2097 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2098 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2099 if(eWindow == MAIN_WINDOW)
2100 {
2101 if(u8id == 0)
2102 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_08_L); // frcm_w base address0
2103 else if(u8id == 1)
2104 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L); // frcm_w base address1
2105 else //if(u8id == 2)
2106 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_0C_L); // frcm_w base address2
2107 }
2108 else
2109 {
2110 if(u8id == 0)
2111 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_48_L); // frcm_w base address0
2112 else if(u8id == 1)
2113 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_4A_L); // frcm_w base address1
2114 else //if(u8id == 2)
2115 return SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_4C_L); // frcm_w base address2
2116 }
2117 }
2118
Hal_SC_Get_LBOffset(void * pInstance,SCALER_WIN eWindow)2119 MS_U8 Hal_SC_Get_LBOffset(void *pInstance, SCALER_WIN eWindow)
2120 {
2121 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2122 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2123 if(eWindow == MAIN_WINDOW)
2124 {
2125 return SC_R2BYTEMSK(0, REG_SC_BK20_1D_L, 0x00FF);
2126 }
2127 else
2128 {
2129 return (SC_R2BYTEMSK(0, REG_SC_BK20_1D_L, 0xFF00) >> 8);
2130 }
2131 }
2132
Hal_SC_Set_LBOffset(void * pInstance,MS_U8 u8LBOffset,SCALER_WIN eWindow)2133 void Hal_SC_Set_LBOffset(void *pInstance, MS_U8 u8LBOffset, SCALER_WIN eWindow)
2134 {
2135 if(eWindow == MAIN_WINDOW)
2136 {
2137 SC_W2BYTEMSK(0, REG_SC_BK20_1D_L, u8LBOffset, 0x00FF);
2138 }
2139 else
2140 {
2141 SC_W2BYTEMSK(0, REG_SC_BK20_1D_L, u8LBOffset << 8, 0xFF00);
2142 }
2143 }
2144
Hal_SC_set_DNRBase0(void * pInstance,MS_PHY u32DNRBase0,SCALER_WIN eWindow)2145 void Hal_SC_set_DNRBase0(void *pInstance, MS_PHY u32DNRBase0, SCALER_WIN eWindow)
2146 {
2147 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2148 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2149 if(eWindow == MAIN_WINDOW)
2150 {
2151 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2152 }
2153 else
2154 {
2155 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_48_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2156 }
2157 }
2158
Hal_SC_set_DNRBase1(void * pInstance,MS_PHY u32DNRBase1,SCALER_WIN eWindow)2159 void Hal_SC_set_DNRBase1(void *pInstance, MS_PHY u32DNRBase1, SCALER_WIN eWindow)
2160 {
2161 UNUSED(u32DNRBase1);
2162 UNUSED(eWindow);
2163 }
2164
Hal_SC_set_DNRBase2(void * pInstance,MS_PHY u32DNRBase2,SCALER_WIN eWindow)2165 void Hal_SC_set_DNRBase2(void *pInstance, MS_PHY u32DNRBase2, SCALER_WIN eWindow)
2166 {
2167 UNUSED(u32DNRBase2);
2168 UNUSED(eWindow);
2169 }
2170
Hal_SC_set_OPMBase0(void * pInstance,MS_PHY u32OPMBase0,SCALER_WIN eWindow)2171 void Hal_SC_set_OPMBase0(void *pInstance, MS_PHY u32OPMBase0, SCALER_WIN eWindow)
2172 {
2173 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2174 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2175 if(eWindow == MAIN_WINDOW)
2176 {
2177 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_10_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2178 }
2179 else
2180 {
2181 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_50_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2182 }
2183 }
2184
Hal_SC_set_OPMBase1(void * pInstance,MS_PHY u32OPMBase1,SCALER_WIN eWindow)2185 void Hal_SC_set_OPMBase1(void *pInstance, MS_PHY u32OPMBase1, SCALER_WIN eWindow)
2186 {
2187 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2188 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2189 if(eWindow == MAIN_WINDOW)
2190 {
2191 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_12_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2192 }
2193 else
2194 {
2195 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_52_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2196 }
2197 }
2198
Hal_SC_set_OPMBase2(void * pInstance,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2199 void Hal_SC_set_OPMBase2(void *pInstance, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2200 {
2201 UNUSED(u32OPMBase2);
2202 UNUSED(eWindow);
2203 }
2204
Hal_SC_set_FRCM_WBase0(void * pInstance,MS_PHY u32FRCM_WBase0,SCALER_WIN eWindow)2205 void Hal_SC_set_FRCM_WBase0(void *pInstance, MS_PHY u32FRCM_WBase0, SCALER_WIN eWindow)
2206 {
2207 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2208 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2209 if(eWindow == MAIN_WINDOW)
2210 {
2211 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_08_L, u32FRCM_WBase0 / BYTE_PER_WORD); // input address0
2212 }
2213 else
2214 {
2215 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_48_L, u32FRCM_WBase0 / BYTE_PER_WORD); // input address0
2216 }
2217 }
2218
Hal_SC_set_FRCM_WBase1(void * pInstance,MS_PHY u32FRCM_WBase1,SCALER_WIN eWindow)2219 void Hal_SC_set_FRCM_WBase1(void *pInstance, MS_PHY u32FRCM_WBase1, SCALER_WIN eWindow)
2220 {
2221 UNUSED(u32FRCM_WBase1);
2222 UNUSED(eWindow);
2223 }
2224
Hal_SC_set_FRCM_WBase2(void * pInstance,MS_PHY u32FRCM_WBase2,SCALER_WIN eWindow)2225 void Hal_SC_set_FRCM_WBase2(void *pInstance, MS_PHY u32FRCM_WBase2, SCALER_WIN eWindow)
2226 {
2227 UNUSED(u32FRCM_WBase2);
2228 UNUSED(eWindow);
2229 }
2230
Hal_SC_set_FRCM_RBase0(void * pInstance,MS_PHY u32FRCM_RBase0,SCALER_WIN eWindow)2231 void Hal_SC_set_FRCM_RBase0(void *pInstance, MS_PHY u32FRCM_RBase0, SCALER_WIN eWindow)
2232 {
2233 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2234 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2235 if(eWindow == MAIN_WINDOW)
2236 {
2237 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_10_L, u32FRCM_RBase0 / BYTE_PER_WORD); // input address0
2238 }
2239 else
2240 {
2241 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_50_L, u32FRCM_RBase0 / BYTE_PER_WORD); // input address0
2242 }
2243 }
2244
Hal_SC_set_FRCM_RBase1(void * pInstance,MS_PHY u32FRCM_RBase1,SCALER_WIN eWindow)2245 void Hal_SC_set_FRCM_RBase1(void *pInstance, MS_PHY u32FRCM_RBase1, SCALER_WIN eWindow)
2246 {
2247 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2248 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2249 if(eWindow == MAIN_WINDOW)
2250 {
2251 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_12_L, u32FRCM_RBase1 / BYTE_PER_WORD); // input address1
2252 }
2253 else
2254 {
2255 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_52_L, u32FRCM_RBase1 / BYTE_PER_WORD); // input address1
2256 }
2257 }
2258
Hal_SC_set_FRCM_RBase2(void * pInstance,MS_PHY u32FRCM_RBase2,SCALER_WIN eWindow)2259 void Hal_SC_set_FRCM_RBase2(void *pInstance, MS_PHY u32FRCM_RBase2, SCALER_WIN eWindow)
2260 {
2261 UNUSED(u32FRCM_RBase2);
2262 UNUSED(eWindow);
2263 }
2264
Hal_SC_set_Dual_DNRBase0(void * pInstance,MS_PHY u32DNRBase0,SCALER_WIN eWindow)2265 void Hal_SC_set_Dual_DNRBase0(void *pInstance, MS_PHY u32DNRBase0, SCALER_WIN eWindow)
2266 {
2267 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2268 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2269 if(eWindow == MAIN_WINDOW)
2270 {
2271 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_08_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2272 }
2273 else
2274 {
2275 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_48_L, u32DNRBase0 / BYTE_PER_WORD); // input address0
2276 }
2277 }
2278
Hal_SC_set_Dual_DNRBase1(void * pInstance,MS_PHY u32DNRBase1,SCALER_WIN eWindow)2279 void Hal_SC_set_Dual_DNRBase1(void *pInstance, MS_PHY u32DNRBase1, SCALER_WIN eWindow)
2280 {
2281 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2282 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2283 if(eWindow == MAIN_WINDOW)
2284 {
2285 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_1A_L, u32DNRBase1 / BYTE_PER_WORD); // input address0
2286 }
2287 else
2288 {
2289 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_5A_L, u32DNRBase1 / BYTE_PER_WORD); // input address0
2290 }
2291
2292 }
2293
Hal_SC_set_Dual_DNRBase2(void * pInstance,MS_PHY u32DNRBase2,SCALER_WIN eWindow)2294 void Hal_SC_set_Dual_DNRBase2(void *pInstance, MS_PHY u32DNRBase2, SCALER_WIN eWindow)
2295 {
2296 UNUSED(u32DNRBase2);
2297 UNUSED(eWindow);
2298 }
2299
Hal_SC_set_Dual_OPMBase0(void * pInstance,MS_PHY u32OPMBase0,SCALER_WIN eWindow)2300 void Hal_SC_set_Dual_OPMBase0(void *pInstance, MS_PHY u32OPMBase0, SCALER_WIN eWindow)
2301 {
2302 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2303 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2304 if(eWindow == MAIN_WINDOW)
2305 {
2306 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_10_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2307 }
2308 else
2309 {
2310 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_50_L, u32OPMBase0 / BYTE_PER_WORD); // input address0
2311 }
2312 }
2313
Hal_SC_set_Dual_OPMBase1(void * pInstance,MS_PHY u32OPMBase1,SCALER_WIN eWindow)2314 void Hal_SC_set_Dual_OPMBase1(void *pInstance, MS_PHY u32OPMBase1, SCALER_WIN eWindow)
2315 {
2316 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2317 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2318 if(eWindow == MAIN_WINDOW)
2319 {
2320 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_12_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2321 }
2322 else
2323 {
2324 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_52_L, u32OPMBase1 / BYTE_PER_WORD); // input address1
2325 }
2326 }
2327
Hal_SC_set_Dual_OPMBase2(void * pInstance,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2328 void Hal_SC_set_Dual_OPMBase2(void *pInstance, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2329 {
2330 UNUSED(u32OPMBase2);
2331 UNUSED(eWindow);
2332 }
2333
Hal_SC_set_WriteVLength(void * pInstance,SCALER_WIN eWindow)2334 void Hal_SC_set_WriteVLength(void *pInstance, SCALER_WIN eWindow)
2335 {
2336 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2337 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2338 if(eWindow == MAIN_WINDOW)
2339 {
2340 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_15_L, 0x0); // Write V length
2341 }
2342 else
2343 {
2344 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_16_L, 0x0); // Write V length
2345 }
2346 }
2347
Hal_SC_set_memoryaddress(void * pInstance,MS_PHY u32DNRBase0,MS_PHY u32DNRBase1,MS_PHY u32DNRBase2,MS_PHY u32OPMBase0,MS_PHY u32OPMBase1,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2348 void Hal_SC_set_memoryaddress(void *pInstance, MS_PHY u32DNRBase0, MS_PHY u32DNRBase1, MS_PHY u32DNRBase2, MS_PHY u32OPMBase0, MS_PHY u32OPMBase1, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2349 {
2350 Hal_SC_set_DNRBase0(pInstance, u32DNRBase0, eWindow);
2351 Hal_SC_set_DNRBase1(pInstance, u32DNRBase1, eWindow);
2352 Hal_SC_set_DNRBase2(pInstance, u32DNRBase2, eWindow);
2353 Hal_SC_set_OPMBase0(pInstance, u32OPMBase0, eWindow);
2354 Hal_SC_set_OPMBase1(pInstance, u32OPMBase1, eWindow);
2355 Hal_SC_set_OPMBase2(pInstance, u32OPMBase2, eWindow);
2356 }
2357
Hal_SC_set_frcm_memoryaddress(void * pInstance,MS_PHY u32FRCM_WBase0,MS_PHY u32FRCM_WBase1,MS_PHY u32FRCM_WBase2,MS_PHY u32FRCM_RBase0,MS_PHY u32FRCM_RBase1,MS_PHY u32FRCM_RBase2,SCALER_WIN eWindow)2358 void Hal_SC_set_frcm_memoryaddress(void *pInstance, MS_PHY u32FRCM_WBase0, MS_PHY u32FRCM_WBase1, MS_PHY u32FRCM_WBase2, MS_PHY u32FRCM_RBase0, MS_PHY u32FRCM_RBase1, MS_PHY u32FRCM_RBase2, SCALER_WIN eWindow)
2359 {
2360 Hal_SC_set_FRCM_WBase0(pInstance, u32FRCM_WBase0, eWindow);
2361 Hal_SC_set_FRCM_WBase1(pInstance, u32FRCM_WBase1, eWindow);
2362 Hal_SC_set_FRCM_WBase2(pInstance, u32FRCM_WBase2, eWindow);
2363 Hal_SC_set_FRCM_RBase0(pInstance, u32FRCM_RBase0, eWindow);
2364 Hal_SC_set_FRCM_RBase1(pInstance, u32FRCM_RBase1, eWindow);
2365 Hal_SC_set_FRCM_RBase2(pInstance, u32FRCM_RBase2, eWindow);
2366 }
2367
Hal_SC_set_dual_memoryaddress(void * pInstance,MS_PHY u32DNRBase0,MS_PHY u32DNRBase1,MS_PHY u32DNRBase2,MS_PHY u32OPMBase0,MS_PHY u32OPMBase1,MS_PHY u32OPMBase2,SCALER_WIN eWindow)2368 void Hal_SC_set_dual_memoryaddress(void *pInstance, MS_PHY u32DNRBase0, MS_PHY u32DNRBase1, MS_PHY u32DNRBase2, MS_PHY u32OPMBase0, MS_PHY u32OPMBase1, MS_PHY u32OPMBase2, SCALER_WIN eWindow)
2369 {
2370 Hal_SC_set_Dual_DNRBase0(pInstance, u32DNRBase0, eWindow);
2371 Hal_SC_set_Dual_DNRBase1(pInstance, u32DNRBase1, eWindow);
2372 Hal_SC_set_Dual_DNRBase2(pInstance, u32DNRBase2, eWindow);
2373 Hal_SC_set_Dual_OPMBase0(pInstance, u32OPMBase0, eWindow);
2374 Hal_SC_set_Dual_OPMBase1(pInstance, u32OPMBase1, eWindow);
2375 Hal_SC_set_Dual_OPMBase2(pInstance, u32OPMBase2, eWindow);
2376 }
2377
Hal_SC_get_miu0mask(void)2378 static SC_MIUMASK_t Hal_SC_get_miu0mask(void)
2379 {
2380 SC_MIUMASK_t mask;
2381
2382 mask.u16MiuG0Mask = MDrv_Read2Byte(MIU0_G0_REQUEST_MASK);
2383 mask.u16MiuG1Mask = MDrv_Read2Byte(MIU0_G1_REQUEST_MASK);
2384 mask.u16MiuG2Mask = MDrv_Read2Byte(MIU0_G2_REQUEST_MASK);
2385 mask.u16MiuG3Mask = MDrv_Read2Byte(MIU0_G3_REQUEST_MASK);
2386 mask.u16MiuG4Mask = MDrv_Read2Byte(MIU0_G4_REQUEST_MASK);
2387 mask.u16MiuG5Mask = MDrv_Read2Byte(MIU0_G5_REQUEST_MASK);
2388
2389 return mask;
2390 }
2391
Hal_SC_get_miu1mask(void)2392 static SC_MIUMASK_t Hal_SC_get_miu1mask(void)
2393 {
2394 SC_MIUMASK_t mask;
2395
2396 mask.u16MiuG0Mask = MDrv_Read2Byte(MIU1_G0_REQUEST_MASK);
2397 mask.u16MiuG1Mask = MDrv_Read2Byte(MIU1_G1_REQUEST_MASK);
2398 mask.u16MiuG2Mask = MDrv_Read2Byte(MIU1_G2_REQUEST_MASK);
2399 mask.u16MiuG3Mask = MDrv_Read2Byte(MIU1_G3_REQUEST_MASK);
2400 mask.u16MiuG4Mask = MDrv_Read2Byte(MIU1_G4_REQUEST_MASK);
2401 mask.u16MiuG5Mask = MDrv_Read2Byte(MIU1_G5_REQUEST_MASK);
2402
2403 return mask;
2404 }
2405
Hal_SC_set_miu0mask(SC_MIUMASK_t mask)2406 static void Hal_SC_set_miu0mask(SC_MIUMASK_t mask)
2407 {
2408 MDrv_Write2Byte(MIU0_G0_REQUEST_MASK, mask.u16MiuG0Mask);
2409 MDrv_Write2Byte(MIU0_G1_REQUEST_MASK, mask.u16MiuG1Mask);
2410 MDrv_Write2Byte(MIU0_G2_REQUEST_MASK, mask.u16MiuG2Mask);
2411 MDrv_Write2Byte(MIU0_G3_REQUEST_MASK, mask.u16MiuG3Mask);
2412 MDrv_Write2Byte(MIU0_G4_REQUEST_MASK, mask.u16MiuG4Mask);
2413 MDrv_Write2Byte(MIU0_G5_REQUEST_MASK, mask.u16MiuG5Mask);
2414 }
2415
Hal_SC_set_miu1mask(SC_MIUMASK_t mask)2416 static void Hal_SC_set_miu1mask(SC_MIUMASK_t mask)
2417 {
2418 MDrv_Write2Byte(MIU1_G0_REQUEST_MASK, mask.u16MiuG0Mask);
2419 MDrv_Write2Byte(MIU1_G1_REQUEST_MASK, mask.u16MiuG1Mask);
2420 MDrv_Write2Byte(MIU1_G2_REQUEST_MASK, mask.u16MiuG2Mask);
2421 MDrv_Write2Byte(MIU1_G3_REQUEST_MASK, mask.u16MiuG3Mask);
2422 MDrv_Write2Byte(MIU1_G4_REQUEST_MASK, mask.u16MiuG4Mask);
2423 MDrv_Write2Byte(MIU1_G5_REQUEST_MASK, mask.u16MiuG5Mask);
2424 }
2425
Hal_SC_Enable_MiuMask(void * pInstance)2426 void Hal_SC_Enable_MiuMask(void *pInstance)
2427 {
2428 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2429 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2430 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2431 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2432 pXCResourcePrivate->sthal_SC.Miu0MaskOld = Hal_SC_get_miu0mask();
2433 pXCResourcePrivate->sthal_SC.Miu1MaskOld = Hal_SC_get_miu1mask();
2434
2435 pXCResourcePrivate->sthal_SC.Miu0Mask = pXCResourcePrivate->sthal_SC.Miu0MaskOld;
2436 pXCResourcePrivate->sthal_SC.Miu1Mask = pXCResourcePrivate->sthal_SC.Miu1MaskOld;
2437
2438 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG0Mask |= MIU_SC_G0REQUEST_MASK;
2439 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK;
2440 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG2Mask |= MIU_SC_G2REQUEST_MASK;
2441 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG3Mask |= MIU_SC_G3REQUEST_MASK;
2442 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG4Mask |= MIU_SC_G4REQUEST_MASK;
2443 pXCResourcePrivate->sthal_SC.Miu0Mask.u16MiuG5Mask |= MIU_SC_G5REQUEST_MASK;
2444
2445
2446 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG0Mask |= MIU_SC_G0REQUEST_MASK;
2447 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG1Mask |= MIU_SC_G1REQUEST_MASK;
2448 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG2Mask |= MIU_SC_G2REQUEST_MASK;
2449 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG3Mask |= MIU_SC_G3REQUEST_MASK;
2450 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG4Mask |= MIU_SC_G4REQUEST_MASK;
2451 pXCResourcePrivate->sthal_SC.Miu1Mask.u16MiuG5Mask |= MIU_SC_G5REQUEST_MASK;
2452
2453 Hal_SC_set_miu0mask(pXCResourcePrivate->sthal_SC.Miu0Mask);
2454 Hal_SC_set_miu1mask(pXCResourcePrivate->sthal_SC.Miu1Mask);
2455 }
2456
Hal_SC_Disable_MiuMask(void * pInstance)2457 void Hal_SC_Disable_MiuMask(void *pInstance)
2458 {
2459 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2460 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2461 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2462 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2463 Hal_SC_set_miu0mask(pXCResourcePrivate->sthal_SC.Miu0MaskOld);
2464 Hal_SC_set_miu1mask(pXCResourcePrivate->sthal_SC.Miu1MaskOld);
2465 }
2466
Hal_SC_set_miusel(void * pInstance,MS_U8 u8MIUSel)2467 void Hal_SC_set_miusel(void *pInstance, MS_U8 u8MIUSel)
2468 {
2469 // Scaler control MIU by itself
2470 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
2471 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2472 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2473 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2474 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2475 #if 0 // remove and decided by miu_setting.txt
2476 // MIU 1, GROUP0~5: 0x78~0x7D
2477 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF2, 0x60, 0x60); // IP select, group1, for [5]DIPW, [6]LD
2478 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select, group1, for [f]MC2D
2479 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFA, 0xE0, 0xE0); // IP select, group5
2480 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFB, 0xF7, 0xF7); // IP select, group5
2481 #endif
2482
2483
2484 #if 0
2485 // When MIU select controlled by XC internal via BK12_05, IPM/OPM just access the same MIU only.
2486 // For monet Mirror under enbale dual MIU, IPM/OPM need access different miu,
2487 // so miu select must be controlled by MIU (BK7F_10[1..0]).
2488 if (u8MIUSel == 0)
2489 {
2490 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, 0x0, BIT(0) | BIT(1));
2491 }
2492 else
2493 {
2494 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, BIT(0) | BIT(1), BIT(0) | BIT(1));
2495 }
2496 #endif
2497
2498 #if 1
2499 if (u8MIUSel==0)
2500 {
2501 ///SCM
2502 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2503 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2504
2505 if (!IsEnableDualMode(MAIN_WINDOW))
2506 {
2507 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2508 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2509 }
2510 else
2511 {
2512 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU0
2513 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2514 }
2515
2516 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2517 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2518 }
2519 else if(u8MIUSel==1)
2520 {
2521 ///SCM
2522 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2523 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2524
2525 if (!IsEnableDualMode(MAIN_WINDOW))
2526 {
2527 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2528 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2529 }
2530 else
2531 {
2532 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2533 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2534 }
2535
2536 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2537 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2538 }
2539 else if(u8MIUSel==2)
2540 {
2541 ///SCM
2542 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2543 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2544 if (!IsEnableDualMode(MAIN_WINDOW))
2545 {
2546 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2547 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2548 }
2549 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2550 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2551 }
2552 #endif
2553 }
2554
Hal_SC_get_miusel(void * pInstance,SC_MIUSEL_t * stMIUSel)2555 void Hal_SC_get_miusel(void *pInstance, SC_MIUSEL_t* stMIUSel)
2556 {
2557 #if 1
2558 if(SC_R2BYTEMSK(0, REG_SC_BK12_05_L, BIT(4)))
2559 {
2560 stMIUSel-> u8MainFBSel = 1;
2561 }
2562 else
2563 {
2564 if(SC_R2BYTEMSK(0, REG_SC_BK11_05_L, BIT(4)))
2565 {
2566 stMIUSel-> u8MainFBSel = 2;
2567 }
2568 else
2569 {
2570 stMIUSel-> u8MainFBSel = 0;
2571 }
2572 }
2573
2574 if(SC_R2BYTEMSK(0, REG_SC_BK32_05_L, BIT(4)))
2575 {
2576 stMIUSel-> u8SubFBSel = 1;
2577 }
2578 else
2579 {
2580 if(SC_R2BYTEMSK(0, REG_SC_BK31_05_L, BIT(4)))
2581 {
2582 stMIUSel-> u8SubFBSel = 2;
2583 }
2584 else
2585 {
2586 stMIUSel-> u8SubFBSel = 0;
2587 }
2588 }
2589 #else
2590 if(SC_R2BYTEMSK(0, REG_SC_BK7F_10_L, BIT(0)))
2591 {
2592 stMIUSel-> u8MainFBSel = 1;
2593 }
2594 else
2595 {
2596 stMIUSel-> u8MainFBSel = 0;
2597 }
2598 #endif
2599 }
2600
Hal_SC_set_dual_miusel(void * pInstance,MS_U8 u8MIUSel)2601 void Hal_SC_set_dual_miusel(void *pInstance, MS_U8 u8MIUSel)
2602 {
2603 // Scaler control MIU by itself
2604 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
2605 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2606 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2607 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2608 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2609 #if 0 // remove and decided by miu_setting.txt
2610 // MIU 1, GROUP0~5: 0x78~0x7D
2611 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF2, 0x60, 0x60); // IP select, group1, for [5]DIPW, [6]LD
2612 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select, group1, for [f]MC2D
2613 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFA, 0xE0, 0xE0); // IP select, group5
2614 MDrv_WriteByteMask(REG_MIU1_BASE + 0xFB, 0xF7, 0xF7); // IP select, group5
2615 #endif
2616 // For monet BK52_05 can not work and need not to be set.
2617 // When MIU select controlled by XC internal, XC dual miu auto adjust BK12_05[4]
2618 // When MIU select cntrolled by MIU, xc dual miu auto adjust BK7F_10[1..0]
2619 #if 1
2620 if (u8MIUSel==0)
2621 {
2622 ///SCM
2623 if (IsEnableDualMode(MAIN_WINDOW))
2624 {
2625 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2626 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2627 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU0
2628 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU0
2629 }
2630 }
2631 else if(u8MIUSel==1)
2632 {
2633 ///SCM
2634
2635 if (IsEnableDualMode(MAIN_WINDOW))
2636 {
2637 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2638 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2639 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2640 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2641 }
2642 }
2643 else if(u8MIUSel==2)
2644 {
2645 ///SCM
2646 if (IsEnableDualMode(MAIN_WINDOW))
2647 {
2648 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_05_L, 0x0000, 0x0010); // reg_miu_select_f2 to MIU1
2649 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_05_L, 0x0010, 0x0010); // reg_miu_select_f2 to MIU1
2650 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK52_44_L, 0x0000, 0x4000); // reg_miu_select_f1 to MIU1
2651 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK51_44_L, 0x4000, 0x4000); // reg_miu_select_f1 to MIU1
2652 }
2653 }
2654
2655 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK7F_10_L, 0x0, BIT(0) | BIT(1));
2656 #endif
2657 }
2658
Hal_SC_AdjustIpmWriteLimite(void * pInstance,MS_BOOL bIsLeft,MS_BOOL bNeedSwap,SCALER_WIN eWindow)2659 MS_BOOL Hal_SC_AdjustIpmWriteLimite(void *pInstance, MS_BOOL bIsLeft, MS_BOOL bNeedSwap, SCALER_WIN eWindow)
2660 {
2661 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2662 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2663 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2664 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2665 MS_PHY u32WLimitBase = 0x00;
2666 if ((psXCInstPri->u32DeviceID > 0) || (eWindow != MAIN_WINDOW))
2667 {
2668 return FALSE;
2669 }
2670
2671 if (bIsLeft == TRUE)
2672 {
2673 if (bNeedSwap == TRUE)
2674 {
2675 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DNRBufSize[eWindow]) / BYTE_PER_WORD - 1) | F2_WRITE_LIMIT_EN;;
2676 MDrv_SC_set_dual_write_limit(pInstance, u32WLimitBase , eWindow);
2677 }
2678 else
2679 {
2680 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DNRBufSize[eWindow]) / BYTE_PER_WORD - 1) | F2_WRITE_LIMIT_EN;
2681 MDrv_SC_set_write_limit(pInstance, u32WLimitBase , eWindow);
2682 }
2683 }
2684 else
2685 {
2686 if (bNeedSwap == TRUE)
2687 {
2688 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBufSize[eWindow]) / BYTE_PER_WORD - 1) ;
2689 MDrv_SC_set_write_limit(pInstance, u32WLimitBase , eWindow);
2690 }
2691 else
2692 {
2693 u32WLimitBase = ((pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBaseAddr0[eWindow] + pXCResourcePrivate->stdrvXC_Scaling._u32DualMiuDNRBufSize[eWindow]) / BYTE_PER_WORD - 1) ;
2694 MDrv_SC_set_dual_write_limit(pInstance, u32WLimitBase , eWindow);
2695 }
2696 }
2697 return TRUE;
2698 }
2699
Hal_SC_set_dual_disable(void * pInstance)2700 void Hal_SC_set_dual_disable(void *pInstance)
2701 {
2702 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2703 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2704
2705 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_29_L, 0, BIT(15)); // reg_miu_select_f1 to MIU1
2706 }
2707
Hal_SC_get_dual_miusel(void * pInstance,SC_MIUSEL_t * stMIUSel)2708 void Hal_SC_get_dual_miusel(void *pInstance, SC_MIUSEL_t* stMIUSel)
2709 {
2710 if(SC_R2BYTEMSK(0, REG_SC_BK52_05_L, BIT(4)))
2711 {
2712 stMIUSel->u8MainFBSel = 1;
2713 }
2714 else
2715 {
2716 if(SC_R2BYTEMSK(0, REG_SC_BK51_05_L, BIT(4)))
2717 {
2718 stMIUSel->u8MainFBSel = 2;
2719 }
2720 else
2721 {
2722 stMIUSel->u8MainFBSel = 0;
2723 }
2724 }
2725
2726 if(SC_R2BYTEMSK(0, REG_SC_BK52_44_L, BIT(4)))
2727 {
2728 stMIUSel->u8SubFBSel = 1;
2729 }
2730 else
2731 {
2732 if(SC_R2BYTEMSK(0, REG_SC_BK51_44_L, BIT(4)))
2733 {
2734 stMIUSel->u8SubFBSel = 2;
2735 }
2736 else
2737 {
2738 stMIUSel->u8SubFBSel = 0;
2739 }
2740 }
2741 }
2742
Hal_SC_set_blsk(void * pInstance,MS_BOOL bEn)2743 void Hal_SC_set_blsk(void *pInstance, MS_BOOL bEn)
2744 {
2745 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2746 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2747 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_21_L, bEn ? BIT(12) : 0, BIT(12));
2748 }
2749
Hal_SC_set_blsk_burst(void * pInstance,MS_BOOL bEn)2750 void Hal_SC_set_blsk_burst(void *pInstance, MS_BOOL bEn)
2751 {
2752 _MLOAD_ENTRY(pInstance);
2753 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_21_L, bEn ? BIT(12) : 0, BIT(12));
2754 MDrv_XC_MLoad_Fire(pInstance, TRUE);
2755 _MLOAD_RETURN(pInstance);
2756 }
2757
Hal_SC_set_main_black_screen_burst(void * pInstance,MS_BOOL bEn)2758 void Hal_SC_set_main_black_screen_burst(void *pInstance, MS_BOOL bEn)
2759 {
2760 _MLOAD_ENTRY(pInstance);
2761
2762 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? BIT(1) : 0, BIT(1));
2763 MDrv_XC_MLoad_Fire(pInstance, TRUE);
2764
2765 _MLOAD_RETURN(pInstance);
2766 }
2767
Hal_SC_set_main_sub_black_screen_burst(void * pInstance,MS_BOOL bEn)2768 void Hal_SC_set_main_sub_black_screen_burst(void *pInstance, MS_BOOL bEn)
2769 {
2770 _MLOAD_ENTRY(pInstance);
2771
2772 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? (BIT(5)|BIT(1)) : 0, (BIT(6)|BIT(5)|BIT(1)));
2773 MDrv_XC_MLoad_Fire(pInstance, TRUE);
2774
2775 _MLOAD_RETURN(pInstance);
2776 }
2777
Hal_SC_set_main_black_screen(void * pInstance,MS_BOOL bEn)2778 void Hal_SC_set_main_black_screen(void *pInstance, MS_BOOL bEn)
2779 {
2780 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2781 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2782 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? BIT(1) : 0, BIT(1));
2783 }
2784
Hal_SC_set_main_sub_black_screen(void * pInstance,MS_BOOL bEn)2785 void Hal_SC_set_main_sub_black_screen(void *pInstance, MS_BOOL bEn)
2786 {
2787 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2788 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2789 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? (BIT(5)|BIT(1)) : 0, (BIT(6)|BIT(5)|BIT(1)));
2790 }
2791
Hal_SC_set_sub_blue_screen_burst(void * pInstance,MS_BOOL bEn,MS_BOOL bBlue)2792 void Hal_SC_set_sub_blue_screen_burst(void *pInstance, MS_BOOL bEn, MS_BOOL bBlue)
2793 {
2794 _MLOAD_ENTRY(pInstance);
2795
2796 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bBlue ? BIT(6) : 0, BIT(6));
2797 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_19_L, bEn ? BIT(5) : 0, BIT(5));
2798 MDrv_XC_MLoad_Fire(pInstance, TRUE);
2799
2800 _MLOAD_RETURN(pInstance);
2801 }
2802
Hal_SC_set_sub_blue_screen(void * pInstance,MS_BOOL bEn,MS_BOOL bBlue)2803 void Hal_SC_set_sub_blue_screen(void *pInstance, MS_BOOL bEn, MS_BOOL bBlue)
2804 {
2805 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2806 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2807 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bBlue ? BIT(6) : 0, BIT(6));
2808 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, bEn ? BIT(5) : 0, BIT(5));
2809 }
2810
Hal_SC_IP_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2811 E_APIXC_ReturnValue Hal_SC_IP_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2812 {
2813 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2814 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2815 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2816 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2817 if(MAIN_WINDOW == eWindow)
2818 {
2819 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, bEnable? 0 : BIT(0) , BIT(0));
2820 }
2821 else
2822 {
2823 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, bEnable? 0 : BIT(0) , BIT(0));
2824 }
2825
2826 return E_APIXC_RET_OK;
2827 }
2828
Hal_SC_IP_Memory_Read_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2829 E_APIXC_ReturnValue Hal_SC_IP_Memory_Read_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2830 {
2831 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2832 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2833 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2834 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2835 if(MAIN_WINDOW == eWindow)
2836 {
2837 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_02_L, bEnable? 0 : BIT(14) , BIT(14));
2838 }
2839 else
2840 {
2841 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_42_L, bEnable? 0 : BIT(14) , BIT(14));
2842 }
2843 return E_APIXC_RET_OK;
2844 }
2845
Hal_SC_OP_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2846 E_APIXC_ReturnValue Hal_SC_OP_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2847 {
2848 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2849 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2850 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, bEnable? 0 : BIT(1) , BIT(1));//This will stop OPW and OP memory write request
2851 return E_APIXC_RET_OK;
2852 }
2853
Hal_SC_frcmw_Memory_Write_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2854 E_APIXC_ReturnValue Hal_SC_frcmw_Memory_Write_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2855 {
2856 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2857 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2858 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2859 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2860 if(MAIN_WINDOW == eWindow)
2861 {
2862 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_07_L, bEnable? 0 : BIT(0) , BIT(0));
2863 }
2864 else
2865 {
2866 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_47_L, bEnable? 0 : BIT(0) , BIT(0));
2867 }
2868 return E_APIXC_RET_OK;
2869 }
2870
Hal_SC_frcmr_Memory_Read_Request(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)2871 E_APIXC_ReturnValue Hal_SC_frcmr_Memory_Read_Request(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
2872 {
2873 return E_APIXC_RET_OK;
2874 }
2875
Hal_SC_disable_inputsource_burst(void * pInstance,MS_BOOL bDisable,SCALER_WIN eWindow)2876 void Hal_SC_disable_inputsource_burst(void *pInstance, MS_BOOL bDisable, SCALER_WIN eWindow)
2877 {
2878 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2879 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2880 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
2881 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
2882
2883 _MLOAD_ENTRY(pInstance);
2884
2885 // HW PIP architeucture
2886 // Becasue BK3_02[8] and BK20_11[15] can not be enabled toghter,
2887 // otherwise garbage will be showed,we need to use BK12_47[0] to instead.
2888 if( eWindow == MAIN_WINDOW )
2889 {
2890 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK01_02_L, (bDisable ? BIT(7):0), BIT(7));
2891 }
2892 else
2893 {
2894 //MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, (bDisable ? BIT(7):0), BIT(7));
2895 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_47_L, (bDisable ? BIT(0) : 0), BIT(0));
2896 #if (HW_DESIGN_4K2K_VER == 4)
2897 if ((psXCInstPri->u32DeviceID==0)
2898 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
2899 {
2900 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_47_L, (bDisable ? BIT(0) : 0), BIT(0));
2901 }
2902 #endif
2903 }
2904 MDrv_XC_MLoad_Fire(pInstance, TRUE);
2905 _MLOAD_RETURN(pInstance);
2906 }
2907
Hal_SC_disable_inputsource(void * pInstance,MS_BOOL bDisable,SCALER_WIN eWindow)2908 void Hal_SC_disable_inputsource(void *pInstance, MS_BOOL bDisable, SCALER_WIN eWindow)
2909 {
2910 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2911 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2912 if( eWindow == MAIN_WINDOW )
2913 {
2914 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L, (bDisable ? BIT(7):0), BIT(7));
2915 }
2916 else
2917 {
2918 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L, (bDisable ? BIT(7):0), BIT(7));
2919 }
2920 }
2921
2922
Hal_SC_Is_InputSource_Disable(void * pInstance,SCALER_WIN eWindow)2923 MS_U16 Hal_SC_Is_InputSource_Disable(void *pInstance, SCALER_WIN eWindow)
2924 {
2925 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2926 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2927 if(eWindow == MAIN_WINDOW)
2928 return (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L)&0x80);
2929 else
2930 {
2931 if((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L)&0x01) == 0)
2932 {
2933 return (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L)&0x80);
2934 }
2935 else
2936 {
2937 return TRUE;
2938 }
2939 }
2940 }
2941
2942
Hal_SC_set_nosignal_color(void * pInstance,MS_U8 u8Color,SCALER_WIN eWindow)2943 void Hal_SC_set_nosignal_color(void *pInstance, MS_U8 u8Color,SCALER_WIN eWindow)
2944 {
2945 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2946 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2947 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
2948 {
2949 _MLOAD_ENTRY(pInstance);
2950 if ( eWindow == MAIN_WINDOW )
2951 {
2952 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_24_L, u8Color, LBMASK);
2953 }
2954 else
2955 {
2956 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
2957 }
2958 MDrv_XC_MLoad_Fire(pInstance, TRUE);
2959 _MLOAD_RETURN(pInstance);
2960 }
2961 else
2962 {
2963 if ( eWindow == MAIN_WINDOW )
2964 {
2965 #ifdef new_chakra
2966 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_24_L, u8Color, LBMASK);
2967 #else
2968 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_24_L, u8Color, LBMASK);
2969 #endif
2970 }
2971 else
2972 {
2973 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_17_L, ((MS_U16)u8Color)<<8, HBMASK);
2974 }
2975 }
2976 }
2977
Hal_SC_set_fbl(void * pInstance,MS_BOOL bEn)2978 void Hal_SC_set_fbl(void *pInstance, MS_BOOL bEn)
2979 {
2980 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2981 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2982 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn ? BIT(7): 0), BIT(7)); //Enable/Disable FBL
2983 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_02_L, (bEn ? BIT(14):0), BIT(14)); //F2 force IP read request disable
2984
2985 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, (bEn ? 0x3:0), 0x3); //F2 IP read/write request disable
2986 }
2987
Hal_SC_get_fbl(void * pInstance)2988 MS_BOOL Hal_SC_get_fbl(void *pInstance)
2989 {
2990 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
2991 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
2992 return SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, BIT(7)); //Enable/Disable FBL
2993 }
2994
Hal_SC_set_freezeimg_burst(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)2995 void Hal_SC_set_freezeimg_burst(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
2996 {
2997 _MLOAD_ENTRY(pInstance);
2998 #if (HW_DESIGN_4K2K_VER == 4)
2999 if( eWindow == MAIN_WINDOW )
3000 {
3001 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3002 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3003 }
3004 else
3005 {
3006 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3007 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3008 }
3009 #else
3010 if( eWindow == MAIN_WINDOW )
3011 {
3012 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3013 }
3014 else
3015 {
3016 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3017 }
3018 #endif
3019 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3020 _MLOAD_RETURN(pInstance);
3021 }
3022
3023
Hal_SC_set_freezeimg(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)3024 void Hal_SC_set_freezeimg(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
3025 {
3026 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3027 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3028 #if (HW_DESIGN_4K2K_VER == 4)
3029 if( eWindow == MAIN_WINDOW )
3030 {
3031 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3032 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3033 }
3034 else
3035 {
3036 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3037 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3038 }
3039 #else
3040 if( eWindow == MAIN_WINDOW )
3041 {
3042 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, (bEn<<11), BIT(11));
3043 }
3044 else
3045 {
3046 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, (bEn<<11), BIT(11));
3047 }
3048 #endif
3049 }
3050
Hal_SC_set_frcm_freezeimg(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)3051 void Hal_SC_set_frcm_freezeimg(void *pInstance, MS_BOOL bEn, SCALER_WIN eWindow)
3052 {
3053 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3054 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3055 if( eWindow == MAIN_WINDOW )
3056 {
3057 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, (bEn<<11), BIT(11));
3058 }
3059 else
3060 {
3061 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, (bEn<<11), BIT(11));
3062 }
3063 }
3064
Hal_SC_get_freezeimg(void * pInstance,SCALER_WIN eWindow)3065 MS_BOOL Hal_SC_get_freezeimg(void *pInstance, SCALER_WIN eWindow)
3066 {
3067 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3068 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3069 #if (HW_DESIGN_4K2K_VER == 4)
3070 if( eWindow == MAIN_WINDOW )
3071 {
3072 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_01_L, BIT(11)) ? TRUE: FALSE);
3073 }
3074 else
3075 {
3076 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_41_L, BIT(11)) ? TRUE: FALSE);
3077 }
3078 #else
3079 if( eWindow == MAIN_WINDOW )
3080 {
3081 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_01_L, BIT(11)) ? TRUE: FALSE);
3082 }
3083 else
3084 {
3085 return (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_41_L, BIT(11)) ? TRUE: FALSE);
3086 }
3087 #endif
3088 }
3089
Hal_SC_exwith_miuprotect_swreset(void * pInstance,MS_U8 x)3090 void Hal_SC_exwith_miuprotect_swreset(void *pInstance, MS_U8 x)
3091 {
3092 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3093 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3094 //reset IP1F2
3095 //select pattern generator source
3096 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_02_L, x, x);
3097 //MsOS_DelayTask(2);
3098
3099 //select pattern generator source
3100 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_02_L, 0, x);
3101 //MsOS_DelayTask(2);
3102 }
3103
Hal_SC_ip_Init_for_internal_timing(void * pInstance,XC_Internal_TimingType timingtype,SCALER_WIN eWindow)3104 void Hal_SC_ip_Init_for_internal_timing(void *pInstance, XC_Internal_TimingType timingtype, SCALER_WIN eWindow)
3105 {
3106 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3107 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3108 if(eWindow == SUB_WINDOW)
3109 {
3110 if(Hal_SC_ip_get_IPAutoNoSignal(pInstance, eWindow)) Hal_SC_ip_set_IPAutoNoSignal(pInstance, DISABLE, eWindow);
3111
3112 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_02_L, 0x104) ; //Video source
3113 Hal_SC_exwith_miuprotect_swreset(pInstance, REST_IP_F1); //when source is changed, we must reset it to make it work
3114 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_03_L, 0x890);
3115
3116 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_21_L, 0x01, 0x03); //force progressive mode
3117 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0E_L, BIT(15), BIT(15)); //auto gain 10bit
3118
3119 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_04_L, 0x020); //capture V start
3120 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_05_L, 0x50) ; //capture H start
3121
3122 switch (timingtype)
3123 {
3124 case E_XC_480P:
3125 default:
3126
3127 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x1c0) ; // V size
3128 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x280) ; // h size
3129
3130 break;
3131 case E_XC_720P:
3132 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x290) ; // V size (720 - 64) = 656 = 0x290
3133 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x460) ; // h size (1280 - 160) = 1120 = 0x460
3134
3135 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, 0x0800); //DNR Offset
3136 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, 0x0460); //DNR Fetch
3137 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, 0x0800); //OPM Offsest
3138 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, 0x0460); //OPM Fetch
3139
3140 break;
3141 case E_XC_1080P:
3142 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_06_L, 0x3F8) ; // V size (1080 - 64) = 1016 = 0x3F8
3143 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_07_L, 0x6E0) ; // h size (1920 - 160) = 1760 = 0x6E0
3144
3145 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4E_L, 0x0800); //DNR Offset
3146 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_4F_L, 0x06E0); //DNR Fetch
3147 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_56_L, 0x0800); //OPM Offsest
3148 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, 0x06E0); //OPM Fetch
3149 break;
3150 }
3151 }
3152 else
3153 {
3154 if(Hal_SC_ip_get_IPAutoNoSignal(pInstance, eWindow)) Hal_SC_ip_set_IPAutoNoSignal(pInstance, DISABLE, eWindow);
3155
3156 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_02_L, 0x104) ; //Video source
3157 Hal_SC_exwith_miuprotect_swreset(pInstance, REST_IP_F2); //when source is changed, we must reset it to make it work
3158 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_03_L, 0x890);
3159
3160 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_21_L, 0x01, 0x03); //force progressive mode
3161 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0E_L, BIT(15), BIT(15)); //auto gain 10bit
3162
3163 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_04_L, 0x020); //capture V start
3164 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_05_L, 0x50) ; //capture H start
3165
3166 switch (timingtype)
3167 {
3168 case E_XC_480P:
3169 default:
3170
3171 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x1c0) ; // V size
3172 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x280) ; // h size
3173
3174 break;
3175 case E_XC_720P:
3176 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x290) ; // V size (720 - 64) = 656 = 0x290
3177 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x460) ; // h size (1280 - 160) = 1120 = 0x460
3178
3179 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, 0x0800); //DNR Offset
3180 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, 0x0460); //DNR Fetch
3181 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, 0x0800); //OPM Offsest
3182 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, 0x0460); //OPM Fetch
3183
3184 break;
3185 case E_XC_1080P:
3186 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_06_L, 0x3F8) ; // V size (1080 - 64) = 1016 = 0x3F8
3187 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_07_L, 0x6E0) ; // h size (1920 - 160) = 1760 = 0x6E0
3188
3189 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, 0x0800); //DNR Offset
3190 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, 0x06E0); //DNR Fetch
3191 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_16_L, 0x0800); //OPM Offsest
3192 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, 0x06E0); //OPM Fetch
3193 break;
3194 }
3195
3196 }
3197 }
3198
Hal_SC_rgb_average_info(void * pInstance,MS_U16 u16mask,SCALER_WIN eWindow)3199 MS_U16 Hal_SC_rgb_average_info(void *pInstance, MS_U16 u16mask, SCALER_WIN eWindow)
3200 {
3201 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3202 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3203 MS_U16 u16value;
3204
3205 if(eWindow == MAIN_WINDOW)
3206 {
3207 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0F_L, u16mask, 0x0F);
3208 u16value=SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_11_L);
3209 }
3210 else
3211 {
3212 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0F_L, u16mask, 0x0F);
3213 u16value=SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_11_L);
3214 }
3215
3216 return u16value;
3217 }
3218
3219
Hal_SC_autogain_enable(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3220 void Hal_SC_autogain_enable(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3221 {
3222 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3223 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3224 //auto gain enable
3225 if(eWindow == MAIN_WINDOW)
3226 {
3227 if(bEnable)
3228 W2BYTEMSK(REG_SC_BK01_0E_L, 0x11, 0x11);
3229 else
3230 W2BYTEMSK(REG_SC_BK01_0E_L, 0x00, 0x11);
3231 }
3232 else
3233 {
3234 if(bEnable)
3235 W2BYTEMSK(REG_SC_BK03_0E_L, 0x11, 0x11);
3236 else
3237 W2BYTEMSK(REG_SC_BK03_0E_L, 0x00, 0x11);
3238 }
3239 }
3240
Hal_SC_autogain_status(void * pInstance,SCALER_WIN eWindow)3241 MS_BOOL Hal_SC_autogain_status(void *pInstance, SCALER_WIN eWindow)
3242 {
3243 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3244 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3245 MS_BOOL bvalue;
3246 if(eWindow == MAIN_WINDOW)
3247 bvalue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0E_L, BIT(1));
3248 else
3249 bvalue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0E_L, BIT(1));
3250
3251 return bvalue;
3252
3253 }
3254
Hal_SC_set_mirror(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3255 void Hal_SC_set_mirror(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3256 {
3257 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3258 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3259 MS_U32 u32NoSigReg, u32MirrorReg;
3260
3261 if(eWindow == MAIN_WINDOW)
3262 {
3263 u32NoSigReg = REG_SC_BK01_02_L;
3264 u32MirrorReg = REG_SC_BK12_03_L;
3265 }
3266 else
3267 {
3268 u32NoSigReg = REG_SC_BK03_02_L;
3269 u32MirrorReg = REG_SC_BK12_43_L;
3270
3271 }
3272
3273 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32NoSigReg, BIT(7), BIT(7));
3274
3275 if( bEnable )
3276 {
3277 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, (BIT(12)|BIT(13)), (BIT(12)|BIT(13)));
3278 }
3279 else
3280 {
3281 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, 0x0, (BIT(12)|BIT(13)));
3282 }
3283 }
3284
Hal_SC_set_frcm_mirror(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3285 void Hal_SC_set_frcm_mirror(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3286 {
3287 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3288 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3289 MS_U32 u32NoSigReg = 0, u32MirrorReg = 0;
3290
3291 if(eWindow == MAIN_WINDOW)
3292 {
3293 u32NoSigReg = REG_SC_BK01_02_L;
3294 u32MirrorReg = REG_SC_BK32_03_L;
3295 }
3296 else
3297 {
3298 u32NoSigReg = REG_SC_BK03_02_L;
3299 u32MirrorReg = REG_SC_BK32_43_L;
3300 }
3301
3302 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32NoSigReg, BIT(7), BIT(7));
3303
3304 if( bEnable )
3305 {
3306 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, (BIT(12)|BIT(13)), (BIT(12)|BIT(13)));
3307 }
3308 else
3309 {
3310 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, u32MirrorReg, 0x0, (BIT(12)|BIT(13)));
3311 }
3312 }
3313
Hal_SC_GetAVDStatus(void)3314 MS_U16 Hal_SC_GetAVDStatus(void)
3315 {
3316 return MDrv_Read2Byte(L_BK_AFEC(0x66));
3317 }
3318
Hal_SC_set_rep_window(void * pInstance,MS_BOOL bEnable,MS_U16 x,MS_U16 y,MS_U16 w,MS_U16 h,MS_U8 u8Color)3319 void Hal_SC_set_rep_window(void *pInstance, MS_BOOL bEnable,MS_U16 x,MS_U16 y,MS_U16 w,MS_U16 h,MS_U8 u8Color)
3320 {
3321 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3322 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3323 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, bEnable?BIT(9):0x0, BIT(9));
3324 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_42_L,x);
3325 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_43_L,x + w);
3326 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_44_L,y);
3327 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_45_L,y + h);
3328 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, (~u8Color)<<8, 0xFF00);
3329 }
3330
3331 //--------------------------------------------------
3332 //update display window registers with input window
3333 //IN:
3334 // pdspwin: input window info
3335 //--------------------------------------------------
Hal_SC_set_disp_window(void * pInstance,SCALER_WIN eWindow,MS_WINDOW_TYPE * pdspwin)3336 void Hal_SC_set_disp_window(void *pInstance, SCALER_WIN eWindow, MS_WINDOW_TYPE *pdspwin)
3337 {
3338 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3339 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3340 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
3341 {
3342 _MLOAD_ENTRY(pInstance);
3343
3344 if(eWindow == MAIN_WINDOW)
3345 {
3346 //Display window
3347 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_08_L, pdspwin->x,0x1FFF); // Display H start
3348 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_09_L, pdspwin->x+pdspwin->width-1,0x1FFF); // Display H end
3349 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0A_L, pdspwin->y,0xFFF); // Display V start
3350 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK10_0B_L, pdspwin->y+pdspwin->height-1,0xFFF); // Display V end
3351 }
3352 else
3353 {
3354 //Display window
3355 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_07_L, pdspwin->x,0xFFF); // Display H start
3356 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_08_L, pdspwin->x+pdspwin->width-1,0xFFF); // Display H end
3357 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_09_L, pdspwin->y,0xFFF); // Display V start
3358 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK0F_0A_L, pdspwin->y+pdspwin->height-1,0xFFF); // Display V end
3359 }
3360
3361 MDrv_XC_MLoad_Fire(pInstance, TRUE);
3362 _MLOAD_RETURN(pInstance);
3363 }
3364 else
3365 {
3366 if(eWindow == MAIN_WINDOW)
3367 {
3368 //Display window
3369 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L, pdspwin->x); // Display H start
3370 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L, pdspwin->x+pdspwin->width-1); // Display H end
3371 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L, pdspwin->y); // Display V start
3372 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L, pdspwin->y+pdspwin->height-1); // Display V end
3373 }
3374 else
3375 {
3376 //Display window
3377 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L, pdspwin->x); // Display H start
3378 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L, pdspwin->x+pdspwin->width-1); // Display H end
3379 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L, pdspwin->y); // Display V start
3380 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L, pdspwin->y+pdspwin->height-1); // Display V end
3381 }
3382 }
3383 }
3384
3385 //--------------------------------------------------
3386 //get display window registers setting
3387 //OUT:
3388 // pdspwin: Pointer for ouput disp window register
3389 //--------------------------------------------------
Hal_SC_get_disp_window(void * pInstance,SCALER_WIN eWindow,MS_WINDOW_TYPE * pdspwin)3390 void Hal_SC_get_disp_window(void *pInstance, SCALER_WIN eWindow, MS_WINDOW_TYPE *pdspwin)
3391 {
3392 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3393 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3394 if(eWindow == MAIN_WINDOW)
3395 {
3396 //Display window
3397 pdspwin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_08_L); // Display H start
3398 pdspwin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_09_L) - pdspwin->x + 1; // Display H end
3399 pdspwin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0A_L); // Display V start
3400 pdspwin->height = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_0B_L) - pdspwin->y + 1; // Display V end
3401 }
3402 else
3403 {
3404 //Display window
3405 pdspwin->x = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_07_L); // Display H start
3406 pdspwin->width = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_08_L) - pdspwin->x + 1; // Display H end
3407 pdspwin->y = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_09_L); // Display V start
3408 pdspwin->height = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_0A_L) - pdspwin->y + 1; // Display V end
3409 }
3410 }
3411
Hal_SC_set_Fclk(void * pInstance,EN_SET_FCLK_CASE enCase)3412 void Hal_SC_set_Fclk(void *pInstance, EN_SET_FCLK_CASE enCase)
3413 {
3414 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3415 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3416 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3417 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3418
3419 if (enCase == EN_FCLK_FBL)
3420 {
3421 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
3422 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_345MHZ, CKG_FCLK_MASK);
3423 else
3424 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_345MHZ, CKG_S2_FCLK_MASK);
3425 }
3426 else
3427 {
3428 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
3429 MDrv_WriteByteMask(REG_CKG_FCLK, CKG_FCLK_DEFAULT, CKG_FCLK_MASK);
3430 else
3431 MDrv_WriteByteMask(REG_CKG_S2_FCLK, CKG_S2_FCLK_320MHZ, CKG_S2_FCLK_MASK);
3432 }
3433 }
3434
Hal_SC_get_framebuf_Info(void * pInstance,SC_FRAMEBUF_INFO_t * pFrameBufInfo,SCALER_WIN eWindow)3435 void Hal_SC_get_framebuf_Info(void *pInstance, SC_FRAMEBUF_INFO_t *pFrameBufInfo, SCALER_WIN eWindow)
3436 {
3437 MS_U8 u8Reg;
3438
3439 if (!pFrameBufInfo) return;
3440
3441 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3442 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3443 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3444 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3445
3446 pFrameBufInfo->u32IPMBase0 = ((SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_09_L:REG_SC_BK12_49_L, 0x00FF)<<16) |
3447 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_08_L:REG_SC_BK12_48_L))) * BYTE_PER_WORD;
3448 pFrameBufInfo->u32IPMBase1 = ((SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0B_L:REG_SC_BK12_4B_L, 0x00FF)<<16) |
3449 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0A_L:REG_SC_BK12_4A_L))) * BYTE_PER_WORD;
3450 pFrameBufInfo->u32IPMBase2 = ((SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0D_L:REG_SC_BK12_4D_L, 0x00FF)<<16) |
3451 (SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0C_L:REG_SC_BK12_4C_L))) * BYTE_PER_WORD;
3452 pFrameBufInfo->u16IPMOffset = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0E_L:REG_SC_BK12_4E_L);
3453 pFrameBufInfo->u16IPMFetch = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_0F_L:REG_SC_BK12_4F_L);
3454 pFrameBufInfo->u16VLength = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_18_L:REG_SC_BK12_58_L, 0x0FFF);
3455 pFrameBufInfo->bLinearAddrMode = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_03_L:REG_SC_BK12_43_L, BIT(4));
3456 pFrameBufInfo->bYCSeparate = ( SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L, BIT(10)) )?TRUE:FALSE;
3457 pFrameBufInfo->u32WriteLimitBase = SC_R4BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK0D_42_L:REG_SC_BK0D_44_L);
3458 // frcm write base address limit
3459 #if 0
3460 #if (HW_DESIGN_4K2K_VER == 4)
3461 if ((psXCInstPri->u32DeviceID==0)
3462 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
3463 {
3464 pFrameBufInfo->u32FRCMWriteLimitBase = SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L);
3465 }
3466 #endif
3467 #endif
3468 pFrameBufInfo->u8BitPerPixel = 24;//default
3469
3470 u8Reg = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_01_L:REG_SC_BK12_41_L, 0x00FF);
3471 if (u8Reg & 0x30)
3472 {//444
3473 pFrameBufInfo->bMemFormat422 = FALSE;
3474 if (u8Reg & 0x10)
3475 { // 444 8BIT
3476 pFrameBufInfo->u8BitPerPixel = 24;
3477 }
3478 else
3479 { // 444 10BIT
3480 pFrameBufInfo->u8BitPerPixel = 32;
3481 }
3482 pFrameBufInfo->bInterlace = FALSE;
3483 }
3484 else
3485 {//422
3486 pFrameBufInfo->bMemFormat422 = TRUE;
3487
3488 if((BIT(8)|BIT(9)) == SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L, BIT(8)|BIT(9))) //user mode
3489 {
3490 MS_U8 u8MemFmt = SC_R2BYTE(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_02_L:REG_SC_BK12_42_L) & 0x0F;
3491 if((4 == u8MemFmt) || (5 == u8MemFmt) || (6 == u8MemFmt))
3492 {
3493 pFrameBufInfo->u8BitPerPixel = 20;
3494 }
3495 else if((8 == u8MemFmt) || (9 == u8MemFmt) || (10 == u8MemFmt) || (11 == u8MemFmt))
3496 {
3497 pFrameBufInfo->u8BitPerPixel = 24;
3498 }
3499 }
3500 else
3501 {
3502 u8Reg = (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_01_L:REG_SC_BK12_41_L, 0xFF00)) >> 8;
3503
3504 switch(u8Reg & 0x77)
3505 {
3506 case 0x25:
3507 pFrameBufInfo->u8BitPerPixel = 24;
3508 pFrameBufInfo->bInterlace = TRUE;
3509 break;
3510 case 0x24:
3511 pFrameBufInfo->u8BitPerPixel = 20;
3512 pFrameBufInfo->bInterlace = TRUE;
3513 break;
3514 case 0x27:
3515 pFrameBufInfo->u8BitPerPixel = 16;
3516 pFrameBufInfo->bInterlace = TRUE;
3517 break;
3518 case 0x21:
3519 if(BIT(1) == SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_04_L:REG_SC_BK12_44_L, BIT(0)|BIT(1)))
3520 {
3521 pFrameBufInfo->u8BitPerPixel = 24;
3522 }
3523 else
3524 {
3525 pFrameBufInfo->u8BitPerPixel = 20;
3526 }
3527 pFrameBufInfo->bInterlace = FALSE;
3528 break;
3529 case 0x20:
3530 pFrameBufInfo->u8BitPerPixel = 16;
3531 pFrameBufInfo->bInterlace = FALSE;
3532 break;
3533 case 0x00:
3534 default:
3535 pFrameBufInfo->u8BitPerPixel = 16;
3536 pFrameBufInfo->bInterlace = FALSE;
3537 break;
3538 }
3539 }
3540 }
3541
3542 //In M10/J2/A5/A6/A3, New SCMI
3543 pFrameBufInfo->u8FBNum = (MS_U8)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, (eWindow == MAIN_WINDOW)?REG_SC_BK12_19_L:REG_SC_BK12_59_L, 0x1F));
3544
3545 #if 0
3546 printf("base0=0x%x, base1=0x%x, base2=0x%x, offset=%u, 422=%u, i=%u, bpp=%u, fbnum=%u\n",
3547 (unsigned int)pFrameBufInfo->u32IPMBase0,
3548 (unsigned int)pFrameBufInfo->u32IPMBase1,
3549 (unsigned int)pFrameBufInfo->u32IPMBase2,
3550 pFrameBufInfo->u16IPMOffset,
3551 pFrameBufInfo->bMemFormat422,
3552 pFrameBufInfo->bInterlace,
3553 pFrameBufInfo->u8BitPerPixel,
3554 pFrameBufInfo->u8FBNum);
3555 #endif
3556 }
Hal_SC_set_framebuf_Info(void * pInstance,SC_FRAMEBUF_INFO_t pFrameBufInfo)3557 void Hal_SC_set_framebuf_Info(void *pInstance, SC_FRAMEBUF_INFO_t pFrameBufInfo)
3558 {
3559 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3560 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3561 MS_PHY u32IPMBase0, u32IPMBase1, u32IPMBase2;
3562 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3563 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3564
3565 u32IPMBase0=pFrameBufInfo.u32IPMBase0/BYTE_PER_WORD;
3566 u32IPMBase1=pFrameBufInfo.u32IPMBase1/BYTE_PER_WORD;
3567 u32IPMBase2=pFrameBufInfo.u32IPMBase2/BYTE_PER_WORD;
3568
3569 //Step 5.4, Memory Limit V : BK12_18[15] = 1, BK12_18[12:0] to the real V line number
3570 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, (pFrameBufInfo.u16VLength|0x8000),0x8FFF);
3571
3572 // u32WritelimitBase = ((u32IPMBase0 + u32MemSize) / BYTE_PER_WORD - 1) | 0x2000000;
3573 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_1A_L, pFrameBufInfo.u32IPMBase1);
3574 // frcm write base address limit
3575 #if 0
3576 #if (HW_DESIGN_4K2K_VER == 4)
3577 if ((psXCInstPri->u32DeviceID==0)
3578 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
3579 {
3580 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK32_1A_L, pFrameBufInfo.u32FRCMWriteLimitBase);
3581 }
3582 #endif
3583 #endif
3584 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_09_L, (MS_U16)(u32IPMBase0 & 0xFF0000)>>16,0x00FF);
3585 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_08_L, (MS_U16)(u32IPMBase0 & 0xFFFF));
3586
3587 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_0B_L, (MS_U16)(u32IPMBase1 & 0xFF0000)>>16,0x00FF);
3588 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0A_L, (MS_U16)(u32IPMBase1 & 0xFFFF));
3589
3590 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_0D_L, (MS_U16)(u32IPMBase2 & 0xFF0000)>>16,0x00FF);
3591 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0C_L, (MS_U16)(u32IPMBase2 & 0xFFFF));
3592
3593
3594 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0E_L, pFrameBufInfo.u16IPMOffset);
3595 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_0F_L, pFrameBufInfo.u16IPMFetch);
3596 // SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_18_L, (pFrameBufInfo.u16VLength|0x1000),0x1FFF);
3597 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_03_L, ((pFrameBufInfo.bLinearAddrMode)?BIT(4):0),BIT(4));
3598
3599 }
3600
Hal_SC_get_cs_det_cnt(void * pInstance,SCALER_WIN eWindow)3601 MS_U8 Hal_SC_get_cs_det_cnt(void *pInstance, SCALER_WIN eWindow)
3602 {
3603 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3604 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3605 MS_U8 u8val;
3606
3607 if(eWindow == MAIN_WINDOW)
3608 {
3609 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_0C_L) & 0xFF00) >> 8);
3610 }
3611 else
3612 {
3613 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_0C_L) & 0xFF00) >> 8);
3614 }
3615 return u8val;
3616 }
3617
Hal_SC_set_cs_det_cnt(void * pInstance,MS_U8 u8val,SCALER_WIN eWindow)3618 void Hal_SC_set_cs_det_cnt(void *pInstance, MS_U8 u8val, SCALER_WIN eWindow)
3619 {
3620 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3621 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3622 if(eWindow == MAIN_WINDOW)
3623 {
3624 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_0C_L, (((MS_U16)u8val)<<8), 0xFF00);
3625 }
3626 else
3627 {
3628 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_0C_L, (((MS_U16)u8val)<<8), 0xFF00);
3629 }
3630 }
3631
Hal_SC_get_plus_width(void * pInstance,SCALER_WIN eWindow)3632 MS_U8 Hal_SC_get_plus_width(void *pInstance, SCALER_WIN eWindow)
3633 {
3634 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3635 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3636 MS_U8 u8val;
3637
3638 if(eWindow == MAIN_WINDOW)
3639 {
3640 u8val = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_22_L) & 0x00FF);
3641 }
3642 else
3643 {
3644 u8val = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK03_22_L) & 0x00FF);
3645 }
3646 return u8val;
3647 }
3648
Hal_SC_set_opm_fetch(void * pInstance,SCALER_WIN eWindow,MS_U16 u16OPMFetch)3649 void Hal_SC_set_opm_fetch(void *pInstance, SCALER_WIN eWindow, MS_U16 u16OPMFetch)
3650 {
3651 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3652 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3653 if(eWindow == MAIN_WINDOW)
3654 {
3655 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L, u16OPMFetch, 0x0FFF);
3656 }
3657 else
3658 {
3659 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L, u16OPMFetch, 0x0FFF);
3660 }
3661 }
3662
Hal_SC_get_opm_fetch(void * pInstance,SCALER_WIN eWindow)3663 MS_U16 Hal_SC_get_opm_fetch(void *pInstance, SCALER_WIN eWindow)
3664 {
3665 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3666 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3667 MS_U16 u16Val = 0;
3668 if(eWindow == MAIN_WINDOW)
3669 {
3670 u16Val = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_17_L) & 0x0FFF;
3671 }
3672 else
3673 {
3674 u16Val = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_57_L) & 0x0FFF;
3675 }
3676 return u16Val;
3677 }
3678
HAL_SC_get_dnr_setting(void * pInstance,SCALER_WIN eWindow)3679 MS_U8 HAL_SC_get_dnr_setting(void *pInstance, SCALER_WIN eWindow)
3680 {
3681 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3682 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3683 if(eWindow == MAIN_WINDOW)
3684 return (MS_U8)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_21_L, BIT(1)|BIT(0));
3685 else
3686 return (MS_U8)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_01_L, BIT(1)|BIT(0));
3687 }
3688
HAL_SC_enable_field_avg_y(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3689 void HAL_SC_enable_field_avg_y(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3690 {
3691 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3692 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3693 if(eWindow == MAIN_WINDOW)
3694 {
3695 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_21_L, bEnable ? BIT(6) : 0, BIT(6));
3696 }
3697 else
3698 {
3699 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_01_L, bEnable ? BIT(6) : 0, BIT(6));
3700 }
3701
3702 }
3703
HAL_SC_enable_field_avg_c(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3704 void HAL_SC_enable_field_avg_c(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
3705 {
3706 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3707 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3708 if(eWindow == MAIN_WINDOW)
3709 {
3710 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_21_L, bEnable ? BIT(7) : 0, BIT(7));
3711 }
3712 else
3713 {
3714 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_01_L, bEnable ? BIT(7) : 0, BIT(7));
3715 }
3716 }
3717
HAL_SC_enable_dnr(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)3718 void HAL_SC_enable_dnr(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
3719 {
3720 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3721 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3722 if(eWindow == MAIN_WINDOW)
3723 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_21_L, u8Val, BIT(1)|BIT(0));
3724 else
3725 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK06_01_L, u8Val, BIT(1)|BIT(0));
3726 }
3727
HAL_SC_VOP_Set_Contrast_En(void * pInstance,MS_BOOL bEenable,SCALER_WIN eWindow)3728 void HAL_SC_VOP_Set_Contrast_En(void *pInstance, MS_BOOL bEenable, SCALER_WIN eWindow)
3729 {
3730 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3731 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3732 if(eWindow == MAIN_WINDOW)
3733 {
3734 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(0):0), BIT(0));
3735 }
3736 else
3737 {
3738 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(8):0), BIT(8));
3739 }
3740 }
HAL_SC_VOP_Set_Contrast_Value(void * pInstance,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val,SCALER_WIN eWindow)3741 void HAL_SC_VOP_Set_Contrast_Value(void *pInstance, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val, SCALER_WIN eWindow)
3742 {
3743 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3744 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3745 if(eWindow == MAIN_WINDOW)
3746 {
3747 switch(eVop_Channel)
3748 {
3749 default:
3750 case XC_VOP_CHR:
3751 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_47_L, u16Val, 0x0FFF);
3752 break;
3753 case XC_VOP_CHG:
3754 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_48_L, u16Val, 0x0FFF);
3755 break;
3756 case XC_VOP_CHB:
3757 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_49_L, u16Val, 0x0FFF);
3758 break;
3759 case XC_VOP_ALL:
3760 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_47_L, u16Val, 0x0FFF);
3761 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_48_L, u16Val, 0x0FFF);
3762 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_49_L, u16Val, 0x0FFF);
3763 break;
3764 }
3765 }
3766 else
3767 {
3768 switch(eVop_Channel)
3769 {
3770 default:
3771 case XC_VOP_CHR:
3772 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4A_L, u16Val, 0x0FFF);
3773 break;
3774 case XC_VOP_CHG:
3775 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4B_L, u16Val, 0x0FFF);
3776 break;
3777 case XC_VOP_CHB:
3778 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4C_L, u16Val, 0x0FFF);
3779 break;
3780 case XC_VOP_ALL:
3781 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4A_L, u16Val, 0x0FFF);
3782 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4B_L, u16Val, 0x0FFF);
3783 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4C_L, u16Val, 0x0FFF);
3784 break;
3785 }
3786 }
3787 }
3788
HAL_SC_VOP_Set_Brightness_En(void * pInstance,MS_BOOL bEenable,SCALER_WIN eWindow)3789 void HAL_SC_VOP_Set_Brightness_En(void *pInstance, MS_BOOL bEenable, SCALER_WIN eWindow)
3790 {
3791 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3792 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3793 if(eWindow == MAIN_WINDOW)
3794 {
3795 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(1):0), BIT(1));
3796 }
3797 else
3798 {
3799 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_53_L, (MS_U16)(bEenable?BIT(9):0), BIT(9));
3800 }
3801 }
HAL_SC_VOP_Set_Brightness_Value(void * pInstance,MS_XC_VOP_CHANNEL_t eVop_Channel,MS_U16 u16Val,SCALER_WIN eWindow)3802 void HAL_SC_VOP_Set_Brightness_Value(void *pInstance, MS_XC_VOP_CHANNEL_t eVop_Channel, MS_U16 u16Val, SCALER_WIN eWindow)
3803 {
3804 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3805 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3806 if(eWindow == MAIN_WINDOW)
3807 {
3808 switch(eVop_Channel)
3809 {
3810 default:
3811 case XC_VOP_CHR:
3812 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4D_L, u16Val, 0x07FF);
3813 break;
3814 case XC_VOP_CHG:
3815 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4E_L, u16Val, 0x07FF);
3816 break;
3817 case XC_VOP_CHB:
3818 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4F_L, u16Val, 0x07FF);
3819 break;
3820 case XC_VOP_ALL:
3821 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4D_L, u16Val, 0x07FF);
3822 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4E_L, u16Val, 0x07FF);
3823 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_4F_L, u16Val, 0x07FF);
3824 break;
3825 }
3826 }
3827 else
3828 {
3829 switch(eVop_Channel)
3830 {
3831 default:
3832 case XC_VOP_CHR:
3833 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_50_L, u16Val, 0x07FF);
3834 break;
3835 case XC_VOP_CHG:
3836 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_51_L, u16Val, 0x07FF);
3837 break;
3838 case XC_VOP_CHB:
3839 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_52_L, u16Val, 0x07FF);
3840 break;
3841 case XC_VOP_ALL:
3842 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_50_L, u16Val, 0x07FF);
3843 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_51_L, u16Val, 0x07FF);
3844 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_52_L, u16Val, 0x07FF);
3845 break;
3846 }
3847 }
3848 }
3849
HAL_SC_Set_FB_Num(void * pInstance,SCALER_WIN eWindow,XC_FRAME_STORE_NUMBER enFBType,MS_BOOL bInterlace)3850 void HAL_SC_Set_FB_Num(void *pInstance, SCALER_WIN eWindow, XC_FRAME_STORE_NUMBER enFBType, MS_BOOL bInterlace)
3851 {
3852 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3853 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3854 MS_U8 u8FrameCount = 2;
3855
3856 switch( enFBType )
3857 {
3858 case IMAGE_STORE_2_FRAMES:
3859 u8FrameCount = 2;
3860 break;
3861 case IMAGE_STORE_3_FRAMES:
3862 u8FrameCount = 3;
3863 break;
3864 case IMAGE_STORE_4_FRAMES:
3865 u8FrameCount = 4;
3866 break;
3867 case IMAGE_STORE_6_FRAMES:
3868 u8FrameCount = 6;
3869 break;
3870 case IMAGE_STORE_8_FRAMES:
3871 u8FrameCount = 8;
3872 break;
3873 case IMAGE_STORE_12_FRAMES:
3874 u8FrameCount = 12;
3875 break;
3876 default:
3877 break;
3878 }
3879
3880 if (!bInterlace)
3881 {
3882 if (eWindow == MAIN_WINDOW)
3883 {
3884 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L, u8FrameCount , BITMASK(4:0) );
3885 }
3886 else
3887 {
3888 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L, u8FrameCount , BITMASK(4:0) );
3889 }
3890 }
3891 }
3892
HAL_SC_Enable_VInitFactor(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)3893 void HAL_SC_Enable_VInitFactor(void *pInstance, MS_BOOL bEnable,SCALER_WIN eWindow)
3894 {
3895 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3896 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3897 if (eWindow == MAIN_WINDOW)
3898 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_13_L, (MS_U16)(bEnable?BIT(0):0), BIT(0));
3899 else
3900 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_33_L, (MS_U16)(bEnable?BIT(0):0), BIT(0));
3901 }
3902
HAL_SC_Set_VInitFactorOne(void * pInstance,MS_U32 u32Value,SCALER_WIN eWindow)3903 void HAL_SC_Set_VInitFactorOne(void *pInstance, MS_U32 u32Value,SCALER_WIN eWindow)
3904 {
3905 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3906 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3907 if (eWindow == MAIN_WINDOW)
3908 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_03_L, u32Value);
3909 else
3910 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_23_L, u32Value);
3911 }
3912
HAL_SC_Set_VInitFactorTwo(void * pInstance,MS_U32 u32Value,SCALER_WIN eWindow)3913 void HAL_SC_Set_VInitFactorTwo(void *pInstance, MS_U32 u32Value,SCALER_WIN eWindow)
3914 {
3915 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3916 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3917 if (eWindow == MAIN_WINDOW)
3918 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_05_L, u32Value);
3919 else
3920 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_25_L, u32Value);
3921 }
3922
HAL_SC_Set_vsd_output_line_count(void * pInstance,MS_BOOL bEnable,MS_U32 u32LineCount,SCALER_WIN eWindow)3923 void HAL_SC_Set_vsd_output_line_count(void *pInstance, MS_BOOL bEnable,MS_U32 u32LineCount,SCALER_WIN eWindow)
3924 {
3925 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3926 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3927 MS_U16 u16OutputLineCount = 0x00;
3928
3929 if (bEnable)
3930 {
3931 u16OutputLineCount = BIT(15);
3932 u16OutputLineCount |= (MS_U16)(u32LineCount & 0x1FFF);
3933 }
3934
3935 if (eWindow == MAIN_WINDOW)
3936 {
3937 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_37_L, u16OutputLineCount);
3938 }
3939 else
3940 {
3941 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_37_L, u16OutputLineCount);
3942 }
3943
3944 }
3945
3946 /*
3947 bEnable : Enable input line count.
3948 bUserMode : 1 -> the input line count will ref u32UserLineCount
3949 0 -> the input line count will ref V capture win
3950 */
HAL_SC_Set_vsd_input_line_count(void * pInstance,MS_BOOL bEnable,MS_BOOL bUserMode,MS_U32 u32UserLineCount,SCALER_WIN eWindow)3951 void HAL_SC_Set_vsd_input_line_count(void *pInstance, MS_BOOL bEnable,MS_BOOL bUserMode,MS_U32 u32UserLineCount,SCALER_WIN eWindow)
3952 {
3953 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3954 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3955 MS_U16 u16InputLineCount = 0x00;
3956
3957 if (bEnable)
3958 {
3959 u16InputLineCount = BIT(15);
3960
3961 if (bUserMode)
3962 {
3963 u16InputLineCount |= BIT(14);
3964 u16InputLineCount |= (MS_U16)(u32UserLineCount & 0x1FFF);
3965 }
3966 }
3967
3968 if (eWindow == MAIN_WINDOW)
3969 {
3970 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_36_L, u16InputLineCount);
3971 }
3972 else
3973 {
3974 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK04_36_L, u16InputLineCount);
3975 }
3976
3977 }
3978
Hal_SC_CheckSubWinPreScaling(MS_U16 u16ScaleDst,MS_BOOL bInterlace)3979 MS_U32 Hal_SC_CheckSubWinPreScaling(MS_U16 u16ScaleDst,MS_BOOL bInterlace)
3980 {
3981 UNUSED(u16ScaleDst);
3982 UNUSED(bInterlace);
3983 //New chip sub window unnecessary to the same with the main window's pre scaling setting.
3984 return 0;
3985 }
3986
HAL_SC_FilmMode_Patch1(void * pInstance)3987 void HAL_SC_FilmMode_Patch1(void *pInstance)
3988 {
3989 #if 1
3990 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
3991 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
3992 MS_U16 u16Value;
3993 MS_U16 u16RegValue;
3994 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
3995 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
3996
3997 u16RegValue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK22_7D_L, 0xFF);
3998 if(pXCResourcePrivate->sthal_SC.g_bCntFlg)
3999 pXCResourcePrivate->sthal_SC.g_u16TmpValue = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, 0xFF);
4000
4001 if(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_21_L, BIT(6)))
4002 {
4003 //Counter
4004 if(pXCResourcePrivate->sthal_SC.u8Time_count != 0xFF)
4005 pXCResourcePrivate->sthal_SC.u8Time_count ++;
4006
4007 if(pXCResourcePrivate->sthal_SC.u8Time_count < u16RegValue) // fake out duration
4008 u16Value = 0x06; // madi fake out enable
4009 else
4010 u16Value = 0x00; // madi fake out disable
4011
4012 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_25_L, (0x10<<8), 0xFF00);
4013 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, 0x22, 0xFF);
4014 pXCResourcePrivate->sthal_SC.g_bCntFlg = 0;
4015 }
4016 else
4017 {
4018 pXCResourcePrivate->sthal_SC.u8Time_count = 0;
4019 u16Value = 0x00; // madi fake out disable
4020 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_25_L, (0x08<<8), 0xFF00);
4021 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_02_L, pXCResourcePrivate->sthal_SC.g_u16TmpValue, 0xFF);
4022 pXCResourcePrivate->sthal_SC.g_bCntFlg = 1;
4023 }
4024 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0A_21_L, u16Value, BIT(2)|BIT(1));
4025
4026 #else
4027 MS_U8 u8Bank, u8Value;
4028 MS_U8 u8RegValue;
4029
4030 static MS_U8 u8Time_count = 0;
4031
4032 MDrv_WriteByte(BK_SELECT_00, REG_BANK_MADI); //bk22
4033 u8RegValue = MDrv_ReadByte(L_BK_MADI(0x7D));
4034
4035 MDrv_WriteByte(BK_SELECT_00, REG_BANK_FILM);
4036
4037
4038 if(MDrv_ReadRegBit(L_BK_FILM(0x21), BIT(6)))
4039 {
4040 //Counter
4041 if(u8Time_count != 0xFF)
4042 u8Time_count ++;
4043
4044 if(u8Time_count < u8RegValue) // fake out duration
4045 u8Value = 0x06; // madi fake out enable
4046 else
4047 u8Value = 0x00; // madi fake out disable
4048
4049 MDrv_WriteByte(H_BK_FILM(0x25), 0x10);
4050
4051 }
4052 else
4053 {
4054 u8Time_count = 0;
4055 u8Value = 0x00; // madi fake out disable
4056 MDrv_WriteByte(H_BK_FILM(0x25), 0x08);
4057 }
4058
4059 MDrv_WriteByteMask(L_BK_FILM(0x21), u8Value, BIT(2)|BIT(1));
4060 MDrv_WriteByte(BK_SELECT_00, u8Bank);
4061 #endif
4062 }
4063
HAL_SC_EnableFPLL(void)4064 void HAL_SC_EnableFPLL(void)
4065 {
4066 MDrv_WriteByteMask(L_BK_LPLL(0x0C), BIT(3), BIT(3));
4067 MDrv_WriteByteMask(L_BK_LPLL(0x0C), 0, BIT(6));
4068 }
4069
4070
_HAL_SC_GetFPLLPhaseDiffISR(SC_INT_SRC eIntNum,void * pParam)4071 static void _HAL_SC_GetFPLLPhaseDiffISR(SC_INT_SRC eIntNum, void *pParam)
4072 {
4073 volatile MS_XC_GET_FPLL_PHASEDIFF * pFpllPhaseDiff = (volatile MS_XC_GET_FPLL_PHASEDIFF *) pParam;
4074
4075 pFpllPhaseDiff->u16PhaseDiff = MDrv_Read2Byte(L_BK_LPLL(0x11));
4076 pFpllPhaseDiff->eFpllDir = (MDrv_Read2Byte(L_BK_LPLL(0x12)) & BIT(0)) == BIT(0) ? E_XC_FPLL_DIR_UP : E_XC_FPLL_DIR_DOWN;
4077 pFpllPhaseDiff->u8Debounce++;
4078
4079 if(pFpllPhaseDiff->u8Debounce > 3)
4080 {
4081 if(pFpllPhaseDiff->u16PhaseDiff < 0x200)
4082 {
4083 pFpllPhaseDiff->eFpllResult = E_XC_FPLL_RES_FINISHED;
4084 }
4085 else
4086 {
4087 if(pFpllPhaseDiff->u8Debounce > 90)
4088 {
4089 pFpllPhaseDiff->eFpllResult = E_XC_FPLL_RES_TIMEOUT;
4090 }
4091 }
4092 }
4093 }
4094
HAL_SC_WaitFPLLDone(void * pInstance)4095 MS_BOOL HAL_SC_WaitFPLLDone(void *pInstance)
4096 {
4097 MS_XC_GET_FPLL_PHASEDIFF stGetFpllPhaseDiff = {0, 0, E_XC_FPLL_DIR_UNKNOWN, E_XC_FPLL_RES_WAITING};
4098
4099 MDrv_XC_InterruptAttach(pInstance, SC_INT_VSINT, _HAL_SC_GetFPLLPhaseDiffISR, (void *) &stGetFpllPhaseDiff);
4100 while(*(volatile MS_BOOL*)(&(stGetFpllPhaseDiff.eFpllResult)) == E_XC_FPLL_RES_WAITING);
4101 MDrv_XC_InterruptDeAttach(pInstance, SC_INT_VSINT, _HAL_SC_GetFPLLPhaseDiffISR, (void *) &stGetFpllPhaseDiff);
4102
4103 if(stGetFpllPhaseDiff.eFpllResult == E_XC_FPLL_RES_FINISHED)
4104 {
4105 return TRUE;
4106 }
4107 else
4108 {
4109 return FALSE;
4110 }
4111 }
4112
HAL_SC_GetOutputVFreqX100(MS_U32 u32XTAL_Clock)4113 MS_U16 HAL_SC_GetOutputVFreqX100(MS_U32 u32XTAL_Clock)
4114 {
4115 return ((MS_U16) ((u32XTAL_Clock * 100) / MDrv_Read4Byte(L_BK_LPLL(0x23))));
4116 }
4117
4118 //Line buffer offset between Main and Sub, MAX(Main+Sub) = 1920+960
4119 //Main Win Line buffer offset , start from max size of main's
HAL_SC_SetMainLineBufferOffset(void * pInstance,MS_U16 u16Linebuffer)4120 void HAL_SC_SetMainLineBufferOffset(void *pInstance, MS_U16 u16Linebuffer)
4121 {
4122 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4123 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4124 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_12_L, u16Linebuffer);
4125 }
4126
4127 //Line buffer offset between Main and Sub, MAX(Main+Sub) = 1920+960
4128 //Sub Win Line buffer offset , start from max size of main's
HAL_SC_SetSubLineBufferOffset(void * pInstance,MS_U16 u16Linebuffer)4129 void HAL_SC_SetSubLineBufferOffset(void *pInstance, MS_U16 u16Linebuffer)
4130 {
4131 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4132 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4133 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK20_13_L, u16Linebuffer);
4134 }
4135
4136 //Select the trig mode
4137 //0: Line base(Line Buffer Mode)
4138 //1: Fill line buffer(Ring Buffer Mode)
HAL_SC_SetDisplay_LineBuffer_Mode(void * pInstance,MS_BOOL bEnable)4139 void HAL_SC_SetDisplay_LineBuffer_Mode(void *pInstance, MS_BOOL bEnable)
4140 {
4141 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4142 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4143 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1F_L, (bEnable ? BIT(4) : 0), BIT(4));
4144 }
4145
4146 //Select the start mode
4147 //0: start at advance 1 display line
4148 //1: start at faling edge of Vsync_init
HAL_SC_SetDisplay_Start_Mode(void * pInstance,MS_BOOL bEnable)4149 void HAL_SC_SetDisplay_Start_Mode(void *pInstance, MS_BOOL bEnable)
4150 {
4151 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4152 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4153 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_1F_L, (bEnable ? BIT(5) : 0), BIT(5));
4154 }
4155
4156 //bk20_10[10]: Fill the main window's line buffer in vertical blanking for pip left and up corner
4157 //bk20_10[11]: Fill the sub window's line buffer in vertical blanking for pip left and down corner
HAL_SC_FillLineBuffer(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)4158 void HAL_SC_FillLineBuffer(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
4159 {
4160 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4161 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4162 if(bEnable)
4163 {
4164 if(eWindow == MAIN_WINDOW)
4165 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(10), BIT(10));
4166 else
4167 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(11), BIT(11));
4168 }
4169 else
4170 {
4171 if(eWindow == MAIN_WINDOW)
4172 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(10));
4173 else
4174 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(11));
4175 }
4176 }
4177
Hal_SC_enable_window(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)4178 void Hal_SC_enable_window(void *pInstance, MS_BOOL bEn,SCALER_WIN eWindow)
4179 {
4180 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4181 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4182 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4183 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4184
4185 if (eWindow == MAIN_WINDOW)
4186 {
4187 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, bEn ? BIT(0) : 0, BIT(0));
4188 }
4189 else
4190 {
4191 // Sub prefill line must be enable, when PIP on (enable input source of sub win)
4192 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, BIT(11) , BIT(11));
4193 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, bEn ? BIT(1) : 0, BIT(1));
4194 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK58_10_L, bEn ? BIT(0) : 0, BIT(0));
4195 }
4196 #ifdef XC_SUPPORT_2STEP_SCALING
4197 if ((MDrv_XC_IsSupport2StepScaling() == TRUE) && MDrv_XC_GetMWEStatus(pInstance))
4198 {
4199 if (bEn == TRUE)
4200 {
4201 if (SC_R2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0)) == BIT(0)) // enable 2-step scaling.
4202 {
4203 P_SC_SWDB_INFO pDBreg = &pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg;
4204 // Disable 2 Step Scaling
4205 SC_W2BYTEMSK(0, REG_SC_BK4F_10_L, 0, BIT(0));
4206 // Adjust XC postScaling
4207 MS_U32 u32TmpScaling = 0;
4208 //H post-scaling
4209 u32TmpScaling = pDBreg->u32H_PostScalingRatio & (~0x1000000L);
4210 u32TmpScaling = u32TmpScaling/2;
4211 u32TmpScaling |= 0x1000000L;
4212
4213 SC_W2BYTEMSK(0, REG_SC_BK23_07_L, (MS_U16)(u32TmpScaling>>00), 0xFFFF);
4214 SC_W2BYTEMSK(0, REG_SC_BK23_08_L, (MS_U16)(u32TmpScaling>>16), 0xFFFF);
4215
4216 //V post-scaling
4217 u32TmpScaling = pDBreg->u32V_PostScalingRatio & (~0x1000000L);
4218 u32TmpScaling = u32TmpScaling/2;
4219 u32TmpScaling |= 0x1000000L;
4220 SC_W2BYTEMSK(0, REG_SC_BK23_09_L, (MS_U16)(u32TmpScaling>>00), 0xFFFF);
4221 SC_W2BYTEMSK(0, REG_SC_BK23_0A_L, (MS_U16)(u32TmpScaling>>16), 0xFFFF);
4222 }
4223 }
4224 else
4225 {
4226 if (SC_R2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0)) == 0) // Disable 2-step scaling.
4227 {
4228 P_SC_SWDB_INFO pDBreg = &pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg;
4229 // Restore 2 Step Scaling
4230 SC_W2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0), BIT(0));
4231 // Restore XC postScaling
4232 //H post-scaling
4233
4234 SC_W2BYTEMSK(0, REG_SC_BK23_07_L, (MS_U16)((pDBreg->u32H_PostScalingRatio)>>00), 0xFFFF);
4235 SC_W2BYTEMSK(0, REG_SC_BK23_08_L, (MS_U16)((pDBreg->u32H_PostScalingRatio)>>16), 0xFFFF);
4236 //V post-scaling
4237 SC_W2BYTEMSK(0, REG_SC_BK23_09_L, (MS_U16)((pDBreg->u32V_PostScalingRatio)>>00), 0xFFFF);
4238 SC_W2BYTEMSK(0, REG_SC_BK23_0A_L, (MS_U16)((pDBreg->u32V_PostScalingRatio)>>16), 0xFFFF);
4239 }
4240 }
4241 }
4242
4243 #endif
4244 }
4245
_Hal_SC_GetInputVPeriod(void * pInstance,SCALER_WIN eWindow)4246 static MS_U16 _Hal_SC_GetInputVPeriod(void *pInstance, SCALER_WIN eWindow)
4247 {
4248 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4249 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4250 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4251 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4252 MS_U16 u16VFreq = gSrcInfo[eWindow].u16InputVFreq * 10;
4253 SC_DBG(printf("(100000+u16VFreq/2)/u16VFreq)=%u, u16VFreq=%u\n",((100000+u16VFreq/2)/u16VFreq), u16VFreq));
4254 if(u16VFreq == 0)
4255 {
4256 return 0;
4257 }
4258 else
4259 {
4260 return ((100000+u16VFreq/2)/u16VFreq); //Period = 1000/(vfreq/100)
4261 }
4262 }
4263
Hal_SC_enable_window_burst(void * pInstance,MS_BOOL bEn,SCALER_WIN eWindow)4264 void Hal_SC_enable_window_burst(void *pInstance, MS_BOOL bEn,SCALER_WIN eWindow)
4265 {
4266 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4267 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4268 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4269 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4270 _MLOAD_ENTRY(pInstance);
4271 if (eWindow == MAIN_WINDOW)
4272 {
4273 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, bEn ? BIT(0) : 0, BIT(0));
4274 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4275 }
4276 else
4277 {
4278 if(bEn == TRUE)
4279 {
4280 MS_U16 u16extra_req = 0;
4281 MS_U16 u16Delaytime = 0;
4282
4283 // When Main is foreground, sub is background, extra must enable.
4284 u16extra_req = 0x01;
4285
4286 if(Hal_SC_is_extra_req_en(pInstance, NULL, NULL , NULL , NULL))
4287 {
4288 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(15), BIT(15));
4289 u16extra_req = u16extra_req | 0x8000;
4290 }
4291
4292 // HW PIP architeucture
4293 // Becasue BK3_02[8] and BK20_11[15] should enable together, otherwise garbage will be showed,
4294 // we need to use BK12_47[0] to instead. And the default value of BK3_02[8] is 1. So, we need
4295 // to set it to 0 in this function.
4296 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, u16extra_req , 0x800F);
4297 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, 0, 0x0080);
4298
4299 // Sub prefill line must be enable, when PIP on (enable input source of sub win)
4300 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, BIT(11), BIT(11) );
4301 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4302 //if we let REG_SC_BK20_10_L[1] to enable with other register settings in the same menuload fire
4303 //it will produce a rectangular horizontal noise. so we move outside to let those register settings
4304 //to be set first then let REG_SC_BK20_10_L[1] on.
4305
4306 //betwen REG_SC_BK03_02_L[7] and REG_SC_BK20_10_L[1], we need to delay time of wr mapping mode,
4307 // to let the data fill in xc sub buffer
4308 u16Delaytime = _Hal_SC_GetInputVPeriod(pInstance, eWindow) * (Hal_SC_Get_WR_Bank_Mapping(pInstance, eWindow) + 1);
4309 MsOS_DelayTask(u16Delaytime);
4310
4311 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, BIT(1), BIT(1));
4312 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK58_10_L, BIT(0), BIT(0));
4313 #ifdef XC_SUPPORT_2STEP_SCALING
4314 if ((MDrv_XC_IsSupport2StepScaling() == TRUE) && MDrv_XC_GetMWEStatus(pInstance))
4315 {
4316 if (SC_R2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0)) == BIT(0)) // enable 2-step scaling.
4317 {
4318 P_SC_SWDB_INFO pDBreg = &pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg;
4319 // Disable 2 Step Scaling
4320 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_10_L, 0, BIT(0));
4321 // Adjust XC postScaling
4322 MS_U32 u32TmpScaling = 0;
4323
4324 //H post-scaling
4325 u32TmpScaling = pDBreg->u32H_PostScalingRatio & (~0x1000000L);
4326 u32TmpScaling = u32TmpScaling/2;
4327 u32TmpScaling |= 0x1000000L;
4328 //H post-scaling
4329 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_07_L, (MS_U16)(u32TmpScaling>>00), 0xFFFF);
4330 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_08_L, (MS_U16)(u32TmpScaling>>16), 0xFFFF);
4331 //V post-scaling
4332 u32TmpScaling = pDBreg->u32V_PostScalingRatio & (~0x1000000L);
4333 u32TmpScaling = u32TmpScaling/2;
4334 u32TmpScaling |= 0x1000000L;
4335 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_09_L, (MS_U16)(u32TmpScaling>>00), 0xFFFF);
4336 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_0A_L, (MS_U16)(u32TmpScaling>>16), 0xFFFF);
4337 }
4338 }
4339 #endif
4340
4341 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4342 }
4343 else
4344 {
4345 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK58_10_L, 0, BIT(0));
4346 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, 0, BIT(1));
4347 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4348 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK03_02_L, 0x0080, 0x0080);
4349 #ifdef XC_SUPPORT_2STEP_SCALING
4350 if ((MDrv_XC_IsSupport2StepScaling() == TRUE) && MDrv_XC_GetMWEStatus(pInstance))
4351 {
4352 if (SC_R2BYTEMSK(0, REG_SC_BK4F_10_L, BIT(0)) == 0) // Disable 2-step scaling.
4353 {
4354 P_SC_SWDB_INFO pDBreg = &pXCResourcePrivate->stdrvXC_MVideo_Context.stDBreg;
4355 // Restore 2 Step Scaling
4356 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK4F_10_L, BIT(0), BIT(0));
4357 // Restore XC postScaling
4358 //H post-scaling
4359 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_07_L, (MS_U16)((pDBreg->u32H_PostScalingRatio)>>00), 0xFFFF);
4360 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_08_L, (MS_U16)((pDBreg->u32H_PostScalingRatio)>>16), 0xFFFF);
4361 //V post-scaling
4362 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_09_L, (MS_U16)((pDBreg->u32V_PostScalingRatio)>>00), 0xFFFF);
4363 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK23_0A_L, (MS_U16)((pDBreg->u32V_PostScalingRatio)>>16), 0xFFFF);
4364 }
4365 }
4366 #endif
4367 MDrv_XC_MLoad_Fire(pInstance, TRUE);
4368 }
4369 }
4370 _MLOAD_RETURN(pInstance);
4371 }
4372
Hal_SC_set_trigger_signal(void)4373 void Hal_SC_set_trigger_signal(void)
4374 {
4375 // only used in U4
4376 }
4377
Hal_SC_Set_OSD2VE(void * pInstance,EN_VOP_SEL_OSD_XC2VE_MUX eVOPSelOSD_MUX)4378 void Hal_SC_Set_OSD2VE(void *pInstance, EN_VOP_SEL_OSD_XC2VE_MUX eVOPSelOSD_MUX)
4379 {
4380 UNUSED(eVOPSelOSD_MUX);
4381 }
4382
Hal_SC_IsOPMFetchPatch_Enable(void)4383 MS_BOOL Hal_SC_IsOPMFetchPatch_Enable(void)
4384 {
4385 //Patch for Janus u01 and T4 U01/02: OPMFetch need +2
4386 return FALSE;
4387 }
Hal_SC_Check_HNonLinearScaling(void * pInstance)4388 MS_BOOL Hal_SC_Check_HNonLinearScaling(void *pInstance)
4389 {
4390 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4391 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4392 MS_U16 u16Offset = (SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_15_L)>>8);
4393 MS_U16 u16MaxOffset = ((SC_R4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L) & 0xFFFFFF)>>12);
4394 //Non-Linear scaling Postive offset, the maximum offset is HPstRatio[23:12]
4395 if(((u16Offset & BIT(7)) == 0) && (u16Offset > u16MaxOffset))
4396 {
4397 return FALSE;
4398 }
4399 return TRUE;
4400 }
4401
4402 //IP2 Pre-Filter enable
Hal_SC_IP2_PreFilter_Enable(void * pInstance,MS_BOOL bEnable)4403 void Hal_SC_IP2_PreFilter_Enable(void* pInstance, MS_BOOL bEnable)
4404 {
4405 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4406 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4407 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_48_L, (bEnable?BIT(15):0), BIT(15));
4408 }
4409
Hal_SC_Set_extra_fetch_line(void * pInstance,MS_U8 u8val)4410 void Hal_SC_Set_extra_fetch_line(void *pInstance, MS_U8 u8val)
4411 {
4412 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4413 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4414 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_17_L, ((MS_U16)(u8val & 0x0F))<<8, 0x0F00);
4415 }
4416
Hal_SC_Set_extra_adv_line(void * pInstance,MS_U8 u8val)4417 void Hal_SC_Set_extra_adv_line(void *pInstance, MS_U8 u8val)
4418 {
4419 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4420 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4421 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_17_L, ((MS_U16)(u8val & 0x0F))<<12, 0xF000);
4422 }
4423
HAL_SC_Set_FPLL_Limit(void * pInstance,MS_U32 * u32PllSet,MS_U32 u32LowBound,MS_U32 u32UpBound,MS_BOOL _bInFPLLDbgMode,MS_U32 _U32LimitD5D6D7)4424 void HAL_SC_Set_FPLL_Limit(void *pInstance, MS_U32 *u32PllSet, MS_U32 u32LowBound, MS_U32 u32UpBound, MS_BOOL _bInFPLLDbgMode, MS_U32 _U32LimitD5D6D7)
4425 {
4426 MS_U32 u32LpllLimitLow, u32LpllLimitHigh;
4427 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4428 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4429 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4430 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4431 //printf("Fpll_Limit: Set %lx, bound (%lx -> %lx)\n", *u32PllSet, u32UpBound, u32LowBound);
4432
4433 if(_bInFPLLDbgMode)
4434 {
4435 MDrv_WriteByteMask(L_BK_LPLL(0x0D), 0x00, BIT(4)); // turn off 2 limit
4436 if(!pXCResourcePrivate->stdrvXC_MVideo._SContext.bEnableFPLLManualDebug)
4437 {
4438 MDrv_Write3Byte(L_BK_LPLL(0x06), _U32LimitD5D6D7);
4439 }
4440 }
4441 else
4442 {
4443 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit
4444
4445 // check if u32PllSet out of range and also the FPLL limit
4446 if (*u32PllSet <= u32LowBound)
4447 {
4448 *u32PllSet = u32LowBound;
4449 gSrcInfo[MAIN_WINDOW].bEnableFPLL = FALSE;
4450 }
4451 else if (*u32PllSet >= u32UpBound)
4452 {
4453 *u32PllSet = u32UpBound;
4454 gSrcInfo[MAIN_WINDOW].bEnableFPLL = FALSE;
4455 }
4456
4457 u32LpllLimitHigh = u32UpBound - *u32PllSet;
4458 u32LpllLimitLow = *u32PllSet - u32LowBound - 1;
4459
4460 //printf("Fpll set %lx, limit (high %lx, low %lx)\n", *u32PllSet, u32LpllLimitHigh, u32LpllLimitLow);
4461
4462 if(!pXCResourcePrivate->stdrvXC_MVideo._SContext.bEnableFPLLManualDebug)
4463 {
4464 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh);
4465 MDrv_Write3Byte(L_BK_LPLL(0x08), u32LpllLimitLow);
4466 }
4467
4468 //printf("Fpll limit reg (high %lx, low %lx)\n", MDrv_Read4Byte(L_BK_LPLL(0x06)), MDrv_Read4Byte(L_BK_LPLL(0x08)));
4469 }
4470 }
4471
Hal_XC_H3D_Enable(void * pInstance,MS_BOOL bEn)4472 void Hal_XC_H3D_Enable(void *pInstance, MS_BOOL bEn)
4473 {
4474 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4475 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4476 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_70_L, (bEn<<15), (BIT(15)));
4477 }
4478
Hal_XC_H3D_Input3DType(void * pInstance,E_XC_3D_INPUT_MODE e3DType)4479 void Hal_XC_H3D_Input3DType(void *pInstance, E_XC_3D_INPUT_MODE e3DType)
4480 {
4481 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4482 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4483 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (e3DType), (BIT(1) | BIT(0)));
4484 }
4485
Hal_XC_H3D_Breakline_Enable(void * pInstance,MS_BOOL bEn)4486 void Hal_XC_H3D_Breakline_Enable(void *pInstance, MS_BOOL bEn)
4487 {
4488 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4489 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4490 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (bEn<<7), (BIT(7)));
4491 if(bEn)
4492 {
4493 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (8<<8), HBMASK);
4494 }
4495 else
4496 {
4497 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_7B_L, (0<<8), HBMASK);
4498 }
4499 }
4500
Hal_XC_H3D_HDE(void * pInstance,MS_U16 u16Hde)4501 void Hal_XC_H3D_HDE(void *pInstance, MS_U16 u16Hde)
4502 {
4503 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4504 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4505 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_71_L, (u16Hde), 0x0FFF);
4506 }
4507
Hal_XC_H3D_VDE_F0(MS_U16 u16Vde)4508 void Hal_XC_H3D_VDE_F0(MS_U16 u16Vde)
4509 {
4510 SC_W2BYTEMSK(0, REG_SC_BK01_73_L, (u16Vde), 0x0FFF);
4511 }
4512
Hal_XC_H3D_VDE_F2(MS_U16 u16Vde)4513 void Hal_XC_H3D_VDE_F2(MS_U16 u16Vde)
4514 {
4515 SC_W2BYTEMSK(0, REG_SC_BK01_77_L, (u16Vde), 0x0FFF);
4516 }
4517
Hal_XC_H3D_HBLANK(MS_U16 u16Hblank)4518 void Hal_XC_H3D_HBLANK(MS_U16 u16Hblank)
4519 {
4520 SC_W2BYTEMSK(0, REG_SC_BK01_70_L, (u16Hblank), 0x03FF);
4521 }
4522
Hal_XC_H3D_INIT_VBLANK(MS_U8 u8Vblank)4523 void Hal_XC_H3D_INIT_VBLANK(MS_U8 u8Vblank)
4524 {
4525 SC_W2BYTEMSK(0, REG_SC_BK01_72_L, (u8Vblank), LBMASK);
4526 }
4527
Hal_XC_H3D_VBLANK0(MS_U8 u8Vblank)4528 void Hal_XC_H3D_VBLANK0(MS_U8 u8Vblank)
4529 {
4530 SC_W2BYTEMSK(0, REG_SC_BK01_74_L, (u8Vblank), LBMASK);
4531 }
4532
Hal_XC_H3D_VBLANK1(MS_U8 u8Vblank)4533 void Hal_XC_H3D_VBLANK1(MS_U8 u8Vblank)
4534 {
4535 SC_W2BYTEMSK(0, REG_SC_BK01_76_L, (u8Vblank), LBMASK);
4536 }
4537
Hal_XC_H3D_VBLANK2(MS_U8 u8Vblank)4538 void Hal_XC_H3D_VBLANK2(MS_U8 u8Vblank)
4539 {
4540 SC_W2BYTEMSK(0, REG_SC_BK01_78_L, (u8Vblank), LBMASK);
4541 }
4542
Hal_XC_H3D_VSYNC_WIDTH(MS_U8 u8Width)4543 void Hal_XC_H3D_VSYNC_WIDTH(MS_U8 u8Width)
4544 {
4545 SC_W2BYTEMSK(0, REG_SC_BK01_7A_L, (u8Width), 0x001F);
4546 }
4547
Hal_XC_H3D_VSYNC_POSITION(MS_U16 u16Position)4548 void Hal_XC_H3D_VSYNC_POSITION(MS_U16 u16Position)
4549 {
4550 SC_W2BYTEMSK(0, REG_SC_BK01_7A_L, (u16Position), HBMASK);
4551 }
4552
Hal_XC_H3D_SELECT_REGEN_TIMING(MS_BOOL bEn)4553 void Hal_XC_H3D_SELECT_REGEN_TIMING(MS_BOOL bEn)
4554 {
4555 SC_W2BYTEMSK(0, REG_SC_BK01_7B_L, (bEn<<4), (BIT(4)));
4556 }
4557
Hal_XC_H3D_LR_Toggle_Enable(void * pInstance,MS_BOOL bEn,MS_BOOL b2DTo3D,MS_BOOL bSkipDefaultLRFlag)4558 void Hal_XC_H3D_LR_Toggle_Enable(void *pInstance, MS_BOOL bEn, MS_BOOL b2DTo3D, MS_BOOL bSkipDefaultLRFlag)
4559 {
4560 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4561 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4562 if(!bSkipDefaultLRFlag)
4563 {
4564 if(bEn)
4565 {
4566 //Enanble I2S_IN_SD to send out lr flag
4567 MDrv_WriteByteMask(0x101E24, 0x00, BIT(4)|BIT(5)|BIT(6));
4568 MDrv_WriteByteMask(0x101EC9, 0x00, BIT(0)|BIT(1));
4569 MDrv_WriteByteMask(0x101EDC, 0x00, BIT(2));
4570 MDrv_WriteByteMask(0x101EB3, 0xC0, 0xC0);
4571 // after timing change , hw must do L/R alignment,BK12, 33[2]=1 to enable it.
4572 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, BIT(2), BIT(2));
4573 }
4574 else
4575 {
4576 MDrv_WriteByteMask(0x101EB3, 0x00, 0xC0);
4577 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, 0, BIT(2));
4578 }
4579 }
4580
4581 if(b2DTo3D)
4582 {
4583 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_24_L, BIT(11), BIT(0)|BIT(1)|BIT(11)); //Output 3D L/R selection
4584 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_30_L, (bEn<<8), (BIT(8))); //enable Enable free run 3D LR flag
4585 }
4586 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_33_L, (bEn<<1), (BIT(1)));
4587 }
4588
HAL_XC_H3D_OPM_SBYS_PIP_Enable(void * pInstance,MS_BOOL bEn)4589 void HAL_XC_H3D_OPM_SBYS_PIP_Enable(void *pInstance, MS_BOOL bEn)
4590 {
4591 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4592 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4593 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_34_L, (bEn<<7), (BIT(7)));
4594 }
4595
Hal_SC_enable_cursor_report(void * pInstance,MS_BOOL bEn)4596 void Hal_SC_enable_cursor_report(void *pInstance, MS_BOOL bEn)
4597 {
4598 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4599 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4600 if(bEn)
4601 {
4602 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(8) | BIT(10), BIT(8) | BIT(10));
4603 }
4604 else
4605 {
4606 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00 , BIT(8) | BIT(10));
4607 }
4608 }
4609
Hal_SC_get_pixel_rgb(void * pInstance,XC_Get_Pixel_RGB * pData)4610 MS_BOOL Hal_SC_get_pixel_rgb(void *pInstance, XC_Get_Pixel_RGB *pData)
4611 {
4612 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4613 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4614 MS_BOOL bret = TRUE;
4615
4616 switch(pData->enStage)
4617 {
4618 case E_XC_GET_PIXEL_STAGE_AFTER_DLC:
4619 //SC_W2BYTEMSK(0, REG_SC_BK0F_46_L, 0x00 , BMASK(3:0));
4620 bret = FALSE;//Not support, Must set to stage C for HW issue
4621 break;
4622 case E_XC_GET_PIXEL_STAGE_PRE_GAMMA:
4623 //SC_W2BYTEMSK(0, REG_SC_BK0F_46_L, 0x08, BMASK(3:0));
4624 bret = FALSE;//Not support, Must set to stage C for HW issue
4625 break;
4626 case E_XC_GET_PIXEL_STAGE_AFTER_OSD:
4627 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, 0x0D, 0xFF);
4628 break;
4629 default:
4630 bret = FALSE;
4631 break;
4632 }
4633 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4634 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4635 if(bret)
4636 {
4637 // Enable
4638 if(!pXCResourcePrivate->stdrvXC_MVideo.s_bKeepPixelPointerAppear)
4639 {
4640 Hal_SC_enable_cursor_report(pInstance, TRUE);
4641 }
4642
4643 // Initial position (x,y) Set point you want to read.
4644 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_19_L, pData->u16x);
4645 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_1A_L, pData->u16y);
4646
4647 //SW trigger for reading
4648 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, BIT(8), BIT(8));
4649 MsOS_DelayTask(5);
4650 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_18_L, 0, BIT(8));
4651 MsOS_DelayTask(32); // Must wait .
4652
4653 pData->u32r = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2D_L);
4654 pData->u32g = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2E_L);
4655 pData->u32b = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_2F_L);
4656
4657 // Disable
4658 if(!pXCResourcePrivate->stdrvXC_MVideo.s_bKeepPixelPointerAppear)
4659 {
4660 Hal_SC_enable_cursor_report(pInstance, FALSE);
4661 }
4662 }
4663 return bret;
4664 }
4665
Hal_SC_SetOPWriteOff(void * pInstance,MS_BOOL bEna)4666 void Hal_SC_SetOPWriteOff(void *pInstance, MS_BOOL bEna)
4667 {
4668 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4669 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4670 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4671 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4672
4673 MS_BOOL u16OldReg = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, BIT(0)));
4674
4675 #if (HW_DESIGN_4K2K_VER == 4)
4676 // For monaco new chip design, only Legacy mode need to control OPW
4677 // If Monaco mode, always keep OPW is on
4678 if ((psXCInstPri->u32DeviceID==0)
4679 && !(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_Init_Misc.u32MISC_A & E_XC_INIT_MISC_A_LEGACY_MODE))
4680 {
4681 bEna = FALSE;
4682 }
4683 #endif
4684
4685 if(u16OldReg != bEna)
4686 {
4687 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, bEna, BIT(0));//This will stop OPW only, OP memory write request still on
4688 }
4689 }
4690
4691
Hal_SC_GetOPWriteOff(void * pInstance)4692 MS_BOOL Hal_SC_GetOPWriteOff(void *pInstance)
4693 {
4694 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4695 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4696 return (MS_BOOL)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_27_L, BIT(0));
4697 }
4698
Hal_SC_Detect_RequestFBL_Mode(void * pInstance)4699 MS_BOOL Hal_SC_Detect_RequestFBL_Mode(void *pInstance)
4700 {
4701 UNUSED(pInstance);
4702 return ENABLE_REQUEST_FBL;
4703 }
4704
Hal_SC_Set_RequestFBL_Mode(void * pInstance,MS_BOOL bEn)4705 MS_BOOL Hal_SC_Set_RequestFBL_Mode(void *pInstance, MS_BOOL bEn)
4706 {
4707 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4708 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4709 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4710 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4711
4712 if(IsSrcTypeDTV(gSrcInfo[MAIN_WINDOW].enInputSourceType) || (IsSrcTypeStorage(gSrcInfo[MAIN_WINDOW].enInputSourceType)))//MVOP source
4713 {
4714 gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode = bEn;
4715
4716 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, bEn?BIT(14):0 , BIT(14)); //reg_short_1line_disable 1:Disable 0:Enable
4717 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_10_L, bEn?(BIT(0)|BIT(2)):0 , BIT(0)|BIT(2)); // Bit0: Enable HSK mode Bit2:reg_ip2_vs_sel 0:ip1 1:mvop
4718
4719 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_5D_L, 0x1D2A , 0xFFFF);
4720 Hal_XC_MLoad_set_trig_p(pInstance, 0x14, 0x18);
4721
4722 //this feature conflicts with HSK mode
4723 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_45_L, 0x0000, 0x9FFF); // edclk pd control start and edclk pd control enable
4724 }
4725 else
4726 {
4727 gSrcInfo[MAIN_WINDOW].Status2.bMVOPHSKMode = FALSE;
4728
4729 //SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1C_L, 0x0 , BIT(14)); //reg_short_1line_disable 1:Disable 0:Enable
4730 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_10_L, 0x0 , BIT(0)|BIT(2)); // Disable HSK mode Bit2:reg_ip2_vs_sel 0:ip1 1:mvop
4731 }
4732
4733 #ifdef UFO_XC_HDR
4734 #if (UFO_XC_HDR_VERSION == 2)
4735 if (IsSrcTypeHDMI(gSrcInfo[MAIN_WINDOW].enInputSourceType))
4736 {
4737 // enable hdr dma seamless with rfbl mode on maserati
4738 MApi_XC_W2BYTEMSK(REG_SC_BK79_03_L, 1, BIT(15));
4739 }
4740 #endif
4741 #endif
4742
4743 return ENABLE_REQUEST_FBL;
4744 }
4745
Hal_XC_SetFrameColor(void * pInstance,MS_U32 u32aRGB)4746 void Hal_XC_SetFrameColor(void *pInstance, MS_U32 u32aRGB)
4747 {
4748 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4749 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4750 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_19_L, (u32aRGB >> 8),0xFF00); ///< R
4751 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, (u32aRGB >> 8),0x00FF); ///< G
4752 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, (u32aRGB << 8),0xFF00); ///< B
4753 }
Hal_SC_getVSyncWidth(void * pInstance,SCALER_WIN eWindow)4754 MS_U8 Hal_SC_getVSyncWidth(void *pInstance, SCALER_WIN eWindow)
4755 {
4756 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4757 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4758 MS_U8 u8val = 0;
4759
4760 if(eWindow == MAIN_WINDOW)
4761 {
4762 u8val = ((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK01_22_L) & 0xFF00) >> 8);
4763 }
4764 else
4765 {
4766 }
4767 return u8val;
4768 }
4769
Hal_SC_Set_OSDLayer(void * pInstance,E_VOP_OSD_LAYER_SEL eVOPOSDLayer,SCALER_WIN eWindow)4770 E_APIXC_ReturnValue Hal_SC_Set_OSDLayer(void *pInstance, E_VOP_OSD_LAYER_SEL eVOPOSDLayer, SCALER_WIN eWindow)
4771 {
4772 return E_APIXC_RET_FAIL;
4773 }
4774
Hal_SC_Get_OSDLayer(void * pInstance,SCALER_WIN eWindow)4775 E_VOP_OSD_LAYER_SEL Hal_SC_Get_OSDLayer(void *pInstance, SCALER_WIN eWindow)
4776 {
4777 //do nothing
4778 return E_VOP_LAYER_RESERVED;
4779 }
4780
Hal_SC_Set_VideoAlpha(void * pInstance,MS_U8 u8Val,SCALER_WIN eWindow)4781 E_APIXC_ReturnValue Hal_SC_Set_VideoAlpha(void *pInstance, MS_U8 u8Val, SCALER_WIN eWindow)
4782 {
4783 //do nothing
4784 return E_APIXC_RET_FAIL;
4785 }
4786
Hal_SC_Get_VideoAlpha(void * pInstance,MS_U8 * pu8Val,SCALER_WIN eWindow)4787 E_APIXC_ReturnValue Hal_SC_Get_VideoAlpha(void *pInstance, MS_U8 *pu8Val, SCALER_WIN eWindow)
4788 {
4789 *pu8Val += 0;
4790
4791 //do nothing
4792 return E_APIXC_RET_FAIL;
4793 }
4794
Hal_XC_ClearScalingFactorForInternalCalib(void * pInstance)4795 void Hal_XC_ClearScalingFactorForInternalCalib(void *pInstance)
4796 {
4797 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4798 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4799 //MDrv_WriteRegBit(H_BK_SCMI(0x09), FALSE, BIT(7));
4800 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_04_L, 0x0000); // H pre-scaling
4801 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_05_L, 0xC010); // H pre-scaling
4802 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_08_L, 0x0000); // V pre-scaling
4803 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK02_09_L, 0x0000); // V pre-scaling
4804
4805 //HVSP
4806 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_07_L, 0x0000); // H post-scaling
4807 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_08_L, 0x0100); // H post-scaling
4808 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_09_L, 0x0000); // V post-scaling
4809 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK23_0A_L, 0x0100); // V post-scaling
4810 }
4811
MHal_SC_cal_usedgain_to_reggain(MS_U32 u16UsedGain_x32)4812 MS_U8 MHal_SC_cal_usedgain_to_reggain(MS_U32 u16UsedGain_x32)
4813 {
4814 MS_U8 u8Value = 0;
4815
4816 if (u16UsedGain_x32 >=65536) u8Value = 16;
4817 else if (u16UsedGain_x32 >=32768) u8Value = 15;
4818 else if (u16UsedGain_x32 >=16384) u8Value = 14;
4819 else if (u16UsedGain_x32 >= 8192) u8Value = 13;
4820 else if (u16UsedGain_x32 >= 4096) u8Value = 12;
4821 else if (u16UsedGain_x32 >= 2048) u8Value = 11;
4822 else if (u16UsedGain_x32 >= 1024) u8Value = 10;
4823 else if (u16UsedGain_x32 >= 512) u8Value = 9;
4824 else if (u16UsedGain_x32 >= 256) u8Value = 8;
4825 else if (u16UsedGain_x32 >= 128) u8Value = 7;
4826 else if (u16UsedGain_x32 >= 64) u8Value = 6;
4827 else if (u16UsedGain_x32 >= 32) u8Value = 5;
4828 else if (u16UsedGain_x32 >= 16) u8Value = 4;
4829 else if (u16UsedGain_x32 >= 8) u8Value = 3;
4830 else if (u16UsedGain_x32 >= 4) u8Value = 2;
4831 else if (u16UsedGain_x32 >= 2) u8Value = 1;
4832 else if (u16UsedGain_x32 >= 1) u8Value = 0;
4833 else {
4834 u8Value = 0;
4835 }
4836
4837 u8Value += IPGAIN_REFACTOR;
4838
4839 return u8Value;
4840 }
4841
Hal_SC_OP2VOPDESel(void * pInstance,E_OP2VOP_DE_SEL eVopDESel)4842 E_APIXC_ReturnValue Hal_SC_OP2VOPDESel(void *pInstance, E_OP2VOP_DE_SEL eVopDESel)
4843 {
4844 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4845 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4846 //Select op2vop de, for DWIN capture etc
4847 if(eVopDESel == E_OP2VOPDE_WHOLEFRAME_WITHOSD)
4848 {
4849 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, ((MS_U16)(E_OP2VOPDE_WHOLEFRAME) << 12), (BIT(12)+BIT(13)));
4850 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(15), BIT(15));
4851 }
4852 else
4853 {
4854 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, 0, BIT(15));
4855 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6B_L, (eVopDESel << 12), (BIT(12)+BIT(13)));
4856 }
4857 return E_APIXC_RET_OK;
4858 }
4859
Hal_XC_SVOutput_GetCaps(void * pInstance)4860 MS_BOOL Hal_XC_SVOutput_GetCaps(void *pInstance)
4861 {
4862 return FALSE;
4863 }
4864
4865 /////Add for FRC
_MHal_SC_Flock_Caculate_LPLLSet(MS_U32 u32Dclk)4866 void _MHal_SC_Flock_Caculate_LPLLSet(MS_U32 u32Dclk)
4867 {
4868 MS_U64 ldPllSet = 0xff;
4869
4870 ldPllSet = ((MS_U64)320 * 524288 * 10000000 + (u32Dclk>>1)); // LPLL BK01 LPLL Set
4871 do_div(ldPllSet, u32Dclk);
4872
4873 LPLL_BK_STORE;
4874 LPLL_BK_SWITCH(0x01);
4875 W4BYTE(L_BK_LPLL(0x0F), (MS_U32)ldPllSet);
4876 LPLL_BK_RESTORE;
4877 }
4878
_MHal_SC_Set_LPLL_Limit(MS_U32 u32LpllLimitHigh,MS_U32 u32LpllLimitLow,MS_U8 u8Lpll_bank)4879 void _MHal_SC_Set_LPLL_Limit(MS_U32 u32LpllLimitHigh, MS_U32 u32LpllLimitLow, MS_U8 u8Lpll_bank)
4880 {
4881 //printf("Fpll_Limit: Set %lx, bound (%lx -> %lx)\n", *u32PllSet, u32UpBound, u32LowBound);
4882 LPLL_BK_STORE;
4883 LPLL_BK_SWITCH(u8Lpll_bank);
4884
4885
4886 MDrv_WriteByteMask(L_BK_LPLL(0x0D), BIT(4), BIT(4)); // turn on 2 limit
4887
4888 //printf("Fpll set %lx, limit (high %lx, low %lx)\n", *u32PllSet, u32LpllLimitHigh, u32LpllLimitLow);
4889 MDrv_Write3Byte(L_BK_LPLL(0x06), u32LpllLimitHigh);
4890 MDrv_Write3Byte(L_BK_LPLL(0x08), u32LpllLimitLow);
4891
4892 //printf("Fpll limit reg (high %lx, low %lx)\n", MDrv_Read4Byte(L_BK_LPLL(0x06)), MDrv_Read4Byte(L_BK_LPLL(0x08)));
4893
4894 LPLL_BK_RESTORE;
4895 }
4896 #define LVDS_FRC_CLOCK_MHZ 320
_MHal_SC_Flock_Set_IGainPGain(void * pInstance,MS_U8 u8FRC_Out,MS_U16 u16OutputVfreqAfterFRC,MS_U16 u16Htt,MS_U16 u16Vtt)4897 void _MHal_SC_Flock_Set_IGainPGain(void *pInstance, MS_U8 u8FRC_Out, MS_U16 u16OutputVfreqAfterFRC, MS_U16 u16Htt, MS_U16 u16Vtt)
4898 {
4899 MS_U32 u32dclk=0;
4900 MS_U8 u8GainI, u8GainP;
4901 MS_U64 u64Div_Factor;
4902 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
4903 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
4904 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
4905 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
4906
4907 //check parameter valid, avoiding the diving zero failure
4908 if(0 == u8FRC_Out)
4909 {
4910 u8FRC_Out = 1;
4911 }
4912
4913 u32dclk = (MS_U32)(u16Vtt * u16Htt * u8FRC_Out);
4914 //u64Div_Factor = (MS_U64)LVDS_FRC_CLOCK_MHZ*524288*1000000/pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock;
4915 u64Div_Factor = (MS_U64)LVDS_FRC_CLOCK_MHZ*524288*1000000;
4916 do_div(u64Div_Factor, pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock);
4917 do_div(u64Div_Factor, (MS_U32)u32dclk * 8);
4918
4919 u8GainI = MHal_SC_cal_usedgain_to_reggain(u64Div_Factor);
4920
4921 if((u8FRC_Out == 5)&&(u64Div_Factor==0))
4922 {
4923 //24 to 60Hz, because the SW can't get the real value by log table
4924 u8GainI = 1;
4925
4926 u8GainI += 2;
4927 }
4928
4929 u8GainP = u8GainI+1;
4930 if((u8FRC_Out >= 2) && (u8GainP == u8GainI))
4931 {
4932 u8GainP++;
4933 }
4934
4935 LPLL_BK_STORE;
4936 LPLL_BK_SWITCH(0x01);
4937 MDrv_WriteByte(H_BK_LPLL(0x0B), (u8GainP<<4)|u8GainI); //Gain
4938 LPLL_BK_RESTORE;
4939 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "i_Gain= 0x%x (%u)\n", (MS_U32)u64Div_Factor, (MS_U32)u64Div_Factor)
4940 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "REG_IGain= 0x%x (%u)\n", u8GainI, u8GainI)
4941 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "REG_PGain= 0x%x (%u)\n", u8GainP, u8GainP)
4942 }
4943
4944
_MHal_SC_Flock_Set_LPLL_Enable(E_XC_FLOCK_TYPE eFlock_type)4945 void _MHal_SC_Flock_Set_LPLL_Enable(E_XC_FLOCK_TYPE eFlock_type)
4946 {
4947 MS_BOOL bDiv_en = DISABLE;
4948
4949 switch(eFlock_type)
4950 {
4951 case E_XC_FLOCK_DIV_ON:
4952 bDiv_en = ENABLE;
4953 break;
4954
4955 case E_XC_FLOCK_FPLL_ON:
4956 case E_XC_FLOCK_DIV_OFF:
4957 default:
4958 break;
4959 }
4960
4961 LPLL_BK_STORE;
4962 LPLL_BK_SWITCH(0x01);
4963 MDrv_Write2ByteMask(L_BK_LPLL(0x7F), bDiv_en?BIT(8):0, BIT(8));
4964 LPLL_BK_RESTORE;
4965
4966 }
4967
MHal_CLKGEN_FRC_Init(MS_U8 u8LPLL_Mode)4968 void MHal_CLKGEN_FRC_Init(MS_U8 u8LPLL_Mode)
4969 {
4970 //Patch for MSTV_TOOL to R/W FRC base address
4971 MDrv_WriteByte(0x103C0E, 0x02);
4972
4973 #if 0 // Move into Panel driver
4974 // Enable CLK_DOT_MINI
4975 W2BYTEMSK(L_CLKGEN0(0x56), 0x0004, 0x000C); // FIFO_CLK
4976 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0002); // Not Invert
4977 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0001); // Enable clock
4978
4979 // Enable CLK_DOT_MINI_PRE
4980 W2BYTEMSK(L_CLKGEN0(0x56), 0x0400, 0x0C00); // FIFO_CLK
4981 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0200); // Not Invert
4982 W2BYTEMSK(L_CLKGEN0(0x56), 0x0000, 0x0100); // Enable clock
4983 #endif
4984
4985 // Enable CLK_R2_FRC
4986 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x000C); // 216 MHz
4987 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0002); // Not Invert
4988 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0101); // Enable clock
4989
4990 // Enable CLK_MCU_FRC
4991 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0C00); // 216 MHz
4992 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0200); // Not Invert
4993 W2BYTEMSK(L_CLKGEN1(0x30), 0x0000, 0x0100); // Enable clock
4994
4995 // Enable CLK_ODCLK_FRC
4996 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0C00); // CLK_LPLL
4997 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0200); // Not Invert
4998 W2BYTEMSK(L_CLKGEN1(0x31), 0x0000, 0x0100); // Enable clock
4999
5000 #if 0 // Move into panel driver
5001 // Enable CLK_TX_MOD_FRC
5002 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x000C); // clk_odclk_frc
5003 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0002); // Not Invert
5004 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0001); // Enable clock
5005
5006
5007 // Enable CLK_MINIFIFO_FRC
5008 if (u8LPLL_Mode== E_XC_MOD_OUTPUT_SINGLE ) //0: single, 1: dual
5009 {
5010 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0C00); // CLK_LPLL
5011 }
5012 else
5013 {
5014 W2BYTEMSK(L_CLKGEN1(0x32), 0x0800, 0x0C00); // CLK_LPLL_div2
5015 }
5016 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0200); // Not Invert
5017 W2BYTEMSK(L_CLKGEN1(0x32), 0x0000, 0x0100); // Enable clock
5018
5019
5020 // Enable CLK_MISC_FRC
5021 if (u8LPLL_Mode == E_XC_MOD_OUTPUT_SINGLE)
5022 {
5023 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0C00); // CLK_LPLL
5024 }
5025 else
5026 {
5027 W2BYTEMSK(L_CLKGEN1(0x33), 0x0400, 0x0C00); // CLK_LPLL_div2
5028 }
5029
5030 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0200); // Not Invert
5031 W2BYTEMSK(L_CLKGEN1(0x33), 0x0000, 0x0100); // Enable clock
5032
5033
5034
5035 // Enable CLK_MFT_FRC
5036 W2BYTEMSK(L_CLKGEN1(0x34), 0x0008, 0x000C); // CLK_LPLL_div2
5037 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0002); // Not Invert
5038 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0001); // Enable clock
5039 #endif
5040
5041 // Enable CLK_FDCLK_FRC
5042 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x1C00); // 172 MHz
5043 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0200); // Not Invert
5044 W2BYTEMSK(L_CLKGEN1(0x34), 0x0000, 0x0100); // Enable clock
5045
5046 // Enable CLK_ICLK_FRC
5047 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0004); // clk_fdclk_frc
5048 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0002); // Not Invert
5049 W2BYTEMSK(L_CLKGEN1(0x35), 0x0000, 0x0001); // Enable clock
5050
5051 // Enable CLK_OP2_SRAM_FRC
5052 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0004); // clk_odclk_frc_p
5053 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0002); // Not Invert
5054 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0001); // Enable clock
5055
5056 // Enable CLK_LD_SRAM_FRC
5057 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0400); // clk_odclk_frc_p
5058 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0200); // Not Invert
5059 W2BYTEMSK(L_CLKGEN1(0x36), 0x0000, 0x0100); // Enable clock
5060
5061 // Enable CLK_OD_SRAM_FRC
5062 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0004); // clk_odclk_frc_p
5063 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0002); // Not Invert
5064 W2BYTEMSK(L_CLKGEN1(0x37), 0x0000, 0x0001); // Enable clock
5065
5066 // Enable CLK_LPLL_FRC
5067 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x000C); // CLK_LPLL
5068 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0002); // Not Invert
5069 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0001); // Enable clock
5070
5071 // Enable CLK_OCC_FRC
5072 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0C00); // flock_clk_synth_out
5073 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0200); // Not Invert
5074 W2BYTEMSK(L_CLKGEN1(0x3A), 0x0000, 0x0100); // Enable clock
5075
5076 // Enable LVDS_MPLL
5077 //[10]reg_lvds_mpll_clk_adc432m_pd, [8]reg_lvds_mpll_pd
5078 //W2BYTEMSK(L_BK_AFEC(0x41), 0x0000, 0x0500); // MPLL_CLK_DP432M
5079 }
5080
MHal_CLKGEN_FRC_Bypass_Enable(MS_BOOL bEnable)5081 void MHal_CLKGEN_FRC_Bypass_Enable(MS_BOOL bEnable)
5082 {
5083
5084 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x02); // Not Invert
5085 W2BYTEMSK(L_CLKGEN0(0x53),0x00,0x01); // Enable clock
5086
5087 if (bEnable)
5088 {
5089 // Enable CLK_ODCLK
5090 W2BYTEMSK(L_CLKGEN0(0x53),0xC0C,0xC0C); // LPLL output clock
5091 // Disable CLK_R2_FRC
5092 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0xFFFF); // turn-on clk_mcu_frc
5093 // Enable CLK_SPI_M_FRC
5094 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Disable clock
5095 }
5096 else
5097 {
5098 // Enable CLK_ODCLK
5099 W2BYTEMSK(L_CLKGEN0(0x53), 0x00, 0xC0C); // synthetic clock out
5100 // Enable CLK_R2_FRC
5101 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x0C); // 216 MHz
5102 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x02); // Not Invert
5103 W2BYTEMSK(L_CLKGEN1(0x30), 0x00, 0x01); // Enable clock
5104 // Enable CLK_SPI_M_FRC
5105 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x1C); // 27 MHz
5106 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x02); // Not Invert
5107 W2BYTEMSK(L_CLKGEN1(0x31), 0x00, 0x01); // Enable clock
5108 }
5109 }
5110
5111
Hal_XC_IsForcePrescaling(void * pInstance,XC_InternalStatus * pSrcInfo,MS_BOOL * pbForceV,MS_BOOL * pbForceH,SCALER_WIN eWindow)5112 E_APIXC_ReturnValue Hal_XC_IsForcePrescaling(void *pInstance, XC_InternalStatus *pSrcInfo, MS_BOOL *pbForceV, MS_BOOL *pbForceH, SCALER_WIN eWindow)
5113 {
5114 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5115 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5116 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5117 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5118 *pbForceV = FALSE;
5119 *pbForceH = FALSE;
5120
5121 if(MDrv_XC_Is_SupportSWDS(pInstance)
5122 && (MDrv_XC_GetDynamicScalingStatus(pInstance) || MDrv_XC_Is_DSForceIndexEnabled(pInstance, eWindow))
5123 && (pSrcInfo->Status2.bPreVCusScaling || pSrcInfo->Status2.bPreHCusScaling))
5124 {
5125 if(pSrcInfo->Status2.u16PreHCusScalingDst > gSrcInfo[eWindow].Status2.u16XCVirtualBoxWidth)
5126 {
5127 *pbForceH = TRUE;
5128 pSrcInfo->Status2.u16PreHCusScalingDst = gSrcInfo[eWindow].Status2.u16XCVirtualBoxWidth;
5129 }
5130
5131 if(pSrcInfo->Status2.u16PreVCusScalingDst > gSrcInfo[eWindow].Status2.u16XCVirtualBoxHeight)
5132 {
5133 *pbForceV = TRUE;
5134 pSrcInfo->Status2.u16PreVCusScalingDst = gSrcInfo[eWindow].Status2.u16XCVirtualBoxHeight;
5135 }
5136 XC_LOG_TRACE(XC_DBGLEVEL_SETWINDOW,"Check force pre-scaling for limitation, even if customer pre-scaling has been set.\n");
5137 }
5138
5139 //-----------------------------------------
5140 // Vertical
5141 //-----------------------------------------
5142
5143 //FHD case. FHD has tight bandwidth in FCLK (post scaling), so force pre-scaling if disp.v size > 80% of crop.v size.
5144 if ( (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1000) &&
5145 (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width > 1600) ) //consider 1680x1050 into this case
5146 {
5147 // 80%
5148 if ( ( pSrcInfo->stDispWin.height * 10 ) < ( pSrcInfo->stCropWin.height * 8 ) )
5149 {
5150 *pbForceV = TRUE;
5151 }
5152 }
5153 else // SD, HD panel.
5154 {
5155 // 60%
5156 if ( ( pSrcInfo->stDispWin.height * 10 ) < ( pSrcInfo->stCropWin.height * 6 ) )
5157 {
5158 *pbForceV = TRUE;
5159 }
5160 }
5161
5162 //-----------------------------------------
5163 // Horizontal
5164 //-----------------------------------------
5165
5166 if ( (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1000)
5167 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width > 1600) ) //consider 1680x1050 into this case
5168 {
5169 // 80% ( SEC using 80% for HD panel ). Increase % if meet FCLK bandwidth issue in the future.
5170 if ( ( pSrcInfo->stDispWin.width * 10 ) < ( pSrcInfo->stCropWin.width * 8 ) )
5171 {
5172 *pbForceH = TRUE;
5173 }
5174 }
5175 else // SD panel.
5176 {
5177 // 60%
5178 if ( ( pSrcInfo->stDispWin.width * 10 ) < ( pSrcInfo->stCropWin.width * 6 ) )
5179 {
5180 *pbForceH = TRUE;
5181 }
5182 }
5183
5184 return E_APIXC_RET_OK;
5185 }
5186
Hal_SC_IsHW2Dto3DPatch_Enable(void)5187 MS_BOOL Hal_SC_IsHW2Dto3DPatch_Enable(void)
5188 {
5189 MS_BOOL bRet = FALSE;
5190 if(PM_R1BYTE(REG_CHIP_REVISION, 7:0) < 1)//a1 u01 2d to 3d hw bug
5191 {
5192 bRet = TRUE;
5193 }
5194 return bRet;
5195 }
5196
MHal_SC_Get_LpllSet_Factor(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)5197 MS_U32 MHal_SC_Get_LpllSet_Factor(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)
5198 {
5199 MS_U32 u32Factor = 0;
5200 UNUSED(u8LPLL_Type);
5201 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5202 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5203 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5204 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5205
5206 u32Factor = LPLL_LOOPGAIN/8/2;
5207
5208 if ((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16HTotal> 3000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16VTotal > 2000) && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16DefaultVFreq > 500))
5209 {
5210 //printf("\033[0;31m [%s][%d] enter For 4K2K used!!! \033[0m\n", __FUNCTION__, __LINE__);
5211 u32Factor = 1;
5212 }
5213
5214 if (u8LPLL_Type == E_XC_PNL_LPLL_LVDS)
5215 {
5216 u32Factor = 3;
5217 }
5218
5219 // for the WUXGA 1920x1200 case
5220 if((u8LPLL_Mode==E_XC_MOD_OUTPUT_DUAL)&&(u32DefaultDClk > 1500000000)
5221 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 1100)
5222 &&(pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width < 2000))
5223 {
5224 u32Factor = LPLL_LOOPGAIN/8;
5225 }
5226
5227 if((u8LPLL_Type >= E_XC_PNL_LPLL_VBY1_10BIT_4LANE)&&(u8LPLL_Type <= E_XC_PNL_LPLL_VBY1_8BIT_8LANE))
5228 {
5229 u32Factor = 8;
5230 }
5231
5232 return u32Factor;
5233 }
5234
MHal_SC_Get_LpllSet_Div(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)5235 MS_U32 MHal_SC_Get_LpllSet_Div(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type,MS_U32 u32DefaultDClk)
5236 {
5237 MS_U32 u32Div = 1;
5238
5239 if (u8LPLL_Type == E_XC_PNL_LPLL_LVDS)
5240 {
5241 u32Div = 2;
5242 }
5243
5244 if((u8LPLL_Type >= E_XC_PNL_LPLL_VBY1_10BIT_4LANE)&&(u8LPLL_Type <= E_XC_PNL_LPLL_VBY1_8BIT_8LANE))
5245 {
5246 u32Div = 5;
5247 }
5248
5249 return u32Div;
5250 }
5251
Hal_SC_Enable_AVMute(void * pInstance,SCALER_WIN eWindow)5252 E_APIXC_ReturnValue Hal_SC_Enable_AVMute(void *pInstance, SCALER_WIN eWindow)
5253 {
5254 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5255 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5256 if (eWindow == MAIN_WINDOW)
5257 {
5258 //HDMI V-mute detect enable
5259 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_34_L, BIT(9), BIT(9));
5260 //force IPM enable at av-mute case
5261 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_19_L, BIT(5), BIT(5));
5262 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_19_L, BIT(5), BIT(5));
5263
5264 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, BIT(13) | BIT(15), BIT(13) | BIT(15));
5265 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(9) | BIT(11), BIT(9) | BIT(11));
5266 }
5267 else
5268 {
5269 //HDMI V-mute detect enable
5270 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK03_34_L, BIT(9), BIT(9));
5271 //force IPM enable at av-mute case
5272 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_59_L, BIT(5), BIT(5));
5273 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_59_L, BIT(5), BIT(5));
5274
5275 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_01_L, BIT(12) | BIT(14), BIT(12) | BIT(14));
5276 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_23_L, BIT(8) | BIT(10), BIT(8) | BIT(10));
5277 }
5278
5279 return E_APIXC_RET_OK;
5280 }
5281
Hal_XC_ReportPixelInfo(void * pInstance,MS_XC_REPORT_PIXELINFO * pstRepPixInfo)5282 MS_BOOL Hal_XC_ReportPixelInfo(void *pInstance, MS_XC_REPORT_PIXELINFO *pstRepPixInfo)
5283 {
5284 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5285 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5286 MS_BOOL bret = TRUE;
5287
5288 switch(pstRepPixInfo->enStage)
5289 {
5290 case E_XC_GET_PIXEL_STAGE_AFTER_DLC:
5291 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x00 , BMASK(3:0));
5292 break;
5293 case E_XC_GET_PIXEL_STAGE_PRE_GAMMA:
5294 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x08, BMASK(3:0));
5295 break;
5296 case E_XC_GET_PIXEL_STAGE_AFTER_OSD:
5297 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, 0x0C, BMASK(3:0));
5298 break;
5299 default:
5300 bret = FALSE;
5301 break;
5302 }
5303
5304 if(bret)
5305 {
5306 // Enable
5307 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(8), BIT(8));
5308
5309 if(pstRepPixInfo->bShowRepWin)
5310 {
5311 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, BIT(9), BIT(9));
5312 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_46_L, pstRepPixInfo->u16RepWinColor<<8, 0xFF00);
5313 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, BIT(0), BIT(0));
5314 }
5315
5316 // Set Report Window
5317 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_42_L, pstRepPixInfo->u16XStart);
5318 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_43_L, pstRepPixInfo->u16XEnd);
5319 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_44_L, pstRepPixInfo->u16YStart);
5320 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_45_L, pstRepPixInfo->u16YEnd);
5321
5322 MsOS_DelayTask(50); // Must wait .
5323
5324 pstRepPixInfo->u16RCrMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_64_L);
5325 pstRepPixInfo->u16RCrMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_65_L);
5326 pstRepPixInfo->u16GYMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_66_L);
5327 pstRepPixInfo->u16GYMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_67_L);
5328 pstRepPixInfo->u16BCbMin = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_68_L);
5329 pstRepPixInfo->u16BCbMax = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK0F_69_L);
5330 pstRepPixInfo->u32RCrSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_01_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_02_L)<<16);
5331 pstRepPixInfo->u32GYSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_03_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_04_L)<<16);
5332 pstRepPixInfo->u32BCbSum = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_05_L)|(SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK2D_06_L)<<16);
5333
5334 if(pstRepPixInfo->bShowRepWin)
5335 {
5336 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_1A_L, 0x00, BIT(0));
5337 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00, BIT(9));
5338 }
5339 // Disable
5340 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0F_57_L, 0x00, BIT(8));
5341 }
5342
5343 return bret;
5344 }
5345
Hal_SC_set_mrq_miusel(void * pInstance,MS_U8 u8MIUSel)5346 void Hal_SC_set_mrq_miusel(void *pInstance, MS_U8 u8MIUSel)
5347 {
5348 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5349 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5350
5351 // Scaler control MRQ MIU by itself
5352 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
5353 if (u8MIUSel==0)
5354 {
5355 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, 0, BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU0
5356 }
5357 else if (u8MIUSel==1)
5358 {
5359 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, BIT(8), BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU1
5360 }
5361 else if (u8MIUSel==2)
5362 {
5363 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_07_L, BIT(9), BIT(8)|BIT(9)); // reg_mrq_miu_sel to MIU2
5364 }
5365
5366 MDrv_WriteByteMask(REG_MIU0_BASE + 0xF3, 0x00, 0x80); // MIU select (Group1 BIT15)
5367 MDrv_WriteByteMask(REG_MIU1_BASE + 0xF3, 0x80, 0x80); // IP select
5368 }
5369
Hal_SC_set_mcdi_memoryaddress(void * pInstance,MS_PHY u32FBAddress,E_XC_MCDI_TYPE eType)5370 void Hal_SC_set_mcdi_memoryaddress(void *pInstance, MS_PHY u32FBAddress, E_XC_MCDI_TYPE eType)
5371 {
5372 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5373 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5374
5375 if (eType == E_XC_MCDI_BOTH) // MAIN
5376 {
5377 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0A_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME1 address
5378 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_12_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME2 address
5379 }
5380 else if(eType == E_XC_MCDI_SUB_BOTH) // SUB
5381 {
5382 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_28_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME1 address
5383 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2C_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME2 address
5384 }
5385 else if(eType == E_XC_MCDI_ME1)
5386 {
5387 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0A_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME1 address
5388 }
5389 else if (eType == E_XC_MCDI_ME2)
5390 {
5391 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_12_L, u32FBAddress / MCDI_BYTE_PER_WORD); // MAIN ME2 address
5392 }
5393 else if (eType == E_XC_MCDI_SUB_ME1)
5394 {
5395 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_28_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME1 address
5396 }
5397 else if (eType == E_XC_MCDI_SUB_ME2)
5398 {
5399 SC_W4BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2C_L, u32FBAddress / MCDI_BYTE_PER_WORD); // SUB ME2 address
5400 }
5401 }
5402
Hal_SC_set_mcdi_write_limit(void * pInstance,MS_BOOL bEn,MS_PHY u32LimitAddress,E_XC_MCDI_TYPE eType)5403 void Hal_SC_set_mcdi_write_limit(void *pInstance, MS_BOOL bEn, MS_PHY u32LimitAddress, E_XC_MCDI_TYPE eType)
5404 {
5405 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5406 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5407
5408 u32LimitAddress = u32LimitAddress / MCDI_BYTE_PER_WORD -1;
5409
5410 if(eType == E_XC_MCDI_BOTH)
5411 {
5412 // Main/Sub shares the same enable bit of ME1
5413 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
5414 // Bit 0 ~ 26
5415 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0C_L, u32LimitAddress & 0xFFFF);
5416 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0D_L, (u32LimitAddress >> 16) & 0x3FF);
5417
5418 // Main/Sub shares the same enable bit of ME2
5419 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
5420 // Bit 0 ~ 26
5421 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_14_L, u32LimitAddress & 0xFFFF);
5422 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_15_L, (u32LimitAddress >> 16) & 0x3FF);
5423 }
5424 else if(eType==E_XC_MCDI_SUB_BOTH)
5425 {
5426 // Main/Sub shares the same enable bit of ME1
5427 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
5428 // Bit 0 ~ 26
5429 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2A_L, u32LimitAddress & 0xFFFF);
5430 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2B_L, (u32LimitAddress >> 16) & 0x3FF);
5431
5432 // Main/Sub shares the same enable bit of ME2
5433 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
5434 // Bit 0 ~ 26
5435 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2E_L, u32LimitAddress & 0xFFFF);
5436 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2F_L, (u32LimitAddress >> 16) & 0x3FF);
5437 }
5438 else if(eType == E_XC_MCDI_ME1)
5439 {
5440 // Main/Sub shares the same enable bit
5441 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
5442 // Bit 0 ~ 26
5443 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0C_L, u32LimitAddress & 0xFFFF);
5444 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_0D_L, (u32LimitAddress >> 16) & 0x3FF);
5445 }
5446 else if (eType == E_XC_MCDI_ME2)
5447 {
5448 // Main/Sub shares the same enable bit
5449 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
5450 // Bit 0 ~ 26
5451 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_14_L, u32LimitAddress & 0xFFFF);
5452 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_15_L, (u32LimitAddress >> 16) & 0x3FF);
5453 }
5454 else if (eType == E_XC_MCDI_SUB_ME1)
5455 {
5456 // Main/Sub shares the same enable bit
5457 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_08_L, bEn ? BIT(0) : 0, BIT(0));
5458 // Bit 0 ~ 26
5459 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2A_L, u32LimitAddress & 0xFFFF);
5460 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2B_L, (u32LimitAddress >> 16) & 0x3FF);
5461 }
5462 else if (eType == E_XC_MCDI_SUB_ME2)
5463 {
5464 // Main/Sub shares the same enable bit
5465 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_10_L, bEn ? BIT(0) : 0, BIT(0));
5466 // Bit 0 ~ 26
5467 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2E_L, u32LimitAddress & 0xFFFF);
5468 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_2F_L, (u32LimitAddress >> 16) & 0x3FF);
5469 }
5470 }
Hal_SC_enable_mcdi(void * pInstance,MS_BOOL bEn,E_XC_MCDI_TYPE eType)5471 void Hal_SC_enable_mcdi(void *pInstance, MS_BOOL bEn, E_XC_MCDI_TYPE eType)
5472 {
5473 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5474 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5475
5476 #define ME1_CTRL_BIT ( BIT(1) )
5477 #define ME2_CTRL_BIT ( BIT(2) )
5478 MS_U16 u16Value = 0;
5479 MS_U16 u16Mask = 0;
5480 switch (eType)
5481 {
5482 case E_XC_MCDI_ME1:
5483 u16Value = u16Value | (bEn ? 0 : ME1_CTRL_BIT);
5484 u16Mask = ME1_CTRL_BIT;
5485 break;
5486 case E_XC_MCDI_ME2:
5487 u16Value = u16Value | (bEn ? 0 : ME2_CTRL_BIT);
5488 u16Mask = ME2_CTRL_BIT;
5489 break;
5490 case E_XC_MCDI_BOTH:
5491 u16Value = u16Value | (bEn ? 0 : ME1_CTRL_BIT);
5492 u16Value = u16Value | (bEn ? 0 : ME2_CTRL_BIT);
5493 u16Mask = ME1_CTRL_BIT | ME2_CTRL_BIT;
5494 break;
5495 case E_XC_MCDI_SUB_ME1:
5496 u16Value = u16Value | ((bEn ? 0 : ME1_CTRL_BIT)<<3);
5497 u16Mask = ME1_CTRL_BIT << 3;
5498 break;
5499 case E_XC_MCDI_SUB_ME2:
5500 u16Value = u16Value | ((bEn ? 0 : ME2_CTRL_BIT)<<3);
5501 u16Mask = ME2_CTRL_BIT << 3;
5502 break;
5503 case E_XC_MCDI_SUB_BOTH:
5504 u16Value = u16Value | ((bEn ? 0 : ME1_CTRL_BIT)<<3);
5505 u16Value = u16Value | ((bEn ? 0 : ME2_CTRL_BIT)<<3);
5506 u16Mask = (ME1_CTRL_BIT | ME2_CTRL_BIT)<<3;
5507 break;
5508 default:
5509 u16Value = 0;
5510 break;
5511 }
5512 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L, u16Value, u16Mask);
5513 if (bEn)
5514 {
5515 // Turn on MIU access arbitor
5516 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_04_L, 0x00 , BIT(6) );
5517 }
5518 else
5519 {
5520 MS_U16 u16MCDiCtrl_Main = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L) & ( ME1_CTRL_BIT | ME2_CTRL_BIT ) ;
5521 MS_U16 u16MCDiCtrl_Sub = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK17_07_L) & (( ME1_CTRL_BIT | ME2_CTRL_BIT )<<3) ;
5522 MS_U16 u16MCDiCtrl = u16MCDiCtrl_Main | u16MCDiCtrl_Sub;
5523 // Current ME1/2 is turned off
5524 if ( u16MCDiCtrl == ( ( ME1_CTRL_BIT | ME2_CTRL_BIT) // Main_Window
5525 | ((ME1_CTRL_BIT | ME2_CTRL_BIT)<<3))) // Sub_Window
5526 {
5527 // Turn off arbitor only when all MCDi function is off.
5528 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_04_L, BIT(6) , BIT(6) );
5529 }
5530 }
5531 }
5532
5533 /// bandwidth saving Mode
Hal_SC_set_bws_mode(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)5534 void Hal_SC_set_bws_mode(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
5535 {
5536 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5537 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5538
5539 if(eWindow == MAIN_WINDOW)
5540 {
5541 //ipm Main
5542 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, (bEnable? 0x00:BIT(0)), BIT(0));
5543 }
5544 else
5545 {
5546 //ipm Sub
5547 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_01_L, (bEnable? 0x00:BIT(1)), BIT(1));
5548 }
5549 }
5550
Hal_SC_sw_lcnt_en(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)5551 void Hal_SC_sw_lcnt_en(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
5552 {
5553 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5554 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5555
5556 if(eWindow == MAIN_WINDOW)
5557 {
5558 //ipm Main
5559 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_11_L, (bEnable? BIT(0):0x00), BIT(0));
5560 }
5561 else
5562 {
5563 //ipm Sub
5564 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_21_L, (bEnable? BIT(0):0x00), BIT(0));
5565 }
5566 }
5567
Hal_SC_set_sw_lcnt(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)5568 void Hal_SC_set_sw_lcnt(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
5569 {
5570 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5571 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5572
5573 if(eWindow == MAIN_WINDOW)
5574 {
5575 //ipm Main
5576 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_11_L, (bEnable? BIT(1):0x00), BIT(1));
5577 }
5578 else
5579 {
5580 //ipm Sub
5581 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_21_L, (bEnable? BIT(1):0x00), BIT(1));
5582 }
5583 }
5584
Hal_SC_set_ipmw_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)5585 void Hal_SC_set_ipmw_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
5586 {
5587 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5588 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5589
5590 if(eWindow == MAIN_WINDOW)
5591 {
5592 //ipm Main
5593 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_12_L, (bEnable? BIT(4):0x00), BIT(4));
5594 }
5595 else
5596 {
5597 //ipm Sub
5598 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_22_L, (bEnable? BIT(4):0x00), BIT(4));
5599 }
5600 }
5601
Hal_SC_set_ipmr_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)5602 void Hal_SC_set_ipmr_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
5603 {
5604 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5605 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5606
5607 if(eWindow == MAIN_WINDOW)
5608 {
5609 //ipm Main
5610 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_12_L, (bEnable? BIT(12):0x00), BIT(12));
5611 }
5612 else
5613 {
5614 //ipm Sub
5615 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_22_L, (bEnable? BIT(12):0x00), BIT(12));
5616 }
5617 }
5618
Hal_SC_set_opm_lcnt_inv(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)5619 void Hal_SC_set_opm_lcnt_inv(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
5620 {
5621 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5622 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5623 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5624 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5625
5626 if(eWindow == MAIN_WINDOW)
5627 {
5628 //opm Main
5629 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, (bEnable? BIT(5):0x00), BIT(5));
5630 }
5631 else
5632 {
5633 //opm Sub
5634 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK08_32_L, (bEnable? BIT(4):0x00), BIT(4));
5635 }
5636
5637 }
5638
MHal_XC_Calc_IGainPGain(void * pInstance,MS_U8 * u8GainI,MS_U8 * u8GainP,MS_U32 u32XTAL_Clock,MS_U8 u8LGain,MS_U8 u8Vco,MS_U16 u16HTotal,MS_U16 u16VTotal,MS_U8 u8FRC_Out)5639 void MHal_XC_Calc_IGainPGain(void *pInstance, MS_U8 *u8GainI, MS_U8 *u8GainP, MS_U32 u32XTAL_Clock, MS_U8 u8LGain, MS_U8 u8Vco, MS_U16 u16HTotal, MS_U16 u16VTotal, MS_U8 u8FRC_Out)
5640 {
5641 MS_U32 u32Factor, u32Temp;
5642 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5643 UtopiaResourceGetPrivate(g_pXCResource[E_XC_POOL_ID_INTERNAL_VARIABLE],(void**)(&pXCResourcePrivate));
5644 u32Temp = (MS_U32)(u16VTotal*u16HTotal*u8FRC_Out);
5645 u32XTAL_Clock*=2;
5646 u32Factor = ((LVDS_MPLL_CLOCK_MHZ*1000000UL/u32XTAL_Clock)*524288*u8LGain)/((MS_U32)(u32Temp*u8Vco/2*8));
5647
5648 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "MM=%ld,u8LGain1=%d,Htt=%d,Vtt=%d,Ovs=%d,Vco=%d,i_gain=%d,REGIg=%d,u32XTAL_Clock=%u\n",
5649 (LVDS_MPLL_CLOCK_MHZ*1000000UL/pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.u32XTAL_Clock),u8LGain,
5650 u16HTotal,u16VTotal,u8FRC_Out,u8Vco/2,u32Factor,MHal_SC_cal_usedgain_to_reggain(u32Factor),u32XTAL_Clock);
5651
5652 *u8GainI = MHal_SC_cal_usedgain_to_reggain(u32Factor);
5653 /// for high accurate log value
5654 u32Factor = ((LVDS_MPLL_CLOCK_MHZ*1000000UL/u32XTAL_Clock)*524288*u8LGain*10)/((MS_U32)(u32Temp*u8Vco/2*8));
5655
5656 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "new i_gain=%d\n", u32Factor);
5657
5658 if(u32Factor <= 1)
5659 *u8GainI=2;
5660 else if(u32Factor <= 3)
5661 *u8GainI=3;
5662 else if(u32Factor <= 7)
5663 *u8GainI=4;
5664
5665 *u8GainP = *u8GainI+1;
5666
5667 XC_LOG_TRACE(XC_DBGLEVEL_SETTIMING, "==>LG1=%d,iGain=%d,I=%d,P=%d\n",u8LGain,u32Factor,*u8GainI,*u8GainP);
5668 }
5669
MHAL_SC_set_osdc_tgen_hsync_start(void * pInstance,MS_U16 u16Value)5670 void MHAL_SC_set_osdc_tgen_hsync_start(void *pInstance, MS_U16 u16Value)
5671 {
5672 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5673 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5674
5675 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_01_L, u16Value, 0x1FFF);
5676 }
5677
MHAL_SC_set_osdc_tgen_hsync_end(void * pInstance,MS_U16 u16Value)5678 void MHAL_SC_set_osdc_tgen_hsync_end(void *pInstance, MS_U16 u16Value)
5679 {
5680 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5681 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5682
5683 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_02_L, u16Value, 0x1FFF);
5684 }
5685
MHAL_SC_set_osdc_tgen_hframe_de_start(void * pInstance,MS_U16 u16Value)5686 void MHAL_SC_set_osdc_tgen_hframe_de_start(void *pInstance, MS_U16 u16Value)
5687 {
5688 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5689 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5690
5691 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_03_L, u16Value, 0x1FFF);
5692 }
5693
MHAL_SC_set_osdc_tgen_hframe_de_end(void * pInstance,MS_U16 u16Value)5694 void MHAL_SC_set_osdc_tgen_hframe_de_end(void *pInstance, MS_U16 u16Value)
5695 {
5696 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5697 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5698
5699 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_04_L, u16Value, 0x1FFF);
5700 }
5701
MHAL_SC_set_osdc_tgen_htotal(void * pInstance,MS_U16 u16Value)5702 void MHAL_SC_set_osdc_tgen_htotal(void *pInstance, MS_U16 u16Value)
5703 {
5704 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5705 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5706
5707 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_05_L, u16Value, 0x1FFF);
5708 }
5709
MHAL_SC_set_osdc_tgen_vtotal(void * pInstance,MS_U16 u16Value)5710 void MHAL_SC_set_osdc_tgen_vtotal(void *pInstance, MS_U16 u16Value)
5711 {
5712 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5713 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5714
5715 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_07_L, u16Value, 0x1FFF);
5716 }
5717
MHAL_SC_set_osdc_tgen_vframe_de_start(void * pInstance,MS_U16 u16Value)5718 void MHAL_SC_set_osdc_tgen_vframe_de_start(void *pInstance, MS_U16 u16Value)
5719 {
5720 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5721 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5722
5723 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0A_L, u16Value, 0x1FFF);
5724 }
5725
MHAL_SC_set_osdc_tgen_vframe_de_end(void * pInstance,MS_U16 u16Value)5726 void MHAL_SC_set_osdc_tgen_vframe_de_end(void *pInstance, MS_U16 u16Value)
5727 {
5728 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5729 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5730
5731 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0B_L, u16Value, 0x1FFF);
5732 }
5733
MHAL_SC_set_osdc_tgen_vsync_start(void * pInstance,MS_U16 u16Value)5734 void MHAL_SC_set_osdc_tgen_vsync_start(void *pInstance, MS_U16 u16Value)
5735 {
5736 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5737 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5738
5739 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0E_L, u16Value, 0x1FFF);
5740 }
5741
MHAL_SC_set_osdc_tgen_vsync_end(void * pInstance,MS_U16 u16Value)5742 void MHAL_SC_set_osdc_tgen_vsync_end(void *pInstance, MS_U16 u16Value)
5743 {
5744 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5745 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5746
5747 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0F_L, u16Value, 0x1FFF);
5748 }
5749
MHAL_SC_set_osdc_tgen_reset_enable(void * pInstance,MS_BOOL bEnable)5750 void MHAL_SC_set_osdc_tgen_reset_enable(void *pInstance, MS_BOOL bEnable)
5751 {
5752 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5753 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5754
5755 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_20_L, bEnable?BIT(0):0x00, BIT(0));
5756 }
5757
MHAL_SC_set_osdc_swreset_enable(void * pInstance,MS_BOOL bEnable)5758 void MHAL_SC_set_osdc_swreset_enable(void *pInstance, MS_BOOL bEnable)
5759 {
5760 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5761 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5762
5763 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_21_L, bEnable?BIT(0):0x00, BIT(0));
5764 }
5765
MHAL_SC_set_osdc_mixer_bypass_enable(void * pInstance,MS_BOOL bEnable)5766 void MHAL_SC_set_osdc_mixer_bypass_enable(void *pInstance, MS_BOOL bEnable)
5767 {
5768 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5769 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5770
5771 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(0):0x00, BIT(0));
5772 }
5773
MHAL_SC_set_osdc_mixer_inv_alpha_enable(void * pInstance,MS_BOOL bEnable)5774 void MHAL_SC_set_osdc_mixer_inv_alpha_enable(void *pInstance, MS_BOOL bEnable)
5775 {
5776 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5777 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5778
5779 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(1):0x00, BIT(1));
5780 }
5781 //1:hs_out = hs&vfde
MHAL_SC_set_osdc_mixer_hs_n_vfde_enable(void * pInstance,MS_BOOL bEnable)5782 void MHAL_SC_set_osdc_mixer_hs_n_vfde_enable(void *pInstance, MS_BOOL bEnable)
5783 {
5784 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5785 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5786
5787 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(2):0x00, BIT(2));
5788 }
5789 //1:de(hfde)_out = de(hfde)&vfde
MHAL_SC_set_osdc_mixer_hfde_n_vfde_enable(void * pInstance,MS_BOOL bEnable)5790 void MHAL_SC_set_osdc_mixer_hfde_n_vfde_enable(void *pInstance, MS_BOOL bEnable)
5791 {
5792 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5793 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5794
5795 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, bEnable?BIT(3):0x00, BIT(3));
5796 }
5797
MHAL_SC_set_osdc_clk_mux(void * pInstance,MS_U8 u8Clk_Mux)5798 void MHAL_SC_set_osdc_clk_mux(void *pInstance, MS_U8 u8Clk_Mux)
5799 {
5800 MDrv_WriteByteMask(REG_CKG_OSDC, u8Clk_Mux << 2, CKG_OSDC_MASK);
5801 }
5802
MHAL_SC_enable_osdc(void * pInstance,MS_BOOL bEnable)5803 void MHAL_SC_enable_osdc(void *pInstance, MS_BOOL bEnable)
5804 {
5805 // Enable OSDC LPLL
5806 if(bEnable)
5807 {
5808 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_INVERT); // Not Invert
5809 MDrv_WriteRegBit(REG_CKG_OSDC, DISABLE, CKG_OSDC_GATED); // Enable clock
5810 }
5811 else
5812 {
5813 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_INVERT); // Not Invert
5814 MDrv_WriteRegBit(REG_CKG_OSDC, ENABLE, CKG_OSDC_GATED); // Enable clock
5815 }
5816 }
5817
MHAL_SC_get_osdc_tgen_hsync_start(void * pInstance)5818 MS_U16 MHAL_SC_get_osdc_tgen_hsync_start(void *pInstance)
5819 {
5820 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5821 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5822
5823 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_01_L, 0x1FFF);
5824 }
5825
MHAL_SC_get_osdc_tgen_hsync_end(void * pInstance)5826 MS_U16 MHAL_SC_get_osdc_tgen_hsync_end(void *pInstance)
5827 {
5828 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5829 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5830
5831 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_02_L, 0x1FFF);
5832 }
5833
MHAL_SC_get_osdc_tgen_hframe_de_start(void * pInstance)5834 MS_U16 MHAL_SC_get_osdc_tgen_hframe_de_start(void *pInstance)
5835 {
5836 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5837 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5838
5839 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_03_L, 0x1FFF);
5840 }
5841
MHAL_SC_get_osdc_tgen_hframe_de_end(void * pInstance)5842 MS_U16 MHAL_SC_get_osdc_tgen_hframe_de_end(void *pInstance)
5843 {
5844 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5845 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5846
5847 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_04_L, 0x1FFF);
5848 }
5849
MHAL_SC_get_osdc_tgen_htotal(void * pInstance)5850 MS_U16 MHAL_SC_get_osdc_tgen_htotal(void *pInstance)
5851 {
5852 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5853 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5854
5855 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_05_L, 0x1FFF);
5856 }
5857
MHAL_SC_get_osdc_tgen_vtotal(void * pInstance)5858 MS_U16 MHAL_SC_get_osdc_tgen_vtotal(void *pInstance)
5859 {
5860 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5861 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5862
5863 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_07_L, 0x1FFF);
5864 }
5865
MHAL_SC_get_osdc_tgen_vframe_de_start(void * pInstance)5866 MS_U16 MHAL_SC_get_osdc_tgen_vframe_de_start(void *pInstance)
5867 {
5868 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5869 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5870
5871 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0A_L, 0x1FFF);
5872 }
5873
MHAL_SC_get_osdc_tgen_vframe_de_end(void * pInstance)5874 MS_U16 MHAL_SC_get_osdc_tgen_vframe_de_end(void *pInstance)
5875 {
5876 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5877 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5878
5879 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0B_L, 0x1FFF);
5880 }
5881
MHAL_SC_get_osdc_tgen_vsync_start(void * pInstance)5882 MS_U16 MHAL_SC_get_osdc_tgen_vsync_start(void *pInstance)
5883 {
5884 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5885 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5886
5887 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0E_L, 0x1FFF);
5888 }
5889
MHAL_SC_get_osdc_tgen_vsync_end(void * pInstance)5890 MS_U16 MHAL_SC_get_osdc_tgen_vsync_end(void *pInstance)
5891 {
5892 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5893 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5894
5895 return (MS_U16)SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_0F_L, 0x1FFF);
5896 }
5897
MHAL_SC_get_osdc_mixer_bypass_status(void * pInstance)5898 MS_BOOL MHAL_SC_get_osdc_mixer_bypass_status(void *pInstance)
5899 {
5900 MS_BOOL bEnable = DISABLE;
5901 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5902 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5903
5904 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(0)));
5905 return bEnable;
5906 }
5907
MHAL_SC_get_osdc_mixer_inv_alpha_status(void * pInstance)5908 MS_BOOL MHAL_SC_get_osdc_mixer_inv_alpha_status(void *pInstance)
5909 {
5910 MS_BOOL bEnable = DISABLE;
5911 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5912 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5913
5914 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(1))>>1);
5915 return bEnable;
5916 }
5917 //1:hs_out = hs&vfde
MHAL_SC_get_osdc_mixer_hs_n_vfde_status(void * pInstance)5918 MS_BOOL MHAL_SC_get_osdc_mixer_hs_n_vfde_status(void *pInstance)
5919 {
5920 MS_BOOL bEnable = DISABLE;
5921 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5922 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5923
5924 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(2))>>2);
5925 return bEnable;
5926 }
5927 //1:de(hfde)_out = de(hfde)&vfde
MHAL_SC_get_osdc_mixer_hfde_n_vfde_status(void * pInstance)5928 MS_BOOL MHAL_SC_get_osdc_mixer_hfde_n_vfde_status(void *pInstance)
5929 {
5930 MS_BOOL bEnable = DISABLE;
5931 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5932 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5933
5934 bEnable = (MS_BOOL)(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK37_22_L, BIT(3))>>3);
5935 return bEnable;
5936 }
5937
MHAL_SC_get_osdc_onoff_status(void * pInstance)5938 MS_BOOL MHAL_SC_get_osdc_onoff_status(void *pInstance)
5939 {
5940 // Enable OSDC LPLL
5941 MS_BOOL bEnable = DISABLE;
5942 bEnable = (MS_BOOL)(MDrv_ReadRegBit(REG_CKG_OSDC, CKG_OSDC_GATED));
5943 return bEnable;
5944 }
5945
MHal_XC_SetForceReadBank(void * pInstance,MS_BOOL bEnable,MS_U8 u8Bank,SCALER_WIN eWindow)5946 void MHal_XC_SetForceReadBank(void *pInstance, MS_BOOL bEnable, MS_U8 u8Bank, SCALER_WIN eWindow)
5947 {
5948 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5949 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5950 if (eWindow == MAIN_WINDOW)
5951 {
5952 if (bEnable)
5953 {
5954 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, BIT(11), BIT(11));
5955 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, (u8Bank & 0x7) << 8, BIT(10)|BIT(9)|BIT(8));
5956 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_06_L, ((u8Bank & 0x8) >> 3) << 14, BIT(14));
5957 }
5958 else
5959 {
5960 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0, BIT(11));
5961 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0, BIT(10)|BIT(9)|BIT(8));
5962 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_06_L, 0, BIT(14));
5963 }
5964 }
5965 else
5966 {
5967 if (bEnable)
5968 {
5969 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, BIT(11), BIT(11));
5970 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, (u8Bank & 0x7) << 8, BIT(10)|BIT(9)|BIT(8));
5971 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_46_L, ((u8Bank & 0x8) >> 3) << 14, BIT(14));
5972 }
5973 else
5974 {
5975 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0, BIT(11));
5976 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_47_L, 0, BIT(10)|BIT(9)|BIT(8));
5977 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_46_L, 0, BIT(14));
5978 }
5979 }
5980 }
5981
MHal_XC_SetDNRBufAddress(void * pInstance,MS_PHY u32DNRBaseAddr,SCALER_WIN eWindow)5982 MS_BOOL MHal_XC_SetDNRBufAddress(void *pInstance, MS_PHY u32DNRBaseAddr, SCALER_WIN eWindow)
5983 {
5984 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5985 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5986 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5987 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5988 pXCResourcePrivate->sthal_SC._u32DNRBaseAddress[eWindow] = u32DNRBaseAddr;
5989 return TRUE;
5990 }
5991
MHal_XC_GetDNRBufAddress(void * pInstance,SCALER_WIN eWindow)5992 MS_PHY MHal_XC_GetDNRBufAddress(void *pInstance, SCALER_WIN eWindow)
5993 {
5994 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
5995 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
5996 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
5997 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
5998 return pXCResourcePrivate->sthal_SC._u32DNRBaseAddress[eWindow] ;
5999 }
6000
MHal_XC_SetDNRBufSize(void * pInstance,MS_PHY u32DNRBufSize,SCALER_WIN eWindow)6001 MS_BOOL MHal_XC_SetDNRBufSize(void *pInstance, MS_PHY u32DNRBufSize, SCALER_WIN eWindow)
6002 {
6003 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6004 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6005 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6006 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6007 pXCResourcePrivate->sthal_SC._u32DNRBufferSize[eWindow] = u32DNRBufSize;
6008 return TRUE;
6009 }
6010
MHal_XC_GetDNRBufSize(void * pInstance,SCALER_WIN eWindow)6011 MS_PHY MHal_XC_GetDNRBufSize(void *pInstance, SCALER_WIN eWindow)
6012 {
6013 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6014 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6015 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6016 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6017 return pXCResourcePrivate->sthal_SC._u32DNRBufferSize[eWindow] ;
6018 }
6019
MHal_XC_SetFRCMBufAddress(void * pInstance,MS_PHY u32BaseAddr,SCALER_WIN eWindow)6020 MS_BOOL MHal_XC_SetFRCMBufAddress(void *pInstance, MS_PHY u32BaseAddr, SCALER_WIN eWindow)
6021 {
6022 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6023 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6024 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6025 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6026 pXCResourcePrivate->sthal_SC._u32FRCBaseAddress[eWindow] = u32BaseAddr;
6027 return TRUE;
6028 }
6029
MHal_XC_GetFRCMBufAddress(void * pInstance,SCALER_WIN eWindow)6030 MS_PHY MHal_XC_GetFRCMBufAddress(void *pInstance, SCALER_WIN eWindow)
6031 {
6032 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6033 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6034 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6035 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6036 return pXCResourcePrivate->sthal_SC._u32FRCBaseAddress[eWindow] ;
6037 }
6038
MHal_XC_SetFRCMBufSize(void * pInstance,MS_PHY u32BufSize,SCALER_WIN eWindow)6039 MS_BOOL MHal_XC_SetFRCMBufSize(void *pInstance, MS_PHY u32BufSize, SCALER_WIN eWindow)
6040 {
6041 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6042 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6043 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6044 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6045 pXCResourcePrivate->sthal_SC._u32FRCBufferSize[eWindow] = u32BufSize;
6046 return TRUE;
6047 }
6048
MHal_XC_GetFRCMBufSize(void * pInstance,SCALER_WIN eWindow)6049 MS_PHY MHal_XC_GetFRCMBufSize(void *pInstance, SCALER_WIN eWindow)
6050 {
6051 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6052 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6053 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6054 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6055 return pXCResourcePrivate->sthal_SC._u32FRCBufferSize[eWindow] ;
6056 }
6057
MHal_XC_SetDualDNRBufAddress(void * pInstance,MS_PHY u32DNRBaseAddr,SCALER_WIN eWindow)6058 MS_BOOL MHal_XC_SetDualDNRBufAddress(void *pInstance, MS_PHY u32DNRBaseAddr, SCALER_WIN eWindow)
6059 {
6060 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6061 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6062 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6063 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6064 pXCResourcePrivate->_u32DualDNRBaseAddress[eWindow] = u32DNRBaseAddr;
6065 return TRUE;
6066 }
6067
MHal_XC_GetDualDNRBufAddress(void * pInstance,SCALER_WIN eWindow)6068 MS_PHY MHal_XC_GetDualDNRBufAddress(void *pInstance, SCALER_WIN eWindow)
6069 {
6070 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6071 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6072 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6073 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6074 return pXCResourcePrivate->_u32DualDNRBaseAddress[eWindow];
6075 }
6076
MHal_XC_SetDualDNRBufSize(void * pInstance,MS_PHY u32DNRBufSize,SCALER_WIN eWindow)6077 MS_BOOL MHal_XC_SetDualDNRBufSize(void *pInstance, MS_PHY u32DNRBufSize, SCALER_WIN eWindow)
6078 {
6079 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6080 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6081 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6082 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6083 pXCResourcePrivate->_u32DualDNRBufferSize[eWindow] = u32DNRBufSize;
6084 return TRUE;
6085 }
6086
MHal_XC_GetDualDNRBufSize(void * pInstance,SCALER_WIN eWindow)6087 MS_PHY MHal_XC_GetDualDNRBufSize(void *pInstance, SCALER_WIN eWindow)
6088 {
6089 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6090 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6091 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6092 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6093 return pXCResourcePrivate->_u32DualDNRBufferSize[eWindow] ;
6094 }
6095
MHal_XC_Init_Patch(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6096 MS_BOOL MHal_XC_Init_Patch(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6097 {
6098 if (eWindow >= MAX_WINDOW)
6099 {
6100 printf("[%s,%5d] maximum window exceeded",__FUNCTION__,__LINE__);
6101 return FALSE;
6102 }
6103
6104 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6105 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6106
6107 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_6F_L, 0x20, 0x3F); // by HW RD's request, for BB section offset issue
6108
6109 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_25_L, 0x3030); // by HW RD's request, for HDMI 4K BW issue, adjust R/W line buffer length
6110 #ifdef UFO_XC_SUPPORT_DUAL_MIU
6111 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK52_25_L, 0x3030); // by HW RD's request, for HDMI 4K BW issue, adjust R/W line buffer length
6112 #endif
6113
6114 // SW patch for Monaco
6115 // by HW RD's request, to fix HDMI 1080i repeat garbage at left side
6116 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK12_37_L, 0x20); // bypass main line buffer length setting
6117 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK11_37_L, 0x20); // bypass sub line buffer length setting
6118
6119 // ECO item for Monaco: hvsp PIP B section last flag error
6120 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK23_5F_L, BIT(14), BIT(14));
6121
6122 // ECO item for Monaco: ip2ve 4K path Vsync need inverse
6123 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_7F_L, BIT(14), BIT(14));
6124 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK04_7F_L, BIT(14), BIT(14));
6125
6126 // SW patch for muji : 4k2k 3D LA out show garbage on the top, issue with BW
6127 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK58_10_L, 0x0000, BIT(0));//disable SCM sub OP
6128
6129 // BK00_03[13] conflict with compression mode (patch for HW issue)
6130 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK00_03_L, 0x0000, 0x2000);
6131
6132 //U03 compatible setting
6133 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK32_66_L, BIT(13), BIT(13));
6134
6135 ///Patch here ////
6136 #if (FRC_INSIDE)
6137 MHal_FRC_interrupt_mask(pInstance, 0xFF);
6138 #endif
6139
6140 // SW patch for Eisntein
6141 // With HW Auto no signal case, sub video source change would causes OP1 broken, looks like main video broken
6142 Hal_SC_ip_enable_turnoff_OP1_for_AutoNoSignal(pInstance, DISABLE);
6143
6144 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_61_L, 0x01, 0x03); // for HDMI 2.0, always receive 444 format
6145 SC_W2BYTEMSK(psXCInstPri->u32DeviceID,REG_SC_BK01_63_L, 0x01, 0x01); // for HDMI odd Htt support
6146
6147 return TRUE;
6148 }
MHal_XC_IsPNLYUVOutput(void * pInstance)6149 MS_BOOL MHal_XC_IsPNLYUVOutput(void *pInstance)
6150 {
6151 MS_BOOL bIsPNLYUVOutput = TRUE;
6152 #if 0//below is logic from TV, need box RD's confirm, disable it temporary
6153 MS_BOOL bIsY2REnable = FALSE, bIsR2YEnable = FALSE;
6154 SCALER_WIN eWindow = MAIN_WINDOW;
6155 MS_U16 u16Temp = 0;
6156 //Get CSC state before OP2
6157 if(gSrcInfo[MAIN_WINDOW].bBlackscreenEnabled || gSrcInfo[MAIN_WINDOW].bBluescreenEnabled)
6158 {
6159 //Main is mute, so check sub
6160 if(Hal_SC_Is_subwindow_enable())
6161 {
6162 if(!(gSrcInfo[SUB_WINDOW].bBlackscreenEnabled || gSrcInfo[SUB_WINDOW].bBluescreenEnabled))
6163 {
6164 eWindow = SUB_WINDOW;
6165 }
6166 }
6167 }
6168
6169 if(eWindow == MAIN_WINDOW)
6170 {
6171 u16Temp = SC_R2BYTE(REG_SC_BK10_2F_L);
6172 if((u16Temp & ( BIT(0) | BIT(2) | BIT(4))) == ( BIT(0) | BIT(2) | BIT(4)))
6173 {
6174 bIsY2REnable = TRUE;
6175 }
6176 }
6177 else
6178 {
6179 u16Temp = SC_R2BYTE(REG_SC_BK0F_26_L);
6180 if((u16Temp & ( BIT(0) | BIT(2) | BIT(4))) == ( BIT(0) | BIT(2) | BIT(4)))
6181 {
6182 bIsY2REnable = TRUE;
6183 }
6184 }
6185
6186 if(bIsY2REnable)
6187 {
6188 bIsPNLYUVOutput = FALSE;
6189 }
6190 else
6191 {
6192 //OP Y2R disable, so check op input
6193 if(eWindow == MAIN_WINDOW)
6194 {
6195 bIsR2YEnable = (MS_BOOL)(SC_R2BYTEMSK(REG_SC_BK02_40_L, BIT(3)) || SC_R2BYTEMSK(REG_SC_BK18_06_L, BIT(0)));
6196
6197 }
6198 else
6199 {
6200 bIsR2YEnable = (MS_BOOL)(SC_R2BYTEMSK(REG_SC_BK04_40_L, BIT(3)) || SC_R2BYTEMSK(REG_SC_BK18_76_L, BIT(0)));
6201 }
6202
6203 if(bIsR2YEnable)
6204 {
6205 //Y2R enable
6206 bIsPNLYUVOutput = TRUE;
6207 }
6208 else
6209 {
6210 //All Csc is off, so check input
6211 //VGA/DVI/rgb HDMI is rgb input
6212 if( IsSrcTypeVga(gSrcInfo[eWindow].enInputSourceType) //VGA
6213 ||IsSrcTypeDVI(gSrcInfo[eWindow].enInputSourceType) //DVI
6214 ||( IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType)
6215 &&(g_HdmiPollingStatus.bIsHDMIMode == TRUE)
6216 &&(g_HdmiPollingStatus.u8ColorFormat == MS_HDMI_COLOR_RGB))//HDMI RGB
6217 ||( IsSrcTypeHDMI(gSrcInfo[eWindow].enInputSourceType)
6218 &&(g_HdmiPollingStatus.bIsHDMIMode == FALSE)) //HDMI_DVI
6219 )
6220 {
6221 bIsPNLYUVOutput = FALSE;
6222 }
6223 else
6224 {
6225 bIsPNLYUVOutput = TRUE;
6226 }
6227 }
6228 }
6229 #endif
6230 return bIsPNLYUVOutput;
6231 }
6232
MHal_SC_Memory_Request_Force_Off(void * pInstance,MS_BOOL bEnable,E_XC_FORCE_MEMORY_REQUEST_OFF eMemoryOffType)6233 static void MHal_SC_Memory_Request_Force_Off(void * pInstance, MS_BOOL bEnable,E_XC_FORCE_MEMORY_REQUEST_OFF eMemoryOffType)
6234 {
6235 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6236 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6237
6238 switch(eMemoryOffType)
6239 {
6240 case E_XC_FORCE_MEMORY_REQUEST_OFF_MAIN:
6241 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_39_L, bEnable?BIT(0):0x00, BIT(0));
6242 break;
6243 case E_XC_FORCE_MEMORY_REQUEST_OFF_MIAN_DUAL:
6244 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_39_L, bEnable?BIT(4):0x00, BIT(4));
6245 break;
6246 case E_XC_FORCE_MEMORY_REQUEST_OFF_SUB:
6247 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_39_L, bEnable?BIT(1):0x00, BIT(1));
6248 break;
6249 case E_XC_FORCE_MEMORY_REQUEST_OFF_SUB_DUAL:
6250 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_39_L, bEnable?BIT(2):0x00, BIT(2));
6251 break;
6252 case E_XC_FORCE_MEMORY_REQUEST_OFF_SUB_OPW:
6253 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_39_L, bEnable?BIT(6):0x00, BIT(6));
6254 break;
6255 case E_XC_FORCE_MEMORY_REQUEST_OFF_ALL:
6256 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK0D_39_L, bEnable?(BIT(0)|BIT(1)|BIT(2)|BIT(4)|BIT(6)):0x00, (BIT(0)|BIT(1)|BIT(2)|BIT(4)|BIT(6)));
6257 break;
6258 default:
6259 break;
6260 }
6261 }
6262
Hal_SC_Init(void * pInstance)6263 MS_BOOL Hal_SC_Init(void *pInstance)
6264 {
6265 #ifndef DONT_USE_CMA
6266 #if (XC_SUPPORT_CMA ==TRUE)
6267 MHal_SC_Memory_Request_Force_Off(pInstance, TRUE, E_XC_FORCE_MEMORY_REQUEST_OFF_ALL);
6268 #endif
6269 #endif
6270 return TRUE;
6271 }
6272
Hal_SC_Get_Device_Offset(MS_U8 deviceIdx)6273 MS_U32 Hal_SC_Get_Device_Offset(MS_U8 deviceIdx)
6274 {
6275 MS_U32 ret_U32 = 0 ;
6276 if(deviceIdx == 0 )
6277 {
6278 ret_U32 = MAX_XC_DEVICE0_OFFSET;
6279 }
6280 else if(deviceIdx == 1)
6281 {
6282 ret_U32 = MAX_XC_DEVICE1_OFFSET;
6283 }
6284 return ret_U32;
6285 }
6286
HAL_SC_Set_LB_MergeAddress(void * pInstance)6287 void HAL_SC_Set_LB_MergeAddress(void *pInstance)
6288 {
6289 return;
6290 }
6291
Hal_SC_set_edclk(void * pInstance,MS_U8 u8Clk_Mux,MS_BOOL bEnable,SCALER_WIN eWindow)6292 void Hal_SC_set_edclk(void *pInstance, MS_U8 u8Clk_Mux, MS_BOOL bEnable, SCALER_WIN eWindow)
6293 {
6294 if(eWindow==MAIN_WINDOW)
6295 {
6296 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, (bEnable? 0x00 : CKG_EDCLK_F2_GATED), CKG_EDCLK_F2_GATED);
6297 if(bEnable)
6298 MDrv_WriteByteMask(REG_CKG_EDCLK_F2, u8Clk_Mux, CKG_EDCLK_F2_MASK);
6299 }
6300 else if(eWindow==SUB_WINDOW)
6301 {
6302 MDrv_WriteByteMask(REG_CKG_EDCLK_F1, (bEnable? 0x00 : CKG_EDCLK_F1_GATED), CKG_EDCLK_F1_GATED);
6303 if(bEnable)
6304 MDrv_WriteByteMask(REG_CKG_EDCLK_F1, u8Clk_Mux, CKG_EDCLK_F1_MASK);
6305 }
6306 }
6307
Hal_SC_set_ficlk2(void * pInstance,MS_U8 u8Clk_Mux,MS_BOOL bEnable,SCALER_WIN eWindow)6308 void Hal_SC_set_ficlk2(void *pInstance, MS_U8 u8Clk_Mux, MS_BOOL bEnable, SCALER_WIN eWindow)
6309 {
6310 if(eWindow==MAIN_WINDOW)
6311 {
6312 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, (bEnable? 0x00 : CKG_FICLK2_F2_GATED), CKG_FICLK2_F2_GATED);
6313 if(bEnable)
6314 MDrv_WriteByteMask(REG_CKG_FICLK2_F2, u8Clk_Mux, CKG_FICLK2_F2_MASK);
6315 }
6316 else if(eWindow==SUB_WINDOW)
6317 {
6318 printf("[%s,%5d] ficlk2_f2 not support sub!",__FUNCTION__,__LINE__);// no ficlk2_f1 for sub window
6319 }
6320 }
6321
Hal_SC_set_fmclk(void * pInstance,MS_BOOL bEnable)6322 void Hal_SC_set_fmclk(void *pInstance, MS_BOOL bEnable)
6323 {
6324 if(bEnable == TRUE)
6325 {
6326 MDrv_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_FCLK, CKG_FMCLK_MASK);
6327 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_GATED);
6328 MDrv_WriteByteMask(REG_CKG_FMCLK, DISABLE, CKG_FMCLK_INVERT);
6329 }
6330 else
6331 {
6332 MDrv_WriteByteMask(REG_CKG_FMCLK, ENABLE, CKG_FMCLK_GATED); // disable clock
6333 }
6334 }
6335
HAL_SC_EnableLegacyMode(void * pInstance,MS_BOOL bEnable)6336 void HAL_SC_EnableLegacyMode(void *pInstance, MS_BOOL bEnable)
6337 {
6338 #if (HW_DESIGN_4K2K_VER == 4)
6339 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6340 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6341
6342 if (psXCInstPri->u32DeviceID == 0)
6343 {
6344 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_01_L, (bEnable<<0), BIT(0));
6345 }
6346 else
6347 {
6348 // do nothing, because there is only legacy mode in SC2, we don't have to do any switch
6349 }
6350 #endif
6351 }
6352
MHal_XC_DTVPatchISR(SC_INT_SRC eIntNum,void * pParam)6353 static void MHal_XC_DTVPatchISR(SC_INT_SRC eIntNum, void * pParam)
6354 {
6355 void *pInstance = pu32XCInst_private;
6356 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6357 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6358 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6359 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6360
6361 if(gSrcInfo[MAIN_WINDOW].bBlackscreenEnabled==FALSE)
6362 {
6363 //Check timing 2s
6364 if(((MsOS_GetSystemTime()- u32DTVPatchTimer)>2000))
6365 {
6366 u32DTVPatchTimer = MsOS_GetSystemTime();
6367 u16FDMaskCount=0;
6368 }
6369
6370 //Check FD mask
6371 if(bPreFDMaskStatse != (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0))
6372 {
6373 bPreFDMaskStatse =(SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, BIT(4))==0);
6374 u16FDMaskCount++;
6375 }
6376
6377 if(u16FDMaskCount>6)
6378 {
6379 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
6380 {
6381 //UC_CTL off
6382 _MLOAD_ENTRY(pInstance);
6383 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK17_01_L, 0 ,BIT(0));
6384 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK57_23_L, 0 ,0x40);
6385 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_67_L, 0x80 ,0xF0);
6386 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK12_07_L, 0 ,BIT(0));
6387 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_20_L, 0 ,BIT(7));
6388 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK11_21_L, 0 ,BIT(15));
6389 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_78_L, 0 ,0xC000);
6390 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2A_02_L, BIT(1) ,BIT(1)|BIT(15));
6391 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_20_L, 0 ,BIT(0));
6392 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK05_12_L, 0 ,BIT(0));
6393 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK2A_07_L, 0 ,BIT(0));
6394 MDrv_XC_MLoad_Fire(pInstance, TRUE);
6395 _MLOAD_RETURN(pInstance);
6396 }
6397 else
6398 {
6399 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK17_01_L, 0 ,BIT(0));
6400 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_23_L, 0 ,0x40);
6401 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_67_L, 0x80 ,0xF0);
6402 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK12_07_L, 0 ,BIT(0));
6403 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_20_L, 0 ,BIT(7));
6404 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK11_21_L, 0 ,BIT(15));
6405 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_78_L, 0 ,0xC000);
6406 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_02_L, BIT(1) ,BIT(1)|BIT(15));
6407 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_20_L, 0 ,BIT(0));
6408 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK05_12_L, 0 ,BIT(0));
6409 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK2A_07_L, 0 ,BIT(0));
6410 }
6411
6412 u16FDMaskCount=0;
6413
6414 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL))
6415 {
6416 //Disable ISR
6417 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL);
6418 }
6419 }
6420 }
6421 }
6422
MHal_XC_DTVPatch(void * pInstance,SCALER_WIN eWindow)6423 void MHal_XC_DTVPatch(void *pInstance, SCALER_WIN eWindow)
6424 {
6425 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6426 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6427 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6428 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6429
6430 if(eWindow ==MAIN_WINDOW)
6431 {
6432 if(IsSrcTypeDTV(gSrcInfo[MAIN_WINDOW].enInputSourceType)
6433 &&(gSrcInfo[MAIN_WINDOW].stCapWin.width==1920)
6434 &&(gSrcInfo[MAIN_WINDOW].stCapWin.height==1080)
6435 &&(gSrcInfo[MAIN_WINDOW].bInterlace==TRUE))
6436 {
6437 //DTV 1080i patch
6438 if(FALSE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT,MHal_XC_DTVPatchISR, (void *)NULL))
6439 {
6440 //Start DTV 1080i patch, enable ISR
6441 MDrv_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT,MHal_XC_DTVPatchISR, (void *)NULL);
6442 }
6443 }
6444 else
6445 {
6446 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL))
6447 {
6448 //Disable ISR
6449 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_DTVPatchISR, (void *)NULL);
6450 }
6451 }
6452 }
6453 }
6454
6455
6456 #ifndef DONT_USE_CMA
6457 #if (XC_SUPPORT_CMA ==TRUE)
MHal_XC_Get_CMA_Addr(void * pInstance,XC_CMA_CLIENT enCmaClient,MS_U32 u32GetCMASize,SCALER_WIN eWindow)6458 MS_U64 MHal_XC_Get_CMA_Addr(void *pInstance, XC_CMA_CLIENT enCmaClient, MS_U32 u32GetCMASize, SCALER_WIN eWindow)
6459 {
6460 MS_U64 u64CMAAddr = 0;
6461 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6462 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6463 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6464 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6465
6466 if (u32GetCMASize == 0)
6467 {
6468 return u64CMAAddr;
6469 }
6470
6471 struct CMA_Pool_Alloc_Param CMA_Pool_GetMem;
6472 CMA_Pool_GetMem.pool_handle_id = CMA_Pool_Init_PARAM[enCmaClient].pool_handle_id;
6473 CMA_Pool_GetMem.offset_in_pool = gSrcInfo[eWindow].Status2.stXCConfigCMA[enCmaClient].u64AddrHeapOffset;
6474 CMA_Pool_GetMem.flags = CMA_FLAG_VIRT_ADDR;
6475 if(CMA_Pool_Init_PARAM[enCmaClient].heap_length >= u32GetCMASize)
6476 {
6477 CMA_Pool_GetMem.length = u32GetCMASize;
6478 }
6479 else
6480 {
6481 printf("\033[35m Function = %s, Line = %d, Max CMA buffer size is %x!!\033[m\n", __PRETTY_FUNCTION__, __LINE__,(MS_U32)(CMA_Pool_Init_PARAM[enCmaClient].heap_length));
6482 CMA_Pool_GetMem.length = CMA_Pool_Init_PARAM[enCmaClient].heap_length;
6483 }
6484
6485 MApi_CMA_Pool_GetMem(&CMA_Pool_GetMem);
6486 u64CMAAddr = CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset;
6487 if(CMA_Pool_Init_PARAM[enCmaClient].miu==E_CHIP_MIU_1)
6488 {
6489 u64CMAAddr= CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset+HAL_MIU1_BASE;
6490 }
6491 else if(CMA_Pool_Init_PARAM[enCmaClient].miu==E_CHIP_MIU_2)
6492 {
6493 u64CMAAddr= CMA_Pool_Init_PARAM[enCmaClient].heap_miu_start_offset+HAL_MIU2_BASE;
6494 }
6495
6496 MHal_SC_Memory_Request_Force_Off(pInstance, FALSE, E_XC_FORCE_MEMORY_REQUEST_OFF_ALL);
6497 return u64CMAAddr;
6498 }
6499
MHal_XC_Release_CMA(void * pInstance,XC_CMA_CLIENT enCmaClient,SCALER_WIN eWindow)6500 MS_BOOL MHal_XC_Release_CMA(void *pInstance, XC_CMA_CLIENT enCmaClient, SCALER_WIN eWindow)
6501 {
6502 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6503 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6504 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6505 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6506
6507 struct CMA_Pool_Free_Param stCMAFreeParam;
6508 if ((gSrcInfo[eWindow].u32PreCMAMemSCMSize[enCmaClient]+gSrcInfo[eWindow].u32PreCMAMemFRCMSize[enCmaClient])!=0)
6509 {
6510 MHal_SC_Memory_Request_Force_Off(pInstance, TRUE, E_XC_FORCE_MEMORY_REQUEST_OFF_MAIN);
6511 stCMAFreeParam.pool_handle_id = CMA_Pool_Init_PARAM[enCmaClient].heap_id; //in: pool handle id, when pool init, returned by kernel
6512 stCMAFreeParam.offset_in_pool = gSrcInfo[eWindow].Status2.stXCConfigCMA[enCmaClient].u64AddrHeapOffset;
6513 stCMAFreeParam.length = gSrcInfo[eWindow].u32PreCMAMemSCMSize[enCmaClient]+gSrcInfo[eWindow].u32PreCMAMemFRCMSize[enCmaClient];
6514 MApi_CMA_Pool_PutMem(&stCMAFreeParam);
6515
6516 gSrcInfo[eWindow].u32PreCMAMemSCMSize[enCmaClient] = 0;
6517 gSrcInfo[eWindow].u32PreCMAMemFRCMSize[enCmaClient] = 0;
6518 }
6519
6520 if ((gSrcInfo[MAIN_WINDOW].Status2.u32PreCMAMemDualSCMSize != 0) && (enCmaClient == CMA_XC_COBUFF_MEM))
6521 {
6522 MHal_SC_Memory_Request_Force_Off(pInstance, TRUE, E_XC_FORCE_MEMORY_REQUEST_OFF_MIAN_DUAL);
6523 stCMAFreeParam.pool_handle_id = CMA_Pool_Init_PARAM[enCmaClient].heap_id; //in: pool handle id, when pool init, returned by kernel
6524 stCMAFreeParam.offset_in_pool = gSrcInfo[eWindow].Status2.stXCConfigCMA[enCmaClient].u64AddrHeapOffset;
6525 stCMAFreeParam.length = gSrcInfo[MAIN_WINDOW].Status2.u32PreCMAMemDualSCMSize;
6526 MApi_CMA_Pool_PutMem(&stCMAFreeParam);
6527
6528 gSrcInfo[MAIN_WINDOW].Status2.u32PreCMAMemDualSCMSize = 0;
6529 }
6530
6531 return TRUE;
6532 }
6533
_getDualModeMemorySize(void * pInstance,MS_U32 * pu32LeftSize,MS_U32 * pu32RightSize,SCALER_WIN eWindow)6534 static MS_BOOL _getDualModeMemorySize(void *pInstance, MS_U32 *pu32LeftSize, MS_U32 *pu32RightSize, SCALER_WIN eWindow)
6535 {
6536 MS_U32 u32TotalSize = 0;
6537
6538 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6539 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6540 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6541 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6542 if (gSrcInfo[eWindow].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID != XC_INVALID_HEAP_ID)
6543 {
6544 u32TotalSize = XC_CMA_96MB;
6545 }
6546 *pu32LeftSize = u32TotalSize * gSrcInfo[eWindow].Status2.stMiuDualModCfg.u32LeftFactor/(gSrcInfo[eWindow].Status2.stMiuDualModCfg.u32LeftFactor + gSrcInfo[eWindow].Status2.stMiuDualModCfg.u32RightFactor);
6547 *pu32RightSize = u32TotalSize - *pu32LeftSize;
6548 return TRUE;
6549 }
6550
MHal_XC_Get_CMA_UsingCondition(void * pInstance,MS_BOOL bIsGetCMABuff[],MS_U32 au32CMAMemSCMSize[],MS_U32 au32CMAMemFRCMSize[],MS_U32 * pu32DualMiuMemSize,MS_U32 u32DataSize,SCALER_WIN eWindow)6551 MS_BOOL MHal_XC_Get_CMA_UsingCondition(void *pInstance, MS_BOOL bIsGetCMABuff[], MS_U32 au32CMAMemSCMSize[],MS_U32 au32CMAMemFRCMSize[], MS_U32* pu32DualMiuMemSize, MS_U32 u32DataSize, SCALER_WIN eWindow)
6552 {
6553 MS_U32 u32CMAMemSCMSize = 0;
6554 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6555 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6556 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6557 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6558
6559 if (u32DataSize < CMA_XC_MEM_NUM)
6560 {
6561 return FALSE;
6562 }
6563
6564 if (((MDrv_XC_Is_DSForceIndexEnabled(pInstance, MAIN_WINDOW)||MDrv_XC_GetDynamicScalingStatus(pInstance))
6565 && IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType)) ||
6566 (pXCResourcePrivate->sthal_Optee.op_tee_xc[MAIN_WINDOW].isEnable == TRUE))
6567 {
6568 // MM source and DS on
6569 if(gSrcInfo[eWindow].bInterlace)
6570 {
6571 //DS ON , FHD case
6572 u32CMAMemSCMSize = XC_CMA_24MB;
6573 }
6574 else
6575 {
6576 //DS ON , 4K2K case
6577 if(gSrcInfo[eWindow].eFBLevel == E_XC_FB_LEVEL_FB)
6578 {
6579 // 4K2K input source,prescaling case,run in FB mode
6580 u32CMAMemSCMSize = XC_CMA_48MB;
6581 }
6582 else
6583 {
6584 u32CMAMemSCMSize = XC_CMA_18MB;
6585 }
6586 }
6587 }
6588 else if (IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType))
6589 {
6590 if((gSrcInfo[eWindow].stCapWin.width>=XC_4K2K_WIDTH_MIN)&&(gSrcInfo[eWindow].stCapWin.height>=XC_4K2K_HIGH_MIN))
6591 {
6592 if(gSrcInfo[eWindow].u16InputVFreq <= 151)
6593 {
6594 u32CMAMemSCMSize = XC_CMA_48MB;
6595 }
6596 else
6597 {
6598 u32CMAMemSCMSize = 0;
6599 }
6600 }
6601 else
6602 {
6603 u32CMAMemSCMSize = XC_CMA_24MB;
6604 }
6605 }
6606 else if ( (IsSrcTypeAV(gSrcInfo[eWindow].enInputSourceType))
6607 ||(IsSrcTypeSV(gSrcInfo[eWindow].enInputSourceType))
6608 ||(IsSrcTypeATV(gSrcInfo[eWindow].enInputSourceType))
6609 ||(IsSrcTypeScart(gSrcInfo[eWindow].enInputSourceType)))
6610 {
6611 u32CMAMemSCMSize = XC_CMA_19MB;
6612 }
6613 else
6614 {
6615 if ( ((gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI)||(gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI2)||(gSrcInfo[eWindow].enInputSourceType == INPUT_SOURCE_HDMI3))
6616 &&((gSrcInfo[(eWindow)].stCapWin.width>= 3840) && (gSrcInfo[(eWindow)].stCapWin.height>= 2160))
6617 &&(IS_OUTPUT_4K2K()))
6618 {
6619 u32CMAMemSCMSize = XC_CMA_48MB;
6620 }
6621 else
6622 {
6623 u32CMAMemSCMSize = XC_CMA_24MB;
6624 }
6625 }
6626
6627 if (
6628 #ifdef UFO_XC_SUPPORT_DUAL_MIU
6629 (gSrcInfo[eWindow].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID != XC_INVALID_HEAP_ID)
6630 && IsEnableDualMode(eWindow)
6631 #else
6632 0
6633 #endif
6634 &&(IS_OUTPUT_4K2K()))
6635 {
6636 bIsGetCMABuff[CMA_XC_SELF_MEM] = TRUE;
6637 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = TRUE;
6638 //*pu32DualMiuMemSize = XC_CMA_48MB;
6639 //au32CMAMemSCMSize[CMA_XC_SELF_MEM] = u32CMAMemSCMSize;
6640 _getDualModeMemorySize(pInstance, &au32CMAMemSCMSize[CMA_XC_SELF_MEM], pu32DualMiuMemSize, eWindow);
6641 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = 0;
6642 }
6643 else
6644 {
6645 if (gSrcInfo[eWindow].Status2.stXCConfigCMA[CMA_XC_COBUFF_MEM].u32HeapID == XC_INVALID_HEAP_ID || (IsSrcTypeStorage(gSrcInfo[eWindow].enInputSourceType) && (gSrcInfo[eWindow].bInterlace)) || IsSrcTypeDTV(gSrcInfo[eWindow].enInputSourceType))
6646 {
6647 bIsGetCMABuff[CMA_XC_SELF_MEM] = TRUE;
6648 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = FALSE;
6649 au32CMAMemSCMSize[CMA_XC_SELF_MEM] = u32CMAMemSCMSize;
6650 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = 0;
6651 }
6652 else
6653 {
6654 bIsGetCMABuff[CMA_XC_SELF_MEM] = FALSE;
6655 bIsGetCMABuff[CMA_XC_COBUFF_MEM] = TRUE;
6656 au32CMAMemSCMSize[CMA_XC_SELF_MEM] = 0;
6657 au32CMAMemSCMSize[CMA_XC_COBUFF_MEM] = u32CMAMemSCMSize;
6658 }
6659 *pu32DualMiuMemSize = 0;
6660 }
6661
6662 au32CMAMemFRCMSize[CMA_XC_SELF_MEM] = 0;
6663 au32CMAMemFRCMSize[CMA_XC_COBUFF_MEM] = 0;
6664
6665 return TRUE;
6666 }
6667
MHal_XC_CMAPatchISR(SC_INT_SRC eIntNum,void * pParam)6668 static void MHal_XC_CMAPatchISR(SC_INT_SRC eIntNum, void * pParam)
6669 {
6670 void *pInstance = pu32XCInst_private;
6671 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6672 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6673 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6674 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6675
6676 if((MDrv_XC_IsInputSourceDisabled(pInstance, MAIN_WINDOW)==TRUE)
6677 &&( ((gSrcInfo[MAIN_WINDOW].u32PreCMAMemSCMSize[CMA_XC_SELF_MEM]+gSrcInfo[MAIN_WINDOW].u32PreCMAMemFRCMSize[CMA_XC_SELF_MEM])!=0)
6678 ||((gSrcInfo[MAIN_WINDOW].u32PreCMAMemSCMSize[CMA_XC_COBUFF_MEM]+gSrcInfo[MAIN_WINDOW].u32PreCMAMemFRCMSize[CMA_XC_COBUFF_MEM])!=0)
6679 #ifdef UFO_XC_SUPPORT_DUAL_MIU
6680 ||(gSrcInfo[MAIN_WINDOW].Status2.u32PreCMAMemDualSCMSize!=0)
6681 #endif
6682 )
6683 )
6684 {
6685 //Check timing 5s
6686 if(((MsOS_GetSystemTime()- u32CMAPatchTimer_Main)>5000))
6687 {
6688 u32CMAPatchTimer_Main = MsOS_GetSystemTime();
6689
6690 MHal_XC_Release_CMA(pInstance, CMA_XC_SELF_MEM, MAIN_WINDOW);
6691 MHal_XC_Release_CMA(pInstance, CMA_XC_COBUFF_MEM, MAIN_WINDOW);
6692 }
6693 }
6694 else
6695 {
6696 u32CMAPatchTimer_Main = MsOS_GetSystemTime();
6697 }
6698 }
6699
MHal_XC_CMAPatch(void * pInstance,SCALER_WIN eWindow)6700 void MHal_XC_CMAPatch(void *pInstance, SCALER_WIN eWindow)
6701 {
6702 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6703 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6704 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6705 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6706
6707 if(eWindow ==MAIN_WINDOW)
6708 {
6709 if(FALSE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT,MHal_XC_CMAPatchISR, (void *)NULL))
6710 {
6711 //Start CMA patch, enable ISR
6712 //FIXME: PATCH
6713 u32CMAPatchTimer_Main = MsOS_GetSystemTime();
6714 MDrv_XC_InterruptAttachWithoutMutex(pInstance, SC_INT_VSINT,MHal_XC_CMAPatchISR, (void *)NULL);
6715 }
6716 }
6717 }
6718
MHal_XC_CMAPatchClose(void * pInstance,SCALER_WIN eWindow)6719 void MHal_XC_CMAPatchClose(void *pInstance, SCALER_WIN eWindow)
6720 {
6721 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6722 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6723 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6724 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6725
6726 if(eWindow ==MAIN_WINDOW)
6727 {
6728 if(TRUE == MDrv_XC_InterruptIsAttached(pInstance, SC_INT_VSINT, MHal_XC_CMAPatchISR, (void *)NULL))
6729 {
6730 //Disable ISR
6731 MDrv_XC_InterruptDeAttachWithoutMutex(pInstance, SC_INT_VSINT, MHal_XC_CMAPatchISR, (void *)NULL);
6732 }
6733 }
6734 }
6735 #endif
6736 #endif
6737
MHAL_SC_set_r2y_en(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6738 void MHAL_SC_set_r2y_en(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6739 {
6740 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6741 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6742 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6743 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6744
6745 if(eWindow == MAIN_WINDOW)
6746 {
6747 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_06_L, bEnable?BIT(0):0x00, BIT(0));
6748 }
6749 else if(eWindow == SUB_WINDOW)
6750 {
6751 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_76_L, bEnable?BIT(0):0x00, BIT(0));
6752 }
6753 }
6754
MHAL_SC_get_r2y_en_status(void * pInstance,SCALER_WIN eWindow)6755 MS_BOOL MHAL_SC_get_r2y_en_status(void *pInstance, SCALER_WIN eWindow)
6756 {
6757 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6758 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6759 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
6760 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
6761
6762 MS_BOOL bstatus = FALSE;
6763
6764 if(eWindow == MAIN_WINDOW)
6765 {
6766 bstatus = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_06_L, BIT(0));
6767 }
6768 else if(eWindow == SUB_WINDOW)
6769 {
6770 bstatus = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK18_76_L, BIT(0));
6771 }
6772
6773 return bstatus;
6774 }
6775
Hal_SC_set_T3D_setting(void * pInstance,MS_BOOL bEnable)6776 void Hal_SC_set_T3D_setting(void *pInstance, MS_BOOL bEnable)
6777 {
6778 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6779 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6780
6781 if (MDrv_XC_MLoad_GetStatus(pInstance) == E_MLOAD_ENABLED)
6782 {
6783 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
6784 }
6785 else
6786 {
6787 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK62_63_L, 0x00, BIT(0)); // default disable T3D SRAM
6788 }
6789
6790 }
6791
Hal_SC_set_T3D_H_size(void * pInstance,MS_U16 u16Hsize)6792 void Hal_SC_set_T3D_H_size(void *pInstance, MS_U16 u16Hsize)
6793 {
6794 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6795 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6796
6797 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK63_55_L, u16Hsize, 0x1FFF); //horizontal pixel number
6798 }
6799
Hal_SC_3D_Is_LR_Sbs2Line(void * pInstance)6800 MS_BOOL Hal_SC_3D_Is_LR_Sbs2Line(void *pInstance)
6801 {
6802 if(SC_R2BYTEMSK(0, REG_SC_BK23_53_L, BIT(15)))
6803 {
6804 return TRUE;
6805 }
6806 else
6807 {
6808 return FALSE;
6809 }
6810 }
6811
Hal_SC_3D_SetLRChgMode(void * pInstance,HAL_SC_3D_LRCHGMODE eLRChgMode)6812 void Hal_SC_3D_SetLRChgMode(void *pInstance, HAL_SC_3D_LRCHGMODE eLRChgMode)
6813 {
6814 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6815 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6816 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, eLRChgMode, BIT(1)|BIT(0));
6817 }
6818
6819 // 0: L is the first frame, 1: R is the first frame
Hal_SC_3D_SetInitialLRIndex(void * pInstance,MS_BOOL bRFirst)6820 void Hal_SC_3D_SetInitialLRIndex(void *pInstance, MS_BOOL bRFirst)
6821 {
6822 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6823 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6824 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, (bRFirst==TRUE)?BIT(4):0, BIT(4));
6825 }
6826
6827 // Split 1 frame into 2 frames
Hal_SC_3D_SetSplitHalf(void * pInstance,MS_BOOL bEnable)6828 void Hal_SC_3D_SetSplitHalf(void *pInstance, MS_BOOL bEnable)
6829 {
6830 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6831 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6832 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_63_L, (bEnable==TRUE)?BIT(8):0, BIT(8));
6833 }
6834
Hal_SC_set_frcm_to_FD_mask(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)6835 void Hal_SC_set_frcm_to_FD_mask(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
6836 {
6837 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6838 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6839 if (eWindow == MAIN_WINDOW)
6840 {
6841 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(2):0, BIT(2));
6842 }
6843 else
6844 {
6845 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(10):0, BIT(10));
6846 }
6847 }
6848
Hal_SC_3D_set_top_win_6Tap(void * pInstance,MS_BOOL bEnable)6849 void Hal_SC_3D_set_top_win_6Tap(void *pInstance, MS_BOOL bEnable)
6850 {
6851 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6852 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6853 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_23_L, (bEnable==TRUE)?BIT(10):0, BIT(10)); //force top window using 6line
6854 }
6855
Hal_SC_3D_SetActiveVideoHeight(void * pInstance,MS_U16 u16VideoSize)6856 void Hal_SC_3D_SetActiveVideoHeight(void *pInstance, MS_U16 u16VideoSize)
6857 {
6858 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6859 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6860
6861 #if _ENABLE_SW_DS
6862 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
6863 {
6864 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_65_L,u16VideoSize,DS_IP);
6865 }
6866 else
6867 #endif
6868 {
6869 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_65_L, u16VideoSize, 0x1FFF);//v_active region
6870 }
6871 }
6872
6873 // 0 for blank area 0
6874 //v blanking between field1&field2 or field3&field4
Hal_SC_3D_SetActiveBlankSize0(void * pInstance,MS_U16 u16BlankSize)6875 void Hal_SC_3D_SetActiveBlankSize0(void *pInstance, MS_U16 u16BlankSize)
6876 {
6877 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6878 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6879 #if _ENABLE_SW_DS
6880 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
6881 {
6882 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_66_L,u16BlankSize,DS_IP);
6883 }
6884 else
6885 #endif
6886 {
6887 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_66_L, u16BlankSize, 0x1FFF);
6888 }
6889 }
6890
6891 // 1 for blank area 1
6892 //v blanking between field2&field3
Hal_SC_3D_SetActiveBlankSize1(void * pInstance,MS_U16 u16BlankSize)6893 void Hal_SC_3D_SetActiveBlankSize1(void *pInstance, MS_U16 u16BlankSize)
6894 {
6895 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6896 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6897 #if _ENABLE_SW_DS
6898 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
6899 {
6900 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_67_L,u16BlankSize,DS_IP);
6901 }
6902 else
6903 #endif
6904 {
6905 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_67_L, u16BlankSize, 0x1FFF);//v blanking between field1&field2 or field3&field4
6906 }
6907 }
6908
Hal_SC_3D_SetActiveVideoWidth(void * pInstance,MS_U16 u16VideoSize)6909 void Hal_SC_3D_SetActiveVideoWidth(void *pInstance, MS_U16 u16VideoSize)
6910 {
6911 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6912 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6913
6914 MS_U16 u16ActiveWidthUsrEnable = 0;
6915 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, BIT(15)) == BIT(15))
6916 {
6917 u16ActiveWidthUsrEnable = BIT(15);
6918 }
6919
6920 #if _ENABLE_SW_DS
6921 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
6922 {
6923 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_7F_L,u16VideoSize | u16ActiveWidthUsrEnable,DS_IP);
6924 }
6925 else
6926 #endif
6927 {
6928 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_7F_L, u16VideoSize | u16ActiveWidthUsrEnable, 0x9FFF);//v_active region
6929 }
6930 }
6931
6932
Hal_SC_3D_SetActiveVideoHeightAfterVSD(void * pInstance,MS_U16 u16VideoSize)6933 void Hal_SC_3D_SetActiveVideoHeightAfterVSD(void *pInstance, MS_U16 u16VideoSize)
6934 {
6935 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6936 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6937
6938 MS_U16 u16Enable = BIT(15);
6939
6940 #if _ENABLE_SW_DS
6941 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
6942 {
6943 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_38_L,u16VideoSize | u16Enable,DS_IP);
6944 }
6945 else
6946 #endif
6947 {
6948 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_38_L, u16VideoSize | u16Enable, 0x9FFF);
6949 }
6950 }
6951
Hal_SC_3D_SetFRCMActiveVideoHeightAfterVSD(void * pInstance,MS_U16 u16VideoSize)6952 void Hal_SC_3D_SetFRCMActiveVideoHeightAfterVSD(void *pInstance, MS_U16 u16VideoSize)
6953 {
6954 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6955 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6956
6957 MS_U16 u16Enable = BIT(15);
6958
6959 #if _ENABLE_SW_DS
6960 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
6961 {
6962 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK48_38_L,u16VideoSize | u16Enable,DS_IP);
6963 }
6964 else
6965 #endif
6966 {
6967 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK48_38_L, u16VideoSize | u16Enable, 0x9FFF);
6968 }
6969 }
6970
Hal_SC_3D_SetPixelSeparationWidth(void * pInstance,MS_U16 u16VideoSize)6971 void Hal_SC_3D_SetPixelSeparationWidth(void *pInstance, MS_U16 u16VideoSize)
6972 {
6973 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6974 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
6975
6976 MS_U16 u16ActiveWidthUsrEnable = 0;
6977 #if (HW_DESIGN_3D_VER >= 3)
6978 if (SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK01_2F_L, BIT(15)) == BIT(15))
6979 {
6980 u16ActiveWidthUsrEnable = BIT(15);
6981 }
6982 #endif
6983
6984 #if _ENABLE_SW_DS
6985 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
6986 {
6987 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK02_6C_L,u16VideoSize | u16ActiveWidthUsrEnable,DS_IP);
6988 }
6989 else
6990 #endif
6991 {
6992 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK02_6C_L, u16VideoSize | u16ActiveWidthUsrEnable, 0x87FF);
6993 }
6994 }
6995
Hal_SC_3D_SetSoftware_F1VBottomEndPosition(void * pInstance,MS_U16 u16VideoSize)6996 void Hal_SC_3D_SetSoftware_F1VBottomEndPosition(void *pInstance, MS_U16 u16VideoSize)
6997 {
6998 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
6999 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7000
7001 #if _ENABLE_SW_DS
7002 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7003 {
7004 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4F_L,u16VideoSize,DS_IP);
7005 }
7006 else
7007 #endif
7008 {
7009 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4F_L, u16VideoSize, 0x0FFF);
7010 }
7011 }
7012
Hal_SC_3D_SetSoftware_F2VBottomEndPosition(void * pInstance,MS_U16 u16VideoSize)7013 void Hal_SC_3D_SetSoftware_F2VBottomEndPosition(void *pInstance, MS_U16 u16VideoSize)
7014 {
7015 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7016 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7017
7018 #if _ENABLE_SW_DS
7019 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7020 {
7021 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4D_L,u16VideoSize,DS_IP);
7022 }
7023 else
7024 #endif
7025 {
7026 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4D_L, u16VideoSize, 0x0FFF);
7027 }
7028 }
7029
Hal_SC_3D_SetSoftware_F1VBottomStartPosition(void * pInstance,MS_U16 u16VideoSize)7030 void Hal_SC_3D_SetSoftware_F1VBottomStartPosition(void *pInstance, MS_U16 u16VideoSize)
7031 {
7032 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7033 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7034
7035 #if _ENABLE_SW_DS
7036 if(MDrv_XC_GetDynamicScalingStatus(pInstance))
7037 {
7038 Hal_SC_WriteSWDSCommand(pInstance,MAIN_WINDOW,REG_SC_BK57_4E_L,u16VideoSize,DS_IP);
7039 }
7040 else
7041 #endif
7042 {
7043 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK57_4E_L, u16VideoSize, 0x0FFF);
7044 }
7045 }
7046
Hal_SC_set_frcm_to_freeze(void * pInstance,MS_BOOL bEnable,SCALER_WIN eWindow)7047 void Hal_SC_set_frcm_to_freeze(void *pInstance, MS_BOOL bEnable, SCALER_WIN eWindow)
7048 {
7049 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7050 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7051 if (eWindow == MAIN_WINDOW)
7052 {
7053 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(0):0, BIT(0));
7054 }
7055 else
7056 {
7057 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_02_L, (bEnable==TRUE)?BIT(8):0, BIT(8));
7058 }
7059 }
7060
Hal_SC_SetOSDDetect(void * pInstance,MS_BOOL bEnable,MS_U32 Threhold)7061 E_APIXC_ReturnValue Hal_SC_SetOSDDetect(void *pInstance, MS_BOOL bEnable, MS_U32 Threhold)
7062 {
7063 MS_U16 u16Reg = 0;
7064 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7065 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7066 if(Threhold == 0)
7067 {
7068 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L, 0x0, (BIT(15)+BMASK(11:0)));
7069 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK25_2E_L, BIT(1), BIT(1));
7070
7071 }
7072 else
7073 {
7074 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK25_2E_L, 0x0, BIT(1));
7075 u16Reg = ((MS_U16)Threhold*2)|(bEnable << 15);
7076 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L, u16Reg, (BIT(15)+BMASK(11:0)));
7077 }
7078 return E_APIXC_RET_OK;
7079 }
7080
Hal_SC_GetOSDDetect(void * pInstance,MS_BOOL * pbOSD)7081 E_APIXC_ReturnValue Hal_SC_GetOSDDetect(void *pInstance, MS_BOOL *pbOSD)
7082 {
7083 MS_U16 u16Reg = 0;
7084 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7085 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7086
7087 u16Reg = SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK10_6A_L);
7088 *pbOSD = ((u16Reg&BIT(14))>>14);
7089 return E_APIXC_RET_OK;
7090 }
7091
Hal_SC_SetHDMI_Spliter(void * pInstance,XC_IP_SYNC_STATUS * sXC_Sync_Status,E_MUX_INPUTPORT enInputPort,SCALER_WIN eWindow)7092 void Hal_SC_SetHDMI_Spliter(void *pInstance,XC_IP_SYNC_STATUS *sXC_Sync_Status,E_MUX_INPUTPORT enInputPort ,SCALER_WIN eWindow)
7093 {
7094
7095 #if 0//SUPPORT_HDMI20
7096 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7097 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7098
7099 MS_U16 u16HDE_temp_size,u16HDE_size =0;
7100
7101 if((sXC_Sync_Status->u8SyncStatus & XC_MD_SYNC_LOSS) != XC_MD_SYNC_LOSS)
7102 {
7103 if(MDrv_HDMI_CheckHDMI20_Setting(enInputPort))
7104 {
7105 //printf("[%s][%d]HDMI 4K2K 2P mode\n", __FUNCTION__, __LINE__);
7106 if(eWindow == MAIN_WINDOW)
7107 W2BYTEMSK(0x102e02,0x0010,BMASK(7:4)); // ipmux sel=0xb
7108 else if(eWindow == SUB_WINDOW)
7109 W2BYTEMSK(0x102e02,0x0001,BMASK(3:0)); // ipmux sel=0xb
7110
7111 }
7112 else
7113 {
7114 //SUPPORT_HDMI20_420
7115 //printf("[%s][%d]HDMI 4K2K 2P mode\n", __FUNCTION__, __LINE__);
7116 //printf("[%s][%d]sXC_Sync_Status->u16Vtotal=%x, sXC_Sync_Status->u16Hperiod=%x\n",
7117 // __FUNCTION__, __LINE__, sXC_Sync_Status->u16Vtotal, sXC_Sync_Status->u16Hperiod);
7118 if((sXC_Sync_Status->u16Vtotal >= 0x8C0)
7119 &&(sXC_Sync_Status->u16Hperiod>= 0x50))
7120 {
7121 if((MDrv_HDMI_avi_infoframe_info(_BYTE_1)& 0x60) == 0x60)
7122 {
7123 //printf("@@#@@4K2K@60 420\n");
7124 // clkgen2
7125 W2BYTE(0x100a80,0x0004); // spt_l0 1: hdmi d: mhl
7126 // ipmux
7127 if(eWindow == MAIN_WINDOW)
7128 {
7129 W2BYTEMSK(0x102e02,0x00b0,BMASK(7:4)); // ipmux sel=0xb
7130 }
7131 else if(eWindow == SUB_WINDOW)
7132 {
7133 W2BYTEMSK(0x102e02,0x000b,BMASK(3:0)); // ipmux sel=0xb
7134 }
7135
7136 //BK40_SPT4k
7137 SC_W2BYTE(0, REG_SC_BK40_01_L,0x0000); // [3:0] reg_spt_ipmux_sel0
7138 // [11:8] reg_spt_ipmux_sel1
7139 SC_W2BYTE(0, REG_SC_BK40_03_L,0x0001); // [7] reg_spt_2p_oe_en [0] reg_spt_420_en
7140 SC_W2BYTE(0, REG_SC_BK40_04_L,0x0180); // [7] reg_spt_2p_oe_out_en [9] hsd_en
7141 // [8] reg_spt_2poe_out_sel 1'b0: dual ch eo in
7142 // 1'b1: dual ch LR in or 420
7143 SC_W2BYTE(0, REG_SC_BK40_30_L, 0x0003); // de_only
7144 SC_W2BYTE(0, REG_SC_BK40_0B_L, 0x0000); // gb_size
7145
7146 u16HDE_temp_size = MDrv_HDMI_GetHDE();
7147 //printf("[%s][%d]u16HDE_size=%u\n", __FUNCTION__, __LINE__,u16HDE_temp_size);
7148 if((u16HDE_temp_size >= 2028)&&(u16HDE_temp_size<= 2068))
7149 {
7150 u16HDE_size = 2048;
7151 }
7152 else //if((u16HDE_temp_size >= 1900)&&(u16HDE_temp_size<= 1940))
7153 {
7154 u16HDE_size = 1920;
7155 }
7156 SC_W2BYTE(0, REG_SC_BK40_08_L, u16HDE_size); // de_in_size
7157 SC_W2BYTE(0, REG_SC_BK40_0A_L, u16HDE_size); // de_out_with_gb_size
7158
7159 SC_W2BYTE(0, REG_SC_BK40_20_L, 0x0000); // ra
7160 SC_W2BYTE(0, REG_SC_BK40_21_L, u16HDE_size/2-2); //
7161 SC_W2BYTE(0, REG_SC_BK40_22_L, 0x0001);
7162 SC_W2BYTE(0, REG_SC_BK40_23_L, u16HDE_size/2-1);
7163
7164 SC_W2BYTE(0, REG_SC_BK40_24_L, 0x0000); // wa
7165 SC_W2BYTE(0, REG_SC_BK40_25_L, u16HDE_size/2-2);
7166 SC_W2BYTE(0, REG_SC_BK40_26_L, 0x0001);
7167 SC_W2BYTE(0, REG_SC_BK40_27_L, u16HDE_size/2-1);
7168 }
7169 else
7170 {
7171 //printf("@@#@@4K2K@30\n");
7172 /// for 4K2K@30Hz
7173 if(eWindow == MAIN_WINDOW)
7174 {
7175 W2BYTEMSK(0x102e02,0x0010,BMASK(7:4)); // ipmux sel=0xb
7176 }
7177 else if(eWindow == SUB_WINDOW)
7178 {
7179 W2BYTEMSK(0x102e02,0x0001,BMASK(3:0)); // ipmux sel=0xb
7180 }
7181 }
7182 }
7183 }
7184 }
7185 #endif
7186 }
7187
Hal_SC_Set_2pmode(void * pInstance,MS_BOOL benable_IP2p,MS_BOOL benable_OP2p,MS_BOOL benable_bypass_all_2p,SCALER_WIN eWindow)7188 void Hal_SC_Set_2pmode(void *pInstance,MS_BOOL benable_IP2p,MS_BOOL benable_OP2p,MS_BOOL benable_bypass_all_2p,SCALER_WIN eWindow)
7189 {
7190 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7191 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7192
7193 if(eWindow == MAIN_WINDOW)
7194 {
7195 SC_W2BYTEMSK(0, REG_SC_BK01_07_L,(benable_IP2p ? BIT(15):0), BIT(15));//reg_sprange_hdc_2p
7196 SC_W2BYTEMSK(0, REG_SC_BK20_01_L,(benable_OP2p ? BIT(1):0), BIT(1));//reg_opm_2p_mode
7197 SC_W2BYTEMSK(0, REG_SC_BK12_04_L,(benable_bypass_all_2p ? BIT(6):0), BIT(6));//reg_bypass_all_2p_f2
7198 }
7199 }
7200
MHal_SC_set_manual_rbank_switch_cnt(void * pInstance,MS_BOOL bEnable,MS_U16 u16SwitchCnt,SCALER_WIN eWindow)7201 void MHal_SC_set_manual_rbank_switch_cnt(void *pInstance, MS_BOOL bEnable, MS_U16 u16SwitchCnt, SCALER_WIN eWindow)
7202 {
7203 if (eWindow >= MAX_WINDOW)
7204 {
7205 printf("unsupported eWindow, return!\n");
7206 return;
7207 }
7208
7209 if( eWindow == MAIN_WINDOW)
7210 {
7211 // these two registers must be set simultaneously for this feature to work
7212 // frame rate convert dependence with IP write line count
7213 SC_W2BYTEMSK(0,REG_SC_BK12_05_L, bEnable? BIT(3):0, BIT(3));
7214 // frame rate convert dependence with IP write line count FULL
7215 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, bEnable? BIT(15):0, BIT(15));
7216
7217 // set specific line count according to when you will change rbank switch
7218 // this line count starts at VDE rising edge, ends at u16SwitchCnt
7219 SC_W2BYTEMSK(0,REG_SC_BK11_18_L, u16SwitchCnt, 0x1FFF);
7220 }
7221 else
7222 {
7223 // these two registers must be set simultaneously for this feature to work
7224 // frame rate convert dependence with IP write line count
7225 SC_W2BYTEMSK(0,REG_SC_BK12_45_L, bEnable? BIT(3):0, BIT(3));
7226 // frame rate convert dependence with IP write line count FULL
7227 SC_W2BYTEMSK(0,REG_SC_BK11_58_L, bEnable? BIT(15):0, BIT(15));
7228
7229 // set specific line count according to when you will change rbank switch
7230 // this line count starts at VDE rising edge, ends at u16SwitchCnt
7231 SC_W2BYTEMSK(0,REG_SC_BK11_58_L, u16SwitchCnt, 0x1FFF);
7232 }
7233 }
7234
7235 #ifdef SUPPORT_BWD
_HAL_SC_BWR_set_base_address(void * pInstance,MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex,SCALER_WIN eWindow)7236 static void _HAL_SC_BWR_set_base_address(void *pInstance, MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex, SCALER_WIN eWindow)
7237 {
7238 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7239 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7240 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7241 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7242
7243 E_XC_BWR_MEM_CONFIG u8Memtype = E_XC_BWR_MEM_CONFIG_1;
7244 E_XC_BWR_MEM_CFG_BPP_TYPE eBPPType = E_XC_BWR_MEM_CFG_BPP_24;
7245 for(u8Memtype=E_XC_BWR_MEM_CONFIG_1;u8Memtype<E_XC_BWR_MEM_CONFIG_Max;u8Memtype++)
7246 {
7247 if(u16MemCfgValue == gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].u16BWR_MEM_CFG_VALUE)
7248 {
7249 eBPPType = gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].eBitPerPixelType;
7250 break;
7251 }
7252 }
7253
7254 #ifdef UFO_XC_SUPPORT_DUAL_MIU
7255 if (IsEnableDualMode(eWindow))
7256 {
7257 //SCMI: IPM address 0
7258 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
7259 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
7260 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x48 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>00), 0xFFFF);
7261 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x49 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>16), 0x03FF);
7262 //SCMI: IPM address 1
7263 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
7264 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
7265 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x58 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>00), 0xFFFF);
7266 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x59 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>16), 0x03FF);
7267 //SCMI: OPM address 0
7268 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
7269 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
7270 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x68 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>00), 0xFFFF);
7271 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x69 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>16), 0x03FF);
7272 //SCMI: OPM address 1
7273 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
7274 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
7275 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x78 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0xFFFF);
7276 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x79 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x03FF);
7277 }
7278 else
7279 #endif
7280 {
7281 //SCMI: IPM address 0
7282 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
7283 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
7284 //SCMI: IPM address 1
7285 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
7286 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
7287 //SCMI: OPM address 0
7288 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
7289 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
7290 //SCMI: OPM address 1
7291 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
7292 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
7293 }
7294 }
7295
_HAL_SC_BWR_set_vlen(void * pInstance,SCALER_WIN eWindow)7296 void _HAL_SC_BWR_set_vlen(void * pInstance, SCALER_WIN eWindow)
7297 {
7298 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7299 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7300
7301 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7302 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7303 //update BWR Configuration vlen,IP 3D source: LA
7304 if(MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE)
7305 {
7306 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, BIT(15) | (gSrcInfo[eWindow].u16V_SizeAfterPreScaling/2), BIT(15) | 0x1FFF);
7307 }
7308 else
7309 {
7310 //update BWR Configuration vlen, VSD
7311 if(gSrcInfo[eWindow].bPreV_ScalingDown)
7312 {
7313 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, BIT(15) | gSrcInfo[eWindow].u16V_SizeAfterPreScaling, BIT(15) | 0x1FFF);
7314 }
7315 else
7316 {
7317 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3D_L, 0, BIT(15));
7318 }
7319 }
7320 //update BWR Configuration vlen,OP 3D output: LA
7321 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
7322 {
7323 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3E_L, BIT(15) | (gSrcInfo[eWindow].u16V_Length*2), BIT(15) | 0x1FFF);
7324 }
7325 else
7326 {
7327 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3E_L, 0, BIT(15));
7328 }
7329
7330 }
7331
_HAL_SC_BWR_set_3d_mode(void * pInstance,SCALER_WIN eWindow)7332 static void _HAL_SC_BWR_set_3d_mode(void * pInstance, SCALER_WIN eWindow)
7333 {
7334 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7335 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7336 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7337 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7338
7339 //BWR 422 to 420 set drop mode register
7340 if((MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE) && (gSrcInfo[eWindow].stCapWin.width > 1920))
7341 {
7342 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_38_L, BIT(7), BIT(7));
7343 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3A_L, 0, BIT(2));
7344 }
7345
7346 //BWR 422 to 420 set TB mode register
7347 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_TOP_BOTTOM)
7348 {
7349 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_3A_L, BIT(4), BIT(4));
7350 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_10_L, 0, BIT(11));
7351 }
7352
7353 //OP1 must turn off initial process
7354 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
7355 {
7356 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L,BIT(12) ,BIT(12));
7357 }
7358 else
7359 {
7360 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK20_11_L,0 ,BIT(12));
7361 }
7362 }
7363
_HAL_SC_BWR_set_base_address_burst(void * pInstance,MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex,SCALER_WIN eWindow)7364 static void _HAL_SC_BWR_set_base_address_burst(void *pInstance, MS_U16 u16MemCfgValue,MS_U16 u16MemCfgIndex, SCALER_WIN eWindow)
7365 {
7366 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7367 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7368 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7369 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7370
7371 E_XC_BWR_MEM_CONFIG u8Memtype = E_XC_BWR_MEM_CONFIG_1;
7372 E_XC_BWR_MEM_CFG_BPP_TYPE eBPPType = E_XC_BWR_MEM_CFG_BPP_24;
7373 for(u8Memtype=E_XC_BWR_MEM_CONFIG_1;u8Memtype<E_XC_BWR_MEM_CONFIG_Max;u8Memtype++)
7374 {
7375 if(u16MemCfgValue == gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].u16BWR_MEM_CFG_VALUE)
7376 {
7377 eBPPType = gSrcInfo[eWindow].Status2.stMemCfgMap[u8Memtype].eBitPerPixelType;
7378 break;
7379 }
7380 }
7381
7382 #ifdef UFO_XC_SUPPORT_DUAL_MIU
7383 if (IsEnableDualMode(eWindow))
7384 {
7385 //SCMI: IPM address 0
7386 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
7387 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
7388
7389 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x48 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>00), 0xFFFF);
7390 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x49 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase0>>16), 0x03FF);
7391
7392 //SCMI: IPM address 1
7393 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
7394 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
7395
7396 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x58 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>00), 0xFFFF);
7397 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x59 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_DNRBase1>>16), 0x03FF);
7398
7399 //SCMI: OPM address 0
7400 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
7401 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
7402
7403 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x68 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>00), 0xFFFF);
7404 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x69 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase0>>16), 0x03FF);
7405
7406 //SCMI: OPM address 1
7407 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
7408 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
7409
7410 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x78 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>00), 0xFFFF);
7411 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x79 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Right_OPMBase1>>16), 0x03FF);
7412 }
7413 else // Disbale dual
7414 #endif
7415 {
7416 //SCMI: IPM address 0
7417 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x40 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>00), 0xFFFF);
7418 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x41 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase0>>16), 0x03FF);
7419
7420 //SCMI: IPM address 1
7421 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x50 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>00), 0xFFFF);
7422 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x51 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_DNRBase1>>16), 0x03FF);
7423
7424 //SCMI: OPM address 0
7425 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x60 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>00), 0xFFFF);
7426 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x61 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase0>>16), 0x03FF);
7427
7428 //SCMI: OPM address 1
7429 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x70 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>00), 0xFFFF);
7430 MDrv_XC_MLoad_WriteCmd(pInstance, _PK_L_(0x46, (0x71 + u16MemCfgIndex * 2)), (MS_U16)(gSrcInfo[eWindow].Status2.stBWRBase[eBPPType].u32BWR_Miu_Left_OPMBase1>>16), 0x03FF);
7431 }
7432 }
7433
_HAL_SC_BWR_set_vlen_burst(void * pInstance,SCALER_WIN eWindow)7434 static void _HAL_SC_BWR_set_vlen_burst(void * pInstance, SCALER_WIN eWindow)
7435 {
7436 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7437 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7438
7439 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7440 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7441 //update BWR Configuration vlen,IP 3D source: LA
7442 if(MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE)
7443 {
7444 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, BIT(15) | (gSrcInfo[eWindow].u16V_SizeAfterPreScaling/2), BIT(15) | 0x1FFF);
7445 }
7446 else
7447 {
7448 //update BWR Configuration vlen, VSD
7449 if(gSrcInfo[eWindow].bPreV_ScalingDown)
7450 {
7451 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, BIT(15) | gSrcInfo[eWindow].u16V_SizeAfterPreScaling, BIT(15) | 0x1FFF);
7452 }
7453 else
7454 {
7455 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3D_L, 0, BIT(15));
7456 }
7457 }
7458 //update BWR Configuration vlen,OP 3D output: LA
7459 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
7460 {
7461 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3E_L, BIT(15) | (gSrcInfo[eWindow].u16V_Length*2), BIT(15) | 0x1FFF);
7462 }
7463 else
7464 {
7465 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3E_L, 0, BIT(15));
7466 }
7467 }
7468
_HAL_SC_BWR_set_3d_mode_burst(void * pInstance,SCALER_WIN eWindow)7469 static void _HAL_SC_BWR_set_3d_mode_burst(void * pInstance, SCALER_WIN eWindow)
7470 {
7471 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7472 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7473
7474 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7475 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7476
7477 //BWR 422 to 420 set drop mode register
7478 if((MDrv_XC_Get_3D_Input_Mode(pInstance, eWindow) == E_XC_3D_INPUT_LINE_ALTERNATIVE) && (gSrcInfo[eWindow].stCapWin.width > 1920))
7479 {
7480 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_38_L, BIT(7), BIT(7));
7481 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3A_L, 0, BIT(2));
7482 }
7483
7484 //BWR 422 to 420 set TB mode register
7485 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_TOP_BOTTOM)
7486 {
7487 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_3A_L, BIT(4),BIT(4));
7488 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_10_L, 0, BIT(11));
7489 }
7490
7491 //OP1 must turn off initial process
7492 if(MDrv_XC_Get_3D_Output_Mode(pInstance) == E_XC_3D_OUTPUT_LINE_ALTERNATIVE)
7493 {
7494 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, BIT(12), BIT(12));
7495 }
7496 else
7497 {
7498 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK20_11_L, 0, BIT(12));
7499 }
7500 }
7501 #endif
7502
HAL_SC_set_bwr_config_burst(void * pInstance,void * pstParam,SCALER_WIN eWindow)7503 MS_BOOL HAL_SC_set_bwr_config_burst(void *pInstance, void *pstParam, SCALER_WIN eWindow)
7504 {
7505 #ifdef SUPPORT_BWD
7506 MS_U16 u16BwrMemCfgTmp = 0;
7507 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7508 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7509 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7510 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7511
7512 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_17_L, 0xFFFF);
7513 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x000F) >> 0, E_XC_BWR_MME_CFG_INDEX_0, eWindow);
7514 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x00F0) >> 4, E_XC_BWR_MME_CFG_INDEX_1, eWindow);
7515 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0x0F00) >> 8, E_XC_BWR_MME_CFG_INDEX_2, eWindow);
7516 _HAL_SC_BWR_set_base_address_burst(pInstance, (u16BwrMemCfgTmp&0xF000) >> 12, E_XC_BWR_MME_CFG_INDEX_3, eWindow);
7517 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_16_L, 0xF);
7518 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_28_L, u16BwrMemCfgTmp, 0x0F);
7519 MDrv_XC_MLoad_WriteCmd(pInstance, REG_SC_BK46_29_L, u16BwrMemCfgTmp, 0x0F);
7520
7521 _HAL_SC_BWR_set_vlen_burst(pInstance, eWindow);
7522 _HAL_SC_BWR_set_3d_mode_burst(pInstance, eWindow);
7523
7524 MDrv_XC_MLoad_Fire(pInstance, TRUE);
7525 return TRUE;
7526 #else
7527 return FALSE;
7528 #endif
7529 }
7530
HAL_SC_set_bwr_config(void * pInstance,void * pstParam,SCALER_WIN eWindow)7531 MS_BOOL HAL_SC_set_bwr_config(void *pInstance, void *pstParam, SCALER_WIN eWindow)
7532 {
7533 #ifdef SUPPORT_BWD
7534 MS_U16 u16BwrMemCfgTmp = 0;
7535 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7536 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7537 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7538 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7539
7540 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_17_L, 0xFFFF);
7541 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x000F) >> 0, E_XC_BWR_MME_CFG_INDEX_0, eWindow);
7542 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x00F0) >> 4, E_XC_BWR_MME_CFG_INDEX_1, eWindow);
7543 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0x0F00) >> 8, E_XC_BWR_MME_CFG_INDEX_2, eWindow);
7544 _HAL_SC_BWR_set_base_address(pInstance, (u16BwrMemCfgTmp&0xF000) >> 12, E_XC_BWR_MME_CFG_INDEX_3, eWindow);
7545 u16BwrMemCfgTmp = SC_R2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_16_L, 0xF);
7546 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_28_L, u16BwrMemCfgTmp, 0x0F);
7547 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK46_29_L, u16BwrMemCfgTmp, 0x0F);
7548
7549 _HAL_SC_BWR_set_vlen(pInstance, eWindow);
7550 _HAL_SC_BWR_set_3d_mode(pInstance, eWindow);
7551 return TRUE;
7552 #else
7553 return FALSE;
7554 #endif
7555 }
7556
7557
7558 #ifdef UFO_XC_AUTO_DOWNLOAD
_Hal_XC_Set_Auto_Download_WorkMode(MS_U32 u32DeviceID,MS_U32 u32RegAddr,MS_U8 u8Bit,EN_XC_AUTODOWNLOAD_MODE enMode)7559 static E_APIXC_ReturnValue _Hal_XC_Set_Auto_Download_WorkMode(MS_U32 u32DeviceID, MS_U32 u32RegAddr, MS_U8 u8Bit, EN_XC_AUTODOWNLOAD_MODE enMode)
7560 {
7561 switch (enMode)
7562 {
7563 case E_XC_AUTODOWNLOAD_TRIGGER_MODE:
7564 {
7565 SC_W2BYTEMSK(u32DeviceID, u32RegAddr, 0, BIT(u8Bit));
7566 break;
7567 }
7568 case E_XC_AUTODOWNLOAD_ENABLE_MODE:
7569 {
7570 SC_W2BYTEMSK(u32DeviceID, u32RegAddr, 1 << u8Bit, BIT(u8Bit));
7571 break;
7572 }
7573 default:
7574 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
7575 }
7576
7577 return E_APIXC_RET_OK;
7578 }
7579
MHal_XC_AutoDownload_Config(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_PHY phyBaseAddr,EN_XC_AUTODOWNLOAD_MODE enMode)7580 E_APIXC_ReturnValue MHal_XC_AutoDownload_Config(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_PHY phyBaseAddr, EN_XC_AUTODOWNLOAD_MODE enMode)
7581 {
7582 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7583 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7584
7585 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7586 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7587
7588 switch(enClient)
7589 {
7590 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
7591 {
7592 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = 0xFFFFFFFF;
7593 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = 0;
7594 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].enMode = enMode;
7595
7596 //set baseaddr
7597 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_29_L, phyBaseAddr & 0x0000FFFF);
7598 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_2A_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7599
7600 //set work mode
7601 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L, 1, enMode);
7602 break;
7603 }
7604 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
7605 {
7606 //set baseaddr
7607 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_02_L, phyBaseAddr & 0x0000FFFF);
7608 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_03_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7609
7610 //set work mode
7611 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 3, enMode);
7612 break;
7613 }
7614 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
7615 {
7616 //set baseaddr
7617 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_12_L, phyBaseAddr & 0x0000FFFF);
7618 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_13_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7619
7620 //set work mode
7621 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 6, enMode);
7622 break;
7623 }
7624 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
7625 {
7626 //set baseaddr
7627 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_16_L, phyBaseAddr & 0x0000FFFF);
7628 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_17_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7629
7630 //set work mode
7631 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 15, enMode);
7632 break;
7633 }
7634 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
7635 {
7636 //set baseaddr
7637 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
7638 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7639
7640 //set work mode
7641 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
7642 break;
7643 }
7644 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
7645 {
7646 //set baseaddr
7647 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
7648 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7649
7650 //set work mode
7651 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
7652 break;
7653 }
7654 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
7655 {
7656 //set baseaddr
7657 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_04_L, phyBaseAddr & 0x0000FFFF);
7658 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_05_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7659
7660 //set work mode
7661 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 4, enMode);
7662 break;
7663 }
7664 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
7665 {
7666 //set baseaddr
7667 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_06_L, phyBaseAddr & 0x0000FFFF);
7668 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_07_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7669
7670 //set work mode
7671 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 5, enMode);
7672 break;
7673 }
7674 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
7675 {
7676 //set baseaddr
7677 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_23_L, phyBaseAddr & 0x0000FFFF);
7678 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_24_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7679
7680 //set work mode
7681 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_22_L, 1, enMode);
7682 break;
7683 }
7684 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
7685 {
7686 //set baseaddr
7687 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_33_L, phyBaseAddr & 0x0000FFFF);
7688 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_34_L, (phyBaseAddr >>16 & 0x0000FFFF), 0x07FF);
7689
7690 //set work mode
7691 _Hal_XC_Set_Auto_Download_WorkMode(psXCInstPri->u32DeviceID, REG_SC_BK67_32_L, 1, enMode);
7692 break;
7693 }
7694 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
7695 {
7696 return E_APIXC_RET_FAIL;
7697 }
7698 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
7699 {
7700 return E_APIXC_RET_FAIL;
7701 }
7702 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
7703 {
7704 return E_APIXC_RET_FAIL;
7705 }
7706 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
7707 default:
7708 {
7709 return E_APIXC_RET_FAIL;
7710 }
7711
7712 }
7713
7714 return E_APIXC_RET_OK;
7715 }
7716
MHal_XC_AutoDownload_Fire(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient)7717 E_APIXC_ReturnValue MHal_XC_AutoDownload_Fire(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient)
7718 {
7719 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7720 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7721
7722 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7723 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7724
7725 switch(enClient)
7726 {
7727 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
7728 {
7729 MS_PHY phyBaseAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].phyBaseAddr;
7730 MS_U32 u32Depth = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth;
7731 MS_VIRT* pVirtBaseAddr = (MS_VIRT *)MS_PA2KSEG1(phyBaseAddr);
7732 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
7733 MS_U32 u32StartAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr;
7734 pu8BaseAddr += 16 * u32StartAddr;
7735
7736 // set baseaddr
7737 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_29_L, (MS_PHY)MS_VA2PA((MS_VIRT)pu8BaseAddr) & 0x0000FFFF);
7738 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_2A_L, (MS_PHY)(MS_VA2PA((MS_VIRT)pu8BaseAddr) >> 16 & 0x0000FFFF), 0x07FF);
7739
7740 // set depth
7741 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_2B_L, u32Depth);
7742 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_2C_L, u32Depth);
7743
7744 // enable auto download
7745 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L, 1, BIT(0));
7746
7747 EN_XC_AUTODOWNLOAD_MODE enMode = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].enMode;
7748 if (enMode == E_XC_AUTODOWNLOAD_TRIGGER_MODE)
7749 {
7750 //check auto download done
7751 MS_U32 u32Delayms = 0;
7752 while(((SC_R2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK67_28_L) & 0x0001) != 0) && u32Delayms < 500)
7753 {
7754 MsOS_DelayTask(1);
7755 u32Delayms++;
7756 }
7757
7758 // clear buffer
7759 MS_U32 i = 0;
7760 for (i = 0; i < u32Depth; i++)
7761 {
7762 CLEAR_HDR_DATA_FORMAT_1(pu8BaseAddr + i * 16);
7763 }
7764 if (u32Delayms >= 500)
7765 {
7766 printf("Check auto download done timeout.\n");
7767 }
7768 }
7769
7770 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = 0xFFFFFFFF;
7771 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = 0;
7772 break;
7773 }
7774 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
7775 {
7776 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1, BIT(0));
7777 break;
7778 }
7779 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
7780 {
7781 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_11_L, 1, BIT(0));
7782 break;
7783 }
7784 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
7785 {
7786 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_11_L, 1 << 2, BIT(2));
7787 break;
7788 }
7789 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
7790 {
7791 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1 << 1, BIT(1));
7792 break;
7793 }
7794 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
7795 {
7796 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_21_L, 1, BIT(0));
7797 break;
7798 }
7799 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
7800 {
7801 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_21_L, 1 << 1, BIT(1));
7802 break;
7803 }
7804 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
7805 {
7806 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_01_L, 1 << 2, BIT(2));
7807 break;
7808 }
7809 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
7810 {
7811 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_22_L, 1, BIT(0));
7812 break;
7813 }
7814 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
7815 {
7816 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK67_32_L, 1, BIT(0));
7817 break;
7818 }
7819 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
7820 {
7821 return E_APIXC_RET_FAIL;
7822 }
7823 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
7824 {
7825 return E_APIXC_RET_FAIL;
7826 }
7827 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
7828 {
7829 return E_APIXC_RET_FAIL;
7830 }
7831 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
7832 default:
7833 {
7834 return E_APIXC_RET_FAIL;
7835 }
7836
7837 }
7838
7839 return E_APIXC_RET_OK;
7840 }
7841
_Hal_XC_Auto_Download_Format_Hdr_Data(void * pInstance,EN_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient,MS_U8 * pu8Data,MS_U32 u32Size,MS_U16 u16StartAddr)7842 static E_APIXC_ReturnValue _Hal_XC_Auto_Download_Format_Hdr_Data(void* pInstance,
7843 EN_XC_AUTODOWNLOAD_SUB_CLIENT enSubClient, MS_U8* pu8Data, MS_U32 u32Size, MS_U16 u16StartAddr)
7844 {
7845 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
7846 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
7847
7848 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
7849 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
7850
7851 MS_PHY phyBaseAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].phyBaseAddr;
7852 MS_U32 u32Depth = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth;
7853 MS_VIRT* pVirtBaseAddr = (MS_VIRT *)MS_PA2KSEG1(phyBaseAddr);
7854 unsigned int i = 0;
7855 MS_U32 u32Index = u16StartAddr;
7856 MS_U32 u32WriteNum = 0;
7857 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
7858 pu8BaseAddr += 16 * u16StartAddr;
7859
7860 // update start addr of DRAM
7861 MS_U32 u32StartAddr = pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr;
7862 if (u32StartAddr == 0xFFFFFFFF)
7863 {
7864 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = u16StartAddr;
7865 }
7866 else
7867 {
7868 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32StartAddr = u32StartAddr > u16StartAddr ? u16StartAddr : u32StartAddr;
7869 }
7870
7871 //format&write datas into DRAM
7872 for (i = 0; i < u32Size; )
7873 {
7874 switch (enSubClient)
7875 {
7876 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
7877 {
7878 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + i);
7879 if (u16Value & 0xF000)
7880 {
7881 printf("The %dth data is 0x%x, exceed max value, please check!!!\n", i + 1, u16Value);
7882 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
7883 }
7884 WRITE_TMO_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Value);
7885 i++;
7886 break;
7887 }
7888 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
7889 {
7890 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + i);
7891 WRITE_GAMMA_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Value);
7892 i++;
7893 break;
7894 }
7895 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
7896 {
7897 MS_U32 u32Value = *(((MS_U32 *)pu8Data) + i);
7898 if (u32Value & 0xFFF80000)
7899 {
7900 printf("The %dth data is 0x%x, exceed max value, please check!!!\n", i + 1, (unsigned int)u32Value);
7901 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
7902 }
7903 WRITE_DEGAMMA_DATA_FORMAT_1(pu8BaseAddr, u32Index, u32Value);
7904 i++;
7905 break;
7906 }
7907 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
7908 {
7909 MS_U16 u16RVal = *(((MS_U16 *)pu8Data) + i);
7910 MS_U16 u16GVal = *(((MS_U16 *)pu8Data) + i + 1);
7911 MS_U16 u16BVal = *(((MS_U16 *)pu8Data) + i + 2);
7912 MS_U16 u16Subindex = 0;
7913 if(i < _au32_3dlut_entry_num[0])
7914 {
7915 u16Subindex = 0;
7916 }
7917 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1]))
7918 {
7919 u16Subindex = 1;
7920 }
7921 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2]))
7922 {
7923 u16Subindex = 2;
7924 }
7925 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3]))
7926 {
7927 u16Subindex = 3;
7928 }
7929 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4]))
7930 {
7931 u16Subindex = 4;
7932 }
7933 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5]))
7934 {
7935 u16Subindex = 5;
7936 }
7937 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5] + _au32_3dlut_entry_num[6]))
7938 {
7939 u16Subindex = 6;
7940 }
7941 else if(i < (_au32_3dlut_entry_num[0] + _au32_3dlut_entry_num[1] + _au32_3dlut_entry_num[2] + _au32_3dlut_entry_num[3] + _au32_3dlut_entry_num[4] + _au32_3dlut_entry_num[5] + _au32_3dlut_entry_num[6] + _au32_3dlut_entry_num[7]))
7942 {
7943 u16Subindex = 7;
7944 }
7945 WRITE_3DLUT_DATA_FORMAT_1(pu8BaseAddr, u32Index, u16Subindex, u16RVal, u16GVal, u16BVal);
7946 i += 3;
7947 break;
7948 }
7949 }
7950 pu8BaseAddr += 16;
7951 u32WriteNum++;
7952 u32Index++;
7953 }
7954
7955 u32Depth = u32Depth > u32WriteNum ? u32Depth : u32WriteNum;
7956 pXCResourcePrivate->stdrvXC_Display._stClientInfo[E_XC_AUTODOWNLOAD_CLIENT_HDR].u32Depth = u32Depth;
7957
7958 #if DEBUG_HDR
7959 int j = 0;
7960 int l = 0;
7961
7962 printf("\n#####################Dump Input Data####################\n");
7963 for (j = 0; j < u32Size;)
7964 {
7965 printf("The %04dth row: ", u16StartAddr++);
7966 switch (enSubClient)
7967 {
7968 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
7969 {
7970 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + j);
7971 printf("%02X \n", u16Value);
7972 j++;
7973 break;
7974 }
7975 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
7976 {
7977 MS_U16 u16Value = *(((MS_U16 *)pu8Data) + j);
7978 printf("%02X \n", u16Value);
7979 j++;
7980 break;
7981 }
7982 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
7983 {
7984 MS_U32 u32Value = *(((MS_U32 *)pu8Data) + j);
7985 printf("%04X \n", u32Value);
7986 j++;
7987 break;
7988 }
7989 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
7990 {
7991 MS_U16 u16RVal = *(((MS_U16 *)pu8Data) + j);
7992 MS_U16 u16GVal = *(((MS_U16 *)pu8Data) + j + 1);
7993 MS_U16 u16BVal = *(((MS_U16 *)pu8Data) + j + 2);
7994 printf("%02X %02X %02X \n", u16RVal, u16GVal, u16BVal);
7995 j += 3;
7996 break;
7997 }
7998 }
7999 printf("\n");
8000 }
8001 printf("\n#####################Dump End####################\n\n");
8002
8003 int k = AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR;
8004 printf("\n#####################Dump DRAM Buffer####################\n");
8005 for (j = 0; j < k; j++)
8006 {
8007 MS_U8 *pu8BaseAddr = (MS_U8 *)pVirtBaseAddr;
8008 printf("\nThe %04dth row: ", j);
8009 for (l = 0; l < 16; l++)
8010 {
8011 switch (enSubClient)
8012 {
8013 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
8014 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
8015 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
8016 {
8017 printf("%02X ", *(pu8BaseAddr + 16 * j + l));
8018 break;
8019 }
8020 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
8021 {
8022 printf("%02X ", *(pu8BaseAddr + 16 * j + l));
8023 k = AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR;
8024 break;
8025 }
8026 }
8027 }
8028 }
8029 printf("\n#####################Dump End####################\n");
8030 #endif
8031
8032 return E_APIXC_RET_OK;
8033 }
8034
MHal_XC_AutoDownload_Write(void * pInstance,EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_U8 * pu8Data,MS_U32 u32Size,void * pParam)8035 E_APIXC_ReturnValue MHal_XC_AutoDownload_Write(void* pInstance, EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_U8* pu8Data, MS_U32 u32Size, void* pParam)
8036 {
8037 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8038 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8039
8040 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8041 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8042
8043 switch(enClient)
8044 {
8045 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
8046 {
8047 XC_AUTODOWNLOAD_FORMAT_INFO* pstFormatInfo = (XC_AUTODOWNLOAD_FORMAT_INFO *)pParam;
8048 MS_U16 u16StartAddr = 0;
8049 MS_U32 u32MaxSize = 0;
8050 switch (pstFormatInfo->enSubClient)
8051 {
8052 case E_XC_AUTODOWNLOAD_HDR_SUB_TMO:
8053 case E_XC_AUTODOWNLOAD_HDR_SUB_GAMMA:
8054 case E_XC_AUTODOWNLOAD_HDR_SUB_DEGAMMA:
8055 {
8056 u32MaxSize = AUTO_DOWNLOAD_HDR_TMO_SRAM_MAX_ADDR;
8057 break;
8058 }
8059 case E_XC_AUTODOWNLOAD_HDR_SUB_3DLUT:
8060 {
8061 u32MaxSize = AUTO_DOWNLOAD_HDR_3DLUT_SRAM_MAX_ADDR * 3;
8062 break;
8063 }
8064 default:
8065 {
8066 printf("Write auto download fail, invaild paramters, subClient: %d\n", pstFormatInfo->enSubClient);
8067 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8068 }
8069 }
8070 if (pstFormatInfo->bEnableRange == TRUE)
8071 {
8072 if (pstFormatInfo->u16StartAddr <= pstFormatInfo->u16EndAddr && pstFormatInfo->u16EndAddr < u32MaxSize
8073 && (pstFormatInfo->u16StartAddr + u32Size - 1) < u32MaxSize)
8074 {
8075 u16StartAddr = pstFormatInfo->u16StartAddr;
8076 }
8077 else
8078 {
8079 printf("Write auto download fail, invaild paramters, size: %d, addr range(enable, start, end) = (%d, %d, %d)\n",
8080 (unsigned int)u32Size, pstFormatInfo->bEnableRange, pstFormatInfo->u16StartAddr, pstFormatInfo->u16EndAddr);
8081 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8082 }
8083 }
8084 else
8085 {
8086 if (u32Size > u32MaxSize)
8087 {
8088 printf("Write auto download fail, invaild paramters, size: %d\n", (unsigned int)u32Size);
8089 return E_APIXC_RET_FAIL_INVALID_PARAMETER;
8090 }
8091 }
8092 return _Hal_XC_Auto_Download_Format_Hdr_Data(pInstance, pstFormatInfo->enSubClient, pu8Data, u32Size, u16StartAddr);
8093 }
8094 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
8095 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
8096 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
8097 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
8098 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
8099 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
8100 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
8101 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
8102 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
8103 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
8104 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
8105 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
8106 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
8107 default:
8108 {
8109 return E_APIXC_RET_FAIL;
8110 }
8111
8112 }
8113
8114 return E_APIXC_RET_OK;
8115 }
8116
MHal_XC_GetAutoDownloadCaps(EN_XC_AUTODOWNLOAD_CLIENT enClient,MS_BOOL * pbSupported)8117 E_APIXC_ReturnValue MHal_XC_GetAutoDownloadCaps(EN_XC_AUTODOWNLOAD_CLIENT enClient, MS_BOOL *pbSupported)
8118 {
8119 switch(enClient)
8120 {
8121 case E_XC_AUTODOWNLOAD_CLIENT_HDR:
8122 case E_XC_AUTODOWNLOAD_CLIENT_OP2GAMMA:
8123 case E_XC_AUTODOWNLOAD_CLIENT_FRCOP2GAMMA:
8124 case E_XC_AUTODOWNLOAD_CLIENT_XVYCC:
8125 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE1:
8126 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE2:
8127 case E_XC_AUTODOWNLOAD_CLIENT_ODTABLE3:
8128 case E_XC_AUTODOWNLOAD_CLIENT_DEMURA:
8129 case E_XC_AUTODOWNLOAD_CLIENT_OP2LUT:
8130 case E_XC_AUTODOWNLOAD_CLIENT_T3D_0:
8131 case E_XC_AUTODOWNLOAD_CLIENT_T3D_1:
8132 case E_XC_AUTODOWNLOAD_CLIENT_FRCSPTPOPM:
8133 case E_XC_AUTODOWNLOAD_CLIENT_FOOPM:
8134 {
8135 *pbSupported = TRUE;
8136 break;
8137 }
8138 case E_XC_AUTODOWNLOAD_CLIENT_MAX:
8139 default:
8140 {
8141 *pbSupported = FALSE;
8142 break;
8143 }
8144
8145 }
8146
8147 return E_APIXC_RET_OK;
8148 }
8149 #endif
8150
8151 #ifdef UFO_XC_HDR
8152 #if (UFO_XC_HDR_VERSION == 2)
_Hal_XC_HDR_UpdateDMAMode(void * pInstance)8153 static E_APIXC_ReturnValue _Hal_XC_HDR_UpdateDMAMode(void* pInstance)
8154 {
8155 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8156 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8157
8158 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8159 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8160
8161 EN_XC_HDR_COLOR_FORMAT enColorFormat = pXCResourcePrivate->stdrvXC_Display._enColorFormat;
8162 EN_XC_HDR_DMA_MODE enMode = pXCResourcePrivate->stdrvXC_Display._stDMAConfigInfo.enMode;
8163
8164 switch (enColorFormat)
8165 {
8166 case E_XC_HDR_COLOR_YUV422:
8167 {
8168 // set dma mode
8169 if (enMode == E_XC_HDR_DMA_MODE_12BIT)
8170 {
8171 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 0, 0x0003);
8172 }
8173 else if (enMode == E_XC_HDR_DMA_MODE_8BIT)
8174 {
8175 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 2, 0x0003);
8176 }
8177 else if (enMode == E_XC_HDR_DMA_MODE_10BIT)
8178 {
8179 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 3, 0x0003);
8180 }
8181 break;
8182 }
8183 case E_XC_HDR_COLOR_YUV444:
8184 {
8185 if (enMode == E_XC_HDR_DMA_MODE_10BIT)
8186 {
8187 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_01_L, 1, 0x0003);
8188 }
8189 break;
8190 }
8191 case E_XC_HDR_COLOR_YUV420:
8192 case E_XC_HDR_COLOR_RGB:
8193 default:
8194 {
8195 break;
8196 }
8197 }
8198
8199 return E_APIXC_RET_OK;
8200 }
8201
MHal_XC_HDR_Control(void * pInstance,EN_XC_HDR_CTRL_TYPE enCtrlType,void * pParam)8202 E_APIXC_ReturnValue MHal_XC_HDR_Control(void* pInstance, EN_XC_HDR_CTRL_TYPE enCtrlType, void *pParam)
8203 {
8204 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8205 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8206
8207 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8208 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8209
8210 switch(enCtrlType)
8211 {
8212 case E_XC_HDR_CTRL_CONFIG_DMA:
8213 case E_XC_HDR_CTRL_SET_COLOR_FORMAT:
8214 {
8215 _Hal_XC_HDR_UpdateDMAMode(pInstance);
8216 break;
8217 }
8218 case E_XC_HDR_CTRL_INIT_DMA:
8219 {
8220 MS_U8 u8MIUSel = 0;
8221 XC_HDR_DMA_INIT_INFO stDMAInitInfo = *(XC_HDR_DMA_INIT_INFO *)pParam;
8222 _phy_to_miu_offset(u8MIUSel, stDMAInitInfo.phyBaseAddr, stDMAInitInfo.phyBaseAddr);
8223 if (stDMAInitInfo.u32Size != 0)
8224 {
8225 // set IPM/OPM addr
8226 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_08_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
8227 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_09_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
8228 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_10_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
8229 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_11_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
8230 // set miu
8231 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_05_L, u8MIUSel << 4, BMASK(5:4));
8232 // set limit addr
8233 // enable limit
8234 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_50_L, 1, BIT(0));
8235 // min addr
8236 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_52_L, stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD);
8237 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_53_L, (stDMAInitInfo.phyBaseAddr / BYTE_PER_WORD) >> 16, 0x01FF);
8238 // max addr
8239 SC_W2BYTE(psXCInstPri->u32DeviceID, REG_SC_BK42_54_L, (stDMAInitInfo.phyBaseAddr + stDMAInitInfo.u32Size) / BYTE_PER_WORD - 1);
8240 SC_W2BYTEMSK(psXCInstPri->u32DeviceID, REG_SC_BK42_55_L, ((stDMAInitInfo.phyBaseAddr + stDMAInitInfo.u32Size) / BYTE_PER_WORD - 1) >> 16, 0x01FF);
8241 }
8242 break;
8243 }
8244 case E_XC_HDR_CTRL_ENABLE:
8245 case E_XC_HDR_CTRL_SET_TYPE:
8246 case E_XC_HDR_CTRL_SET_3DLUT:
8247 case E_XC_HDR_CTRL_SET_OTT_SHARE_MEMORY:
8248 case E_XC_HDR_CTRL_SET_OPEN_METADATA:
8249 default:
8250 {
8251 break;
8252 }
8253 }
8254
8255 return E_APIXC_RET_OK;
8256 }
8257
MHal_XC_HDR_GetCaps(void * pInstance,XC_HDR_SUPPORTED_CAPS * pstHDRCaps)8258 E_APIXC_ReturnValue MHal_XC_HDR_GetCaps(void *pInstance, XC_HDR_SUPPORTED_CAPS *pstHDRCaps)
8259 {
8260 EN_XC_HDR_TYPE enHDRType = pstHDRCaps->enHDRType;
8261
8262 switch (enHDRType)
8263 {
8264 case E_XC_HDR_TYPE_OPEN:
8265 {
8266 pstHDRCaps->bSupported = TRUE;
8267 break;
8268 }
8269 case E_XC_HDR_TYPE_DOLBY:
8270 {
8271 if (MDrv_AUTH_IPCheck(IPAUTH_DOLBY_HDR_PIN) == TRUE)
8272 {
8273 pstHDRCaps->bSupported = TRUE;
8274 }
8275 else
8276 {
8277 pstHDRCaps->bSupported = FALSE;
8278 }
8279 break;
8280 }
8281 case E_XC_HDR_TYPE_TECHNICOLOR:
8282 {
8283 pstHDRCaps->bSupported = FALSE;
8284 break;
8285 }
8286 case E_XC_HDR_TYPE_HLG:
8287 {
8288 pstHDRCaps->bSupported = FALSE;
8289 break;
8290 }
8291 default:
8292 {
8293 pstHDRCaps->bSupported = FALSE;
8294 }
8295 }
8296
8297 pstHDRCaps->s32MaxLuminanceData = -1;
8298 pstHDRCaps->s32MinLuminanceData = -1;
8299 pstHDRCaps->s32MaxFrameAveLumiance = -1;
8300
8301 return E_APIXC_RET_OK;
8302 }
8303 #endif
8304 #endif
8305
MHal_XC_Get_FB_Level(void * pInstance,MS_WINDOW_TYPE * pstCropWin,MS_WINDOW_TYPE * pstDispWin,MS_BOOL bInterlace,MS_U16 * pu16HSize,MS_U16 * pu16VSize)8306 E_XC_FB_LEVEL MHal_XC_Get_FB_Level(void* pInstance, MS_WINDOW_TYPE* pstCropWin, MS_WINDOW_TYPE* pstDispWin, MS_BOOL bInterlace, MS_U16* pu16HSize, MS_U16* pu16VSize)
8307 {
8308 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8309 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8310 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8311 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8312 E_XC_FB_LEVEL ret = E_XC_FB_LEVEL_NUM;
8313
8314 if(E_XC_DEVICE0 == psXCInstPri->u32DeviceID)
8315 {
8316 MS_BOOL bEnablePreH = FALSE;
8317 MS_BOOL bEnablePreV = FALSE;
8318 //-----------------------------------------
8319 // Vertical
8320 //--------------------------------
8321
8322 if((pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Height > 2000)
8323 && (pXCResourcePrivate->stdrvXC_MVideo_Context.g_XC_InitData.stPanelInfo.u16Width > 3200))
8324 {
8325 // Need force pre-scaling if disp.V size < 88% of crop.V size.
8326 if((pstDispWin->height * 25) < (pstCropWin->height * 22))
8327 {
8328 bEnablePreV = TRUE;
8329 }
8330
8331 if((pstDispWin->width * 25) < (pstCropWin->width * 22))
8332 {
8333 bEnablePreH = TRUE;
8334 }
8335 }
8336
8337 if(bEnablePreH || bEnablePreV)
8338 {
8339 ret = E_XC_FB_LEVEL_FB;
8340 }
8341 else
8342 {
8343 ret = E_XC_FB_LEVEL_FBL;
8344 }
8345 }
8346 return ret;
8347 }
8348
Hal_SC_add_dram_to_shm(void * pInstance,SCALER_WIN eWindow,MS_U32 u32address,MS_U32 u32length)8349 void Hal_SC_add_dram_to_shm(void *pInstance,SCALER_WIN eWindow,MS_U32 u32address,MS_U32 u32length)
8350 {
8351 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8352 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8353 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8354 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8355
8356 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_cnt].address = u32address;
8357 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_cnt].length = u32length;
8358 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_cnt++;
8359 }
Hal_SC_add_reg_to_shm(void * pInstance,SCALER_WIN eWindow,MS_U32 u32_bk,MS_U16 u16_value,MS_U16 u16_mask)8360 void Hal_SC_add_reg_to_shm(void *pInstance,SCALER_WIN eWindow,MS_U32 u32_bk,MS_U16 u16_value,MS_U16 u16_mask)
8361 {
8362 MS_U32 u32offset = 0;
8363 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8364 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8365 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8366 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8367
8368 u32offset = _XC_Device_Offset[psXCInstPri->u32DeviceID];
8369
8370 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_cnt].bk = REG_SCALER_BASE + u32_bk + (u32offset << 8);
8371 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_cnt].value = u16_value;
8372 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_data[pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_cnt].mask = u16_mask;
8373 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].regs_cnt ++;
8374 }
8375
Hal_SC_secure_lock(void * pInstance,SCALER_WIN eWindow,MS_U32 u32SecureDMA,MS_U32 u32OperationMode)8376 MS_BOOL Hal_SC_secure_lock(void *pInstance, SCALER_WIN eWindow, MS_U32 u32SecureDMA, MS_U32 u32OperationMode)
8377 {
8378 #ifdef MSOS_TYPE_OPTEE
8379 MS_PHY phy_dramAddr = 0;
8380 MS_U8 u8i = 0;
8381 #endif
8382 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8383 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8384 #ifndef MSOS_TYPE_OPTEE
8385 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8386 #else
8387 XC_RESOURCE_PRIVATE_FOR_TEE* pXCResourcePrivate = NULL;
8388 #endif
8389 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8390 #ifdef MSOS_TYPE_OPTEE
8391 if (u32SecureDMA == 0)
8392 {
8393 MDrv_Seal_ChangeIPSecureDMAAbillity(MODULE_XC, 0 , FALSE);
8394 }
8395 for (u8i = 0; u8i < pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_cnt; u8i++)
8396 {
8397 phy_dramAddr = (MS_PHY) pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[u8i].address;
8398 if (u8i >= OP_TEE_XC_DRAM_MAX_CNT)
8399 {
8400 printf("dram cnt overflow\n");
8401 break;
8402 }
8403 if (u32OperationMode == 1)
8404 {
8405 if(MDrv_Seal_SetSecureRange(phy_dramAddr, pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[u8i].length , TRUE) == FALSE)
8406 {
8407 return FALSE;
8408 }
8409 }
8410 else if (u32OperationMode == 0)
8411 {
8412 if(MDrv_Seal_SetSecureRange(phy_dramAddr , pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[u8i].length , FALSE) == FALSE)
8413 {
8414 return FALSE;
8415 }
8416 }
8417 }
8418 if (u32SecureDMA == 1)
8419 {
8420 MDrv_Seal_ChangeIPSecureDMAAbillity(MODULE_XC, 0 , TRUE);
8421 }
8422 if (u32OperationMode == 1)
8423 {
8424 MDrv_Seal_SecureSlaveSet(E_SEAL_SC0_PROT_NONPM, TRUE);
8425 MDrv_Seal_BufferLock(E_SEAL_SC_WP_SCM_M, TRUE);
8426 }
8427 else if (u32OperationMode == 0)
8428 {
8429 MDrv_Seal_SecureSlaveSet(E_SEAL_SC0_PROT_NONPM, FALSE);
8430 MDrv_Seal_BufferLock(E_SEAL_SC_WP_SCM_M, FALSE);
8431 }
8432 pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].isEnable=u32OperationMode; //Update OPtee status for tee side
8433 #endif
8434 return TRUE;
8435
8436 }
Hal_SC_update_to_shm(void * pInstance,SCALER_WIN eWindow)8437 void Hal_SC_update_to_shm(void *pInstance, SCALER_WIN eWindow)
8438 {
8439 XC_INSTANCE_PRIVATE *psXCInstPri = NULL;
8440 UtopiaInstanceGetPrivate(pInstance, (void**)&psXCInstPri);
8441 XC_RESOURCE_PRIVATE* pXCResourcePrivate = NULL;
8442 UtopiaResourceGetPrivate(g_pXCResource[_XC_SELECT_INTERNAL_VARIABLE(psXCInstPri->u32DeviceID)],(void**)(&pXCResourcePrivate));
8443 if (eWindow == MAIN_WINDOW)
8444 {
8445 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK0D_38_L, (BIT(0) | BIT(4)), (BIT(0) | BIT(4)));
8446 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_08_L, ((pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address/BYTE_PER_WORD) & 0xFFFF), 0xFFFF);
8447 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_09_L, ((pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address/BYTE_PER_WORD) >> 16), 0xFFFF);
8448 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_1C_L, 0x0000, 0xFFFF);
8449 }
8450 else if (eWindow == SUB_WINDOW)
8451 {
8452 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK0D_38_L, (BIT(1) | BIT(6)), (BIT(1) | BIT(6)));
8453 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_48_L, ((pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address/BYTE_PER_WORD) & 0xFFFF), 0xFFFF);
8454 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_49_L, ((pXCResourcePrivate->sthal_Optee.op_tee_xc[eWindow].drams_data[0].address/BYTE_PER_WORD) >> 16), 0xFFFF);
8455 Hal_SC_add_reg_to_shm(pInstance, eWindow, REG_SC_BK12_5C_L, 0x0000, 0xFFFF);
8456 }
8457 }
8458
8459 #ifdef UFO_XC_SUPPORT_2STEP_SCALING
MHal_XC_CheckHwSupport2StepScaling(void)8460 MS_BOOL MHal_XC_CheckHwSupport2StepScaling(void)
8461 {
8462 return TRUE;
8463 }
8464 #endif
8465
8466 #undef MHAL_SC_C
8467