1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_TBL_H_ 80 #define _LPLL_TBL_H_ 81 82 #define LPLL_REG_NUM 31 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_TTL_100to150MHz, //0 87 E_PNL_SUPPORTED_LPLL_TTL_75to100MHz, //1 88 E_PNL_SUPPORTED_LPLL_TTL_75to75MHz, //2 89 90 E_PNL_SUPPORTED_LPLL_LVDS_1CH_55to80MHz, //3 91 E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to55MHz, //4 92 E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to40MHz, //5 93 94 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz, //6 95 E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to50MHz, //7 96 E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to37_5MHz, //8 97 98 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz, //9 99 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to100MHz, //10 100 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to75MHz, //11 101 102 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz, //12 103 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to100MHz, //13 104 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to75MHz, //14 105 106 E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to80MHz, //15 107 E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to40MHz, //16 108 109 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to150MHz, //17 110 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to75MHz, //18 111 112 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to150MHz, //19 113 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to75MHz, //20 114 115 E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz, //21 116 E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to66_67MHz, //22 117 E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to40MHz, //23 118 119 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_133_33to150MHz, //24 120 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to133_33MHz, //25 121 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to75MHz, //26 122 123 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_133_33to150MHz, //27 124 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to133_33MHz, //28 125 E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to75MHz, //29 126 127 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_115to150MHz, //30 128 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to115MHz, //31 129 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to75MHz, //32 130 131 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_115to150MHz, //33 132 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to115MHz, //34 133 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to75MHz, //35 134 135 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to300MHz, //36 136 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to150MHz, //37 137 138 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_230to300MHz, //38 139 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to230MHz, //39 140 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to150MHz, //40 141 142 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to300MHz, //41 143 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to150MHz, //42 144 145 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_200to300MHz, //43 146 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to200MHz, //44 147 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to150MHz, //45 148 149 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to300MHz, //46 150 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to150MHz, //47 151 152 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to300MHz, //48 153 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to150MHz, //49 154 155 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_240to300MHz, //50 156 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to240MHz, //51 157 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to150MHz, //52 158 159 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz, //53 160 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz, //54 161 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz, //55 162 163 E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to300MHz, //56 164 E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to150MHz, //57 165 166 E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to300MHz, //58 167 E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to150MHz, //59 168 169 E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz, //60 170 E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz, //61 171 172 E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz, //62 173 E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz, //63 174 175 E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to300MHz, //64 176 E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to150MHz, //65 177 178 E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_200to300MHz, //66 179 E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to200MHz, //67 180 E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz, //68 181 182 E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz, //69 183 E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz, //70 184 185 E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz, //71 186 E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz, //72 187 188 E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz, //73 189 E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz, //74 190 E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz, //75 191 192 E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz, //76 193 E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz, //77 194 E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz, //78 195 196 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz, //79 197 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz, //80 198 199 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz, //81 200 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz, //82 201 202 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz, //83 203 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz, //84 204 205 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz, //85 206 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz, //86 207 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz, //87 208 209 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz, //88 210 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz, //89 211 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz, //90 212 213 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz, //91 214 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz, //92 215 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz, //93 216 217 E_PNL_SUPPORTED_LPLL_MAX, //94 218 } E_PNL_SUPPORTED_LPLL_TYPE; 219 220 typedef struct 221 { 222 MS_U8 address; 223 MS_U16 value; 224 MS_U16 mask; 225 }TBLStruct,*pTBLStruct; 226 227 TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= 228 { 229 { //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 230 //Address,Value,Mask 231 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 232 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 233 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 234 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 235 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 236 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 237 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 238 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 239 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 240 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 241 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 242 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 243 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 244 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 245 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 246 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 247 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 248 {0x33,0x0020,0x0020},//reg_lpll2_pd 249 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 250 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 251 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 252 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 253 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 254 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 255 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 256 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 257 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 258 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 259 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 260 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 261 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 262 }, 263 264 { //E_PNL_SUPPORTED_LPLL_TTL_75to100MHz NO.1 265 //Address,Value,Mask 266 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 267 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 268 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 269 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 270 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 271 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 272 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 273 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 274 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 275 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 276 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 277 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 278 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 279 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 280 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 281 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 282 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 283 {0x33,0x0020,0x0020},//reg_lpll2_pd 284 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 285 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 286 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 287 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 288 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 289 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 290 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 291 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 292 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 293 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 294 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 295 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 296 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 297 }, 298 299 { //E_PNL_SUPPORTED_LPLL_TTL_75to75MHz NO.2 300 //Address,Value,Mask 301 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 302 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 303 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 304 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 305 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 306 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 307 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 308 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 309 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 310 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 311 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 312 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 313 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 314 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 315 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 316 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 317 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 318 {0x33,0x0020,0x0020},//reg_lpll2_pd 319 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 320 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 321 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 322 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 323 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 324 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 325 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 326 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 327 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 328 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 329 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 330 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 331 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 332 }, 333 334 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_55to80MHz NO.3 335 //Address,Value,Mask 336 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 337 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 338 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 339 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 340 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 341 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 342 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 343 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 344 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 345 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 346 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 347 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 348 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 349 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 350 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 351 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 352 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 353 {0x33,0x0020,0x0020},//reg_lpll2_pd 354 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 355 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 356 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 357 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 358 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 359 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 360 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 361 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 362 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 363 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 364 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 365 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 366 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 367 }, 368 369 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to55MHz NO.4 370 //Address,Value,Mask 371 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 372 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 373 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 374 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 375 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 376 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 377 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 378 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 379 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 380 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 381 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 382 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 383 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 384 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 385 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 386 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 387 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 388 {0x33,0x0020,0x0020},//reg_lpll2_pd 389 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 390 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 391 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 392 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 393 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 394 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 395 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 396 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 397 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 398 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 399 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 400 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 401 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 402 }, 403 404 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to40MHz NO.5 405 //Address,Value,Mask 406 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 407 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 408 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 409 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 410 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 411 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 412 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 413 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 414 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 415 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 416 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 417 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 418 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 419 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 420 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 421 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 422 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 423 {0x33,0x0020,0x0020},//reg_lpll2_pd 424 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 425 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 426 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 427 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 428 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 429 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 430 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 431 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 432 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 433 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 434 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 435 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 436 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 437 }, 438 439 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.6 440 //Address,Value,Mask 441 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 442 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 443 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 444 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 445 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 446 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 447 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 448 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 449 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 450 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 451 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 452 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 453 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 454 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 455 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 456 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 457 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 458 {0x33,0x0020,0x0020},//reg_lpll2_pd 459 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 460 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 461 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 462 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 463 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 464 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 465 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 466 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 467 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 468 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 469 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 470 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 471 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 472 }, 473 474 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to50MHz NO.7 475 //Address,Value,Mask 476 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 477 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 478 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 479 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 480 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 481 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 482 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 483 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 484 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 485 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 486 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 487 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 488 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 489 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 490 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 491 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 492 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 493 {0x33,0x0020,0x0020},//reg_lpll2_pd 494 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 495 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 496 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 497 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 498 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 499 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 500 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 501 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 502 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 503 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 504 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 505 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 506 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 507 }, 508 509 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to37_5MHz NO.8 510 //Address,Value,Mask 511 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 512 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 513 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 514 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 515 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 516 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 517 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 518 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 519 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 520 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 521 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 522 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 523 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 524 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 525 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 526 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 527 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 528 {0x33,0x0020,0x0020},//reg_lpll2_pd 529 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 530 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 531 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 532 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 533 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 534 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 535 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 536 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 537 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 538 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 539 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 540 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 541 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 542 }, 543 544 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.9 545 //Address,Value,Mask 546 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 547 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 548 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 549 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 550 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 551 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 552 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 553 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 554 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 555 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 556 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 557 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 558 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 559 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 560 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 561 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 562 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 563 {0x33,0x0020,0x0020},//reg_lpll2_pd 564 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 565 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 566 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 567 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 568 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 569 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 570 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 571 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 572 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 573 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 574 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 575 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 576 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 577 }, 578 579 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to100MHz NO.10 580 //Address,Value,Mask 581 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 582 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 583 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 584 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 585 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 586 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 587 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 588 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 589 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 590 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 591 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 592 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 593 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 594 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 595 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 596 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 597 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 598 {0x33,0x0020,0x0020},//reg_lpll2_pd 599 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 600 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 601 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 602 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 603 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 604 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 605 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 606 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 607 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 608 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 609 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 610 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 611 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 612 }, 613 614 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to75MHz NO.11 615 //Address,Value,Mask 616 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 617 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 618 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 619 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 620 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 621 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 622 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 623 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 624 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 625 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 626 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 627 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 628 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 629 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 630 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 631 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 632 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 633 {0x33,0x0020,0x0020},//reg_lpll2_pd 634 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 635 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 636 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 637 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 638 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 639 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 640 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 641 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 642 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 643 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 644 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 645 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 646 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 647 }, 648 649 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.12 650 //Address,Value,Mask 651 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 652 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 653 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 654 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 655 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 656 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 657 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 658 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 659 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 660 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 661 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 662 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 663 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 664 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 665 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 666 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 667 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 668 {0x33,0x0020,0x0020},//reg_lpll2_pd 669 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 670 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 671 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 672 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 673 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 674 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 675 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 676 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 677 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 678 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 679 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 680 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 681 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 682 }, 683 684 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to100MHz NO.13 685 //Address,Value,Mask 686 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 687 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 688 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 689 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 690 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 691 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 692 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 693 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 694 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 695 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 696 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 697 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 698 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 699 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 700 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 701 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 702 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 703 {0x33,0x0020,0x0020},//reg_lpll2_pd 704 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 705 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 706 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 707 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 708 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 709 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 710 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 711 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 712 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 713 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 714 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 715 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 716 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 717 }, 718 719 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to75MHz NO.14 720 //Address,Value,Mask 721 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 722 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 723 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 724 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 725 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 726 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 727 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 728 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 729 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 730 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 731 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 732 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 733 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 734 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 735 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 736 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 737 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 738 {0x33,0x0020,0x0020},//reg_lpll2_pd 739 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 740 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 741 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 742 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 743 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 744 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 745 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 746 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 747 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 748 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 749 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 750 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 751 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 752 }, 753 754 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to80MHz NO.15 755 //Address,Value,Mask 756 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 757 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 758 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 759 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 760 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 761 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 762 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 763 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 764 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 765 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 766 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 767 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 768 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 769 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 770 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 771 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 772 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 773 {0x33,0x0020,0x0020},//reg_lpll2_pd 774 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 775 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 776 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 777 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 778 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 779 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 780 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 781 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 782 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 783 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 784 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 785 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 786 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 787 }, 788 789 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to40MHz NO.16 790 //Address,Value,Mask 791 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 792 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 793 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 794 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 795 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 796 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 797 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 798 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 799 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 800 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 801 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 802 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 803 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 804 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 805 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 806 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 807 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 808 {0x33,0x0020,0x0020},//reg_lpll2_pd 809 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 810 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 811 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 812 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 813 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 814 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 815 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 816 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 817 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 818 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 819 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 820 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 821 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 822 }, 823 824 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to150MHz NO.17 825 //Address,Value,Mask 826 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 827 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 828 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 829 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 830 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 831 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 832 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 833 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 834 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 835 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 836 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 837 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 838 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 839 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 840 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 841 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 842 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 843 {0x33,0x0020,0x0020},//reg_lpll2_pd 844 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 845 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 846 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 847 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 848 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 849 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 850 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 851 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 852 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 853 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 854 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 855 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 856 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 857 }, 858 859 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to75MHz NO.18 860 //Address,Value,Mask 861 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 862 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 863 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 864 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 865 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 866 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 867 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 868 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 869 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 870 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 871 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 872 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 873 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 874 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 875 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 876 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 877 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 878 {0x33,0x0020,0x0020},//reg_lpll2_pd 879 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 880 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 881 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 882 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 883 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 884 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 885 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 886 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 887 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 888 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 889 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 890 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 891 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 892 }, 893 894 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to150MHz NO.19 895 //Address,Value,Mask 896 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 897 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 898 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 899 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 900 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 901 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 902 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 903 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 904 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 905 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 906 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 907 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 908 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 909 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 910 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 911 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 912 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 913 {0x33,0x0020,0x0020},//reg_lpll2_pd 914 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 915 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 916 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 917 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 918 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 919 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 920 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 921 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 922 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 923 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 924 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 925 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 926 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 927 }, 928 929 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to75MHz NO.20 930 //Address,Value,Mask 931 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 932 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 933 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 934 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 935 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 936 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 937 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 938 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 939 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 940 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 941 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 942 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 943 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 944 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 945 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 946 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 947 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 948 {0x33,0x0020,0x0020},//reg_lpll2_pd 949 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 950 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 951 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 952 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 953 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 954 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 955 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 956 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 957 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 958 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 959 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 960 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 961 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 962 }, 963 964 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz NO.21 965 //Address,Value,Mask 966 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 967 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 968 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 969 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 970 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 971 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 972 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 973 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 974 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 975 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 976 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 977 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 978 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 979 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 980 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 981 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 982 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 983 {0x33,0x0020,0x0020},//reg_lpll2_pd 984 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 985 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 986 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 987 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 988 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 989 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 990 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 991 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 992 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 993 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 994 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 995 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 996 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 997 }, 998 999 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to66_67MHz NO.22 1000 //Address,Value,Mask 1001 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1002 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1003 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1004 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 1005 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1006 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1007 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1008 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1009 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1010 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1011 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1012 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1013 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1014 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1015 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1016 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1017 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1018 {0x33,0x0020,0x0020},//reg_lpll2_pd 1019 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1020 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1021 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1022 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1023 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1024 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1025 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1026 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1027 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1028 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1029 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1030 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1031 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1032 }, 1033 1034 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to40MHz NO.23 1035 //Address,Value,Mask 1036 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1037 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1038 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1039 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 1040 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1041 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1042 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1043 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1044 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1045 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1046 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1047 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1048 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1049 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1050 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1051 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1052 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1053 {0x33,0x0020,0x0020},//reg_lpll2_pd 1054 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1055 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1056 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1057 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1058 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1059 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1060 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1061 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1062 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1063 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1064 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1065 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1066 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1067 }, 1068 1069 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_133_33to150MHz NO.24 1070 //Address,Value,Mask 1071 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1072 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1073 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1074 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 1075 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1076 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1077 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1078 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1079 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1080 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1081 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1082 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1083 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1084 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1085 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1086 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1087 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1088 {0x33,0x0020,0x0020},//reg_lpll2_pd 1089 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1090 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1091 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1092 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1093 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1094 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1095 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1096 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1097 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1098 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1099 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1100 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1101 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1102 }, 1103 1104 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to133_33MHz NO.25 1105 //Address,Value,Mask 1106 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1107 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1108 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1109 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 1110 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1111 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1112 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1113 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1114 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1115 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1116 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1117 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1118 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1119 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1120 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1121 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1122 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1123 {0x33,0x0020,0x0020},//reg_lpll2_pd 1124 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1125 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1126 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1127 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1128 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1129 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1130 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1131 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1132 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1133 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1134 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1135 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1136 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1137 }, 1138 1139 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to75MHz NO.26 1140 //Address,Value,Mask 1141 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1142 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1143 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1144 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 1145 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1146 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1147 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1148 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1149 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1150 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1151 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1152 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1153 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1154 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1155 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1156 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1157 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1158 {0x33,0x0020,0x0020},//reg_lpll2_pd 1159 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1160 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1161 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1162 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1163 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1164 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1165 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1166 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1167 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1168 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1169 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1170 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1171 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1172 }, 1173 1174 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_133_33to150MHz NO.27 1175 //Address,Value,Mask 1176 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1177 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1178 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1179 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 1180 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1181 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1182 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1183 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1184 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1185 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1186 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1187 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1188 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1189 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1190 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1191 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1192 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1193 {0x33,0x0020,0x0020},//reg_lpll2_pd 1194 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1195 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1196 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1197 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1198 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1199 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1200 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1201 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1202 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1203 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1204 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1205 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1206 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1207 }, 1208 1209 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to133_33MHz NO.28 1210 //Address,Value,Mask 1211 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1212 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1213 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1214 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 1215 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1216 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1217 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 1218 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 1219 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1220 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1221 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1222 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1223 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1224 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1225 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1226 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1227 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1228 {0x33,0x0020,0x0020},//reg_lpll2_pd 1229 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1230 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1231 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1232 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1233 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1234 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1235 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1236 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1237 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1238 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1239 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1240 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1241 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1242 }, 1243 1244 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to75MHz NO.29 1245 //Address,Value,Mask 1246 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1247 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1248 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1249 {0x01,0x0300,0x1F00},//reg_lpll1_loop_div_second 1250 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1251 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1252 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 1253 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 1254 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1255 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1256 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1257 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1258 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1259 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1260 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1261 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1262 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1263 {0x33,0x0020,0x0020},//reg_lpll2_pd 1264 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1265 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1266 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1267 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1268 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1269 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1270 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1271 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1272 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1273 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1274 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1275 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1276 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1277 }, 1278 1279 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_115to150MHz NO.30 1280 //Address,Value,Mask 1281 {0x03,0x0014,0x001C},//reg_lpll1_ibias_ictrl 1282 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1283 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1284 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1285 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1286 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1287 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1288 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1289 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1290 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1291 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1292 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1293 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1294 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1295 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1296 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1297 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1298 {0x33,0x0000,0x0020},//reg_lpll2_pd 1299 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1300 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1301 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1302 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1303 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1304 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1305 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1306 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1307 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1308 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1309 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1310 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1311 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1312 }, 1313 1314 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to115MHz NO.31 1315 //Address,Value,Mask 1316 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1317 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1318 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1319 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1320 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1321 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1322 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1323 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1324 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1325 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1326 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1327 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1328 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1329 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1330 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1331 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1332 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1333 {0x33,0x0000,0x0020},//reg_lpll2_pd 1334 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1335 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1336 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1337 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1338 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1339 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1340 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1341 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1342 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1343 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1344 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1345 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1346 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1347 }, 1348 1349 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to75MHz NO.32 1350 //Address,Value,Mask 1351 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1352 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1353 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1354 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1355 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1356 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1357 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1358 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1359 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1360 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1361 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1362 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1363 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1364 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1365 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1366 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1367 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1368 {0x33,0x0000,0x0020},//reg_lpll2_pd 1369 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1370 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1371 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1372 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1373 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1374 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1375 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1376 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1377 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1378 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1379 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1380 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1381 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1382 }, 1383 1384 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_115to150MHz NO.33 1385 //Address,Value,Mask 1386 {0x03,0x0014,0x001C},//reg_lpll1_ibias_ictrl 1387 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1388 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1389 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1390 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1391 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1392 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1393 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1394 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1395 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1396 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1397 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1398 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1399 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1400 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1401 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1402 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1403 {0x33,0x0000,0x0020},//reg_lpll2_pd 1404 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1405 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1406 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1407 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1408 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1409 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1410 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1411 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1412 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1413 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1414 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1415 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1416 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1417 }, 1418 1419 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to115MHz NO.34 1420 //Address,Value,Mask 1421 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1422 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1423 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1424 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1425 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1426 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1427 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1428 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1429 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1430 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1431 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1432 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1433 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1434 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1435 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1436 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1437 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1438 {0x33,0x0000,0x0020},//reg_lpll2_pd 1439 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1440 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1441 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1442 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1443 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1444 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1445 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1446 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1447 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1448 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1449 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1450 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1451 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1452 }, 1453 1454 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to75MHz NO.35 1455 //Address,Value,Mask 1456 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1457 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1458 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1459 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1460 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1461 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1462 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1463 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1464 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1465 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1466 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1467 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1468 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1469 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1470 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1471 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1472 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1473 {0x33,0x0000,0x0020},//reg_lpll2_pd 1474 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1475 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1476 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1477 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1478 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1479 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1480 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1481 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1482 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1483 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1484 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1485 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1486 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1487 }, 1488 1489 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to300MHz NO.36 1490 //Address,Value,Mask 1491 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1492 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1493 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1494 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1495 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1496 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1497 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1498 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1499 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1500 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1501 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1502 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1503 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1504 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1505 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1506 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1507 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1508 {0x33,0x0000,0x0020},//reg_lpll2_pd 1509 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1510 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1511 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1512 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1513 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1514 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1515 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1516 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1517 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1518 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1519 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1520 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1521 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1522 }, 1523 1524 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to150MHz NO.37 1525 //Address,Value,Mask 1526 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1527 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1528 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1529 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1530 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1531 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1532 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1533 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1534 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1535 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1536 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1537 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1538 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1539 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1540 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1541 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1542 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1543 {0x33,0x0000,0x0020},//reg_lpll2_pd 1544 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1545 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1546 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1547 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1548 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1549 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1550 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1551 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1552 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1553 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1554 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1555 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1556 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1557 }, 1558 1559 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_230to300MHz NO.38 1560 //Address,Value,Mask 1561 {0x03,0x0014,0x001C},//reg_lpll1_ibias_ictrl 1562 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1563 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1564 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1565 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1566 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1567 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1568 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1569 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1570 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1571 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1572 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1573 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1574 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1575 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1576 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1577 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1578 {0x33,0x0000,0x0020},//reg_lpll2_pd 1579 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1580 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1581 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1582 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1583 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1584 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1585 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1586 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1587 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1588 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1589 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1590 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1591 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1592 }, 1593 1594 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to230MHz NO.39 1595 //Address,Value,Mask 1596 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1597 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1598 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1599 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1600 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1601 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1602 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1603 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1604 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1605 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1606 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1607 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1608 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1609 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1610 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1611 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1612 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1613 {0x33,0x0000,0x0020},//reg_lpll2_pd 1614 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1615 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1616 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1617 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1618 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1619 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1620 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1621 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1622 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1623 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1624 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1625 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1626 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1627 }, 1628 1629 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to150MHz NO.40 1630 //Address,Value,Mask 1631 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1632 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1633 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1634 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1635 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1636 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1637 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1638 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1639 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1640 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1641 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1642 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1643 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1644 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1645 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1646 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1647 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1648 {0x33,0x0000,0x0020},//reg_lpll2_pd 1649 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1650 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1651 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1652 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1653 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1654 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1655 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1656 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1657 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1658 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1659 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1660 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1661 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1662 }, 1663 1664 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to300MHz NO.41 1665 //Address,Value,Mask 1666 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1667 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1668 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1669 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1670 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1671 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1672 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1673 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1674 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1675 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1676 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1677 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1678 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1679 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1680 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1681 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1682 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1683 {0x33,0x0000,0x0020},//reg_lpll2_pd 1684 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1685 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1686 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1687 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1688 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1689 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1690 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1691 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1692 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1693 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1694 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1695 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1696 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1697 }, 1698 1699 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to150MHz NO.42 1700 //Address,Value,Mask 1701 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1702 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1703 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1704 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1705 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1706 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1707 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1708 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1709 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1710 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1711 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1712 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1713 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1714 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1715 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1716 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1717 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1718 {0x33,0x0000,0x0020},//reg_lpll2_pd 1719 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1720 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1721 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1722 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1723 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1724 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1725 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1726 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1727 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1728 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1729 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1730 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1731 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1732 }, 1733 1734 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_200to300MHz NO.43 1735 //Address,Value,Mask 1736 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1737 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1738 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1739 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1740 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1741 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1742 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1743 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1744 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1745 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1746 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1747 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1748 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1749 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1750 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1751 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1752 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1753 {0x33,0x0000,0x0020},//reg_lpll2_pd 1754 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1755 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1756 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1757 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1758 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1759 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1760 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1761 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1762 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1763 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1764 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1765 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1766 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1767 }, 1768 1769 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to200MHz NO.44 1770 //Address,Value,Mask 1771 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1772 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1773 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1774 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1775 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1776 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1777 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1778 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1779 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1780 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1781 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1782 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1783 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1784 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1785 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1786 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1787 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1788 {0x33,0x0000,0x0020},//reg_lpll2_pd 1789 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1790 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1791 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1792 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1793 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1794 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1795 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1796 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1797 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1798 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1799 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1800 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1801 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1802 }, 1803 1804 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to150MHz NO.45 1805 //Address,Value,Mask 1806 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1807 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1808 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1809 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1810 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1811 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1812 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1813 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1814 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1815 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1816 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1817 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1818 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1819 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1820 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1821 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1822 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1823 {0x33,0x0000,0x0020},//reg_lpll2_pd 1824 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1825 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1826 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1827 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1828 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1829 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1830 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1831 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1832 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1833 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1834 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1835 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1836 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1837 }, 1838 1839 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to300MHz NO.46 1840 //Address,Value,Mask 1841 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1842 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1843 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1844 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1845 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1846 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1847 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1848 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1849 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1850 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1851 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1852 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1853 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1854 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1855 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1856 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1857 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1858 {0x33,0x0000,0x0020},//reg_lpll2_pd 1859 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1860 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1861 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1862 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1863 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1864 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1865 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1866 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1867 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1868 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1869 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1870 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1871 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1872 }, 1873 1874 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to150MHz NO.47 1875 //Address,Value,Mask 1876 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1877 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1878 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1879 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 1880 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1881 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1882 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1883 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1884 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1885 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1886 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1887 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1888 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1889 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1890 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1891 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1892 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1893 {0x33,0x0000,0x0020},//reg_lpll2_pd 1894 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1895 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1896 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1897 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1898 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1899 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1900 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1901 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1902 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1903 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1904 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1905 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1906 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1907 }, 1908 1909 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to300MHz NO.48 1910 //Address,Value,Mask 1911 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1912 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1913 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1914 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1915 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1916 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1917 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1918 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1919 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1920 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1921 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1922 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1923 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1924 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1925 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1926 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1927 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1928 {0x33,0x0000,0x0020},//reg_lpll2_pd 1929 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1930 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1931 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1932 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1933 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1934 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1935 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1936 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1937 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1938 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1939 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1940 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1941 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1942 }, 1943 1944 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to150MHz NO.49 1945 //Address,Value,Mask 1946 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1947 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1948 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1949 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1950 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1951 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1952 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1953 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1954 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1955 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1956 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1957 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1958 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1959 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1960 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1961 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1962 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1963 {0x33,0x0000,0x0020},//reg_lpll2_pd 1964 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1965 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1966 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1967 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1968 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1969 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1970 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1971 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1972 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1973 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1974 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1975 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1976 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1977 }, 1978 1979 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_240to300MHz NO.50 1980 //Address,Value,Mask 1981 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1982 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1983 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1984 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 1985 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1986 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1987 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1988 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1989 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1990 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1991 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1992 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1993 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1994 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1995 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1996 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1997 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1998 {0x33,0x0000,0x0020},//reg_lpll2_pd 1999 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2000 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2001 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2002 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2003 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2004 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 2005 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2006 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2007 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2008 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2009 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2010 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2011 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2012 }, 2013 2014 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to240MHz NO.51 2015 //Address,Value,Mask 2016 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2017 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2018 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2019 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 2020 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2021 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2022 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2023 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2024 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2025 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2026 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2027 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2028 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2029 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2030 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2031 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2032 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2033 {0x33,0x0000,0x0020},//reg_lpll2_pd 2034 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2035 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2036 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2037 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2038 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2039 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 2040 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2041 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2042 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2043 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2044 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2045 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2046 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2047 }, 2048 2049 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to150MHz NO.52 2050 //Address,Value,Mask 2051 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2052 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2053 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2054 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 2055 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2056 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2057 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2058 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2059 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2060 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2061 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2062 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2063 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2064 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2065 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2066 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2067 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2068 {0x33,0x0000,0x0020},//reg_lpll2_pd 2069 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2070 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2071 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2072 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2073 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2074 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 2075 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2076 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2077 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2078 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2079 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2080 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2081 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2082 }, 2083 2084 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz NO.53 2085 //Address,Value,Mask 2086 {0x03,0x0014,0x001C},//reg_lpll1_ibias_ictrl 2087 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2088 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2089 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 2090 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2091 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2092 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2093 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2094 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2095 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2096 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2097 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2098 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2099 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2100 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2101 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2102 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2103 {0x33,0x0000,0x0020},//reg_lpll2_pd 2104 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2105 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2106 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2107 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2108 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2109 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2110 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2111 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2112 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2113 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2114 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2115 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2116 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2117 }, 2118 2119 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz NO.54 2120 //Address,Value,Mask 2121 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2122 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2123 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2124 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 2125 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2126 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2127 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2128 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2129 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2130 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2131 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2132 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2133 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2134 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2135 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2136 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2137 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2138 {0x33,0x0000,0x0020},//reg_lpll2_pd 2139 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2140 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2141 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2142 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2143 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2144 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2145 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2146 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2147 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2148 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2149 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2150 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2151 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2152 }, 2153 2154 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz NO.55 2155 //Address,Value,Mask 2156 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2157 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2158 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2159 {0x01,0x0700,0x1F00},//reg_lpll1_loop_div_second 2160 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2161 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2162 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2163 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2164 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2165 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2166 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2167 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2168 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2169 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2170 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2171 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2172 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2173 {0x33,0x0000,0x0020},//reg_lpll2_pd 2174 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2175 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2176 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2177 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2178 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2179 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2180 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2181 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2182 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2183 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2184 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2185 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2186 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2187 }, 2188 2189 { //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to300MHz NO.56 2190 //Address,Value,Mask 2191 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2192 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2193 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2194 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2195 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2196 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2197 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2198 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2199 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2200 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2201 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2202 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2203 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2204 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2205 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2206 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2207 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2208 {0x33,0x0000,0x0020},//reg_lpll2_pd 2209 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2210 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2211 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2212 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2213 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2214 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2215 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2216 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2217 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2218 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2219 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2220 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2221 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2222 }, 2223 2224 { //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to150MHz NO.57 2225 //Address,Value,Mask 2226 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2227 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2228 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2229 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2230 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2231 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2232 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2233 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2234 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2235 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2236 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2237 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2238 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2239 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2240 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2241 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2242 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2243 {0x33,0x0000,0x0020},//reg_lpll2_pd 2244 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2245 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2246 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2247 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2248 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2249 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2250 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2251 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2252 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2253 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2254 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2255 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2256 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2257 }, 2258 2259 { //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to300MHz NO.58 2260 //Address,Value,Mask 2261 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2262 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2263 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2264 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2265 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2266 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2267 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2268 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2269 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2270 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2271 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2272 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2273 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2274 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2275 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2276 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2277 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2278 {0x33,0x0000,0x0020},//reg_lpll2_pd 2279 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2280 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2281 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2282 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2283 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2284 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2285 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2286 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2287 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2288 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2289 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2290 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2291 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2292 }, 2293 2294 { //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to150MHz NO.59 2295 //Address,Value,Mask 2296 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2297 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2298 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2299 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2300 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2301 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2302 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2303 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2304 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2305 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2306 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2307 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2308 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2309 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2310 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2311 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2312 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2313 {0x33,0x0000,0x0020},//reg_lpll2_pd 2314 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2315 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2316 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2317 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2318 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2319 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2320 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2321 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2322 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2323 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2324 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2325 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2326 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2327 }, 2328 2329 { //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz NO.60 2330 //Address,Value,Mask 2331 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2332 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2333 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2334 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2335 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 2336 {0x02,0x0500,0x0F00},//reg_lpll1_output_div_second[11:8] 2337 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2338 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2339 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2340 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2341 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2342 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2343 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2344 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2345 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2346 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2347 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2348 {0x33,0x0000,0x0020},//reg_lpll2_pd 2349 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 2350 {0x30,0x0005,0x001F},//reg_lpll2_input_div_first 2351 {0x31,0x0001,0x0003},//reg_lpll2_loop_div_first 2352 {0x31,0x0900,0x1F00},//reg_lpll2_loop_div_second 2353 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2354 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2355 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2356 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2357 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2358 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2359 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2360 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2361 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2362 }, 2363 2364 { //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.61 2365 //Address,Value,Mask 2366 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2367 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2368 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2369 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 2370 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 2371 {0x02,0x0500,0x0F00},//reg_lpll1_output_div_second[11:8] 2372 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2373 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2374 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2375 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2376 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2377 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2378 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2379 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2380 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2381 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2382 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2383 {0x33,0x0000,0x0020},//reg_lpll2_pd 2384 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 2385 {0x30,0x0005,0x001F},//reg_lpll2_input_div_first 2386 {0x31,0x0001,0x0003},//reg_lpll2_loop_div_first 2387 {0x31,0x0900,0x1F00},//reg_lpll2_loop_div_second 2388 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2389 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2390 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2391 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2392 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2393 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2394 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2395 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2396 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2397 }, 2398 2399 { //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz NO.62 2400 //Address,Value,Mask 2401 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2402 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2403 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2404 {0x01,0x0500,0x1F00},//reg_lpll1_loop_div_second 2405 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2406 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2407 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2408 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2409 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2410 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2411 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2412 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2413 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2414 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2415 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2416 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2417 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2418 {0x33,0x0000,0x0020},//reg_lpll2_pd 2419 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2420 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2421 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2422 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2423 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2424 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2425 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2426 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2427 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2428 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2429 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2430 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2431 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2432 }, 2433 2434 { //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.63 2435 //Address,Value,Mask 2436 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2437 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2438 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2439 {0x01,0x0500,0x1F00},//reg_lpll1_loop_div_second 2440 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2441 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2442 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2443 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2444 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2445 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2446 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2447 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2448 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2449 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2450 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2451 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2452 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2453 {0x33,0x0000,0x0020},//reg_lpll2_pd 2454 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2455 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2456 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2457 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2458 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2459 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2460 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2461 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2462 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2463 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2464 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2465 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2466 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2467 }, 2468 2469 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to300MHz NO.64 2470 //Address,Value,Mask 2471 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2472 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2473 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2474 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2475 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2476 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2477 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2478 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2479 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2480 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2481 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2482 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2483 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2484 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2485 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2486 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2487 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2488 {0x33,0x0000,0x0020},//reg_lpll2_pd 2489 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2490 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2491 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2492 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2493 {0x32,0x0005,0x000F},//reg_lpll2_output_div_first 2494 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2495 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2496 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2497 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2498 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2499 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2500 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2501 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2502 }, 2503 2504 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to150MHz NO.65 2505 //Address,Value,Mask 2506 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2507 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2508 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2509 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2510 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2511 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2512 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2513 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2514 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2515 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2516 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2517 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2518 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2519 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2520 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2521 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2522 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2523 {0x33,0x0000,0x0020},//reg_lpll2_pd 2524 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2525 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2526 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2527 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2528 {0x32,0x0005,0x000F},//reg_lpll2_output_div_first 2529 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2530 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2531 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2532 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2533 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2534 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2535 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2536 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2537 }, 2538 2539 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_200to300MHz NO.66 2540 //Address,Value,Mask 2541 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2542 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2543 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2544 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2545 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2546 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2547 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2548 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2549 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2550 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2551 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2552 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2553 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2554 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2555 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2556 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2557 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2558 {0x33,0x0000,0x0020},//reg_lpll2_pd 2559 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2560 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2561 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2562 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2563 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2564 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2565 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2566 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2567 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2568 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2569 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2570 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2571 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2572 }, 2573 2574 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to200MHz NO.67 2575 //Address,Value,Mask 2576 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2577 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2578 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2579 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2580 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2581 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2582 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2583 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2584 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2585 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2586 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2587 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2588 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2589 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2590 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2591 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2592 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2593 {0x33,0x0000,0x0020},//reg_lpll2_pd 2594 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2595 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2596 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2597 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2598 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2599 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2600 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2601 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2602 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2603 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2604 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2605 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2606 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2607 }, 2608 2609 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz NO.68 2610 //Address,Value,Mask 2611 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2612 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2613 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2614 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2615 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2616 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2617 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2618 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2619 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2620 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2621 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2622 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2623 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2624 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2625 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2626 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2627 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2628 {0x33,0x0000,0x0020},//reg_lpll2_pd 2629 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2630 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2631 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2632 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2633 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2634 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2635 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2636 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2637 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2638 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2639 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2640 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2641 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2642 }, 2643 2644 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.69 2645 //Address,Value,Mask 2646 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2647 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2648 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2649 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2650 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2651 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2652 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2653 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2654 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2655 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2656 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2657 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2658 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2659 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2660 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2661 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2662 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2663 {0x33,0x0000,0x0020},//reg_lpll2_pd 2664 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2665 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2666 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2667 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2668 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2669 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2670 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2671 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2672 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2673 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2674 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 2675 {0x38,0x0100,0x0100},//reg_lpll1_scalar2fifo_div2 2676 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2677 }, 2678 2679 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.70 2680 //Address,Value,Mask 2681 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2682 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2683 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2684 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2685 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2686 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2687 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2688 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2689 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2690 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2691 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2692 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2693 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2694 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2695 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2696 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2697 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2698 {0x33,0x0000,0x0020},//reg_lpll2_pd 2699 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2700 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2701 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2702 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2703 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2704 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2705 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2706 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2707 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2708 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2709 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 2710 {0x38,0x0100,0x0100},//reg_lpll1_scalar2fifo_div2 2711 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2712 }, 2713 2714 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz NO.71 2715 //Address,Value,Mask 2716 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2717 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2718 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2719 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2720 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2721 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2722 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2723 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2724 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2725 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2726 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2727 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2728 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2729 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2730 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2731 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2732 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2733 {0x33,0x0000,0x0020},//reg_lpll2_pd 2734 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2735 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2736 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2737 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2738 {0x32,0x0005,0x000F},//reg_lpll2_output_div_first 2739 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2740 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2741 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2742 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2743 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2744 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2745 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2746 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2747 }, 2748 2749 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz NO.72 2750 //Address,Value,Mask 2751 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2752 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2753 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2754 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2755 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2756 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2757 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2758 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2759 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2760 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2761 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2762 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2763 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2764 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2765 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2766 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2767 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2768 {0x33,0x0000,0x0020},//reg_lpll2_pd 2769 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2770 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2771 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2772 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2773 {0x32,0x0005,0x000F},//reg_lpll2_output_div_first 2774 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2775 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2776 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2777 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2778 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2779 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2780 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2781 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2782 }, 2783 2784 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz NO.73 2785 //Address,Value,Mask 2786 {0x03,0x0010,0x001C},//reg_lpll1_ibias_ictrl 2787 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2788 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2789 {0x01,0x0F00,0x1F00},//reg_lpll1_loop_div_second 2790 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2791 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2792 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2793 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2794 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2795 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2796 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2797 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2798 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2799 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2800 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2801 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2802 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2803 {0x33,0x0000,0x0020},//reg_lpll2_pd 2804 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2805 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2806 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2807 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2808 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2809 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2810 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2811 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2812 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2813 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2814 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2815 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2816 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2817 }, 2818 2819 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz NO.74 2820 //Address,Value,Mask 2821 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 2822 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2823 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2824 {0x01,0x0F00,0x1F00},//reg_lpll1_loop_div_second 2825 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2826 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2827 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2828 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2829 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2830 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2831 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2832 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2833 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2834 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2835 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2836 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2837 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2838 {0x33,0x0000,0x0020},//reg_lpll2_pd 2839 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2840 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2841 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2842 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2843 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2844 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2845 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2846 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2847 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2848 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2849 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2850 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2851 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2852 }, 2853 2854 { //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz NO.75 2855 //Address,Value,Mask 2856 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 2857 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2858 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2859 {0x01,0x0F00,0x1F00},//reg_lpll1_loop_div_second 2860 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2861 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2862 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2863 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2864 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2865 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2866 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2867 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2868 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2869 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2870 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2871 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2872 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2873 {0x33,0x0000,0x0020},//reg_lpll2_pd 2874 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2875 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2876 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2877 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2878 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2879 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2880 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2881 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2882 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2883 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2884 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2885 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2886 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2887 }, 2888 2889 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz NO.76 2890 //Address,Value,Mask 2891 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 2892 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2893 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2894 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2895 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2896 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2897 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2898 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2899 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2900 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2901 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 2902 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2903 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 2904 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2905 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2906 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2907 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2908 {0x33,0x0000,0x0020},//reg_lpll2_pd 2909 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2910 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2911 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2912 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2913 {0x32,0x0008,0x000F},//reg_lpll2_output_div_first 2914 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 2915 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2916 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2917 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2918 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2919 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2920 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2921 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2922 }, 2923 2924 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz NO.77 2925 //Address,Value,Mask 2926 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2927 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2928 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2929 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2930 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2931 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2932 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2933 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2934 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2935 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2936 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2937 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2938 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2939 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2940 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2941 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2942 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2943 {0x33,0x0000,0x0020},//reg_lpll2_pd 2944 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2945 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2946 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2947 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2948 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2949 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2950 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2951 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2952 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2953 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2954 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2955 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2956 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2957 }, 2958 2959 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz NO.78 2960 //Address,Value,Mask 2961 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2962 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2963 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2964 {0x01,0x0900,0x1F00},//reg_lpll1_loop_div_second 2965 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2966 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2967 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2968 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 2969 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2970 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2971 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2972 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2973 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2974 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2975 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2976 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2977 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2978 {0x33,0x0000,0x0020},//reg_lpll2_pd 2979 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2980 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2981 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2982 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2983 {0x32,0x000E,0x000F},//reg_lpll2_output_div_first 2984 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2985 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2986 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2987 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2988 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2989 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2990 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2991 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2992 }, 2993 2994 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz NO.79 2995 //Address,Value,Mask 2996 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 2997 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2998 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 2999 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3000 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 3001 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 3002 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3003 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3004 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3005 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3006 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3007 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3008 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3009 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3010 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3011 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3012 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3013 {0x33,0x0020,0x0020},//reg_lpll2_pd 3014 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3015 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3016 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3017 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3018 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3019 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3020 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3021 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3022 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3023 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3024 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3025 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3026 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3027 }, 3028 3029 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz NO.80 3030 //Address,Value,Mask 3031 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3032 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3033 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3034 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3035 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 3036 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 3037 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3038 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3039 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3040 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3041 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3042 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3043 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3044 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3045 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3046 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3047 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3048 {0x33,0x0020,0x0020},//reg_lpll2_pd 3049 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3050 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3051 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3052 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3053 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3054 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3055 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3056 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3057 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3058 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3059 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3060 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3061 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3062 }, 3063 3064 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.81 3065 //Address,Value,Mask 3066 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3067 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3068 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3069 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3070 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 3071 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 3072 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3073 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3074 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3075 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3076 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3077 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3078 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3079 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3080 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3081 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3082 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3083 {0x33,0x0020,0x0020},//reg_lpll2_pd 3084 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3085 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3086 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3087 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3088 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3089 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3090 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3091 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3092 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3093 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3094 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3095 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3096 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3097 }, 3098 3099 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.82 3100 //Address,Value,Mask 3101 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3102 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3103 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3104 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3105 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 3106 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 3107 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3108 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3109 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3110 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3111 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3112 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3113 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3114 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3115 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3116 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3117 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3118 {0x33,0x0020,0x0020},//reg_lpll2_pd 3119 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3120 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3121 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3122 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3123 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3124 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3125 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3126 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3127 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3128 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3129 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3130 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3131 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3132 }, 3133 3134 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.83 3135 //Address,Value,Mask 3136 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3137 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3138 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3139 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3140 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 3141 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 3142 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3143 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3144 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3145 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3146 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3147 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3148 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3149 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3150 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3151 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3152 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3153 {0x33,0x0020,0x0020},//reg_lpll2_pd 3154 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3155 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3156 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3157 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3158 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3159 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3160 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3161 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3162 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3163 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3164 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3165 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3166 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3167 }, 3168 3169 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.84 3170 //Address,Value,Mask 3171 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3172 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3173 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3174 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3175 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 3176 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 3177 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3178 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3179 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3180 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3181 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3182 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3183 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3184 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3185 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3186 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3187 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3188 {0x33,0x0020,0x0020},//reg_lpll2_pd 3189 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3190 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3191 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3192 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3193 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3194 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3195 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3196 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3197 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3198 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3199 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3200 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3201 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3202 }, 3203 3204 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz NO.85 3205 //Address,Value,Mask 3206 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3207 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3208 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3209 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3210 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 3211 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3212 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3213 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3214 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3215 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3216 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3217 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3218 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3219 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3220 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3221 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3222 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3223 {0x33,0x0020,0x0020},//reg_lpll2_pd 3224 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3225 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3226 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3227 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3228 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3229 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3230 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3231 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3232 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3233 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3234 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3235 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3236 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3237 }, 3238 3239 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz NO.86 3240 //Address,Value,Mask 3241 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3242 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3243 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3244 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3245 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 3246 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3247 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 3248 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 3249 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3250 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3251 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3252 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3253 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3254 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3255 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3256 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3257 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3258 {0x33,0x0020,0x0020},//reg_lpll2_pd 3259 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3260 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3261 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3262 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3263 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3264 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3265 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3266 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3267 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3268 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3269 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3270 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3271 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3272 }, 3273 3274 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz NO.87 3275 //Address,Value,Mask 3276 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3277 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3278 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3279 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3280 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 3281 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3282 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 3283 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 3284 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3285 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3286 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3287 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3288 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3289 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3290 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3291 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3292 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3293 {0x33,0x0020,0x0020},//reg_lpll2_pd 3294 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3295 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3296 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3297 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3298 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3299 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3300 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3301 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3302 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3303 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3304 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3305 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3306 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3307 }, 3308 3309 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.88 3310 //Address,Value,Mask 3311 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3312 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3313 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3314 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3315 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 3316 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3317 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3318 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3319 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3320 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3321 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3322 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3323 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3324 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3325 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3326 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3327 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3328 {0x33,0x0020,0x0020},//reg_lpll2_pd 3329 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3330 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3331 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3332 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3333 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3334 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3335 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3336 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3337 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3338 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3339 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3340 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3341 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3342 }, 3343 3344 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.89 3345 //Address,Value,Mask 3346 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3347 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3348 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3349 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3350 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 3351 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3352 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 3353 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 3354 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3355 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3356 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3357 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3358 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3359 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3360 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3361 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3362 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3363 {0x33,0x0020,0x0020},//reg_lpll2_pd 3364 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3365 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3366 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3367 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3368 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3369 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3370 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3371 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3372 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3373 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3374 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3375 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3376 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3377 }, 3378 3379 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.90 3380 //Address,Value,Mask 3381 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3382 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3383 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3384 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3385 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 3386 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3387 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 3388 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 3389 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3390 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3391 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3392 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3393 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3394 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3395 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3396 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3397 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3398 {0x33,0x0020,0x0020},//reg_lpll2_pd 3399 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3400 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3401 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3402 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3403 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3404 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3405 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3406 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3407 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3408 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3409 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3410 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3411 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3412 }, 3413 3414 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.91 3415 //Address,Value,Mask 3416 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3417 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3418 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3419 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3420 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 3421 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3422 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 3423 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 3424 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3425 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3426 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3427 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3428 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3429 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3430 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3431 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3432 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3433 {0x33,0x0020,0x0020},//reg_lpll2_pd 3434 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3435 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3436 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3437 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3438 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3439 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3440 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3441 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3442 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3443 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3444 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3445 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3446 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3447 }, 3448 3449 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.92 3450 //Address,Value,Mask 3451 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3452 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3453 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3454 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3455 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 3456 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3457 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 3458 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 3459 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3460 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3461 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3462 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3463 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3464 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3465 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3466 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3467 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3468 {0x33,0x0020,0x0020},//reg_lpll2_pd 3469 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3470 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3471 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3472 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3473 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3474 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3475 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3476 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3477 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3478 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3479 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3480 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3481 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3482 }, 3483 3484 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.93 3485 //Address,Value,Mask 3486 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 3487 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 3488 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 3489 {0x01,0x0400,0x1F00},//reg_lpll1_loop_div_second 3490 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 3491 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 3492 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 3493 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 3494 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 3495 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 3496 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 3497 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 3498 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 3499 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 3500 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 3501 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 3502 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 3503 {0x33,0x0020,0x0020},//reg_lpll2_pd 3504 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 3505 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 3506 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 3507 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 3508 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 3509 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 3510 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 3511 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 3512 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 3513 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 3514 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 3515 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 3516 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 3517 }, 3518 3519 }; 3520 MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= 3521 { 3522 12, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 3523 12, //E_PNL_SUPPORTED_LPLL_TTL_75to100MHz NO.1 3524 12, //E_PNL_SUPPORTED_LPLL_TTL_75to75MHz NO.2 3525 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_55to80MHz NO.3 3526 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to55MHz NO.4 3527 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to40MHz NO.5 3528 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.6 3529 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to50MHz NO.7 3530 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to37_5MHz NO.8 3531 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.9 3532 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to100MHz NO.10 3533 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to75MHz NO.11 3534 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.12 3535 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to100MHz NO.13 3536 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to75MHz NO.14 3537 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to80MHz NO.15 3538 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to40MHz NO.16 3539 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to150MHz NO.17 3540 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to75MHz NO.18 3541 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to150MHz NO.19 3542 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to75MHz NO.20 3543 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz NO.21 3544 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to66_67MHz NO.22 3545 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to40MHz NO.23 3546 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_133_33to150MHz NO.24 3547 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to133_33MHz NO.25 3548 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to75MHz NO.26 3549 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_133_33to150MHz NO.27 3550 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to133_33MHz NO.28 3551 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to75MHz NO.29 3552 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_115to150MHz NO.30 3553 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to115MHz NO.31 3554 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to75MHz NO.32 3555 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_115to150MHz NO.33 3556 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to115MHz NO.34 3557 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to75MHz NO.35 3558 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to300MHz NO.36 3559 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to150MHz NO.37 3560 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_230to300MHz NO.38 3561 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to230MHz NO.39 3562 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to150MHz NO.40 3563 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to300MHz NO.41 3564 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to150MHz NO.42 3565 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_200to300MHz NO.43 3566 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to200MHz NO.44 3567 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to150MHz NO.45 3568 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to300MHz NO.46 3569 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to150MHz NO.47 3570 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to300MHz NO.48 3571 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to150MHz NO.49 3572 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_240to300MHz NO.50 3573 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to240MHz NO.51 3574 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to150MHz NO.52 3575 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz NO.53 3576 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz NO.54 3577 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz NO.55 3578 8, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to300MHz NO.56 3579 8, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to150MHz NO.57 3580 8, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to300MHz NO.58 3581 8, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to150MHz NO.59 3582 72, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz NO.60 3583 72, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.61 3584 8, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz NO.62 3585 8, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.63 3586 8, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to300MHz NO.64 3587 8, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to150MHz NO.65 3588 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_200to300MHz NO.66 3589 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to200MHz NO.67 3590 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz NO.68 3591 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.69 3592 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.70 3593 8, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz NO.71 3594 8, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz NO.72 3595 16, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz NO.73 3596 16, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz NO.74 3597 16, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz NO.75 3598 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz NO.76 3599 16, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz NO.77 3600 16, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz NO.78 3601 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz NO.79 3602 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz NO.80 3603 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.81 3604 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.82 3605 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.83 3606 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.84 3607 64, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz NO.85 3608 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz NO.86 3609 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz NO.87 3610 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.88 3611 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.89 3612 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.90 3613 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.91 3614 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.92 3615 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.93 3616 }; 3617 MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= 3618 { 3619 8, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 3620 16, //E_PNL_SUPPORTED_LPLL_TTL_75to100MHz NO.1 3621 16, //E_PNL_SUPPORTED_LPLL_TTL_75to75MHz NO.2 3622 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_55to80MHz NO.3 3623 28, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to55MHz NO.4 3624 28, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_40to40MHz NO.5 3625 14, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.6 3626 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to50MHz NO.7 3627 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_37_5to37_5MHz NO.8 3628 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.9 3629 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to100MHz NO.10 3630 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_75to75MHz NO.11 3631 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.12 3632 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to100MHz NO.13 3633 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_75to75MHz NO.14 3634 16, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to80MHz NO.15 3635 16, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_8BIT_40to40MHz NO.16 3636 8, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to150MHz NO.17 3637 8, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_8BIT_75to75MHz NO.18 3638 8, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to150MHz NO.19 3639 8, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_8BIT_75to75MHz NO.20 3640 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz NO.21 3641 24, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to66_67MHz NO.22 3642 24, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_40to40MHz NO.23 3643 6, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_133_33to150MHz NO.24 3644 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to133_33MHz NO.25 3645 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_3PAIR_6BIT_75to75MHz NO.26 3646 6, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_133_33to150MHz NO.27 3647 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to133_33MHz NO.28 3648 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2BK_6PAIR_6BIT_75to75MHz NO.29 3649 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_115to150MHz NO.30 3650 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to115MHz NO.31 3651 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_2PAIR_FHD_75to75MHz NO.32 3652 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_115to150MHz NO.33 3653 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to115MHz NO.34 3654 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_FHD_75to75MHz NO.35 3655 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to300MHz NO.36 3656 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_FHD_150to150MHz NO.37 3657 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_230to300MHz NO.38 3658 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to230MHz NO.39 3659 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_FHD_150to150MHz NO.40 3660 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to300MHz NO.41 3661 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_16PAIR_UHD_150to150MHz NO.42 3662 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_200to300MHz NO.43 3663 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to200MHz NO.44 3664 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_16PAIR_UHD_150to150MHz NO.45 3665 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to300MHz NO.46 3666 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_UHD_150to150MHz NO.47 3667 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to300MHz NO.48 3668 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_UHD_150to150MHz NO.49 3669 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_240to300MHz NO.50 3670 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to240MHz NO.51 3671 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_EPI3G_UHD_150to150MHz NO.52 3672 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_180to300MHz NO.53 3673 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to180MHz NO.54 3674 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_EPI3G_V17_150to150MHz NO.55 3675 4, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to300MHz NO.56 3676 4, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_150to150MHz NO.57 3677 4, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to300MHz NO.58 3678 4, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_150to150MHz NO.59 3679 25, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to300MHz NO.60 3680 25, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.61 3681 4, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to300MHz NO.62 3682 4, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.63 3683 5, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to300MHz NO.64 3684 5, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_6PAIR_DUAL_150to150MHz NO.65 3685 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_200to300MHz NO.66 3686 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to200MHz NO.67 3687 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz NO.68 3688 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.69 3689 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.70 3690 5, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to300MHz NO.71 3691 5, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_12PAIR_150to150MHz NO.72 3692 9, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_199_2to300MHz NO.73 3693 9, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to199_2MHz NO.74 3694 9, //E_PNL_SUPPORTED_LPLL_ISP_10BIT_8PAIR_150to150MHz NO.75 3695 3, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_249to300MHz NO.76 3696 9, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to249MHz NO.77 3697 9, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_8PAIR_150to150MHz NO.78 3698 10, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to300MHz NO.79 3699 10, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to150MHz NO.80 3700 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.81 3701 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.82 3702 40, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.83 3703 40, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.84 3704 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_200to300MHz NO.85 3705 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to200MHz NO.86 3706 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to150MHz NO.87 3707 15, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.88 3708 30, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.89 3709 30, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.90 3710 30, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.91 3711 60, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.92 3712 60, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.93 3713 }; 3714 3715 #endif //_LPLL_TBL_H_ 3716