1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_TBL_H_ 80 #define _LPLL_TBL_H_ 81 82 #define LPLL_REG_NUM 24 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz, //0 87 88 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz, //1 89 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz, //2 90 91 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz, //3 92 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz, //4 93 94 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz, //5 95 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz, //6 96 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz, //7 97 98 E_PNL_SUPPORTED_LPLL_TTL_100to150MHz, //8 99 E_PNL_SUPPORTED_LPLL_TTL_50to100MHz, //9 100 E_PNL_SUPPORTED_LPLL_TTL_25to50MHz, //10 101 102 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz, //11 103 104 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz, //12 105 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz, //13 106 107 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz, //14 108 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz, //15 109 110 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz, //16 111 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz, //17 112 113 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz, //18 114 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz, //19 115 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz, //20 116 117 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz, //21 118 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz, //22 119 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz, //23 120 121 E_PNL_SUPPORTED_LPLL_EPI34_10BIT_2PAIR_150to150MHz, //24 122 123 E_PNL_SUPPORTED_LPLL_EPI34_10BIT_4PAIR_80to150MHz, //25 124 125 E_PNL_SUPPORTED_LPLL_EPI34_10BIT_6PAIR_80to150MHz, //26 126 127 E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_188to300MHz, //27 128 E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_80to188MHz, //28 129 130 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_2PAIR_150to150MHz, //29 131 132 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_114to150MHz, //30 133 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_80to114MHz, //31 134 135 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_172to300MHz, //32 136 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_80to172MHz, //33 137 138 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_228to300MHz, //34 139 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_114to228MHz, //35 140 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_80to114MHz, //36 141 142 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to340MHz, //37 143 144 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz, //38 145 146 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz, //39 147 148 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_220to340MHz, //40 149 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to220MHz, //41 150 151 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz, //42 152 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz, //43 153 154 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz, //44 155 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to55MHz, //45 156 157 E_PNL_SUPPORTED_LPLL_EPI28_8BIT_12PAIR_340to340MHz, //46 158 159 E_PNL_SUPPORTED_LPLL_MAX, //47 160 } E_PNL_SUPPORTED_LPLL_TYPE; 161 162 typedef struct 163 { 164 MS_U8 address; 165 MS_U16 value; 166 MS_U16 mask; 167 }TBLStruct,*pTBLStruct; 168 169 TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= 170 { 171 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.0 172 //Address,Value,Mask 173 {0x03,0x0000,0x0020},//reg_lpll1_pd 174 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 175 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 176 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 177 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 178 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 179 {0x02,0x0700,0x0F00},//reg_lpll1_scalar_div_second 180 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 181 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 182 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 183 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 184 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 185 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 186 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 187 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 188 {0x33,0x0020,0x0020},//reg_lpll2_pd 189 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 190 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 191 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 192 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 193 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 194 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 195 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 196 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 197 }, 198 199 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.1 200 //Address,Value,Mask 201 {0x03,0x0000,0x0020},//reg_lpll1_pd 202 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 203 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 204 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 205 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 206 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 207 {0x02,0x0700,0x0F00},//reg_lpll1_scalar_div_second 208 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 209 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 210 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 211 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 212 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 213 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 214 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 215 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 216 {0x33,0x0020,0x0020},//reg_lpll2_pd 217 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 218 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 219 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 220 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 221 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 222 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 223 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 224 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 225 }, 226 227 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.2 228 //Address,Value,Mask 229 {0x03,0x0000,0x0020},//reg_lpll1_pd 230 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 231 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 232 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 233 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 234 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 235 {0x02,0x0700,0x0F00},//reg_lpll1_scalar_div_second 236 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 237 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 238 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 239 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 240 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 241 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 242 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 243 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 244 {0x33,0x0020,0x0020},//reg_lpll2_pd 245 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 246 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 247 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 248 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 249 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 250 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 251 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 252 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 253 }, 254 255 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.3 256 //Address,Value,Mask 257 {0x03,0x0000,0x0020},//reg_lpll1_pd 258 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 259 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 260 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 261 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 262 {0x02,0x0000,0x3000},//reg_lpll1_scalar_div_first 263 {0x02,0x0700,0x0F00},//reg_lpll1_scalar_div_second 264 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 265 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 266 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 267 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 268 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 269 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 270 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 271 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 272 {0x33,0x0020,0x0020},//reg_lpll2_pd 273 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 274 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 275 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 276 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 277 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 278 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 279 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 280 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 281 }, 282 283 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.4 284 //Address,Value,Mask 285 {0x03,0x0000,0x0020},//reg_lpll1_pd 286 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 287 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 288 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 289 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 290 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 291 {0x02,0x0700,0x0F00},//reg_lpll1_scalar_div_second 292 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 293 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 294 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 295 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 296 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 297 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 298 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 299 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 300 {0x33,0x0020,0x0020},//reg_lpll2_pd 301 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 302 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 303 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 304 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 305 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 306 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 307 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 308 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 309 }, 310 311 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz NO.5 312 //Address,Value,Mask 313 {0x03,0x0000,0x0020},//reg_lpll1_pd 314 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 315 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 316 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 317 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 318 {0x02,0x0000,0x3000},//reg_lpll1_scalar_div_first 319 {0x02,0x0700,0x0F00},//reg_lpll1_scalar_div_second 320 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 321 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 322 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 323 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 324 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 325 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 326 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 327 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 328 {0x33,0x0020,0x0020},//reg_lpll2_pd 329 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 330 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 331 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 332 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 333 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 334 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 335 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 336 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 337 }, 338 339 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz NO.6 340 //Address,Value,Mask 341 {0x03,0x0000,0x0020},//reg_lpll1_pd 342 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 343 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 344 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 345 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 346 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 347 {0x02,0x0700,0x0F00},//reg_lpll1_scalar_div_second 348 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 349 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 350 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 351 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 352 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 353 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 354 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 355 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 356 {0x33,0x0020,0x0020},//reg_lpll2_pd 357 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 358 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 359 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 360 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 361 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 362 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 363 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 364 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 365 }, 366 367 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz NO.7 368 //Address,Value,Mask 369 {0x03,0x0000,0x0020},//reg_lpll1_pd 370 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 371 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 372 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 373 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 374 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 375 {0x02,0x0700,0x0F00},//reg_lpll1_scalar_div_second 376 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 377 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 378 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 379 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 380 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 381 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 382 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 383 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 384 {0x33,0x0020,0x0020},//reg_lpll2_pd 385 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 386 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 387 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 388 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 389 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 390 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 391 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 392 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 393 }, 394 395 { //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.8 396 //Address,Value,Mask 397 {0x03,0x0000,0x0020},//reg_lpll1_pd 398 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 399 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 400 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 401 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 402 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 403 {0x02,0x0200,0x0F00},//reg_lpll1_scalar_div_second 404 {0x35,0x5000,0x7000},//reg_lpll1_skew_div 405 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 406 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 407 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 408 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 409 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 410 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 411 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 412 {0x33,0x0020,0x0020},//reg_lpll2_pd 413 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 414 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 415 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 416 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 417 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 418 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 419 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 420 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 421 }, 422 423 { //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.9 424 //Address,Value,Mask 425 {0x03,0x0000,0x0020},//reg_lpll1_pd 426 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 427 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 428 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 429 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 430 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 431 {0x02,0x0400,0x0F00},//reg_lpll1_scalar_div_second 432 {0x35,0x5000,0x7000},//reg_lpll1_skew_div 433 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 434 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 435 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 436 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 437 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 438 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 439 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 440 {0x33,0x0020,0x0020},//reg_lpll2_pd 441 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 442 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 443 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 444 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 445 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 446 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 447 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 448 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 449 }, 450 451 { //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.10 452 //Address,Value,Mask 453 {0x03,0x0000,0x0020},//reg_lpll1_pd 454 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 455 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 456 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 457 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 458 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 459 {0x02,0x0800,0x0F00},//reg_lpll1_scalar_div_second 460 {0x35,0x5000,0x7000},//reg_lpll1_skew_div 461 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 462 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 463 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 464 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 465 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 466 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 467 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 468 {0x33,0x0020,0x0020},//reg_lpll2_pd 469 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 470 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 471 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 472 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 473 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 474 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 475 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 476 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 477 }, 478 479 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.11 480 //Address,Value,Mask 481 {0x03,0x0000,0x0020},//reg_lpll1_pd 482 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 483 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 484 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 485 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 486 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 487 {0x02,0x0200,0x0F00},//reg_lpll1_scalar_div_second 488 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 489 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 490 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 491 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 492 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 493 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 494 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 495 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 496 {0x33,0x0020,0x0020},//reg_lpll2_pd 497 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 498 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 499 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 500 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 501 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 502 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 503 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 504 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 505 }, 506 507 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.12 508 //Address,Value,Mask 509 {0x03,0x0000,0x0020},//reg_lpll1_pd 510 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 511 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 512 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 513 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 514 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 515 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 516 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 517 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 518 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 519 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 520 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 521 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 522 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 523 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 524 {0x33,0x0020,0x0020},//reg_lpll2_pd 525 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 526 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 527 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 528 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 529 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 530 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 531 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 532 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 533 }, 534 535 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.13 536 //Address,Value,Mask 537 {0x03,0x0000,0x0020},//reg_lpll1_pd 538 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 539 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 540 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 541 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 542 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 543 {0x02,0x0200,0x0F00},//reg_lpll1_scalar_div_second 544 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 545 {0x2E,0x0001,0x000F},//reg_lpll_fifo_div 546 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 547 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 548 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 549 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 550 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 551 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 552 {0x33,0x0020,0x0020},//reg_lpll2_pd 553 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 554 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 555 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 556 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 557 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 558 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 559 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 560 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 561 }, 562 563 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.14 564 //Address,Value,Mask 565 {0x03,0x0000,0x0020},//reg_lpll1_pd 566 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 567 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 568 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 569 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 570 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 571 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 572 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 573 {0x2E,0x0001,0x000F},//reg_lpll_fifo_div 574 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 575 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 576 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 577 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 578 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 579 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 580 {0x33,0x0020,0x0020},//reg_lpll2_pd 581 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 582 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 583 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 584 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 585 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 586 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 587 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 588 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 589 }, 590 591 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.15 592 //Address,Value,Mask 593 {0x03,0x0000,0x0020},//reg_lpll1_pd 594 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 595 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 596 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 597 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 598 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 599 {0x02,0x0200,0x0F00},//reg_lpll1_scalar_div_second 600 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 601 {0x2E,0x0002,0x000F},//reg_lpll_fifo_div 602 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 603 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 604 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 605 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 606 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 607 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 608 {0x33,0x0020,0x0020},//reg_lpll2_pd 609 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 610 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 611 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 612 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 613 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 614 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 615 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 616 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 617 }, 618 619 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz NO.16 620 //Address,Value,Mask 621 {0x03,0x0000,0x0020},//reg_lpll1_pd 622 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 623 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 624 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 625 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 626 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 627 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 628 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 629 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 630 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 631 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 632 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 633 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 634 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 635 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 636 {0x33,0x0020,0x0020},//reg_lpll2_pd 637 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 638 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 639 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 640 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 641 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 642 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 643 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 644 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 645 }, 646 647 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz NO.17 648 //Address,Value,Mask 649 {0x03,0x0000,0x0020},//reg_lpll1_pd 650 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 651 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 652 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 653 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 654 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 655 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 656 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 657 {0x2E,0x0001,0x000F},//reg_lpll_fifo_div 658 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 659 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 660 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 661 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 662 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 663 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 664 {0x33,0x0020,0x0020},//reg_lpll2_pd 665 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 666 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 667 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 668 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 669 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 670 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 671 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 672 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 673 }, 674 675 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.18 676 //Address,Value,Mask 677 {0x03,0x0000,0x0020},//reg_lpll1_pd 678 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 679 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 680 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 681 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 682 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 683 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 684 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 685 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 686 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 687 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 688 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 689 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 690 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 691 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 692 {0x33,0x0020,0x0020},//reg_lpll2_pd 693 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 694 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 695 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 696 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 697 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 698 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 699 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 700 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 701 }, 702 703 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.19 704 //Address,Value,Mask 705 {0x03,0x0000,0x0020},//reg_lpll1_pd 706 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 707 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 708 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 709 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 710 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 711 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 712 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 713 {0x2E,0x0001,0x000F},//reg_lpll_fifo_div 714 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 715 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 716 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 717 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 718 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 719 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 720 {0x33,0x0020,0x0020},//reg_lpll2_pd 721 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 722 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 723 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 724 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 725 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 726 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 727 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 728 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 729 }, 730 731 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.20 732 //Address,Value,Mask 733 {0x03,0x0000,0x0020},//reg_lpll1_pd 734 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 735 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 736 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 737 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 738 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 739 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 740 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 741 {0x2E,0x0002,0x000F},//reg_lpll_fifo_div 742 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 743 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 744 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 745 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 746 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 747 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 748 {0x33,0x0020,0x0020},//reg_lpll2_pd 749 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 750 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 751 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 752 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 753 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 754 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 755 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 756 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 757 }, 758 759 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz NO.21 760 //Address,Value,Mask 761 {0x03,0x0000,0x0020},//reg_lpll1_pd 762 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 763 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 764 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 765 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 766 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 767 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 768 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 769 {0x2E,0x0001,0x000F},//reg_lpll_fifo_div 770 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 771 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 772 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 773 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 774 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 775 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 776 {0x33,0x0020,0x0020},//reg_lpll2_pd 777 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 778 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 779 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 780 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 781 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 782 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 783 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 784 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 785 }, 786 787 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz NO.22 788 //Address,Value,Mask 789 {0x03,0x0000,0x0020},//reg_lpll1_pd 790 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 791 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 792 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 793 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 794 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 795 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 796 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 797 {0x2E,0x0002,0x000F},//reg_lpll_fifo_div 798 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 799 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 800 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 801 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 802 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 803 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 804 {0x33,0x0020,0x0020},//reg_lpll2_pd 805 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 806 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 807 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 808 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 809 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 810 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 811 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 812 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 813 }, 814 815 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz NO.23 816 //Address,Value,Mask 817 {0x03,0x0000,0x0020},//reg_lpll1_pd 818 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 819 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 820 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 821 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 822 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 823 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 824 {0x35,0x4000,0x7000},//reg_lpll1_skew_div 825 {0x2E,0x0003,0x000F},//reg_lpll_fifo_div 826 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 827 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 828 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 829 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 830 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 831 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 832 {0x33,0x0020,0x0020},//reg_lpll2_pd 833 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 834 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 835 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 836 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 837 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 838 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 839 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 840 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 841 }, 842 843 { //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_2PAIR_150to150MHz NO.24 844 //Address,Value,Mask 845 {0x03,0x0000,0x0020},//reg_lpll1_pd 846 {0x03,0x0000,0x001C},//reg_lpll1_ibias_ictrl 847 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 848 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 849 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 850 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 851 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 852 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 853 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 854 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 855 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 856 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 857 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 858 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 859 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 860 {0x33,0x0000,0x0020},//reg_lpll2_pd 861 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 862 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 863 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 864 {0x31,0x0600,0xFF00},//reg_lpll2_loop_div_second 865 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 866 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 867 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 868 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 869 }, 870 871 { //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_4PAIR_80to150MHz NO.25 872 //Address,Value,Mask 873 {0x03,0x0000,0x0020},//reg_lpll1_pd 874 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 875 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 876 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 877 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 878 {0x02,0x0000,0x3000},//reg_lpll1_scalar_div_first 879 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 880 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 881 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 882 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 883 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 884 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 885 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 886 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 887 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 888 {0x33,0x0000,0x0020},//reg_lpll2_pd 889 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 890 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 891 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 892 {0x31,0x0600,0xFF00},//reg_lpll2_loop_div_second 893 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 894 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 895 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 896 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 897 }, 898 899 { //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_6PAIR_80to150MHz NO.26 900 //Address,Value,Mask 901 {0x03,0x0000,0x0020},//reg_lpll1_pd 902 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 903 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 904 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 905 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 906 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 907 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 908 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 909 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 910 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 911 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 912 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 913 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 914 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 915 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 916 {0x33,0x0000,0x0020},//reg_lpll2_pd 917 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 918 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 919 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 920 {0x31,0x0600,0xFF00},//reg_lpll2_loop_div_second 921 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 922 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 923 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 924 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 925 }, 926 927 { //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_188to300MHz NO.27 928 //Address,Value,Mask 929 {0x03,0x0000,0x0020},//reg_lpll1_pd 930 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 931 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 932 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 933 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 934 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 935 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 936 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 937 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 938 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 939 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 940 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 941 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 942 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 943 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 944 {0x33,0x0000,0x0020},//reg_lpll2_pd 945 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 946 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 947 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 948 {0x31,0x0400,0xFF00},//reg_lpll2_loop_div_second 949 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 950 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 951 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 952 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 953 }, 954 955 { //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_80to188MHz NO.28 956 //Address,Value,Mask 957 {0x03,0x0000,0x0020},//reg_lpll1_pd 958 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 959 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 960 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 961 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 962 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 963 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 964 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 965 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 966 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 967 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 968 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 969 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 970 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 971 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 972 {0x33,0x0000,0x0020},//reg_lpll2_pd 973 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 974 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 975 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 976 {0x31,0x0400,0xFF00},//reg_lpll2_loop_div_second 977 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 978 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 979 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 980 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 981 }, 982 983 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_2PAIR_150to150MHz NO.29 984 //Address,Value,Mask 985 {0x03,0x0000,0x0020},//reg_lpll1_pd 986 {0x03,0x0000,0x001C},//reg_lpll1_ibias_ictrl 987 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 988 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 989 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 990 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 991 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 992 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 993 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 994 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 995 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 996 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 997 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 998 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 999 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1000 {0x33,0x0000,0x0020},//reg_lpll2_pd 1001 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1002 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1003 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1004 {0x31,0x0600,0xFF00},//reg_lpll2_loop_div_second 1005 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1006 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1007 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1008 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1009 }, 1010 1011 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_114to150MHz NO.30 1012 //Address,Value,Mask 1013 {0x03,0x0000,0x0020},//reg_lpll1_pd 1014 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1015 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1016 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1017 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1018 {0x02,0x0000,0x3000},//reg_lpll1_scalar_div_first 1019 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 1020 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1021 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1022 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1023 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1024 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 1025 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1026 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1027 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1028 {0x33,0x0000,0x0020},//reg_lpll2_pd 1029 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1030 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1031 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1032 {0x31,0x0600,0xFF00},//reg_lpll2_loop_div_second 1033 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1034 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1035 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1036 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1037 }, 1038 1039 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_80to114MHz NO.31 1040 //Address,Value,Mask 1041 {0x03,0x0000,0x0020},//reg_lpll1_pd 1042 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1043 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1044 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1045 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1046 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 1047 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 1048 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1049 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1050 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1051 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1052 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 1053 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1054 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1055 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1056 {0x33,0x0000,0x0020},//reg_lpll2_pd 1057 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1058 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1059 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1060 {0x31,0x0600,0xFF00},//reg_lpll2_loop_div_second 1061 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1062 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1063 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1064 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1065 }, 1066 1067 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_172to300MHz NO.32 1068 //Address,Value,Mask 1069 {0x03,0x0000,0x0020},//reg_lpll1_pd 1070 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1071 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1072 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1073 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1074 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 1075 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 1076 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1077 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1078 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1079 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1080 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 1081 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1082 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1083 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1084 {0x33,0x0000,0x0020},//reg_lpll2_pd 1085 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1086 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1087 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1088 {0x31,0x0600,0xFF00},//reg_lpll2_loop_div_second 1089 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1090 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1091 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1092 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1093 }, 1094 1095 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_80to172MHz NO.33 1096 //Address,Value,Mask 1097 {0x03,0x0000,0x0020},//reg_lpll1_pd 1098 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1099 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1100 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1101 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1102 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 1103 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 1104 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1105 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1106 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1107 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1108 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 1109 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1110 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1111 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1112 {0x33,0x0000,0x0020},//reg_lpll2_pd 1113 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1114 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1115 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1116 {0x31,0x0600,0xFF00},//reg_lpll2_loop_div_second 1117 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1118 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1119 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1120 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1121 }, 1122 1123 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_228to300MHz NO.34 1124 //Address,Value,Mask 1125 {0x03,0x0000,0x0020},//reg_lpll1_pd 1126 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1127 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1128 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1129 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1130 {0x02,0x0000,0x3000},//reg_lpll1_scalar_div_first 1131 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 1132 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1133 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1134 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1135 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1136 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 1137 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1138 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1139 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1140 {0x33,0x0020,0x0020},//reg_lpll2_pd 1141 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1142 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1143 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1144 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1145 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1146 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1147 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1148 {0x04,0x2000,0x2000},//reg_lpll1_sdiv3p5_en 1149 }, 1150 1151 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_114to228MHz NO.35 1152 //Address,Value,Mask 1153 {0x03,0x0000,0x0020},//reg_lpll1_pd 1154 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1155 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1156 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1157 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1158 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 1159 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 1160 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1161 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1162 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1163 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1164 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 1165 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1166 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1167 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1168 {0x33,0x0020,0x0020},//reg_lpll2_pd 1169 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1170 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1171 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1172 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1173 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1174 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1175 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1176 {0x04,0x2000,0x2000},//reg_lpll1_sdiv3p5_en 1177 }, 1178 1179 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_80to114MHz NO.36 1180 //Address,Value,Mask 1181 {0x03,0x0000,0x0020},//reg_lpll1_pd 1182 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1183 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1184 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1185 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1186 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 1187 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 1188 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1189 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1190 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1191 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1192 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 1193 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1194 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1195 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1196 {0x33,0x0020,0x0020},//reg_lpll2_pd 1197 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1198 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1199 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1200 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1201 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1202 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1203 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1204 {0x04,0x2000,0x2000},//reg_lpll1_sdiv3p5_en 1205 }, 1206 1207 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to340MHz NO.37 1208 //Address,Value,Mask 1209 {0x03,0x0000,0x0020},//reg_lpll1_pd 1210 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1211 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1212 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1213 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1214 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 1215 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 1216 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1217 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1218 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1219 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1220 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1221 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1222 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1223 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1224 {0x33,0x0020,0x0020},//reg_lpll2_pd 1225 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1226 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1227 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1228 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1229 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1230 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1231 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1232 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1233 }, 1234 1235 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.38 1236 //Address,Value,Mask 1237 {0x03,0x0000,0x0020},//reg_lpll1_pd 1238 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1239 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1240 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1241 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1242 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 1243 {0x02,0x0200,0x0F00},//reg_lpll1_scalar_div_second 1244 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1245 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1246 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1247 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1248 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1249 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1250 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1251 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1252 {0x33,0x0020,0x0020},//reg_lpll2_pd 1253 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1254 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1255 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1256 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1257 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1258 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1259 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1260 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1261 }, 1262 1263 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz NO.39 1264 //Address,Value,Mask 1265 {0x03,0x0000,0x0020},//reg_lpll1_pd 1266 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1267 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1268 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1269 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1270 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 1271 {0x02,0x0200,0x0F00},//reg_lpll1_scalar_div_second 1272 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1273 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1274 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1275 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1276 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1277 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1278 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1279 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1280 {0x33,0x0020,0x0020},//reg_lpll2_pd 1281 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1282 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1283 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1284 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1285 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1286 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1287 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1288 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1289 }, 1290 1291 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_220to340MHz NO.40 1292 //Address,Value,Mask 1293 {0x03,0x0000,0x0020},//reg_lpll1_pd 1294 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1295 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1296 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1297 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1298 {0x02,0x0000,0x3000},//reg_lpll1_scalar_div_first 1299 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 1300 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1301 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1302 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1303 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1304 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1305 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1306 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1307 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1308 {0x33,0x0020,0x0020},//reg_lpll2_pd 1309 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1310 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1311 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1312 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1313 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1314 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1315 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1316 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1317 }, 1318 1319 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to220MHz NO.41 1320 //Address,Value,Mask 1321 {0x03,0x0000,0x0020},//reg_lpll1_pd 1322 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1323 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1324 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1325 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1326 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 1327 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 1328 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1329 {0x2E,0x0004,0x000F},//reg_lpll_fifo_div 1330 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1331 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1332 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1333 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1334 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1335 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1336 {0x33,0x0020,0x0020},//reg_lpll2_pd 1337 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1338 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1339 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1340 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1341 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1342 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1343 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1344 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1345 }, 1346 1347 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz NO.42 1348 //Address,Value,Mask 1349 {0x03,0x0000,0x0020},//reg_lpll1_pd 1350 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1351 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1352 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1353 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1354 {0x02,0x1000,0x3000},//reg_lpll1_scalar_div_first 1355 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 1356 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1357 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1358 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1359 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1360 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1361 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1362 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1363 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1364 {0x33,0x0020,0x0020},//reg_lpll2_pd 1365 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1366 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1367 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1368 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1369 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1370 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1371 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1372 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1373 }, 1374 1375 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz NO.43 1376 //Address,Value,Mask 1377 {0x03,0x0000,0x0020},//reg_lpll1_pd 1378 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1379 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1380 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1381 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1382 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 1383 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 1384 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1385 {0x2E,0x0004,0x000F},//reg_lpll_fifo_div 1386 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1387 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1388 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1389 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1390 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1391 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1392 {0x33,0x0020,0x0020},//reg_lpll2_pd 1393 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1394 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1395 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1396 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1397 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1398 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1399 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1400 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1401 }, 1402 1403 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz NO.44 1404 //Address,Value,Mask 1405 {0x03,0x0000,0x0020},//reg_lpll1_pd 1406 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1407 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1408 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1409 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1410 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 1411 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 1412 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1413 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1414 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1415 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1416 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1417 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1418 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1419 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1420 {0x33,0x0020,0x0020},//reg_lpll2_pd 1421 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1422 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1423 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1424 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1425 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1426 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1427 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1428 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1429 }, 1430 1431 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to55MHz NO.45 1432 //Address,Value,Mask 1433 {0x03,0x0000,0x0020},//reg_lpll1_pd 1434 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1435 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1436 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1437 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1438 {0x02,0x3000,0x3000},//reg_lpll1_scalar_div_first 1439 {0x02,0x0300,0x0F00},//reg_lpll1_scalar_div_second 1440 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1441 {0x2E,0x0004,0x000F},//reg_lpll_fifo_div 1442 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1443 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1444 {0x2E,0x8000,0x8000},//reg_lpll1_duap_lp_en 1445 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1446 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1447 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1448 {0x33,0x0020,0x0020},//reg_lpll2_pd 1449 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1450 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1451 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1452 {0x31,0x0000,0xFF00},//reg_lpll2_loop_div_second 1453 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1454 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1455 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1456 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1457 }, 1458 1459 { //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_12PAIR_340to340MHz NO.46 1460 //Address,Value,Mask 1461 {0x03,0x0000,0x0020},//reg_lpll1_pd 1462 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1463 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1464 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1465 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1466 {0x02,0x2000,0x3000},//reg_lpll1_scalar_div_first 1467 {0x02,0x0000,0x0F00},//reg_lpll1_scalar_div_second 1468 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1469 {0x2E,0x0000,0x000F},//reg_lpll_fifo_div 1470 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1471 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1472 {0x2E,0x0000,0x8000},//reg_lpll1_duap_lp_en 1473 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1474 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1475 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1476 {0x33,0x0000,0x0020},//reg_lpll2_pd 1477 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1478 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1479 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1480 {0x31,0x0300,0xFF00},//reg_lpll2_loop_div_second 1481 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1482 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1483 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1484 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1485 }, 1486 1487 }; 1488 MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= 1489 { 1490 6, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.0 1491 6, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.1 1492 3, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.2 1493 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.3 1494 6, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.4 1495 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz NO.5 1496 6, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz NO.6 1497 3, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz NO.7 1498 3, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.8 1499 3, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.9 1500 3, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.10 1501 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.11 1502 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.12 1503 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.13 1504 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.14 1505 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.15 1506 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz NO.16 1507 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz NO.17 1508 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.18 1509 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.19 1510 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.20 1511 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz NO.21 1512 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz NO.22 1513 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz NO.23 1514 16, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_2PAIR_150to150MHz NO.24 1515 24, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_4PAIR_80to150MHz NO.25 1516 18, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_6PAIR_80to150MHz NO.26 1517 48, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_188to300MHz NO.27 1518 24, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_80to188MHz NO.28 1519 8, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_2PAIR_150to150MHz NO.29 1520 12, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_114to150MHz NO.30 1521 6, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_80to114MHz NO.31 1522 18, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_172to300MHz NO.32 1523 9, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_80to172MHz NO.33 1524 24, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_228to300MHz NO.34 1525 12, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_114to228MHz NO.35 1526 6, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_80to114MHz NO.36 1527 2, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to340MHz NO.37 1528 1, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.38 1529 1, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz NO.39 1530 8, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_220to340MHz NO.40 1531 4, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to220MHz NO.41 1532 4, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz NO.42 1533 2, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz NO.43 1534 2, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz NO.44 1535 1, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to55MHz NO.45 1536 18, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_12PAIR_340to340MHz NO.46 1537 }; 1538 MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= 1539 { 1540 7, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.0 1541 7, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.1 1542 7, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.2 1543 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.3 1544 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.4 1545 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_115to150MHz NO.5 1546 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_57to115MHz NO.6 1547 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to57MHz NO.7 1548 2, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.8 1549 4, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.9 1550 8, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.10 1551 4, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.11 1552 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.12 1553 4, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.13 1554 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.14 1555 4, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.15 1556 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz NO.16 1557 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz NO.17 1558 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.18 1559 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.19 1560 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.20 1561 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz NO.21 1562 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz NO.22 1563 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz NO.23 1564 17, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_2PAIR_150to150MHz NO.24 1565 17, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_4PAIR_80to150MHz NO.25 1566 17, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_6PAIR_80to150MHz NO.26 1567 17, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_188to300MHz NO.27 1568 17, //E_PNL_SUPPORTED_LPLL_EPI34_10BIT_8PAIR_80to188MHz NO.28 1569 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_2PAIR_150to150MHz NO.29 1570 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_114to150MHz NO.30 1571 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_4PAIR_80to114MHz NO.31 1572 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_172to300MHz NO.32 1573 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_6PAIR_80to172MHz NO.33 1574 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_228to300MHz NO.34 1575 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_114to228MHz NO.35 1576 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_8PAIR_80to114MHz NO.36 1577 1, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_150to340MHz NO.37 1578 1, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.38 1579 2, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_38to75MHz NO.39 1580 3, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_220to340MHz NO.40 1581 3, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_150to220MHz NO.41 1582 3, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_110to150MHz NO.42 1583 3, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to110MHz NO.43 1584 3, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_55to75MHz NO.44 1585 3, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to55MHz NO.45 1586 7, //E_PNL_SUPPORTED_LPLL_EPI28_8BIT_12PAIR_340to340MHz NO.46 1587 }; 1588 1589 #endif //_LPLL_TBL_H_ 1590