1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 //alex_tung 95 #ifndef _HWREG_PM_SLEEP_H_ 96 #define _HWREG_PM_SLEEP_H_ 97 98 //============================================================= 99 //PM SLEEP 100 //#define REG_PM_SLEEP_BASE 0x0E00UL 101 #define REG_PM_SLEEP_00_L (REG_PM_SLEEP_BASE + 0x00) 102 #define REG_PM_SLEEP_00_H (REG_PM_SLEEP_BASE + 0x01) 103 #define REG_PM_SLEEP_01_L (REG_PM_SLEEP_BASE + 0x02) 104 #define REG_PM_SLEEP_01_H (REG_PM_SLEEP_BASE + 0x03) 105 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) 106 #define REG_PM_SLEEP_02_H (REG_PM_SLEEP_BASE + 0x05) 107 #define REG_PM_SLEEP_03_L (REG_PM_SLEEP_BASE + 0x06) 108 #define REG_PM_SLEEP_03_H (REG_PM_SLEEP_BASE + 0x07) 109 #define REG_PM_SLEEP_04_L (REG_PM_SLEEP_BASE + 0x08) 110 #define REG_PM_SLEEP_04_H (REG_PM_SLEEP_BASE + 0x09) 111 #define REG_PM_SLEEP_05_L (REG_PM_SLEEP_BASE + 0x0A) 112 #define REG_PM_SLEEP_05_H (REG_PM_SLEEP_BASE + 0x0B) 113 #define REG_PM_SLEEP_06_L (REG_PM_SLEEP_BASE + 0x0C) 114 #define REG_PM_SLEEP_06_H (REG_PM_SLEEP_BASE + 0x0D) 115 #define REG_PM_SLEEP_07_L (REG_PM_SLEEP_BASE + 0x0E) 116 #define REG_PM_SLEEP_07_H (REG_PM_SLEEP_BASE + 0x0F) 117 #define REG_PM_SLEEP_08_L (REG_PM_SLEEP_BASE + 0x10) 118 #define REG_PM_SLEEP_08_H (REG_PM_SLEEP_BASE + 0x11) 119 #define REG_PM_SLEEP_09_L (REG_PM_SLEEP_BASE + 0x12) 120 #define REG_PM_SLEEP_09_H (REG_PM_SLEEP_BASE + 0x13) 121 #define REG_PM_SLEEP_0A_L (REG_PM_SLEEP_BASE + 0x14) 122 #define REG_PM_SLEEP_0A_H (REG_PM_SLEEP_BASE + 0x15) 123 #define REG_PM_SLEEP_0B_L (REG_PM_SLEEP_BASE + 0x16) 124 #define REG_PM_SLEEP_0B_H (REG_PM_SLEEP_BASE + 0x17) 125 #define REG_PM_SLEEP_0C_L (REG_PM_SLEEP_BASE + 0x18) 126 #define REG_PM_SLEEP_0C_H (REG_PM_SLEEP_BASE + 0x19) 127 #define REG_PM_SLEEP_0D_L (REG_PM_SLEEP_BASE + 0x1A) 128 #define REG_PM_SLEEP_0D_H (REG_PM_SLEEP_BASE + 0x1B) 129 #define REG_PM_SLEEP_0E_L (REG_PM_SLEEP_BASE + 0x1C) 130 #define REG_PM_SLEEP_0E_H (REG_PM_SLEEP_BASE + 0x1D) 131 #define REG_PM_SLEEP_0F_L (REG_PM_SLEEP_BASE + 0x1E) 132 #define REG_PM_SLEEP_0F_H (REG_PM_SLEEP_BASE + 0x1F) 133 #define REG_PM_SLEEP_10_L (REG_PM_SLEEP_BASE + 0x20) 134 #define REG_PM_SLEEP_10_H (REG_PM_SLEEP_BASE + 0x21) 135 #define REG_PM_SLEEP_11_L (REG_PM_SLEEP_BASE + 0x22) 136 #define REG_PM_SLEEP_11_H (REG_PM_SLEEP_BASE + 0x23) 137 #define REG_PM_SLEEP_12_L (REG_PM_SLEEP_BASE + 0x24) 138 #define REG_PM_SLEEP_12_H (REG_PM_SLEEP_BASE + 0x25) 139 #define REG_PM_SLEEP_13_L (REG_PM_SLEEP_BASE + 0x26) 140 #define REG_PM_SLEEP_13_H (REG_PM_SLEEP_BASE + 0x27) 141 #define REG_PM_SLEEP_14_L (REG_PM_SLEEP_BASE + 0x28) 142 #define REG_PM_SLEEP_14_H (REG_PM_SLEEP_BASE + 0x29) 143 #define REG_PM_SLEEP_15_L (REG_PM_SLEEP_BASE + 0x2A) 144 #define REG_PM_SLEEP_15_H (REG_PM_SLEEP_BASE + 0x2B) 145 #define REG_PM_SLEEP_16_L (REG_PM_SLEEP_BASE + 0x2C) 146 #define REG_PM_SLEEP_16_H (REG_PM_SLEEP_BASE + 0x2D) 147 #define REG_PM_SLEEP_17_L (REG_PM_SLEEP_BASE + 0x2E) 148 #define REG_PM_SLEEP_17_H (REG_PM_SLEEP_BASE + 0x2F) 149 #define REG_PM_SLEEP_18_L (REG_PM_SLEEP_BASE + 0x30) 150 #define REG_PM_SLEEP_18_H (REG_PM_SLEEP_BASE + 0x31) 151 #define REG_PM_SLEEP_19_L (REG_PM_SLEEP_BASE + 0x32) 152 #define REG_PM_SLEEP_19_H (REG_PM_SLEEP_BASE + 0x33) 153 #define REG_PM_SLEEP_1A_L (REG_PM_SLEEP_BASE + 0x34) 154 #define REG_PM_SLEEP_1A_H (REG_PM_SLEEP_BASE + 0x35) 155 #define REG_PM_SLEEP_1B_L (REG_PM_SLEEP_BASE + 0x36) 156 #define REG_PM_SLEEP_1B_H (REG_PM_SLEEP_BASE + 0x37) 157 #define REG_PM_SLEEP_1C_L (REG_PM_SLEEP_BASE + 0x38) 158 #define REG_PM_SLEEP_1C_H (REG_PM_SLEEP_BASE + 0x39) 159 #define REG_PM_SLEEP_1D_L (REG_PM_SLEEP_BASE + 0x3A) 160 #define REG_PM_SLEEP_1D_H (REG_PM_SLEEP_BASE + 0x3B) 161 #define REG_PM_SLEEP_1E_L (REG_PM_SLEEP_BASE + 0x3C) 162 #define REG_PM_SLEEP_1E_H (REG_PM_SLEEP_BASE + 0x3D) 163 #define REG_PM_SLEEP_1F_L (REG_PM_SLEEP_BASE + 0x3E) 164 #define REG_PM_SLEEP_1F_H (REG_PM_SLEEP_BASE + 0x3F) 165 #define REG_PM_SLEEP_20_L (REG_PM_SLEEP_BASE + 0x40) 166 #define REG_PM_SLEEP_20_H (REG_PM_SLEEP_BASE + 0x41) 167 #define REG_PM_SLEEP_21_L (REG_PM_SLEEP_BASE + 0x42) 168 #define REG_PM_SLEEP_21_H (REG_PM_SLEEP_BASE + 0x43) 169 #define REG_PM_SLEEP_22_L (REG_PM_SLEEP_BASE + 0x44) 170 #define REG_PM_SLEEP_22_H (REG_PM_SLEEP_BASE + 0x45) 171 #define REG_PM_SLEEP_23_L (REG_PM_SLEEP_BASE + 0x46) 172 #define REG_PM_SLEEP_23_H (REG_PM_SLEEP_BASE + 0x47) 173 #define REG_PM_SLEEP_24_L (REG_PM_SLEEP_BASE + 0x48) 174 #define REG_PM_SLEEP_24_H (REG_PM_SLEEP_BASE + 0x49) 175 #define REG_PM_SLEEP_25_L (REG_PM_SLEEP_BASE + 0x4A) 176 #define REG_PM_SLEEP_25_H (REG_PM_SLEEP_BASE + 0x4B) 177 #define REG_PM_SLEEP_26_L (REG_PM_SLEEP_BASE + 0x4C) 178 #define REG_PM_SLEEP_26_H (REG_PM_SLEEP_BASE + 0x4D) 179 #define REG_PM_SLEEP_27_L (REG_PM_SLEEP_BASE + 0x4E) 180 #define REG_PM_SLEEP_27_H (REG_PM_SLEEP_BASE + 0x4F) 181 #define REG_PM_SLEEP_28_L (REG_PM_SLEEP_BASE + 0x50) 182 #define REG_PM_SLEEP_28_H (REG_PM_SLEEP_BASE + 0x51) 183 #define REG_PM_SLEEP_29_L (REG_PM_SLEEP_BASE + 0x52) 184 #define REG_PM_SLEEP_29_H (REG_PM_SLEEP_BASE + 0x53) 185 #define REG_PM_SLEEP_2A_L (REG_PM_SLEEP_BASE + 0x54) 186 #define REG_PM_SLEEP_2A_H (REG_PM_SLEEP_BASE + 0x55) 187 #define REG_PM_SLEEP_2B_L (REG_PM_SLEEP_BASE + 0x56) 188 #define REG_PM_SLEEP_2B_H (REG_PM_SLEEP_BASE + 0x57) 189 #define REG_PM_SLEEP_2C_L (REG_PM_SLEEP_BASE + 0x58) 190 #define REG_PM_SLEEP_2C_H (REG_PM_SLEEP_BASE + 0x59) 191 #define REG_PM_SLEEP_2D_L (REG_PM_SLEEP_BASE + 0x5A) 192 #define REG_PM_SLEEP_2D_H (REG_PM_SLEEP_BASE + 0x5B) 193 #define REG_PM_SLEEP_2E_L (REG_PM_SLEEP_BASE + 0x5C) 194 #define REG_PM_SLEEP_2E_H (REG_PM_SLEEP_BASE + 0x5D) 195 #define REG_PM_SLEEP_2F_L (REG_PM_SLEEP_BASE + 0x5E) 196 #define REG_PM_SLEEP_2F_H (REG_PM_SLEEP_BASE + 0x5F) 197 #define REG_PM_SLEEP_30_L (REG_PM_SLEEP_BASE + 0x60) 198 #define REG_PM_SLEEP_30_H (REG_PM_SLEEP_BASE + 0x61) 199 #define REG_PM_SLEEP_31_L (REG_PM_SLEEP_BASE + 0x62) 200 #define REG_PM_SLEEP_31_H (REG_PM_SLEEP_BASE + 0x63) 201 #define REG_PM_SLEEP_32_L (REG_PM_SLEEP_BASE + 0x64) 202 #define REG_PM_SLEEP_32_H (REG_PM_SLEEP_BASE + 0x65) 203 #define REG_PM_SLEEP_33_L (REG_PM_SLEEP_BASE + 0x66) 204 #define REG_PM_SLEEP_33_H (REG_PM_SLEEP_BASE + 0x67) 205 #define REG_PM_SLEEP_34_L (REG_PM_SLEEP_BASE + 0x68) 206 #define REG_PM_SLEEP_34_H (REG_PM_SLEEP_BASE + 0x69) 207 #define REG_PM_SLEEP_35_L (REG_PM_SLEEP_BASE + 0x6A) 208 #define REG_PM_SLEEP_35_H (REG_PM_SLEEP_BASE + 0x6B) 209 #define REG_PM_SLEEP_36_L (REG_PM_SLEEP_BASE + 0x6C) 210 #define REG_PM_SLEEP_36_H (REG_PM_SLEEP_BASE + 0x6D) 211 #define REG_PM_SLEEP_37_L (REG_PM_SLEEP_BASE + 0x6E) 212 #define REG_PM_SLEEP_37_H (REG_PM_SLEEP_BASE + 0x6F) 213 #define REG_PM_SLEEP_38_L (REG_PM_SLEEP_BASE + 0x70) 214 #define REG_PM_SLEEP_38_H (REG_PM_SLEEP_BASE + 0x71) 215 #define REG_PM_SLEEP_39_L (REG_PM_SLEEP_BASE + 0x72) 216 #define REG_PM_SLEEP_39_H (REG_PM_SLEEP_BASE + 0x73) 217 #define REG_PM_SLEEP_3A_L (REG_PM_SLEEP_BASE + 0x74) 218 #define REG_PM_SLEEP_3A_H (REG_PM_SLEEP_BASE + 0x75) 219 #define REG_PM_SLEEP_3B_L (REG_PM_SLEEP_BASE + 0x76) 220 #define REG_PM_SLEEP_3B_H (REG_PM_SLEEP_BASE + 0x77) 221 #define REG_PM_SLEEP_3C_L (REG_PM_SLEEP_BASE + 0x78) 222 #define REG_PM_SLEEP_3C_H (REG_PM_SLEEP_BASE + 0x79) 223 #define REG_PM_SLEEP_3D_L (REG_PM_SLEEP_BASE + 0x7A) 224 #define REG_PM_SLEEP_3D_H (REG_PM_SLEEP_BASE + 0x7B) 225 #define REG_PM_SLEEP_3E_L (REG_PM_SLEEP_BASE + 0x7C) 226 #define REG_PM_SLEEP_3E_H (REG_PM_SLEEP_BASE + 0x7D) 227 #define REG_PM_SLEEP_3F_L (REG_PM_SLEEP_BASE + 0x7E) 228 #define REG_PM_SLEEP_3F_H (REG_PM_SLEEP_BASE + 0x7F) 229 #define REG_PM_SLEEP_40_L (REG_PM_SLEEP_BASE + 0x80) 230 #define REG_PM_SLEEP_40_H (REG_PM_SLEEP_BASE + 0x81) 231 #define REG_PM_SLEEP_41_L (REG_PM_SLEEP_BASE + 0x82) 232 #define REG_PM_SLEEP_41_H (REG_PM_SLEEP_BASE + 0x83) 233 #define REG_PM_SLEEP_42_L (REG_PM_SLEEP_BASE + 0x84) 234 #define REG_PM_SLEEP_42_H (REG_PM_SLEEP_BASE + 0x85) 235 #define REG_PM_SLEEP_43_L (REG_PM_SLEEP_BASE + 0x86) 236 #define REG_PM_SLEEP_43_H (REG_PM_SLEEP_BASE + 0x87) 237 #define REG_PM_SLEEP_44_L (REG_PM_SLEEP_BASE + 0x88) 238 #define REG_PM_SLEEP_44_H (REG_PM_SLEEP_BASE + 0x89) 239 #define REG_PM_SLEEP_45_L (REG_PM_SLEEP_BASE + 0x8A) 240 #define REG_PM_SLEEP_45_H (REG_PM_SLEEP_BASE + 0x8B) 241 #define REG_PM_SLEEP_46_L (REG_PM_SLEEP_BASE + 0x8C) 242 #define REG_PM_SLEEP_46_H (REG_PM_SLEEP_BASE + 0x8D) 243 #define REG_PM_SLEEP_47_L (REG_PM_SLEEP_BASE + 0x8E) 244 #define REG_PM_SLEEP_47_H (REG_PM_SLEEP_BASE + 0x8F) 245 #define REG_PM_SLEEP_48_L (REG_PM_SLEEP_BASE + 0x90) 246 #define REG_PM_SLEEP_48_H (REG_PM_SLEEP_BASE + 0x91) 247 #define REG_PM_SLEEP_49_L (REG_PM_SLEEP_BASE + 0x92) 248 #define REG_PM_SLEEP_49_H (REG_PM_SLEEP_BASE + 0x93) 249 #define REG_PM_SLEEP_4A_L (REG_PM_SLEEP_BASE + 0x94) 250 #define REG_PM_SLEEP_4A_H (REG_PM_SLEEP_BASE + 0x95) 251 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) 252 #define REG_PM_SLEEP_4B_H (REG_PM_SLEEP_BASE + 0x97) 253 #define REG_PM_SLEEP_4C_L (REG_PM_SLEEP_BASE + 0x98) 254 #define REG_PM_SLEEP_4C_H (REG_PM_SLEEP_BASE + 0x99) 255 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) 256 #define REG_PM_SLEEP_4D_H (REG_PM_SLEEP_BASE + 0x9B) 257 #define REG_PM_SLEEP_4E_L (REG_PM_SLEEP_BASE + 0x9C) 258 #define REG_PM_SLEEP_4E_H (REG_PM_SLEEP_BASE + 0x9D) 259 #define REG_PM_SLEEP_4F_L (REG_PM_SLEEP_BASE + 0x9E) 260 #define REG_PM_SLEEP_4F_H (REG_PM_SLEEP_BASE + 0x9F) 261 #define REG_PM_SLEEP_50_L (REG_PM_SLEEP_BASE + 0xA0) 262 #define REG_PM_SLEEP_50_H (REG_PM_SLEEP_BASE + 0xA1) 263 #define REG_PM_SLEEP_51_L (REG_PM_SLEEP_BASE + 0xA2) 264 #define REG_PM_SLEEP_51_H (REG_PM_SLEEP_BASE + 0xA3) 265 #define REG_PM_SLEEP_52_L (REG_PM_SLEEP_BASE + 0xA4) 266 #define REG_PM_SLEEP_52_H (REG_PM_SLEEP_BASE + 0xA5) 267 #define REG_PM_SLEEP_53_L (REG_PM_SLEEP_BASE + 0xA6) 268 #define REG_PM_SLEEP_53_H (REG_PM_SLEEP_BASE + 0xA7) 269 #define REG_PM_SLEEP_54_L (REG_PM_SLEEP_BASE + 0xA8) 270 #define REG_PM_SLEEP_54_H (REG_PM_SLEEP_BASE + 0xA9) 271 #define REG_PM_SLEEP_55_L (REG_PM_SLEEP_BASE + 0xAA) 272 #define REG_PM_SLEEP_55_H (REG_PM_SLEEP_BASE + 0xAB) 273 #define REG_PM_SLEEP_56_L (REG_PM_SLEEP_BASE + 0xAC) 274 #define REG_PM_SLEEP_56_H (REG_PM_SLEEP_BASE + 0xAD) 275 #define REG_PM_SLEEP_57_L (REG_PM_SLEEP_BASE + 0xAE) 276 #define REG_PM_SLEEP_57_H (REG_PM_SLEEP_BASE + 0xAF) 277 #define REG_PM_SLEEP_58_L (REG_PM_SLEEP_BASE + 0xB0) 278 #define REG_PM_SLEEP_58_H (REG_PM_SLEEP_BASE + 0xB1) 279 #define REG_PM_SLEEP_59_L (REG_PM_SLEEP_BASE + 0xB2) 280 #define REG_PM_SLEEP_59_H (REG_PM_SLEEP_BASE + 0xB3) 281 #define REG_PM_SLEEP_5A_L (REG_PM_SLEEP_BASE + 0xB4) 282 #define REG_PM_SLEEP_5A_H (REG_PM_SLEEP_BASE + 0xB5) 283 #define REG_PM_SLEEP_5B_L (REG_PM_SLEEP_BASE + 0xB6) 284 #define REG_PM_SLEEP_5B_H (REG_PM_SLEEP_BASE + 0xB7) 285 #define REG_PM_SLEEP_5C_L (REG_PM_SLEEP_BASE + 0xB8) 286 #define REG_PM_SLEEP_5C_H (REG_PM_SLEEP_BASE + 0xB9) 287 #define REG_PM_SLEEP_5D_L (REG_PM_SLEEP_BASE + 0xBA) 288 #define REG_PM_SLEEP_5D_H (REG_PM_SLEEP_BASE + 0xBB) 289 #define REG_PM_SLEEP_5E_L (REG_PM_SLEEP_BASE + 0xBC) 290 #define REG_PM_SLEEP_5E_H (REG_PM_SLEEP_BASE + 0xBD) 291 #define REG_PM_SLEEP_5F_L (REG_PM_SLEEP_BASE + 0xBE) 292 #define REG_PM_SLEEP_5F_H (REG_PM_SLEEP_BASE + 0xBF) 293 #define REG_PM_SLEEP_60_L (REG_PM_SLEEP_BASE + 0xC0) 294 #define REG_PM_SLEEP_60_H (REG_PM_SLEEP_BASE + 0xC1) 295 #define REG_PM_SLEEP_61_L (REG_PM_SLEEP_BASE + 0xC2) 296 #define REG_PM_SLEEP_61_H (REG_PM_SLEEP_BASE + 0xC3) 297 #define REG_PM_SLEEP_62_L (REG_PM_SLEEP_BASE + 0xC4) 298 #define REG_PM_SLEEP_62_H (REG_PM_SLEEP_BASE + 0xC5) 299 #define REG_PM_SLEEP_63_L (REG_PM_SLEEP_BASE + 0xC6) 300 #define REG_PM_SLEEP_63_H (REG_PM_SLEEP_BASE + 0xC7) 301 #define REG_PM_SLEEP_64_L (REG_PM_SLEEP_BASE + 0xC8) 302 #define REG_PM_SLEEP_64_H (REG_PM_SLEEP_BASE + 0xC9) 303 #define REG_PM_SLEEP_65_L (REG_PM_SLEEP_BASE + 0xCA) 304 #define REG_PM_SLEEP_65_H (REG_PM_SLEEP_BASE + 0xCB) 305 #define REG_PM_SLEEP_66_L (REG_PM_SLEEP_BASE + 0xCC) 306 #define REG_PM_SLEEP_66_H (REG_PM_SLEEP_BASE + 0xCD) 307 #define REG_PM_SLEEP_67_L (REG_PM_SLEEP_BASE + 0xCE) 308 #define REG_PM_SLEEP_67_H (REG_PM_SLEEP_BASE + 0xCF) 309 #define REG_PM_SLEEP_68_L (REG_PM_SLEEP_BASE + 0xD0) 310 #define REG_PM_SLEEP_68_H (REG_PM_SLEEP_BASE + 0xD1) 311 #define REG_PM_SLEEP_69_L (REG_PM_SLEEP_BASE + 0xD2) 312 #define REG_PM_SLEEP_69_H (REG_PM_SLEEP_BASE + 0xD3) 313 #define REG_PM_SLEEP_6A_L (REG_PM_SLEEP_BASE + 0xD4) 314 #define REG_PM_SLEEP_6A_H (REG_PM_SLEEP_BASE + 0xD5) 315 #define REG_PM_SLEEP_6B_L (REG_PM_SLEEP_BASE + 0xD6) 316 #define REG_PM_SLEEP_6B_H (REG_PM_SLEEP_BASE + 0xD7) 317 #define REG_PM_SLEEP_6C_L (REG_PM_SLEEP_BASE + 0xD8) 318 #define REG_PM_SLEEP_6C_H (REG_PM_SLEEP_BASE + 0xD9) 319 #define REG_PM_SLEEP_6D_L (REG_PM_SLEEP_BASE + 0xDA) 320 #define REG_PM_SLEEP_6D_H (REG_PM_SLEEP_BASE + 0xDB) 321 #define REG_PM_SLEEP_6E_L (REG_PM_SLEEP_BASE + 0xDC) 322 #define REG_PM_SLEEP_6E_H (REG_PM_SLEEP_BASE + 0xDD) 323 #define REG_PM_SLEEP_6F_L (REG_PM_SLEEP_BASE + 0xDE) 324 #define REG_PM_SLEEP_6F_H (REG_PM_SLEEP_BASE + 0xDF) 325 #define REG_PM_SLEEP_70_L (REG_PM_SLEEP_BASE + 0xE0) 326 #define REG_PM_SLEEP_70_H (REG_PM_SLEEP_BASE + 0xE1) 327 #define REG_PM_SLEEP_71_L (REG_PM_SLEEP_BASE + 0xE2) 328 #define REG_PM_SLEEP_71_H (REG_PM_SLEEP_BASE + 0xE3) 329 #define REG_PM_SLEEP_72_L (REG_PM_SLEEP_BASE + 0xE4) 330 #define REG_PM_SLEEP_72_H (REG_PM_SLEEP_BASE + 0xE5) 331 #define REG_PM_SLEEP_73_L (REG_PM_SLEEP_BASE + 0xE6) 332 #define REG_PM_SLEEP_73_H (REG_PM_SLEEP_BASE + 0xE7) 333 #define REG_PM_SLEEP_74_L (REG_PM_SLEEP_BASE + 0xE8) 334 #define REG_PM_SLEEP_74_H (REG_PM_SLEEP_BASE + 0xE9) 335 #define REG_PM_SLEEP_75_L (REG_PM_SLEEP_BASE + 0xEA) 336 #define REG_PM_SLEEP_75_H (REG_PM_SLEEP_BASE + 0xEB) 337 #define REG_PM_SLEEP_76_L (REG_PM_SLEEP_BASE + 0xEC) 338 #define REG_PM_SLEEP_76_H (REG_PM_SLEEP_BASE + 0xED) 339 #define REG_PM_SLEEP_77_L (REG_PM_SLEEP_BASE + 0xEE) 340 #define REG_PM_SLEEP_77_H (REG_PM_SLEEP_BASE + 0xEF) 341 #define REG_PM_SLEEP_78_L (REG_PM_SLEEP_BASE + 0xF0) 342 #define REG_PM_SLEEP_78_H (REG_PM_SLEEP_BASE + 0xF1) 343 #define REG_PM_SLEEP_79_L (REG_PM_SLEEP_BASE + 0xF2) 344 #define REG_PM_SLEEP_79_H (REG_PM_SLEEP_BASE + 0xF3) 345 #define REG_PM_SLEEP_7A_L (REG_PM_SLEEP_BASE + 0xF4) 346 #define REG_PM_SLEEP_7A_H (REG_PM_SLEEP_BASE + 0xF5) 347 #define REG_PM_SLEEP_7B_L (REG_PM_SLEEP_BASE + 0xF6) 348 #define REG_PM_SLEEP_7B_H (REG_PM_SLEEP_BASE + 0xF7) 349 #define REG_PM_SLEEP_7C_L (REG_PM_SLEEP_BASE + 0xF8) 350 #define REG_PM_SLEEP_7C_H (REG_PM_SLEEP_BASE + 0xF9) 351 #define REG_PM_SLEEP_7D_L (REG_PM_SLEEP_BASE + 0xFA) 352 #define REG_PM_SLEEP_7D_H (REG_PM_SLEEP_BASE + 0xFB) 353 #define REG_PM_SLEEP_7E_L (REG_PM_SLEEP_BASE + 0xFC) 354 #define REG_PM_SLEEP_7E_H (REG_PM_SLEEP_BASE + 0xFD) 355 #define REG_PM_SLEEP_7F_L (REG_PM_SLEEP_BASE + 0xFE) 356 #define REG_PM_SLEEP_7F_H (REG_PM_SLEEP_BASE + 0xFF) 357 358 //============================================================= 359 //PM TOP 360 //#define REG_PM_TOP_BASE 0x001E00UL 361 #define REG_PM_TOP_BANK_01_L (REG_PM_TOP_BASE + 0x02) 362 #define REG_PM_TOP_BANK_01_H (REG_PM_TOP_BASE + 0x03) 363 364 //============================================================= 365 //PM EFUSE 366 //#define REG_EFUSE_BASE 0x002000UL 367 #define REG_PM_EFUSE_28_L (REG_EFUSE_BASE + 0x50) 368 #define REG_PM_EFUSE_28_H (REG_EFUSE_BASE + 0x51) 369 #define REG_PM_EFUSE_2C_L (REG_EFUSE_BASE + 0x58) 370 #define REG_PM_EFUSE_2C_H (REG_EFUSE_BASE + 0x59) 371 #define REG_PM_EFUSE_2D_L (REG_EFUSE_BASE + 0x5A) 372 #define REG_PM_EFUSE_2D_H (REG_EFUSE_BASE + 0x5B) 373 374 //============================================================= 375 //PM MISC 376 //#define REG_PM_MISC_BASE 0x002E00UL 377 #define REG_PM_MISC_62_L (REG_PM_MISC_BASE + 0xC4) 378 379 380 #endif 381 382