1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_TBL_H_ 80 #define _LPLL_TBL_H_ 81 82 #define LPLL_REG_NUM 23 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_TTL_75to150MHz, //0 87 E_PNL_SUPPORTED_LPLL_TTL_50to75MHz, //1 88 E_PNL_SUPPORTED_LPLL_TTL_25to50MHz, //2 89 E_PNL_SUPPORTED_LPLL_TTL_25to25MHz, //3 90 91 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz, //4 92 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz, //5 93 94 E_PNL_SUPPORTED_LPLL_LVDS_2CH_115to150MHz, //6 95 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to115MHz, //7 96 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to50MHz, //8 97 98 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz, //9 99 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz, //10 100 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz, //11 101 102 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz, //12 103 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to50MHz, //13 104 105 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz, //14 106 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz, //15 107 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to50MHz, //16 108 109 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz, //17 110 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz, //18 111 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to50MHz, //19 112 113 E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz, //20 114 E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to66_67MHz, //21 115 E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to50MHz, //22 116 117 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz, //23 118 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz, //24 119 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz, //25 120 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to50MHz, //26 121 122 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz, //27 123 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz, //28 124 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz, //29 125 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to50MHz, //30 126 127 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_114to150MHz, //31 128 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to114MHz, //32 129 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to80MHz, //33 130 131 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to150MHz, //34 132 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to80MHz, //35 133 134 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_114to150MHz, //36 135 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to114MHz, //37 136 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to80MHz, //38 137 138 E_PNL_SUPPORTED_LPLL_MAX, //39 139 } E_PNL_SUPPORTED_LPLL_TYPE; 140 141 typedef struct 142 { 143 MS_U8 address; 144 MS_U16 value; 145 MS_U16 mask; 146 }TBLStruct,*pTBLStruct; 147 148 TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= 149 { 150 { //E_PNL_SUPPORTED_LPLL_TTL_75to150MHz NO.0 151 //Address,Value,Mask 152 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 153 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 154 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 155 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 156 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 157 {0x02,0x0500,0x0F00},//reg_lpll1_output_div_second[3:0] 158 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 159 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 160 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 161 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 162 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 163 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 164 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 165 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 166 {0x33,0x0020,0x0020},//reg_lpll2_pd 167 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 168 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 169 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 170 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 171 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 172 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 173 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 174 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 175 }, 176 177 { //E_PNL_SUPPORTED_LPLL_TTL_50to75MHz NO.1 178 //Address,Value,Mask 179 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 180 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 181 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 182 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 183 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 184 {0x02,0x0500,0x0F00},//reg_lpll1_output_div_second[3:0] 185 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 186 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 187 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 188 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 189 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 190 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 191 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 192 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 193 {0x33,0x0020,0x0020},//reg_lpll2_pd 194 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 195 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 196 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 197 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 198 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 199 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 200 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 201 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 202 }, 203 204 { //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 205 //Address,Value,Mask 206 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 207 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 208 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 209 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 210 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 211 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 212 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 213 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 214 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 215 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 216 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 217 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 218 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 219 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 220 {0x33,0x0020,0x0020},//reg_lpll2_pd 221 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 222 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 223 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 224 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 225 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 226 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 227 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 228 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 229 }, 230 231 { //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 232 //Address,Value,Mask 233 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 234 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 235 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 236 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 237 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 238 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 239 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 240 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 241 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 242 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 243 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 244 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 245 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 246 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 247 {0x33,0x0020,0x0020},//reg_lpll2_pd 248 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 249 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 250 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 251 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 252 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 253 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 254 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 255 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 256 }, 257 258 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.4 259 //Address,Value,Mask 260 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 261 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 262 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 263 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 264 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 265 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 266 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 267 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 268 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 269 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 270 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 271 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 272 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 273 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 274 {0x33,0x0020,0x0020},//reg_lpll2_pd 275 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 276 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 277 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 278 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 279 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 280 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 281 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 282 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 283 }, 284 285 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.5 286 //Address,Value,Mask 287 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 288 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 289 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 290 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 291 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 292 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 293 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 294 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 295 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 296 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 297 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 298 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 299 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 300 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 301 {0x33,0x0020,0x0020},//reg_lpll2_pd 302 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 303 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 304 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 305 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 306 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 307 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 308 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 309 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 310 }, 311 312 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_115to150MHz NO.6 313 //Address,Value,Mask 314 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 315 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 316 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 317 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 318 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[5:4] 319 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 320 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 321 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 322 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 323 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 324 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 325 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 326 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 327 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 328 {0x33,0x0020,0x0020},//reg_lpll2_pd 329 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 330 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 331 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 332 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 333 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 334 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 335 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 336 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 337 }, 338 339 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to115MHz NO.7 340 //Address,Value,Mask 341 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 342 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 343 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 344 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 345 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 346 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 347 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 348 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 349 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 350 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 351 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 352 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 353 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 354 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 355 {0x33,0x0020,0x0020},//reg_lpll2_pd 356 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 357 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 358 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 359 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 360 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 361 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 362 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 363 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 364 }, 365 366 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to50MHz NO.8 367 //Address,Value,Mask 368 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 369 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 370 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 371 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 372 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 373 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 374 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 375 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 376 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 377 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 378 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 379 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 380 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 381 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 382 {0x33,0x0020,0x0020},//reg_lpll2_pd 383 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 384 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 385 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 386 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 387 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 388 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 389 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 390 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 391 }, 392 393 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.9 394 //Address,Value,Mask 395 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 396 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 397 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 398 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 399 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[5:4] 400 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 401 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 402 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 403 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 404 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 405 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 406 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 407 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 408 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 409 {0x33,0x0020,0x0020},//reg_lpll2_pd 410 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 411 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 412 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 413 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 414 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 415 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 416 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 417 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 418 }, 419 420 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.10 421 //Address,Value,Mask 422 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 423 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 424 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 425 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 426 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 427 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 428 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 429 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 430 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 431 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 432 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 433 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 434 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 435 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 436 {0x33,0x0020,0x0020},//reg_lpll2_pd 437 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 438 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 439 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 440 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 441 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 442 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 443 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 444 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 445 }, 446 447 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.11 448 //Address,Value,Mask 449 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 450 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 451 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 452 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 453 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 454 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 455 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 456 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 457 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 458 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 459 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 460 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 461 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 462 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 463 {0x33,0x0020,0x0020},//reg_lpll2_pd 464 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 465 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 466 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 467 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 468 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 469 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 470 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 471 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 472 }, 473 474 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.12 475 //Address,Value,Mask 476 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 477 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 478 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 479 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 480 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 481 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 482 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 483 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 484 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 485 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 486 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 487 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 488 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 489 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 490 {0x33,0x0020,0x0020},//reg_lpll2_pd 491 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 492 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 493 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 494 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 495 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 496 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 497 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 498 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 499 }, 500 501 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to50MHz NO.13 502 //Address,Value,Mask 503 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 504 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 505 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 506 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 507 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 508 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 509 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 510 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 511 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 512 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 513 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 514 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 515 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 516 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 517 {0x33,0x0020,0x0020},//reg_lpll2_pd 518 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 519 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 520 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 521 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 522 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 523 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 524 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 525 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 526 }, 527 528 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.14 529 //Address,Value,Mask 530 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 531 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 532 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 533 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 534 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 535 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 536 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 537 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 538 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 539 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 540 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 541 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 542 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 543 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 544 {0x33,0x0020,0x0020},//reg_lpll2_pd 545 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 546 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 547 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 548 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 549 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 550 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 551 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 552 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 553 }, 554 555 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.15 556 //Address,Value,Mask 557 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 558 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 559 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 560 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 561 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 562 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 563 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 564 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 565 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 566 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 567 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 568 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 569 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 570 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 571 {0x33,0x0020,0x0020},//reg_lpll2_pd 572 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 573 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 574 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 575 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 576 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 577 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 578 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 579 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 580 }, 581 582 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to50MHz NO.16 583 //Address,Value,Mask 584 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 585 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 586 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 587 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 588 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 589 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 590 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 591 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 592 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 593 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 594 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 595 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 596 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 597 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 598 {0x33,0x0020,0x0020},//reg_lpll2_pd 599 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 600 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 601 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 602 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 603 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 604 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 605 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 606 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 607 }, 608 609 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.17 610 //Address,Value,Mask 611 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 612 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 613 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 614 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 615 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 616 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 617 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 618 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 619 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 620 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 621 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 622 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 623 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 624 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 625 {0x33,0x0020,0x0020},//reg_lpll2_pd 626 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 627 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 628 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 629 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 630 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 631 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 632 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 633 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 634 }, 635 636 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.18 637 //Address,Value,Mask 638 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 639 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 640 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 641 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 642 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 643 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 644 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 645 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 646 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 647 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 648 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 649 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 650 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 651 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 652 {0x33,0x0020,0x0020},//reg_lpll2_pd 653 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 654 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 655 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 656 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 657 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 658 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 659 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 660 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 661 }, 662 663 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to50MHz NO.19 664 //Address,Value,Mask 665 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 666 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 667 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 668 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 669 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 670 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 671 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 672 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 673 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 674 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 675 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 676 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 677 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 678 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 679 {0x33,0x0020,0x0020},//reg_lpll2_pd 680 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 681 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 682 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 683 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 684 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 685 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 686 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 687 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 688 }, 689 690 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz NO.20 691 //Address,Value,Mask 692 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 693 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 694 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 695 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 696 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 697 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 698 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 699 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 700 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 701 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 702 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 703 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 704 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 705 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 706 {0x33,0x0020,0x0020},//reg_lpll2_pd 707 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 708 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 709 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 710 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 711 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 712 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 713 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 714 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 715 }, 716 717 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to66_67MHz NO.21 718 //Address,Value,Mask 719 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 720 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 721 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 722 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 723 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 724 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 725 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 726 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 727 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 728 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 729 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 730 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 731 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 732 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 733 {0x33,0x0020,0x0020},//reg_lpll2_pd 734 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 735 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 736 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 737 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 738 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 739 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 740 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 741 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 742 }, 743 744 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to50MHz NO.22 745 //Address,Value,Mask 746 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 747 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 748 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 749 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 750 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 751 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 752 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 753 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 754 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 755 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 756 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 757 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 758 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 759 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 760 {0x33,0x0020,0x0020},//reg_lpll2_pd 761 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 762 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 763 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 764 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 765 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 766 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 767 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 768 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 769 }, 770 771 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.23 772 //Address,Value,Mask 773 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 774 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 775 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 776 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 777 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 778 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 779 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 780 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 781 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 782 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 783 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 784 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 785 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 786 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 787 {0x33,0x0020,0x0020},//reg_lpll2_pd 788 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 789 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 790 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 791 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 792 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 793 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 794 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 795 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 796 }, 797 798 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.24 799 //Address,Value,Mask 800 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 801 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 802 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 803 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 804 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 805 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 806 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 807 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 808 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 809 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 810 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 811 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 812 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 813 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 814 {0x33,0x0020,0x0020},//reg_lpll2_pd 815 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 816 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 817 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 818 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 819 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 820 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 821 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 822 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 823 }, 824 825 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.25 826 //Address,Value,Mask 827 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 828 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 829 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 830 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 831 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 832 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 833 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 834 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 835 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 836 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 837 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 838 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 839 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 840 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 841 {0x33,0x0020,0x0020},//reg_lpll2_pd 842 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 843 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 844 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 845 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 846 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 847 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 848 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 849 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 850 }, 851 852 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to50MHz NO.26 853 //Address,Value,Mask 854 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 855 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 856 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 857 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 858 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 859 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 860 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 861 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 862 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 863 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 864 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 865 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 866 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 867 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 868 {0x33,0x0020,0x0020},//reg_lpll2_pd 869 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 870 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 871 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 872 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 873 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 874 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 875 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 876 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 877 }, 878 879 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz NO.27 880 //Address,Value,Mask 881 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 882 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 883 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 884 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 885 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 886 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 887 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 888 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 889 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 890 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 891 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 892 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 893 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 894 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 895 {0x33,0x0020,0x0020},//reg_lpll2_pd 896 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 897 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 898 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 899 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 900 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 901 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 902 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 903 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 904 }, 905 906 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz NO.28 907 //Address,Value,Mask 908 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 909 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 910 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 911 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 912 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 913 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 914 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 915 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 916 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 917 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 918 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 919 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 920 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 921 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 922 {0x33,0x0020,0x0020},//reg_lpll2_pd 923 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 924 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 925 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 926 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 927 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 928 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 929 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 930 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 931 }, 932 933 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz NO.29 934 //Address,Value,Mask 935 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 936 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 937 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 938 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 939 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 940 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 941 {0x35,0x4000,0x7000},//reg_lpll1_skew_div 942 {0x2E,0x0003,0x0007},//reg_lpll1_fifo_div 943 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 944 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 945 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 946 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 947 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 948 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 949 {0x33,0x0020,0x0020},//reg_lpll2_pd 950 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 951 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 952 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 953 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 954 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 955 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 956 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 957 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 958 }, 959 960 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to50MHz NO.30 961 //Address,Value,Mask 962 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 963 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 964 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 965 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 966 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 967 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 968 {0x35,0x4000,0x7000},//reg_lpll1_skew_div 969 {0x2E,0x0003,0x0007},//reg_lpll1_fifo_div 970 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 971 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 972 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 973 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 974 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 975 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 976 {0x33,0x0020,0x0020},//reg_lpll2_pd 977 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 978 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 979 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 980 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 981 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 982 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 983 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 984 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 985 }, 986 987 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_114to150MHz NO.31 988 //Address,Value,Mask 989 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 990 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 991 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 992 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 993 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[5:4] 994 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 995 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 996 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 997 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 998 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 999 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1000 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1001 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1002 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1003 {0x33,0x0000,0x0020},//reg_lpll2_pd 1004 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1005 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1006 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1007 {0x31,0x0600,0x1F00},//reg_lpll2_loop_div_second 1008 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1009 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1010 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1011 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1012 }, 1013 1014 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to114MHz NO.32 1015 //Address,Value,Mask 1016 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1017 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1018 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1019 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1020 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 1021 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 1022 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1023 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1024 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1025 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1026 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1027 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1028 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1029 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1030 {0x33,0x0000,0x0020},//reg_lpll2_pd 1031 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1032 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1033 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1034 {0x31,0x0600,0x1F00},//reg_lpll2_loop_div_second 1035 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1036 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1037 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1038 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1039 }, 1040 1041 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to80MHz NO.33 1042 //Address,Value,Mask 1043 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1044 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1045 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1046 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1047 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 1048 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 1049 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1050 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1051 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1052 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1053 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1054 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1055 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1056 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1057 {0x33,0x0000,0x0020},//reg_lpll2_pd 1058 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1059 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1060 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1061 {0x31,0x0600,0x1F00},//reg_lpll2_loop_div_second 1062 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1063 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1064 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1065 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1066 }, 1067 1068 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to150MHz NO.34 1069 //Address,Value,Mask 1070 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1071 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1072 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1073 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1074 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1075 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1076 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1077 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1078 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1079 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1080 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1081 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1082 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1083 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1084 {0x33,0x0000,0x0020},//reg_lpll2_pd 1085 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1086 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1087 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1088 {0x31,0x0600,0x1F00},//reg_lpll2_loop_div_second 1089 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1090 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1091 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1092 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1093 }, 1094 1095 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to80MHz NO.35 1096 //Address,Value,Mask 1097 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1098 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1099 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1100 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1101 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1102 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1103 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1104 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1105 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1106 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1107 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1108 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1109 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1110 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1111 {0x33,0x0000,0x0020},//reg_lpll2_pd 1112 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1113 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1114 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1115 {0x31,0x0600,0x1F00},//reg_lpll2_loop_div_second 1116 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1117 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1118 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1119 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1120 }, 1121 1122 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_114to150MHz NO.36 1123 //Address,Value,Mask 1124 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1125 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1126 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1127 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1128 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[5:4] 1129 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 1130 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1131 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1132 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1133 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1134 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1135 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1136 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1137 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1138 {0x33,0x0000,0x0020},//reg_lpll2_pd 1139 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1140 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1141 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1142 {0x31,0x0600,0x1F00},//reg_lpll2_loop_div_second 1143 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1144 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1145 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1146 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1147 }, 1148 1149 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to114MHz NO.37 1150 //Address,Value,Mask 1151 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1152 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1153 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1154 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1155 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 1156 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 1157 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1158 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1159 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1160 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1161 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1162 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1163 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1164 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1165 {0x33,0x0000,0x0020},//reg_lpll2_pd 1166 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1167 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1168 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1169 {0x31,0x0600,0x1F00},//reg_lpll2_loop_div_second 1170 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1171 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1172 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1173 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1174 }, 1175 1176 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to80MHz NO.38 1177 //Address,Value,Mask 1178 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1179 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1180 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1181 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1182 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 1183 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 1184 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1185 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1186 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1187 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1188 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1189 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1190 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1191 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1192 {0x33,0x0000,0x0020},//reg_lpll2_pd 1193 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1194 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1195 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1196 {0x31,0x0600,0x1F00},//reg_lpll2_loop_div_second 1197 {0x32,0x0002,0x000F},//reg_lpll2_output_div_first 1198 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1199 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1200 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1201 }, 1202 1203 }; 1204 MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= 1205 { 1206 12, //E_PNL_SUPPORTED_LPLL_TTL_75to150MHz NO.0 1207 12, //E_PNL_SUPPORTED_LPLL_TTL_50to75MHz NO.1 1208 12, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 1209 12, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 1210 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.4 1211 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.5 1212 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_115to150MHz NO.6 1213 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to115MHz NO.7 1214 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to50MHz NO.8 1215 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.9 1216 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.10 1217 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.11 1218 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.12 1219 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to50MHz NO.13 1220 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.14 1221 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.15 1222 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to50MHz NO.16 1223 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.17 1224 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.18 1225 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to50MHz NO.19 1226 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz NO.20 1227 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to66_67MHz NO.21 1228 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to50MHz NO.22 1229 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.23 1230 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.24 1231 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.25 1232 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to50MHz NO.26 1233 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz NO.27 1234 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz NO.28 1235 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz NO.29 1236 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to50MHz NO.30 1237 12, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_114to150MHz NO.31 1238 6, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to114MHz NO.32 1239 6, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to80MHz NO.33 1240 9, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to150MHz NO.34 1241 9, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to80MHz NO.35 1242 12, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_114to150MHz NO.36 1243 6, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to114MHz NO.37 1244 6, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to80MHz NO.38 1245 }; 1246 MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= 1247 { 1248 10, //E_PNL_SUPPORTED_LPLL_TTL_75to150MHz NO.0 1249 20, //E_PNL_SUPPORTED_LPLL_TTL_50to75MHz NO.1 1250 28, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 1251 28, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 1252 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.4 1253 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.5 1254 7, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_115to150MHz NO.6 1255 14, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to115MHz NO.7 1256 14, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to50MHz NO.8 1257 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_115to150MHz NO.9 1258 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to115MHz NO.10 1259 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.11 1260 16, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.12 1261 16, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to50MHz NO.13 1262 8, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.14 1263 16, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.15 1264 16, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to50MHz NO.16 1265 8, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.17 1266 16, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.18 1267 16, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to50MHz NO.19 1268 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_66_67to80MHz NO.20 1269 24, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to66_67MHz NO.21 1270 24, //E_PNL_SUPPORTED_LPLL_MINILVDS_1BK_3PAIR_6BIT_50to50MHz NO.22 1271 6, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.23 1272 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.24 1273 24, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.25 1274 24, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to50MHz NO.26 1275 6, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133to150MHz NO.27 1276 12, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_67to133MHz NO.28 1277 24, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to67MHz NO.29 1278 24, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to50MHz NO.30 1279 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_114to150MHz NO.31 1280 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to114MHz NO.32 1281 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_4PAIR_80to80MHz NO.33 1282 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to150MHz NO.34 1283 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_80to80MHz NO.35 1284 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_114to150MHz NO.36 1285 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to114MHz NO.37 1286 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_80to80MHz NO.38 1287 }; 1288 1289 #endif //_LPLL_TBL_H_ 1290