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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef MHAL_FRC_H 96 #define MHAL_FRC_H 97 98 #include "hwreg_frc_map.h" 99 #include "hwreg_frc.h" 100 #include "hwreg_sc.h" 101 102 #ifdef MHAL_FRC_C 103 #define INTERFACE 104 #else 105 #define INTERFACE extern 106 #endif 107 108 //------------------------------------------------------------------------------------------------- 109 // Macro and Define 110 //------------------------------------------------------------------------------------------------- 111 #define FRC_MIU1_MEM_ADDR 0x20000000 112 #define CRYSTAL_CLOCK 12000000ul//24000000ul 113 #define MST_CLOCK_HZ CRYSTAL_CLOCK 114 #define MST_CLOCK_KHZ (MST_CLOCK_HZ / 1000) 115 #define MST_CLOCK_MHZ (MST_CLOCK_KHZ / 1000) 116 #define FRC_MAP_REG(reg) (((reg)>>8)&0xFF), ((reg)&0xFF) 117 #define FRC_IP_ALL 0xff 118 #define FRC_IP_NULL 0xff 119 #define REG_ADDR_SIZE 2 120 #define REG_MASK_SIZE 1 121 //#define REG_TABLE_END 0xFFFF 122 #define _END_OF_TBL_ 0xFFFF 123 #define MS_ALG_CMD_LEN 16 124 #define FRC_BK_SWITCH(_x_)\ 125 MDrv_WriteByte(REG_FRC_BANK_BASE, _x_) 126 #define FRC_BK_CURRENT \ 127 MDrv_ReadByte(REG_FRC_BANK_BASE) 128 129 #define VSTART_OFFSET 2 130 #define VSYNCSTART_OFFSET 14 131 #define VSYNC_FRONT_PORCH 11 132 133 #define FRC_Y_TRIGGER_DELAY 70 134 #define FRC_Y_TRIGGER_DELAY_RGB 10 135 136 #ifdef PATCH_TCON_BRING_UP 137 #define VSYNC_OFFSET_FOR_UD_VB1_8LANE_DRDEPI 65 138 #define FRC_Y_TRIGGER_START_OFFSET_YUV_FOR_UD_VB1_8LANE_DRDEPI 69 139 #define FRC_Y_TRIGGER_START_OFFSET_RGB_FOR_UD_VB1_8LANE_DRDEPI 10 140 #define FRC_TGEN_VSYNC_START_FOR_UD_VB1_8LANE_DRDEPI 1 141 #define FRC_TGEN_VSYNC_END_FOR_UD_VB1_8LANE_DRDEPI 3 142 #endif 143 144 #define FRCR2_MBX_QUEUESIZE 10 145 146 #define GOP_FSC_FHD_OFFSET_H 0x02 147 #define GOP_FSC_FHD_OFFSET_V 0x0C 148 #define GOP_FSC_4K_OFFSET_H 0x02 149 #define GOP_FSC_4K_OFFSET_V 0x0C 150 #define GOP_NO_FSC_OFFSET_H 0x00 151 #define GOP_NO_FSC_OFFSET_V 0x00 152 153 typedef struct 154 { 155 MS_U8 *pIPTable; 156 MS_U8 u8TabNums; 157 MS_U8 u8TabIdx; 158 } EN_FRC_IP_Info; 159 160 typedef struct 161 { 162 MS_U8 *pIPTable; 163 MS_U8 u8TabNums; 164 } EN_FRC_IPTAB_INFO; 165 166 typedef struct __attribute__((packed)) 167 { 168 MS_U8 u8FRC_InputType_Num; 169 MS_U8 u8FRC_IP_Num; 170 }FRCTABLE_INFO; 171 172 173 typedef enum 174 { 175 E_FRC_op2_gamma_table = 1, // gamma table 176 E_FRC_od_table = 2, // OD table 177 E_FRC_ld_table = 3, // Local diming table 178 } FRC_CLIENT_TABLE; 179 180 //------------------------------------------------------------------------------------------------- 181 // Structure enum 182 //------------------------------------------------------------------------------------------------- 183 184 typedef enum 185 { 186 FRC_IP_MEM_IP_YC_8 = 0x00, 187 FRC_IP_MEM_IP_YC_10 = 0x01, 188 FRC_IP_MEM_IP_RGB_8 = 0x02, 189 FRC_IP_MEM_IP_RGB_10 = 0x03, 190 FRC_IP_MEM_IP_YC_10_SPECIAL = 0x04, 191 FRC_IP_MEM_IP_YUV_8 = 0x05, 192 FRC_IP_MEM_IP_RGB_10_SPECIAL = 0x06, 193 FRC_IP_MEM_IP_YUV_10_SPECIAL = 0x07 194 195 } FRC_IP_MEM_MODE_e; 196 197 typedef enum 198 { 199 FRC_MIRROR_OFF, 200 FRC_MIRROR_H_MODE, 201 FRC_MIRROR_V_MODE, 202 FRC_MIRROR_HV_MODE 203 } FRC_MirrorModeType_e; 204 205 typedef struct MST_PANEL_INFO_s 206 { 207 // Basic 208 MS_U16 u16HStart; //ursa scaler 209 MS_U16 u16VStart; //ursa scaler 210 MS_U16 u16Width; //ursa scaler 211 MS_U16 u16Height; //ursa scaler 212 MS_U16 u16HTotal; //ursa scaler 213 MS_U16 u16VTotal; //ursa scaler 214 215 MS_U16 u16DE_VStart; 216 217 MS_U16 u16DefaultVFreq; 218 219 // LPLL 220 MS_U16 u16LPLL_InputDiv; 221 MS_U16 u16LPLL_LoopDiv; 222 MS_U16 u16LPLL_OutputDiv; 223 224 MS_U8 u8LPLL_Type; 225 MS_U8 u8LPLL_Mode; 226 227 // sync 228 MS_U8 u8HSyncWidth; 229 MS_BOOL bPnlDblVSync; 230 231 // output control 232 MS_U16 u16OCTRL; 233 MS_U16 u16OSTRL; 234 MS_U16 u16ODRV; 235 MS_U16 u16DITHCTRL; 236 237 // MOD 238 MS_U16 u16MOD_CTRL0; // BIT2: tiMode, BIT5: lvdsSwapPol, BIT6: lvdsSwapCh 239 MS_U8 u8MOD_CTRL2; 240 MS_U16 u16MOD_CTRL9; 241 MS_U16 u16MOD_CTRLA; // BIT2: invertDE, BIT3: invertVS, BIT12: invertHS 242 MS_U8 u8MOD_CTRLB; // BIT0~1: panelBitNums 243 244 MS_U8 u8MOD_CTRL77; //pre-emphasis level 245 MS_U8 u8MOD_CTRL78; 246 //LGE [vivakjh] 2008/11/12 Add for DVB PDP Panel 247 //Additional Info.(V Total) 248 MS_U16 u16VTotal60Hz; //ursa scaler 249 MS_U16 u16VTotal50Hz; //ursa scaler 250 MS_U16 u16VTotal48Hz; //ursa scaler 251 //[vivakjh] 2008/12/23 Add for adjusting the MRE in PDP S6 252 MS_U16 u16VStart60Hz; 253 MS_U16 u16VStart50Hz; 254 MS_U16 u16VStart48Hz; 255 MS_U16 u16VBackPorch60Hz; 256 MS_U16 u16VBackPorch50Hz; 257 MS_U16 u16VBackPorch48Hz; 258 259 /*Panel Option 260 0: LCD 261 1: PDP 262 2: LCD_NO_FRC 263 3: LCD_TCON 264 */ 265 MS_U8 u8LCDorPDP; 266 267 MS_U32 u32LimitD5d6d7; //thchen 20081216 268 MS_U16 u16LimitOffset; //thchen 20081216 269 MS_U8 u8LvdsSwingUp; 270 MS_BOOL bTTL_10BIT; 271 MS_BOOL bOD_DataPath; 272 273 //------------------------------------------------------------------------------------------------- 274 // FRC Control 275 //------------------------------------------------------------------------------------------------- 276 MS_BOOL bFRC; 277 MS_U16 u16MOD_SwingLevel; 278 MS_U16 u16MOD_SwingCLK; 279 MS_U16 u16output_cfg_10; 280 MS_U16 u16output_cfg_11; 281 MS_U16 u16output_cfg_12; 282 MS_U8 u8output_cfg_13; 283 MS_U8 u8PanelNoiseDith; 284 MS_U8 u8lvdsSwapCh; 285 MS_U8 u8FRC3DPanelType; 286 287 MS_BOOL bdither6Bits; 288 MS_BOOL blvdsShiftPair; 289 MS_BOOL blvdsSwapPair; 290 291 // TGEN 292 MS_U16 u16HSyncStart; 293 MS_U16 u16HSyncEnd; 294 MS_U16 u16VSyncStart; 295 MS_U16 u16VSyncEnd; 296 MS_U16 u16VTrigX; 297 MS_U16 u16VTrigY; 298 299 // EPI 300 MS_BOOL bepiLRSwap; 301 MS_BOOL bepiLMirror; 302 MS_BOOL bepiRMirror; 303 304 } MST_PANEL_INFO_t, *PMST_PANEL_INFO_t; 305 306 // for composer setting 307 typedef enum 308 { 309 E_FRC_COMPOSER_SOURCE_MODE_VIP = 0, // only STGEN disable case use this! 310 E_FRC_COMPOSER_SOURCE_MODE_FSC = 1, 311 E_FRC_COMPOSER_SOURCE_MODE_FRC = 2, 312 E_FRC_COMPOSER_SOURCE_MODE_VIP_FB = 3, 313 } E_FRC_COMPOSER_SOURCE_MODE; 314 315 typedef enum 316 { 317 E_FRC_PIPE_DELAY_MODE_FIXED = 0, 318 E_FRC_PIPE_DELAY_MODE_USER = 1, 319 E_FRC_PIPE_DELAY_MODE_AUTO = 2, 320 } E_FRC_PIPE_DELAY_MODE; 321 322 typedef enum 323 { 324 E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_IP = 0, // with FRC case 325 E_FRC_TGEN_LOCK_SOURCE_MODE_FROM_TGEN = 1, // no FRC case 326 } E_FRC_TGEN_LOCK_SOURCE_MODE; 327 328 typedef enum 329 { 330 E_FRC_STGEN_ODCLK_1 = 0, // ODLCK 331 E_FRC_STGEN_ODCLK_N = 1, // ODLCK div N 332 E_FRC_STGEN_ODCLK_2 = 2, // ODLCK/2 333 E_FRC_STGEN_ODCLK_4 = 3, // ODCLK/4 334 } E_FRC_STGEN_ODCLK; 335 336 typedef enum 337 { 338 E_FSC_IDCLK_1 = 0, // ODLCK 339 E_FSC_IDCLK_2 = 1, // ODLCK/2 340 E_FSC_IDCLK_4 = 2, // ODCLK/4 341 } E_FSC_IDCLK; 342 343 typedef enum 344 { 345 E_FRC_FSC_SOURCE_MODE_MDE = 0, // vip to fsc's de selection use MDE 346 E_FRC_FSC_SOURCE_MODE_FDE = 1, 347 } E_FRC_FSC_SOURCE_MODE; 348 349 typedef enum 350 { 351 E_FRC_MLOAD_TRIG_MODE_FROM_OP1 = 0, // no FRC case, menuload trig form stgen(FSC is enabled) 352 E_FRC_MLOAD_TRIG_MODE_FROM_OP2 = 1, // 1. with FRC case 2. no FRC and no FSC case, menuload trig form tgen 353 } E_FRC_MLOAD_TRIG_MODE; 354 355 typedef enum 356 { 357 /// MEMC level off 358 MEMC_LEVEL_OFF, 359 /// MEMC level low 360 MEMC_LEVEL_LOW, 361 /// MEMC level middle 362 MEMC_LEVEL_MID, 363 /// MEMC level high 364 MEMC_LEVEL_HIGH, 365 /// MEMC level bypass, its same as bypass 64 mode 366 MEMC_LEVEL_BYPASS, 367 /// MEMC level bypass 64, one kind framerate converter of bypass. 368 MEMC_LEVEL_BYPASS_64 = MEMC_LEVEL_BYPASS, 369 /// MEMC level bypass 55, one kind framerate convertr of bypass. 370 MEMC_LEVEL_BYPASS_55, 371 }E_MEMC_LEVEL; 372 373 #define PIP_DELAY_COUNTER_RESET (BIT(3)) // BK68_50_L [3] 374 //------------------------------------------------------------------------------------------------- 375 // Function and Variable 376 //------------------------------------------------------------------------------------------------- 377 #define MHal_FRC_IsRGB(args...) 0 378 379 #define MHal_FRC_TGEN_SWReset(args...) 380 INTERFACE void MHal_FRC_TGEN_DoubleBuf(void *pInstance, MS_BOOL bEnDis); 381 INTERFACE void MHal_FRC_TGEN_SetVTotal(void *pInstance, MS_U16 u16VTotal); 382 INTERFACE void MHal_FRC_TGEN_SetHTotal(void *pInstance, MS_U16 u16HTotal); 383 #define MHal_FRC_TGEN_SetVTrigY(args...) 384 #define MHal_FRC_TGEN_SetVTrigX(args...) 385 INTERFACE void MHal_FRC_TGEN_SetVSyncStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End); 386 INTERFACE void MHal_FRC_TGEN_SetHSyncStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End); 387 INTERFACE void MHal_FRC_TGEN_SetFdeStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End); 388 INTERFACE void MHal_FRC_TGEN_SetFdeStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End); 389 INTERFACE void MHal_FRC_TGEN_SetMdeStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End); 390 INTERFACE void MHal_FRC_TGEN_SetMdeStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End); 391 INTERFACE void MHal_FRC_TGEN_SetSubMdeStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End); 392 INTERFACE void MHal_FRC_TGEN_SetSubMdeStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End); 393 394 #define MHal_FRC_TGEN_FpllRefPointY(args...) 395 #define MHal_FRC_TGEN_1Clk2PixOut(args...) 396 #define MHal_FRC_TGEN_SetSyncHcnt(args...) 397 #define MHal_FRC_TGEN_SetClrSyncAhead(args...) 398 399 INTERFACE void MHal_FRC_TGEN_Init(void *pInstance); 400 INTERFACE void MHal_FRC_TGEN_Enable_LockMode(void *pInstance, MS_BOOL bEn); 401 INTERFACE void MHal_FRC_TGEN_Enable_Source_Select_Mode(void *pInstance, MS_BOOL bEn); 402 //INTERFACE void MHal_FRC_TGEN_Set_Lock_Source(void *pInstance, E_FRC_TGEN_LOCK_SOURCE_MODE eMode); 403 INTERFACE void MHal_FRC_TGEN_Enable_Lock_Source(void *pInstance, MS_BOOL bEn, E_FRC_TGEN_LOCK_SOURCE_MODE eMode, MS_BOOL bMenuload); 404 405 INTERFACE void MHal_FRC_SetYTrig(void *pInstance, MS_U16 u16Trig1, MS_U16 u16Trig2); 406 407 INTERFACE void MHal_FRC_Enable_MiuMask(void *pInstance); 408 INTERFACE void MHal_FRC_Disable_MiuMask(void *pInstance); 409 INTERFACE void MHal_FRC_set_miusel(void *pInstance, MS_U8 u8MIUSel); 410 411 #define MHal_FRC_IPM_SoftwareReset(args...) 412 #define MHal_FRC_IPM_RWEn(args...) 413 #define MHal_FRC_IPM_RW_CEN_Select(args...) 414 #define MHal_FRC_IPM_SetYuv10Bit(args...) 415 #define MHal_FRC_IPM_SetMr(args...) 416 #define MHal_FRC_IPM_SetMemoryMode(args...) 417 #define MHal_FRC_IPM_YC444To422Control(args...) 418 #define MHal_FRC_IPM_SetFrameBufferNum(args...) 419 #define MHal_FRC_IPM_CeLineCountEn(args...) 420 INTERFACE void MHal_FRC_IPM_SetBaseAddr(void *pInstance, MS_PHY addr, MS_U32 u32FrameYcout, MS_U16 u16FB_YcountLinePitch, MS_U8 u8MirrorMode ); 421 INTERFACE void MHal_FRC_IPM_R_SetBaseAddr(void *pInstance, MS_PHY addr); 422 #define MHal_FRC_IPM_SetIp2Mc(args...) 423 #define MHal_FRC_IPM_SetYCoutLinePitch(args...) 424 #define MHal_FRC_IPM_SetReadFetchNumber(args...) 425 #define MHal_FRC_IPM_SetWriteFetchNumber(args...) 426 #define MHal_FRC_IPM_SetRfifoThr(args...) 427 #define MHal_FRC_IPM_SetWfifoThr(args...) 428 #define MHal_FRC_IPM_SetReadLength(args...) 429 #define MHal_FRC_IPM_SetWriteLength(args...) 430 #define MHal_FRC_IPM_SetHTotalPixellimit(args...) 431 #define MHal_FRC_IPM_SetVTotalPixellimit(args...) 432 #define MHal_FRC_IPM_SetRmaskNum(args...) 433 #define MHal_FRC_IPM_SetWmaskNum(args...) 434 #define MHal_FRC_IPM_SetMirrorMode(args...) 435 #define MHal_FRC_IPM_PacketInitCnt(args...) 436 #define MHal_FRC_IPM_SetLvdsInputMode(args...) 437 #define MHal_FRC_IPM_SetOsdWinIdx(args...) 438 #define MHal_FRC_IPM_SetVPulseLineRst(args...) 439 #define MHal_FRC_IPM_SetVPulseLoc(args...) 440 #define MHal_FRC_IPM_SetLockIntCtrl(args...) 441 #define MHal_FRC_IPM_SetBlankBoundary(args...) 442 #define MHal_FRC_IPM_GetHTotal(args...) 0 443 #define MHal_FRC_IPM_GetVTotal(args...) 0 444 #define MHal_FRC_IPM_GetHde(args...) 0 445 #define MHal_FRC_IPM_GetVde(args...) 0 446 #define MHal_FRC_IPM_Csc(args...) 447 #define MHal_FRC_IPM_CscDither(args...) 448 #define MHal_FRC_IPM_CscRound(args...) 449 #define MHal_FRC_IPM_CscSaturation(args...) 450 #define MHal_FRC_IPM_CheckBoardEn(args...) 451 #define MHal_FRC_IPM_SetIpCtrl(args...) 452 #define MHal_FRC_IPM_SetHRefLock(args...) 453 #define MHal_FRC_IPM_GetHdeCount(args...) 0 454 #define MHal_FRC_IPM_TestPattern(args...) 455 #define MHal_FRC_IPM_SetHTotal(args...) 456 #define MHal_FRC_IPM_SetVTotal(args...) 457 #define MHal_FRC_IPM_HActive(args...) 458 #define MHal_FRC_IPM_VActive(args...) 459 #define MHal_FRC_IPM_GetYcoutLinePitch(args...) 0 460 #define MHal_FRC_IPM_GetWriteFetchNum(args...) 0 461 #define MHal_FRC_IPM_GetReadFetchNum(args...) 0 462 #define MHal_FRC_IPM_GetLineLimit(args...) 0 463 #define MHal_FRC_IPM_SetPacketCount(args...) 464 #define MHal_FRC_IPM_GetFrameYcout(args...) 0 465 #define MHal_FRC_IPM_3DFlag_In_SWMode_En(args...) 466 #define MHal_FRC_IPM_3DFlag_In_SWMode_SetIdx(args...) 467 #define MHal_FRC_IPM_3DFlag_In_HWMode_SrcSel(args...) 468 #define MHal_FRC_IPM_GetIPVfreqX10(args...) 0 469 470 471 472 #define MHal_FRC_OPM_SetFbLineOffset_Data(args...) 473 #define MHal_FRC_OPM_SetFbLineOffset_Me3(args...) 474 #define MHal_FRC_OPM_SetSrcPixNum(args...) 475 #define MHal_FRC_OPM_SetSrcLineNum(args...) 476 #define MHal_FRC_OPM_CeLineCountEn(args...) 477 #define MHal_FRC_OPM_SetLbiSrcPixelNum_Left(args...) 478 #define MHal_FRC_OPM_SetLbiReadPixelNum_Left(args...) 479 #define MHal_FRC_OPM_SetLbiSkipEn(args...) 480 #define MHal_FRC_OPM_SetLbiSkipNum_Left(args...) 481 #define MHal_FRC_OPM_SetLbiSrcPixelNum_Right(args...) 482 #define MHal_FRC_OPM_SetLbiReadPixelNum_Right(args...) 483 #define MHal_FRC_OPM_SetLbiSkipEn3D(args...) 484 #define MHal_FRC_OPM_SetLbiSkipNum_Right(args...) 485 #define MHal_FRC_OPM_FuncEn(args...) 486 #define MHal_FRC_OPM_3dFuncEn(args...) 487 #define MHal_FRC_OPM_SetBaseOffset_Data0(args...) 488 #define MHal_FRC_OPM_SetBaseOffset_Data1(args...) 489 #define MHal_FRC_OPM_SetBaseOffset_Me0(args...) 490 #define MHal_FRC_OPM_SetBaseOffset_Me1(args...) 491 #define MHal_FRC_OPM_SetBaseOffset_Me3(args...) 492 #define MHal_FRC_OPM_SetBaseOffset_Da0_L(args...) 493 #define MHal_FRC_OPM_SetBaseOffset_Da1_L(args...) 494 #define MHal_FRC_OPM_SetBaseOffset_Me0_L(args...) 495 #define MHal_FRC_OPM_SetBaseOffset_Me1_L(args...) 496 #define MHal_FRC_OPM_SetBaseOffset_Me3_L(args...) 497 #define MHal_FRC_OPM_SetBaseOffset_Mr1_L(args...) 498 #define MHal_FRC_OPM_SetBaseOffset_Mr1(args...) 499 #define MHal_FRC_OPM_SetDebugMask(args...) 500 #define MHal_FRC_OPM_SwReset(args...) 501 #define MHal_FRC_OPM_enableBaseAdrMr(args...) 502 INTERFACE void MHal_FRC_OPM_SetBaseAddr(void *pInstance, MS_PHY addr, MS_U32 u32FrameYcout); 503 INTERFACE void MHal_FRC_OPM_R_SetBaseAddr(void *pInstance, MS_PHY addr); 504 #define MHal_FRC_OPM_SetMlbOutRstCycle(args...) 505 #define MHal_FRC_OPM_SetFifoTrigThr(args...) 506 #define MHal_FRC_OPM_SetFifoMaxReadReq(args...) 507 #define MHal_FRC_OPM_SetGatingClk(args...) 508 #define MHal_FRC_SetMemMode(args...) 509 510 #define MHal_FRC_OP2_ColorMatrixEn(args...) 511 #define MHal_FRC_OP2_CscDitherEn(args...) 512 #define MHal_FRC_OP2_DataPathEn(args...) 513 #define MHal_FRC_OP2_DebugFuncEn(args...) 514 #define MHal_FRC_OP2_SetGain_R(args...) 515 #define MHal_FRC_OP2_SetGain_G(args...) 516 #define MHal_FRC_OP2_SetGain_B(args...) 517 #define MHal_FRC_OP2_SetOffset_R(args...) 518 #define MHal_FRC_OP2_SetOffset_G(args...) 519 #define MHal_FRC_OP2_SetOffset_B(args...) 520 #define MHal_FRC_OP2_SetDither(args...) 521 #define MHal_FRC_OP2_PAFRC_FuncEn(args...) 522 #define MHal_FRC_OP2_PAFRC_FuncEn2(args...) 523 #define MHal_FRC_OP2_PAFRC_FuncEn3(args...) 524 #define MHal_FRC_OP2_PAFRC_Set2x2BlockRotDir(args...) 525 #define MHal_FRC_OP2_PAFRC_TopBoxFrSeq(args...) 526 #define MHal_FRC_OP2_PAFRC_TopBoxFrC2Seq(args...) 527 #define MHal_FRC_OP2_PAFRC_SetBoxRotDir(args...) 528 #define MHal_FRC_OP2_PAFRC_Set8x8BoxRotDir(args...) 529 #define MHal_FRC_OP2_PAFRC_SetBlockEntities(args...) 530 #define MHal_FRC_OP2_PAFRC_PolarityCtrl(args...) 531 #define MHal_FRC_OP2_PAFRC_SetBoxLsbValue(args...) 532 533 #define MHal_FRC_SCTOP_SCMI_Bypass_Enable(args...) 534 #define MHal_FRC_SCTOP_FRC_Bypass_Enable(args...) 535 536 #define MHal_FRC_SNR_SetPixelHorixontalNum(args...) 537 #define MHal_FRC_SNR_SetLineVerticalNum(args...) 538 539 #define MHal_FRC_SCP_HSU1_HSP(args...) 540 #define MHal_FRC_SCP_HSU1_Init_Position(args...) 541 #define MHal_FRC_SCP_HSU1_Scaling_Mode(args...) 542 #define MHal_FRC_SCP_HSU1_444to422_Mode(args...) 543 #define MHal_FRC_SCP_HSU1_VSU_Scaling_Mode(args...) 544 #define MHal_FRC_SCP_HSU1_VSU_Scaling_coef(args...) 545 #define MHal_FRC_SCP_HSU2_HSP(args...) 546 #define MHal_FRC_SCP_HSU2_Init_Position(args...) 547 #define MHal_FRC_SCP_HSU2_Scaling_Mode(args...) 548 549 #define MHal_FRC_OD_SetBaseAddr(args...) 550 #define MHal_FRC_LD_SetBaseAddr(args...) 551 #define MHal_FRC_LD_Edge2D_SetBaseAddr(args...) 552 INTERFACE void MHal_FRC_ME1_SetBaseAddr(void *pInstance, MS_PHY addr, MS_U32 u32Size); 553 INTERFACE void MHal_FRC_ME2_SetBaseAddr(void *pInstance, MS_PHY addr, MS_U32 u32Size); 554 #define MHal_FRC_2D3D_Render_SetBaseAddr(args...) 555 #define MHal_FRC_2D3D_Render_Detection_SetBaseAddr(args...) 556 INTERFACE void MHal_FRC_Halo_SetBaseAddr(void *pInstance, MS_PHY addr, MS_U32 u32Size); 557 #define MHal_FRC_OverDriverSwitch(args...) 558 #define MHal_FRC_OD_Init(args...) 559 560 // for FRC init 561 INTERFACE void MHal_FRC_Init(void *pInstance, PMST_PANEL_INFO_t pPanelInfo, PFRC_INFO_t pFRCInfo); 562 INTERFACE void MHal_FRC_ByPass_Enable(void *pInstance, MS_BOOL bEnable); 563 564 #define MHal_FRC_LoadTabelbySrcType(args...) 565 INTERFACE void MHal_FRC_Set_3D_QMap(void *pInstance, MS_U8 u8FRC3DPanelType, MS_U16 u16sc_in_3dformat, MS_U16 u16sc_out_3dformat, MS_U8 u83D_FI_out); 566 567 568 //FRC R2 Mail Box Control 569 INTERFACE MS_BOOL MHal_XC_SendCmdToFRC(void *pInstance, MS_U8 u8Cmd, MS_U8 count, MS_U8 p1, MS_U8 p2, MS_U8 p3, MS_U8 p4, MS_U8 p5, MS_U8 p6, MS_U8 p7, MS_U8 p8); 570 INTERFACE MS_BOOL MHal_XC_GetMsgFromFRC(void *pInstance, MS_U8* pu8Cmd, MS_U8* pu8ParaCount, MS_U8* pu8Para); 571 572 INTERFACE MS_U16 Hal_XC_FRC_R2_Get_SwVersion(void *pInstance); 573 INTERFACE MS_U16 Hal_XC_FRC_R2_Get_CmdVersion(void *pInstance); 574 INTERFACE MS_BOOL Hal_XC_FRC_R2_Init(void *pInstance, MS_U8 u8Panel3DType, MS_U8 u8PanelMaxFreq, MS_U8 u8LocalDimingPanelType, MS_U8 u8ChipRevision); 575 INTERFACE MS_BOOL Hal_XC_FRC_R2_Set_Timing(void *pInstance, MS_U8 u8InVFreq, MS_U8 u8OutVFreq); 576 INTERFACE MS_BOOL Hal_XC_FRC_R2_Set_InputFrameSize(void *pInstance, MS_U16 u16HSize, MS_U16 u16VSize ); 577 INTERFACE MS_BOOL Hal_XC_FRC_R2_Set_OutputFrameSize(void *pInstance, MS_U16 u16HSize, MS_U16 u16VSize ); 578 INTERFACE MS_BOOL Hal_XC_FRC_R2_Set_FPLL_Lockdone(void *pInstance, MS_BOOL bLockDone); 579 INTERFACE MS_BOOL Hal_XC_FRC_R2_Enable_MEMC(void *pInstance, MS_U16 u16MEMCLevel); 580 INTERFACE MS_BOOL Hal_XC_FRC_R2_Set_Input3DFormat(void *pInstance, MS_U8 u8FrcInput3DType); 581 582 583 #define Hal_XC_FRC_R2_Set_MfcMode(args...) 584 #define Hal_XC_FRC_R2_Set_MfcDemoMode(args...) 585 #define Hal_XC_FRC_R2_Set_LocalDimmingMode(args...) 586 #define Hal_XC_FRC_R2_Set_2DTo3DMode(args...) 0 587 588 //FRC auto download 589 #define Hal_FRC_ADLG_set_base_addr(args...) 590 #define Hal_FRC_ADLG_set_depth(args...) 591 #define Hal_FRC_ADLG_set_dma(args...) 592 #define Hal_FRC_ADLG_set_on_off(args...) 593 594 #define Hal_FRC_get_table_idx(args...) FRC_NOTSUPPORT_MODE 595 596 #define MHal_XC_OC_set_HSyncStartEnd(args...) 597 #define MHal_XC_OC_set_VSyncStartEnd(args...) 598 #define MHal_XC_OC_set_HFdeStartEnd(args...) 599 #define MHal_XC_OC_set_VFdeStartEnd(args...) 600 #define MHal_XC_OC_set_HTotal(args...) 601 #define MHal_XC_OC_set_VTotal(args...) 602 603 #define MHal_FRC_IPM_SetOffset(args...) 604 #define MHal_FRC_IPM_SetFetchNum(args...) 605 #define MHal_FRC_OPM_SetOffset(args...) 606 #define MHal_FRC_OPM_SetFetchNum(args...) 607 #define MHal_FRC_HSU_SetScalingSize(args...) 608 #define MHal_FRC_VSU_SetScalingSize(args...) 609 #define MHal_FRC_CSC_SelectPath(args...) 610 611 #define MHal_FRC_interrupt_mask(args...) 612 #define MHal_FRC_Mute(args...) 613 #define MHal_FRC_3DLR_Select(args...) 614 615 INTERFACE void MHal_FRC_Composer_User_Mode_Enable(void *pInstance, MS_BOOL bEnable); 616 INTERFACE void MHal_FRC_Set_Composer_User_Mode(void *pInstance, E_FRC_COMPOSER_SOURCE_MODE eMode, MS_BOOL bMenuload); 617 618 INTERFACE void MHal_FRC_Set_Pipe_Delay_Mode(void *pInstance, E_FRC_PIPE_DELAY_MODE eMode); 619 INTERFACE void MHal_FRC_Set_Pipe_Delay_Value(void *pInstance, MS_U16 u16Hcnt, MS_U16 u16Vcnt); 620 INTERFACE void MHal_FRC_Set_Pipe_Delay_Reset(void *pInstance, MS_BOOL bEnable, MS_BOOL bMenuload); 621 622 INTERFACE void MHal_FRC_Set_STGEN_ODCLK(void *pInstance, E_FRC_STGEN_ODCLK eMode, MS_BOOL bMenuload); 623 INTERFACE void MHal_FRC_Set_FSC_DE_Selection(void *pInstance, E_FRC_FSC_SOURCE_MODE eMode); 624 INTERFACE MS_BOOL MHal_FRC_IsFHDToFSC(void *pInstance, SCALER_WIN eWindow); 625 INTERFACE MS_BOOL MHal_FRC_IsSupportFRC_byEfuse(void *pInstance); 626 INTERFACE MS_BOOL MHal_FRC_Check_Condition(void *pInstance); 627 INTERFACE void MHal_FRC_AdjustGOPPosition(void *pInstance); 628 INTERFACE void MHal_FRC_GetGOPOffset(void *pInstance, MS_U16 *u16OffsetH, MS_U16 *u16OffsetV); 629 INTERFACE MS_BOOL MHal_FRC_IsEnableFRC3D(void *pInstance, SCALER_WIN eWindow); 630 INTERFACE void MHal_FRC_Set_Mload_Trig_Mode(void *pInstance, E_FRC_MLOAD_TRIG_MODE eMode); 631 632 //----------------- Maserati new API, Maxim no need ---------------------// 633 #define MHal_FRC_Set_FO_Path(args...) 634 #define MHal_FRC_Set_FO_VOP_H_Size(args...) 635 #define MHal_FRC_Set_FO_SPTP_Setting(args...) 636 #define MHal_FRC_Set_FO_2Line_Setting(args...) 637 #define MHal_FRC_Set_FO_OSDDS_Setting(args...) 638 639 #define MHal_FRC_FO_TGEN_SetVTotal(args...) 640 #define MHal_FRC_FO_TGEN_SetHTotal(args...) 641 #define MHal_FRC_FO_TGEN_SetVTrigY(args...) 642 #define MHal_FRC_FO_TGEN_SetVTrigX(args...) 643 #define MHal_FRC_FO_TGEN_SetVSyncStartEndY(args...) 644 #define MHal_FRC_FO_TGEN_SetHSyncStartEndX(args...) 645 #define MHal_FRC_FO_TGEN_SetFdeStartEndY(args...) 646 #define MHal_FRC_FO_TGEN_SetFdeStartEndX(args...) 647 #define MHal_FRC_FO_TGEN_SetMdeStartEndY(args...) 648 #define MHal_FRC_FO_TGEN_SetMdeStartEndX(args...) 649 #define MHal_FRC_FO_TGEN_SetMdeStartEndX_L(args...) 650 #define MHal_FRC_FO_TGEN_SetMdeStartEndX_R(args...) 651 652 #define MHal_FRC_Set_SC2_PLL_Vsync_Ref(args...) 653 //------------------------------------------------ --------------------// 654 655 INTERFACE void MHal_SWDS_AddTGENMdeStartEndY(void *pInstance, MS_U16 u16Start, MS_U16 u16End, SCALER_WIN eWindow); 656 INTERFACE void MHal_SWDS_AddTGENMdeStartEndX(void *pInstance, MS_U16 u16Start, MS_U16 u16End, SCALER_WIN eWindow); 657 INTERFACE MS_BOOL Hal_XC_Get_Stgen_Lock_Ip_status(void *pInstance); 658 #undef INTERFACE 659 #endif /* MHAL_FRC_H */ 660 661