1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_TBL_H_ 80 #define _LPLL_TBL_H_ 81 82 #define LPLL_REG_NUM 35 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to90MHz, //0 87 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz, //1 88 89 E_PNL_SUPPORTED_LPLL_LVDS_2CH_110to150MHz, //2 90 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to110MHz, //3 91 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to50MHz, //4 92 93 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_110to150MHz, //5 94 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to110MHz, //6 95 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz, //7 96 97 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_230to300MHz, //8 98 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_114_5to230MHz, //9 99 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to114_5MHz, //10 100 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to50MHz, //11 101 102 E_PNL_SUPPORTED_LPLL_TTL_100to150MHz, //12 103 E_PNL_SUPPORTED_LPLL_TTL_50to100MHz, //13 104 E_PNL_SUPPORTED_LPLL_TTL_25to50MHz, //14 105 E_PNL_SUPPORTED_LPLL_TTL_25to25MHz, //15 106 107 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz, //16 108 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to50MHz, //17 109 110 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz, //18 111 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz, //19 112 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to50MHz, //20 113 114 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz, //21 115 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz, //22 116 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to50MHz, //23 117 118 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz, //24 119 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz, //25 120 E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to50MHz, //26 121 122 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz, //27 123 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz, //28 124 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz, //29 125 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to50MHz, //30 126 127 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133_33to150MHz, //31 128 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_66_67to133_33MHz, //32 129 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to66_67MHz, //33 130 E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to50MHz, //34 131 132 E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_95to150MHz, //35 133 E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to95MHz, //36 134 E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to80MHz, //37 135 136 E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to150MHz, //38 137 E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to80MHz, //39 138 139 E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_95to150MHz, //40 140 E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to95MHz, //41 141 E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to80MHz, //42 142 143 E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_115to150MHz, //43 144 E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to115MHz, //44 145 E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to80MHz, //45 146 147 E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to150MHz, //46 148 E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to80MHz, //47 149 150 E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_115to150MHz, //48 151 E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to115MHz, //49 152 E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to80MHz, //50 153 154 E_PNL_SUPPORTED_LPLL_MAX, //51 155 } E_PNL_SUPPORTED_LPLL_TYPE; 156 157 typedef struct 158 { 159 MS_U8 address; 160 MS_U16 value; 161 MS_U16 mask; 162 }TBLStruct,*pTBLStruct; 163 164 TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= 165 { 166 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to90MHz NO.0 167 //Address,Value,Mask 168 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 169 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 170 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 171 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 172 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 173 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 174 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 175 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 176 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 177 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 178 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 179 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 180 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 181 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 182 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 183 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 184 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 185 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 186 {0x33,0x0020,0x0020},//reg_lpll2_pd 187 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 188 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 189 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 190 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 191 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 192 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 193 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 194 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 195 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 196 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 197 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 198 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 199 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 200 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 201 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 202 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 203 }, 204 205 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.1 206 //Address,Value,Mask 207 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 208 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 209 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 210 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 211 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 212 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 213 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 214 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 215 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 216 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 217 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 218 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 219 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 220 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 221 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 222 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 223 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 224 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 225 {0x33,0x0020,0x0020},//reg_lpll2_pd 226 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 227 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 228 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 229 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 230 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 231 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 232 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 233 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 234 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 235 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 236 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 237 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 238 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 239 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 240 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 241 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 242 }, 243 244 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_110to150MHz NO.2 245 //Address,Value,Mask 246 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 247 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 248 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 249 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 250 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 251 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 252 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 253 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 254 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 255 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 256 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 257 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 258 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 259 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 260 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 261 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 262 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 263 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 264 {0x33,0x0020,0x0020},//reg_lpll2_pd 265 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 266 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 267 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 268 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 269 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 270 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 271 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 272 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 273 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 274 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 275 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 276 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 277 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 278 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 279 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 280 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 281 }, 282 283 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to110MHz NO.3 284 //Address,Value,Mask 285 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 286 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 287 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 288 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 289 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 290 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 291 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 292 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 293 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 294 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 295 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 296 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 297 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 298 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 299 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 300 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 301 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 302 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 303 {0x33,0x0020,0x0020},//reg_lpll2_pd 304 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 305 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 306 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 307 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 308 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 309 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 310 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 311 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 312 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 313 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 314 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 315 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 316 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 317 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 318 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 319 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 320 }, 321 322 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to50MHz NO.4 323 //Address,Value,Mask 324 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 325 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 326 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 327 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 328 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 329 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 330 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 331 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 332 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 333 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 334 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 335 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 336 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 337 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 338 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 339 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 340 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 341 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 342 {0x33,0x0020,0x0020},//reg_lpll2_pd 343 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 344 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 345 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 346 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 347 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 348 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 349 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 350 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 351 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 352 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 353 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 354 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 355 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 356 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 357 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 358 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 359 }, 360 361 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_110to150MHz NO.5 362 //Address,Value,Mask 363 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 364 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 365 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 366 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 367 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 368 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 369 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 370 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 371 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 372 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 373 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 374 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 375 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 376 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 377 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 378 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 379 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 380 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 381 {0x33,0x0020,0x0020},//reg_lpll2_pd 382 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 383 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 384 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 385 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 386 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 387 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 388 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 389 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 390 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 391 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 392 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 393 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 394 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 395 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 396 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 397 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 398 }, 399 400 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to110MHz NO.6 401 //Address,Value,Mask 402 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 403 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 404 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 405 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 406 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 407 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 408 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 409 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 410 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 411 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 412 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 413 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 414 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 415 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 416 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 417 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 418 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 419 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 420 {0x33,0x0020,0x0020},//reg_lpll2_pd 421 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 422 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 423 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 424 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 425 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 426 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 427 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 428 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 429 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 430 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 431 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 432 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 433 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 434 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 435 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 436 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 437 }, 438 439 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.7 440 //Address,Value,Mask 441 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 442 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 443 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 444 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 445 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 446 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 447 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 448 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 449 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 450 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 451 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 452 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 453 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 454 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 455 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 456 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 457 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 458 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 459 {0x33,0x0020,0x0020},//reg_lpll2_pd 460 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 461 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 462 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 463 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 464 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 465 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 466 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 467 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 468 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 469 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 470 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 471 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 472 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 473 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 474 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 475 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 476 }, 477 478 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_230to300MHz NO.8 479 //Address,Value,Mask 480 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 481 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 482 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 483 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 484 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 485 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 486 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 487 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 488 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 489 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 490 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 491 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 492 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 493 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 494 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 495 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 496 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 497 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 498 {0x33,0x0020,0x0020},//reg_lpll2_pd 499 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 500 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 501 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 502 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 503 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 504 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 505 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 506 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 507 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 508 {0x04,0x2000,0x2000},//reg_lpll1_sdiv3p5_en 509 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 510 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 511 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 512 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 513 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 514 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 515 }, 516 517 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_114_5to230MHz NO.9 518 //Address,Value,Mask 519 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 520 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 521 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 522 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 523 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 524 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 525 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 526 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 527 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 528 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 529 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 530 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 531 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 532 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 533 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 534 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 535 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 536 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 537 {0x33,0x0020,0x0020},//reg_lpll2_pd 538 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 539 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 540 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 541 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 542 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 543 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 544 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 545 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 546 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 547 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 548 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 549 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 550 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 551 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 552 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 553 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 554 }, 555 556 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to114_5MHz NO.10 557 //Address,Value,Mask 558 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 559 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 560 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 561 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 562 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 563 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 564 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 565 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 566 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 567 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 568 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 569 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 570 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 571 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 572 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 573 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 574 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 575 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 576 {0x33,0x0020,0x0020},//reg_lpll2_pd 577 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 578 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 579 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 580 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 581 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 582 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 583 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 584 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 585 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 586 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 587 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 588 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 589 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 590 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 591 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 592 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 593 }, 594 595 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to50MHz NO.11 596 //Address,Value,Mask 597 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 598 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 599 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 600 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 601 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 602 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 603 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 604 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 605 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 606 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 607 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 608 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 609 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 610 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 611 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 612 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 613 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 614 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 615 {0x33,0x0020,0x0020},//reg_lpll2_pd 616 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 617 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 618 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 619 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 620 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 621 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 622 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 623 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 624 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 625 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 626 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 627 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 628 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 629 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 630 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 631 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 632 }, 633 634 { //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.12 635 //Address,Value,Mask 636 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 637 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 638 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 639 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 640 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 641 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 642 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 643 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 644 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 645 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 646 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 647 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 648 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 649 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 650 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 651 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 652 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 653 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 654 {0x33,0x0020,0x0020},//reg_lpll2_pd 655 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 656 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 657 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 658 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 659 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 660 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 661 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 662 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 663 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 664 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 665 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 666 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 667 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 668 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 669 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 670 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 671 }, 672 673 { //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.13 674 //Address,Value,Mask 675 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 676 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 677 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 678 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 679 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 680 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 681 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 682 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 683 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 684 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 685 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 686 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 687 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 688 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 689 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 690 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 691 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 692 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 693 {0x33,0x0020,0x0020},//reg_lpll2_pd 694 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 695 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 696 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 697 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 698 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 699 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 700 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 701 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 702 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 703 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 704 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 705 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 706 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 707 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 708 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 709 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 710 }, 711 712 { //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.14 713 //Address,Value,Mask 714 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 715 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 716 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 717 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 718 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 719 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 720 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 721 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 722 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 723 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 724 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 725 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 726 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 727 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 728 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 729 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 730 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 731 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 732 {0x33,0x0020,0x0020},//reg_lpll2_pd 733 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 734 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 735 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 736 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 737 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 738 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 739 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 740 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 741 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 742 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 743 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 744 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 745 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 746 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 747 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 748 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 749 }, 750 751 { //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.15 752 //Address,Value,Mask 753 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 754 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 755 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 756 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 757 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 758 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 759 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 760 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 761 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 762 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 763 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 764 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 765 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 766 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 767 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 768 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 769 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 770 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 771 {0x33,0x0020,0x0020},//reg_lpll2_pd 772 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 773 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 774 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 775 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 776 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 777 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 778 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 779 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 780 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 781 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 782 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 783 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 784 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 785 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 786 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 787 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 788 }, 789 790 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.16 791 //Address,Value,Mask 792 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 793 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 794 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 795 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 796 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 797 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 798 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 799 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 800 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 801 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 802 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 803 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 804 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 805 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 806 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 807 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 808 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 809 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 810 {0x33,0x0020,0x0020},//reg_lpll2_pd 811 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 812 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 813 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 814 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 815 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 816 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 817 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 818 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 819 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 820 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 821 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 822 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 823 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 824 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 825 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 826 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 827 }, 828 829 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to50MHz NO.17 830 //Address,Value,Mask 831 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 832 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 833 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 834 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 835 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 836 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 837 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 838 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 839 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 840 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 841 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 842 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 843 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 844 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 845 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 846 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 847 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 848 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 849 {0x33,0x0020,0x0020},//reg_lpll2_pd 850 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 851 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 852 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 853 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 854 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 855 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 856 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 857 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 858 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 859 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 860 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 861 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 862 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 863 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 864 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 865 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 866 }, 867 868 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.18 869 //Address,Value,Mask 870 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 871 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 872 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 873 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 874 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 875 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 876 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 877 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 878 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 879 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 880 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 881 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 882 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 883 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 884 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 885 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 886 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 887 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 888 {0x33,0x0020,0x0020},//reg_lpll2_pd 889 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 890 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 891 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 892 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 893 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 894 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 895 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 896 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 897 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 898 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 899 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 900 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 901 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 902 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 903 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 904 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 905 }, 906 907 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.19 908 //Address,Value,Mask 909 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 910 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 911 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 912 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 913 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 914 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 915 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 916 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 917 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 918 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 919 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 920 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 921 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 922 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 923 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 924 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 925 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 926 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 927 {0x33,0x0020,0x0020},//reg_lpll2_pd 928 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 929 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 930 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 931 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 932 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 933 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 934 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 935 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 936 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 937 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 938 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 939 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 940 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 941 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 942 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 943 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 944 }, 945 946 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to50MHz NO.20 947 //Address,Value,Mask 948 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 949 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 950 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 951 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 952 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 953 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 954 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 955 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 956 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 957 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 958 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 959 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 960 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 961 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 962 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 963 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 964 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 965 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 966 {0x33,0x0020,0x0020},//reg_lpll2_pd 967 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 968 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 969 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 970 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 971 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 972 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 973 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 974 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 975 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 976 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 977 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 978 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 979 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 980 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 981 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 982 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 983 }, 984 985 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.21 986 //Address,Value,Mask 987 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 988 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 989 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 990 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 991 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 992 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 993 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 994 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 995 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 996 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 997 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 998 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 999 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1000 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1001 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1002 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1003 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1004 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1005 {0x33,0x0020,0x0020},//reg_lpll2_pd 1006 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1007 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1008 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1009 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1010 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1011 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1012 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1013 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1014 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1015 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1016 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1017 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1018 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1019 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1020 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1021 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1022 }, 1023 1024 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.22 1025 //Address,Value,Mask 1026 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1027 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1028 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1029 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1030 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1031 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1032 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1033 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 1034 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 1035 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 1036 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1037 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1038 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1039 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1040 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1041 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1042 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1043 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1044 {0x33,0x0020,0x0020},//reg_lpll2_pd 1045 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1046 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1047 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1048 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1049 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1050 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1051 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1052 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1053 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1054 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1055 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1056 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1057 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1058 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1059 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1060 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1061 }, 1062 1063 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to50MHz NO.23 1064 //Address,Value,Mask 1065 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1066 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1067 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1068 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1069 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1070 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1071 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1072 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 1073 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 1074 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 1075 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1076 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1077 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1078 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1079 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1080 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1081 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1082 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1083 {0x33,0x0020,0x0020},//reg_lpll2_pd 1084 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1085 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1086 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1087 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1088 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1089 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1090 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1091 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1092 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1093 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1094 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1095 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1096 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1097 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1098 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1099 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1100 }, 1101 1102 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz NO.24 1103 //Address,Value,Mask 1104 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1105 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1106 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1107 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1108 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1109 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1110 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1111 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1112 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1113 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1114 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1115 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1116 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1117 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1118 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1119 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1120 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1121 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1122 {0x33,0x0020,0x0020},//reg_lpll2_pd 1123 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1124 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1125 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1126 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1127 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1128 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1129 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1130 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1131 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1132 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1133 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1134 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1135 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1136 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1137 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1138 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1139 }, 1140 1141 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz NO.25 1142 //Address,Value,Mask 1143 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1144 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1145 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1146 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1147 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1148 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1149 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1150 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1151 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1152 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1153 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1154 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1155 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1156 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1157 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1158 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1159 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1160 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1161 {0x33,0x0020,0x0020},//reg_lpll2_pd 1162 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1163 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1164 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1165 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1166 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1167 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1168 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1169 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1170 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1171 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1172 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1173 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1174 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1175 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1176 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1177 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1178 }, 1179 1180 { //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to50MHz NO.26 1181 //Address,Value,Mask 1182 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1183 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1184 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1185 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1186 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1187 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1188 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1189 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1190 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1191 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1192 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1193 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1194 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1195 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1196 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1197 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1198 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1199 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1200 {0x33,0x0020,0x0020},//reg_lpll2_pd 1201 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1202 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1203 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1204 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1205 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1206 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1207 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1208 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1209 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1210 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1211 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1212 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1213 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1214 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1215 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1216 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1217 }, 1218 1219 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.27 1220 //Address,Value,Mask 1221 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1222 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1223 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1224 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1225 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1226 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1227 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1228 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1229 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1230 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1231 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1232 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1233 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1234 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1235 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1236 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1237 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1238 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1239 {0x33,0x0020,0x0020},//reg_lpll2_pd 1240 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1241 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1242 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1243 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1244 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1245 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1246 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1247 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1248 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1249 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1250 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1251 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1252 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1253 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1254 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1255 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1256 }, 1257 1258 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.28 1259 //Address,Value,Mask 1260 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1261 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1262 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1263 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1264 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1265 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1266 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1267 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1268 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1269 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1270 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1271 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1272 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1273 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1274 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1275 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1276 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1277 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1278 {0x33,0x0020,0x0020},//reg_lpll2_pd 1279 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1280 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1281 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1282 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1283 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1284 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1285 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1286 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1287 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1288 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1289 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1290 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1291 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1292 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1293 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1294 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1295 }, 1296 1297 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.29 1298 //Address,Value,Mask 1299 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1300 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1301 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1302 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1303 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1304 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1305 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1306 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1307 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 1308 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 1309 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1310 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1311 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1312 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1313 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1314 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1315 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1316 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1317 {0x33,0x0020,0x0020},//reg_lpll2_pd 1318 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1319 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1320 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1321 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1322 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1323 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1324 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1325 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1326 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1327 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1328 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1329 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1330 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1331 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1332 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1333 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1334 }, 1335 1336 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to50MHz NO.30 1337 //Address,Value,Mask 1338 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1339 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1340 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1341 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1342 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1343 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1344 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1345 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1346 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 1347 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 1348 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1349 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1350 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1351 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1352 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1353 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1354 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1355 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1356 {0x33,0x0020,0x0020},//reg_lpll2_pd 1357 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1358 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1359 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1360 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1361 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1362 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1363 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1364 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1365 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1366 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1367 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1368 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1369 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1370 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1371 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1372 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1373 }, 1374 1375 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133_33to150MHz NO.31 1376 //Address,Value,Mask 1377 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1378 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1379 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1380 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1381 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1382 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1383 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1384 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1385 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1386 {0x2E,0x0001,0x0007},//reg_lpll1_fifo_div 1387 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1388 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1389 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1390 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1391 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1392 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1393 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1394 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1395 {0x33,0x0020,0x0020},//reg_lpll2_pd 1396 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1397 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1398 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1399 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1400 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1401 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1402 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1403 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1404 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1405 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1406 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1407 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1408 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1409 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1410 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1411 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1412 }, 1413 1414 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_66_67to133_33MHz NO.32 1415 //Address,Value,Mask 1416 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1417 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1418 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1419 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1420 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1421 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1422 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1423 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1424 {0x35,0x3000,0x7000},//reg_lpll1_skew_div 1425 {0x2E,0x0002,0x0007},//reg_lpll1_fifo_div 1426 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1427 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1428 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1429 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1430 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1431 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1432 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1433 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1434 {0x33,0x0020,0x0020},//reg_lpll2_pd 1435 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1436 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1437 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1438 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1439 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1440 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1441 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1442 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1443 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1444 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1445 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1446 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1447 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1448 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1449 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1450 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1451 }, 1452 1453 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to66_67MHz NO.33 1454 //Address,Value,Mask 1455 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1456 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1457 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1458 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1459 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1460 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1461 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1462 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1463 {0x35,0x4000,0x7000},//reg_lpll1_skew_div 1464 {0x2E,0x0003,0x0007},//reg_lpll1_fifo_div 1465 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1466 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1467 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1468 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1469 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1470 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1471 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1472 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1473 {0x33,0x0020,0x0020},//reg_lpll2_pd 1474 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1475 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1476 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1477 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1478 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1479 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1480 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1481 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1482 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1483 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1484 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1485 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1486 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1487 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1488 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1489 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1490 }, 1491 1492 { //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to50MHz NO.34 1493 //Address,Value,Mask 1494 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1495 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1496 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1497 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1498 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1499 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1500 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1501 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1502 {0x35,0x4000,0x7000},//reg_lpll1_skew_div 1503 {0x2E,0x0003,0x0007},//reg_lpll1_fifo_div 1504 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1505 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1506 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1507 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1508 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1509 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1510 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1511 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1512 {0x33,0x0020,0x0020},//reg_lpll2_pd 1513 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1514 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1515 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1516 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1517 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1518 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1519 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1520 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1521 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1522 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1523 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1524 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1525 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1526 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1527 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1528 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1529 }, 1530 1531 { //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_95to150MHz NO.35 1532 //Address,Value,Mask 1533 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1534 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1535 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1536 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1537 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1538 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1539 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1540 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1541 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1542 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1543 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1544 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1545 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1546 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1547 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1548 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1549 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1550 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1551 {0x33,0x0000,0x0020},//reg_lpll2_pd 1552 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1553 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1554 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 1555 {0x31,0x0002,0x0003},//reg_lpll2_loop_div_first 1556 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1557 {0x31,0x0400,0x1F00},//reg_lpll2_loop_div_second 1558 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1559 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1560 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1561 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1562 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1563 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1564 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1565 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1566 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1567 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1568 }, 1569 1570 { //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to95MHz NO.36 1571 //Address,Value,Mask 1572 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1573 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1574 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1575 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1576 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1577 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1578 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1579 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1580 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1581 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1582 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1583 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1584 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1585 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1586 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1587 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1588 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1589 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1590 {0x33,0x0000,0x0020},//reg_lpll2_pd 1591 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1592 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1593 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 1594 {0x31,0x0002,0x0003},//reg_lpll2_loop_div_first 1595 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1596 {0x31,0x0400,0x1F00},//reg_lpll2_loop_div_second 1597 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1598 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1599 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1600 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1601 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1602 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1603 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1604 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1605 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1606 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1607 }, 1608 1609 { //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to80MHz NO.37 1610 //Address,Value,Mask 1611 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1612 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1613 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1614 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1615 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1616 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1617 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1618 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1619 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1620 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1621 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1622 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1623 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1624 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1625 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1626 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1627 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1628 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1629 {0x33,0x0000,0x0020},//reg_lpll2_pd 1630 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1631 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1632 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 1633 {0x31,0x0002,0x0003},//reg_lpll2_loop_div_first 1634 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1635 {0x31,0x0400,0x1F00},//reg_lpll2_loop_div_second 1636 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1637 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1638 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1639 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1640 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1641 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1642 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1643 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1644 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1645 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1646 }, 1647 1648 { //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to150MHz NO.38 1649 //Address,Value,Mask 1650 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1651 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1652 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1653 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1654 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1655 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1656 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1657 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1658 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1659 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1660 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1661 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1662 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1663 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1664 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1665 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1666 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1667 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1668 {0x33,0x0000,0x0020},//reg_lpll2_pd 1669 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1670 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1671 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 1672 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1673 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1674 {0x31,0x0300,0x1F00},//reg_lpll2_loop_div_second 1675 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1676 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1677 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1678 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1679 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1680 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1681 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1682 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1683 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1684 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1685 }, 1686 1687 { //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to80MHz NO.39 1688 //Address,Value,Mask 1689 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1690 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1691 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1692 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1693 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1694 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1695 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1696 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1697 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1698 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1699 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1700 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1701 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1702 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1703 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1704 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1705 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1706 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1707 {0x33,0x0000,0x0020},//reg_lpll2_pd 1708 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1709 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 1710 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 1711 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1712 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1713 {0x31,0x0300,0x1F00},//reg_lpll2_loop_div_second 1714 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1715 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1716 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1717 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1718 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1719 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1720 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1721 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1722 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1723 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1724 }, 1725 1726 { //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_95to150MHz NO.40 1727 //Address,Value,Mask 1728 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1729 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1730 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1731 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1732 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1733 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1734 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1735 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1736 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1737 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1738 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1739 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1740 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1741 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1742 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1743 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1744 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1745 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1746 {0x33,0x0000,0x0020},//reg_lpll2_pd 1747 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1748 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1749 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 1750 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1751 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1752 {0x31,0x0200,0x1F00},//reg_lpll2_loop_div_second 1753 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1754 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1755 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1756 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1757 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1758 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1759 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1760 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1761 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1762 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1763 }, 1764 1765 { //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to95MHz NO.41 1766 //Address,Value,Mask 1767 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1768 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1769 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1770 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1771 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1772 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1773 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1774 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1775 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1776 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1777 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1778 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1779 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1780 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1781 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1782 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1783 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1784 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1785 {0x33,0x0000,0x0020},//reg_lpll2_pd 1786 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1787 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1788 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 1789 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1790 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1791 {0x31,0x0200,0x1F00},//reg_lpll2_loop_div_second 1792 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1793 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1794 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1795 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1796 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1797 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1798 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1799 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1800 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1801 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1802 }, 1803 1804 { //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to80MHz NO.42 1805 //Address,Value,Mask 1806 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1807 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1808 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1809 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1810 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1811 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1812 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1813 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1814 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 1815 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1816 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1817 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1818 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1819 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1820 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1821 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1822 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1823 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1824 {0x33,0x0000,0x0020},//reg_lpll2_pd 1825 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1826 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1827 {0x30,0x0011,0x001F},//reg_lpll2_input_div_first 1828 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1829 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1830 {0x31,0x0200,0x1F00},//reg_lpll2_loop_div_second 1831 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1832 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1833 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1834 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1835 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1836 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1837 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1838 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1839 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1840 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1841 }, 1842 1843 { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_115to150MHz NO.43 1844 //Address,Value,Mask 1845 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1846 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1847 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1848 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1849 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1850 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1851 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1852 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1853 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1854 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1855 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1856 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1857 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1858 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1859 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1860 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1861 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1862 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1863 {0x33,0x0000,0x0020},//reg_lpll2_pd 1864 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1865 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1866 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1867 {0x31,0x0002,0x0003},//reg_lpll2_loop_div_first 1868 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1869 {0x31,0x0400,0x1F00},//reg_lpll2_loop_div_second 1870 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1871 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1872 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1873 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1874 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1875 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1876 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1877 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1878 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1879 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1880 }, 1881 1882 { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to115MHz NO.44 1883 //Address,Value,Mask 1884 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1885 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1886 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1887 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1888 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1889 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1890 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1891 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1892 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1893 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1894 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1895 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1896 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1897 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1898 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1899 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1900 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1901 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1902 {0x33,0x0000,0x0020},//reg_lpll2_pd 1903 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1904 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1905 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1906 {0x31,0x0002,0x0003},//reg_lpll2_loop_div_first 1907 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1908 {0x31,0x0400,0x1F00},//reg_lpll2_loop_div_second 1909 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1910 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1911 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1912 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1913 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1914 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1915 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1916 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1917 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1918 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1919 }, 1920 1921 { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to80MHz NO.45 1922 //Address,Value,Mask 1923 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1924 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1925 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1926 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1927 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1928 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1929 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1930 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1931 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1932 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1933 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1934 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1935 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1936 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1937 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1938 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1939 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1940 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1941 {0x33,0x0000,0x0020},//reg_lpll2_pd 1942 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1943 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1944 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1945 {0x31,0x0002,0x0003},//reg_lpll2_loop_div_first 1946 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1947 {0x31,0x0400,0x1F00},//reg_lpll2_loop_div_second 1948 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1949 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1950 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1951 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1952 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1953 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1954 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1955 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1956 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1957 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1958 }, 1959 1960 { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to150MHz NO.46 1961 //Address,Value,Mask 1962 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1963 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1964 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1965 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1966 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1967 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1968 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1969 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1970 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1971 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1972 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1973 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1974 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1975 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1976 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1977 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1978 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1979 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1980 {0x33,0x0000,0x0020},//reg_lpll2_pd 1981 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1982 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1983 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 1984 {0x31,0x0002,0x0003},//reg_lpll2_loop_div_first 1985 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1986 {0x31,0x0300,0x1F00},//reg_lpll2_loop_div_second 1987 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1988 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1989 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1990 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 1991 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1992 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1993 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1994 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1995 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1996 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1997 }, 1998 1999 { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to80MHz NO.47 2000 //Address,Value,Mask 2001 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2002 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2003 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2004 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2005 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2006 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2007 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2008 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2009 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2010 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2011 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2012 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2013 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2014 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2015 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2016 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2017 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2018 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2019 {0x33,0x0000,0x0020},//reg_lpll2_pd 2020 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2021 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2022 {0x30,0x000E,0x001F},//reg_lpll2_input_div_first 2023 {0x31,0x0002,0x0003},//reg_lpll2_loop_div_first 2024 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2025 {0x31,0x0300,0x1F00},//reg_lpll2_loop_div_second 2026 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2027 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2028 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2029 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 2030 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2031 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2032 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2033 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2034 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2035 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2036 }, 2037 2038 { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_115to150MHz NO.48 2039 //Address,Value,Mask 2040 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2041 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2042 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2043 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2044 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2045 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 2046 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2047 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2048 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2049 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2050 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2051 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2052 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2053 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2054 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2055 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2056 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2057 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2058 {0x33,0x0020,0x0020},//reg_lpll2_pd 2059 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2060 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2061 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2062 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2063 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2064 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2065 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2066 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2067 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2068 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 2069 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2070 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2071 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2072 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2073 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2074 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2075 }, 2076 2077 { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to115MHz NO.49 2078 //Address,Value,Mask 2079 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2080 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2081 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2082 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2083 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2084 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2085 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2086 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2087 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2088 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2089 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2090 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2091 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2092 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2093 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2094 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2095 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2096 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2097 {0x33,0x0020,0x0020},//reg_lpll2_pd 2098 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2099 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2100 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2101 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2102 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2103 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2104 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2105 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2106 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2107 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 2108 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2109 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2110 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2111 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2112 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2113 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2114 }, 2115 2116 { //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to80MHz NO.50 2117 //Address,Value,Mask 2118 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2119 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2120 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2121 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2122 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2123 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2124 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2125 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2126 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2127 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2128 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2129 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2130 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2131 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2132 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2133 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2134 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2135 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2136 {0x33,0x0020,0x0020},//reg_lpll2_pd 2137 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2138 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2139 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2140 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2141 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2142 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2143 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2144 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2145 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2146 {0x04,0x0000,0x2000},//reg_lpll1_sdiv3p5_en 2147 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2148 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2149 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2150 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2151 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2152 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2153 }, 2154 2155 }; 2156 MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= 2157 { 2158 6, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to90MHz NO.0 2159 6, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.1 2160 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_110to150MHz NO.2 2161 6, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to110MHz NO.3 2162 6, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to50MHz NO.4 2163 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_110to150MHz NO.5 2164 6, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to110MHz NO.6 2165 6, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.7 2166 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_230to300MHz NO.8 2167 6, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_114_5to230MHz NO.9 2168 6, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to114_5MHz NO.10 2169 6, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to50MHz NO.11 2170 3, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.12 2171 3, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.13 2172 3, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.14 2173 3, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.15 2174 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.16 2175 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to50MHz NO.17 2176 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.18 2177 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.19 2178 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to50MHz NO.20 2179 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.21 2180 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.22 2181 3, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to50MHz NO.23 2182 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz NO.24 2183 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz NO.25 2184 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to50MHz NO.26 2185 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.27 2186 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.28 2187 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.29 2188 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to50MHz NO.30 2189 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133_33to150MHz NO.31 2190 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_66_67to133_33MHz NO.32 2191 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to66_67MHz NO.33 2192 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to50MHz NO.34 2193 24, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_95to150MHz NO.35 2194 12, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to95MHz NO.36 2195 12, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to80MHz NO.37 2196 18, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to150MHz NO.38 2197 18, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to80MHz NO.39 2198 24, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_95to150MHz NO.40 2199 12, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to95MHz NO.41 2200 12, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to80MHz NO.42 2201 24, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_115to150MHz NO.43 2202 12, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to115MHz NO.44 2203 12, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to80MHz NO.45 2204 9, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to150MHz NO.46 2205 9, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to80MHz NO.47 2206 12, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_115to150MHz NO.48 2207 6, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to115MHz NO.49 2208 6, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to80MHz NO.50 2209 }; 2210 MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= 2211 { 2212 7, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to90MHz NO.0 2213 7, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.1 2214 7, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_110to150MHz NO.2 2215 7, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to110MHz NO.3 2216 7, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to50MHz NO.4 2217 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_110to150MHz NO.5 2218 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to110MHz NO.6 2219 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.7 2220 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_230to300MHz NO.8 2221 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_114_5to230MHz NO.9 2222 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to114_5MHz NO.10 2223 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to50MHz NO.11 2224 2, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.12 2225 4, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.13 2226 8, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.14 2227 8, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.15 2228 4, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to80MHz NO.16 2229 4, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_8BIT_50to50MHz NO.17 2230 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_100to150MHz NO.18 2231 4, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to100MHz NO.19 2232 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_8BIT_50to50MHz NO.20 2233 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_100to150MHz NO.21 2234 4, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to100MHz NO.22 2235 4, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_8BIT_50to50MHz NO.23 2236 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_66_67to80MHz NO.24 2237 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to66_67MHz NO.25 2238 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_1CH_3PAIR_6BIT_50to50MHz NO.26 2239 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_133_33to150MHz NO.27 2240 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_66_67to133_33MHz NO.28 2241 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to66_67MHz NO.29 2242 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_3PAIR_6BIT_50to50MHz NO.30 2243 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_133_33to150MHz NO.31 2244 1, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_66_67to133_33MHz NO.32 2245 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to66_67MHz NO.33 2246 2, //E_PNL_SUPPORTED_LPLL_MINILVDS_2CH_6PAIR_6BIT_50to50MHz NO.34 2247 17, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_95to150MHz NO.35 2248 17, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to95MHz NO.36 2249 17, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_4PAIR_80to80MHz NO.37 2250 17, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to150MHz NO.38 2251 17, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_6PAIR_80to80MHz NO.39 2252 17, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_95to150MHz NO.40 2253 17, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to95MHz NO.41 2254 17, //E_PNL_SUPPORTED_LPLL_EPI_34_10bit_8PAIR_80to80MHz NO.42 2255 9, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_115to150MHz NO.43 2256 9, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to115MHz NO.44 2257 9, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_4PAIR_80to80MHz NO.45 2258 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to150MHz NO.46 2259 14, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_6PAIR_80to80MHz NO.47 2260 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_115to150MHz NO.48 2261 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to115MHz NO.49 2262 7, //E_PNL_SUPPORTED_LPLL_EPI_28_8bit_8PAIR_80to80MHz NO.50 2263 }; 2264 2265 #endif //_LPLL_TBL_H_ 2266