1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_TBL_H_ 80 #define _LPLL_TBL_H_ 81 82 #define LPLL_REG_NUM 41 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_TTL_100to150MHz, //0 87 E_PNL_SUPPORTED_LPLL_TTL_50to100MHz, //1 88 E_PNL_SUPPORTED_LPLL_TTL_25to50MHz, //2 89 E_PNL_SUPPORTED_LPLL_TTL_25to25MHz, //3 90 91 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to300MHz, //4 92 E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz, //5 93 94 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz, //6 95 E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz, //7 96 97 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz, //8 98 E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz, //9 99 100 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to300MHz, //10 101 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz, //11 102 E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz, //12 103 104 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz, //13 105 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz, //14 106 E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz, //15 107 108 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz, //16 109 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz, //17 110 E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz, //18 111 112 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to300MHz, //19 113 E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to150MHz, //20 114 115 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to300MHz, //21 116 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to150MHz, //22 117 118 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_240to300MHz, //23 119 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to240MHz, //24 120 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to150MHz, //25 121 122 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_180to300MHz, //26 123 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to180MHz, //27 124 E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to150MHz, //28 125 126 E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz, //29 127 E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz, //30 128 129 E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz, //31 130 E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz, //32 131 132 E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to300MHz, //33 133 E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to150MHz, //34 134 135 E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz, //35 136 E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz, //36 137 138 E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to300MHz, //37 139 E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to150MHz, //38 140 141 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz, //39 142 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz, //40 143 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz, //41 144 145 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz, //42 146 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz, //43 147 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz, //44 148 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz, //45 149 150 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz, //46 151 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz, //47 152 153 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz, //48 154 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz, //49 155 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz, //50 156 157 E_PNL_SUPPORTED_LPLL_MAX, //51 158 } E_PNL_SUPPORTED_LPLL_TYPE; 159 160 typedef struct 161 { 162 MS_U8 address; 163 MS_U16 value; 164 MS_U16 mask; 165 }TBLStruct,*pTBLStruct; 166 167 TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= 168 { 169 { //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 170 //Address,Value,Mask 171 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 172 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 173 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 174 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 175 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 176 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 177 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 178 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 179 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 180 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 181 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 182 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 183 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 184 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 185 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 186 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 187 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 188 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 189 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 190 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 191 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 192 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 193 {0x33,0x0020,0x0020},//reg_lpll2_pd 194 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 195 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 196 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 197 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 198 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 199 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 200 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 201 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 202 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 203 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 204 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 205 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 206 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 207 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 208 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 209 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 210 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 211 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 212 }, 213 214 { //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 215 //Address,Value,Mask 216 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 217 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 218 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 219 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 220 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 221 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 222 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 223 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[3:0] 224 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 225 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 226 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 227 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 228 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 229 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 230 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 231 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 232 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 233 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 234 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 235 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 236 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 237 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 238 {0x33,0x0020,0x0020},//reg_lpll2_pd 239 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 240 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 241 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 242 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 243 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 244 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 245 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 246 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 247 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 248 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 249 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 250 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 251 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 252 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 253 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 254 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 255 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 256 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 257 }, 258 259 { //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 260 //Address,Value,Mask 261 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 262 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 263 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 264 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 265 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 266 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 267 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 268 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[3:0] 269 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 270 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 271 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 272 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 273 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 274 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 275 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 276 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 277 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 278 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 279 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 280 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 281 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 282 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 283 {0x33,0x0020,0x0020},//reg_lpll2_pd 284 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 285 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 286 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 287 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 288 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 289 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 290 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 291 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 292 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 293 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 294 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 295 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 296 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 297 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 298 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 299 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 300 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 301 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 302 }, 303 304 { //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 305 //Address,Value,Mask 306 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 307 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 308 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 309 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 310 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 311 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 312 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 313 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[3:0] 314 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 315 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 316 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 317 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 318 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 319 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 320 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 321 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 322 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 323 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 324 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 325 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 326 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 327 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 328 {0x33,0x0020,0x0020},//reg_lpll2_pd 329 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 330 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 331 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 332 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 333 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 334 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 335 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 336 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 337 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 338 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 339 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 340 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 341 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 342 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 343 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 344 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 345 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 346 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 347 }, 348 349 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to300MHz NO.4 350 //Address,Value,Mask 351 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 352 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 353 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 354 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 355 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 356 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 357 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 358 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 359 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 360 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 361 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 362 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 363 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 364 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 365 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 366 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 367 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 368 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 369 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 370 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 371 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 372 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 373 {0x33,0x0020,0x0020},//reg_lpll2_pd 374 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 375 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 376 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 377 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 378 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 379 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 380 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 381 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 382 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 383 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 384 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 385 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 386 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 387 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 388 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 389 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 390 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 391 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 392 }, 393 394 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz NO.5 395 //Address,Value,Mask 396 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 397 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 398 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 399 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 400 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 401 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 402 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 403 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 404 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 405 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 406 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 407 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 408 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 409 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 410 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 411 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 412 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 413 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 414 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 415 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 416 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 417 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 418 {0x33,0x0020,0x0020},//reg_lpll2_pd 419 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 420 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 421 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 422 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 423 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 424 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 425 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 426 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 427 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 428 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 429 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 430 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 431 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 432 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 433 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 434 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 435 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 436 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 437 }, 438 439 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.6 440 //Address,Value,Mask 441 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 442 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 443 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 444 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 445 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 446 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 447 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 448 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 449 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 450 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 451 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 452 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 453 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 454 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 455 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 456 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 457 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 458 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 459 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 460 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 461 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 462 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 463 {0x33,0x0020,0x0020},//reg_lpll2_pd 464 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 465 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 466 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 467 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 468 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 469 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 470 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 471 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 472 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 473 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 474 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 475 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 476 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 477 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 478 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 479 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 480 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 481 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 482 }, 483 484 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.7 485 //Address,Value,Mask 486 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 487 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 488 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 489 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 490 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 491 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 492 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 493 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 494 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 495 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 496 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 497 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 498 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 499 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 500 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 501 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 502 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 503 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 504 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 505 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 506 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 507 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 508 {0x33,0x0020,0x0020},//reg_lpll2_pd 509 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 510 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 511 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 512 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 513 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 514 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 515 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 516 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 517 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 518 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 519 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 520 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 521 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 522 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 523 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 524 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 525 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 526 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 527 }, 528 529 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.8 530 //Address,Value,Mask 531 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 532 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 533 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 534 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 535 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 536 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 537 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 538 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 539 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 540 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 541 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 542 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 543 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 544 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 545 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 546 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 547 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 548 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 549 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 550 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 551 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 552 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 553 {0x33,0x0020,0x0020},//reg_lpll2_pd 554 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 555 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 556 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 557 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 558 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 559 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 560 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 561 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 562 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 563 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 564 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 565 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 566 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 567 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 568 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 569 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 570 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 571 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 572 }, 573 574 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.9 575 //Address,Value,Mask 576 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 577 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 578 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 579 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 580 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 581 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 582 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 583 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[3:0] 584 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 585 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 586 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 587 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 588 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 589 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 590 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 591 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 592 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 593 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 594 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 595 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 596 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 597 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 598 {0x33,0x0020,0x0020},//reg_lpll2_pd 599 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 600 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 601 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 602 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 603 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 604 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 605 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 606 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 607 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 608 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 609 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 610 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 611 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 612 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 613 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 614 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 615 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 616 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 617 }, 618 619 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to300MHz NO.10 620 //Address,Value,Mask 621 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 622 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 623 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 624 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 625 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 626 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[5:4] 627 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 628 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 629 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 630 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 631 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 632 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 633 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 634 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 635 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 636 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 637 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 638 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 639 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 640 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 641 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 642 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 643 {0x33,0x0020,0x0020},//reg_lpll2_pd 644 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 645 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 646 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 647 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 648 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 649 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 650 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 651 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 652 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 653 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 654 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 655 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 656 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 657 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 658 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 659 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 660 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 661 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 662 }, 663 664 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz NO.11 665 //Address,Value,Mask 666 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 667 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 668 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 669 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 670 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 671 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 672 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 673 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 674 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 675 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 676 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 677 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 678 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 679 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 680 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 681 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 682 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 683 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 684 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 685 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 686 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 687 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 688 {0x33,0x0020,0x0020},//reg_lpll2_pd 689 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 690 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 691 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 692 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 693 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 694 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 695 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 696 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 697 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 698 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 699 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 700 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 701 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 702 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 703 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 704 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 705 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 706 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 707 }, 708 709 { //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz NO.12 710 //Address,Value,Mask 711 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 712 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 713 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 714 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 715 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 716 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 717 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 718 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 719 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 720 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 721 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 722 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 723 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 724 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 725 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 726 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 727 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 728 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 729 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 730 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 731 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 732 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 733 {0x33,0x0020,0x0020},//reg_lpll2_pd 734 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 735 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 736 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 737 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 738 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 739 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 740 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 741 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 742 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 743 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 744 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 745 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 746 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 747 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 748 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 749 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 750 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 751 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 752 }, 753 754 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.13 755 //Address,Value,Mask 756 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 757 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 758 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 759 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 760 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 761 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 762 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 763 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 764 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 765 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 766 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 767 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 768 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 769 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 770 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 771 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 772 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 773 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 774 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 775 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 776 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 777 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 778 {0x33,0x0020,0x0020},//reg_lpll2_pd 779 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 780 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 781 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 782 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 783 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 784 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 785 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 786 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 787 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 788 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 789 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 790 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 791 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 792 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 793 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 794 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 795 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 796 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 797 }, 798 799 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.14 800 //Address,Value,Mask 801 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 802 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 803 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 804 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 805 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 806 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 807 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 808 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 809 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 810 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 811 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 812 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 813 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 814 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 815 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 816 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 817 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 818 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 819 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 820 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 821 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 822 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 823 {0x33,0x0020,0x0020},//reg_lpll2_pd 824 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 825 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 826 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 827 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 828 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 829 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 830 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 831 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 832 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 833 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 834 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 835 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 836 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 837 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 838 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 839 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 840 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 841 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 842 }, 843 844 { //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.15 845 //Address,Value,Mask 846 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 847 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 848 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 849 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 850 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 851 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 852 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 853 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 854 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 855 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 856 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 857 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 858 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 859 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 860 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 861 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 862 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 863 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 864 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 865 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 866 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 867 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 868 {0x33,0x0020,0x0020},//reg_lpll2_pd 869 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 870 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 871 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 872 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 873 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 874 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 875 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 876 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 877 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 878 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 879 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 880 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 881 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 882 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 883 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 884 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 885 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 886 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 887 }, 888 889 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.16 890 //Address,Value,Mask 891 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 892 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 893 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 894 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 895 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 896 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 897 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 898 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 899 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 900 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 901 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 902 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 903 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 904 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 905 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 906 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 907 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 908 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 909 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 910 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 911 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 912 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 913 {0x33,0x0020,0x0020},//reg_lpll2_pd 914 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 915 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 916 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 917 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 918 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 919 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 920 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 921 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 922 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 923 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 924 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 925 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 926 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 927 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 928 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 929 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 930 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 931 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 932 }, 933 934 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.17 935 //Address,Value,Mask 936 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 937 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 938 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 939 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 940 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 941 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 942 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 943 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 944 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 945 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 946 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 947 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 948 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 949 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 950 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 951 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 952 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 953 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 954 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 955 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 956 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 957 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 958 {0x33,0x0020,0x0020},//reg_lpll2_pd 959 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 960 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 961 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 962 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 963 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 964 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 965 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 966 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 967 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 968 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 969 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 970 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 971 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 972 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 973 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 974 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 975 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 976 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 977 }, 978 979 { //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.18 980 //Address,Value,Mask 981 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 982 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 983 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 984 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 985 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 986 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[5:4] 987 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 988 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[3:0] 989 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 990 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 991 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 992 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 993 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 994 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 995 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 996 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 997 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 998 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 999 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1000 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1001 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1002 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1003 {0x33,0x0020,0x0020},//reg_lpll2_pd 1004 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1005 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1006 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1007 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1008 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1009 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1010 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1011 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1012 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1013 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1014 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1015 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1016 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1017 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1018 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1019 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1020 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1021 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1022 }, 1023 1024 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to300MHz NO.19 1025 //Address,Value,Mask 1026 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1027 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1028 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1029 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1030 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1031 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1032 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1033 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1034 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1035 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1036 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1037 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1038 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1039 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1040 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1041 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1042 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1043 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1044 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1045 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1046 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1047 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1048 {0x33,0x0000,0x0020},//reg_lpll2_pd 1049 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1050 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1051 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1052 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1053 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1054 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1055 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1056 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1057 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1058 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1059 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1060 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1061 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1062 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1063 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1064 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1065 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1066 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1067 }, 1068 1069 { //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to150MHz NO.20 1070 //Address,Value,Mask 1071 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1072 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1073 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1074 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1075 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1076 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1077 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1078 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1079 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1080 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1081 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1082 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1083 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1084 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1085 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1086 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1087 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1088 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1089 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1090 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1091 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1092 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1093 {0x33,0x0000,0x0020},//reg_lpll2_pd 1094 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1095 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1096 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1097 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1098 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1099 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1100 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1101 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1102 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1103 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1104 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1105 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1106 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1107 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1108 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1109 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1110 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1111 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1112 }, 1113 1114 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to300MHz NO.21 1115 //Address,Value,Mask 1116 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1117 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1118 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1119 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1120 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1121 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1122 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1123 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1124 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1125 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1126 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1127 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1128 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1129 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1130 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1131 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1132 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1133 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1134 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1135 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1136 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1137 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1138 {0x33,0x0000,0x0020},//reg_lpll2_pd 1139 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1140 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1141 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1142 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1143 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1144 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1145 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1146 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1147 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1148 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1149 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1150 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1151 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1152 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1153 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1154 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1155 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1156 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1157 }, 1158 1159 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to150MHz NO.22 1160 //Address,Value,Mask 1161 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1162 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1163 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1164 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1165 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1166 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1167 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1168 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1169 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1170 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1171 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1172 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1173 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1174 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1175 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1176 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1177 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1178 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1179 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1180 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1181 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1182 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1183 {0x33,0x0000,0x0020},//reg_lpll2_pd 1184 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1185 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1186 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1187 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1188 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1189 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1190 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1191 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1192 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1193 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1194 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1195 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1196 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1197 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1198 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1199 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1200 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1201 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1202 }, 1203 1204 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_240to300MHz NO.23 1205 //Address,Value,Mask 1206 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1207 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1208 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1209 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1210 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1211 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1212 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1213 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1214 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1215 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1216 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1217 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1218 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1219 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1220 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1221 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1222 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1223 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1224 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1225 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1226 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1227 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1228 {0x33,0x0000,0x0020},//reg_lpll2_pd 1229 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1230 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1231 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1232 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1233 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1234 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1235 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1236 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1237 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1238 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1239 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1240 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1241 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1242 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1243 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1244 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1245 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1246 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1247 }, 1248 1249 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to240MHz NO.24 1250 //Address,Value,Mask 1251 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1252 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1253 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1254 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1255 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1256 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1257 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1258 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1259 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1260 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1261 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1262 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1263 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1264 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1265 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1266 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1267 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1268 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1269 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1270 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1271 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1272 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1273 {0x33,0x0000,0x0020},//reg_lpll2_pd 1274 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1275 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1276 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1277 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1278 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1279 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1280 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1281 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1282 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1283 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1284 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1285 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1286 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1287 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1288 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1289 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1290 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1291 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1292 }, 1293 1294 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to150MHz NO.25 1295 //Address,Value,Mask 1296 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1297 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1298 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1299 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1300 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1301 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1302 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1303 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1304 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1305 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1306 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1307 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1308 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1309 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1310 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1311 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1312 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1313 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1314 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1315 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1316 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1317 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1318 {0x33,0x0000,0x0020},//reg_lpll2_pd 1319 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1320 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1321 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1322 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1323 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1324 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1325 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1326 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1327 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1328 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1329 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1330 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1331 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1332 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1333 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1334 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1335 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1336 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1337 }, 1338 1339 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_180to300MHz NO.26 1340 //Address,Value,Mask 1341 {0x03,0x0014,0x001C},//reg_lpll1_ibias_ictrl 1342 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1343 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1344 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1345 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1346 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1347 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1348 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1349 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1350 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1351 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1352 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1353 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1354 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1355 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1356 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1357 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1358 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1359 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1360 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1361 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1362 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1363 {0x33,0x0000,0x0020},//reg_lpll2_pd 1364 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1365 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1366 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1367 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1368 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1369 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1370 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1371 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1372 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1373 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1374 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1375 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1376 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1377 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1378 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1379 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1380 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1381 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1382 }, 1383 1384 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to180MHz NO.27 1385 //Address,Value,Mask 1386 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1387 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1388 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1389 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1390 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1391 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1392 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1393 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1394 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1395 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1396 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1397 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1398 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1399 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1400 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1401 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1402 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1403 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1404 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1405 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1406 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1407 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1408 {0x33,0x0000,0x0020},//reg_lpll2_pd 1409 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1410 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1411 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1412 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1413 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1414 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1415 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1416 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1417 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1418 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1419 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1420 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1421 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1422 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1423 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1424 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1425 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1426 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1427 }, 1428 1429 { //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to150MHz NO.28 1430 //Address,Value,Mask 1431 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1432 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1433 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1434 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1435 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1436 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1437 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1438 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1439 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1440 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1441 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1442 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1443 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1444 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1445 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1446 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1447 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1448 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1449 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1450 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1451 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1452 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1453 {0x33,0x0000,0x0020},//reg_lpll2_pd 1454 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1455 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1456 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1457 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1458 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1459 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1460 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1461 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1462 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1463 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1464 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1465 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1466 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1467 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1468 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1469 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1470 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1471 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1472 }, 1473 1474 { //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz NO.29 1475 //Address,Value,Mask 1476 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1477 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1478 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1479 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1480 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1481 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1482 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1483 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1484 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1485 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1486 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1487 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1488 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1489 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1490 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1491 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1492 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1493 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1494 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1495 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1496 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1497 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1498 {0x33,0x0000,0x0020},//reg_lpll2_pd 1499 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1500 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1501 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1502 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1503 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1504 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1505 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1506 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1507 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1508 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1509 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1510 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1511 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1512 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1513 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1514 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1515 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1516 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1517 }, 1518 1519 { //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz NO.30 1520 //Address,Value,Mask 1521 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1522 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1523 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1524 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1525 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1526 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1527 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1528 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1529 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1530 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1531 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1532 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1533 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1534 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1535 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1536 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1537 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1538 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1539 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1540 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1541 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1542 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1543 {0x33,0x0000,0x0020},//reg_lpll2_pd 1544 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1545 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1546 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1547 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1548 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1549 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1550 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1551 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1552 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1553 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1554 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1555 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1556 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1557 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1558 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1559 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1560 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1561 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1562 }, 1563 1564 { //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz NO.31 1565 //Address,Value,Mask 1566 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1567 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1568 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1569 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1570 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1571 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1572 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1573 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1574 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1575 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1576 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1577 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1578 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1579 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1580 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1581 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1582 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1583 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1584 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1585 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1586 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1587 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1588 {0x33,0x0000,0x0020},//reg_lpll2_pd 1589 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1590 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1591 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1592 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1593 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1594 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1595 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1596 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1597 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1598 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1599 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1600 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1601 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1602 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1603 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1604 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1605 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1606 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1607 }, 1608 1609 { //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz NO.32 1610 //Address,Value,Mask 1611 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1612 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1613 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1614 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1615 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1616 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1617 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1618 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1619 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1620 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1621 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1622 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1623 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1624 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1625 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1626 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1627 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1628 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1629 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1630 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1631 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1632 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1633 {0x33,0x0000,0x0020},//reg_lpll2_pd 1634 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1635 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1636 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1637 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1638 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1639 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1640 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1641 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1642 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1643 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1644 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1645 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1646 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1647 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1648 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1649 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1650 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1651 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1652 }, 1653 1654 { //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to300MHz NO.33 1655 //Address,Value,Mask 1656 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1657 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1658 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1659 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1660 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1661 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1662 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1663 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1664 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1665 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1666 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1667 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1668 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1669 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1670 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1671 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1672 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1673 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1674 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1675 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1676 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1677 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1678 {0x33,0x0000,0x0020},//reg_lpll2_pd 1679 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1680 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1681 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1682 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1683 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1684 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1685 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1686 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1687 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1688 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1689 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1690 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1691 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1692 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1693 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1694 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1695 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1696 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1697 }, 1698 1699 { //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to150MHz NO.34 1700 //Address,Value,Mask 1701 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1702 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1703 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1704 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1705 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1706 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1707 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1708 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1709 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1710 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1711 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1712 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1713 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1714 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1715 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1716 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1717 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1718 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1719 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1720 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1721 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1722 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1723 {0x33,0x0000,0x0020},//reg_lpll2_pd 1724 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1725 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1726 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1727 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1728 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1729 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1730 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1731 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1732 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1733 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1734 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1735 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1736 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1737 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1738 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1739 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1740 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1741 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1742 }, 1743 1744 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.35 1745 //Address,Value,Mask 1746 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1747 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1748 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1749 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1750 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1751 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1752 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1753 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1754 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1755 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1756 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1757 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1758 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1759 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1760 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1761 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1762 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1763 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1764 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1765 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1766 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1767 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1768 {0x33,0x0000,0x0020},//reg_lpll2_pd 1769 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1770 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1771 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1772 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1773 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1774 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1775 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1776 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1777 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1778 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1779 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1780 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1781 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1782 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1783 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 1784 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1785 {0x38,0x0100,0x0100},//reg_lpll1_scalar2fifo_div2 1786 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1787 }, 1788 1789 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.36 1790 //Address,Value,Mask 1791 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1792 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1793 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1794 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1795 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1796 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1797 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1798 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1799 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1800 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1801 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1802 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1803 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1804 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1805 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1806 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1807 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1808 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1809 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1810 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1811 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1812 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1813 {0x33,0x0000,0x0020},//reg_lpll2_pd 1814 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1815 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1816 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1817 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1818 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1819 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1820 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1821 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1822 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1823 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1824 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1825 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1826 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1827 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1828 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 1829 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1830 {0x38,0x0100,0x0100},//reg_lpll1_scalar2fifo_div2 1831 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1832 }, 1833 1834 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to300MHz NO.37 1835 //Address,Value,Mask 1836 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1837 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1838 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1839 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1840 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1841 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1842 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1843 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1844 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1845 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1846 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1847 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1848 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1849 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1850 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1851 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1852 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1853 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1854 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1855 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1856 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1857 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1858 {0x33,0x0000,0x0020},//reg_lpll2_pd 1859 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1860 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1861 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1862 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1863 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1864 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1865 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1866 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1867 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1868 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1869 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1870 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1871 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1872 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1873 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 1874 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1875 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1876 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1877 }, 1878 1879 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to150MHz NO.38 1880 //Address,Value,Mask 1881 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1882 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1883 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1884 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1885 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1886 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 1887 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1888 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[3:0] 1889 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1890 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1891 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1892 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1893 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1894 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1895 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1896 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1897 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1898 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1899 {0x36,0x8000,0x8000},//reg_lpll1_test[15] 1900 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1901 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1902 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1903 {0x33,0x0000,0x0020},//reg_lpll2_pd 1904 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1905 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1906 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1907 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1908 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1909 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1910 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1911 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1912 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1913 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1914 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1915 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1916 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1917 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1918 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 1919 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1920 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1921 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1922 }, 1923 1924 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.39 1925 //Address,Value,Mask 1926 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1927 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1928 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1929 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1930 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1931 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[5:4] 1932 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1933 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 1934 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1935 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1936 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1937 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1938 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1939 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1940 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1941 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1942 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1943 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1944 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1945 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1946 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1947 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1948 {0x33,0x0020,0x0020},//reg_lpll2_pd 1949 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1950 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1951 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1952 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1953 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1954 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1955 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1956 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1957 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1958 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1959 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1960 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1961 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1962 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 1963 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1964 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1965 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1966 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 1967 }, 1968 1969 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.40 1970 //Address,Value,Mask 1971 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1972 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1973 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1974 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1975 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 1976 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 1977 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1978 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 1979 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1980 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1981 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1982 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1983 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1984 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1985 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1986 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1987 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1988 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1989 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 1990 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 1991 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1992 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 1993 {0x33,0x0020,0x0020},//reg_lpll2_pd 1994 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1995 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1996 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1997 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1998 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1999 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2000 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2001 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2002 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2003 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2004 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2005 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2006 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2007 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2008 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2009 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2010 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2011 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2012 }, 2013 2014 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.41 2015 //Address,Value,Mask 2016 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2017 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2018 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2019 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2020 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2021 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 2022 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2023 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2024 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2025 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2026 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2027 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2028 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2029 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2030 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2031 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2032 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2033 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2034 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2035 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2036 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2037 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2038 {0x33,0x0020,0x0020},//reg_lpll2_pd 2039 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2040 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2041 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2042 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2043 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2044 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2045 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2046 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2047 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2048 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2049 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2050 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2051 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2052 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2053 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2054 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2055 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2056 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2057 }, 2058 2059 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.42 2060 //Address,Value,Mask 2061 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2062 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2063 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2064 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2065 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2066 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[5:4] 2067 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2068 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2069 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2070 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2071 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2072 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2073 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2074 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2075 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2076 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2077 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2078 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2079 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2080 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2081 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2082 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2083 {0x33,0x0020,0x0020},//reg_lpll2_pd 2084 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2085 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2086 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2087 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2088 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2089 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2090 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2091 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2092 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2093 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2094 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2095 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2096 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2097 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2098 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2099 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2100 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2101 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2102 }, 2103 2104 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.43 2105 //Address,Value,Mask 2106 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2107 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2108 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2109 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2110 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2111 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 2112 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2113 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2114 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2115 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2116 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2117 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2118 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2119 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2120 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2121 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2122 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2123 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2124 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2125 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2126 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2127 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2128 {0x33,0x0020,0x0020},//reg_lpll2_pd 2129 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2130 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2131 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2132 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2133 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2134 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2135 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2136 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2137 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2138 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2139 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2140 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2141 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2142 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2143 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2144 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2145 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2146 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2147 }, 2148 2149 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.44 2150 //Address,Value,Mask 2151 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2152 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2153 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2154 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2155 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2156 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 2157 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2158 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2159 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2160 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2161 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2162 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2163 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2164 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2165 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2166 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2167 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2168 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2169 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2170 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2171 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2172 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2173 {0x33,0x0020,0x0020},//reg_lpll2_pd 2174 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2175 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2176 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2177 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2178 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2179 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2180 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2181 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2182 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2183 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2184 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2185 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2186 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2187 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2188 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2189 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2190 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2191 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2192 }, 2193 2194 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.45 2195 //Address,Value,Mask 2196 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2197 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2198 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2199 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2200 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2201 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 2202 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2203 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2204 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2205 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2206 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2207 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2208 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2209 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2210 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2211 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2212 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2213 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2214 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2215 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2216 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2217 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2218 {0x33,0x0020,0x0020},//reg_lpll2_pd 2219 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2220 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2221 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2222 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2223 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2224 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2225 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2226 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2227 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2228 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2229 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2230 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2231 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2232 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2233 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2234 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2235 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2236 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2237 }, 2238 2239 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.46 2240 //Address,Value,Mask 2241 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2242 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2243 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2244 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2245 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2246 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 2247 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2248 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2249 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2250 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2251 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2252 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2253 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2254 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2255 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2256 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2257 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2258 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2259 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2260 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2261 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2262 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2263 {0x33,0x0020,0x0020},//reg_lpll2_pd 2264 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2265 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2266 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2267 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2268 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2269 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2270 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2271 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2272 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2273 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2274 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2275 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2276 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2277 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2278 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2279 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2280 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2281 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2282 }, 2283 2284 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.47 2285 //Address,Value,Mask 2286 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2287 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2288 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2289 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2290 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2291 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 2292 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2293 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2294 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2295 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2296 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2297 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2298 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2299 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2300 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2301 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2302 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2303 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2304 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2305 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2306 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2307 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2308 {0x33,0x0020,0x0020},//reg_lpll2_pd 2309 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2310 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2311 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2312 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2313 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2314 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2315 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2316 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2317 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2318 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2319 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2320 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2321 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2322 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2323 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2324 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2325 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2326 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2327 }, 2328 2329 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.48 2330 //Address,Value,Mask 2331 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2332 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2333 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2334 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2335 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2336 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[5:4] 2337 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2338 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2339 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2340 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2341 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2342 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2343 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2344 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2345 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2346 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2347 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2348 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2349 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2350 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2351 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2352 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2353 {0x33,0x0020,0x0020},//reg_lpll2_pd 2354 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2355 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2356 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2357 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2358 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2359 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2360 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2361 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2362 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2363 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2364 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2365 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2366 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2367 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2368 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2369 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2370 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2371 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2372 }, 2373 2374 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.49 2375 //Address,Value,Mask 2376 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2377 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2378 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2379 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2380 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2381 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 2382 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2383 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2384 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2385 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2386 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2387 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2388 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2389 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2390 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2391 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2392 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2393 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2394 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2395 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2396 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2397 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2398 {0x33,0x0020,0x0020},//reg_lpll2_pd 2399 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2400 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2401 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2402 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2403 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2404 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2405 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2406 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2407 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2408 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2409 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2410 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2411 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2412 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2413 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2414 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2415 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2416 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2417 }, 2418 2419 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.50 2420 //Address,Value,Mask 2421 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2422 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2423 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2424 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2425 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2426 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[5:4] 2427 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2428 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[3:0] 2429 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2430 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2431 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2432 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2433 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2434 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2435 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2436 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2437 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2438 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2439 {0x36,0x0000,0x8000},//reg_lpll1_test[15] 2440 {0x37,0x0000,0x0001},//reg_lpll1_test[16] 2441 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2442 {0x37,0x0000,0x0040},//reg_lpll1_test[22] 2443 {0x33,0x0020,0x0020},//reg_lpll2_pd 2444 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2445 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2446 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2447 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2448 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2449 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2450 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2451 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2452 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2453 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2454 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2455 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2456 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2457 {0x2E,0x0010,0x0010},//reg_lpll1_en_scalar 2458 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2459 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2460 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2461 {0x36,0x0000,0x0004},//reg_lpll1_test[2] 2462 }, 2463 2464 }; 2465 MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= 2466 { 2467 12, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 2468 12, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 2469 12, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 2470 12, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 2471 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to300MHz NO.4 2472 32, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz NO.5 2473 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.6 2474 32, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.7 2475 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.8 2476 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.9 2477 64, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to300MHz NO.10 2478 64, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz NO.11 2479 64, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz NO.12 2480 64, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.13 2481 64, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.14 2482 64, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.15 2483 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.16 2484 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.17 2485 32, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.18 2486 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to300MHz NO.19 2487 8, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to150MHz NO.20 2488 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to300MHz NO.21 2489 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to150MHz NO.22 2490 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_240to300MHz NO.23 2491 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to240MHz NO.24 2492 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to150MHz NO.25 2493 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_180to300MHz NO.26 2494 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to180MHz NO.27 2495 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to150MHz NO.28 2496 8, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz NO.29 2497 8, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz NO.30 2498 8, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz NO.31 2499 8, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz NO.32 2500 8, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to300MHz NO.33 2501 8, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to150MHz NO.34 2502 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.35 2503 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.36 2504 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to300MHz NO.37 2505 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to150MHz NO.38 2506 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.39 2507 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.40 2508 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.41 2509 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.42 2510 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.43 2511 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.44 2512 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.45 2513 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.46 2514 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.47 2515 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.48 2516 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.49 2517 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.50 2518 }; 2519 MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= 2520 { 2521 8, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 2522 16, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 2523 32, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 2524 32, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 2525 10, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to300MHz NO.4 2526 10, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_10BIT_4K_150to150MHz NO.5 2527 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to150MHz NO.6 2528 20, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_10BIT_75to75MHz NO.7 2529 40, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to75MHz NO.8 2530 40, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_10BIT_37_5to37_5MHz NO.9 2531 15, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_200to300MHz NO.10 2532 30, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to200MHz NO.11 2533 30, //E_PNL_SUPPORTED_LPLL_VBY1_8CH_8BIT_4K_150to150MHz NO.12 2534 30, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_100to150MHz NO.13 2535 60, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to100MHz NO.14 2536 60, //E_PNL_SUPPORTED_LPLL_VBY1_4CH_8BIT_75to75MHz NO.15 2537 30, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_50to75MHz NO.16 2538 60, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to50MHz NO.17 2539 60, //E_PNL_SUPPORTED_LPLL_VBY1_2CH_8BIT_37_5to37_5MHz NO.18 2540 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to300MHz NO.19 2541 4, //E_PNL_SUPPORTED_LPLL_EPI_24_10BIT_12PAIR_4K_CASE1_150to150MHz NO.20 2542 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to300MHz NO.21 2543 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_12PAIR_4K_150to150MHz NO.22 2544 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_240to300MHz NO.23 2545 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to240MHz NO.24 2546 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_8PAIR_4K_EPI3G_FOR_TRY_150to150MHz NO.25 2547 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_180to300MHz NO.26 2548 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to180MHz NO.27 2549 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8BIT_6PAIR_4K_EPI3G_FOR_TRY_150to150MHz NO.28 2550 4, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to300MHz NO.29 2551 4, //E_PNL_SUPPORTED_LPLL_CMPI_24_10BIT_12PAIR_X1_150to150MHz NO.30 2552 4, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to300MHz NO.31 2553 4, //E_PNL_SUPPORTED_LPLL_CMPI_27_8BIT_12PAIR_X1_150to150MHz NO.32 2554 4, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to300MHz NO.33 2555 4, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_4K_150to150MHz NO.34 2556 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to300MHz NO.35 2557 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.36 2558 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to300MHz NO.37 2559 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_X1_DUAL_150to150MHz NO.38 2560 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.39 2561 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.40 2562 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.41 2563 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.42 2564 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.43 2565 28, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.44 2566 28, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.45 2567 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.46 2568 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.47 2569 14, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to75MHz NO.48 2570 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.49 2571 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.50 2572 }; 2573 2574 #endif //_LPLL_TBL_H_ 2575