xref: /utopia/UTPA2-700.0.x/modules/xc/hal/kano/xc/include/hwreg_hdmi.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef) 
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94 
95 #ifndef _HWREG_HDMI_H_
96 #define _HWREG_HDMI_H_
97 
98 
99 //=============================================================
100 // DVI DTOP
101 
102 #define REG_DVI_DTOP_00_L        (REG_DVI_DTOP_BASE + 0x00)
103 #define REG_DVI_DTOP_00_H        (REG_DVI_DTOP_BASE + 0x01)
104 #define REG_DVI_DTOP_01_L        (REG_DVI_DTOP_BASE + 0x02)
105 #define REG_DVI_DTOP_01_H        (REG_DVI_DTOP_BASE + 0x03)
106 #define REG_DVI_DTOP_02_L        (REG_DVI_DTOP_BASE + 0x04)
107 #define REG_DVI_DTOP_02_H        (REG_DVI_DTOP_BASE + 0x05)
108 #define REG_DVI_DTOP_03_L        (REG_DVI_DTOP_BASE + 0x06)
109 #define REG_DVI_DTOP_03_H        (REG_DVI_DTOP_BASE + 0x07)
110 #define REG_DVI_DTOP_04_L        (REG_DVI_DTOP_BASE + 0x08)
111 #define REG_DVI_DTOP_04_H        (REG_DVI_DTOP_BASE + 0x09)
112 #define REG_DVI_DTOP_05_L        (REG_DVI_DTOP_BASE + 0x0A)
113 #define REG_DVI_DTOP_05_H        (REG_DVI_DTOP_BASE + 0x0B)
114 #define REG_DVI_DTOP_06_L        (REG_DVI_DTOP_BASE + 0x0C)
115 #define REG_DVI_DTOP_06_H        (REG_DVI_DTOP_BASE + 0x0D)
116 #define REG_DVI_DTOP_07_L        (REG_DVI_DTOP_BASE + 0x0E)
117 #define REG_DVI_DTOP_07_H        (REG_DVI_DTOP_BASE + 0x0F)
118 #define REG_DVI_DTOP_08_L        (REG_DVI_DTOP_BASE + 0x10)
119 #define REG_DVI_DTOP_08_H        (REG_DVI_DTOP_BASE + 0x11)
120 #define REG_DVI_DTOP_09_L        (REG_DVI_DTOP_BASE + 0x12)
121 #define REG_DVI_DTOP_09_H        (REG_DVI_DTOP_BASE + 0x13)
122 #define REG_DVI_DTOP_0A_L        (REG_DVI_DTOP_BASE + 0x14)
123 #define REG_DVI_DTOP_0A_H        (REG_DVI_DTOP_BASE + 0x15)
124 #define REG_DVI_DTOP_0B_L        (REG_DVI_DTOP_BASE + 0x16)
125 #define REG_DVI_DTOP_0B_H        (REG_DVI_DTOP_BASE + 0x17)
126 #define REG_DVI_DTOP_0C_L        (REG_DVI_DTOP_BASE + 0x18)
127 #define REG_DVI_DTOP_0C_H        (REG_DVI_DTOP_BASE + 0x19)
128 #define REG_DVI_DTOP_0D_L        (REG_DVI_DTOP_BASE + 0x1A)
129 #define REG_DVI_DTOP_0D_H        (REG_DVI_DTOP_BASE + 0x1B)
130 #define REG_DVI_DTOP_0E_L        (REG_DVI_DTOP_BASE + 0x1C)
131 #define REG_DVI_DTOP_0E_H        (REG_DVI_DTOP_BASE + 0x1D)
132 #define REG_DVI_DTOP_0F_L        (REG_DVI_DTOP_BASE + 0x1E)
133 #define REG_DVI_DTOP_0F_H        (REG_DVI_DTOP_BASE + 0x1F)
134 #define REG_DVI_DTOP_10_L        (REG_DVI_DTOP_BASE + 0x20)
135 #define REG_DVI_DTOP_10_H        (REG_DVI_DTOP_BASE + 0x21)
136 #define REG_DVI_DTOP_11_L        (REG_DVI_DTOP_BASE + 0x22)
137 #define REG_DVI_DTOP_11_H        (REG_DVI_DTOP_BASE + 0x23)
138 #define REG_DVI_DTOP_12_L        (REG_DVI_DTOP_BASE + 0x24)
139 #define REG_DVI_DTOP_12_H        (REG_DVI_DTOP_BASE + 0x25)
140 #define REG_DVI_DTOP_13_L        (REG_DVI_DTOP_BASE + 0x26)
141 #define REG_DVI_DTOP_13_H        (REG_DVI_DTOP_BASE + 0x27)
142 #define REG_DVI_DTOP_14_L        (REG_DVI_DTOP_BASE + 0x28)
143 #define REG_DVI_DTOP_14_H        (REG_DVI_DTOP_BASE + 0x29)
144 #define REG_DVI_DTOP_15_L        (REG_DVI_DTOP_BASE + 0x2A)
145 #define REG_DVI_DTOP_15_H        (REG_DVI_DTOP_BASE + 0x2B)
146 #define REG_DVI_DTOP_16_L        (REG_DVI_DTOP_BASE + 0x2C)
147 #define REG_DVI_DTOP_16_H        (REG_DVI_DTOP_BASE + 0x2D)
148 #define REG_DVI_DTOP_17_L        (REG_DVI_DTOP_BASE + 0x2E)
149 #define REG_DVI_DTOP_17_H        (REG_DVI_DTOP_BASE + 0x2F)
150 #define REG_DVI_DTOP_18_L        (REG_DVI_DTOP_BASE + 0x30)
151 #define REG_DVI_DTOP_18_H        (REG_DVI_DTOP_BASE + 0x31)
152 #define REG_DVI_DTOP_19_L        (REG_DVI_DTOP_BASE + 0x32)
153 #define REG_DVI_DTOP_19_H        (REG_DVI_DTOP_BASE + 0x33)
154 #define REG_DVI_DTOP_1A_L        (REG_DVI_DTOP_BASE + 0x34)
155 #define REG_DVI_DTOP_1A_H        (REG_DVI_DTOP_BASE + 0x35)
156 #define REG_DVI_DTOP_1B_L        (REG_DVI_DTOP_BASE + 0x36)
157 #define REG_DVI_DTOP_1B_H        (REG_DVI_DTOP_BASE + 0x37)
158 #define REG_DVI_DTOP_1C_L        (REG_DVI_DTOP_BASE + 0x38)
159 #define REG_DVI_DTOP_1C_H        (REG_DVI_DTOP_BASE + 0x39)
160 #define REG_DVI_DTOP_1D_L        (REG_DVI_DTOP_BASE + 0x3A)
161 #define REG_DVI_DTOP_1D_H        (REG_DVI_DTOP_BASE + 0x3B)
162 #define REG_DVI_DTOP_1E_L        (REG_DVI_DTOP_BASE + 0x3C)
163 #define REG_DVI_DTOP_1E_H        (REG_DVI_DTOP_BASE + 0x3D)
164 #define REG_DVI_DTOP_1F_L        (REG_DVI_DTOP_BASE + 0x3E)
165 #define REG_DVI_DTOP_1F_H        (REG_DVI_DTOP_BASE + 0x3F)
166 #define REG_DVI_DTOP_20_L        (REG_DVI_DTOP_BASE + 0x40)
167 #define REG_DVI_DTOP_20_H        (REG_DVI_DTOP_BASE + 0x41)
168 #define REG_DVI_DTOP_21_L        (REG_DVI_DTOP_BASE + 0x42)
169 #define REG_DVI_DTOP_21_H        (REG_DVI_DTOP_BASE + 0x43)
170 #define REG_DVI_DTOP_22_L        (REG_DVI_DTOP_BASE + 0x44)
171 #define REG_DVI_DTOP_22_H        (REG_DVI_DTOP_BASE + 0x45)
172 #define REG_DVI_DTOP_23_L        (REG_DVI_DTOP_BASE + 0x46)
173 #define REG_DVI_DTOP_23_H        (REG_DVI_DTOP_BASE + 0x47)
174 #define REG_DVI_DTOP_24_L        (REG_DVI_DTOP_BASE + 0x48)
175 #define REG_DVI_DTOP_24_H        (REG_DVI_DTOP_BASE + 0x49)
176 #define REG_DVI_DTOP_25_L        (REG_DVI_DTOP_BASE + 0x4A)
177 #define REG_DVI_DTOP_25_H        (REG_DVI_DTOP_BASE + 0x4B)
178 #define REG_DVI_DTOP_26_L        (REG_DVI_DTOP_BASE + 0x4C)
179 #define REG_DVI_DTOP_26_H        (REG_DVI_DTOP_BASE + 0x4D)
180 #define REG_DVI_DTOP_27_L        (REG_DVI_DTOP_BASE + 0x4E)
181 #define REG_DVI_DTOP_27_H        (REG_DVI_DTOP_BASE + 0x4F)
182 #define REG_DVI_DTOP_28_L        (REG_DVI_DTOP_BASE + 0x50)
183 #define REG_DVI_DTOP_28_H        (REG_DVI_DTOP_BASE + 0x51)
184 #define REG_DVI_DTOP_29_L        (REG_DVI_DTOP_BASE + 0x52)
185 #define REG_DVI_DTOP_29_H        (REG_DVI_DTOP_BASE + 0x53)
186 #define REG_DVI_DTOP_2A_L        (REG_DVI_DTOP_BASE + 0x54)
187 #define REG_DVI_DTOP_2A_H        (REG_DVI_DTOP_BASE + 0x55)
188 #define REG_DVI_DTOP_2B_L        (REG_DVI_DTOP_BASE + 0x56)
189 #define REG_DVI_DTOP_2B_H        (REG_DVI_DTOP_BASE + 0x57)
190 #define REG_DVI_DTOP_2C_L        (REG_DVI_DTOP_BASE + 0x58)
191 #define REG_DVI_DTOP_2C_H        (REG_DVI_DTOP_BASE + 0x59)
192 #define REG_DVI_DTOP_2D_L        (REG_DVI_DTOP_BASE + 0x5A)
193 #define REG_DVI_DTOP_2D_H        (REG_DVI_DTOP_BASE + 0x5B)
194 #define REG_DVI_DTOP_2E_L        (REG_DVI_DTOP_BASE + 0x5C)
195 #define REG_DVI_DTOP_2E_H        (REG_DVI_DTOP_BASE + 0x5D)
196 #define REG_DVI_DTOP_2F_L        (REG_DVI_DTOP_BASE + 0x5E)
197 #define REG_DVI_DTOP_2F_H        (REG_DVI_DTOP_BASE + 0x5F)
198 #define REG_DVI_DTOP_30_L        (REG_DVI_DTOP_BASE + 0x60)
199 #define REG_DVI_DTOP_30_H        (REG_DVI_DTOP_BASE + 0x61)
200 #define REG_DVI_DTOP_31_L        (REG_DVI_DTOP_BASE + 0x62)
201 #define REG_DVI_DTOP_31_H        (REG_DVI_DTOP_BASE + 0x63)
202 #define REG_DVI_DTOP_32_L        (REG_DVI_DTOP_BASE + 0x64)
203 #define REG_DVI_DTOP_32_H        (REG_DVI_DTOP_BASE + 0x65)
204 #define REG_DVI_DTOP_33_L        (REG_DVI_DTOP_BASE + 0x66)
205 #define REG_DVI_DTOP_33_H        (REG_DVI_DTOP_BASE + 0x67)
206 #define REG_DVI_DTOP_34_L        (REG_DVI_DTOP_BASE + 0x68)
207 #define REG_DVI_DTOP_34_H        (REG_DVI_DTOP_BASE + 0x69)
208 #define REG_DVI_DTOP_35_L        (REG_DVI_DTOP_BASE + 0x6A)
209 #define REG_DVI_DTOP_35_H        (REG_DVI_DTOP_BASE + 0x6B)
210 #define REG_DVI_DTOP_36_L        (REG_DVI_DTOP_BASE + 0x6C)
211 #define REG_DVI_DTOP_36_H        (REG_DVI_DTOP_BASE + 0x6D)
212 #define REG_DVI_DTOP_37_L        (REG_DVI_DTOP_BASE + 0x6E)
213 #define REG_DVI_DTOP_37_H        (REG_DVI_DTOP_BASE + 0x6F)
214 #define REG_DVI_DTOP_38_L        (REG_DVI_DTOP_BASE + 0x70)
215 #define REG_DVI_DTOP_38_H        (REG_DVI_DTOP_BASE + 0x71)
216 #define REG_DVI_DTOP_39_L        (REG_DVI_DTOP_BASE + 0x72)
217 #define REG_DVI_DTOP_39_H        (REG_DVI_DTOP_BASE + 0x73)
218 #define REG_DVI_DTOP_3A_L        (REG_DVI_DTOP_BASE + 0x74)
219 #define REG_DVI_DTOP_3A_H        (REG_DVI_DTOP_BASE + 0x75)
220 #define REG_DVI_DTOP_3B_L        (REG_DVI_DTOP_BASE + 0x76)
221 #define REG_DVI_DTOP_3B_H        (REG_DVI_DTOP_BASE + 0x77)
222 #define REG_DVI_DTOP_3C_L        (REG_DVI_DTOP_BASE + 0x78)
223 #define REG_DVI_DTOP_3C_H        (REG_DVI_DTOP_BASE + 0x79)
224 #define REG_DVI_DTOP_3D_L        (REG_DVI_DTOP_BASE + 0x7A)
225 #define REG_DVI_DTOP_3D_H        (REG_DVI_DTOP_BASE + 0x7B)
226 #define REG_DVI_DTOP_3E_L        (REG_DVI_DTOP_BASE + 0x7C)
227 #define REG_DVI_DTOP_3E_H        (REG_DVI_DTOP_BASE + 0x7D)
228 #define REG_DVI_DTOP_3F_L        (REG_DVI_DTOP_BASE + 0x7E)
229 #define REG_DVI_DTOP_3F_H        (REG_DVI_DTOP_BASE + 0x7F)
230 
231 // DVI DTOP1
232 #define REG_DVI_DTOP1_00_L        (REG_DVI_DTOP1_BASE + 0x00)
233 #define REG_DVI_DTOP1_00_H        (REG_DVI_DTOP1_BASE + 0x01)
234 #define REG_DVI_DTOP1_01_L        (REG_DVI_DTOP1_BASE + 0x02)
235 #define REG_DVI_DTOP1_01_H        (REG_DVI_DTOP1_BASE + 0x03)
236 #define REG_DVI_DTOP1_02_L        (REG_DVI_DTOP1_BASE + 0x04)
237 #define REG_DVI_DTOP1_02_H        (REG_DVI_DTOP1_BASE + 0x05)
238 #define REG_DVI_DTOP1_03_L        (REG_DVI_DTOP1_BASE + 0x06)
239 #define REG_DVI_DTOP1_03_H        (REG_DVI_DTOP1_BASE + 0x07)
240 #define REG_DVI_DTOP1_05_L        (REG_DVI_DTOP1_BASE + 0x0A)
241 #define REG_DVI_DTOP1_05_H        (REG_DVI_DTOP1_BASE + 0x0B)
242 #define REG_DVI_DTOP1_0B_L        (REG_DVI_DTOP1_BASE + 0x16)
243 #define REG_DVI_DTOP1_0B_H        (REG_DVI_DTOP1_BASE + 0x17)
244 #define REG_DVI_DTOP1_0E_L        (REG_DVI_DTOP1_BASE + 0x1C)
245 #define REG_DVI_DTOP1_0E_H        (REG_DVI_DTOP1_BASE + 0x1D)
246 #define REG_DVI_DTOP1_16_L        (REG_DVI_DTOP1_BASE + 0x2C)
247 #define REG_DVI_DTOP1_16_H        (REG_DVI_DTOP1_BASE + 0x2D)
248 #define REG_DVI_DTOP1_17_L        (REG_DVI_DTOP1_BASE + 0x2E)
249 #define REG_DVI_DTOP1_17_H        (REG_DVI_DTOP1_BASE + 0x2F)
250 #define REG_DVI_DTOP1_19_L        (REG_DVI_DTOP1_BASE + 0x32)
251 #define REG_DVI_DTOP1_19_H        (REG_DVI_DTOP1_BASE + 0x33)
252 #define REG_DVI_DTOP1_1E_L        (REG_DVI_DTOP1_BASE + 0x3C)
253 #define REG_DVI_DTOP1_1E_H        (REG_DVI_DTOP1_BASE + 0x3D)
254 #define REG_DVI_DTOP1_21_L        (REG_DVI_DTOP1_BASE + 0x42)
255 #define REG_DVI_DTOP1_21_H        (REG_DVI_DTOP1_BASE + 0x43)
256 #define REG_DVI_DTOP1_23_L        (REG_DVI_DTOP1_BASE + 0x46)
257 #define REG_DVI_DTOP1_24_L        (REG_DVI_DTOP1_BASE + 0x48)
258 #define REG_DVI_DTOP1_24_H        (REG_DVI_DTOP1_BASE + 0x49)
259 #define REG_DVI_DTOP1_25_L        (REG_DVI_DTOP1_BASE + 0x4A)
260 #define REG_DVI_DTOP1_25_H        (REG_DVI_DTOP1_BASE + 0x4B)
261 #define REG_DVI_DTOP1_29_L        (REG_DVI_DTOP1_BASE + 0x52)
262 #define REG_DVI_DTOP1_29_H        (REG_DVI_DTOP1_BASE + 0x53)
263 #define REG_DVI_DTOP1_2A_L        (REG_DVI_DTOP1_BASE + 0x54)
264 #define REG_DVI_DTOP1_2A_H        (REG_DVI_DTOP1_BASE + 0x55)
265 #define REG_DVI_DTOP1_2F_L        (REG_DVI_DTOP1_BASE + 0x5E)
266 #define REG_DVI_DTOP1_2F_H        (REG_DVI_DTOP1_BASE + 0x5F)
267 #define REG_DVI_DTOP1_30_L        (REG_DVI_DTOP1_BASE + 0x60)
268 #define REG_DVI_DTOP1_30_H        (REG_DVI_DTOP1_BASE + 0x61)
269 #define REG_DVI_DTOP1_31_L        (REG_DVI_DTOP1_BASE + 0x62)
270 #define REG_DVI_DTOP1_31_H        (REG_DVI_DTOP1_BASE + 0x63)
271 
272 // DVI DTOP2
273 #define REG_DVI_DTOP2_00_L        (REG_DVI_DTOP2_BASE + 0x00)
274 #define REG_DVI_DTOP2_00_H        (REG_DVI_DTOP2_BASE + 0x01)
275 #define REG_DVI_DTOP2_01_L        (REG_DVI_DTOP2_BASE + 0x02)
276 #define REG_DVI_DTOP2_01_H        (REG_DVI_DTOP2_BASE + 0x03)
277 #define REG_DVI_DTOP2_02_L        (REG_DVI_DTOP2_BASE + 0x04)
278 #define REG_DVI_DTOP2_02_H        (REG_DVI_DTOP2_BASE + 0x05)
279 #define REG_DVI_DTOP2_03_L        (REG_DVI_DTOP2_BASE + 0x06)
280 #define REG_DVI_DTOP2_03_H        (REG_DVI_DTOP2_BASE + 0x07)
281 #define REG_DVI_DTOP2_05_L        (REG_DVI_DTOP2_BASE + 0x0A)
282 #define REG_DVI_DTOP2_05_H        (REG_DVI_DTOP2_BASE + 0x0B)
283 #define REG_DVI_DTOP2_0B_L        (REG_DVI_DTOP2_BASE + 0x16)
284 #define REG_DVI_DTOP2_0B_H        (REG_DVI_DTOP2_BASE + 0x17)
285 #define REG_DVI_DTOP2_0E_L        (REG_DVI_DTOP2_BASE + 0x1C)
286 #define REG_DVI_DTOP2_0E_H        (REG_DVI_DTOP2_BASE + 0x1D)
287 #define REG_DVI_DTOP2_16_L        (REG_DVI_DTOP2_BASE + 0x2C)
288 #define REG_DVI_DTOP2_16_H        (REG_DVI_DTOP2_BASE + 0x2D)
289 #define REG_DVI_DTOP2_17_L        (REG_DVI_DTOP2_BASE + 0x2E)
290 #define REG_DVI_DTOP2_17_H        (REG_DVI_DTOP2_BASE + 0x2F)
291 #define REG_DVI_DTOP2_19_L        (REG_DVI_DTOP2_BASE + 0x32)
292 #define REG_DVI_DTOP2_19_H        (REG_DVI_DTOP2_BASE + 0x33)
293 #define REG_DVI_DTOP2_20_L        (REG_DVI_DTOP2_BASE + 0x40)
294 #define REG_DVI_DTOP2_20_H        (REG_DVI_DTOP2_BASE + 0x41)
295 #define REG_DVI_DTOP2_1E_L        (REG_DVI_DTOP2_BASE + 0x3C)
296 #define REG_DVI_DTOP2_1E_H        (REG_DVI_DTOP2_BASE + 0x3D)
297 #define REG_DVI_DTOP2_1F_L        (REG_DVI_DTOP2_BASE + 0x3E)
298 #define REG_DVI_DTOP2_1F_H        (REG_DVI_DTOP2_BASE + 0x3F)
299 #define REG_DVI_DTOP2_20_L        (REG_DVI_DTOP2_BASE + 0x40)
300 #define REG_DVI_DTOP2_20_H        (REG_DVI_DTOP2_BASE + 0x41)
301 #define REG_DVI_DTOP2_21_L        (REG_DVI_DTOP2_BASE + 0x42)
302 #define REG_DVI_DTOP2_21_H        (REG_DVI_DTOP2_BASE + 0x43)
303 #define REG_DVI_DTOP2_23_L        (REG_DVI_DTOP2_BASE + 0x46)
304 #define REG_DVI_DTOP2_24_L        (REG_DVI_DTOP2_BASE + 0x48)
305 #define REG_DVI_DTOP2_24_H        (REG_DVI_DTOP2_BASE + 0x49)
306 #define REG_DVI_DTOP2_25_L        (REG_DVI_DTOP2_BASE + 0x4A)
307 #define REG_DVI_DTOP2_25_H        (REG_DVI_DTOP2_BASE + 0x4B)
308 #define REG_DVI_DTOP2_27_L        (REG_DVI_DTOP2_BASE + 0x4E)
309 #define REG_DVI_DTOP2_27_H        (REG_DVI_DTOP2_BASE + 0x4F)
310 #define REG_DVI_DTOP2_28_L        (REG_DVI_DTOP2_BASE + 0x50)
311 #define REG_DVI_DTOP2_28_H        (REG_DVI_DTOP2_BASE + 0x51)
312 #define REG_DVI_DTOP2_29_L        (REG_DVI_DTOP2_BASE + 0x52)
313 #define REG_DVI_DTOP2_29_H        (REG_DVI_DTOP2_BASE + 0x53)
314 #define REG_DVI_DTOP2_2A_L        (REG_DVI_DTOP2_BASE + 0x54)
315 #define REG_DVI_DTOP2_2A_H        (REG_DVI_DTOP2_BASE + 0x55)
316 #define REG_DVI_DTOP2_2E_L        (REG_DVI_DTOP2_BASE + 0x5C)
317 #define REG_DVI_DTOP2_2E_H        (REG_DVI_DTOP2_BASE + 0x5D)
318 #define REG_DVI_DTOP2_2F_L        (REG_DVI_DTOP2_BASE + 0x5E)
319 #define REG_DVI_DTOP2_2F_H        (REG_DVI_DTOP2_BASE + 0x5F)
320 #define REG_DVI_DTOP2_30_L        (REG_DVI_DTOP2_BASE + 0x60)
321 #define REG_DVI_DTOP2_30_H        (REG_DVI_DTOP2_BASE + 0x61)
322 #define REG_DVI_DTOP2_31_L        (REG_DVI_DTOP2_BASE + 0x62)
323 #define REG_DVI_DTOP2_31_H        (REG_DVI_DTOP2_BASE + 0x63)
324 #define REG_DVI_DTOP2_37_L        (REG_DVI_DTOP2_BASE + 0x6E)
325 #define REG_DVI_DTOP2_3A_L        (REG_DVI_DTOP2_BASE + 0x74)
326 #define REG_DVI_DTOP2_3A_H        (REG_DVI_DTOP2_BASE + 0x75)
327 #define REG_DVI_DTOP2_3B_L        (REG_DVI_DTOP2_BASE + 0x76)
328 #define REG_DVI_DTOP2_3B_H        (REG_DVI_DTOP2_BASE + 0x77)
329 #define REG_DVI_DTOP2_3C_L        (REG_DVI_DTOP2_BASE + 0x78)
330 #define REG_DVI_DTOP2_3C_H        (REG_DVI_DTOP2_BASE + 0x79)
331 #define REG_DVI_DTOP2_3D_L        (REG_DVI_DTOP2_BASE + 0x7A)
332 #define REG_DVI_DTOP2_3D_H        (REG_DVI_DTOP2_BASE + 0x7B)
333 #define REG_DVI_DTOP2_3E_L        (REG_DVI_DTOP2_BASE + 0x7C)
334 #define REG_DVI_DTOP2_3E_H        (REG_DVI_DTOP2_BASE + 0x7D)
335 #define REG_DVI_DTOP2_3F_L        (REG_DVI_DTOP2_BASE + 0x7E)
336 #define REG_DVI_DTOP2_3F_H        (REG_DVI_DTOP2_BASE + 0x7F)
337 
338 // DVI DTOP3
339 #define REG_DVI_DTOP3_00_L        (REG_DVI_DTOP3_BASE + 0x00)
340 #define REG_DVI_DTOP3_00_H        (REG_DVI_DTOP3_BASE + 0x01)
341 #define REG_DVI_DTOP3_01_L        (REG_DVI_DTOP3_BASE + 0x02)
342 #define REG_DVI_DTOP3_01_H        (REG_DVI_DTOP3_BASE + 0x03)
343 #define REG_DVI_DTOP3_02_L        (REG_DVI_DTOP3_BASE + 0x04)
344 #define REG_DVI_DTOP3_02_H        (REG_DVI_DTOP3_BASE + 0x05)
345 #define REG_DVI_DTOP3_03_L        (REG_DVI_DTOP3_BASE + 0x06)
346 #define REG_DVI_DTOP3_03_H        (REG_DVI_DTOP3_BASE + 0x07)
347 #define REG_DVI_DTOP3_04_L        (REG_DVI_DTOP3_BASE + 0x08)
348 #define REG_DVI_DTOP3_04_H        (REG_DVI_DTOP3_BASE + 0x09)
349 #define REG_DVI_DTOP3_05_L        (REG_DVI_DTOP3_BASE + 0x0A)
350 #define REG_DVI_DTOP3_05_H        (REG_DVI_DTOP3_BASE + 0x0B)
351 #define REG_DVI_DTOP3_0B_L        (REG_DVI_DTOP3_BASE + 0x16)
352 #define REG_DVI_DTOP3_0B_H        (REG_DVI_DTOP3_BASE + 0x17)
353 #define REG_DVI_DTOP3_0C_L        (REG_DVI_DTOP3_BASE + 0x18)
354 #define REG_DVI_DTOP3_0C_H        (REG_DVI_DTOP3_BASE + 0x19)
355 #define REG_DVI_DTOP3_0E_L        (REG_DVI_DTOP3_BASE + 0x1C)
356 #define REG_DVI_DTOP3_0E_H        (REG_DVI_DTOP3_BASE + 0x1D)
357 #define REG_DVI_DTOP3_16_L        (REG_DVI_DTOP3_BASE + 0x2C)
358 #define REG_DVI_DTOP3_16_H        (REG_DVI_DTOP3_BASE + 0x2D)
359 #define REG_DVI_DTOP3_17_L        (REG_DVI_DTOP3_BASE + 0x2E)
360 #define REG_DVI_DTOP3_17_H        (REG_DVI_DTOP3_BASE + 0x2F)
361 #define REG_DVI_DTOP3_19_L        (REG_DVI_DTOP3_BASE + 0x32)
362 #define REG_DVI_DTOP3_19_H        (REG_DVI_DTOP3_BASE + 0x33)
363 #define REG_DVI_DTOP3_1E_L        (REG_DVI_DTOP3_BASE + 0x3C)
364 #define REG_DVI_DTOP3_1E_H        (REG_DVI_DTOP3_BASE + 0x3D)
365 #define REG_DVI_DTOP3_1F_L        (REG_DVI_DTOP3_BASE + 0x3E)
366 #define REG_DVI_DTOP3_1F_H        (REG_DVI_DTOP3_BASE + 0x3F)
367 #define REG_DVI_DTOP3_20_L        (REG_DVI_DTOP3_BASE + 0x40)
368 #define REG_DVI_DTOP3_21_L        (REG_DVI_DTOP3_BASE + 0x42)
369 #define REG_DVI_DTOP3_21_H        (REG_DVI_DTOP3_BASE + 0x43)
370 #define REG_DVI_DTOP3_23_L        (REG_DVI_DTOP3_BASE + 0x46)
371 #define REG_DVI_DTOP3_23_H        (REG_DVI_DTOP3_BASE + 0x47)
372 #define REG_DVI_DTOP3_24_L        (REG_DVI_DTOP3_BASE + 0x48)
373 #define REG_DVI_DTOP3_24_H        (REG_DVI_DTOP3_BASE + 0x49)
374 #define REG_DVI_DTOP3_25_L        (REG_DVI_DTOP3_BASE + 0x4A)
375 #define REG_DVI_DTOP3_25_H        (REG_DVI_DTOP3_BASE + 0x4B)
376 #define REG_DVI_DTOP3_27_L        (REG_DVI_DTOP3_BASE + 0x4E)
377 #define REG_DVI_DTOP3_27_H        (REG_DVI_DTOP3_BASE + 0x4F)
378 #define REG_DVI_DTOP3_28_L        (REG_DVI_DTOP3_BASE + 0x50)
379 #define REG_DVI_DTOP3_28_H        (REG_DVI_DTOP3_BASE + 0x51)
380 #define REG_DVI_DTOP3_29_L        (REG_DVI_DTOP3_BASE + 0x52)
381 #define REG_DVI_DTOP3_29_H        (REG_DVI_DTOP3_BASE + 0x53)
382 #define REG_DVI_DTOP3_2A_L        (REG_DVI_DTOP3_BASE + 0x54)
383 #define REG_DVI_DTOP3_2A_H        (REG_DVI_DTOP3_BASE + 0x55)
384 #define REG_DVI_DTOP3_2E_L        (REG_DVI_DTOP3_BASE + 0x5C)
385 #define REG_DVI_DTOP3_2E_H        (REG_DVI_DTOP3_BASE + 0x5D)
386 #define REG_DVI_DTOP3_2F_L        (REG_DVI_DTOP3_BASE + 0x5E)
387 #define REG_DVI_DTOP3_2F_H        (REG_DVI_DTOP3_BASE + 0x5F)
388 #define REG_DVI_DTOP3_30_L        (REG_DVI_DTOP3_BASE + 0x60)
389 #define REG_DVI_DTOP3_30_H        (REG_DVI_DTOP3_BASE + 0x61)
390 #define REG_DVI_DTOP3_31_L        (REG_DVI_DTOP3_BASE + 0x62)
391 #define REG_DVI_DTOP3_31_H        (REG_DVI_DTOP3_BASE + 0x63)
392 #define REG_DVI_DTOP3_37_L        (REG_DVI_DTOP3_BASE + 0x6E)
393 #define REG_DVI_DTOP3_37_H        (REG_DVI_DTOP3_BASE + 0x6F)
394 #define REG_DVI_DTOP3_3A_L        (REG_DVI_DTOP3_BASE + 0x74)
395 #define REG_DVI_DTOP3_3B_L        (REG_DVI_DTOP3_BASE + 0x76)
396 #define REG_DVI_DTOP3_3C_L        (REG_DVI_DTOP3_BASE + 0x78)
397 #define REG_DVI_DTOP3_3D_L        (REG_DVI_DTOP3_BASE + 0x7A)
398 #define REG_DVI_DTOP3_3E_L        (REG_DVI_DTOP3_BASE + 0x7C)
399 #define REG_DVI_DTOP3_3E_H        (REG_DVI_DTOP3_BASE + 0x7D)
400 #define REG_DVI_DTOP3_3F_L        (REG_DVI_DTOP3_BASE + 0x7E)
401 
402 
403 //=============================================================
404 // DVI EQ
405 
406 #define REG_DVI_EQ_00_L        (REG_DVI_EQ_BASE + 0x00)
407 #define REG_DVI_EQ_00_H        (REG_DVI_EQ_BASE + 0x01)
408 #define REG_DVI_EQ_01_L        (REG_DVI_EQ_BASE + 0x02)
409 #define REG_DVI_EQ_01_H        (REG_DVI_EQ_BASE + 0x03)
410 #define REG_DVI_EQ_02_L        (REG_DVI_EQ_BASE + 0x04)
411 #define REG_DVI_EQ_02_H        (REG_DVI_EQ_BASE + 0x05)
412 #define REG_DVI_EQ_03_L        (REG_DVI_EQ_BASE + 0x06)
413 #define REG_DVI_EQ_03_H        (REG_DVI_EQ_BASE + 0x07)
414 #define REG_DVI_EQ_04_L        (REG_DVI_EQ_BASE + 0x08)
415 #define REG_DVI_EQ_04_H        (REG_DVI_EQ_BASE + 0x09)
416 #define REG_DVI_EQ_05_L        (REG_DVI_EQ_BASE + 0x0A)
417 #define REG_DVI_EQ_05_H        (REG_DVI_EQ_BASE + 0x0B)
418 #define REG_DVI_EQ_06_L        (REG_DVI_EQ_BASE + 0x0C)
419 #define REG_DVI_EQ_06_H        (REG_DVI_EQ_BASE + 0x0D)
420 #define REG_DVI_EQ_07_L        (REG_DVI_EQ_BASE + 0x0E)
421 #define REG_DVI_EQ_07_H        (REG_DVI_EQ_BASE + 0x0F)
422 #define REG_DVI_EQ_08_L        (REG_DVI_EQ_BASE + 0x10)
423 #define REG_DVI_EQ_08_H        (REG_DVI_EQ_BASE + 0x11)
424 #define REG_DVI_EQ_09_L        (REG_DVI_EQ_BASE + 0x12)
425 #define REG_DVI_EQ_09_H        (REG_DVI_EQ_BASE + 0x13)
426 #define REG_DVI_EQ_0A_L        (REG_DVI_EQ_BASE + 0x14)
427 #define REG_DVI_EQ_0A_H        (REG_DVI_EQ_BASE + 0x15)
428 #define REG_DVI_EQ_0B_L        (REG_DVI_EQ_BASE + 0x16)
429 #define REG_DVI_EQ_0B_H        (REG_DVI_EQ_BASE + 0x17)
430 #define REG_DVI_EQ_0C_L        (REG_DVI_EQ_BASE + 0x18)
431 #define REG_DVI_EQ_0C_H        (REG_DVI_EQ_BASE + 0x19)
432 #define REG_DVI_EQ_0D_L        (REG_DVI_EQ_BASE + 0x1A)
433 #define REG_DVI_EQ_0D_H        (REG_DVI_EQ_BASE + 0x1B)
434 #define REG_DVI_EQ_0E_L        (REG_DVI_EQ_BASE + 0x1C)
435 #define REG_DVI_EQ_0E_H        (REG_DVI_EQ_BASE + 0x1D)
436 #define REG_DVI_EQ_0F_L        (REG_DVI_EQ_BASE + 0x1E)
437 #define REG_DVI_EQ_0F_H        (REG_DVI_EQ_BASE + 0x1F)
438 #define REG_DVI_EQ_10_L        (REG_DVI_EQ_BASE + 0x20)
439 #define REG_DVI_EQ_10_H        (REG_DVI_EQ_BASE + 0x21)
440 #define REG_DVI_EQ_11_L        (REG_DVI_EQ_BASE + 0x22)
441 #define REG_DVI_EQ_11_H        (REG_DVI_EQ_BASE + 0x23)
442 #define REG_DVI_EQ_12_L        (REG_DVI_EQ_BASE + 0x24)
443 #define REG_DVI_EQ_12_H        (REG_DVI_EQ_BASE + 0x25)
444 #define REG_DVI_EQ_13_L        (REG_DVI_EQ_BASE + 0x26)
445 #define REG_DVI_EQ_13_H        (REG_DVI_EQ_BASE + 0x27)
446 #define REG_DVI_EQ_14_L        (REG_DVI_EQ_BASE + 0x28)
447 #define REG_DVI_EQ_14_H        (REG_DVI_EQ_BASE + 0x29)
448 #define REG_DVI_EQ_15_L        (REG_DVI_EQ_BASE + 0x2A)
449 #define REG_DVI_EQ_15_H        (REG_DVI_EQ_BASE + 0x2B)
450 #define REG_DVI_EQ_16_L        (REG_DVI_EQ_BASE + 0x2C)
451 #define REG_DVI_EQ_16_H        (REG_DVI_EQ_BASE + 0x2D)
452 #define REG_DVI_EQ_17_L        (REG_DVI_EQ_BASE + 0x2E)
453 #define REG_DVI_EQ_17_H        (REG_DVI_EQ_BASE + 0x2F)
454 #define REG_DVI_EQ_18_L        (REG_DVI_EQ_BASE + 0x30)
455 #define REG_DVI_EQ_18_H        (REG_DVI_EQ_BASE + 0x31)
456 #define REG_DVI_EQ_19_L        (REG_DVI_EQ_BASE + 0x32)
457 #define REG_DVI_EQ_19_H        (REG_DVI_EQ_BASE + 0x33)
458 #define REG_DVI_EQ_1A_L        (REG_DVI_EQ_BASE + 0x34)
459 #define REG_DVI_EQ_1A_H        (REG_DVI_EQ_BASE + 0x35)
460 #define REG_DVI_EQ_1B_L        (REG_DVI_EQ_BASE + 0x36)
461 #define REG_DVI_EQ_1B_H        (REG_DVI_EQ_BASE + 0x37)
462 #define REG_DVI_EQ_1C_L        (REG_DVI_EQ_BASE + 0x38)
463 #define REG_DVI_EQ_1C_H        (REG_DVI_EQ_BASE + 0x39)
464 #define REG_DVI_EQ_1D_L        (REG_DVI_EQ_BASE + 0x3A)
465 #define REG_DVI_EQ_1D_H        (REG_DVI_EQ_BASE + 0x3B)
466 #define REG_DVI_EQ_1E_L        (REG_DVI_EQ_BASE + 0x3C)
467 #define REG_DVI_EQ_1E_H        (REG_DVI_EQ_BASE + 0x3D)
468 #define REG_DVI_EQ_1F_L        (REG_DVI_EQ_BASE + 0x3E)
469 
470 // DVI EQ1
471 #define REG_DVI_EQ1_00_L        (REG_DVI_EQ1_BASE + 0x00)
472 #define REG_DVI_EQ1_00_H        (REG_DVI_EQ1_BASE + 0x01)
473 #define REG_DVI_EQ1_01_L        (REG_DVI_EQ1_BASE + 0x02)
474 #define REG_DVI_EQ1_01_H        (REG_DVI_EQ1_BASE + 0x03)
475 #define REG_DVI_EQ1_02_L        (REG_DVI_EQ1_BASE + 0x04)
476 #define REG_DVI_EQ1_02_H        (REG_DVI_EQ1_BASE + 0x05)
477 #define REG_DVI_EQ1_04_L        (REG_DVI_EQ1_BASE + 0x08)
478 #define REG_DVI_EQ1_04_H        (REG_DVI_EQ1_BASE + 0x09)
479 #define REG_DVI_EQ1_10_L        (REG_DVI_EQ1_BASE + 0x20)
480 #define REG_DVI_EQ1_10_H        (REG_DVI_EQ1_BASE + 0x21)
481 #define REG_DVI_EQ1_11_L        (REG_DVI_EQ1_BASE + 0x22)
482 #define REG_DVI_EQ1_11_H        (REG_DVI_EQ1_BASE + 0x23)
483 #define REG_DVI_EQ1_12_L        (REG_DVI_EQ1_BASE + 0x24)
484 #define REG_DVI_EQ1_12_H        (REG_DVI_EQ1_BASE + 0x25)
485 #define REG_DVI_EQ1_17_L        (REG_DVI_EQ1_BASE + 0x2E)
486 #define REG_DVI_EQ1_17_H        (REG_DVI_EQ1_BASE + 0x2F)
487 
488 // DVI EQ2
489 #define REG_DVI_EQ2_00_L        (REG_DVI_EQ2_BASE + 0x00)
490 #define REG_DVI_EQ2_00_H        (REG_DVI_EQ2_BASE + 0x01)
491 #define REG_DVI_EQ2_01_L        (REG_DVI_EQ2_BASE + 0x02)
492 #define REG_DVI_EQ2_01_H        (REG_DVI_EQ2_BASE + 0x03)
493 #define REG_DVI_EQ2_02_L        (REG_DVI_EQ2_BASE + 0x04)
494 #define REG_DVI_EQ2_02_H        (REG_DVI_EQ2_BASE + 0x05)
495 #define REG_DVI_EQ2_04_L        (REG_DVI_EQ2_BASE + 0x08)
496 #define REG_DVI_EQ2_04_H        (REG_DVI_EQ2_BASE + 0x09)
497 #define REG_DVI_EQ2_10_L        (REG_DVI_EQ2_BASE + 0x20)
498 #define REG_DVI_EQ2_10_H        (REG_DVI_EQ2_BASE + 0x21)
499 #define REG_DVI_EQ2_11_L        (REG_DVI_EQ2_BASE + 0x22)
500 #define REG_DVI_EQ2_11_H        (REG_DVI_EQ2_BASE + 0x23)
501 #define REG_DVI_EQ2_12_L        (REG_DVI_EQ2_BASE + 0x24)
502 #define REG_DVI_EQ2_12_H        (REG_DVI_EQ2_BASE + 0x25)
503 #define REG_DVI_EQ2_17_L        (REG_DVI_EQ2_BASE + 0x2E)
504 #define REG_DVI_EQ2_17_H        (REG_DVI_EQ2_BASE + 0x2F)
505 
506 // DVI EQ3
507 #define REG_DVI_EQ3_00_L        (REG_DVI_EQ3_BASE + 0x00)
508 #define REG_DVI_EQ3_00_H        (REG_DVI_EQ3_BASE + 0x01)
509 #define REG_DVI_EQ3_01_L        (REG_DVI_EQ3_BASE + 0x02)
510 #define REG_DVI_EQ3_01_H        (REG_DVI_EQ3_BASE + 0x03)
511 #define REG_DVI_EQ3_02_L        (REG_DVI_EQ3_BASE + 0x04)
512 #define REG_DVI_EQ3_02_H        (REG_DVI_EQ3_BASE + 0x05)
513 #define REG_DVI_EQ3_04_L        (REG_DVI_EQ3_BASE + 0x08)
514 #define REG_DVI_EQ3_04_H        (REG_DVI_EQ3_BASE + 0x09)
515 #define REG_DVI_EQ3_10_L        (REG_DVI_EQ3_BASE + 0x20)
516 #define REG_DVI_EQ3_10_H        (REG_DVI_EQ3_BASE + 0x21)
517 #define REG_DVI_EQ3_11_L        (REG_DVI_EQ3_BASE + 0x22)
518 #define REG_DVI_EQ3_11_H        (REG_DVI_EQ3_BASE + 0x23)
519 #define REG_DVI_EQ3_12_L        (REG_DVI_EQ3_BASE + 0x24)
520 #define REG_DVI_EQ3_12_H        (REG_DVI_EQ3_BASE + 0x25)
521 #define REG_DVI_EQ3_17_L        (REG_DVI_EQ3_BASE + 0x2E)
522 #define REG_DVI_EQ3_17_H        (REG_DVI_EQ3_BASE + 0x2F)
523 
524 //=============================================================
525 // DVI ATOP
526 
527 #define REG_DVI_ATOP_00_L        (REG_DVI_ATOP_BASE + 0x00)
528 #define REG_DVI_ATOP_00_H        (REG_DVI_ATOP_BASE + 0x01)
529 #define REG_DVI_ATOP_01_L        (REG_DVI_ATOP_BASE + 0x02)
530 #define REG_DVI_ATOP_01_H        (REG_DVI_ATOP_BASE + 0x03)
531 #define REG_DVI_ATOP_02_L        (REG_DVI_ATOP_BASE + 0x04)
532 #define REG_DVI_ATOP_02_H        (REG_DVI_ATOP_BASE + 0x05)
533 #define REG_DVI_ATOP_03_L        (REG_DVI_ATOP_BASE + 0x06)
534 #define REG_DVI_ATOP_03_H        (REG_DVI_ATOP_BASE + 0x07)
535 #define REG_DVI_ATOP_04_L        (REG_DVI_ATOP_BASE + 0x08)
536 #define REG_DVI_ATOP_04_H        (REG_DVI_ATOP_BASE + 0x09)
537 #define REG_DVI_ATOP_05_L        (REG_DVI_ATOP_BASE + 0x0A)
538 #define REG_DVI_ATOP_05_H        (REG_DVI_ATOP_BASE + 0x0B)
539 #define REG_DVI_ATOP_06_L        (REG_DVI_ATOP_BASE + 0x0C)
540 #define REG_DVI_ATOP_06_H        (REG_DVI_ATOP_BASE + 0x0D)
541 #define REG_DVI_ATOP_07_L        (REG_DVI_ATOP_BASE + 0x0E)
542 #define REG_DVI_ATOP_07_H        (REG_DVI_ATOP_BASE + 0x0F)
543 #define REG_DVI_ATOP_08_L        (REG_DVI_ATOP_BASE + 0x10)
544 #define REG_DVI_ATOP_08_H        (REG_DVI_ATOP_BASE + 0x11)
545 #define REG_DVI_ATOP_09_L        (REG_DVI_ATOP_BASE + 0x12)
546 #define REG_DVI_ATOP_09_H        (REG_DVI_ATOP_BASE + 0x13)
547 #define REG_DVI_ATOP_0A_L        (REG_DVI_ATOP_BASE + 0x14)
548 #define REG_DVI_ATOP_0A_H        (REG_DVI_ATOP_BASE + 0x15)
549 #define REG_DVI_ATOP_0B_L        (REG_DVI_ATOP_BASE + 0x16)
550 #define REG_DVI_ATOP_0B_H        (REG_DVI_ATOP_BASE + 0x17)
551 #define REG_DVI_ATOP_0C_L        (REG_DVI_ATOP_BASE + 0x18)
552 #define REG_DVI_ATOP_0C_H        (REG_DVI_ATOP_BASE + 0x19)
553 #define REG_DVI_ATOP_0D_L        (REG_DVI_ATOP_BASE + 0x1A)
554 #define REG_DVI_ATOP_0D_H        (REG_DVI_ATOP_BASE + 0x1B)
555 #define REG_DVI_ATOP_0E_L        (REG_DVI_ATOP_BASE + 0x1C)
556 #define REG_DVI_ATOP_0E_H        (REG_DVI_ATOP_BASE + 0x1D)
557 #define REG_DVI_ATOP_0F_L        (REG_DVI_ATOP_BASE + 0x1E)
558 #define REG_DVI_ATOP_0F_H        (REG_DVI_ATOP_BASE + 0x1F)
559 #define REG_DVI_ATOP_10_L        (REG_DVI_ATOP_BASE + 0x20)
560 #define REG_DVI_ATOP_10_H        (REG_DVI_ATOP_BASE + 0x21)
561 #define REG_DVI_ATOP_11_L        (REG_DVI_ATOP_BASE + 0x22)
562 #define REG_DVI_ATOP_11_H        (REG_DVI_ATOP_BASE + 0x23)
563 #define REG_DVI_ATOP_12_L        (REG_DVI_ATOP_BASE + 0x24)
564 #define REG_DVI_ATOP_12_H        (REG_DVI_ATOP_BASE + 0x25)
565 #define REG_DVI_ATOP_13_L        (REG_DVI_ATOP_BASE + 0x26)
566 #define REG_DVI_ATOP_13_H        (REG_DVI_ATOP_BASE + 0x27)
567 #define REG_DVI_ATOP_14_L        (REG_DVI_ATOP_BASE + 0x28)
568 #define REG_DVI_ATOP_14_H        (REG_DVI_ATOP_BASE + 0x29)
569 #define REG_DVI_ATOP_15_L        (REG_DVI_ATOP_BASE + 0x2A)
570 #define REG_DVI_ATOP_15_H        (REG_DVI_ATOP_BASE + 0x2B)
571 #define REG_DVI_ATOP_16_L        (REG_DVI_ATOP_BASE + 0x2C)
572 #define REG_DVI_ATOP_16_H        (REG_DVI_ATOP_BASE + 0x2D)
573 #define REG_DVI_ATOP_17_L        (REG_DVI_ATOP_BASE + 0x2E)
574 #define REG_DVI_ATOP_17_H        (REG_DVI_ATOP_BASE + 0x2F)
575 #define REG_DVI_ATOP_18_L        (REG_DVI_ATOP_BASE + 0x30)
576 #define REG_DVI_ATOP_18_H        (REG_DVI_ATOP_BASE + 0x31)
577 #define REG_DVI_ATOP_19_L        (REG_DVI_ATOP_BASE + 0x32)
578 #define REG_DVI_ATOP_19_H        (REG_DVI_ATOP_BASE + 0x33)
579 #define REG_DVI_ATOP_1A_L        (REG_DVI_ATOP_BASE + 0x34)
580 #define REG_DVI_ATOP_1A_H        (REG_DVI_ATOP_BASE + 0x35)
581 #define REG_DVI_ATOP_1B_L        (REG_DVI_ATOP_BASE + 0x36)
582 #define REG_DVI_ATOP_1B_H        (REG_DVI_ATOP_BASE + 0x37)
583 #define REG_DVI_ATOP_1C_L        (REG_DVI_ATOP_BASE + 0x38)
584 #define REG_DVI_ATOP_1C_H        (REG_DVI_ATOP_BASE + 0x39)
585 #define REG_DVI_ATOP_1D_L        (REG_DVI_ATOP_BASE + 0x3A)
586 #define REG_DVI_ATOP_1D_H        (REG_DVI_ATOP_BASE + 0x3B)
587 #define REG_DVI_ATOP_1E_L        (REG_DVI_ATOP_BASE + 0x3C)
588 #define REG_DVI_ATOP_1E_H        (REG_DVI_ATOP_BASE + 0x3D)
589 #define REG_DVI_ATOP_1F_L        (REG_DVI_ATOP_BASE + 0x3E)
590 #define REG_DVI_ATOP_1F_H        (REG_DVI_ATOP_BASE + 0x3F)
591 #define REG_DVI_ATOP_20_L        (REG_DVI_ATOP_BASE + 0x40)
592 #define REG_DVI_ATOP_20_H        (REG_DVI_ATOP_BASE + 0x41)
593 #define REG_DVI_ATOP_21_L        (REG_DVI_ATOP_BASE + 0x42)
594 #define REG_DVI_ATOP_21_H        (REG_DVI_ATOP_BASE + 0x43)
595 #define REG_DVI_ATOP_22_L        (REG_DVI_ATOP_BASE + 0x44)
596 #define REG_DVI_ATOP_22_H        (REG_DVI_ATOP_BASE + 0x45)
597 #define REG_DVI_ATOP_23_L        (REG_DVI_ATOP_BASE + 0x46)
598 #define REG_DVI_ATOP_23_H        (REG_DVI_ATOP_BASE + 0x47)
599 #define REG_DVI_ATOP_24_L        (REG_DVI_ATOP_BASE + 0x48)
600 #define REG_DVI_ATOP_24_H        (REG_DVI_ATOP_BASE + 0x49)
601 #define REG_DVI_ATOP_25_L        (REG_DVI_ATOP_BASE + 0x4A)
602 #define REG_DVI_ATOP_25_H        (REG_DVI_ATOP_BASE + 0x4B)
603 #define REG_DVI_ATOP_26_L        (REG_DVI_ATOP_BASE + 0x4C)
604 #define REG_DVI_ATOP_26_H        (REG_DVI_ATOP_BASE + 0x4D)
605 #define REG_DVI_ATOP_27_L        (REG_DVI_ATOP_BASE + 0x4E)
606 #define REG_DVI_ATOP_27_H        (REG_DVI_ATOP_BASE + 0x4F)
607 #define REG_DVI_ATOP_28_L        (REG_DVI_ATOP_BASE + 0x50)
608 #define REG_DVI_ATOP_28_H        (REG_DVI_ATOP_BASE + 0x51)
609 #define REG_DVI_ATOP_29_L        (REG_DVI_ATOP_BASE + 0x52)
610 #define REG_DVI_ATOP_29_H        (REG_DVI_ATOP_BASE + 0x53)
611 #define REG_DVI_ATOP_2A_L        (REG_DVI_ATOP_BASE + 0x54)
612 #define REG_DVI_ATOP_2A_H        (REG_DVI_ATOP_BASE + 0x55)
613 #define REG_DVI_ATOP_2B_L        (REG_DVI_ATOP_BASE + 0x56)
614 #define REG_DVI_ATOP_2B_H        (REG_DVI_ATOP_BASE + 0x57)
615 #define REG_DVI_ATOP_2C_L        (REG_DVI_ATOP_BASE + 0x58)
616 #define REG_DVI_ATOP_2C_H        (REG_DVI_ATOP_BASE + 0x59)
617 #define REG_DVI_ATOP_2D_L        (REG_DVI_ATOP_BASE + 0x5A)
618 #define REG_DVI_ATOP_2D_H        (REG_DVI_ATOP_BASE + 0x5B)
619 #define REG_DVI_ATOP_2E_L        (REG_DVI_ATOP_BASE + 0x5C)
620 #define REG_DVI_ATOP_2E_H        (REG_DVI_ATOP_BASE + 0x5D)
621 #define REG_DVI_ATOP_2F_L        (REG_DVI_ATOP_BASE + 0x5E)
622 #define REG_DVI_ATOP_2F_H        (REG_DVI_ATOP_BASE + 0x5F)
623 #define REG_DVI_ATOP_30_L        (REG_DVI_ATOP_BASE + 0x60)
624 #define REG_DVI_ATOP_30_H        (REG_DVI_ATOP_BASE + 0x61)
625 #define REG_DVI_ATOP_31_L        (REG_DVI_ATOP_BASE + 0x62)
626 #define REG_DVI_ATOP_31_H        (REG_DVI_ATOP_BASE + 0x63)
627 #define REG_DVI_ATOP_32_L        (REG_DVI_ATOP_BASE + 0x64)
628 #define REG_DVI_ATOP_32_H        (REG_DVI_ATOP_BASE + 0x65)
629 #define REG_DVI_ATOP_33_L        (REG_DVI_ATOP_BASE + 0x66)
630 #define REG_DVI_ATOP_33_H        (REG_DVI_ATOP_BASE + 0x67)
631 #define REG_DVI_ATOP_34_L        (REG_DVI_ATOP_BASE + 0x68)
632 #define REG_DVI_ATOP_34_H        (REG_DVI_ATOP_BASE + 0x69)
633 #define REG_DVI_ATOP_35_L        (REG_DVI_ATOP_BASE + 0x6A)
634 #define REG_DVI_ATOP_35_H        (REG_DVI_ATOP_BASE + 0x6B)
635 #define REG_DVI_ATOP_36_L        (REG_DVI_ATOP_BASE + 0x6C)
636 #define REG_DVI_ATOP_36_H        (REG_DVI_ATOP_BASE + 0x6D)
637 #define REG_DVI_ATOP_37_L        (REG_DVI_ATOP_BASE + 0x6E)
638 #define REG_DVI_ATOP_37_H        (REG_DVI_ATOP_BASE + 0x6F)
639 #define REG_DVI_ATOP_38_L        (REG_DVI_ATOP_BASE + 0x70)
640 #define REG_DVI_ATOP_38_H        (REG_DVI_ATOP_BASE + 0x71)
641 #define REG_DVI_ATOP_39_L        (REG_DVI_ATOP_BASE + 0x72)
642 #define REG_DVI_ATOP_39_H        (REG_DVI_ATOP_BASE + 0x73)
643 #define REG_DVI_ATOP_3A_L        (REG_DVI_ATOP_BASE + 0x74)
644 #define REG_DVI_ATOP_3A_H        (REG_DVI_ATOP_BASE + 0x75)
645 #define REG_DVI_ATOP_3B_L        (REG_DVI_ATOP_BASE + 0x76)
646 #define REG_DVI_ATOP_3B_H        (REG_DVI_ATOP_BASE + 0x77)
647 #define REG_DVI_ATOP_3C_L        (REG_DVI_ATOP_BASE + 0x78)
648 #define REG_DVI_ATOP_3C_H        (REG_DVI_ATOP_BASE + 0x79)
649 #define REG_DVI_ATOP_3D_L        (REG_DVI_ATOP_BASE + 0x7A)
650 #define REG_DVI_ATOP_3D_H        (REG_DVI_ATOP_BASE + 0x7B)
651 #define REG_DVI_ATOP_3E_L        (REG_DVI_ATOP_BASE + 0x7C)
652 #define REG_DVI_ATOP_3E_H        (REG_DVI_ATOP_BASE + 0x7D)
653 #define REG_DVI_ATOP_3F_L        (REG_DVI_ATOP_BASE + 0x7E)
654 #define REG_DVI_ATOP_3F_H        (REG_DVI_ATOP_BASE + 0x7F)
655 #define REG_DVI_ATOP_40_L        (REG_DVI_ATOP_BASE + 0x80)
656 #define REG_DVI_ATOP_40_H        (REG_DVI_ATOP_BASE + 0x81)
657 #define REG_DVI_ATOP_41_L        (REG_DVI_ATOP_BASE + 0x82)
658 #define REG_DVI_ATOP_41_H        (REG_DVI_ATOP_BASE + 0x83)
659 #define REG_DVI_ATOP_42_L        (REG_DVI_ATOP_BASE + 0x84)
660 #define REG_DVI_ATOP_42_H        (REG_DVI_ATOP_BASE + 0x85)
661 #define REG_DVI_ATOP_43_L        (REG_DVI_ATOP_BASE + 0x86)
662 #define REG_DVI_ATOP_43_H        (REG_DVI_ATOP_BASE + 0x87)
663 #define REG_DVI_ATOP_44_L        (REG_DVI_ATOP_BASE + 0x88)
664 #define REG_DVI_ATOP_44_H        (REG_DVI_ATOP_BASE + 0x89)
665 #define REG_DVI_ATOP_45_L        (REG_DVI_ATOP_BASE + 0x8A)
666 #define REG_DVI_ATOP_45_H        (REG_DVI_ATOP_BASE + 0x8B)
667 #define REG_DVI_ATOP_46_L        (REG_DVI_ATOP_BASE + 0x8C)
668 #define REG_DVI_ATOP_46_H        (REG_DVI_ATOP_BASE + 0x8D)
669 #define REG_DVI_ATOP_47_L        (REG_DVI_ATOP_BASE + 0x8E)
670 #define REG_DVI_ATOP_47_H        (REG_DVI_ATOP_BASE + 0x8F)
671 #define REG_DVI_ATOP_48_L        (REG_DVI_ATOP_BASE + 0x90)
672 #define REG_DVI_ATOP_48_H        (REG_DVI_ATOP_BASE + 0x91)
673 #define REG_DVI_ATOP_49_L        (REG_DVI_ATOP_BASE + 0x92)
674 #define REG_DVI_ATOP_49_H        (REG_DVI_ATOP_BASE + 0x93)
675 #define REG_DVI_ATOP_4A_L        (REG_DVI_ATOP_BASE + 0x94)
676 #define REG_DVI_ATOP_4A_H        (REG_DVI_ATOP_BASE + 0x95)
677 #define REG_DVI_ATOP_4B_L        (REG_DVI_ATOP_BASE + 0x96)
678 #define REG_DVI_ATOP_4B_H        (REG_DVI_ATOP_BASE + 0x97)
679 #define REG_DVI_ATOP_4C_L        (REG_DVI_ATOP_BASE + 0x98)
680 #define REG_DVI_ATOP_4C_H        (REG_DVI_ATOP_BASE + 0x99)
681 #define REG_DVI_ATOP_4D_L        (REG_DVI_ATOP_BASE + 0x9A)
682 #define REG_DVI_ATOP_4D_H        (REG_DVI_ATOP_BASE + 0x9B)
683 #define REG_DVI_ATOP_4E_L        (REG_DVI_ATOP_BASE + 0x9C)
684 #define REG_DVI_ATOP_4E_H        (REG_DVI_ATOP_BASE + 0x9D)
685 #define REG_DVI_ATOP_4F_L        (REG_DVI_ATOP_BASE + 0x9E)
686 #define REG_DVI_ATOP_4F_H        (REG_DVI_ATOP_BASE + 0x9F)
687 #define REG_DVI_ATOP_50_L        (REG_DVI_ATOP_BASE + 0xA0)
688 #define REG_DVI_ATOP_50_H        (REG_DVI_ATOP_BASE + 0xA1)
689 #define REG_DVI_ATOP_51_L        (REG_DVI_ATOP_BASE + 0xA2)
690 #define REG_DVI_ATOP_51_H        (REG_DVI_ATOP_BASE + 0xA3)
691 #define REG_DVI_ATOP_52_L        (REG_DVI_ATOP_BASE + 0xA4)
692 #define REG_DVI_ATOP_52_H        (REG_DVI_ATOP_BASE + 0xA5)
693 #define REG_DVI_ATOP_53_L        (REG_DVI_ATOP_BASE + 0xA6)
694 #define REG_DVI_ATOP_53_H        (REG_DVI_ATOP_BASE + 0xA7)
695 #define REG_DVI_ATOP_54_L        (REG_DVI_ATOP_BASE + 0xA8)
696 #define REG_DVI_ATOP_54_H        (REG_DVI_ATOP_BASE + 0xA9)
697 #define REG_DVI_ATOP_55_L        (REG_DVI_ATOP_BASE + 0xAA)
698 #define REG_DVI_ATOP_55_H        (REG_DVI_ATOP_BASE + 0xAB)
699 #define REG_DVI_ATOP_56_L        (REG_DVI_ATOP_BASE + 0xAC)
700 #define REG_DVI_ATOP_56_H        (REG_DVI_ATOP_BASE + 0xAD)
701 #define REG_DVI_ATOP_57_L        (REG_DVI_ATOP_BASE + 0xAE)
702 #define REG_DVI_ATOP_57_H        (REG_DVI_ATOP_BASE + 0xAF)
703 #define REG_DVI_ATOP_58_L        (REG_DVI_ATOP_BASE + 0xB0)
704 #define REG_DVI_ATOP_58_H        (REG_DVI_ATOP_BASE + 0xB1)
705 #define REG_DVI_ATOP_59_L        (REG_DVI_ATOP_BASE + 0xB2)
706 #define REG_DVI_ATOP_59_H        (REG_DVI_ATOP_BASE + 0xB3)
707 #define REG_DVI_ATOP_5A_L        (REG_DVI_ATOP_BASE + 0xB4)
708 #define REG_DVI_ATOP_5A_H        (REG_DVI_ATOP_BASE + 0xB5)
709 #define REG_DVI_ATOP_5B_L        (REG_DVI_ATOP_BASE + 0xB6)
710 #define REG_DVI_ATOP_5B_H        (REG_DVI_ATOP_BASE + 0xB7)
711 #define REG_DVI_ATOP_5C_L        (REG_DVI_ATOP_BASE + 0xB8)
712 #define REG_DVI_ATOP_5C_H        (REG_DVI_ATOP_BASE + 0xB9)
713 #define REG_DVI_ATOP_5D_L        (REG_DVI_ATOP_BASE + 0xBA)
714 #define REG_DVI_ATOP_5D_H        (REG_DVI_ATOP_BASE + 0xBB)
715 #define REG_DVI_ATOP_5E_L        (REG_DVI_ATOP_BASE + 0xBC)
716 #define REG_DVI_ATOP_5E_H        (REG_DVI_ATOP_BASE + 0xBD)
717 #define REG_DVI_ATOP_5F_L        (REG_DVI_ATOP_BASE + 0xBE)
718 #define REG_DVI_ATOP_5F_H        (REG_DVI_ATOP_BASE + 0xBF)
719 #define REG_DVI_ATOP_60_L        (REG_DVI_ATOP_BASE + 0xC0)
720 #define REG_DVI_ATOP_60_H        (REG_DVI_ATOP_BASE + 0xC1)
721 #define REG_DVI_ATOP_61_L        (REG_DVI_ATOP_BASE + 0xC2)
722 #define REG_DVI_ATOP_61_H        (REG_DVI_ATOP_BASE + 0xC3)
723 #define REG_DVI_ATOP_62_L        (REG_DVI_ATOP_BASE + 0xC4)
724 #define REG_DVI_ATOP_62_H        (REG_DVI_ATOP_BASE + 0xC5)
725 #define REG_DVI_ATOP_63_L        (REG_DVI_ATOP_BASE + 0xC6)
726 #define REG_DVI_ATOP_63_H        (REG_DVI_ATOP_BASE + 0xC7)
727 #define REG_DVI_ATOP_64_L        (REG_DVI_ATOP_BASE + 0xC8)
728 #define REG_DVI_ATOP_64_H        (REG_DVI_ATOP_BASE + 0xC9)
729 #define REG_DVI_ATOP_65_L        (REG_DVI_ATOP_BASE + 0xCA)
730 #define REG_DVI_ATOP_65_H        (REG_DVI_ATOP_BASE + 0xCB)
731 #define REG_DVI_ATOP_66_L        (REG_DVI_ATOP_BASE + 0xCC)
732 #define REG_DVI_ATOP_66_H        (REG_DVI_ATOP_BASE + 0xCD)
733 #define REG_DVI_ATOP_67_L        (REG_DVI_ATOP_BASE + 0xCE)
734 #define REG_DVI_ATOP_67_H        (REG_DVI_ATOP_BASE + 0xCF)
735 #define REG_DVI_ATOP_68_L        (REG_DVI_ATOP_BASE + 0xD0)
736 #define REG_DVI_ATOP_68_H        (REG_DVI_ATOP_BASE + 0xD1)
737 #define REG_DVI_ATOP_69_L        (REG_DVI_ATOP_BASE + 0xD2)
738 #define REG_DVI_ATOP_69_H        (REG_DVI_ATOP_BASE + 0xD3)
739 #define REG_DVI_ATOP_6A_L        (REG_DVI_ATOP_BASE + 0xD4)
740 #define REG_DVI_ATOP_6A_H        (REG_DVI_ATOP_BASE + 0xD5)
741 #define REG_DVI_ATOP_6B_L        (REG_DVI_ATOP_BASE + 0xD6)
742 #define REG_DVI_ATOP_6B_H        (REG_DVI_ATOP_BASE + 0xD7)
743 #define REG_DVI_ATOP_6C_L        (REG_DVI_ATOP_BASE + 0xD8)
744 #define REG_DVI_ATOP_6C_H        (REG_DVI_ATOP_BASE + 0xD9)
745 #define REG_DVI_ATOP_6D_L        (REG_DVI_ATOP_BASE + 0xDA)
746 #define REG_DVI_ATOP_6D_H        (REG_DVI_ATOP_BASE + 0xDB)
747 #define REG_DVI_ATOP_6E_L        (REG_DVI_ATOP_BASE + 0xDC)
748 #define REG_DVI_ATOP_6E_H        (REG_DVI_ATOP_BASE + 0xDD)
749 #define REG_DVI_ATOP_6F_L        (REG_DVI_ATOP_BASE + 0xDE)
750 #define REG_DVI_ATOP_6F_H        (REG_DVI_ATOP_BASE + 0xDF)
751 #define REG_DVI_ATOP_70_L        (REG_DVI_ATOP_BASE + 0xE0)
752 #define REG_DVI_ATOP_70_H        (REG_DVI_ATOP_BASE + 0xE1)
753 #define REG_DVI_ATOP_71_L        (REG_DVI_ATOP_BASE + 0xE2)
754 #define REG_DVI_ATOP_71_H        (REG_DVI_ATOP_BASE + 0xE3)
755 #define REG_DVI_ATOP_72_L        (REG_DVI_ATOP_BASE + 0xE4)
756 #define REG_DVI_ATOP_72_H        (REG_DVI_ATOP_BASE + 0xE5)
757 #define REG_DVI_ATOP_73_L        (REG_DVI_ATOP_BASE + 0xE6)
758 #define REG_DVI_ATOP_73_H        (REG_DVI_ATOP_BASE + 0xE7)
759 #define REG_DVI_ATOP_74_L        (REG_DVI_ATOP_BASE + 0xE8)
760 #define REG_DVI_ATOP_74_H        (REG_DVI_ATOP_BASE + 0xE9)
761 #define REG_DVI_ATOP_75_L        (REG_DVI_ATOP_BASE + 0xEA)
762 #define REG_DVI_ATOP_75_H        (REG_DVI_ATOP_BASE + 0xEB)
763 #define REG_DVI_ATOP_76_L        (REG_DVI_ATOP_BASE + 0xEC)
764 #define REG_DVI_ATOP_76_H        (REG_DVI_ATOP_BASE + 0xED)
765 #define REG_DVI_ATOP_77_L        (REG_DVI_ATOP_BASE + 0xEE)
766 #define REG_DVI_ATOP_77_H        (REG_DVI_ATOP_BASE + 0xEF)
767 #define REG_DVI_ATOP_78_L        (REG_DVI_ATOP_BASE + 0xF0)
768 #define REG_DVI_ATOP_78_H        (REG_DVI_ATOP_BASE + 0xF1)
769 #define REG_DVI_ATOP_79_L        (REG_DVI_ATOP_BASE + 0xF2)
770 #define REG_DVI_ATOP_79_H        (REG_DVI_ATOP_BASE + 0xF3)
771 #define REG_DVI_ATOP_7A_L        (REG_DVI_ATOP_BASE + 0xF4)
772 #define REG_DVI_ATOP_7A_H        (REG_DVI_ATOP_BASE + 0xF5)
773 #define REG_DVI_ATOP_7B_L        (REG_DVI_ATOP_BASE + 0xF6)
774 #define REG_DVI_ATOP_7B_H        (REG_DVI_ATOP_BASE + 0xF7)
775 #define REG_DVI_ATOP_7C_L        (REG_DVI_ATOP_BASE + 0xF8)
776 #define REG_DVI_ATOP_7C_H        (REG_DVI_ATOP_BASE + 0xF9)
777 #define REG_DVI_ATOP_7D_L        (REG_DVI_ATOP_BASE + 0xFA)
778 #define REG_DVI_ATOP_7D_H        (REG_DVI_ATOP_BASE + 0xFB)
779 #define REG_DVI_ATOP_7E_L        (REG_DVI_ATOP_BASE + 0xFC)
780 #define REG_DVI_ATOP_7E_H        (REG_DVI_ATOP_BASE + 0xFD)
781 #define REG_DVI_ATOP_7F_L        (REG_DVI_ATOP_BASE + 0xFE)
782 #define REG_DVI_ATOP_7F_H        (REG_DVI_ATOP_BASE + 0xFF)
783 
784 // DVI ATOP1
785 #define REG_DVI_ATOP1_00_L        (REG_DVI_ATOP1_BASE + 0x00)
786 #define REG_DVI_ATOP1_00_H        (REG_DVI_ATOP1_BASE + 0x01)
787 #define REG_DVI_ATOP1_06_L        (REG_DVI_ATOP1_BASE + 0x0C)
788 #define REG_DVI_ATOP1_06_H        (REG_DVI_ATOP1_BASE + 0x0D)
789 #define REG_DVI_ATOP1_07_L        (REG_DVI_ATOP1_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
790 #define REG_DVI_ATOP1_32_L        (REG_DVI_ATOP1_BASE + 0x64)
791 #define REG_DVI_ATOP1_32_H        (REG_DVI_ATOP1_BASE + 0x65)
792 #define REG_DVI_ATOP1_5E_L        (REG_DVI_ATOP1_BASE + 0xBC)
793 #define REG_DVI_ATOP1_5E_H        (REG_DVI_ATOP1_BASE + 0xBD)
794 #define REG_DVI_ATOP1_60_L        (REG_DVI_ATOP1_BASE + 0xC0)
795 #define REG_DVI_ATOP1_60_H        (REG_DVI_ATOP1_BASE + 0xC1)
796 #define REG_DVI_ATOP1_61_L        (REG_DVI_ATOP1_BASE + 0xC2)
797 #define REG_DVI_ATOP1_61_H        (REG_DVI_ATOP1_BASE + 0xC3)
798 #define REG_DVI_ATOP1_62_L        (REG_DVI_ATOP1_BASE + 0xC4)
799 #define REG_DVI_ATOP1_63_L        (REG_DVI_ATOP1_BASE + 0xC6)
800 #define REG_DVI_ATOP1_63_H        (REG_DVI_ATOP1_BASE + 0xC7)
801 #define REG_DVI_ATOP1_64_L        (REG_DVI_ATOP1_BASE + 0xC8)
802 
803 #define REG_DVI_ATOP1_65_L        (REG_DVI_ATOP1_BASE + 0xCA)
804 #define REG_DVI_ATOP1_67_L        (REG_DVI_ATOP1_BASE + 0xCE)
805 #define REG_DVI_ATOP1_68_L        (REG_DVI_ATOP1_BASE + 0xD0)
806 #define REG_DVI_ATOP1_68_H        (REG_DVI_ATOP1_BASE + 0xD1)
807 
808 #define REG_DVI_ATOP1_70_L        (REG_DVI_ATOP1_BASE + 0xE0)
809 #define REG_DVI_ATOP1_70_H        (REG_DVI_ATOP1_BASE + 0xE1)
810 #define REG_DVI_ATOP1_71_L        (REG_DVI_ATOP1_BASE + 0xE2)
811 #define REG_DVI_ATOP1_71_H        (REG_DVI_ATOP1_BASE + 0xE3)
812 #define REG_DVI_ATOP1_74_L        (REG_DVI_ATOP1_BASE + 0xE8)
813 
814 // DVI ATOP2
815 #define REG_DVI_ATOP2_00_L        (REG_DVI_ATOP2_BASE + 0x00)
816 #define REG_DVI_ATOP2_00_H        (REG_DVI_ATOP2_BASE + 0x01)
817 #define REG_DVI_ATOP2_06_L        (REG_DVI_ATOP2_BASE + 0x0C)
818 #define REG_DVI_ATOP2_06_H        (REG_DVI_ATOP2_BASE + 0x0D)
819 #define REG_DVI_ATOP2_07_L        (REG_DVI_ATOP2_BASE + 0x0E) // ENABLE_PATCH_HDCP_FOR_SEC_PC
820 #define REG_DVI_ATOP2_32_L        (REG_DVI_ATOP2_BASE + 0x64)
821 #define REG_DVI_ATOP2_32_H        (REG_DVI_ATOP2_BASE + 0x65)
822 #define REG_DVI_ATOP2_5E_L        (REG_DVI_ATOP2_BASE + 0xBC)
823 #define REG_DVI_ATOP2_5E_H        (REG_DVI_ATOP2_BASE + 0xBD)
824 #define REG_DVI_ATOP2_60_L        (REG_DVI_ATOP2_BASE + 0xC0)
825 #define REG_DVI_ATOP2_60_H        (REG_DVI_ATOP2_BASE + 0xC1)
826 #define REG_DVI_ATOP2_61_L        (REG_DVI_ATOP2_BASE + 0xC2)
827 #define REG_DVI_ATOP2_61_H        (REG_DVI_ATOP2_BASE + 0xC3)
828 #define REG_DVI_ATOP2_62_L        (REG_DVI_ATOP2_BASE + 0xC4)
829 #define REG_DVI_ATOP2_62_H        (REG_DVI_ATOP2_BASE + 0xC5)
830 #define REG_DVI_ATOP2_63_L        (REG_DVI_ATOP2_BASE + 0xC6)
831 #define REG_DVI_ATOP2_63_H        (REG_DVI_ATOP2_BASE + 0xC7)
832 
833 #define REG_DVI_ATOP2_64_L        (REG_DVI_ATOP2_BASE + 0xC8)
834 #define REG_DVI_ATOP2_64_H        (REG_DVI_ATOP2_BASE + 0xC9)
835 #define REG_DVI_ATOP2_65_L        (REG_DVI_ATOP2_BASE + 0xCA)
836 #define REG_DVI_ATOP2_66_L        (REG_DVI_ATOP2_BASE + 0xCC)
837 #define REG_DVI_ATOP2_66_H        (REG_DVI_ATOP2_BASE + 0xCD)
838 #define REG_DVI_ATOP2_67_L        (REG_DVI_ATOP2_BASE + 0xCE)
839 #define REG_DVI_ATOP2_68_L        (REG_DVI_ATOP2_BASE + 0xD0)
840 #define REG_DVI_ATOP2_68_H        (REG_DVI_ATOP2_BASE + 0xD1)
841 
842 #define REG_DVI_ATOP2_69_L        (REG_DVI_ATOP2_BASE + 0xD2)
843 #define REG_DVI_ATOP2_69_H        (REG_DVI_ATOP2_BASE + 0xD3)
844 #define REG_DVI_ATOP2_6D_L        (REG_DVI_ATOP2_BASE + 0xDA)
845 #define REG_DVI_ATOP2_6D_H        (REG_DVI_ATOP2_BASE + 0xDB)
846 #define REG_DVI_ATOP2_70_L        (REG_DVI_ATOP2_BASE + 0xE0)
847 #define REG_DVI_ATOP2_70_H        (REG_DVI_ATOP2_BASE + 0xE1)
848 #define REG_DVI_ATOP2_71_L        (REG_DVI_ATOP2_BASE + 0xE2)
849 #define REG_DVI_ATOP2_71_H        (REG_DVI_ATOP2_BASE + 0xE3)
850 #define REG_DVI_ATOP2_74_L        (REG_DVI_ATOP2_BASE + 0xE8)
851 
852 // DVI ATOP3
853 #define REG_DVI_ATOP3_00_L        (REG_DVI_ATOP3_BASE + 0x00)
854 #define REG_DVI_ATOP3_00_H        (REG_DVI_ATOP3_BASE + 0x01)
855 #define REG_DVI_ATOP3_06_L        (REG_DVI_ATOP3_BASE + 0x0C)
856 #define REG_DVI_ATOP3_06_H        (REG_DVI_ATOP3_BASE + 0x0D)
857 #define REG_DVI_ATOP3_07_L        (REG_DVI_ATOP3_BASE + 0x0E)
858 #define REG_DVI_ATOP3_07_H        (REG_DVI_ATOP3_BASE + 0x0F)
859 #define REG_DVI_ATOP3_0A_L        (REG_DVI_ATOP3_BASE + 0x14)
860 #define REG_DVI_ATOP3_0A_H        (REG_DVI_ATOP3_BASE + 0x15)
861 #define REG_DVI_ATOP3_0B_L        (REG_DVI_ATOP3_BASE + 0x16)
862 #define REG_DVI_ATOP3_0B_H        (REG_DVI_ATOP3_BASE + 0x17)
863 #define REG_DVI_ATOP3_0C_L        (REG_DVI_ATOP3_BASE + 0x18)
864 #define REG_DVI_ATOP3_0C_H        (REG_DVI_ATOP3_BASE + 0x19)
865 #define REG_DVI_ATOP3_5E_L        (REG_DVI_ATOP3_BASE + 0xBC)
866 #define REG_DVI_ATOP3_5E_H        (REG_DVI_ATOP3_BASE + 0xBD)
867 #define REG_DVI_ATOP3_60_L        (REG_DVI_ATOP3_BASE + 0xC0)
868 #define REG_DVI_ATOP3_60_H        (REG_DVI_ATOP3_BASE + 0xC1)
869 #define REG_DVI_ATOP3_61_L        (REG_DVI_ATOP3_BASE + 0xC2)
870 #define REG_DVI_ATOP3_61_H        (REG_DVI_ATOP3_BASE + 0xC3)
871 #define REG_DVI_ATOP3_62_L        (REG_DVI_ATOP3_BASE + 0xC4)
872 #define REG_DVI_ATOP3_62_H        (REG_DVI_ATOP3_BASE + 0xC5)
873 #define REG_DVI_ATOP3_63_L        (REG_DVI_ATOP3_BASE + 0xC6)
874 #define REG_DVI_ATOP3_63_H        (REG_DVI_ATOP3_BASE + 0xC7)
875 #define REG_DVI_ATOP3_64_L        (REG_DVI_ATOP3_BASE + 0xC8)
876 #define REG_DVI_ATOP3_64_H        (REG_DVI_ATOP3_BASE + 0xC9)
877 #define REG_DVI_ATOP3_65_L        (REG_DVI_ATOP3_BASE + 0xCA)
878 #define REG_DVI_ATOP3_65_H        (REG_DVI_ATOP3_BASE + 0xCB)
879 #define REG_DVI_ATOP3_67_L        (REG_DVI_ATOP3_BASE + 0xCE)
880 #define REG_DVI_ATOP3_67_H        (REG_DVI_ATOP3_BASE + 0xCF)
881 #define REG_DVI_ATOP3_68_L        (REG_DVI_ATOP3_BASE + 0xD0)
882 #define REG_DVI_ATOP3_68_H        (REG_DVI_ATOP3_BASE + 0xD1)
883 
884 #define REG_DVI_ATOP3_70_L        (REG_DVI_ATOP3_BASE + 0xE0)
885 #define REG_DVI_ATOP3_70_H        (REG_DVI_ATOP3_BASE + 0xE1)
886 #define REG_DVI_ATOP3_71_L        (REG_DVI_ATOP3_BASE + 0xE2)
887 #define REG_DVI_ATOP3_71_H        (REG_DVI_ATOP3_BASE + 0xE3)
888 #define REG_DVI_ATOP3_74_L        (REG_DVI_ATOP3_BASE + 0xE8)
889 #define REG_DVI_ATOP3_74_H        (REG_DVI_ATOP3_BASE + 0xE9)
890 
891 //=============================================================
892 // DVI Power Saving
893 #define REG_DVI_PS_00_L         (REG_DVI_PS_BASE + 0x00)
894 #define REG_DVI_PS_00_H         (REG_DVI_PS_BASE + 0x01)
895 #define REG_DVI_PS_01_L         (REG_DVI_PS_BASE + 0x02)
896 #define REG_DVI_PS_01_H         (REG_DVI_PS_BASE + 0x03)
897 #define REG_DVI_PS_02_L         (REG_DVI_PS_BASE + 0x04)
898 #define REG_DVI_PS_02_H         (REG_DVI_PS_BASE + 0x05)
899 #define REG_DVI_PS_03_L         (REG_DVI_PS_BASE + 0x06)
900 #define REG_DVI_PS_03_H         (REG_DVI_PS_BASE + 0x07)
901 #define REG_DVI_PS_04_L         (REG_DVI_PS_BASE + 0x08)	//
902 #define REG_DVI_PS_04_H         (REG_DVI_PS_BASE + 0x09)	//add DVI VDE period change tolerance
903 #define REG_DVI_PS_06_L         (REG_DVI_PS_BASE + 0x0C)
904 #define REG_DVI_PS_06_H         (REG_DVI_PS_BASE + 0x0D)
905 #define REG_DVI_PS_0A_L         (REG_DVI_PS_BASE + 0x14)
906 #define REG_DVI_PS_0A_H         (REG_DVI_PS_BASE + 0x15)
907 #define REG_DVI_PS_0B_L         (REG_DVI_PS_BASE + 0x16)
908 #define REG_DVI_PS_0B_H         (REG_DVI_PS_BASE + 0x17)
909 #define REG_DVI_PS_12_L         (REG_DVI_PS_BASE + 0x24)
910 #define REG_DVI_PS_12_H         (REG_DVI_PS_BASE + 0x25)
911 
912 
913 // DVI PS1
914 #define REG_DVI_PS1_00_L         (REG_DVI_PS1_BASE + 0x00)
915 #define REG_DVI_PS1_00_H         (REG_DVI_PS1_BASE + 0x01)
916 #define REG_DVI_PS1_01_L         (REG_DVI_PS1_BASE + 0x02)
917 #define REG_DVI_PS1_01_H         (REG_DVI_PS1_BASE + 0x03)
918 #define REG_DVI_PS1_0B_L         (REG_DVI_PS1_BASE + 0x16)
919 #define REG_DVI_PS1_0B_H         (REG_DVI_PS1_BASE + 0x17)
920 // DVI PS2
921 #define REG_DVI_PS2_00_L         (REG_DVI_PS2_BASE + 0x00)
922 #define REG_DVI_PS2_00_H         (REG_DVI_PS2_BASE + 0x01)
923 #define REG_DVI_PS2_01_L         (REG_DVI_PS2_BASE + 0x02)
924 #define REG_DVI_PS2_01_H         (REG_DVI_PS2_BASE + 0x03)
925 #define REG_DVI_PS2_0B_L         (REG_DVI_PS2_BASE + 0x16)
926 #define REG_DVI_PS2_0B_H         (REG_DVI_PS2_BASE + 0x17)
927 // DVI PS3
928 #define REG_DVI_PS3_00_L         (REG_DVI_PS3_BASE + 0x00)
929 #define REG_DVI_PS3_00_H         (REG_DVI_PS3_BASE + 0x01)
930 #define REG_DVI_PS3_01_L         (REG_DVI_PS3_BASE + 0x02)
931 #define REG_DVI_PS3_01_H         (REG_DVI_PS3_BASE + 0x03)
932 #define REG_DVI_PS3_0B_L         (REG_DVI_PS3_BASE + 0x16)
933 #define REG_DVI_PS3_0B_H         (REG_DVI_PS3_BASE + 0x17)
934 //=============================================================
935 //HDMI
936 //#define REG_HDMI_BASE       0x2700
937 
938 #define REG_HDMI_00_L       (REG_HDMI_BASE + 0x00)
939 #define REG_HDMI_00_H       (REG_HDMI_BASE + 0x01)
940 #define REG_HDMI_01_L       (REG_HDMI_BASE + 0x02)
941 #define REG_HDMI_01_H       (REG_HDMI_BASE + 0x03)
942 #define REG_HDMI_02_L       (REG_HDMI_BASE + 0x04)
943 #define REG_HDMI_02_H       (REG_HDMI_BASE + 0x05)
944 #define REG_HDMI_03_L       (REG_HDMI_BASE + 0x06)
945 #define REG_HDMI_03_H       (REG_HDMI_BASE + 0x07)
946 #define REG_HDMI_04_L       (REG_HDMI_BASE + 0x08)
947 #define REG_HDMI_04_H       (REG_HDMI_BASE + 0x09)
948 #define REG_HDMI_05_L       (REG_HDMI_BASE + 0x0A)
949 #define REG_HDMI_05_H       (REG_HDMI_BASE + 0x0B)
950 #define REG_HDMI_06_L       (REG_HDMI_BASE + 0x0C)
951 #define REG_HDMI_06_H       (REG_HDMI_BASE + 0x0D)
952 #define REG_HDMI_07_L       (REG_HDMI_BASE + 0x0E)
953 #define REG_HDMI_07_H       (REG_HDMI_BASE + 0x0F)
954 #define REG_HDMI_08_L       (REG_HDMI_BASE + 0x10)
955 #define REG_HDMI_08_H       (REG_HDMI_BASE + 0x11)
956 #define REG_HDMI_09_L       (REG_HDMI_BASE + 0x12)
957 #define REG_HDMI_09_H       (REG_HDMI_BASE + 0x13)
958 #define REG_HDMI_0A_L       (REG_HDMI_BASE + 0x14)
959 #define REG_HDMI_0A_H       (REG_HDMI_BASE + 0x15)
960 #define REG_HDMI_0B_L       (REG_HDMI_BASE + 0x16)
961 #define REG_HDMI_0B_H       (REG_HDMI_BASE + 0x17)
962 #define REG_HDMI_0C_L       (REG_HDMI_BASE + 0x18)
963 #define REG_HDMI_0C_H       (REG_HDMI_BASE + 0x19)
964 #define REG_HDMI_0D_L       (REG_HDMI_BASE + 0x1A)
965 #define REG_HDMI_0D_H       (REG_HDMI_BASE + 0x1B)
966 #define REG_HDMI_0E_L       (REG_HDMI_BASE + 0x1C)
967 #define REG_HDMI_0E_H       (REG_HDMI_BASE + 0x1D)
968 #define REG_HDMI_0F_L       (REG_HDMI_BASE + 0x1E)
969 #define REG_HDMI_0F_H       (REG_HDMI_BASE + 0x1F)
970 #define REG_HDMI_10_L       (REG_HDMI_BASE + 0x20)
971 #define REG_HDMI_10_H       (REG_HDMI_BASE + 0x21)
972 #define REG_HDMI_11_L       (REG_HDMI_BASE + 0x22)
973 #define REG_HDMI_11_H       (REG_HDMI_BASE + 0x23)
974 #define REG_HDMI_12_L       (REG_HDMI_BASE + 0x24)
975 #define REG_HDMI_12_H       (REG_HDMI_BASE + 0x25)
976 #define REG_HDMI_13_L       (REG_HDMI_BASE + 0x26)
977 #define REG_HDMI_13_H       (REG_HDMI_BASE + 0x27)
978 #define REG_HDMI_14_L       (REG_HDMI_BASE + 0x28)
979 #define REG_HDMI_14_H       (REG_HDMI_BASE + 0x29)
980 #define REG_HDMI_15_L       (REG_HDMI_BASE + 0x2A)
981 #define REG_HDMI_15_H       (REG_HDMI_BASE + 0x2B)
982 #define REG_HDMI_16_L       (REG_HDMI_BASE + 0x2C)
983 #define REG_HDMI_16_H       (REG_HDMI_BASE + 0x2D)
984 #define REG_HDMI_17_L       (REG_HDMI_BASE + 0x2E)
985 #define REG_HDMI_17_H       (REG_HDMI_BASE + 0x2F)
986 #define REG_HDMI_18_L       (REG_HDMI_BASE + 0x30)
987 #define REG_HDMI_18_H       (REG_HDMI_BASE + 0x31)
988 #define REG_HDMI_19_L       (REG_HDMI_BASE + 0x32)
989 #define REG_HDMI_19_H       (REG_HDMI_BASE + 0x33)
990 #define REG_HDMI_1A_L       (REG_HDMI_BASE + 0x34)
991 #define REG_HDMI_1A_H       (REG_HDMI_BASE + 0x35)
992 #define REG_HDMI_1B_L       (REG_HDMI_BASE + 0x36)
993 #define REG_HDMI_1B_H       (REG_HDMI_BASE + 0x37)
994 #define REG_HDMI_1C_L       (REG_HDMI_BASE + 0x38)
995 #define REG_HDMI_1C_H       (REG_HDMI_BASE + 0x39)
996 #define REG_HDMI_1D_L       (REG_HDMI_BASE + 0x3A)
997 #define REG_HDMI_1D_H       (REG_HDMI_BASE + 0x3B)
998 #define REG_HDMI_1E_L       (REG_HDMI_BASE + 0x3C)
999 #define REG_HDMI_1E_H       (REG_HDMI_BASE + 0x3D)
1000 #define REG_HDMI_1F_L       (REG_HDMI_BASE + 0x3E)
1001 #define REG_HDMI_1F_H       (REG_HDMI_BASE + 0x3F)
1002 #define REG_HDMI_20_L       (REG_HDMI_BASE + 0x40)
1003 #define REG_HDMI_20_H       (REG_HDMI_BASE + 0x41)
1004 #define REG_HDMI_21_L       (REG_HDMI_BASE + 0x42)
1005 #define REG_HDMI_21_H       (REG_HDMI_BASE + 0x43)
1006 #define REG_HDMI_22_L       (REG_HDMI_BASE + 0x44)
1007 #define REG_HDMI_22_H       (REG_HDMI_BASE + 0x45)
1008 #define REG_HDMI_23_L       (REG_HDMI_BASE + 0x46)
1009 #define REG_HDMI_23_H       (REG_HDMI_BASE + 0x47)
1010 #define REG_HDMI_24_L       (REG_HDMI_BASE + 0x48)
1011 #define REG_HDMI_24_H       (REG_HDMI_BASE + 0x49)
1012 #define REG_HDMI_25_L       (REG_HDMI_BASE + 0x4A)
1013 #define REG_HDMI_25_H       (REG_HDMI_BASE + 0x4B)
1014 #define REG_HDMI_26_L       (REG_HDMI_BASE + 0x4C)
1015 #define REG_HDMI_26_H       (REG_HDMI_BASE + 0x4D)
1016 #define REG_HDMI_27_L       (REG_HDMI_BASE + 0x4E)
1017 #define REG_HDMI_27_H       (REG_HDMI_BASE + 0x4F)
1018 #define REG_HDMI_28_L       (REG_HDMI_BASE + 0x50)
1019 #define REG_HDMI_28_H       (REG_HDMI_BASE + 0x51)
1020 #define REG_HDMI_29_L       (REG_HDMI_BASE + 0x52)
1021 #define REG_HDMI_29_H       (REG_HDMI_BASE + 0x53)
1022 #define REG_HDMI_2A_L       (REG_HDMI_BASE + 0x54)
1023 #define REG_HDMI_2A_H       (REG_HDMI_BASE + 0x55)
1024 #define REG_HDMI_2B_L       (REG_HDMI_BASE + 0x56)
1025 #define REG_HDMI_2B_H       (REG_HDMI_BASE + 0x57)
1026 #define REG_HDMI_2C_L       (REG_HDMI_BASE + 0x58)
1027 #define REG_HDMI_2C_H       (REG_HDMI_BASE + 0x59)
1028 #define REG_HDMI_2D_L       (REG_HDMI_BASE + 0x5A)
1029 #define REG_HDMI_2D_H       (REG_HDMI_BASE + 0x5B)
1030 #define REG_HDMI_2E_L       (REG_HDMI_BASE + 0x5C)
1031 #define REG_HDMI_2E_H       (REG_HDMI_BASE + 0x5D)
1032 #define REG_HDMI_2F_L       (REG_HDMI_BASE + 0x5E)
1033 #define REG_HDMI_2F_H       (REG_HDMI_BASE + 0x5F)
1034 #define REG_HDMI_30_L       (REG_HDMI_BASE + 0x60)
1035 #define REG_HDMI_30_H       (REG_HDMI_BASE + 0x61)
1036 #define REG_HDMI_31_L       (REG_HDMI_BASE + 0x62)
1037 #define REG_HDMI_31_H       (REG_HDMI_BASE + 0x63)
1038 #define REG_HDMI_32_L       (REG_HDMI_BASE + 0x64)
1039 #define REG_HDMI_32_H       (REG_HDMI_BASE + 0x65)
1040 #define REG_HDMI_33_L       (REG_HDMI_BASE + 0x66)
1041 #define REG_HDMI_33_H       (REG_HDMI_BASE + 0x67)
1042 #define REG_HDMI_34_L       (REG_HDMI_BASE + 0x68)
1043 #define REG_HDMI_34_H       (REG_HDMI_BASE + 0x69)
1044 #define REG_HDMI_35_L       (REG_HDMI_BASE + 0x6A)
1045 #define REG_HDMI_35_H       (REG_HDMI_BASE + 0x6B)
1046 #define REG_HDMI_36_L       (REG_HDMI_BASE + 0x6C)
1047 #define REG_HDMI_36_H       (REG_HDMI_BASE + 0x6D)
1048 #define REG_HDMI_37_L       (REG_HDMI_BASE + 0x6E)
1049 #define REG_HDMI_37_H       (REG_HDMI_BASE + 0x6F)
1050 #define REG_HDMI_38_L       (REG_HDMI_BASE + 0x70)
1051 #define REG_HDMI_38_H       (REG_HDMI_BASE + 0x71)
1052 #define REG_HDMI_39_L       (REG_HDMI_BASE + 0x72)
1053 #define REG_HDMI_39_H       (REG_HDMI_BASE + 0x73)
1054 #define REG_HDMI_3A_L       (REG_HDMI_BASE + 0x74)
1055 #define REG_HDMI_3A_H       (REG_HDMI_BASE + 0x75)
1056 #define REG_HDMI_3B_L       (REG_HDMI_BASE + 0x76)
1057 #define REG_HDMI_3B_H       (REG_HDMI_BASE + 0x77)
1058 #define REG_HDMI_3C_L       (REG_HDMI_BASE + 0x78)
1059 #define REG_HDMI_3C_H       (REG_HDMI_BASE + 0x79)
1060 #define REG_HDMI_3D_L       (REG_HDMI_BASE + 0x7A)
1061 #define REG_HDMI_3D_H       (REG_HDMI_BASE + 0x7B)
1062 #define REG_HDMI_3E_L       (REG_HDMI_BASE + 0x7C)
1063 #define REG_HDMI_3E_H       (REG_HDMI_BASE + 0x7D)
1064 #define REG_HDMI_3F_L       (REG_HDMI_BASE + 0x7E)
1065 #define REG_HDMI_3F_H       (REG_HDMI_BASE + 0x7F)
1066 #define REG_HDMI_40_L       (REG_HDMI_BASE + 0x80)
1067 #define REG_HDMI_40_H       (REG_HDMI_BASE + 0x81)
1068 #define REG_HDMI_41_L       (REG_HDMI_BASE + 0x82)
1069 #define REG_HDMI_41_H       (REG_HDMI_BASE + 0x83)
1070 #define REG_HDMI_42_L       (REG_HDMI_BASE + 0x84)
1071 #define REG_HDMI_42_H       (REG_HDMI_BASE + 0x85)
1072 #define REG_HDMI_43_L       (REG_HDMI_BASE + 0x86)
1073 #define REG_HDMI_43_H       (REG_HDMI_BASE + 0x87)
1074 #define REG_HDMI_44_L       (REG_HDMI_BASE + 0x88)
1075 #define REG_HDMI_44_H       (REG_HDMI_BASE + 0x89)
1076 #define REG_HDMI_45_L       (REG_HDMI_BASE + 0x8A)
1077 #define REG_HDMI_45_H       (REG_HDMI_BASE + 0x8B)
1078 #define REG_HDMI_46_L       (REG_HDMI_BASE + 0x8C)
1079 #define REG_HDMI_46_H       (REG_HDMI_BASE + 0x8D)
1080 #define REG_HDMI_47_L       (REG_HDMI_BASE + 0x8E)
1081 #define REG_HDMI_47_H       (REG_HDMI_BASE + 0x8F)
1082 #define REG_HDMI_48_L       (REG_HDMI_BASE + 0x90)
1083 #define REG_HDMI_48_H       (REG_HDMI_BASE + 0x91)
1084 #define REG_HDMI_49_L       (REG_HDMI_BASE + 0x92)
1085 #define REG_HDMI_49_H       (REG_HDMI_BASE + 0x93)
1086 #define REG_HDMI_4A_L       (REG_HDMI_BASE + 0x94)
1087 #define REG_HDMI_4A_H       (REG_HDMI_BASE + 0x95)
1088 #define REG_HDMI_4B_L       (REG_HDMI_BASE + 0x96)
1089 #define REG_HDMI_4B_H       (REG_HDMI_BASE + 0x97)
1090 #define REG_HDMI_4C_L       (REG_HDMI_BASE + 0x98)
1091 #define REG_HDMI_4C_H       (REG_HDMI_BASE + 0x99)
1092 #define REG_HDMI_4D_L       (REG_HDMI_BASE + 0x9A)
1093 #define REG_HDMI_4D_H       (REG_HDMI_BASE + 0x9B)
1094 #define REG_HDMI_4E_L       (REG_HDMI_BASE + 0x9C)
1095 #define REG_HDMI_4E_H       (REG_HDMI_BASE + 0x9D)
1096 #define REG_HDMI_4F_L       (REG_HDMI_BASE + 0x9E)
1097 #define REG_HDMI_4F_H       (REG_HDMI_BASE + 0x9F)
1098 #define REG_HDMI_50_L       (REG_HDMI_BASE + 0xA0)
1099 #define REG_HDMI_50_H       (REG_HDMI_BASE + 0xA1)
1100 #define REG_HDMI_51_L       (REG_HDMI_BASE + 0xA2)
1101 #define REG_HDMI_51_H       (REG_HDMI_BASE + 0xA3)
1102 #define REG_HDMI_52_L       (REG_HDMI_BASE + 0xA4)
1103 #define REG_HDMI_52_H       (REG_HDMI_BASE + 0xA5)
1104 #define REG_HDMI_53_L       (REG_HDMI_BASE + 0xA6)
1105 #define REG_HDMI_53_H       (REG_HDMI_BASE + 0xA7)
1106 #define REG_HDMI_54_L       (REG_HDMI_BASE + 0xA8)
1107 #define REG_HDMI_54_H       (REG_HDMI_BASE + 0xA9)
1108 #define REG_HDMI_55_L       (REG_HDMI_BASE + 0xAA)
1109 #define REG_HDMI_55_H       (REG_HDMI_BASE + 0xAB)
1110 #define REG_HDMI_56_L       (REG_HDMI_BASE + 0xAC)
1111 #define REG_HDMI_56_H       (REG_HDMI_BASE + 0xAD)
1112 #define REG_HDMI_57_L       (REG_HDMI_BASE + 0xAE)
1113 #define REG_HDMI_57_H       (REG_HDMI_BASE + 0xAF)
1114 #define REG_HDMI_58_L       (REG_HDMI_BASE + 0xB0)
1115 #define REG_HDMI_58_H       (REG_HDMI_BASE + 0xB1)
1116 #define REG_HDMI_59_L       (REG_HDMI_BASE + 0xB2)
1117 #define REG_HDMI_59_H       (REG_HDMI_BASE + 0xB3)
1118 #define REG_HDMI_5A_L       (REG_HDMI_BASE + 0xB4)
1119 #define REG_HDMI_5A_H       (REG_HDMI_BASE + 0xB5)
1120 #define REG_HDMI_5B_L       (REG_HDMI_BASE + 0xB6)
1121 #define REG_HDMI_5B_H       (REG_HDMI_BASE + 0xB7)
1122 #define REG_HDMI_5C_L       (REG_HDMI_BASE + 0xB8)
1123 #define REG_HDMI_5C_H       (REG_HDMI_BASE + 0xB9)
1124 #define REG_HDMI_5D_L       (REG_HDMI_BASE + 0xBA)
1125 #define REG_HDMI_5D_H       (REG_HDMI_BASE + 0xBB)
1126 #define REG_HDMI_5E_L       (REG_HDMI_BASE + 0xBC)
1127 #define REG_HDMI_5E_H       (REG_HDMI_BASE + 0xBD)
1128 #define REG_HDMI_5F_L       (REG_HDMI_BASE + 0xBE)
1129 #define REG_HDMI_5F_H       (REG_HDMI_BASE + 0xBF)
1130 #define REG_HDMI_60_L       (REG_HDMI_BASE + 0xC0)
1131 #define REG_HDMI_60_H       (REG_HDMI_BASE + 0xC1)
1132 #define REG_HDMI_61_L       (REG_HDMI_BASE + 0xC2)
1133 #define REG_HDMI_61_H       (REG_HDMI_BASE + 0xC3)
1134 #define REG_HDMI_62_L       (REG_HDMI_BASE + 0xC4)
1135 #define REG_HDMI_62_H       (REG_HDMI_BASE + 0xC5)
1136 #define REG_HDMI_63_L       (REG_HDMI_BASE + 0xC6)
1137 #define REG_HDMI_63_H       (REG_HDMI_BASE + 0xC7)
1138 #define REG_HDMI_64_L       (REG_HDMI_BASE + 0xC8)
1139 #define REG_HDMI_64_H       (REG_HDMI_BASE + 0xC9)
1140 #define REG_HDMI_65_L       (REG_HDMI_BASE + 0xCA)
1141 #define REG_HDMI_65_H       (REG_HDMI_BASE + 0xCB)
1142 #define REG_HDMI_66_L       (REG_HDMI_BASE + 0xCC)
1143 #define REG_HDMI_66_H       (REG_HDMI_BASE + 0xCD)
1144 #define REG_HDMI_67_L       (REG_HDMI_BASE + 0xCE)
1145 #define REG_HDMI_67_H       (REG_HDMI_BASE + 0xCF)
1146 #define REG_HDMI_68_L       (REG_HDMI_BASE + 0xD0)
1147 #define REG_HDMI_68_H       (REG_HDMI_BASE + 0xD1)
1148 #define REG_HDMI_69_L       (REG_HDMI_BASE + 0xD2)
1149 #define REG_HDMI_69_H       (REG_HDMI_BASE + 0xD3)
1150 #define REG_HDMI_6A_L       (REG_HDMI_BASE + 0xD4)
1151 #define REG_HDMI_6A_H       (REG_HDMI_BASE + 0xD5)
1152 #define REG_HDMI_6B_L       (REG_HDMI_BASE + 0xD6)
1153 #define REG_HDMI_6B_H       (REG_HDMI_BASE + 0xD7)
1154 #define REG_HDMI_6C_L       (REG_HDMI_BASE + 0xD8)
1155 #define REG_HDMI_6C_H       (REG_HDMI_BASE + 0xD9)
1156 #define REG_HDMI_6D_L       (REG_HDMI_BASE + 0xDA)
1157 #define REG_HDMI_6D_H       (REG_HDMI_BASE + 0xDB)
1158 #define REG_HDMI_6E_L       (REG_HDMI_BASE + 0xDC)
1159 #define REG_HDMI_6E_H       (REG_HDMI_BASE + 0xDD)
1160 #define REG_HDMI_6F_L       (REG_HDMI_BASE + 0xDE)
1161 #define REG_HDMI_6F_H       (REG_HDMI_BASE + 0xDF)
1162 #define REG_HDMI_70_L       (REG_HDMI_BASE + 0xE0)
1163 #define REG_HDMI_70_H       (REG_HDMI_BASE + 0xE1)
1164 #define REG_HDMI_71_L       (REG_HDMI_BASE + 0xE2)
1165 #define REG_HDMI_71_H       (REG_HDMI_BASE + 0xE3)
1166 #define REG_HDMI_72_L       (REG_HDMI_BASE + 0xE4)
1167 #define REG_HDMI_72_H       (REG_HDMI_BASE + 0xE5)
1168 #define REG_HDMI_73_L       (REG_HDMI_BASE + 0xE6)
1169 #define REG_HDMI_73_H       (REG_HDMI_BASE + 0xE7)
1170 #define REG_HDMI_74_L       (REG_HDMI_BASE + 0xE8)
1171 #define REG_HDMI_74_H       (REG_HDMI_BASE + 0xE9)
1172 #define REG_HDMI_75_L       (REG_HDMI_BASE + 0xEA)
1173 #define REG_HDMI_75_H       (REG_HDMI_BASE + 0xEB)
1174 #define REG_HDMI_76_L       (REG_HDMI_BASE + 0xEC)
1175 #define REG_HDMI_76_H       (REG_HDMI_BASE + 0xED)
1176 #define REG_HDMI_77_L       (REG_HDMI_BASE + 0xEE)
1177 #define REG_HDMI_77_H       (REG_HDMI_BASE + 0xEF)
1178 #define REG_HDMI_78_L       (REG_HDMI_BASE + 0xF0)
1179 #define REG_HDMI_78_H       (REG_HDMI_BASE + 0xF1)
1180 #define REG_HDMI_79_L       (REG_HDMI_BASE + 0xF2)
1181 #define REG_HDMI_79_H       (REG_HDMI_BASE + 0xF3)
1182 #define REG_HDMI_7A_L       (REG_HDMI_BASE + 0xF4)
1183 #define REG_HDMI_7A_H       (REG_HDMI_BASE + 0xF5)
1184 #define REG_HDMI_7B_L       (REG_HDMI_BASE + 0xF6)
1185 #define REG_HDMI_7B_H       (REG_HDMI_BASE + 0xF7)
1186 #define REG_HDMI_7C_L       (REG_HDMI_BASE + 0xF8)
1187 #define REG_HDMI_7C_H       (REG_HDMI_BASE + 0xF9)
1188 #define REG_HDMI_7D_L       (REG_HDMI_BASE + 0xFA)
1189 #define REG_HDMI_7D_H       (REG_HDMI_BASE + 0xFB)
1190 #define REG_HDMI_7E_L       (REG_HDMI_BASE + 0xFC)
1191 #define REG_HDMI_7E_H       (REG_HDMI_BASE + 0xFD)
1192 #define REG_HDMI_7F_L       (REG_HDMI_BASE + 0xFE)
1193 #define REG_HDMI_7F_H       (REG_HDMI_BASE + 0xFF)
1194 
1195 // HDMI2
1196 #define REG_HDMI2_01_L       (REG_HDMI2_BASE + 0x02)
1197 #define REG_HDMI2_01_H       (REG_HDMI2_BASE + 0x03)
1198 #define REG_HDMI2_02_L       (REG_HDMI2_BASE + 0x04)
1199 #define REG_HDMI2_02_H       (REG_HDMI2_BASE + 0x05)
1200 #define REG_HDMI2_03_L       (REG_HDMI2_BASE + 0x06)
1201 #define REG_HDMI2_03_H       (REG_HDMI2_BASE + 0x07)
1202 #define REG_HDMI2_06_L       (REG_HDMI2_BASE + 0x0C)
1203 #define REG_HDMI2_06_H       (REG_HDMI2_BASE + 0x0D)
1204 #define REG_HDMI2_08_L       (REG_HDMI2_BASE + 0x10)
1205 #define REG_HDMI2_08_H       (REG_HDMI2_BASE + 0x11)
1206 #define REG_HDMI2_10_L       (REG_HDMI2_BASE + 0x20)
1207 #define REG_HDMI2_10_H       (REG_HDMI2_BASE + 0x21)
1208 #define REG_HDMI2_11_L       (REG_HDMI2_BASE + 0x22)
1209 #define REG_HDMI2_11_H       (REG_HDMI2_BASE + 0x23)
1210 #define REG_HDMI2_12_L       (REG_HDMI2_BASE + 0x24)
1211 #define REG_HDMI2_12_H       (REG_HDMI2_BASE + 0x25)
1212 #define REG_HDMI2_13_L       (REG_HDMI2_BASE + 0x26)
1213 #define REG_HDMI2_13_H       (REG_HDMI2_BASE + 0x27)
1214 #define REG_HDMI2_15_L       (REG_HDMI2_BASE + 0x2A)
1215 #define REG_HDMI2_15_H       (REG_HDMI2_BASE + 0x2B)
1216 #define REG_HDMI2_20_L       (REG_HDMI2_BASE + 0x40)
1217 #define REG_HDMI2_20_H       (REG_HDMI2_BASE + 0x41)
1218 #define REG_HDMI2_25_L       (REG_HDMI2_BASE + 0x4A)
1219 #define REG_HDMI2_25_H       (REG_HDMI2_BASE + 0x4B)
1220 #define REG_HDMI2_26_L       (REG_HDMI2_BASE + 0x4C)
1221 #define REG_HDMI2_26_H       (REG_HDMI2_BASE + 0x4D)
1222 #define REG_HDMI2_27_L       (REG_HDMI2_BASE + 0x4E)
1223 #define REG_HDMI2_27_H       (REG_HDMI2_BASE + 0x4F)
1224 #define REG_HDMI2_33_L       (REG_HDMI2_BASE + 0x66)
1225 #define REG_HDMI2_34_L       (REG_HDMI2_BASE + 0x68)
1226 #define REG_HDMI2_35_L       (REG_HDMI2_BASE + 0x6A)
1227 #define REG_HDMI2_36_L       (REG_HDMI2_BASE + 0x6C)
1228 #define REG_HDMI2_36_H       (REG_HDMI2_BASE + 0x6D)
1229 
1230 //#define REG_MHL_TMDS_BASE       0x2700
1231 #define REG_MHL_TMDS_00_L       (REG_MHL_TMDS_BASE + 0x00)
1232 #define REG_MHL_TMDS_00_H       (REG_MHL_TMDS_BASE + 0x01)
1233 #define REG_MHL_TMDS_01_L       (REG_MHL_TMDS_BASE + 0x02)
1234 #define REG_MHL_TMDS_01_H       (REG_MHL_TMDS_BASE + 0x03)
1235 #define REG_MHL_TMDS_02_L       (REG_MHL_TMDS_BASE + 0x04)
1236 #define REG_MHL_TMDS_02_H       (REG_MHL_TMDS_BASE + 0x05)
1237 #define REG_MHL_TMDS_03_L       (REG_MHL_TMDS_BASE + 0x06)
1238 #define REG_MHL_TMDS_03_H       (REG_MHL_TMDS_BASE + 0x07)
1239 #define REG_MHL_TMDS_04_L       (REG_MHL_TMDS_BASE + 0x08)
1240 #define REG_MHL_TMDS_04_H       (REG_MHL_TMDS_BASE + 0x09)
1241 #define REG_MHL_TMDS_05_L       (REG_MHL_TMDS_BASE + 0x0A)
1242 #define REG_MHL_TMDS_05_H       (REG_MHL_TMDS_BASE + 0x0B)
1243 #define REG_MHL_TMDS_06_L       (REG_MHL_TMDS_BASE + 0x0C)
1244 #define REG_MHL_TMDS_06_H       (REG_MHL_TMDS_BASE + 0x0D)
1245 #define REG_MHL_TMDS_07_L       (REG_MHL_TMDS_BASE + 0x0E)
1246 #define REG_MHL_TMDS_07_H       (REG_MHL_TMDS_BASE + 0x0F)
1247 #define REG_MHL_TMDS_08_L       (REG_MHL_TMDS_BASE + 0x10)
1248 #define REG_MHL_TMDS_08_H       (REG_MHL_TMDS_BASE + 0x11)
1249 #define REG_MHL_TMDS_09_L       (REG_MHL_TMDS_BASE + 0x12)
1250 #define REG_MHL_TMDS_09_H       (REG_MHL_TMDS_BASE + 0x13)
1251 #define REG_MHL_TMDS_0A_L       (REG_MHL_TMDS_BASE + 0x14)
1252 #define REG_MHL_TMDS_0A_H       (REG_MHL_TMDS_BASE + 0x15)
1253 #define REG_MHL_TMDS_0B_L       (REG_MHL_TMDS_BASE + 0x16)
1254 #define REG_MHL_TMDS_0B_H       (REG_MHL_TMDS_BASE + 0x17)
1255 #define REG_MHL_TMDS_0C_L       (REG_MHL_TMDS_BASE + 0x18)
1256 #define REG_MHL_TMDS_0C_H       (REG_MHL_TMDS_BASE + 0x19)
1257 #define REG_MHL_TMDS_0D_L       (REG_MHL_TMDS_BASE + 0x1A)
1258 #define REG_MHL_TMDS_0D_H       (REG_MHL_TMDS_BASE + 0x1B)
1259 #define REG_MHL_TMDS_0E_L       (REG_MHL_TMDS_BASE + 0x1C)
1260 #define REG_MHL_TMDS_0E_H       (REG_MHL_TMDS_BASE + 0x1D)
1261 #define REG_MHL_TMDS_0F_L       (REG_MHL_TMDS_BASE + 0x1E)
1262 #define REG_MHL_TMDS_0F_H       (REG_MHL_TMDS_BASE + 0x1F)
1263 #define REG_MHL_TMDS_10_L       (REG_MHL_TMDS_BASE + 0x20)
1264 #define REG_MHL_TMDS_10_H       (REG_MHL_TMDS_BASE + 0x21)
1265 #define REG_MHL_TMDS_11_L       (REG_MHL_TMDS_BASE + 0x22)
1266 #define REG_MHL_TMDS_11_H       (REG_MHL_TMDS_BASE + 0x23)
1267 #define REG_MHL_TMDS_12_L       (REG_MHL_TMDS_BASE + 0x24)
1268 #define REG_MHL_TMDS_12_H       (REG_MHL_TMDS_BASE + 0x25)
1269 #define REG_MHL_TMDS_13_L       (REG_MHL_TMDS_BASE + 0x26)
1270 #define REG_MHL_TMDS_13_H       (REG_MHL_TMDS_BASE + 0x27)
1271 #define REG_MHL_TMDS_14_L       (REG_MHL_TMDS_BASE + 0x28)
1272 #define REG_MHL_TMDS_14_H       (REG_MHL_TMDS_BASE + 0x29)
1273 #define REG_MHL_TMDS_15_L       (REG_MHL_TMDS_BASE + 0x2A)
1274 #define REG_MHL_TMDS_15_H       (REG_MHL_TMDS_BASE + 0x2B)
1275 #define REG_MHL_TMDS_16_L       (REG_MHL_TMDS_BASE + 0x2C)
1276 #define REG_MHL_TMDS_16_H       (REG_MHL_TMDS_BASE + 0x2D)
1277 #define REG_MHL_TMDS_17_L       (REG_MHL_TMDS_BASE + 0x2E)
1278 #define REG_MHL_TMDS_17_H       (REG_MHL_TMDS_BASE + 0x2F)
1279 #define REG_MHL_TMDS_18_L       (REG_MHL_TMDS_BASE + 0x30)
1280 #define REG_MHL_TMDS_18_H       (REG_MHL_TMDS_BASE + 0x31)
1281 #define REG_MHL_TMDS_19_L       (REG_MHL_TMDS_BASE + 0x32)
1282 #define REG_MHL_TMDS_19_H       (REG_MHL_TMDS_BASE + 0x33)
1283 #define REG_MHL_TMDS_1A_L       (REG_MHL_TMDS_BASE + 0x34)
1284 #define REG_MHL_TMDS_1A_H       (REG_MHL_TMDS_BASE + 0x35)
1285 #define REG_MHL_TMDS_1B_L       (REG_MHL_TMDS_BASE + 0x36)
1286 #define REG_MHL_TMDS_1B_H       (REG_MHL_TMDS_BASE + 0x37)
1287 #define REG_MHL_TMDS_1C_L       (REG_MHL_TMDS_BASE + 0x38)
1288 #define REG_MHL_TMDS_1C_H       (REG_MHL_TMDS_BASE + 0x39)
1289 #define REG_MHL_TMDS_1D_L       (REG_MHL_TMDS_BASE + 0x3A)
1290 #define REG_MHL_TMDS_1D_H       (REG_MHL_TMDS_BASE + 0x3B)
1291 #define REG_MHL_TMDS_1E_L       (REG_MHL_TMDS_BASE + 0x3C)
1292 #define REG_MHL_TMDS_1E_H       (REG_MHL_TMDS_BASE + 0x3D)
1293 #define REG_MHL_TMDS_1F_L       (REG_MHL_TMDS_BASE + 0x3E)
1294 #define REG_MHL_TMDS_1F_H       (REG_MHL_TMDS_BASE + 0x3F)
1295 #define REG_MHL_TMDS_20_L       (REG_MHL_TMDS_BASE + 0x40)
1296 #define REG_MHL_TMDS_20_H       (REG_MHL_TMDS_BASE + 0x41)
1297 #define REG_MHL_TMDS_21_L       (REG_MHL_TMDS_BASE + 0x42)
1298 #define REG_MHL_TMDS_21_H       (REG_MHL_TMDS_BASE + 0x43)
1299 #define REG_MHL_TMDS_22_L       (REG_MHL_TMDS_BASE + 0x44)
1300 #define REG_MHL_TMDS_22_H       (REG_MHL_TMDS_BASE + 0x45)
1301 #define REG_MHL_TMDS_23_L       (REG_MHL_TMDS_BASE + 0x46)
1302 #define REG_MHL_TMDS_23_H       (REG_MHL_TMDS_BASE + 0x47)
1303 #define REG_MHL_TMDS_24_L       (REG_MHL_TMDS_BASE + 0x48)
1304 #define REG_MHL_TMDS_24_H       (REG_MHL_TMDS_BASE + 0x49)
1305 #define REG_MHL_TMDS_25_L       (REG_MHL_TMDS_BASE + 0x4A)
1306 #define REG_MHL_TMDS_25_H       (REG_MHL_TMDS_BASE + 0x4B)
1307 #define REG_MHL_TMDS_26_L       (REG_MHL_TMDS_BASE + 0x4C)
1308 #define REG_MHL_TMDS_26_H       (REG_MHL_TMDS_BASE + 0x4D)
1309 #define REG_MHL_TMDS_27_L       (REG_MHL_TMDS_BASE + 0x4E)
1310 #define REG_MHL_TMDS_27_H       (REG_MHL_TMDS_BASE + 0x4F)
1311 #define REG_MHL_TMDS_28_L       (REG_MHL_TMDS_BASE + 0x50)
1312 #define REG_MHL_TMDS_28_H       (REG_MHL_TMDS_BASE + 0x51)
1313 #define REG_MHL_TMDS_29_L       (REG_MHL_TMDS_BASE + 0x52)
1314 #define REG_MHL_TMDS_29_H       (REG_MHL_TMDS_BASE + 0x53)
1315 #define REG_MHL_TMDS_2A_L       (REG_MHL_TMDS_BASE + 0x54)
1316 #define REG_MHL_TMDS_2A_H       (REG_MHL_TMDS_BASE + 0x55)
1317 #define REG_MHL_TMDS_2B_L       (REG_MHL_TMDS_BASE + 0x56)
1318 #define REG_MHL_TMDS_2B_H       (REG_MHL_TMDS_BASE + 0x57)
1319 #define REG_MHL_TMDS_2C_L       (REG_MHL_TMDS_BASE + 0x58)
1320 #define REG_MHL_TMDS_2C_H       (REG_MHL_TMDS_BASE + 0x59)
1321 #define REG_MHL_TMDS_2D_L       (REG_MHL_TMDS_BASE + 0x5A)
1322 #define REG_MHL_TMDS_2D_H       (REG_MHL_TMDS_BASE + 0x5B)
1323 #define REG_MHL_TMDS_2E_L       (REG_MHL_TMDS_BASE + 0x5C)
1324 #define REG_MHL_TMDS_2E_H       (REG_MHL_TMDS_BASE + 0x5D)
1325 #define REG_MHL_TMDS_2F_L       (REG_MHL_TMDS_BASE + 0x5E)
1326 #define REG_MHL_TMDS_2F_H       (REG_MHL_TMDS_BASE + 0x5F)
1327 #define REG_MHL_TMDS_30_L       (REG_MHL_TMDS_BASE + 0x60)
1328 #define REG_MHL_TMDS_30_H       (REG_MHL_TMDS_BASE + 0x61)
1329 #define REG_MHL_TMDS_31_L       (REG_MHL_TMDS_BASE + 0x62)
1330 #define REG_MHL_TMDS_31_H       (REG_MHL_TMDS_BASE + 0x63)
1331 #define REG_MHL_TMDS_32_L       (REG_MHL_TMDS_BASE + 0x64)
1332 #define REG_MHL_TMDS_32_H       (REG_MHL_TMDS_BASE + 0x65)
1333 #define REG_MHL_TMDS_33_L       (REG_MHL_TMDS_BASE + 0x66)
1334 #define REG_MHL_TMDS_33_H       (REG_MHL_TMDS_BASE + 0x67)
1335 #define REG_MHL_TMDS_34_L       (REG_MHL_TMDS_BASE + 0x68)
1336 #define REG_MHL_TMDS_34_H       (REG_MHL_TMDS_BASE + 0x69)
1337 #define REG_MHL_TMDS_35_L       (REG_MHL_TMDS_BASE + 0x6A)
1338 #define REG_MHL_TMDS_35_H       (REG_MHL_TMDS_BASE + 0x6B)
1339 #define REG_MHL_TMDS_36_L       (REG_MHL_TMDS_BASE + 0x6C)
1340 #define REG_MHL_TMDS_36_H       (REG_MHL_TMDS_BASE + 0x6D)
1341 #define REG_MHL_TMDS_37_L       (REG_MHL_TMDS_BASE + 0x6E)
1342 #define REG_MHL_TMDS_37_H       (REG_MHL_TMDS_BASE + 0x6F)
1343 #define REG_MHL_TMDS_38_L       (REG_MHL_TMDS_BASE + 0x70)
1344 #define REG_MHL_TMDS_38_H       (REG_MHL_TMDS_BASE + 0x71)
1345 #define REG_MHL_TMDS_39_L       (REG_MHL_TMDS_BASE + 0x72)
1346 #define REG_MHL_TMDS_39_H       (REG_MHL_TMDS_BASE + 0x73)
1347 #define REG_MHL_TMDS_3A_L       (REG_MHL_TMDS_BASE + 0x74)
1348 #define REG_MHL_TMDS_3A_H       (REG_MHL_TMDS_BASE + 0x75)
1349 #define REG_MHL_TMDS_3B_L       (REG_MHL_TMDS_BASE + 0x76)
1350 #define REG_MHL_TMDS_3B_H       (REG_MHL_TMDS_BASE + 0x77)
1351 #define REG_MHL_TMDS_3C_L       (REG_MHL_TMDS_BASE + 0x78)
1352 #define REG_MHL_TMDS_3C_H       (REG_MHL_TMDS_BASE + 0x79)
1353 #define REG_MHL_TMDS_3D_L       (REG_MHL_TMDS_BASE + 0x7A)
1354 #define REG_MHL_TMDS_3D_H       (REG_MHL_TMDS_BASE + 0x7B)
1355 #define REG_MHL_TMDS_3E_L       (REG_MHL_TMDS_BASE + 0x7C)
1356 #define REG_MHL_TMDS_3E_H       (REG_MHL_TMDS_BASE + 0x7D)
1357 #define REG_MHL_TMDS_3F_L       (REG_MHL_TMDS_BASE + 0x7E)
1358 #define REG_MHL_TMDS_3F_H       (REG_MHL_TMDS_BASE + 0x7F)
1359 #define REG_MHL_TMDS_40_L       (REG_MHL_TMDS_BASE + 0x80)
1360 #define REG_MHL_TMDS_40_H       (REG_MHL_TMDS_BASE + 0x81)
1361 #define REG_MHL_TMDS_41_L       (REG_MHL_TMDS_BASE + 0x82)
1362 #define REG_MHL_TMDS_41_H       (REG_MHL_TMDS_BASE + 0x83)
1363 #define REG_MHL_TMDS_42_L       (REG_MHL_TMDS_BASE + 0x84)
1364 #define REG_MHL_TMDS_42_H       (REG_MHL_TMDS_BASE + 0x85)
1365 #define REG_MHL_TMDS_43_L       (REG_MHL_TMDS_BASE + 0x86)
1366 #define REG_MHL_TMDS_43_H       (REG_MHL_TMDS_BASE + 0x87)
1367 #define REG_MHL_TMDS_44_L       (REG_MHL_TMDS_BASE + 0x88)
1368 #define REG_MHL_TMDS_44_H       (REG_MHL_TMDS_BASE + 0x89)
1369 #define REG_MHL_TMDS_45_L       (REG_MHL_TMDS_BASE + 0x8A)
1370 #define REG_MHL_TMDS_45_H       (REG_MHL_TMDS_BASE + 0x8B)
1371 #define REG_MHL_TMDS_46_L       (REG_MHL_TMDS_BASE + 0x8C)
1372 #define REG_MHL_TMDS_46_H       (REG_MHL_TMDS_BASE + 0x8D)
1373 #define REG_MHL_TMDS_47_L       (REG_MHL_TMDS_BASE + 0x8E)
1374 #define REG_MHL_TMDS_47_H       (REG_MHL_TMDS_BASE + 0x8F)
1375 #define REG_MHL_TMDS_48_L       (REG_MHL_TMDS_BASE + 0x90)
1376 #define REG_MHL_TMDS_48_H       (REG_MHL_TMDS_BASE + 0x91)
1377 #define REG_MHL_TMDS_49_L       (REG_MHL_TMDS_BASE + 0x92)
1378 #define REG_MHL_TMDS_49_H       (REG_MHL_TMDS_BASE + 0x93)
1379 #define REG_MHL_TMDS_4A_L       (REG_MHL_TMDS_BASE + 0x94)
1380 #define REG_MHL_TMDS_4A_H       (REG_MHL_TMDS_BASE + 0x95)
1381 #define REG_MHL_TMDS_4B_L       (REG_MHL_TMDS_BASE + 0x96)
1382 #define REG_MHL_TMDS_4B_H       (REG_MHL_TMDS_BASE + 0x97)
1383 #define REG_MHL_TMDS_4C_L       (REG_MHL_TMDS_BASE + 0x98)
1384 #define REG_MHL_TMDS_4C_H       (REG_MHL_TMDS_BASE + 0x99)
1385 #define REG_MHL_TMDS_4D_L       (REG_MHL_TMDS_BASE + 0x9A)
1386 #define REG_MHL_TMDS_4D_H       (REG_MHL_TMDS_BASE + 0x9B)
1387 #define REG_MHL_TMDS_4E_L       (REG_MHL_TMDS_BASE + 0x9C)
1388 #define REG_MHL_TMDS_4E_H       (REG_MHL_TMDS_BASE + 0x9D)
1389 #define REG_MHL_TMDS_4F_L       (REG_MHL_TMDS_BASE + 0x9E)
1390 #define REG_MHL_TMDS_4F_H       (REG_MHL_TMDS_BASE + 0x9F)
1391 #define REG_MHL_TMDS_50_L       (REG_MHL_TMDS_BASE + 0xA0)
1392 #define REG_MHL_TMDS_50_H       (REG_MHL_TMDS_BASE + 0xA1)
1393 #define REG_MHL_TMDS_51_L       (REG_MHL_TMDS_BASE + 0xA2)
1394 #define REG_MHL_TMDS_51_H       (REG_MHL_TMDS_BASE + 0xA3)
1395 #define REG_MHL_TMDS_52_L       (REG_MHL_TMDS_BASE + 0xA4)
1396 #define REG_MHL_TMDS_52_H       (REG_MHL_TMDS_BASE + 0xA5)
1397 #define REG_MHL_TMDS_53_L       (REG_MHL_TMDS_BASE + 0xA6)
1398 #define REG_MHL_TMDS_53_H       (REG_MHL_TMDS_BASE + 0xA7)
1399 #define REG_MHL_TMDS_54_L       (REG_MHL_TMDS_BASE + 0xA8)
1400 #define REG_MHL_TMDS_54_H       (REG_MHL_TMDS_BASE + 0xA9)
1401 #define REG_MHL_TMDS_55_L       (REG_MHL_TMDS_BASE + 0xAA)
1402 #define REG_MHL_TMDS_55_H       (REG_MHL_TMDS_BASE + 0xAB)
1403 #define REG_MHL_TMDS_56_L       (REG_MHL_TMDS_BASE + 0xAC)
1404 #define REG_MHL_TMDS_56_H       (REG_MHL_TMDS_BASE + 0xAD)
1405 #define REG_MHL_TMDS_57_L       (REG_MHL_TMDS_BASE + 0xAE)
1406 #define REG_MHL_TMDS_57_H       (REG_MHL_TMDS_BASE + 0xAF)
1407 #define REG_MHL_TMDS_58_L       (REG_MHL_TMDS_BASE + 0xB0)
1408 #define REG_MHL_TMDS_58_H       (REG_MHL_TMDS_BASE + 0xB1)
1409 #define REG_MHL_TMDS_59_L       (REG_MHL_TMDS_BASE + 0xB2)
1410 #define REG_MHL_TMDS_59_H       (REG_MHL_TMDS_BASE + 0xB3)
1411 #define REG_MHL_TMDS_5A_L       (REG_MHL_TMDS_BASE + 0xB4)
1412 #define REG_MHL_TMDS_5A_H       (REG_MHL_TMDS_BASE + 0xB5)
1413 #define REG_MHL_TMDS_5B_L       (REG_MHL_TMDS_BASE + 0xB6)
1414 #define REG_MHL_TMDS_5B_H       (REG_MHL_TMDS_BASE + 0xB7)
1415 #define REG_MHL_TMDS_5C_L       (REG_MHL_TMDS_BASE + 0xB8)
1416 #define REG_MHL_TMDS_5C_H       (REG_MHL_TMDS_BASE + 0xB9)
1417 #define REG_MHL_TMDS_5D_L       (REG_MHL_TMDS_BASE + 0xBA)
1418 #define REG_MHL_TMDS_5D_H       (REG_MHL_TMDS_BASE + 0xBB)
1419 #define REG_MHL_TMDS_5E_L       (REG_MHL_TMDS_BASE + 0xBC)
1420 #define REG_MHL_TMDS_5E_H       (REG_MHL_TMDS_BASE + 0xBD)
1421 #define REG_MHL_TMDS_5F_L       (REG_MHL_TMDS_BASE + 0xBE)
1422 #define REG_MHL_TMDS_5F_H       (REG_MHL_TMDS_BASE + 0xBF)
1423 #define REG_MHL_TMDS_60_L       (REG_MHL_TMDS_BASE + 0xC0)
1424 #define REG_MHL_TMDS_60_H       (REG_MHL_TMDS_BASE + 0xC1)
1425 #define REG_MHL_TMDS_61_L       (REG_MHL_TMDS_BASE + 0xC2)
1426 #define REG_MHL_TMDS_61_H       (REG_MHL_TMDS_BASE + 0xC3)
1427 #define REG_MHL_TMDS_62_L       (REG_MHL_TMDS_BASE + 0xC4)
1428 #define REG_MHL_TMDS_62_H       (REG_MHL_TMDS_BASE + 0xC5)
1429 #define REG_MHL_TMDS_63_L       (REG_MHL_TMDS_BASE + 0xC6)
1430 #define REG_MHL_TMDS_63_H       (REG_MHL_TMDS_BASE + 0xC7)
1431 #define REG_MHL_TMDS_64_L       (REG_MHL_TMDS_BASE + 0xC8)
1432 #define REG_MHL_TMDS_64_H       (REG_MHL_TMDS_BASE + 0xC9)
1433 #define REG_MHL_TMDS_65_L       (REG_MHL_TMDS_BASE + 0xCA)
1434 #define REG_MHL_TMDS_65_H       (REG_MHL_TMDS_BASE + 0xCB)
1435 #define REG_MHL_TMDS_66_L       (REG_MHL_TMDS_BASE + 0xCC)
1436 #define REG_MHL_TMDS_66_H       (REG_MHL_TMDS_BASE + 0xCD)
1437 #define REG_MHL_TMDS_67_L       (REG_MHL_TMDS_BASE + 0xCE)
1438 #define REG_MHL_TMDS_67_H       (REG_MHL_TMDS_BASE + 0xCF)
1439 #define REG_MHL_TMDS_68_L       (REG_MHL_TMDS_BASE + 0xD0)
1440 #define REG_MHL_TMDS_68_H       (REG_MHL_TMDS_BASE + 0xD1)
1441 #define REG_MHL_TMDS_69_L       (REG_MHL_TMDS_BASE + 0xD2)
1442 #define REG_MHL_TMDS_69_H       (REG_MHL_TMDS_BASE + 0xD3)
1443 #define REG_MHL_TMDS_6A_L       (REG_MHL_TMDS_BASE + 0xD4)
1444 #define REG_MHL_TMDS_6A_H       (REG_MHL_TMDS_BASE + 0xD5)
1445 #define REG_MHL_TMDS_6B_L       (REG_MHL_TMDS_BASE + 0xD6)
1446 #define REG_MHL_TMDS_6B_H       (REG_MHL_TMDS_BASE + 0xD7)
1447 #define REG_MHL_TMDS_6C_L       (REG_MHL_TMDS_BASE + 0xD8)
1448 #define REG_MHL_TMDS_6C_H       (REG_MHL_TMDS_BASE + 0xD9)
1449 #define REG_MHL_TMDS_6D_L       (REG_MHL_TMDS_BASE + 0xDA)
1450 #define REG_MHL_TMDS_6D_H       (REG_MHL_TMDS_BASE + 0xDB)
1451 #define REG_MHL_TMDS_6E_L       (REG_MHL_TMDS_BASE + 0xDC)
1452 #define REG_MHL_TMDS_6E_H       (REG_MHL_TMDS_BASE + 0xDD)
1453 #define REG_MHL_TMDS_6F_L       (REG_MHL_TMDS_BASE + 0xDE)
1454 #define REG_MHL_TMDS_6F_H       (REG_MHL_TMDS_BASE + 0xDF)
1455 #define REG_MHL_TMDS_70_L       (REG_MHL_TMDS_BASE + 0xE0)
1456 #define REG_MHL_TMDS_70_H       (REG_MHL_TMDS_BASE + 0xE1)
1457 #define REG_MHL_TMDS_71_L       (REG_MHL_TMDS_BASE + 0xE2)
1458 #define REG_MHL_TMDS_71_H       (REG_MHL_TMDS_BASE + 0xE3)
1459 #define REG_MHL_TMDS_72_L       (REG_MHL_TMDS_BASE + 0xE4)
1460 #define REG_MHL_TMDS_72_H       (REG_MHL_TMDS_BASE + 0xE5)
1461 #define REG_MHL_TMDS_73_L       (REG_MHL_TMDS_BASE + 0xE6)
1462 #define REG_MHL_TMDS_73_H       (REG_MHL_TMDS_BASE + 0xE7)
1463 #define REG_MHL_TMDS_74_L       (REG_MHL_TMDS_BASE + 0xE8)
1464 #define REG_MHL_TMDS_74_H       (REG_MHL_TMDS_BASE + 0xE9)
1465 #define REG_MHL_TMDS_75_L       (REG_MHL_TMDS_BASE + 0xEA)
1466 #define REG_MHL_TMDS_75_H       (REG_MHL_TMDS_BASE + 0xEB)
1467 #define REG_MHL_TMDS_76_L       (REG_MHL_TMDS_BASE + 0xEC)
1468 #define REG_MHL_TMDS_76_H       (REG_MHL_TMDS_BASE + 0xED)
1469 #define REG_MHL_TMDS_77_L       (REG_MHL_TMDS_BASE + 0xEE)
1470 #define REG_MHL_TMDS_77_H       (REG_MHL_TMDS_BASE + 0xEF)
1471 #define REG_MHL_TMDS_78_L       (REG_MHL_TMDS_BASE + 0xF0)
1472 #define REG_MHL_TMDS_78_H       (REG_MHL_TMDS_BASE + 0xF1)
1473 #define REG_MHL_TMDS_79_L       (REG_MHL_TMDS_BASE + 0xF2)
1474 #define REG_MHL_TMDS_79_H       (REG_MHL_TMDS_BASE + 0xF3)
1475 #define REG_MHL_TMDS_7A_L       (REG_MHL_TMDS_BASE + 0xF4)
1476 #define REG_MHL_TMDS_7A_H       (REG_MHL_TMDS_BASE + 0xF5)
1477 #define REG_MHL_TMDS_7B_L       (REG_MHL_TMDS_BASE + 0xF6)
1478 #define REG_MHL_TMDS_7B_H       (REG_MHL_TMDS_BASE + 0xF7)
1479 #define REG_MHL_TMDS_7C_L       (REG_MHL_TMDS_BASE + 0xF8)
1480 #define REG_MHL_TMDS_7C_H       (REG_MHL_TMDS_BASE + 0xF9)
1481 #define REG_MHL_TMDS_7D_L       (REG_MHL_TMDS_BASE + 0xFA)
1482 #define REG_MHL_TMDS_7D_H       (REG_MHL_TMDS_BASE + 0xFB)
1483 #define REG_MHL_TMDS_7E_L       (REG_MHL_TMDS_BASE + 0xFC)
1484 #define REG_MHL_TMDS_7E_H       (REG_MHL_TMDS_BASE + 0xFD)
1485 #define REG_MHL_TMDS_7F_L       (REG_MHL_TMDS_BASE + 0xFE)
1486 #define REG_MHL_TMDS_7F_H       (REG_MHL_TMDS_BASE + 0xFF)
1487 
1488 //=============================================================
1489 
1490 // CHIP
1491 #define REG_CHIP_0B_L                (REG_CHIP_BASE + 0x16)
1492 #define REG_CHIP_0B_H                (REG_CHIP_BASE + 0x17)
1493 #define REG_CHIP_28_L                (REG_CHIP_BASE + 0x50)
1494 
1495 //CHIP_GPIO1
1496 #define REG_CHIP_GPIO1_10_L          (REG_CHIP_GPIO1_BASE + 0x20)
1497 
1498 // COMBO_PHY0_P0
1499 #define REG_COMBO_PHY0_P0_00_L       (REG_COMBO_PHY0_P0_BASE + 0x00)
1500 #define REG_COMBO_PHY0_P0_00_H       (REG_COMBO_PHY0_P0_BASE + 0x01)
1501 #define REG_COMBO_PHY0_P0_01_L       (REG_COMBO_PHY0_P0_BASE + 0x02)
1502 #define REG_COMBO_PHY0_P0_01_H       (REG_COMBO_PHY0_P0_BASE + 0x03)
1503 #define REG_COMBO_PHY0_P0_02_L       (REG_COMBO_PHY0_P0_BASE + 0x04)
1504 #define REG_COMBO_PHY0_P0_02_H       (REG_COMBO_PHY0_P0_BASE + 0x05)
1505 #define REG_COMBO_PHY0_P0_03_L       (REG_COMBO_PHY0_P0_BASE + 0x06)
1506 #define REG_COMBO_PHY0_P0_03_H       (REG_COMBO_PHY0_P0_BASE + 0x07)
1507 #define REG_COMBO_PHY0_P0_04_L       (REG_COMBO_PHY0_P0_BASE + 0x08)
1508 #define REG_COMBO_PHY0_P0_04_H       (REG_COMBO_PHY0_P0_BASE + 0x09)
1509 #define REG_COMBO_PHY0_P0_05_L       (REG_COMBO_PHY0_P0_BASE + 0x0A)
1510 #define REG_COMBO_PHY0_P0_05_H       (REG_COMBO_PHY0_P0_BASE + 0x0B)
1511 #define REG_COMBO_PHY0_P0_06_L       (REG_COMBO_PHY0_P0_BASE + 0x0C)
1512 #define REG_COMBO_PHY0_P0_06_H       (REG_COMBO_PHY0_P0_BASE + 0x0D)
1513 #define REG_COMBO_PHY0_P0_07_L       (REG_COMBO_PHY0_P0_BASE + 0x0E)
1514 #define REG_COMBO_PHY0_P0_07_H       (REG_COMBO_PHY0_P0_BASE + 0x0F)
1515 #define REG_COMBO_PHY0_P0_08_L       (REG_COMBO_PHY0_P0_BASE + 0x10)
1516 #define REG_COMBO_PHY0_P0_08_H       (REG_COMBO_PHY0_P0_BASE + 0x11)
1517 #define REG_COMBO_PHY0_P0_09_L       (REG_COMBO_PHY0_P0_BASE + 0x12)
1518 #define REG_COMBO_PHY0_P0_09_H       (REG_COMBO_PHY0_P0_BASE + 0x13)
1519 #define REG_COMBO_PHY0_P0_0A_L       (REG_COMBO_PHY0_P0_BASE + 0x14)
1520 #define REG_COMBO_PHY0_P0_0A_H       (REG_COMBO_PHY0_P0_BASE + 0x15)
1521 #define REG_COMBO_PHY0_P0_0B_L       (REG_COMBO_PHY0_P0_BASE + 0x16)
1522 #define REG_COMBO_PHY0_P0_0B_H       (REG_COMBO_PHY0_P0_BASE + 0x17)
1523 #define REG_COMBO_PHY0_P0_0C_L       (REG_COMBO_PHY0_P0_BASE + 0x18)
1524 #define REG_COMBO_PHY0_P0_0C_H       (REG_COMBO_PHY0_P0_BASE + 0x19)
1525 #define REG_COMBO_PHY0_P0_0D_L       (REG_COMBO_PHY0_P0_BASE + 0x1A)
1526 #define REG_COMBO_PHY0_P0_0D_H       (REG_COMBO_PHY0_P0_BASE + 0x1B)
1527 #define REG_COMBO_PHY0_P0_0E_L       (REG_COMBO_PHY0_P0_BASE + 0x1C)
1528 #define REG_COMBO_PHY0_P0_0E_H       (REG_COMBO_PHY0_P0_BASE + 0x1D)
1529 #define REG_COMBO_PHY0_P0_0F_L       (REG_COMBO_PHY0_P0_BASE + 0x1E)
1530 #define REG_COMBO_PHY0_P0_0F_H       (REG_COMBO_PHY0_P0_BASE + 0x1F)
1531 #define REG_COMBO_PHY0_P0_10_L       (REG_COMBO_PHY0_P0_BASE + 0x20)
1532 #define REG_COMBO_PHY0_P0_10_H       (REG_COMBO_PHY0_P0_BASE + 0x21)
1533 #define REG_COMBO_PHY0_P0_11_L       (REG_COMBO_PHY0_P0_BASE + 0x22)
1534 #define REG_COMBO_PHY0_P0_11_H       (REG_COMBO_PHY0_P0_BASE + 0x23)
1535 #define REG_COMBO_PHY0_P0_12_L       (REG_COMBO_PHY0_P0_BASE + 0x24)
1536 #define REG_COMBO_PHY0_P0_12_H       (REG_COMBO_PHY0_P0_BASE + 0x25)
1537 #define REG_COMBO_PHY0_P0_13_L       (REG_COMBO_PHY0_P0_BASE + 0x26)
1538 #define REG_COMBO_PHY0_P0_13_H       (REG_COMBO_PHY0_P0_BASE + 0x27)
1539 #define REG_COMBO_PHY0_P0_14_L       (REG_COMBO_PHY0_P0_BASE + 0x28)
1540 #define REG_COMBO_PHY0_P0_14_H       (REG_COMBO_PHY0_P0_BASE + 0x29)
1541 #define REG_COMBO_PHY0_P0_15_L       (REG_COMBO_PHY0_P0_BASE + 0x2A)
1542 #define REG_COMBO_PHY0_P0_15_H       (REG_COMBO_PHY0_P0_BASE + 0x2B)
1543 #define REG_COMBO_PHY0_P0_16_L       (REG_COMBO_PHY0_P0_BASE + 0x2C)
1544 #define REG_COMBO_PHY0_P0_16_H       (REG_COMBO_PHY0_P0_BASE + 0x2D)
1545 #define REG_COMBO_PHY0_P0_17_L       (REG_COMBO_PHY0_P0_BASE + 0x2E)
1546 #define REG_COMBO_PHY0_P0_17_H       (REG_COMBO_PHY0_P0_BASE + 0x2F)
1547 #define REG_COMBO_PHY0_P0_18_L       (REG_COMBO_PHY0_P0_BASE + 0x30)
1548 #define REG_COMBO_PHY0_P0_18_H       (REG_COMBO_PHY0_P0_BASE + 0x31)
1549 #define REG_COMBO_PHY0_P0_19_L       (REG_COMBO_PHY0_P0_BASE + 0x32)
1550 #define REG_COMBO_PHY0_P0_19_H       (REG_COMBO_PHY0_P0_BASE + 0x33)
1551 #define REG_COMBO_PHY0_P0_1A_L       (REG_COMBO_PHY0_P0_BASE + 0x34)
1552 #define REG_COMBO_PHY0_P0_1A_H       (REG_COMBO_PHY0_P0_BASE + 0x35)
1553 #define REG_COMBO_PHY0_P0_1B_L       (REG_COMBO_PHY0_P0_BASE + 0x36)
1554 #define REG_COMBO_PHY0_P0_1B_H       (REG_COMBO_PHY0_P0_BASE + 0x37)
1555 #define REG_COMBO_PHY0_P0_1C_L       (REG_COMBO_PHY0_P0_BASE + 0x38)
1556 #define REG_COMBO_PHY0_P0_1C_H       (REG_COMBO_PHY0_P0_BASE + 0x39)
1557 #define REG_COMBO_PHY0_P0_1D_L       (REG_COMBO_PHY0_P0_BASE + 0x3A)
1558 #define REG_COMBO_PHY0_P0_1D_H       (REG_COMBO_PHY0_P0_BASE + 0x3B)
1559 #define REG_COMBO_PHY0_P0_1E_L       (REG_COMBO_PHY0_P0_BASE + 0x3C)
1560 #define REG_COMBO_PHY0_P0_1E_H       (REG_COMBO_PHY0_P0_BASE + 0x3D)
1561 #define REG_COMBO_PHY0_P0_1F_L       (REG_COMBO_PHY0_P0_BASE + 0x3E)
1562 #define REG_COMBO_PHY0_P0_1F_H       (REG_COMBO_PHY0_P0_BASE + 0x3F)
1563 #define REG_COMBO_PHY0_P0_20_L       (REG_COMBO_PHY0_P0_BASE + 0x40)
1564 #define REG_COMBO_PHY0_P0_20_H       (REG_COMBO_PHY0_P0_BASE + 0x41)
1565 #define REG_COMBO_PHY0_P0_21_L       (REG_COMBO_PHY0_P0_BASE + 0x42)
1566 #define REG_COMBO_PHY0_P0_21_H       (REG_COMBO_PHY0_P0_BASE + 0x43)
1567 #define REG_COMBO_PHY0_P0_22_L       (REG_COMBO_PHY0_P0_BASE + 0x44)
1568 #define REG_COMBO_PHY0_P0_22_H       (REG_COMBO_PHY0_P0_BASE + 0x45)
1569 #define REG_COMBO_PHY0_P0_23_L       (REG_COMBO_PHY0_P0_BASE + 0x46)
1570 #define REG_COMBO_PHY0_P0_23_H       (REG_COMBO_PHY0_P0_BASE + 0x47)
1571 #define REG_COMBO_PHY0_P0_24_L       (REG_COMBO_PHY0_P0_BASE + 0x48)
1572 #define REG_COMBO_PHY0_P0_24_H       (REG_COMBO_PHY0_P0_BASE + 0x49)
1573 #define REG_COMBO_PHY0_P0_25_L       (REG_COMBO_PHY0_P0_BASE + 0x4A)
1574 #define REG_COMBO_PHY0_P0_25_H       (REG_COMBO_PHY0_P0_BASE + 0x4B)
1575 #define REG_COMBO_PHY0_P0_26_L       (REG_COMBO_PHY0_P0_BASE + 0x4C)
1576 #define REG_COMBO_PHY0_P0_26_H       (REG_COMBO_PHY0_P0_BASE + 0x4D)
1577 #define REG_COMBO_PHY0_P0_27_L       (REG_COMBO_PHY0_P0_BASE + 0x4E)
1578 #define REG_COMBO_PHY0_P0_27_H       (REG_COMBO_PHY0_P0_BASE + 0x4F)
1579 #define REG_COMBO_PHY0_P0_28_L       (REG_COMBO_PHY0_P0_BASE + 0x50)
1580 #define REG_COMBO_PHY0_P0_28_H       (REG_COMBO_PHY0_P0_BASE + 0x51)
1581 #define REG_COMBO_PHY0_P0_29_L       (REG_COMBO_PHY0_P0_BASE + 0x52)
1582 #define REG_COMBO_PHY0_P0_29_H       (REG_COMBO_PHY0_P0_BASE + 0x53)
1583 #define REG_COMBO_PHY0_P0_2A_L       (REG_COMBO_PHY0_P0_BASE + 0x54)
1584 #define REG_COMBO_PHY0_P0_2A_H       (REG_COMBO_PHY0_P0_BASE + 0x55)
1585 #define REG_COMBO_PHY0_P0_2B_L       (REG_COMBO_PHY0_P0_BASE + 0x56)
1586 #define REG_COMBO_PHY0_P0_2B_H       (REG_COMBO_PHY0_P0_BASE + 0x57)
1587 #define REG_COMBO_PHY0_P0_2C_L       (REG_COMBO_PHY0_P0_BASE + 0x58)
1588 #define REG_COMBO_PHY0_P0_2C_H       (REG_COMBO_PHY0_P0_BASE + 0x59)
1589 #define REG_COMBO_PHY0_P0_2D_L       (REG_COMBO_PHY0_P0_BASE + 0x5A)
1590 #define REG_COMBO_PHY0_P0_2D_H       (REG_COMBO_PHY0_P0_BASE + 0x5B)
1591 #define REG_COMBO_PHY0_P0_2E_L       (REG_COMBO_PHY0_P0_BASE + 0x5C)
1592 #define REG_COMBO_PHY0_P0_2E_H       (REG_COMBO_PHY0_P0_BASE + 0x5D)
1593 #define REG_COMBO_PHY0_P0_2F_L       (REG_COMBO_PHY0_P0_BASE + 0x5E)
1594 #define REG_COMBO_PHY0_P0_2F_H       (REG_COMBO_PHY0_P0_BASE + 0x5F)
1595 #define REG_COMBO_PHY0_P0_30_L       (REG_COMBO_PHY0_P0_BASE + 0x60)
1596 #define REG_COMBO_PHY0_P0_30_H       (REG_COMBO_PHY0_P0_BASE + 0x61)
1597 #define REG_COMBO_PHY0_P0_31_L       (REG_COMBO_PHY0_P0_BASE + 0x62)
1598 #define REG_COMBO_PHY0_P0_31_H       (REG_COMBO_PHY0_P0_BASE + 0x63)
1599 #define REG_COMBO_PHY0_P0_32_L       (REG_COMBO_PHY0_P0_BASE + 0x64)
1600 #define REG_COMBO_PHY0_P0_32_H       (REG_COMBO_PHY0_P0_BASE + 0x65)
1601 #define REG_COMBO_PHY0_P0_33_L       (REG_COMBO_PHY0_P0_BASE + 0x66)
1602 #define REG_COMBO_PHY0_P0_33_H       (REG_COMBO_PHY0_P0_BASE + 0x67)
1603 #define REG_COMBO_PHY0_P0_34_L       (REG_COMBO_PHY0_P0_BASE + 0x68)
1604 #define REG_COMBO_PHY0_P0_34_H       (REG_COMBO_PHY0_P0_BASE + 0x69)
1605 #define REG_COMBO_PHY0_P0_35_L       (REG_COMBO_PHY0_P0_BASE + 0x6A)
1606 #define REG_COMBO_PHY0_P0_35_H       (REG_COMBO_PHY0_P0_BASE + 0x6B)
1607 #define REG_COMBO_PHY0_P0_36_L       (REG_COMBO_PHY0_P0_BASE + 0x6C)
1608 #define REG_COMBO_PHY0_P0_36_H       (REG_COMBO_PHY0_P0_BASE + 0x6D)
1609 #define REG_COMBO_PHY0_P0_37_L       (REG_COMBO_PHY0_P0_BASE + 0x6E)
1610 #define REG_COMBO_PHY0_P0_37_H       (REG_COMBO_PHY0_P0_BASE + 0x6F)
1611 #define REG_COMBO_PHY0_P0_38_L       (REG_COMBO_PHY0_P0_BASE + 0x70)
1612 #define REG_COMBO_PHY0_P0_38_H       (REG_COMBO_PHY0_P0_BASE + 0x71)
1613 #define REG_COMBO_PHY0_P0_39_L       (REG_COMBO_PHY0_P0_BASE + 0x72)
1614 #define REG_COMBO_PHY0_P0_39_H       (REG_COMBO_PHY0_P0_BASE + 0x73)
1615 #define REG_COMBO_PHY0_P0_3A_L       (REG_COMBO_PHY0_P0_BASE + 0x74)
1616 #define REG_COMBO_PHY0_P0_3A_H       (REG_COMBO_PHY0_P0_BASE + 0x75)
1617 #define REG_COMBO_PHY0_P0_3B_L       (REG_COMBO_PHY0_P0_BASE + 0x76)
1618 #define REG_COMBO_PHY0_P0_3B_H       (REG_COMBO_PHY0_P0_BASE + 0x77)
1619 #define REG_COMBO_PHY0_P0_3C_L       (REG_COMBO_PHY0_P0_BASE + 0x78)
1620 #define REG_COMBO_PHY0_P0_3C_H       (REG_COMBO_PHY0_P0_BASE + 0x79)
1621 #define REG_COMBO_PHY0_P0_3D_L       (REG_COMBO_PHY0_P0_BASE + 0x7A)
1622 #define REG_COMBO_PHY0_P0_3D_H       (REG_COMBO_PHY0_P0_BASE + 0x7B)
1623 #define REG_COMBO_PHY0_P0_3E_L       (REG_COMBO_PHY0_P0_BASE + 0x7C)
1624 #define REG_COMBO_PHY0_P0_3E_H       (REG_COMBO_PHY0_P0_BASE + 0x7D)
1625 #define REG_COMBO_PHY0_P0_3F_L       (REG_COMBO_PHY0_P0_BASE + 0x7E)
1626 #define REG_COMBO_PHY0_P0_3F_H       (REG_COMBO_PHY0_P0_BASE + 0x7F)
1627 #define REG_COMBO_PHY0_P0_40_L       (REG_COMBO_PHY0_P0_BASE + 0x80)
1628 #define REG_COMBO_PHY0_P0_40_H       (REG_COMBO_PHY0_P0_BASE + 0x81)
1629 #define REG_COMBO_PHY0_P0_41_L       (REG_COMBO_PHY0_P0_BASE + 0x82)
1630 #define REG_COMBO_PHY0_P0_41_H       (REG_COMBO_PHY0_P0_BASE + 0x83)
1631 #define REG_COMBO_PHY0_P0_42_L       (REG_COMBO_PHY0_P0_BASE + 0x84)
1632 #define REG_COMBO_PHY0_P0_42_H       (REG_COMBO_PHY0_P0_BASE + 0x85)
1633 #define REG_COMBO_PHY0_P0_43_L       (REG_COMBO_PHY0_P0_BASE + 0x86)
1634 #define REG_COMBO_PHY0_P0_43_H       (REG_COMBO_PHY0_P0_BASE + 0x87)
1635 #define REG_COMBO_PHY0_P0_44_L       (REG_COMBO_PHY0_P0_BASE + 0x88)
1636 #define REG_COMBO_PHY0_P0_44_H       (REG_COMBO_PHY0_P0_BASE + 0x89)
1637 #define REG_COMBO_PHY0_P0_45_L       (REG_COMBO_PHY0_P0_BASE + 0x8A)
1638 #define REG_COMBO_PHY0_P0_45_H       (REG_COMBO_PHY0_P0_BASE + 0x8B)
1639 #define REG_COMBO_PHY0_P0_46_L       (REG_COMBO_PHY0_P0_BASE + 0x8C)
1640 #define REG_COMBO_PHY0_P0_46_H       (REG_COMBO_PHY0_P0_BASE + 0x8D)
1641 #define REG_COMBO_PHY0_P0_47_L       (REG_COMBO_PHY0_P0_BASE + 0x8E)
1642 #define REG_COMBO_PHY0_P0_47_H       (REG_COMBO_PHY0_P0_BASE + 0x8F)
1643 #define REG_COMBO_PHY0_P0_48_L       (REG_COMBO_PHY0_P0_BASE + 0x90)
1644 #define REG_COMBO_PHY0_P0_48_H       (REG_COMBO_PHY0_P0_BASE + 0x91)
1645 #define REG_COMBO_PHY0_P0_49_L       (REG_COMBO_PHY0_P0_BASE + 0x92)
1646 #define REG_COMBO_PHY0_P0_49_H       (REG_COMBO_PHY0_P0_BASE + 0x93)
1647 #define REG_COMBO_PHY0_P0_4A_L       (REG_COMBO_PHY0_P0_BASE + 0x94)
1648 #define REG_COMBO_PHY0_P0_4A_H       (REG_COMBO_PHY0_P0_BASE + 0x95)
1649 #define REG_COMBO_PHY0_P0_4B_L       (REG_COMBO_PHY0_P0_BASE + 0x96)
1650 #define REG_COMBO_PHY0_P0_4B_H       (REG_COMBO_PHY0_P0_BASE + 0x97)
1651 #define REG_COMBO_PHY0_P0_4C_L       (REG_COMBO_PHY0_P0_BASE + 0x98)
1652 #define REG_COMBO_PHY0_P0_4C_H       (REG_COMBO_PHY0_P0_BASE + 0x99)
1653 #define REG_COMBO_PHY0_P0_4D_L       (REG_COMBO_PHY0_P0_BASE + 0x9A)
1654 #define REG_COMBO_PHY0_P0_4D_H       (REG_COMBO_PHY0_P0_BASE + 0x9B)
1655 #define REG_COMBO_PHY0_P0_4E_L       (REG_COMBO_PHY0_P0_BASE + 0x9C)
1656 #define REG_COMBO_PHY0_P0_4E_H       (REG_COMBO_PHY0_P0_BASE + 0x9D)
1657 #define REG_COMBO_PHY0_P0_4F_L       (REG_COMBO_PHY0_P0_BASE + 0x9E)
1658 #define REG_COMBO_PHY0_P0_4F_H       (REG_COMBO_PHY0_P0_BASE + 0x9F)
1659 #define REG_COMBO_PHY0_P0_50_L       (REG_COMBO_PHY0_P0_BASE + 0xA0)
1660 #define REG_COMBO_PHY0_P0_50_H       (REG_COMBO_PHY0_P0_BASE + 0xA1)
1661 #define REG_COMBO_PHY0_P0_51_L       (REG_COMBO_PHY0_P0_BASE + 0xA2)
1662 #define REG_COMBO_PHY0_P0_51_H       (REG_COMBO_PHY0_P0_BASE + 0xA3)
1663 #define REG_COMBO_PHY0_P0_52_L       (REG_COMBO_PHY0_P0_BASE + 0xA4)
1664 #define REG_COMBO_PHY0_P0_52_H       (REG_COMBO_PHY0_P0_BASE + 0xA5)
1665 #define REG_COMBO_PHY0_P0_53_L       (REG_COMBO_PHY0_P0_BASE + 0xA6)
1666 #define REG_COMBO_PHY0_P0_53_H       (REG_COMBO_PHY0_P0_BASE + 0xA7)
1667 #define REG_COMBO_PHY0_P0_54_L       (REG_COMBO_PHY0_P0_BASE + 0xA8)
1668 #define REG_COMBO_PHY0_P0_54_H       (REG_COMBO_PHY0_P0_BASE + 0xA9)
1669 #define REG_COMBO_PHY0_P0_55_L       (REG_COMBO_PHY0_P0_BASE + 0xAA)
1670 #define REG_COMBO_PHY0_P0_55_H       (REG_COMBO_PHY0_P0_BASE + 0xAB)
1671 #define REG_COMBO_PHY0_P0_56_L       (REG_COMBO_PHY0_P0_BASE + 0xAC)
1672 #define REG_COMBO_PHY0_P0_56_H       (REG_COMBO_PHY0_P0_BASE + 0xAD)
1673 #define REG_COMBO_PHY0_P0_57_L       (REG_COMBO_PHY0_P0_BASE + 0xAE)
1674 #define REG_COMBO_PHY0_P0_57_H       (REG_COMBO_PHY0_P0_BASE + 0xAF)
1675 #define REG_COMBO_PHY0_P0_58_L       (REG_COMBO_PHY0_P0_BASE + 0xB0)
1676 #define REG_COMBO_PHY0_P0_58_H       (REG_COMBO_PHY0_P0_BASE + 0xB1)
1677 #define REG_COMBO_PHY0_P0_59_L       (REG_COMBO_PHY0_P0_BASE + 0xB2)
1678 #define REG_COMBO_PHY0_P0_59_H       (REG_COMBO_PHY0_P0_BASE + 0xB3)
1679 #define REG_COMBO_PHY0_P0_5A_L       (REG_COMBO_PHY0_P0_BASE + 0xB4)
1680 #define REG_COMBO_PHY0_P0_5A_H       (REG_COMBO_PHY0_P0_BASE + 0xB5)
1681 #define REG_COMBO_PHY0_P0_5B_L       (REG_COMBO_PHY0_P0_BASE + 0xB6)
1682 #define REG_COMBO_PHY0_P0_5B_H       (REG_COMBO_PHY0_P0_BASE + 0xB7)
1683 #define REG_COMBO_PHY0_P0_5C_L       (REG_COMBO_PHY0_P0_BASE + 0xB8)
1684 #define REG_COMBO_PHY0_P0_5C_H       (REG_COMBO_PHY0_P0_BASE + 0xB9)
1685 #define REG_COMBO_PHY0_P0_5D_L       (REG_COMBO_PHY0_P0_BASE + 0xBA)
1686 #define REG_COMBO_PHY0_P0_5D_H       (REG_COMBO_PHY0_P0_BASE + 0xBB)
1687 #define REG_COMBO_PHY0_P0_5E_L       (REG_COMBO_PHY0_P0_BASE + 0xBC)
1688 #define REG_COMBO_PHY0_P0_5E_H       (REG_COMBO_PHY0_P0_BASE + 0xBD)
1689 #define REG_COMBO_PHY0_P0_5F_L       (REG_COMBO_PHY0_P0_BASE + 0xBE)
1690 #define REG_COMBO_PHY0_P0_5F_H       (REG_COMBO_PHY0_P0_BASE + 0xBF)
1691 #define REG_COMBO_PHY0_P0_60_L       (REG_COMBO_PHY0_P0_BASE + 0xC0)
1692 #define REG_COMBO_PHY0_P0_60_H       (REG_COMBO_PHY0_P0_BASE + 0xC1)
1693 #define REG_COMBO_PHY0_P0_61_L       (REG_COMBO_PHY0_P0_BASE + 0xC2)
1694 #define REG_COMBO_PHY0_P0_61_H       (REG_COMBO_PHY0_P0_BASE + 0xC3)
1695 #define REG_COMBO_PHY0_P0_62_L       (REG_COMBO_PHY0_P0_BASE + 0xC4)
1696 #define REG_COMBO_PHY0_P0_62_H       (REG_COMBO_PHY0_P0_BASE + 0xC5)
1697 #define REG_COMBO_PHY0_P0_63_L       (REG_COMBO_PHY0_P0_BASE + 0xC6)
1698 #define REG_COMBO_PHY0_P0_63_H       (REG_COMBO_PHY0_P0_BASE + 0xC7)
1699 #define REG_COMBO_PHY0_P0_64_L       (REG_COMBO_PHY0_P0_BASE + 0xC8)
1700 #define REG_COMBO_PHY0_P0_64_H       (REG_COMBO_PHY0_P0_BASE + 0xC9)
1701 #define REG_COMBO_PHY0_P0_65_L       (REG_COMBO_PHY0_P0_BASE + 0xCA)
1702 #define REG_COMBO_PHY0_P0_65_H       (REG_COMBO_PHY0_P0_BASE + 0xCB)
1703 #define REG_COMBO_PHY0_P0_66_L       (REG_COMBO_PHY0_P0_BASE + 0xCC)
1704 #define REG_COMBO_PHY0_P0_66_H       (REG_COMBO_PHY0_P0_BASE + 0xCD)
1705 #define REG_COMBO_PHY0_P0_67_L       (REG_COMBO_PHY0_P0_BASE + 0xCE)
1706 #define REG_COMBO_PHY0_P0_67_H       (REG_COMBO_PHY0_P0_BASE + 0xCF)
1707 #define REG_COMBO_PHY0_P0_68_L       (REG_COMBO_PHY0_P0_BASE + 0xD0)
1708 #define REG_COMBO_PHY0_P0_68_H       (REG_COMBO_PHY0_P0_BASE + 0xD1)
1709 #define REG_COMBO_PHY0_P0_69_L       (REG_COMBO_PHY0_P0_BASE + 0xD2)
1710 #define REG_COMBO_PHY0_P0_69_H       (REG_COMBO_PHY0_P0_BASE + 0xD3)
1711 #define REG_COMBO_PHY0_P0_6A_L       (REG_COMBO_PHY0_P0_BASE + 0xD4)
1712 #define REG_COMBO_PHY0_P0_6A_H       (REG_COMBO_PHY0_P0_BASE + 0xD5)
1713 #define REG_COMBO_PHY0_P0_6B_L       (REG_COMBO_PHY0_P0_BASE + 0xD6)
1714 #define REG_COMBO_PHY0_P0_6B_H       (REG_COMBO_PHY0_P0_BASE + 0xD7)
1715 #define REG_COMBO_PHY0_P0_6C_L       (REG_COMBO_PHY0_P0_BASE + 0xD8)
1716 #define REG_COMBO_PHY0_P0_6C_H       (REG_COMBO_PHY0_P0_BASE + 0xD9)
1717 #define REG_COMBO_PHY0_P0_6D_L       (REG_COMBO_PHY0_P0_BASE + 0xDA)
1718 #define REG_COMBO_PHY0_P0_6D_H       (REG_COMBO_PHY0_P0_BASE + 0xDB)
1719 #define REG_COMBO_PHY0_P0_6E_L       (REG_COMBO_PHY0_P0_BASE + 0xDC)
1720 #define REG_COMBO_PHY0_P0_6E_H       (REG_COMBO_PHY0_P0_BASE + 0xDD)
1721 #define REG_COMBO_PHY0_P0_6F_L       (REG_COMBO_PHY0_P0_BASE + 0xDE)
1722 #define REG_COMBO_PHY0_P0_6F_H       (REG_COMBO_PHY0_P0_BASE + 0xDF)
1723 #define REG_COMBO_PHY0_P0_70_L       (REG_COMBO_PHY0_P0_BASE + 0xE0)
1724 #define REG_COMBO_PHY0_P0_70_H       (REG_COMBO_PHY0_P0_BASE + 0xE1)
1725 #define REG_COMBO_PHY0_P0_71_L       (REG_COMBO_PHY0_P0_BASE + 0xE2)
1726 #define REG_COMBO_PHY0_P0_71_H       (REG_COMBO_PHY0_P0_BASE + 0xE3)
1727 #define REG_COMBO_PHY0_P0_72_L       (REG_COMBO_PHY0_P0_BASE + 0xE4)
1728 #define REG_COMBO_PHY0_P0_72_H       (REG_COMBO_PHY0_P0_BASE + 0xE5)
1729 #define REG_COMBO_PHY0_P0_73_L       (REG_COMBO_PHY0_P0_BASE + 0xE6)
1730 #define REG_COMBO_PHY0_P0_73_H       (REG_COMBO_PHY0_P0_BASE + 0xE7)
1731 #define REG_COMBO_PHY0_P0_74_L       (REG_COMBO_PHY0_P0_BASE + 0xE8)
1732 #define REG_COMBO_PHY0_P0_74_H       (REG_COMBO_PHY0_P0_BASE + 0xE9)
1733 #define REG_COMBO_PHY0_P0_75_L       (REG_COMBO_PHY0_P0_BASE + 0xEA)
1734 #define REG_COMBO_PHY0_P0_75_H       (REG_COMBO_PHY0_P0_BASE + 0xEB)
1735 #define REG_COMBO_PHY0_P0_76_L       (REG_COMBO_PHY0_P0_BASE + 0xEC)
1736 #define REG_COMBO_PHY0_P0_76_H       (REG_COMBO_PHY0_P0_BASE + 0xED)
1737 #define REG_COMBO_PHY0_P0_77_L       (REG_COMBO_PHY0_P0_BASE + 0xEE)
1738 #define REG_COMBO_PHY0_P0_77_H       (REG_COMBO_PHY0_P0_BASE + 0xEF)
1739 #define REG_COMBO_PHY0_P0_78_L       (REG_COMBO_PHY0_P0_BASE + 0xF0)
1740 #define REG_COMBO_PHY0_P0_78_H       (REG_COMBO_PHY0_P0_BASE + 0xF1)
1741 #define REG_COMBO_PHY0_P0_79_L       (REG_COMBO_PHY0_P0_BASE + 0xF2)
1742 #define REG_COMBO_PHY0_P0_79_H       (REG_COMBO_PHY0_P0_BASE + 0xF3)
1743 #define REG_COMBO_PHY0_P0_7A_L       (REG_COMBO_PHY0_P0_BASE + 0xF4)
1744 #define REG_COMBO_PHY0_P0_7A_H       (REG_COMBO_PHY0_P0_BASE + 0xF5)
1745 #define REG_COMBO_PHY0_P0_7B_L       (REG_COMBO_PHY0_P0_BASE + 0xF6)
1746 #define REG_COMBO_PHY0_P0_7B_H       (REG_COMBO_PHY0_P0_BASE + 0xF7)
1747 #define REG_COMBO_PHY0_P0_7C_L       (REG_COMBO_PHY0_P0_BASE + 0xF8)
1748 #define REG_COMBO_PHY0_P0_7C_H       (REG_COMBO_PHY0_P0_BASE + 0xF9)
1749 #define REG_COMBO_PHY0_P0_7D_L       (REG_COMBO_PHY0_P0_BASE + 0xFA)
1750 #define REG_COMBO_PHY0_P0_7D_H       (REG_COMBO_PHY0_P0_BASE + 0xFB)
1751 #define REG_COMBO_PHY0_P0_7E_L       (REG_COMBO_PHY0_P0_BASE + 0xFC)
1752 #define REG_COMBO_PHY0_P0_7E_H       (REG_COMBO_PHY0_P0_BASE + 0xFD)
1753 #define REG_COMBO_PHY0_P0_7F_L       (REG_COMBO_PHY0_P0_BASE + 0xFE)
1754 #define REG_COMBO_PHY0_P0_7F_H       (REG_COMBO_PHY0_P0_BASE + 0xFF)
1755 
1756 // COMBO_PHY1_P0
1757 #define REG_COMBO_PHY1_P0_00_L       (REG_COMBO_PHY1_P0_BASE + 0x00)
1758 #define REG_COMBO_PHY1_P0_00_H       (REG_COMBO_PHY1_P0_BASE + 0x01)
1759 #define REG_COMBO_PHY1_P0_01_L       (REG_COMBO_PHY1_P0_BASE + 0x02)
1760 #define REG_COMBO_PHY1_P0_01_H       (REG_COMBO_PHY1_P0_BASE + 0x03)
1761 #define REG_COMBO_PHY1_P0_02_L       (REG_COMBO_PHY1_P0_BASE + 0x04)
1762 #define REG_COMBO_PHY1_P0_02_H       (REG_COMBO_PHY1_P0_BASE + 0x05)
1763 #define REG_COMBO_PHY1_P0_03_L       (REG_COMBO_PHY1_P0_BASE + 0x06)
1764 #define REG_COMBO_PHY1_P0_03_H       (REG_COMBO_PHY1_P0_BASE + 0x07)
1765 #define REG_COMBO_PHY1_P0_04_L       (REG_COMBO_PHY1_P0_BASE + 0x08)
1766 #define REG_COMBO_PHY1_P0_04_H       (REG_COMBO_PHY1_P0_BASE + 0x09)
1767 #define REG_COMBO_PHY1_P0_05_L       (REG_COMBO_PHY1_P0_BASE + 0x0A)
1768 #define REG_COMBO_PHY1_P0_05_H       (REG_COMBO_PHY1_P0_BASE + 0x0B)
1769 #define REG_COMBO_PHY1_P0_06_L       (REG_COMBO_PHY1_P0_BASE + 0x0C)
1770 #define REG_COMBO_PHY1_P0_06_H       (REG_COMBO_PHY1_P0_BASE + 0x0D)
1771 #define REG_COMBO_PHY1_P0_07_L       (REG_COMBO_PHY1_P0_BASE + 0x0E)
1772 #define REG_COMBO_PHY1_P0_07_H       (REG_COMBO_PHY1_P0_BASE + 0x0F)
1773 #define REG_COMBO_PHY1_P0_08_L       (REG_COMBO_PHY1_P0_BASE + 0x10)
1774 #define REG_COMBO_PHY1_P0_08_H       (REG_COMBO_PHY1_P0_BASE + 0x11)
1775 #define REG_COMBO_PHY1_P0_09_L       (REG_COMBO_PHY1_P0_BASE + 0x12)
1776 #define REG_COMBO_PHY1_P0_09_H       (REG_COMBO_PHY1_P0_BASE + 0x13)
1777 #define REG_COMBO_PHY1_P0_0A_L       (REG_COMBO_PHY1_P0_BASE + 0x14)
1778 #define REG_COMBO_PHY1_P0_0A_H       (REG_COMBO_PHY1_P0_BASE + 0x15)
1779 #define REG_COMBO_PHY1_P0_0B_L       (REG_COMBO_PHY1_P0_BASE + 0x16)
1780 #define REG_COMBO_PHY1_P0_0B_H       (REG_COMBO_PHY1_P0_BASE + 0x17)
1781 #define REG_COMBO_PHY1_P0_0C_L       (REG_COMBO_PHY1_P0_BASE + 0x18)
1782 #define REG_COMBO_PHY1_P0_0C_H       (REG_COMBO_PHY1_P0_BASE + 0x19)
1783 #define REG_COMBO_PHY1_P0_0D_L       (REG_COMBO_PHY1_P0_BASE + 0x1A)
1784 #define REG_COMBO_PHY1_P0_0D_H       (REG_COMBO_PHY1_P0_BASE + 0x1B)
1785 #define REG_COMBO_PHY1_P0_0E_L       (REG_COMBO_PHY1_P0_BASE + 0x1C)
1786 #define REG_COMBO_PHY1_P0_0E_H       (REG_COMBO_PHY1_P0_BASE + 0x1D)
1787 #define REG_COMBO_PHY1_P0_0F_L       (REG_COMBO_PHY1_P0_BASE + 0x1E)
1788 #define REG_COMBO_PHY1_P0_0F_H       (REG_COMBO_PHY1_P0_BASE + 0x1F)
1789 #define REG_COMBO_PHY1_P0_10_L       (REG_COMBO_PHY1_P0_BASE + 0x20)
1790 #define REG_COMBO_PHY1_P0_10_H       (REG_COMBO_PHY1_P0_BASE + 0x21)
1791 #define REG_COMBO_PHY1_P0_11_L       (REG_COMBO_PHY1_P0_BASE + 0x22)
1792 #define REG_COMBO_PHY1_P0_11_H       (REG_COMBO_PHY1_P0_BASE + 0x23)
1793 #define REG_COMBO_PHY1_P0_12_L       (REG_COMBO_PHY1_P0_BASE + 0x24)
1794 #define REG_COMBO_PHY1_P0_12_H       (REG_COMBO_PHY1_P0_BASE + 0x25)
1795 #define REG_COMBO_PHY1_P0_13_L       (REG_COMBO_PHY1_P0_BASE + 0x26)
1796 #define REG_COMBO_PHY1_P0_13_H       (REG_COMBO_PHY1_P0_BASE + 0x27)
1797 #define REG_COMBO_PHY1_P0_14_L       (REG_COMBO_PHY1_P0_BASE + 0x28)
1798 #define REG_COMBO_PHY1_P0_14_H       (REG_COMBO_PHY1_P0_BASE + 0x29)
1799 #define REG_COMBO_PHY1_P0_15_L       (REG_COMBO_PHY1_P0_BASE + 0x2A)
1800 #define REG_COMBO_PHY1_P0_15_H       (REG_COMBO_PHY1_P0_BASE + 0x2B)
1801 #define REG_COMBO_PHY1_P0_16_L       (REG_COMBO_PHY1_P0_BASE + 0x2C)
1802 #define REG_COMBO_PHY1_P0_16_H       (REG_COMBO_PHY1_P0_BASE + 0x2D)
1803 #define REG_COMBO_PHY1_P0_17_L       (REG_COMBO_PHY1_P0_BASE + 0x2E)
1804 #define REG_COMBO_PHY1_P0_17_H       (REG_COMBO_PHY1_P0_BASE + 0x2F)
1805 #define REG_COMBO_PHY1_P0_18_L       (REG_COMBO_PHY1_P0_BASE + 0x30)
1806 #define REG_COMBO_PHY1_P0_18_H       (REG_COMBO_PHY1_P0_BASE + 0x31)
1807 #define REG_COMBO_PHY1_P0_19_L       (REG_COMBO_PHY1_P0_BASE + 0x32)
1808 #define REG_COMBO_PHY1_P0_19_H       (REG_COMBO_PHY1_P0_BASE + 0x33)
1809 #define REG_COMBO_PHY1_P0_1A_L       (REG_COMBO_PHY1_P0_BASE + 0x34)
1810 #define REG_COMBO_PHY1_P0_1A_H       (REG_COMBO_PHY1_P0_BASE + 0x35)
1811 #define REG_COMBO_PHY1_P0_1B_L       (REG_COMBO_PHY1_P0_BASE + 0x36)
1812 #define REG_COMBO_PHY1_P0_1B_H       (REG_COMBO_PHY1_P0_BASE + 0x37)
1813 #define REG_COMBO_PHY1_P0_1C_L       (REG_COMBO_PHY1_P0_BASE + 0x38)
1814 #define REG_COMBO_PHY1_P0_1C_H       (REG_COMBO_PHY1_P0_BASE + 0x39)
1815 #define REG_COMBO_PHY1_P0_1D_L       (REG_COMBO_PHY1_P0_BASE + 0x3A)
1816 #define REG_COMBO_PHY1_P0_1D_H       (REG_COMBO_PHY1_P0_BASE + 0x3B)
1817 #define REG_COMBO_PHY1_P0_1E_L       (REG_COMBO_PHY1_P0_BASE + 0x3C)
1818 #define REG_COMBO_PHY1_P0_1E_H       (REG_COMBO_PHY1_P0_BASE + 0x3D)
1819 #define REG_COMBO_PHY1_P0_1F_L       (REG_COMBO_PHY1_P0_BASE + 0x3E)
1820 #define REG_COMBO_PHY1_P0_1F_H       (REG_COMBO_PHY1_P0_BASE + 0x3F)
1821 #define REG_COMBO_PHY1_P0_20_L       (REG_COMBO_PHY1_P0_BASE + 0x40)
1822 #define REG_COMBO_PHY1_P0_20_H       (REG_COMBO_PHY1_P0_BASE + 0x41)
1823 #define REG_COMBO_PHY1_P0_21_L       (REG_COMBO_PHY1_P0_BASE + 0x42)
1824 #define REG_COMBO_PHY1_P0_21_H       (REG_COMBO_PHY1_P0_BASE + 0x43)
1825 #define REG_COMBO_PHY1_P0_22_L       (REG_COMBO_PHY1_P0_BASE + 0x44)
1826 #define REG_COMBO_PHY1_P0_22_H       (REG_COMBO_PHY1_P0_BASE + 0x45)
1827 #define REG_COMBO_PHY1_P0_23_L       (REG_COMBO_PHY1_P0_BASE + 0x46)
1828 #define REG_COMBO_PHY1_P0_23_H       (REG_COMBO_PHY1_P0_BASE + 0x47)
1829 #define REG_COMBO_PHY1_P0_24_L       (REG_COMBO_PHY1_P0_BASE + 0x48)
1830 #define REG_COMBO_PHY1_P0_24_H       (REG_COMBO_PHY1_P0_BASE + 0x49)
1831 #define REG_COMBO_PHY1_P0_25_L       (REG_COMBO_PHY1_P0_BASE + 0x4A)
1832 #define REG_COMBO_PHY1_P0_25_H       (REG_COMBO_PHY1_P0_BASE + 0x4B)
1833 #define REG_COMBO_PHY1_P0_26_L       (REG_COMBO_PHY1_P0_BASE + 0x4C)
1834 #define REG_COMBO_PHY1_P0_26_H       (REG_COMBO_PHY1_P0_BASE + 0x4D)
1835 #define REG_COMBO_PHY1_P0_27_L       (REG_COMBO_PHY1_P0_BASE + 0x4E)
1836 #define REG_COMBO_PHY1_P0_27_H       (REG_COMBO_PHY1_P0_BASE + 0x4F)
1837 #define REG_COMBO_PHY1_P0_28_L       (REG_COMBO_PHY1_P0_BASE + 0x50)
1838 #define REG_COMBO_PHY1_P0_28_H       (REG_COMBO_PHY1_P0_BASE + 0x51)
1839 #define REG_COMBO_PHY1_P0_29_L       (REG_COMBO_PHY1_P0_BASE + 0x52)
1840 #define REG_COMBO_PHY1_P0_29_H       (REG_COMBO_PHY1_P0_BASE + 0x53)
1841 #define REG_COMBO_PHY1_P0_2A_L       (REG_COMBO_PHY1_P0_BASE + 0x54)
1842 #define REG_COMBO_PHY1_P0_2A_H       (REG_COMBO_PHY1_P0_BASE + 0x55)
1843 #define REG_COMBO_PHY1_P0_2B_L       (REG_COMBO_PHY1_P0_BASE + 0x56)
1844 #define REG_COMBO_PHY1_P0_2B_H       (REG_COMBO_PHY1_P0_BASE + 0x57)
1845 #define REG_COMBO_PHY1_P0_2C_L       (REG_COMBO_PHY1_P0_BASE + 0x58)
1846 #define REG_COMBO_PHY1_P0_2C_H       (REG_COMBO_PHY1_P0_BASE + 0x59)
1847 #define REG_COMBO_PHY1_P0_2D_L       (REG_COMBO_PHY1_P0_BASE + 0x5A)
1848 #define REG_COMBO_PHY1_P0_2D_H       (REG_COMBO_PHY1_P0_BASE + 0x5B)
1849 #define REG_COMBO_PHY1_P0_2E_L       (REG_COMBO_PHY1_P0_BASE + 0x5C)
1850 #define REG_COMBO_PHY1_P0_2E_H       (REG_COMBO_PHY1_P0_BASE + 0x5D)
1851 #define REG_COMBO_PHY1_P0_2F_L       (REG_COMBO_PHY1_P0_BASE + 0x5E)
1852 #define REG_COMBO_PHY1_P0_2F_H       (REG_COMBO_PHY1_P0_BASE + 0x5F)
1853 #define REG_COMBO_PHY1_P0_30_L       (REG_COMBO_PHY1_P0_BASE + 0x60)
1854 #define REG_COMBO_PHY1_P0_30_H       (REG_COMBO_PHY1_P0_BASE + 0x61)
1855 #define REG_COMBO_PHY1_P0_31_L       (REG_COMBO_PHY1_P0_BASE + 0x62)
1856 #define REG_COMBO_PHY1_P0_31_H       (REG_COMBO_PHY1_P0_BASE + 0x63)
1857 #define REG_COMBO_PHY1_P0_32_L       (REG_COMBO_PHY1_P0_BASE + 0x64)
1858 #define REG_COMBO_PHY1_P0_32_H       (REG_COMBO_PHY1_P0_BASE + 0x65)
1859 #define REG_COMBO_PHY1_P0_33_L       (REG_COMBO_PHY1_P0_BASE + 0x66)
1860 #define REG_COMBO_PHY1_P0_33_H       (REG_COMBO_PHY1_P0_BASE + 0x67)
1861 #define REG_COMBO_PHY1_P0_34_L       (REG_COMBO_PHY1_P0_BASE + 0x68)
1862 #define REG_COMBO_PHY1_P0_34_H       (REG_COMBO_PHY1_P0_BASE + 0x69)
1863 #define REG_COMBO_PHY1_P0_35_L       (REG_COMBO_PHY1_P0_BASE + 0x6A)
1864 #define REG_COMBO_PHY1_P0_35_H       (REG_COMBO_PHY1_P0_BASE + 0x6B)
1865 #define REG_COMBO_PHY1_P0_36_L       (REG_COMBO_PHY1_P0_BASE + 0x6C)
1866 #define REG_COMBO_PHY1_P0_36_H       (REG_COMBO_PHY1_P0_BASE + 0x6D)
1867 #define REG_COMBO_PHY1_P0_37_L       (REG_COMBO_PHY1_P0_BASE + 0x6E)
1868 #define REG_COMBO_PHY1_P0_37_H       (REG_COMBO_PHY1_P0_BASE + 0x6F)
1869 #define REG_COMBO_PHY1_P0_38_L       (REG_COMBO_PHY1_P0_BASE + 0x70)
1870 #define REG_COMBO_PHY1_P0_38_H       (REG_COMBO_PHY1_P0_BASE + 0x71)
1871 #define REG_COMBO_PHY1_P0_39_L       (REG_COMBO_PHY1_P0_BASE + 0x72)
1872 #define REG_COMBO_PHY1_P0_39_H       (REG_COMBO_PHY1_P0_BASE + 0x73)
1873 #define REG_COMBO_PHY1_P0_3A_L       (REG_COMBO_PHY1_P0_BASE + 0x74)
1874 #define REG_COMBO_PHY1_P0_3A_H       (REG_COMBO_PHY1_P0_BASE + 0x75)
1875 #define REG_COMBO_PHY1_P0_3B_L       (REG_COMBO_PHY1_P0_BASE + 0x76)
1876 #define REG_COMBO_PHY1_P0_3B_H       (REG_COMBO_PHY1_P0_BASE + 0x77)
1877 #define REG_COMBO_PHY1_P0_3C_L       (REG_COMBO_PHY1_P0_BASE + 0x78)
1878 #define REG_COMBO_PHY1_P0_3C_H       (REG_COMBO_PHY1_P0_BASE + 0x79)
1879 #define REG_COMBO_PHY1_P0_3D_L       (REG_COMBO_PHY1_P0_BASE + 0x7A)
1880 #define REG_COMBO_PHY1_P0_3D_H       (REG_COMBO_PHY1_P0_BASE + 0x7B)
1881 #define REG_COMBO_PHY1_P0_3E_L       (REG_COMBO_PHY1_P0_BASE + 0x7C)
1882 #define REG_COMBO_PHY1_P0_3E_H       (REG_COMBO_PHY1_P0_BASE + 0x7D)
1883 #define REG_COMBO_PHY1_P0_3F_L       (REG_COMBO_PHY1_P0_BASE + 0x7E)
1884 #define REG_COMBO_PHY1_P0_3F_H       (REG_COMBO_PHY1_P0_BASE + 0x7F)
1885 #define REG_COMBO_PHY1_P0_40_L       (REG_COMBO_PHY1_P0_BASE + 0x80)
1886 #define REG_COMBO_PHY1_P0_40_H       (REG_COMBO_PHY1_P0_BASE + 0x81)
1887 #define REG_COMBO_PHY1_P0_41_L       (REG_COMBO_PHY1_P0_BASE + 0x82)
1888 #define REG_COMBO_PHY1_P0_41_H       (REG_COMBO_PHY1_P0_BASE + 0x83)
1889 #define REG_COMBO_PHY1_P0_42_L       (REG_COMBO_PHY1_P0_BASE + 0x84)
1890 #define REG_COMBO_PHY1_P0_42_H       (REG_COMBO_PHY1_P0_BASE + 0x85)
1891 #define REG_COMBO_PHY1_P0_43_L       (REG_COMBO_PHY1_P0_BASE + 0x86)
1892 #define REG_COMBO_PHY1_P0_43_H       (REG_COMBO_PHY1_P0_BASE + 0x87)
1893 #define REG_COMBO_PHY1_P0_44_L       (REG_COMBO_PHY1_P0_BASE + 0x88)
1894 #define REG_COMBO_PHY1_P0_44_H       (REG_COMBO_PHY1_P0_BASE + 0x89)
1895 #define REG_COMBO_PHY1_P0_45_L       (REG_COMBO_PHY1_P0_BASE + 0x8A)
1896 #define REG_COMBO_PHY1_P0_45_H       (REG_COMBO_PHY1_P0_BASE + 0x8B)
1897 #define REG_COMBO_PHY1_P0_46_L       (REG_COMBO_PHY1_P0_BASE + 0x8C)
1898 #define REG_COMBO_PHY1_P0_46_H       (REG_COMBO_PHY1_P0_BASE + 0x8D)
1899 #define REG_COMBO_PHY1_P0_47_L       (REG_COMBO_PHY1_P0_BASE + 0x8E)
1900 #define REG_COMBO_PHY1_P0_47_H       (REG_COMBO_PHY1_P0_BASE + 0x8F)
1901 #define REG_COMBO_PHY1_P0_48_L       (REG_COMBO_PHY1_P0_BASE + 0x90)
1902 #define REG_COMBO_PHY1_P0_48_H       (REG_COMBO_PHY1_P0_BASE + 0x91)
1903 #define REG_COMBO_PHY1_P0_49_L       (REG_COMBO_PHY1_P0_BASE + 0x92)
1904 #define REG_COMBO_PHY1_P0_49_H       (REG_COMBO_PHY1_P0_BASE + 0x93)
1905 #define REG_COMBO_PHY1_P0_4A_L       (REG_COMBO_PHY1_P0_BASE + 0x94)
1906 #define REG_COMBO_PHY1_P0_4A_H       (REG_COMBO_PHY1_P0_BASE + 0x95)
1907 #define REG_COMBO_PHY1_P0_4B_L       (REG_COMBO_PHY1_P0_BASE + 0x96)
1908 #define REG_COMBO_PHY1_P0_4B_H       (REG_COMBO_PHY1_P0_BASE + 0x97)
1909 #define REG_COMBO_PHY1_P0_4C_L       (REG_COMBO_PHY1_P0_BASE + 0x98)
1910 #define REG_COMBO_PHY1_P0_4C_H       (REG_COMBO_PHY1_P0_BASE + 0x99)
1911 #define REG_COMBO_PHY1_P0_4D_L       (REG_COMBO_PHY1_P0_BASE + 0x9A)
1912 #define REG_COMBO_PHY1_P0_4D_H       (REG_COMBO_PHY1_P0_BASE + 0x9B)
1913 #define REG_COMBO_PHY1_P0_4E_L       (REG_COMBO_PHY1_P0_BASE + 0x9C)
1914 #define REG_COMBO_PHY1_P0_4E_H       (REG_COMBO_PHY1_P0_BASE + 0x9D)
1915 #define REG_COMBO_PHY1_P0_4F_L       (REG_COMBO_PHY1_P0_BASE + 0x9E)
1916 #define REG_COMBO_PHY1_P0_4F_H       (REG_COMBO_PHY1_P0_BASE + 0x9F)
1917 #define REG_COMBO_PHY1_P0_50_L       (REG_COMBO_PHY1_P0_BASE + 0xA0)
1918 #define REG_COMBO_PHY1_P0_50_H       (REG_COMBO_PHY1_P0_BASE + 0xA1)
1919 #define REG_COMBO_PHY1_P0_51_L       (REG_COMBO_PHY1_P0_BASE + 0xA2)
1920 #define REG_COMBO_PHY1_P0_51_H       (REG_COMBO_PHY1_P0_BASE + 0xA3)
1921 #define REG_COMBO_PHY1_P0_52_L       (REG_COMBO_PHY1_P0_BASE + 0xA4)
1922 #define REG_COMBO_PHY1_P0_52_H       (REG_COMBO_PHY1_P0_BASE + 0xA5)
1923 #define REG_COMBO_PHY1_P0_53_L       (REG_COMBO_PHY1_P0_BASE + 0xA6)
1924 #define REG_COMBO_PHY1_P0_53_H       (REG_COMBO_PHY1_P0_BASE + 0xA7)
1925 #define REG_COMBO_PHY1_P0_54_L       (REG_COMBO_PHY1_P0_BASE + 0xA8)
1926 #define REG_COMBO_PHY1_P0_54_H       (REG_COMBO_PHY1_P0_BASE + 0xA9)
1927 #define REG_COMBO_PHY1_P0_55_L       (REG_COMBO_PHY1_P0_BASE + 0xAA)
1928 #define REG_COMBO_PHY1_P0_55_H       (REG_COMBO_PHY1_P0_BASE + 0xAB)
1929 #define REG_COMBO_PHY1_P0_56_L       (REG_COMBO_PHY1_P0_BASE + 0xAC)
1930 #define REG_COMBO_PHY1_P0_56_H       (REG_COMBO_PHY1_P0_BASE + 0xAD)
1931 #define REG_COMBO_PHY1_P0_57_L       (REG_COMBO_PHY1_P0_BASE + 0xAE)
1932 #define REG_COMBO_PHY1_P0_57_H       (REG_COMBO_PHY1_P0_BASE + 0xAF)
1933 #define REG_COMBO_PHY1_P0_58_L       (REG_COMBO_PHY1_P0_BASE + 0xB0)
1934 #define REG_COMBO_PHY1_P0_58_H       (REG_COMBO_PHY1_P0_BASE + 0xB1)
1935 #define REG_COMBO_PHY1_P0_59_L       (REG_COMBO_PHY1_P0_BASE + 0xB2)
1936 #define REG_COMBO_PHY1_P0_59_H       (REG_COMBO_PHY1_P0_BASE + 0xB3)
1937 #define REG_COMBO_PHY1_P0_5A_L       (REG_COMBO_PHY1_P0_BASE + 0xB4)
1938 #define REG_COMBO_PHY1_P0_5A_H       (REG_COMBO_PHY1_P0_BASE + 0xB5)
1939 #define REG_COMBO_PHY1_P0_5B_L       (REG_COMBO_PHY1_P0_BASE + 0xB6)
1940 #define REG_COMBO_PHY1_P0_5B_H       (REG_COMBO_PHY1_P0_BASE + 0xB7)
1941 #define REG_COMBO_PHY1_P0_5C_L       (REG_COMBO_PHY1_P0_BASE + 0xB8)
1942 #define REG_COMBO_PHY1_P0_5C_H       (REG_COMBO_PHY1_P0_BASE + 0xB9)
1943 #define REG_COMBO_PHY1_P0_5D_L       (REG_COMBO_PHY1_P0_BASE + 0xBA)
1944 #define REG_COMBO_PHY1_P0_5D_H       (REG_COMBO_PHY1_P0_BASE + 0xBB)
1945 #define REG_COMBO_PHY1_P0_5E_L       (REG_COMBO_PHY1_P0_BASE + 0xBC)
1946 #define REG_COMBO_PHY1_P0_5E_H       (REG_COMBO_PHY1_P0_BASE + 0xBD)
1947 #define REG_COMBO_PHY1_P0_5F_L       (REG_COMBO_PHY1_P0_BASE + 0xBE)
1948 #define REG_COMBO_PHY1_P0_5F_H       (REG_COMBO_PHY1_P0_BASE + 0xBF)
1949 #define REG_COMBO_PHY1_P0_60_L       (REG_COMBO_PHY1_P0_BASE + 0xC0)
1950 #define REG_COMBO_PHY1_P0_60_H       (REG_COMBO_PHY1_P0_BASE + 0xC1)
1951 #define REG_COMBO_PHY1_P0_61_L       (REG_COMBO_PHY1_P0_BASE + 0xC2)
1952 #define REG_COMBO_PHY1_P0_61_H       (REG_COMBO_PHY1_P0_BASE + 0xC3)
1953 #define REG_COMBO_PHY1_P0_62_L       (REG_COMBO_PHY1_P0_BASE + 0xC4)
1954 #define REG_COMBO_PHY1_P0_62_H       (REG_COMBO_PHY1_P0_BASE + 0xC5)
1955 #define REG_COMBO_PHY1_P0_63_L       (REG_COMBO_PHY1_P0_BASE + 0xC6)
1956 #define REG_COMBO_PHY1_P0_63_H       (REG_COMBO_PHY1_P0_BASE + 0xC7)
1957 #define REG_COMBO_PHY1_P0_64_L       (REG_COMBO_PHY1_P0_BASE + 0xC8)
1958 #define REG_COMBO_PHY1_P0_64_H       (REG_COMBO_PHY1_P0_BASE + 0xC9)
1959 #define REG_COMBO_PHY1_P0_65_L       (REG_COMBO_PHY1_P0_BASE + 0xCA)
1960 #define REG_COMBO_PHY1_P0_65_H       (REG_COMBO_PHY1_P0_BASE + 0xCB)
1961 #define REG_COMBO_PHY1_P0_66_L       (REG_COMBO_PHY1_P0_BASE + 0xCC)
1962 #define REG_COMBO_PHY1_P0_66_H       (REG_COMBO_PHY1_P0_BASE + 0xCD)
1963 #define REG_COMBO_PHY1_P0_67_L       (REG_COMBO_PHY1_P0_BASE + 0xCE)
1964 #define REG_COMBO_PHY1_P0_67_H       (REG_COMBO_PHY1_P0_BASE + 0xCF)
1965 #define REG_COMBO_PHY1_P0_68_L       (REG_COMBO_PHY1_P0_BASE + 0xD0)
1966 #define REG_COMBO_PHY1_P0_68_H       (REG_COMBO_PHY1_P0_BASE + 0xD1)
1967 #define REG_COMBO_PHY1_P0_69_L       (REG_COMBO_PHY1_P0_BASE + 0xD2)
1968 #define REG_COMBO_PHY1_P0_69_H       (REG_COMBO_PHY1_P0_BASE + 0xD3)
1969 #define REG_COMBO_PHY1_P0_6A_L       (REG_COMBO_PHY1_P0_BASE + 0xD4)
1970 #define REG_COMBO_PHY1_P0_6A_H       (REG_COMBO_PHY1_P0_BASE + 0xD5)
1971 #define REG_COMBO_PHY1_P0_6B_L       (REG_COMBO_PHY1_P0_BASE + 0xD6)
1972 #define REG_COMBO_PHY1_P0_6B_H       (REG_COMBO_PHY1_P0_BASE + 0xD7)
1973 #define REG_COMBO_PHY1_P0_6C_L       (REG_COMBO_PHY1_P0_BASE + 0xD8)
1974 #define REG_COMBO_PHY1_P0_6C_H       (REG_COMBO_PHY1_P0_BASE + 0xD9)
1975 #define REG_COMBO_PHY1_P0_6D_L       (REG_COMBO_PHY1_P0_BASE + 0xDA)
1976 #define REG_COMBO_PHY1_P0_6D_H       (REG_COMBO_PHY1_P0_BASE + 0xDB)
1977 #define REG_COMBO_PHY1_P0_6E_L       (REG_COMBO_PHY1_P0_BASE + 0xDC)
1978 #define REG_COMBO_PHY1_P0_6E_H       (REG_COMBO_PHY1_P0_BASE + 0xDD)
1979 #define REG_COMBO_PHY1_P0_6F_L       (REG_COMBO_PHY1_P0_BASE + 0xDE)
1980 #define REG_COMBO_PHY1_P0_6F_H       (REG_COMBO_PHY1_P0_BASE + 0xDF)
1981 #define REG_COMBO_PHY1_P0_70_L       (REG_COMBO_PHY1_P0_BASE + 0xE0)
1982 #define REG_COMBO_PHY1_P0_70_H       (REG_COMBO_PHY1_P0_BASE + 0xE1)
1983 #define REG_COMBO_PHY1_P0_71_L       (REG_COMBO_PHY1_P0_BASE + 0xE2)
1984 #define REG_COMBO_PHY1_P0_71_H       (REG_COMBO_PHY1_P0_BASE + 0xE3)
1985 #define REG_COMBO_PHY1_P0_72_L       (REG_COMBO_PHY1_P0_BASE + 0xE4)
1986 #define REG_COMBO_PHY1_P0_72_H       (REG_COMBO_PHY1_P0_BASE + 0xE5)
1987 #define REG_COMBO_PHY1_P0_73_L       (REG_COMBO_PHY1_P0_BASE + 0xE6)
1988 #define REG_COMBO_PHY1_P0_73_H       (REG_COMBO_PHY1_P0_BASE + 0xE7)
1989 #define REG_COMBO_PHY1_P0_74_L       (REG_COMBO_PHY1_P0_BASE + 0xE8)
1990 #define REG_COMBO_PHY1_P0_74_H       (REG_COMBO_PHY1_P0_BASE + 0xE9)
1991 #define REG_COMBO_PHY1_P0_75_L       (REG_COMBO_PHY1_P0_BASE + 0xEA)
1992 #define REG_COMBO_PHY1_P0_75_H       (REG_COMBO_PHY1_P0_BASE + 0xEB)
1993 #define REG_COMBO_PHY1_P0_76_L       (REG_COMBO_PHY1_P0_BASE + 0xEC)
1994 #define REG_COMBO_PHY1_P0_76_H       (REG_COMBO_PHY1_P0_BASE + 0xED)
1995 #define REG_COMBO_PHY1_P0_77_L       (REG_COMBO_PHY1_P0_BASE + 0xEE)
1996 #define REG_COMBO_PHY1_P0_77_H       (REG_COMBO_PHY1_P0_BASE + 0xEF)
1997 #define REG_COMBO_PHY1_P0_78_L       (REG_COMBO_PHY1_P0_BASE + 0xF0)
1998 #define REG_COMBO_PHY1_P0_78_H       (REG_COMBO_PHY1_P0_BASE + 0xF1)
1999 #define REG_COMBO_PHY1_P0_79_L       (REG_COMBO_PHY1_P0_BASE + 0xF2)
2000 #define REG_COMBO_PHY1_P0_79_H       (REG_COMBO_PHY1_P0_BASE + 0xF3)
2001 #define REG_COMBO_PHY1_P0_7A_L       (REG_COMBO_PHY1_P0_BASE + 0xF4)
2002 #define REG_COMBO_PHY1_P0_7A_H       (REG_COMBO_PHY1_P0_BASE + 0xF5)
2003 #define REG_COMBO_PHY1_P0_7B_L       (REG_COMBO_PHY1_P0_BASE + 0xF6)
2004 #define REG_COMBO_PHY1_P0_7B_H       (REG_COMBO_PHY1_P0_BASE + 0xF7)
2005 #define REG_COMBO_PHY1_P0_7C_L       (REG_COMBO_PHY1_P0_BASE + 0xF8)
2006 #define REG_COMBO_PHY1_P0_7C_H       (REG_COMBO_PHY1_P0_BASE + 0xF9)
2007 #define REG_COMBO_PHY1_P0_7D_L       (REG_COMBO_PHY1_P0_BASE + 0xFA)
2008 #define REG_COMBO_PHY1_P0_7D_H       (REG_COMBO_PHY1_P0_BASE + 0xFB)
2009 #define REG_COMBO_PHY1_P0_7E_L       (REG_COMBO_PHY1_P0_BASE + 0xFC)
2010 #define REG_COMBO_PHY1_P0_7E_H       (REG_COMBO_PHY1_P0_BASE + 0xFD)
2011 #define REG_COMBO_PHY1_P0_7F_L       (REG_COMBO_PHY1_P0_BASE + 0xFE)
2012 #define REG_COMBO_PHY1_P0_7F_H       (REG_COMBO_PHY1_P0_BASE + 0xFF)
2013 
2014 // COMBO_PHY0_P1
2015 #define REG_COMBO_PHY0_P1_00_L       (REG_COMBO_PHY0_P1_BASE + 0x00)
2016 #define REG_COMBO_PHY0_P1_00_H       (REG_COMBO_PHY0_P1_BASE + 0x01)
2017 #define REG_COMBO_PHY0_P1_01_L       (REG_COMBO_PHY0_P1_BASE + 0x02)
2018 #define REG_COMBO_PHY0_P1_01_H       (REG_COMBO_PHY0_P1_BASE + 0x03)
2019 #define REG_COMBO_PHY0_P1_02_L       (REG_COMBO_PHY0_P1_BASE + 0x04)
2020 #define REG_COMBO_PHY0_P1_02_H       (REG_COMBO_PHY0_P1_BASE + 0x05)
2021 #define REG_COMBO_PHY0_P1_03_L       (REG_COMBO_PHY0_P1_BASE + 0x06)
2022 #define REG_COMBO_PHY0_P1_03_H       (REG_COMBO_PHY0_P1_BASE + 0x07)
2023 #define REG_COMBO_PHY0_P1_04_L       (REG_COMBO_PHY0_P1_BASE + 0x08)
2024 #define REG_COMBO_PHY0_P1_04_H       (REG_COMBO_PHY0_P1_BASE + 0x09)
2025 #define REG_COMBO_PHY0_P1_05_L       (REG_COMBO_PHY0_P1_BASE + 0x0A)
2026 #define REG_COMBO_PHY0_P1_05_H       (REG_COMBO_PHY0_P1_BASE + 0x0B)
2027 #define REG_COMBO_PHY0_P1_06_L       (REG_COMBO_PHY0_P1_BASE + 0x0C)
2028 #define REG_COMBO_PHY0_P1_06_H       (REG_COMBO_PHY0_P1_BASE + 0x0D)
2029 #define REG_COMBO_PHY0_P1_07_L       (REG_COMBO_PHY0_P1_BASE + 0x0E)
2030 #define REG_COMBO_PHY0_P1_07_H       (REG_COMBO_PHY0_P1_BASE + 0x0F)
2031 #define REG_COMBO_PHY0_P1_08_L       (REG_COMBO_PHY0_P1_BASE + 0x10)
2032 #define REG_COMBO_PHY0_P1_08_H       (REG_COMBO_PHY0_P1_BASE + 0x11)
2033 #define REG_COMBO_PHY0_P1_09_L       (REG_COMBO_PHY0_P1_BASE + 0x12)
2034 #define REG_COMBO_PHY0_P1_09_H       (REG_COMBO_PHY0_P1_BASE + 0x13)
2035 #define REG_COMBO_PHY0_P1_0A_L       (REG_COMBO_PHY0_P1_BASE + 0x14)
2036 #define REG_COMBO_PHY0_P1_0A_H       (REG_COMBO_PHY0_P1_BASE + 0x15)
2037 #define REG_COMBO_PHY0_P1_0B_L       (REG_COMBO_PHY0_P1_BASE + 0x16)
2038 #define REG_COMBO_PHY0_P1_0B_H       (REG_COMBO_PHY0_P1_BASE + 0x17)
2039 #define REG_COMBO_PHY0_P1_0C_L       (REG_COMBO_PHY0_P1_BASE + 0x18)
2040 #define REG_COMBO_PHY0_P1_0C_H       (REG_COMBO_PHY0_P1_BASE + 0x19)
2041 #define REG_COMBO_PHY0_P1_0D_L       (REG_COMBO_PHY0_P1_BASE + 0x1A)
2042 #define REG_COMBO_PHY0_P1_0D_H       (REG_COMBO_PHY0_P1_BASE + 0x1B)
2043 #define REG_COMBO_PHY0_P1_0E_L       (REG_COMBO_PHY0_P1_BASE + 0x1C)
2044 #define REG_COMBO_PHY0_P1_0E_H       (REG_COMBO_PHY0_P1_BASE + 0x1D)
2045 #define REG_COMBO_PHY0_P1_0F_L       (REG_COMBO_PHY0_P1_BASE + 0x1E)
2046 #define REG_COMBO_PHY0_P1_0F_H       (REG_COMBO_PHY0_P1_BASE + 0x1F)
2047 #define REG_COMBO_PHY0_P1_10_L       (REG_COMBO_PHY0_P1_BASE + 0x20)
2048 #define REG_COMBO_PHY0_P1_10_H       (REG_COMBO_PHY0_P1_BASE + 0x21)
2049 #define REG_COMBO_PHY0_P1_11_L       (REG_COMBO_PHY0_P1_BASE + 0x22)
2050 #define REG_COMBO_PHY0_P1_11_H       (REG_COMBO_PHY0_P1_BASE + 0x23)
2051 #define REG_COMBO_PHY0_P1_12_L       (REG_COMBO_PHY0_P1_BASE + 0x24)
2052 #define REG_COMBO_PHY0_P1_12_H       (REG_COMBO_PHY0_P1_BASE + 0x25)
2053 #define REG_COMBO_PHY0_P1_13_L       (REG_COMBO_PHY0_P1_BASE + 0x26)
2054 #define REG_COMBO_PHY0_P1_13_H       (REG_COMBO_PHY0_P1_BASE + 0x27)
2055 #define REG_COMBO_PHY0_P1_14_L       (REG_COMBO_PHY0_P1_BASE + 0x28)
2056 #define REG_COMBO_PHY0_P1_14_H       (REG_COMBO_PHY0_P1_BASE + 0x29)
2057 #define REG_COMBO_PHY0_P1_15_L       (REG_COMBO_PHY0_P1_BASE + 0x2A)
2058 #define REG_COMBO_PHY0_P1_15_H       (REG_COMBO_PHY0_P1_BASE + 0x2B)
2059 #define REG_COMBO_PHY0_P1_16_L       (REG_COMBO_PHY0_P1_BASE + 0x2C)
2060 #define REG_COMBO_PHY0_P1_16_H       (REG_COMBO_PHY0_P1_BASE + 0x2D)
2061 #define REG_COMBO_PHY0_P1_17_L       (REG_COMBO_PHY0_P1_BASE + 0x2E)
2062 #define REG_COMBO_PHY0_P1_17_H       (REG_COMBO_PHY0_P1_BASE + 0x2F)
2063 #define REG_COMBO_PHY0_P1_18_L       (REG_COMBO_PHY0_P1_BASE + 0x30)
2064 #define REG_COMBO_PHY0_P1_18_H       (REG_COMBO_PHY0_P1_BASE + 0x31)
2065 #define REG_COMBO_PHY0_P1_19_L       (REG_COMBO_PHY0_P1_BASE + 0x32)
2066 #define REG_COMBO_PHY0_P1_19_H       (REG_COMBO_PHY0_P1_BASE + 0x33)
2067 #define REG_COMBO_PHY0_P1_1A_L       (REG_COMBO_PHY0_P1_BASE + 0x34)
2068 #define REG_COMBO_PHY0_P1_1A_H       (REG_COMBO_PHY0_P1_BASE + 0x35)
2069 #define REG_COMBO_PHY0_P1_1B_L       (REG_COMBO_PHY0_P1_BASE + 0x36)
2070 #define REG_COMBO_PHY0_P1_1B_H       (REG_COMBO_PHY0_P1_BASE + 0x37)
2071 #define REG_COMBO_PHY0_P1_1C_L       (REG_COMBO_PHY0_P1_BASE + 0x38)
2072 #define REG_COMBO_PHY0_P1_1C_H       (REG_COMBO_PHY0_P1_BASE + 0x39)
2073 #define REG_COMBO_PHY0_P1_1D_L       (REG_COMBO_PHY0_P1_BASE + 0x3A)
2074 #define REG_COMBO_PHY0_P1_1D_H       (REG_COMBO_PHY0_P1_BASE + 0x3B)
2075 #define REG_COMBO_PHY0_P1_1E_L       (REG_COMBO_PHY0_P1_BASE + 0x3C)
2076 #define REG_COMBO_PHY0_P1_1E_H       (REG_COMBO_PHY0_P1_BASE + 0x3D)
2077 #define REG_COMBO_PHY0_P1_1F_L       (REG_COMBO_PHY0_P1_BASE + 0x3E)
2078 #define REG_COMBO_PHY0_P1_1F_H       (REG_COMBO_PHY0_P1_BASE + 0x3F)
2079 #define REG_COMBO_PHY0_P1_20_L       (REG_COMBO_PHY0_P1_BASE + 0x40)
2080 #define REG_COMBO_PHY0_P1_20_H       (REG_COMBO_PHY0_P1_BASE + 0x41)
2081 #define REG_COMBO_PHY0_P1_21_L       (REG_COMBO_PHY0_P1_BASE + 0x42)
2082 #define REG_COMBO_PHY0_P1_21_H       (REG_COMBO_PHY0_P1_BASE + 0x43)
2083 #define REG_COMBO_PHY0_P1_22_L       (REG_COMBO_PHY0_P1_BASE + 0x44)
2084 #define REG_COMBO_PHY0_P1_22_H       (REG_COMBO_PHY0_P1_BASE + 0x45)
2085 #define REG_COMBO_PHY0_P1_23_L       (REG_COMBO_PHY0_P1_BASE + 0x46)
2086 #define REG_COMBO_PHY0_P1_23_H       (REG_COMBO_PHY0_P1_BASE + 0x47)
2087 #define REG_COMBO_PHY0_P1_24_L       (REG_COMBO_PHY0_P1_BASE + 0x48)
2088 #define REG_COMBO_PHY0_P1_24_H       (REG_COMBO_PHY0_P1_BASE + 0x49)
2089 #define REG_COMBO_PHY0_P1_25_L       (REG_COMBO_PHY0_P1_BASE + 0x4A)
2090 #define REG_COMBO_PHY0_P1_25_H       (REG_COMBO_PHY0_P1_BASE + 0x4B)
2091 #define REG_COMBO_PHY0_P1_26_L       (REG_COMBO_PHY0_P1_BASE + 0x4C)
2092 #define REG_COMBO_PHY0_P1_26_H       (REG_COMBO_PHY0_P1_BASE + 0x4D)
2093 #define REG_COMBO_PHY0_P1_27_L       (REG_COMBO_PHY0_P1_BASE + 0x4E)
2094 #define REG_COMBO_PHY0_P1_27_H       (REG_COMBO_PHY0_P1_BASE + 0x4F)
2095 #define REG_COMBO_PHY0_P1_28_L       (REG_COMBO_PHY0_P1_BASE + 0x50)
2096 #define REG_COMBO_PHY0_P1_28_H       (REG_COMBO_PHY0_P1_BASE + 0x51)
2097 #define REG_COMBO_PHY0_P1_29_L       (REG_COMBO_PHY0_P1_BASE + 0x52)
2098 #define REG_COMBO_PHY0_P1_29_H       (REG_COMBO_PHY0_P1_BASE + 0x53)
2099 #define REG_COMBO_PHY0_P1_2A_L       (REG_COMBO_PHY0_P1_BASE + 0x54)
2100 #define REG_COMBO_PHY0_P1_2A_H       (REG_COMBO_PHY0_P1_BASE + 0x55)
2101 #define REG_COMBO_PHY0_P1_2B_L       (REG_COMBO_PHY0_P1_BASE + 0x56)
2102 #define REG_COMBO_PHY0_P1_2B_H       (REG_COMBO_PHY0_P1_BASE + 0x57)
2103 #define REG_COMBO_PHY0_P1_2C_L       (REG_COMBO_PHY0_P1_BASE + 0x58)
2104 #define REG_COMBO_PHY0_P1_2C_H       (REG_COMBO_PHY0_P1_BASE + 0x59)
2105 #define REG_COMBO_PHY0_P1_2D_L       (REG_COMBO_PHY0_P1_BASE + 0x5A)
2106 #define REG_COMBO_PHY0_P1_2D_H       (REG_COMBO_PHY0_P1_BASE + 0x5B)
2107 #define REG_COMBO_PHY0_P1_2E_L       (REG_COMBO_PHY0_P1_BASE + 0x5C)
2108 #define REG_COMBO_PHY0_P1_2E_H       (REG_COMBO_PHY0_P1_BASE + 0x5D)
2109 #define REG_COMBO_PHY0_P1_2F_L       (REG_COMBO_PHY0_P1_BASE + 0x5E)
2110 #define REG_COMBO_PHY0_P1_2F_H       (REG_COMBO_PHY0_P1_BASE + 0x5F)
2111 #define REG_COMBO_PHY0_P1_30_L       (REG_COMBO_PHY0_P1_BASE + 0x60)
2112 #define REG_COMBO_PHY0_P1_30_H       (REG_COMBO_PHY0_P1_BASE + 0x61)
2113 #define REG_COMBO_PHY0_P1_31_L       (REG_COMBO_PHY0_P1_BASE + 0x62)
2114 #define REG_COMBO_PHY0_P1_31_H       (REG_COMBO_PHY0_P1_BASE + 0x63)
2115 #define REG_COMBO_PHY0_P1_32_L       (REG_COMBO_PHY0_P1_BASE + 0x64)
2116 #define REG_COMBO_PHY0_P1_32_H       (REG_COMBO_PHY0_P1_BASE + 0x65)
2117 #define REG_COMBO_PHY0_P1_33_L       (REG_COMBO_PHY0_P1_BASE + 0x66)
2118 #define REG_COMBO_PHY0_P1_33_H       (REG_COMBO_PHY0_P1_BASE + 0x67)
2119 #define REG_COMBO_PHY0_P1_34_L       (REG_COMBO_PHY0_P1_BASE + 0x68)
2120 #define REG_COMBO_PHY0_P1_34_H       (REG_COMBO_PHY0_P1_BASE + 0x69)
2121 #define REG_COMBO_PHY0_P1_35_L       (REG_COMBO_PHY0_P1_BASE + 0x6A)
2122 #define REG_COMBO_PHY0_P1_35_H       (REG_COMBO_PHY0_P1_BASE + 0x6B)
2123 #define REG_COMBO_PHY0_P1_36_L       (REG_COMBO_PHY0_P1_BASE + 0x6C)
2124 #define REG_COMBO_PHY0_P1_36_H       (REG_COMBO_PHY0_P1_BASE + 0x6D)
2125 #define REG_COMBO_PHY0_P1_37_L       (REG_COMBO_PHY0_P1_BASE + 0x6E)
2126 #define REG_COMBO_PHY0_P1_37_H       (REG_COMBO_PHY0_P1_BASE + 0x6F)
2127 #define REG_COMBO_PHY0_P1_38_L       (REG_COMBO_PHY0_P1_BASE + 0x70)
2128 #define REG_COMBO_PHY0_P1_38_H       (REG_COMBO_PHY0_P1_BASE + 0x71)
2129 #define REG_COMBO_PHY0_P1_39_L       (REG_COMBO_PHY0_P1_BASE + 0x72)
2130 #define REG_COMBO_PHY0_P1_39_H       (REG_COMBO_PHY0_P1_BASE + 0x73)
2131 #define REG_COMBO_PHY0_P1_3A_L       (REG_COMBO_PHY0_P1_BASE + 0x74)
2132 #define REG_COMBO_PHY0_P1_3A_H       (REG_COMBO_PHY0_P1_BASE + 0x75)
2133 #define REG_COMBO_PHY0_P1_3B_L       (REG_COMBO_PHY0_P1_BASE + 0x76)
2134 #define REG_COMBO_PHY0_P1_3B_H       (REG_COMBO_PHY0_P1_BASE + 0x77)
2135 #define REG_COMBO_PHY0_P1_3C_L       (REG_COMBO_PHY0_P1_BASE + 0x78)
2136 #define REG_COMBO_PHY0_P1_3C_H       (REG_COMBO_PHY0_P1_BASE + 0x79)
2137 #define REG_COMBO_PHY0_P1_3D_L       (REG_COMBO_PHY0_P1_BASE + 0x7A)
2138 #define REG_COMBO_PHY0_P1_3D_H       (REG_COMBO_PHY0_P1_BASE + 0x7B)
2139 #define REG_COMBO_PHY0_P1_3E_L       (REG_COMBO_PHY0_P1_BASE + 0x7C)
2140 #define REG_COMBO_PHY0_P1_3E_H       (REG_COMBO_PHY0_P1_BASE + 0x7D)
2141 #define REG_COMBO_PHY0_P1_3F_L       (REG_COMBO_PHY0_P1_BASE + 0x7E)
2142 #define REG_COMBO_PHY0_P1_3F_H       (REG_COMBO_PHY0_P1_BASE + 0x7F)
2143 #define REG_COMBO_PHY0_P1_40_L       (REG_COMBO_PHY0_P1_BASE + 0x80)
2144 #define REG_COMBO_PHY0_P1_40_H       (REG_COMBO_PHY0_P1_BASE + 0x81)
2145 #define REG_COMBO_PHY0_P1_41_L       (REG_COMBO_PHY0_P1_BASE + 0x82)
2146 #define REG_COMBO_PHY0_P1_41_H       (REG_COMBO_PHY0_P1_BASE + 0x83)
2147 #define REG_COMBO_PHY0_P1_42_L       (REG_COMBO_PHY0_P1_BASE + 0x84)
2148 #define REG_COMBO_PHY0_P1_42_H       (REG_COMBO_PHY0_P1_BASE + 0x85)
2149 #define REG_COMBO_PHY0_P1_43_L       (REG_COMBO_PHY0_P1_BASE + 0x86)
2150 #define REG_COMBO_PHY0_P1_43_H       (REG_COMBO_PHY0_P1_BASE + 0x87)
2151 #define REG_COMBO_PHY0_P1_44_L       (REG_COMBO_PHY0_P1_BASE + 0x88)
2152 #define REG_COMBO_PHY0_P1_44_H       (REG_COMBO_PHY0_P1_BASE + 0x89)
2153 #define REG_COMBO_PHY0_P1_45_L       (REG_COMBO_PHY0_P1_BASE + 0x8A)
2154 #define REG_COMBO_PHY0_P1_45_H       (REG_COMBO_PHY0_P1_BASE + 0x8B)
2155 #define REG_COMBO_PHY0_P1_46_L       (REG_COMBO_PHY0_P1_BASE + 0x8C)
2156 #define REG_COMBO_PHY0_P1_46_H       (REG_COMBO_PHY0_P1_BASE + 0x8D)
2157 #define REG_COMBO_PHY0_P1_47_L       (REG_COMBO_PHY0_P1_BASE + 0x8E)
2158 #define REG_COMBO_PHY0_P1_47_H       (REG_COMBO_PHY0_P1_BASE + 0x8F)
2159 #define REG_COMBO_PHY0_P1_48_L       (REG_COMBO_PHY0_P1_BASE + 0x90)
2160 #define REG_COMBO_PHY0_P1_48_H       (REG_COMBO_PHY0_P1_BASE + 0x91)
2161 #define REG_COMBO_PHY0_P1_49_L       (REG_COMBO_PHY0_P1_BASE + 0x92)
2162 #define REG_COMBO_PHY0_P1_49_H       (REG_COMBO_PHY0_P1_BASE + 0x93)
2163 #define REG_COMBO_PHY0_P1_4A_L       (REG_COMBO_PHY0_P1_BASE + 0x94)
2164 #define REG_COMBO_PHY0_P1_4A_H       (REG_COMBO_PHY0_P1_BASE + 0x95)
2165 #define REG_COMBO_PHY0_P1_4B_L       (REG_COMBO_PHY0_P1_BASE + 0x96)
2166 #define REG_COMBO_PHY0_P1_4B_H       (REG_COMBO_PHY0_P1_BASE + 0x97)
2167 #define REG_COMBO_PHY0_P1_4C_L       (REG_COMBO_PHY0_P1_BASE + 0x98)
2168 #define REG_COMBO_PHY0_P1_4C_H       (REG_COMBO_PHY0_P1_BASE + 0x99)
2169 #define REG_COMBO_PHY0_P1_4D_L       (REG_COMBO_PHY0_P1_BASE + 0x9A)
2170 #define REG_COMBO_PHY0_P1_4D_H       (REG_COMBO_PHY0_P1_BASE + 0x9B)
2171 #define REG_COMBO_PHY0_P1_4E_L       (REG_COMBO_PHY0_P1_BASE + 0x9C)
2172 #define REG_COMBO_PHY0_P1_4E_H       (REG_COMBO_PHY0_P1_BASE + 0x9D)
2173 #define REG_COMBO_PHY0_P1_4F_L       (REG_COMBO_PHY0_P1_BASE + 0x9E)
2174 #define REG_COMBO_PHY0_P1_4F_H       (REG_COMBO_PHY0_P1_BASE + 0x9F)
2175 #define REG_COMBO_PHY0_P1_50_L       (REG_COMBO_PHY0_P1_BASE + 0xA0)
2176 #define REG_COMBO_PHY0_P1_50_H       (REG_COMBO_PHY0_P1_BASE + 0xA1)
2177 #define REG_COMBO_PHY0_P1_51_L       (REG_COMBO_PHY0_P1_BASE + 0xA2)
2178 #define REG_COMBO_PHY0_P1_51_H       (REG_COMBO_PHY0_P1_BASE + 0xA3)
2179 #define REG_COMBO_PHY0_P1_52_L       (REG_COMBO_PHY0_P1_BASE + 0xA4)
2180 #define REG_COMBO_PHY0_P1_52_H       (REG_COMBO_PHY0_P1_BASE + 0xA5)
2181 #define REG_COMBO_PHY0_P1_53_L       (REG_COMBO_PHY0_P1_BASE + 0xA6)
2182 #define REG_COMBO_PHY0_P1_53_H       (REG_COMBO_PHY0_P1_BASE + 0xA7)
2183 #define REG_COMBO_PHY0_P1_54_L       (REG_COMBO_PHY0_P1_BASE + 0xA8)
2184 #define REG_COMBO_PHY0_P1_54_H       (REG_COMBO_PHY0_P1_BASE + 0xA9)
2185 #define REG_COMBO_PHY0_P1_55_L       (REG_COMBO_PHY0_P1_BASE + 0xAA)
2186 #define REG_COMBO_PHY0_P1_55_H       (REG_COMBO_PHY0_P1_BASE + 0xAB)
2187 #define REG_COMBO_PHY0_P1_56_L       (REG_COMBO_PHY0_P1_BASE + 0xAC)
2188 #define REG_COMBO_PHY0_P1_56_H       (REG_COMBO_PHY0_P1_BASE + 0xAD)
2189 #define REG_COMBO_PHY0_P1_57_L       (REG_COMBO_PHY0_P1_BASE + 0xAE)
2190 #define REG_COMBO_PHY0_P1_57_H       (REG_COMBO_PHY0_P1_BASE + 0xAF)
2191 #define REG_COMBO_PHY0_P1_58_L       (REG_COMBO_PHY0_P1_BASE + 0xB0)
2192 #define REG_COMBO_PHY0_P1_58_H       (REG_COMBO_PHY0_P1_BASE + 0xB1)
2193 #define REG_COMBO_PHY0_P1_59_L       (REG_COMBO_PHY0_P1_BASE + 0xB2)
2194 #define REG_COMBO_PHY0_P1_59_H       (REG_COMBO_PHY0_P1_BASE + 0xB3)
2195 #define REG_COMBO_PHY0_P1_5A_L       (REG_COMBO_PHY0_P1_BASE + 0xB4)
2196 #define REG_COMBO_PHY0_P1_5A_H       (REG_COMBO_PHY0_P1_BASE + 0xB5)
2197 #define REG_COMBO_PHY0_P1_5B_L       (REG_COMBO_PHY0_P1_BASE + 0xB6)
2198 #define REG_COMBO_PHY0_P1_5B_H       (REG_COMBO_PHY0_P1_BASE + 0xB7)
2199 #define REG_COMBO_PHY0_P1_5C_L       (REG_COMBO_PHY0_P1_BASE + 0xB8)
2200 #define REG_COMBO_PHY0_P1_5C_H       (REG_COMBO_PHY0_P1_BASE + 0xB9)
2201 #define REG_COMBO_PHY0_P1_5D_L       (REG_COMBO_PHY0_P1_BASE + 0xBA)
2202 #define REG_COMBO_PHY0_P1_5D_H       (REG_COMBO_PHY0_P1_BASE + 0xBB)
2203 #define REG_COMBO_PHY0_P1_5E_L       (REG_COMBO_PHY0_P1_BASE + 0xBC)
2204 #define REG_COMBO_PHY0_P1_5E_H       (REG_COMBO_PHY0_P1_BASE + 0xBD)
2205 #define REG_COMBO_PHY0_P1_5F_L       (REG_COMBO_PHY0_P1_BASE + 0xBE)
2206 #define REG_COMBO_PHY0_P1_5F_H       (REG_COMBO_PHY0_P1_BASE + 0xBF)
2207 #define REG_COMBO_PHY0_P1_60_L       (REG_COMBO_PHY0_P1_BASE + 0xC0)
2208 #define REG_COMBO_PHY0_P1_60_H       (REG_COMBO_PHY0_P1_BASE + 0xC1)
2209 #define REG_COMBO_PHY0_P1_61_L       (REG_COMBO_PHY0_P1_BASE + 0xC2)
2210 #define REG_COMBO_PHY0_P1_61_H       (REG_COMBO_PHY0_P1_BASE + 0xC3)
2211 #define REG_COMBO_PHY0_P1_62_L       (REG_COMBO_PHY0_P1_BASE + 0xC4)
2212 #define REG_COMBO_PHY0_P1_62_H       (REG_COMBO_PHY0_P1_BASE + 0xC5)
2213 #define REG_COMBO_PHY0_P1_63_L       (REG_COMBO_PHY0_P1_BASE + 0xC6)
2214 #define REG_COMBO_PHY0_P1_63_H       (REG_COMBO_PHY0_P1_BASE + 0xC7)
2215 #define REG_COMBO_PHY0_P1_64_L       (REG_COMBO_PHY0_P1_BASE + 0xC8)
2216 #define REG_COMBO_PHY0_P1_64_H       (REG_COMBO_PHY0_P1_BASE + 0xC9)
2217 #define REG_COMBO_PHY0_P1_65_L       (REG_COMBO_PHY0_P1_BASE + 0xCA)
2218 #define REG_COMBO_PHY0_P1_65_H       (REG_COMBO_PHY0_P1_BASE + 0xCB)
2219 #define REG_COMBO_PHY0_P1_66_L       (REG_COMBO_PHY0_P1_BASE + 0xCC)
2220 #define REG_COMBO_PHY0_P1_66_H       (REG_COMBO_PHY0_P1_BASE + 0xCD)
2221 #define REG_COMBO_PHY0_P1_67_L       (REG_COMBO_PHY0_P1_BASE + 0xCE)
2222 #define REG_COMBO_PHY0_P1_67_H       (REG_COMBO_PHY0_P1_BASE + 0xCF)
2223 #define REG_COMBO_PHY0_P1_68_L       (REG_COMBO_PHY0_P1_BASE + 0xD0)
2224 #define REG_COMBO_PHY0_P1_68_H       (REG_COMBO_PHY0_P1_BASE + 0xD1)
2225 #define REG_COMBO_PHY0_P1_69_L       (REG_COMBO_PHY0_P1_BASE + 0xD2)
2226 #define REG_COMBO_PHY0_P1_69_H       (REG_COMBO_PHY0_P1_BASE + 0xD3)
2227 #define REG_COMBO_PHY0_P1_6A_L       (REG_COMBO_PHY0_P1_BASE + 0xD4)
2228 #define REG_COMBO_PHY0_P1_6A_H       (REG_COMBO_PHY0_P1_BASE + 0xD5)
2229 #define REG_COMBO_PHY0_P1_6B_L       (REG_COMBO_PHY0_P1_BASE + 0xD6)
2230 #define REG_COMBO_PHY0_P1_6B_H       (REG_COMBO_PHY0_P1_BASE + 0xD7)
2231 #define REG_COMBO_PHY0_P1_6C_L       (REG_COMBO_PHY0_P1_BASE + 0xD8)
2232 #define REG_COMBO_PHY0_P1_6C_H       (REG_COMBO_PHY0_P1_BASE + 0xD9)
2233 #define REG_COMBO_PHY0_P1_6D_L       (REG_COMBO_PHY0_P1_BASE + 0xDA)
2234 #define REG_COMBO_PHY0_P1_6D_H       (REG_COMBO_PHY0_P1_BASE + 0xDB)
2235 #define REG_COMBO_PHY0_P1_6E_L       (REG_COMBO_PHY0_P1_BASE + 0xDC)
2236 #define REG_COMBO_PHY0_P1_6E_H       (REG_COMBO_PHY0_P1_BASE + 0xDD)
2237 #define REG_COMBO_PHY0_P1_6F_L       (REG_COMBO_PHY0_P1_BASE + 0xDE)
2238 #define REG_COMBO_PHY0_P1_6F_H       (REG_COMBO_PHY0_P1_BASE + 0xDF)
2239 #define REG_COMBO_PHY0_P1_70_L       (REG_COMBO_PHY0_P1_BASE + 0xE0)
2240 #define REG_COMBO_PHY0_P1_70_H       (REG_COMBO_PHY0_P1_BASE + 0xE1)
2241 #define REG_COMBO_PHY0_P1_71_L       (REG_COMBO_PHY0_P1_BASE + 0xE2)
2242 #define REG_COMBO_PHY0_P1_71_H       (REG_COMBO_PHY0_P1_BASE + 0xE3)
2243 #define REG_COMBO_PHY0_P1_72_L       (REG_COMBO_PHY0_P1_BASE + 0xE4)
2244 #define REG_COMBO_PHY0_P1_72_H       (REG_COMBO_PHY0_P1_BASE + 0xE5)
2245 #define REG_COMBO_PHY0_P1_73_L       (REG_COMBO_PHY0_P1_BASE + 0xE6)
2246 #define REG_COMBO_PHY0_P1_73_H       (REG_COMBO_PHY0_P1_BASE + 0xE7)
2247 #define REG_COMBO_PHY0_P1_74_L       (REG_COMBO_PHY0_P1_BASE + 0xE8)
2248 #define REG_COMBO_PHY0_P1_74_H       (REG_COMBO_PHY0_P1_BASE + 0xE9)
2249 #define REG_COMBO_PHY0_P1_75_L       (REG_COMBO_PHY0_P1_BASE + 0xEA)
2250 #define REG_COMBO_PHY0_P1_75_H       (REG_COMBO_PHY0_P1_BASE + 0xEB)
2251 #define REG_COMBO_PHY0_P1_76_L       (REG_COMBO_PHY0_P1_BASE + 0xEC)
2252 #define REG_COMBO_PHY0_P1_76_H       (REG_COMBO_PHY0_P1_BASE + 0xED)
2253 #define REG_COMBO_PHY0_P1_77_L       (REG_COMBO_PHY0_P1_BASE + 0xEE)
2254 #define REG_COMBO_PHY0_P1_77_H       (REG_COMBO_PHY0_P1_BASE + 0xEF)
2255 #define REG_COMBO_PHY0_P1_78_L       (REG_COMBO_PHY0_P1_BASE + 0xF0)
2256 #define REG_COMBO_PHY0_P1_78_H       (REG_COMBO_PHY0_P1_BASE + 0xF1)
2257 #define REG_COMBO_PHY0_P1_79_L       (REG_COMBO_PHY0_P1_BASE + 0xF2)
2258 #define REG_COMBO_PHY0_P1_79_H       (REG_COMBO_PHY0_P1_BASE + 0xF3)
2259 #define REG_COMBO_PHY0_P1_7A_L       (REG_COMBO_PHY0_P1_BASE + 0xF4)
2260 #define REG_COMBO_PHY0_P1_7A_H       (REG_COMBO_PHY0_P1_BASE + 0xF5)
2261 #define REG_COMBO_PHY0_P1_7B_L       (REG_COMBO_PHY0_P1_BASE + 0xF6)
2262 #define REG_COMBO_PHY0_P1_7B_H       (REG_COMBO_PHY0_P1_BASE + 0xF7)
2263 #define REG_COMBO_PHY0_P1_7C_L       (REG_COMBO_PHY0_P1_BASE + 0xF8)
2264 #define REG_COMBO_PHY0_P1_7C_H       (REG_COMBO_PHY0_P1_BASE + 0xF9)
2265 #define REG_COMBO_PHY0_P1_7D_L       (REG_COMBO_PHY0_P1_BASE + 0xFA)
2266 #define REG_COMBO_PHY0_P1_7D_H       (REG_COMBO_PHY0_P1_BASE + 0xFB)
2267 #define REG_COMBO_PHY0_P1_7E_L       (REG_COMBO_PHY0_P1_BASE + 0xFC)
2268 #define REG_COMBO_PHY0_P1_7E_H       (REG_COMBO_PHY0_P1_BASE + 0xFD)
2269 #define REG_COMBO_PHY0_P1_7F_L       (REG_COMBO_PHY0_P1_BASE + 0xFE)
2270 #define REG_COMBO_PHY0_P1_7F_H       (REG_COMBO_PHY0_P1_BASE + 0xFF)
2271 
2272 // COMBO_PHY1_P1
2273 #define REG_COMBO_PHY1_P1_00_L       (REG_COMBO_PHY1_P1_BASE + 0x00)
2274 #define REG_COMBO_PHY1_P1_00_H       (REG_COMBO_PHY1_P1_BASE + 0x01)
2275 #define REG_COMBO_PHY1_P1_01_L       (REG_COMBO_PHY1_P1_BASE + 0x02)
2276 #define REG_COMBO_PHY1_P1_01_H       (REG_COMBO_PHY1_P1_BASE + 0x03)
2277 #define REG_COMBO_PHY1_P1_02_L       (REG_COMBO_PHY1_P1_BASE + 0x04)
2278 #define REG_COMBO_PHY1_P1_02_H       (REG_COMBO_PHY1_P1_BASE + 0x05)
2279 #define REG_COMBO_PHY1_P1_03_L       (REG_COMBO_PHY1_P1_BASE + 0x06)
2280 #define REG_COMBO_PHY1_P1_03_H       (REG_COMBO_PHY1_P1_BASE + 0x07)
2281 #define REG_COMBO_PHY1_P1_04_L       (REG_COMBO_PHY1_P1_BASE + 0x08)
2282 #define REG_COMBO_PHY1_P1_04_H       (REG_COMBO_PHY1_P1_BASE + 0x09)
2283 #define REG_COMBO_PHY1_P1_05_L       (REG_COMBO_PHY1_P1_BASE + 0x0A)
2284 #define REG_COMBO_PHY1_P1_05_H       (REG_COMBO_PHY1_P1_BASE + 0x0B)
2285 #define REG_COMBO_PHY1_P1_06_L       (REG_COMBO_PHY1_P1_BASE + 0x0C)
2286 #define REG_COMBO_PHY1_P1_06_H       (REG_COMBO_PHY1_P1_BASE + 0x0D)
2287 #define REG_COMBO_PHY1_P1_07_L       (REG_COMBO_PHY1_P1_BASE + 0x0E)
2288 #define REG_COMBO_PHY1_P1_07_H       (REG_COMBO_PHY1_P1_BASE + 0x0F)
2289 #define REG_COMBO_PHY1_P1_08_L       (REG_COMBO_PHY1_P1_BASE + 0x10)
2290 #define REG_COMBO_PHY1_P1_08_H       (REG_COMBO_PHY1_P1_BASE + 0x11)
2291 #define REG_COMBO_PHY1_P1_09_L       (REG_COMBO_PHY1_P1_BASE + 0x12)
2292 #define REG_COMBO_PHY1_P1_09_H       (REG_COMBO_PHY1_P1_BASE + 0x13)
2293 #define REG_COMBO_PHY1_P1_0A_L       (REG_COMBO_PHY1_P1_BASE + 0x14)
2294 #define REG_COMBO_PHY1_P1_0A_H       (REG_COMBO_PHY1_P1_BASE + 0x15)
2295 #define REG_COMBO_PHY1_P1_0B_L       (REG_COMBO_PHY1_P1_BASE + 0x16)
2296 #define REG_COMBO_PHY1_P1_0B_H       (REG_COMBO_PHY1_P1_BASE + 0x17)
2297 #define REG_COMBO_PHY1_P1_0C_L       (REG_COMBO_PHY1_P1_BASE + 0x18)
2298 #define REG_COMBO_PHY1_P1_0C_H       (REG_COMBO_PHY1_P1_BASE + 0x19)
2299 #define REG_COMBO_PHY1_P1_0D_L       (REG_COMBO_PHY1_P1_BASE + 0x1A)
2300 #define REG_COMBO_PHY1_P1_0D_H       (REG_COMBO_PHY1_P1_BASE + 0x1B)
2301 #define REG_COMBO_PHY1_P1_0E_L       (REG_COMBO_PHY1_P1_BASE + 0x1C)
2302 #define REG_COMBO_PHY1_P1_0E_H       (REG_COMBO_PHY1_P1_BASE + 0x1D)
2303 #define REG_COMBO_PHY1_P1_0F_L       (REG_COMBO_PHY1_P1_BASE + 0x1E)
2304 #define REG_COMBO_PHY1_P1_0F_H       (REG_COMBO_PHY1_P1_BASE + 0x1F)
2305 #define REG_COMBO_PHY1_P1_10_L       (REG_COMBO_PHY1_P1_BASE + 0x20)
2306 #define REG_COMBO_PHY1_P1_10_H       (REG_COMBO_PHY1_P1_BASE + 0x21)
2307 #define REG_COMBO_PHY1_P1_11_L       (REG_COMBO_PHY1_P1_BASE + 0x22)
2308 #define REG_COMBO_PHY1_P1_11_H       (REG_COMBO_PHY1_P1_BASE + 0x23)
2309 #define REG_COMBO_PHY1_P1_12_L       (REG_COMBO_PHY1_P1_BASE + 0x24)
2310 #define REG_COMBO_PHY1_P1_12_H       (REG_COMBO_PHY1_P1_BASE + 0x25)
2311 #define REG_COMBO_PHY1_P1_13_L       (REG_COMBO_PHY1_P1_BASE + 0x26)
2312 #define REG_COMBO_PHY1_P1_13_H       (REG_COMBO_PHY1_P1_BASE + 0x27)
2313 #define REG_COMBO_PHY1_P1_14_L       (REG_COMBO_PHY1_P1_BASE + 0x28)
2314 #define REG_COMBO_PHY1_P1_14_H       (REG_COMBO_PHY1_P1_BASE + 0x29)
2315 #define REG_COMBO_PHY1_P1_15_L       (REG_COMBO_PHY1_P1_BASE + 0x2A)
2316 #define REG_COMBO_PHY1_P1_15_H       (REG_COMBO_PHY1_P1_BASE + 0x2B)
2317 #define REG_COMBO_PHY1_P1_16_L       (REG_COMBO_PHY1_P1_BASE + 0x2C)
2318 #define REG_COMBO_PHY1_P1_16_H       (REG_COMBO_PHY1_P1_BASE + 0x2D)
2319 #define REG_COMBO_PHY1_P1_17_L       (REG_COMBO_PHY1_P1_BASE + 0x2E)
2320 #define REG_COMBO_PHY1_P1_17_H       (REG_COMBO_PHY1_P1_BASE + 0x2F)
2321 #define REG_COMBO_PHY1_P1_18_L       (REG_COMBO_PHY1_P1_BASE + 0x30)
2322 #define REG_COMBO_PHY1_P1_18_H       (REG_COMBO_PHY1_P1_BASE + 0x31)
2323 #define REG_COMBO_PHY1_P1_19_L       (REG_COMBO_PHY1_P1_BASE + 0x32)
2324 #define REG_COMBO_PHY1_P1_19_H       (REG_COMBO_PHY1_P1_BASE + 0x33)
2325 #define REG_COMBO_PHY1_P1_1A_L       (REG_COMBO_PHY1_P1_BASE + 0x34)
2326 #define REG_COMBO_PHY1_P1_1A_H       (REG_COMBO_PHY1_P1_BASE + 0x35)
2327 #define REG_COMBO_PHY1_P1_1B_L       (REG_COMBO_PHY1_P1_BASE + 0x36)
2328 #define REG_COMBO_PHY1_P1_1B_H       (REG_COMBO_PHY1_P1_BASE + 0x37)
2329 #define REG_COMBO_PHY1_P1_1C_L       (REG_COMBO_PHY1_P1_BASE + 0x38)
2330 #define REG_COMBO_PHY1_P1_1C_H       (REG_COMBO_PHY1_P1_BASE + 0x39)
2331 #define REG_COMBO_PHY1_P1_1D_L       (REG_COMBO_PHY1_P1_BASE + 0x3A)
2332 #define REG_COMBO_PHY1_P1_1D_H       (REG_COMBO_PHY1_P1_BASE + 0x3B)
2333 #define REG_COMBO_PHY1_P1_1E_L       (REG_COMBO_PHY1_P1_BASE + 0x3C)
2334 #define REG_COMBO_PHY1_P1_1E_H       (REG_COMBO_PHY1_P1_BASE + 0x3D)
2335 #define REG_COMBO_PHY1_P1_1F_L       (REG_COMBO_PHY1_P1_BASE + 0x3E)
2336 #define REG_COMBO_PHY1_P1_1F_H       (REG_COMBO_PHY1_P1_BASE + 0x3F)
2337 #define REG_COMBO_PHY1_P1_20_L       (REG_COMBO_PHY1_P1_BASE + 0x40)
2338 #define REG_COMBO_PHY1_P1_20_H       (REG_COMBO_PHY1_P1_BASE + 0x41)
2339 #define REG_COMBO_PHY1_P1_21_L       (REG_COMBO_PHY1_P1_BASE + 0x42)
2340 #define REG_COMBO_PHY1_P1_21_H       (REG_COMBO_PHY1_P1_BASE + 0x43)
2341 #define REG_COMBO_PHY1_P1_22_L       (REG_COMBO_PHY1_P1_BASE + 0x44)
2342 #define REG_COMBO_PHY1_P1_22_H       (REG_COMBO_PHY1_P1_BASE + 0x45)
2343 #define REG_COMBO_PHY1_P1_23_L       (REG_COMBO_PHY1_P1_BASE + 0x46)
2344 #define REG_COMBO_PHY1_P1_23_H       (REG_COMBO_PHY1_P1_BASE + 0x47)
2345 #define REG_COMBO_PHY1_P1_24_L       (REG_COMBO_PHY1_P1_BASE + 0x48)
2346 #define REG_COMBO_PHY1_P1_24_H       (REG_COMBO_PHY1_P1_BASE + 0x49)
2347 #define REG_COMBO_PHY1_P1_25_L       (REG_COMBO_PHY1_P1_BASE + 0x4A)
2348 #define REG_COMBO_PHY1_P1_25_H       (REG_COMBO_PHY1_P1_BASE + 0x4B)
2349 #define REG_COMBO_PHY1_P1_26_L       (REG_COMBO_PHY1_P1_BASE + 0x4C)
2350 #define REG_COMBO_PHY1_P1_26_H       (REG_COMBO_PHY1_P1_BASE + 0x4D)
2351 #define REG_COMBO_PHY1_P1_27_L       (REG_COMBO_PHY1_P1_BASE + 0x4E)
2352 #define REG_COMBO_PHY1_P1_27_H       (REG_COMBO_PHY1_P1_BASE + 0x4F)
2353 #define REG_COMBO_PHY1_P1_28_L       (REG_COMBO_PHY1_P1_BASE + 0x50)
2354 #define REG_COMBO_PHY1_P1_28_H       (REG_COMBO_PHY1_P1_BASE + 0x51)
2355 #define REG_COMBO_PHY1_P1_29_L       (REG_COMBO_PHY1_P1_BASE + 0x52)
2356 #define REG_COMBO_PHY1_P1_29_H       (REG_COMBO_PHY1_P1_BASE + 0x53)
2357 #define REG_COMBO_PHY1_P1_2A_L       (REG_COMBO_PHY1_P1_BASE + 0x54)
2358 #define REG_COMBO_PHY1_P1_2A_H       (REG_COMBO_PHY1_P1_BASE + 0x55)
2359 #define REG_COMBO_PHY1_P1_2B_L       (REG_COMBO_PHY1_P1_BASE + 0x56)
2360 #define REG_COMBO_PHY1_P1_2B_H       (REG_COMBO_PHY1_P1_BASE + 0x57)
2361 #define REG_COMBO_PHY1_P1_2C_L       (REG_COMBO_PHY1_P1_BASE + 0x58)
2362 #define REG_COMBO_PHY1_P1_2C_H       (REG_COMBO_PHY1_P1_BASE + 0x59)
2363 #define REG_COMBO_PHY1_P1_2D_L       (REG_COMBO_PHY1_P1_BASE + 0x5A)
2364 #define REG_COMBO_PHY1_P1_2D_H       (REG_COMBO_PHY1_P1_BASE + 0x5B)
2365 #define REG_COMBO_PHY1_P1_2E_L       (REG_COMBO_PHY1_P1_BASE + 0x5C)
2366 #define REG_COMBO_PHY1_P1_2E_H       (REG_COMBO_PHY1_P1_BASE + 0x5D)
2367 #define REG_COMBO_PHY1_P1_2F_L       (REG_COMBO_PHY1_P1_BASE + 0x5E)
2368 #define REG_COMBO_PHY1_P1_2F_H       (REG_COMBO_PHY1_P1_BASE + 0x5F)
2369 #define REG_COMBO_PHY1_P1_30_L       (REG_COMBO_PHY1_P1_BASE + 0x60)
2370 #define REG_COMBO_PHY1_P1_30_H       (REG_COMBO_PHY1_P1_BASE + 0x61)
2371 #define REG_COMBO_PHY1_P1_31_L       (REG_COMBO_PHY1_P1_BASE + 0x62)
2372 #define REG_COMBO_PHY1_P1_31_H       (REG_COMBO_PHY1_P1_BASE + 0x63)
2373 #define REG_COMBO_PHY1_P1_32_L       (REG_COMBO_PHY1_P1_BASE + 0x64)
2374 #define REG_COMBO_PHY1_P1_32_H       (REG_COMBO_PHY1_P1_BASE + 0x65)
2375 #define REG_COMBO_PHY1_P1_33_L       (REG_COMBO_PHY1_P1_BASE + 0x66)
2376 #define REG_COMBO_PHY1_P1_33_H       (REG_COMBO_PHY1_P1_BASE + 0x67)
2377 #define REG_COMBO_PHY1_P1_34_L       (REG_COMBO_PHY1_P1_BASE + 0x68)
2378 #define REG_COMBO_PHY1_P1_34_H       (REG_COMBO_PHY1_P1_BASE + 0x69)
2379 #define REG_COMBO_PHY1_P1_35_L       (REG_COMBO_PHY1_P1_BASE + 0x6A)
2380 #define REG_COMBO_PHY1_P1_35_H       (REG_COMBO_PHY1_P1_BASE + 0x6B)
2381 #define REG_COMBO_PHY1_P1_36_L       (REG_COMBO_PHY1_P1_BASE + 0x6C)
2382 #define REG_COMBO_PHY1_P1_36_H       (REG_COMBO_PHY1_P1_BASE + 0x6D)
2383 #define REG_COMBO_PHY1_P1_37_L       (REG_COMBO_PHY1_P1_BASE + 0x6E)
2384 #define REG_COMBO_PHY1_P1_37_H       (REG_COMBO_PHY1_P1_BASE + 0x6F)
2385 #define REG_COMBO_PHY1_P1_38_L       (REG_COMBO_PHY1_P1_BASE + 0x70)
2386 #define REG_COMBO_PHY1_P1_38_H       (REG_COMBO_PHY1_P1_BASE + 0x71)
2387 #define REG_COMBO_PHY1_P1_39_L       (REG_COMBO_PHY1_P1_BASE + 0x72)
2388 #define REG_COMBO_PHY1_P1_39_H       (REG_COMBO_PHY1_P1_BASE + 0x73)
2389 #define REG_COMBO_PHY1_P1_3A_L       (REG_COMBO_PHY1_P1_BASE + 0x74)
2390 #define REG_COMBO_PHY1_P1_3A_H       (REG_COMBO_PHY1_P1_BASE + 0x75)
2391 #define REG_COMBO_PHY1_P1_3B_L       (REG_COMBO_PHY1_P1_BASE + 0x76)
2392 #define REG_COMBO_PHY1_P1_3B_H       (REG_COMBO_PHY1_P1_BASE + 0x77)
2393 #define REG_COMBO_PHY1_P1_3C_L       (REG_COMBO_PHY1_P1_BASE + 0x78)
2394 #define REG_COMBO_PHY1_P1_3C_H       (REG_COMBO_PHY1_P1_BASE + 0x79)
2395 #define REG_COMBO_PHY1_P1_3D_L       (REG_COMBO_PHY1_P1_BASE + 0x7A)
2396 #define REG_COMBO_PHY1_P1_3D_H       (REG_COMBO_PHY1_P1_BASE + 0x7B)
2397 #define REG_COMBO_PHY1_P1_3E_L       (REG_COMBO_PHY1_P1_BASE + 0x7C)
2398 #define REG_COMBO_PHY1_P1_3E_H       (REG_COMBO_PHY1_P1_BASE + 0x7D)
2399 #define REG_COMBO_PHY1_P1_3F_L       (REG_COMBO_PHY1_P1_BASE + 0x7E)
2400 #define REG_COMBO_PHY1_P1_3F_H       (REG_COMBO_PHY1_P1_BASE + 0x7F)
2401 #define REG_COMBO_PHY1_P1_40_L       (REG_COMBO_PHY1_P1_BASE + 0x80)
2402 #define REG_COMBO_PHY1_P1_40_H       (REG_COMBO_PHY1_P1_BASE + 0x81)
2403 #define REG_COMBO_PHY1_P1_41_L       (REG_COMBO_PHY1_P1_BASE + 0x82)
2404 #define REG_COMBO_PHY1_P1_41_H       (REG_COMBO_PHY1_P1_BASE + 0x83)
2405 #define REG_COMBO_PHY1_P1_42_L       (REG_COMBO_PHY1_P1_BASE + 0x84)
2406 #define REG_COMBO_PHY1_P1_42_H       (REG_COMBO_PHY1_P1_BASE + 0x85)
2407 #define REG_COMBO_PHY1_P1_43_L       (REG_COMBO_PHY1_P1_BASE + 0x86)
2408 #define REG_COMBO_PHY1_P1_43_H       (REG_COMBO_PHY1_P1_BASE + 0x87)
2409 #define REG_COMBO_PHY1_P1_44_L       (REG_COMBO_PHY1_P1_BASE + 0x88)
2410 #define REG_COMBO_PHY1_P1_44_H       (REG_COMBO_PHY1_P1_BASE + 0x89)
2411 #define REG_COMBO_PHY1_P1_45_L       (REG_COMBO_PHY1_P1_BASE + 0x8A)
2412 #define REG_COMBO_PHY1_P1_45_H       (REG_COMBO_PHY1_P1_BASE + 0x8B)
2413 #define REG_COMBO_PHY1_P1_46_L       (REG_COMBO_PHY1_P1_BASE + 0x8C)
2414 #define REG_COMBO_PHY1_P1_46_H       (REG_COMBO_PHY1_P1_BASE + 0x8D)
2415 #define REG_COMBO_PHY1_P1_47_L       (REG_COMBO_PHY1_P1_BASE + 0x8E)
2416 #define REG_COMBO_PHY1_P1_47_H       (REG_COMBO_PHY1_P1_BASE + 0x8F)
2417 #define REG_COMBO_PHY1_P1_48_L       (REG_COMBO_PHY1_P1_BASE + 0x90)
2418 #define REG_COMBO_PHY1_P1_48_H       (REG_COMBO_PHY1_P1_BASE + 0x91)
2419 #define REG_COMBO_PHY1_P1_49_L       (REG_COMBO_PHY1_P1_BASE + 0x92)
2420 #define REG_COMBO_PHY1_P1_49_H       (REG_COMBO_PHY1_P1_BASE + 0x93)
2421 #define REG_COMBO_PHY1_P1_4A_L       (REG_COMBO_PHY1_P1_BASE + 0x94)
2422 #define REG_COMBO_PHY1_P1_4A_H       (REG_COMBO_PHY1_P1_BASE + 0x95)
2423 #define REG_COMBO_PHY1_P1_4B_L       (REG_COMBO_PHY1_P1_BASE + 0x96)
2424 #define REG_COMBO_PHY1_P1_4B_H       (REG_COMBO_PHY1_P1_BASE + 0x97)
2425 #define REG_COMBO_PHY1_P1_4C_L       (REG_COMBO_PHY1_P1_BASE + 0x98)
2426 #define REG_COMBO_PHY1_P1_4C_H       (REG_COMBO_PHY1_P1_BASE + 0x99)
2427 #define REG_COMBO_PHY1_P1_4D_L       (REG_COMBO_PHY1_P1_BASE + 0x9A)
2428 #define REG_COMBO_PHY1_P1_4D_H       (REG_COMBO_PHY1_P1_BASE + 0x9B)
2429 #define REG_COMBO_PHY1_P1_4E_L       (REG_COMBO_PHY1_P1_BASE + 0x9C)
2430 #define REG_COMBO_PHY1_P1_4E_H       (REG_COMBO_PHY1_P1_BASE + 0x9D)
2431 #define REG_COMBO_PHY1_P1_4F_L       (REG_COMBO_PHY1_P1_BASE + 0x9E)
2432 #define REG_COMBO_PHY1_P1_4F_H       (REG_COMBO_PHY1_P1_BASE + 0x9F)
2433 #define REG_COMBO_PHY1_P1_50_L       (REG_COMBO_PHY1_P1_BASE + 0xA0)
2434 #define REG_COMBO_PHY1_P1_50_H       (REG_COMBO_PHY1_P1_BASE + 0xA1)
2435 #define REG_COMBO_PHY1_P1_51_L       (REG_COMBO_PHY1_P1_BASE + 0xA2)
2436 #define REG_COMBO_PHY1_P1_51_H       (REG_COMBO_PHY1_P1_BASE + 0xA3)
2437 #define REG_COMBO_PHY1_P1_52_L       (REG_COMBO_PHY1_P1_BASE + 0xA4)
2438 #define REG_COMBO_PHY1_P1_52_H       (REG_COMBO_PHY1_P1_BASE + 0xA5)
2439 #define REG_COMBO_PHY1_P1_53_L       (REG_COMBO_PHY1_P1_BASE + 0xA6)
2440 #define REG_COMBO_PHY1_P1_53_H       (REG_COMBO_PHY1_P1_BASE + 0xA7)
2441 #define REG_COMBO_PHY1_P1_54_L       (REG_COMBO_PHY1_P1_BASE + 0xA8)
2442 #define REG_COMBO_PHY1_P1_54_H       (REG_COMBO_PHY1_P1_BASE + 0xA9)
2443 #define REG_COMBO_PHY1_P1_55_L       (REG_COMBO_PHY1_P1_BASE + 0xAA)
2444 #define REG_COMBO_PHY1_P1_55_H       (REG_COMBO_PHY1_P1_BASE + 0xAB)
2445 #define REG_COMBO_PHY1_P1_56_L       (REG_COMBO_PHY1_P1_BASE + 0xAC)
2446 #define REG_COMBO_PHY1_P1_56_H       (REG_COMBO_PHY1_P1_BASE + 0xAD)
2447 #define REG_COMBO_PHY1_P1_57_L       (REG_COMBO_PHY1_P1_BASE + 0xAE)
2448 #define REG_COMBO_PHY1_P1_57_H       (REG_COMBO_PHY1_P1_BASE + 0xAF)
2449 #define REG_COMBO_PHY1_P1_58_L       (REG_COMBO_PHY1_P1_BASE + 0xB0)
2450 #define REG_COMBO_PHY1_P1_58_H       (REG_COMBO_PHY1_P1_BASE + 0xB1)
2451 #define REG_COMBO_PHY1_P1_59_L       (REG_COMBO_PHY1_P1_BASE + 0xB2)
2452 #define REG_COMBO_PHY1_P1_59_H       (REG_COMBO_PHY1_P1_BASE + 0xB3)
2453 #define REG_COMBO_PHY1_P1_5A_L       (REG_COMBO_PHY1_P1_BASE + 0xB4)
2454 #define REG_COMBO_PHY1_P1_5A_H       (REG_COMBO_PHY1_P1_BASE + 0xB5)
2455 #define REG_COMBO_PHY1_P1_5B_L       (REG_COMBO_PHY1_P1_BASE + 0xB6)
2456 #define REG_COMBO_PHY1_P1_5B_H       (REG_COMBO_PHY1_P1_BASE + 0xB7)
2457 #define REG_COMBO_PHY1_P1_5C_L       (REG_COMBO_PHY1_P1_BASE + 0xB8)
2458 #define REG_COMBO_PHY1_P1_5C_H       (REG_COMBO_PHY1_P1_BASE + 0xB9)
2459 #define REG_COMBO_PHY1_P1_5D_L       (REG_COMBO_PHY1_P1_BASE + 0xBA)
2460 #define REG_COMBO_PHY1_P1_5D_H       (REG_COMBO_PHY1_P1_BASE + 0xBB)
2461 #define REG_COMBO_PHY1_P1_5E_L       (REG_COMBO_PHY1_P1_BASE + 0xBC)
2462 #define REG_COMBO_PHY1_P1_5E_H       (REG_COMBO_PHY1_P1_BASE + 0xBD)
2463 #define REG_COMBO_PHY1_P1_5F_L       (REG_COMBO_PHY1_P1_BASE + 0xBE)
2464 #define REG_COMBO_PHY1_P1_5F_H       (REG_COMBO_PHY1_P1_BASE + 0xBF)
2465 #define REG_COMBO_PHY1_P1_60_L       (REG_COMBO_PHY1_P1_BASE + 0xC0)
2466 #define REG_COMBO_PHY1_P1_60_H       (REG_COMBO_PHY1_P1_BASE + 0xC1)
2467 #define REG_COMBO_PHY1_P1_61_L       (REG_COMBO_PHY1_P1_BASE + 0xC2)
2468 #define REG_COMBO_PHY1_P1_61_H       (REG_COMBO_PHY1_P1_BASE + 0xC3)
2469 #define REG_COMBO_PHY1_P1_62_L       (REG_COMBO_PHY1_P1_BASE + 0xC4)
2470 #define REG_COMBO_PHY1_P1_62_H       (REG_COMBO_PHY1_P1_BASE + 0xC5)
2471 #define REG_COMBO_PHY1_P1_63_L       (REG_COMBO_PHY1_P1_BASE + 0xC6)
2472 #define REG_COMBO_PHY1_P1_63_H       (REG_COMBO_PHY1_P1_BASE + 0xC7)
2473 #define REG_COMBO_PHY1_P1_64_L       (REG_COMBO_PHY1_P1_BASE + 0xC8)
2474 #define REG_COMBO_PHY1_P1_64_H       (REG_COMBO_PHY1_P1_BASE + 0xC9)
2475 #define REG_COMBO_PHY1_P1_65_L       (REG_COMBO_PHY1_P1_BASE + 0xCA)
2476 #define REG_COMBO_PHY1_P1_65_H       (REG_COMBO_PHY1_P1_BASE + 0xCB)
2477 #define REG_COMBO_PHY1_P1_66_L       (REG_COMBO_PHY1_P1_BASE + 0xCC)
2478 #define REG_COMBO_PHY1_P1_66_H       (REG_COMBO_PHY1_P1_BASE + 0xCD)
2479 #define REG_COMBO_PHY1_P1_67_L       (REG_COMBO_PHY1_P1_BASE + 0xCE)
2480 #define REG_COMBO_PHY1_P1_67_H       (REG_COMBO_PHY1_P1_BASE + 0xCF)
2481 #define REG_COMBO_PHY1_P1_68_L       (REG_COMBO_PHY1_P1_BASE + 0xD0)
2482 #define REG_COMBO_PHY1_P1_68_H       (REG_COMBO_PHY1_P1_BASE + 0xD1)
2483 #define REG_COMBO_PHY1_P1_69_L       (REG_COMBO_PHY1_P1_BASE + 0xD2)
2484 #define REG_COMBO_PHY1_P1_69_H       (REG_COMBO_PHY1_P1_BASE + 0xD3)
2485 #define REG_COMBO_PHY1_P1_6A_L       (REG_COMBO_PHY1_P1_BASE + 0xD4)
2486 #define REG_COMBO_PHY1_P1_6A_H       (REG_COMBO_PHY1_P1_BASE + 0xD5)
2487 #define REG_COMBO_PHY1_P1_6B_L       (REG_COMBO_PHY1_P1_BASE + 0xD6)
2488 #define REG_COMBO_PHY1_P1_6B_H       (REG_COMBO_PHY1_P1_BASE + 0xD7)
2489 #define REG_COMBO_PHY1_P1_6C_L       (REG_COMBO_PHY1_P1_BASE + 0xD8)
2490 #define REG_COMBO_PHY1_P1_6C_H       (REG_COMBO_PHY1_P1_BASE + 0xD9)
2491 #define REG_COMBO_PHY1_P1_6D_L       (REG_COMBO_PHY1_P1_BASE + 0xDA)
2492 #define REG_COMBO_PHY1_P1_6D_H       (REG_COMBO_PHY1_P1_BASE + 0xDB)
2493 #define REG_COMBO_PHY1_P1_6E_L       (REG_COMBO_PHY1_P1_BASE + 0xDC)
2494 #define REG_COMBO_PHY1_P1_6E_H       (REG_COMBO_PHY1_P1_BASE + 0xDD)
2495 #define REG_COMBO_PHY1_P1_6F_L       (REG_COMBO_PHY1_P1_BASE + 0xDE)
2496 #define REG_COMBO_PHY1_P1_6F_H       (REG_COMBO_PHY1_P1_BASE + 0xDF)
2497 #define REG_COMBO_PHY1_P1_70_L       (REG_COMBO_PHY1_P1_BASE + 0xE0)
2498 #define REG_COMBO_PHY1_P1_70_H       (REG_COMBO_PHY1_P1_BASE + 0xE1)
2499 #define REG_COMBO_PHY1_P1_71_L       (REG_COMBO_PHY1_P1_BASE + 0xE2)
2500 #define REG_COMBO_PHY1_P1_71_H       (REG_COMBO_PHY1_P1_BASE + 0xE3)
2501 #define REG_COMBO_PHY1_P1_72_L       (REG_COMBO_PHY1_P1_BASE + 0xE4)
2502 #define REG_COMBO_PHY1_P1_72_H       (REG_COMBO_PHY1_P1_BASE + 0xE5)
2503 #define REG_COMBO_PHY1_P1_73_L       (REG_COMBO_PHY1_P1_BASE + 0xE6)
2504 #define REG_COMBO_PHY1_P1_73_H       (REG_COMBO_PHY1_P1_BASE + 0xE7)
2505 #define REG_COMBO_PHY1_P1_74_L       (REG_COMBO_PHY1_P1_BASE + 0xE8)
2506 #define REG_COMBO_PHY1_P1_74_H       (REG_COMBO_PHY1_P1_BASE + 0xE9)
2507 #define REG_COMBO_PHY1_P1_75_L       (REG_COMBO_PHY1_P1_BASE + 0xEA)
2508 #define REG_COMBO_PHY1_P1_75_H       (REG_COMBO_PHY1_P1_BASE + 0xEB)
2509 #define REG_COMBO_PHY1_P1_76_L       (REG_COMBO_PHY1_P1_BASE + 0xEC)
2510 #define REG_COMBO_PHY1_P1_76_H       (REG_COMBO_PHY1_P1_BASE + 0xED)
2511 #define REG_COMBO_PHY1_P1_77_L       (REG_COMBO_PHY1_P1_BASE + 0xEE)
2512 #define REG_COMBO_PHY1_P1_77_H       (REG_COMBO_PHY1_P1_BASE + 0xEF)
2513 #define REG_COMBO_PHY1_P1_78_L       (REG_COMBO_PHY1_P1_BASE + 0xF0)
2514 #define REG_COMBO_PHY1_P1_78_H       (REG_COMBO_PHY1_P1_BASE + 0xF1)
2515 #define REG_COMBO_PHY1_P1_79_L       (REG_COMBO_PHY1_P1_BASE + 0xF2)
2516 #define REG_COMBO_PHY1_P1_79_H       (REG_COMBO_PHY1_P1_BASE + 0xF3)
2517 #define REG_COMBO_PHY1_P1_7A_L       (REG_COMBO_PHY1_P1_BASE + 0xF4)
2518 #define REG_COMBO_PHY1_P1_7A_H       (REG_COMBO_PHY1_P1_BASE + 0xF5)
2519 #define REG_COMBO_PHY1_P1_7B_L       (REG_COMBO_PHY1_P1_BASE + 0xF6)
2520 #define REG_COMBO_PHY1_P1_7B_H       (REG_COMBO_PHY1_P1_BASE + 0xF7)
2521 #define REG_COMBO_PHY1_P1_7C_L       (REG_COMBO_PHY1_P1_BASE + 0xF8)
2522 #define REG_COMBO_PHY1_P1_7C_H       (REG_COMBO_PHY1_P1_BASE + 0xF9)
2523 #define REG_COMBO_PHY1_P1_7D_L       (REG_COMBO_PHY1_P1_BASE + 0xFA)
2524 #define REG_COMBO_PHY1_P1_7D_H       (REG_COMBO_PHY1_P1_BASE + 0xFB)
2525 #define REG_COMBO_PHY1_P1_7E_L       (REG_COMBO_PHY1_P1_BASE + 0xFC)
2526 #define REG_COMBO_PHY1_P1_7E_H       (REG_COMBO_PHY1_P1_BASE + 0xFD)
2527 #define REG_COMBO_PHY1_P1_7F_L       (REG_COMBO_PHY1_P1_BASE + 0xFE)
2528 #define REG_COMBO_PHY1_P1_7F_H       (REG_COMBO_PHY1_P1_BASE + 0xFF)
2529 
2530 // COMBO_PHY0_P2
2531 #define REG_COMBO_PHY0_P2_00_L       (REG_COMBO_PHY0_P2_BASE + 0x00)
2532 #define REG_COMBO_PHY0_P2_00_H       (REG_COMBO_PHY0_P2_BASE + 0x01)
2533 #define REG_COMBO_PHY0_P2_01_L       (REG_COMBO_PHY0_P2_BASE + 0x02)
2534 #define REG_COMBO_PHY0_P2_01_H       (REG_COMBO_PHY0_P2_BASE + 0x03)
2535 #define REG_COMBO_PHY0_P2_02_L       (REG_COMBO_PHY0_P2_BASE + 0x04)
2536 #define REG_COMBO_PHY0_P2_02_H       (REG_COMBO_PHY0_P2_BASE + 0x05)
2537 #define REG_COMBO_PHY0_P2_03_L       (REG_COMBO_PHY0_P2_BASE + 0x06)
2538 #define REG_COMBO_PHY0_P2_03_H       (REG_COMBO_PHY0_P2_BASE + 0x07)
2539 #define REG_COMBO_PHY0_P2_04_L       (REG_COMBO_PHY0_P2_BASE + 0x08)
2540 #define REG_COMBO_PHY0_P2_04_H       (REG_COMBO_PHY0_P2_BASE + 0x09)
2541 #define REG_COMBO_PHY0_P2_05_L       (REG_COMBO_PHY0_P2_BASE + 0x0A)
2542 #define REG_COMBO_PHY0_P2_05_H       (REG_COMBO_PHY0_P2_BASE + 0x0B)
2543 #define REG_COMBO_PHY0_P2_06_L       (REG_COMBO_PHY0_P2_BASE + 0x0C)
2544 #define REG_COMBO_PHY0_P2_06_H       (REG_COMBO_PHY0_P2_BASE + 0x0D)
2545 #define REG_COMBO_PHY0_P2_07_L       (REG_COMBO_PHY0_P2_BASE + 0x0E)
2546 #define REG_COMBO_PHY0_P2_07_H       (REG_COMBO_PHY0_P2_BASE + 0x0F)
2547 #define REG_COMBO_PHY0_P2_08_L       (REG_COMBO_PHY0_P2_BASE + 0x10)
2548 #define REG_COMBO_PHY0_P2_08_H       (REG_COMBO_PHY0_P2_BASE + 0x11)
2549 #define REG_COMBO_PHY0_P2_09_L       (REG_COMBO_PHY0_P2_BASE + 0x12)
2550 #define REG_COMBO_PHY0_P2_09_H       (REG_COMBO_PHY0_P2_BASE + 0x13)
2551 #define REG_COMBO_PHY0_P2_0A_L       (REG_COMBO_PHY0_P2_BASE + 0x14)
2552 #define REG_COMBO_PHY0_P2_0A_H       (REG_COMBO_PHY0_P2_BASE + 0x15)
2553 #define REG_COMBO_PHY0_P2_0B_L       (REG_COMBO_PHY0_P2_BASE + 0x16)
2554 #define REG_COMBO_PHY0_P2_0B_H       (REG_COMBO_PHY0_P2_BASE + 0x17)
2555 #define REG_COMBO_PHY0_P2_0C_L       (REG_COMBO_PHY0_P2_BASE + 0x18)
2556 #define REG_COMBO_PHY0_P2_0C_H       (REG_COMBO_PHY0_P2_BASE + 0x19)
2557 #define REG_COMBO_PHY0_P2_0D_L       (REG_COMBO_PHY0_P2_BASE + 0x1A)
2558 #define REG_COMBO_PHY0_P2_0D_H       (REG_COMBO_PHY0_P2_BASE + 0x1B)
2559 #define REG_COMBO_PHY0_P2_0E_L       (REG_COMBO_PHY0_P2_BASE + 0x1C)
2560 #define REG_COMBO_PHY0_P2_0E_H       (REG_COMBO_PHY0_P2_BASE + 0x1D)
2561 #define REG_COMBO_PHY0_P2_0F_L       (REG_COMBO_PHY0_P2_BASE + 0x1E)
2562 #define REG_COMBO_PHY0_P2_0F_H       (REG_COMBO_PHY0_P2_BASE + 0x1F)
2563 #define REG_COMBO_PHY0_P2_10_L       (REG_COMBO_PHY0_P2_BASE + 0x20)
2564 #define REG_COMBO_PHY0_P2_10_H       (REG_COMBO_PHY0_P2_BASE + 0x21)
2565 #define REG_COMBO_PHY0_P2_11_L       (REG_COMBO_PHY0_P2_BASE + 0x22)
2566 #define REG_COMBO_PHY0_P2_11_H       (REG_COMBO_PHY0_P2_BASE + 0x23)
2567 #define REG_COMBO_PHY0_P2_12_L       (REG_COMBO_PHY0_P2_BASE + 0x24)
2568 #define REG_COMBO_PHY0_P2_12_H       (REG_COMBO_PHY0_P2_BASE + 0x25)
2569 #define REG_COMBO_PHY0_P2_13_L       (REG_COMBO_PHY0_P2_BASE + 0x26)
2570 #define REG_COMBO_PHY0_P2_13_H       (REG_COMBO_PHY0_P2_BASE + 0x27)
2571 #define REG_COMBO_PHY0_P2_14_L       (REG_COMBO_PHY0_P2_BASE + 0x28)
2572 #define REG_COMBO_PHY0_P2_14_H       (REG_COMBO_PHY0_P2_BASE + 0x29)
2573 #define REG_COMBO_PHY0_P2_15_L       (REG_COMBO_PHY0_P2_BASE + 0x2A)
2574 #define REG_COMBO_PHY0_P2_15_H       (REG_COMBO_PHY0_P2_BASE + 0x2B)
2575 #define REG_COMBO_PHY0_P2_16_L       (REG_COMBO_PHY0_P2_BASE + 0x2C)
2576 #define REG_COMBO_PHY0_P2_16_H       (REG_COMBO_PHY0_P2_BASE + 0x2D)
2577 #define REG_COMBO_PHY0_P2_17_L       (REG_COMBO_PHY0_P2_BASE + 0x2E)
2578 #define REG_COMBO_PHY0_P2_17_H       (REG_COMBO_PHY0_P2_BASE + 0x2F)
2579 #define REG_COMBO_PHY0_P2_18_L       (REG_COMBO_PHY0_P2_BASE + 0x30)
2580 #define REG_COMBO_PHY0_P2_18_H       (REG_COMBO_PHY0_P2_BASE + 0x31)
2581 #define REG_COMBO_PHY0_P2_19_L       (REG_COMBO_PHY0_P2_BASE + 0x32)
2582 #define REG_COMBO_PHY0_P2_19_H       (REG_COMBO_PHY0_P2_BASE + 0x33)
2583 #define REG_COMBO_PHY0_P2_1A_L       (REG_COMBO_PHY0_P2_BASE + 0x34)
2584 #define REG_COMBO_PHY0_P2_1A_H       (REG_COMBO_PHY0_P2_BASE + 0x35)
2585 #define REG_COMBO_PHY0_P2_1B_L       (REG_COMBO_PHY0_P2_BASE + 0x36)
2586 #define REG_COMBO_PHY0_P2_1B_H       (REG_COMBO_PHY0_P2_BASE + 0x37)
2587 #define REG_COMBO_PHY0_P2_1C_L       (REG_COMBO_PHY0_P2_BASE + 0x38)
2588 #define REG_COMBO_PHY0_P2_1C_H       (REG_COMBO_PHY0_P2_BASE + 0x39)
2589 #define REG_COMBO_PHY0_P2_1D_L       (REG_COMBO_PHY0_P2_BASE + 0x3A)
2590 #define REG_COMBO_PHY0_P2_1D_H       (REG_COMBO_PHY0_P2_BASE + 0x3B)
2591 #define REG_COMBO_PHY0_P2_1E_L       (REG_COMBO_PHY0_P2_BASE + 0x3C)
2592 #define REG_COMBO_PHY0_P2_1E_H       (REG_COMBO_PHY0_P2_BASE + 0x3D)
2593 #define REG_COMBO_PHY0_P2_1F_L       (REG_COMBO_PHY0_P2_BASE + 0x3E)
2594 #define REG_COMBO_PHY0_P2_1F_H       (REG_COMBO_PHY0_P2_BASE + 0x3F)
2595 #define REG_COMBO_PHY0_P2_20_L       (REG_COMBO_PHY0_P2_BASE + 0x40)
2596 #define REG_COMBO_PHY0_P2_20_H       (REG_COMBO_PHY0_P2_BASE + 0x41)
2597 #define REG_COMBO_PHY0_P2_21_L       (REG_COMBO_PHY0_P2_BASE + 0x42)
2598 #define REG_COMBO_PHY0_P2_21_H       (REG_COMBO_PHY0_P2_BASE + 0x43)
2599 #define REG_COMBO_PHY0_P2_22_L       (REG_COMBO_PHY0_P2_BASE + 0x44)
2600 #define REG_COMBO_PHY0_P2_22_H       (REG_COMBO_PHY0_P2_BASE + 0x45)
2601 #define REG_COMBO_PHY0_P2_23_L       (REG_COMBO_PHY0_P2_BASE + 0x46)
2602 #define REG_COMBO_PHY0_P2_23_H       (REG_COMBO_PHY0_P2_BASE + 0x47)
2603 #define REG_COMBO_PHY0_P2_24_L       (REG_COMBO_PHY0_P2_BASE + 0x48)
2604 #define REG_COMBO_PHY0_P2_24_H       (REG_COMBO_PHY0_P2_BASE + 0x49)
2605 #define REG_COMBO_PHY0_P2_25_L       (REG_COMBO_PHY0_P2_BASE + 0x4A)
2606 #define REG_COMBO_PHY0_P2_25_H       (REG_COMBO_PHY0_P2_BASE + 0x4B)
2607 #define REG_COMBO_PHY0_P2_26_L       (REG_COMBO_PHY0_P2_BASE + 0x4C)
2608 #define REG_COMBO_PHY0_P2_26_H       (REG_COMBO_PHY0_P2_BASE + 0x4D)
2609 #define REG_COMBO_PHY0_P2_27_L       (REG_COMBO_PHY0_P2_BASE + 0x4E)
2610 #define REG_COMBO_PHY0_P2_27_H       (REG_COMBO_PHY0_P2_BASE + 0x4F)
2611 #define REG_COMBO_PHY0_P2_28_L       (REG_COMBO_PHY0_P2_BASE + 0x50)
2612 #define REG_COMBO_PHY0_P2_28_H       (REG_COMBO_PHY0_P2_BASE + 0x51)
2613 #define REG_COMBO_PHY0_P2_29_L       (REG_COMBO_PHY0_P2_BASE + 0x52)
2614 #define REG_COMBO_PHY0_P2_29_H       (REG_COMBO_PHY0_P2_BASE + 0x53)
2615 #define REG_COMBO_PHY0_P2_2A_L       (REG_COMBO_PHY0_P2_BASE + 0x54)
2616 #define REG_COMBO_PHY0_P2_2A_H       (REG_COMBO_PHY0_P2_BASE + 0x55)
2617 #define REG_COMBO_PHY0_P2_2B_L       (REG_COMBO_PHY0_P2_BASE + 0x56)
2618 #define REG_COMBO_PHY0_P2_2B_H       (REG_COMBO_PHY0_P2_BASE + 0x57)
2619 #define REG_COMBO_PHY0_P2_2C_L       (REG_COMBO_PHY0_P2_BASE + 0x58)
2620 #define REG_COMBO_PHY0_P2_2C_H       (REG_COMBO_PHY0_P2_BASE + 0x59)
2621 #define REG_COMBO_PHY0_P2_2D_L       (REG_COMBO_PHY0_P2_BASE + 0x5A)
2622 #define REG_COMBO_PHY0_P2_2D_H       (REG_COMBO_PHY0_P2_BASE + 0x5B)
2623 #define REG_COMBO_PHY0_P2_2E_L       (REG_COMBO_PHY0_P2_BASE + 0x5C)
2624 #define REG_COMBO_PHY0_P2_2E_H       (REG_COMBO_PHY0_P2_BASE + 0x5D)
2625 #define REG_COMBO_PHY0_P2_2F_L       (REG_COMBO_PHY0_P2_BASE + 0x5E)
2626 #define REG_COMBO_PHY0_P2_2F_H       (REG_COMBO_PHY0_P2_BASE + 0x5F)
2627 #define REG_COMBO_PHY0_P2_30_L       (REG_COMBO_PHY0_P2_BASE + 0x60)
2628 #define REG_COMBO_PHY0_P2_30_H       (REG_COMBO_PHY0_P2_BASE + 0x61)
2629 #define REG_COMBO_PHY0_P2_31_L       (REG_COMBO_PHY0_P2_BASE + 0x62)
2630 #define REG_COMBO_PHY0_P2_31_H       (REG_COMBO_PHY0_P2_BASE + 0x63)
2631 #define REG_COMBO_PHY0_P2_32_L       (REG_COMBO_PHY0_P2_BASE + 0x64)
2632 #define REG_COMBO_PHY0_P2_32_H       (REG_COMBO_PHY0_P2_BASE + 0x65)
2633 #define REG_COMBO_PHY0_P2_33_L       (REG_COMBO_PHY0_P2_BASE + 0x66)
2634 #define REG_COMBO_PHY0_P2_33_H       (REG_COMBO_PHY0_P2_BASE + 0x67)
2635 #define REG_COMBO_PHY0_P2_34_L       (REG_COMBO_PHY0_P2_BASE + 0x68)
2636 #define REG_COMBO_PHY0_P2_34_H       (REG_COMBO_PHY0_P2_BASE + 0x69)
2637 #define REG_COMBO_PHY0_P2_35_L       (REG_COMBO_PHY0_P2_BASE + 0x6A)
2638 #define REG_COMBO_PHY0_P2_35_H       (REG_COMBO_PHY0_P2_BASE + 0x6B)
2639 #define REG_COMBO_PHY0_P2_36_L       (REG_COMBO_PHY0_P2_BASE + 0x6C)
2640 #define REG_COMBO_PHY0_P2_36_H       (REG_COMBO_PHY0_P2_BASE + 0x6D)
2641 #define REG_COMBO_PHY0_P2_37_L       (REG_COMBO_PHY0_P2_BASE + 0x6E)
2642 #define REG_COMBO_PHY0_P2_37_H       (REG_COMBO_PHY0_P2_BASE + 0x6F)
2643 #define REG_COMBO_PHY0_P2_38_L       (REG_COMBO_PHY0_P2_BASE + 0x70)
2644 #define REG_COMBO_PHY0_P2_38_H       (REG_COMBO_PHY0_P2_BASE + 0x71)
2645 #define REG_COMBO_PHY0_P2_39_L       (REG_COMBO_PHY0_P2_BASE + 0x72)
2646 #define REG_COMBO_PHY0_P2_39_H       (REG_COMBO_PHY0_P2_BASE + 0x73)
2647 #define REG_COMBO_PHY0_P2_3A_L       (REG_COMBO_PHY0_P2_BASE + 0x74)
2648 #define REG_COMBO_PHY0_P2_3A_H       (REG_COMBO_PHY0_P2_BASE + 0x75)
2649 #define REG_COMBO_PHY0_P2_3B_L       (REG_COMBO_PHY0_P2_BASE + 0x76)
2650 #define REG_COMBO_PHY0_P2_3B_H       (REG_COMBO_PHY0_P2_BASE + 0x77)
2651 #define REG_COMBO_PHY0_P2_3C_L       (REG_COMBO_PHY0_P2_BASE + 0x78)
2652 #define REG_COMBO_PHY0_P2_3C_H       (REG_COMBO_PHY0_P2_BASE + 0x79)
2653 #define REG_COMBO_PHY0_P2_3D_L       (REG_COMBO_PHY0_P2_BASE + 0x7A)
2654 #define REG_COMBO_PHY0_P2_3D_H       (REG_COMBO_PHY0_P2_BASE + 0x7B)
2655 #define REG_COMBO_PHY0_P2_3E_L       (REG_COMBO_PHY0_P2_BASE + 0x7C)
2656 #define REG_COMBO_PHY0_P2_3E_H       (REG_COMBO_PHY0_P2_BASE + 0x7D)
2657 #define REG_COMBO_PHY0_P2_3F_L       (REG_COMBO_PHY0_P2_BASE + 0x7E)
2658 #define REG_COMBO_PHY0_P2_3F_H       (REG_COMBO_PHY0_P2_BASE + 0x7F)
2659 #define REG_COMBO_PHY0_P2_40_L       (REG_COMBO_PHY0_P2_BASE + 0x80)
2660 #define REG_COMBO_PHY0_P2_40_H       (REG_COMBO_PHY0_P2_BASE + 0x81)
2661 #define REG_COMBO_PHY0_P2_41_L       (REG_COMBO_PHY0_P2_BASE + 0x82)
2662 #define REG_COMBO_PHY0_P2_41_H       (REG_COMBO_PHY0_P2_BASE + 0x83)
2663 #define REG_COMBO_PHY0_P2_42_L       (REG_COMBO_PHY0_P2_BASE + 0x84)
2664 #define REG_COMBO_PHY0_P2_42_H       (REG_COMBO_PHY0_P2_BASE + 0x85)
2665 #define REG_COMBO_PHY0_P2_43_L       (REG_COMBO_PHY0_P2_BASE + 0x86)
2666 #define REG_COMBO_PHY0_P2_43_H       (REG_COMBO_PHY0_P2_BASE + 0x87)
2667 #define REG_COMBO_PHY0_P2_44_L       (REG_COMBO_PHY0_P2_BASE + 0x88)
2668 #define REG_COMBO_PHY0_P2_44_H       (REG_COMBO_PHY0_P2_BASE + 0x89)
2669 #define REG_COMBO_PHY0_P2_45_L       (REG_COMBO_PHY0_P2_BASE + 0x8A)
2670 #define REG_COMBO_PHY0_P2_45_H       (REG_COMBO_PHY0_P2_BASE + 0x8B)
2671 #define REG_COMBO_PHY0_P2_46_L       (REG_COMBO_PHY0_P2_BASE + 0x8C)
2672 #define REG_COMBO_PHY0_P2_46_H       (REG_COMBO_PHY0_P2_BASE + 0x8D)
2673 #define REG_COMBO_PHY0_P2_47_L       (REG_COMBO_PHY0_P2_BASE + 0x8E)
2674 #define REG_COMBO_PHY0_P2_47_H       (REG_COMBO_PHY0_P2_BASE + 0x8F)
2675 #define REG_COMBO_PHY0_P2_48_L       (REG_COMBO_PHY0_P2_BASE + 0x90)
2676 #define REG_COMBO_PHY0_P2_48_H       (REG_COMBO_PHY0_P2_BASE + 0x91)
2677 #define REG_COMBO_PHY0_P2_49_L       (REG_COMBO_PHY0_P2_BASE + 0x92)
2678 #define REG_COMBO_PHY0_P2_49_H       (REG_COMBO_PHY0_P2_BASE + 0x93)
2679 #define REG_COMBO_PHY0_P2_4A_L       (REG_COMBO_PHY0_P2_BASE + 0x94)
2680 #define REG_COMBO_PHY0_P2_4A_H       (REG_COMBO_PHY0_P2_BASE + 0x95)
2681 #define REG_COMBO_PHY0_P2_4B_L       (REG_COMBO_PHY0_P2_BASE + 0x96)
2682 #define REG_COMBO_PHY0_P2_4B_H       (REG_COMBO_PHY0_P2_BASE + 0x97)
2683 #define REG_COMBO_PHY0_P2_4C_L       (REG_COMBO_PHY0_P2_BASE + 0x98)
2684 #define REG_COMBO_PHY0_P2_4C_H       (REG_COMBO_PHY0_P2_BASE + 0x99)
2685 #define REG_COMBO_PHY0_P2_4D_L       (REG_COMBO_PHY0_P2_BASE + 0x9A)
2686 #define REG_COMBO_PHY0_P2_4D_H       (REG_COMBO_PHY0_P2_BASE + 0x9B)
2687 #define REG_COMBO_PHY0_P2_4E_L       (REG_COMBO_PHY0_P2_BASE + 0x9C)
2688 #define REG_COMBO_PHY0_P2_4E_H       (REG_COMBO_PHY0_P2_BASE + 0x9D)
2689 #define REG_COMBO_PHY0_P2_4F_L       (REG_COMBO_PHY0_P2_BASE + 0x9E)
2690 #define REG_COMBO_PHY0_P2_4F_H       (REG_COMBO_PHY0_P2_BASE + 0x9F)
2691 #define REG_COMBO_PHY0_P2_50_L       (REG_COMBO_PHY0_P2_BASE + 0xA0)
2692 #define REG_COMBO_PHY0_P2_50_H       (REG_COMBO_PHY0_P2_BASE + 0xA1)
2693 #define REG_COMBO_PHY0_P2_51_L       (REG_COMBO_PHY0_P2_BASE + 0xA2)
2694 #define REG_COMBO_PHY0_P2_51_H       (REG_COMBO_PHY0_P2_BASE + 0xA3)
2695 #define REG_COMBO_PHY0_P2_52_L       (REG_COMBO_PHY0_P2_BASE + 0xA4)
2696 #define REG_COMBO_PHY0_P2_52_H       (REG_COMBO_PHY0_P2_BASE + 0xA5)
2697 #define REG_COMBO_PHY0_P2_53_L       (REG_COMBO_PHY0_P2_BASE + 0xA6)
2698 #define REG_COMBO_PHY0_P2_53_H       (REG_COMBO_PHY0_P2_BASE + 0xA7)
2699 #define REG_COMBO_PHY0_P2_54_L       (REG_COMBO_PHY0_P2_BASE + 0xA8)
2700 #define REG_COMBO_PHY0_P2_54_H       (REG_COMBO_PHY0_P2_BASE + 0xA9)
2701 #define REG_COMBO_PHY0_P2_55_L       (REG_COMBO_PHY0_P2_BASE + 0xAA)
2702 #define REG_COMBO_PHY0_P2_55_H       (REG_COMBO_PHY0_P2_BASE + 0xAB)
2703 #define REG_COMBO_PHY0_P2_56_L       (REG_COMBO_PHY0_P2_BASE + 0xAC)
2704 #define REG_COMBO_PHY0_P2_56_H       (REG_COMBO_PHY0_P2_BASE + 0xAD)
2705 #define REG_COMBO_PHY0_P2_57_L       (REG_COMBO_PHY0_P2_BASE + 0xAE)
2706 #define REG_COMBO_PHY0_P2_57_H       (REG_COMBO_PHY0_P2_BASE + 0xAF)
2707 #define REG_COMBO_PHY0_P2_58_L       (REG_COMBO_PHY0_P2_BASE + 0xB0)
2708 #define REG_COMBO_PHY0_P2_58_H       (REG_COMBO_PHY0_P2_BASE + 0xB1)
2709 #define REG_COMBO_PHY0_P2_59_L       (REG_COMBO_PHY0_P2_BASE + 0xB2)
2710 #define REG_COMBO_PHY0_P2_59_H       (REG_COMBO_PHY0_P2_BASE + 0xB3)
2711 #define REG_COMBO_PHY0_P2_5A_L       (REG_COMBO_PHY0_P2_BASE + 0xB4)
2712 #define REG_COMBO_PHY0_P2_5A_H       (REG_COMBO_PHY0_P2_BASE + 0xB5)
2713 #define REG_COMBO_PHY0_P2_5B_L       (REG_COMBO_PHY0_P2_BASE + 0xB6)
2714 #define REG_COMBO_PHY0_P2_5B_H       (REG_COMBO_PHY0_P2_BASE + 0xB7)
2715 #define REG_COMBO_PHY0_P2_5C_L       (REG_COMBO_PHY0_P2_BASE + 0xB8)
2716 #define REG_COMBO_PHY0_P2_5C_H       (REG_COMBO_PHY0_P2_BASE + 0xB9)
2717 #define REG_COMBO_PHY0_P2_5D_L       (REG_COMBO_PHY0_P2_BASE + 0xBA)
2718 #define REG_COMBO_PHY0_P2_5D_H       (REG_COMBO_PHY0_P2_BASE + 0xBB)
2719 #define REG_COMBO_PHY0_P2_5E_L       (REG_COMBO_PHY0_P2_BASE + 0xBC)
2720 #define REG_COMBO_PHY0_P2_5E_H       (REG_COMBO_PHY0_P2_BASE + 0xBD)
2721 #define REG_COMBO_PHY0_P2_5F_L       (REG_COMBO_PHY0_P2_BASE + 0xBE)
2722 #define REG_COMBO_PHY0_P2_5F_H       (REG_COMBO_PHY0_P2_BASE + 0xBF)
2723 #define REG_COMBO_PHY0_P2_60_L       (REG_COMBO_PHY0_P2_BASE + 0xC0)
2724 #define REG_COMBO_PHY0_P2_60_H       (REG_COMBO_PHY0_P2_BASE + 0xC1)
2725 #define REG_COMBO_PHY0_P2_61_L       (REG_COMBO_PHY0_P2_BASE + 0xC2)
2726 #define REG_COMBO_PHY0_P2_61_H       (REG_COMBO_PHY0_P2_BASE + 0xC3)
2727 #define REG_COMBO_PHY0_P2_62_L       (REG_COMBO_PHY0_P2_BASE + 0xC4)
2728 #define REG_COMBO_PHY0_P2_62_H       (REG_COMBO_PHY0_P2_BASE + 0xC5)
2729 #define REG_COMBO_PHY0_P2_63_L       (REG_COMBO_PHY0_P2_BASE + 0xC6)
2730 #define REG_COMBO_PHY0_P2_63_H       (REG_COMBO_PHY0_P2_BASE + 0xC7)
2731 #define REG_COMBO_PHY0_P2_64_L       (REG_COMBO_PHY0_P2_BASE + 0xC8)
2732 #define REG_COMBO_PHY0_P2_64_H       (REG_COMBO_PHY0_P2_BASE + 0xC9)
2733 #define REG_COMBO_PHY0_P2_65_L       (REG_COMBO_PHY0_P2_BASE + 0xCA)
2734 #define REG_COMBO_PHY0_P2_65_H       (REG_COMBO_PHY0_P2_BASE + 0xCB)
2735 #define REG_COMBO_PHY0_P2_66_L       (REG_COMBO_PHY0_P2_BASE + 0xCC)
2736 #define REG_COMBO_PHY0_P2_66_H       (REG_COMBO_PHY0_P2_BASE + 0xCD)
2737 #define REG_COMBO_PHY0_P2_67_L       (REG_COMBO_PHY0_P2_BASE + 0xCE)
2738 #define REG_COMBO_PHY0_P2_67_H       (REG_COMBO_PHY0_P2_BASE + 0xCF)
2739 #define REG_COMBO_PHY0_P2_68_L       (REG_COMBO_PHY0_P2_BASE + 0xD0)
2740 #define REG_COMBO_PHY0_P2_68_H       (REG_COMBO_PHY0_P2_BASE + 0xD1)
2741 #define REG_COMBO_PHY0_P2_69_L       (REG_COMBO_PHY0_P2_BASE + 0xD2)
2742 #define REG_COMBO_PHY0_P2_69_H       (REG_COMBO_PHY0_P2_BASE + 0xD3)
2743 #define REG_COMBO_PHY0_P2_6A_L       (REG_COMBO_PHY0_P2_BASE + 0xD4)
2744 #define REG_COMBO_PHY0_P2_6A_H       (REG_COMBO_PHY0_P2_BASE + 0xD5)
2745 #define REG_COMBO_PHY0_P2_6B_L       (REG_COMBO_PHY0_P2_BASE + 0xD6)
2746 #define REG_COMBO_PHY0_P2_6B_H       (REG_COMBO_PHY0_P2_BASE + 0xD7)
2747 #define REG_COMBO_PHY0_P2_6C_L       (REG_COMBO_PHY0_P2_BASE + 0xD8)
2748 #define REG_COMBO_PHY0_P2_6C_H       (REG_COMBO_PHY0_P2_BASE + 0xD9)
2749 #define REG_COMBO_PHY0_P2_6D_L       (REG_COMBO_PHY0_P2_BASE + 0xDA)
2750 #define REG_COMBO_PHY0_P2_6D_H       (REG_COMBO_PHY0_P2_BASE + 0xDB)
2751 #define REG_COMBO_PHY0_P2_6E_L       (REG_COMBO_PHY0_P2_BASE + 0xDC)
2752 #define REG_COMBO_PHY0_P2_6E_H       (REG_COMBO_PHY0_P2_BASE + 0xDD)
2753 #define REG_COMBO_PHY0_P2_6F_L       (REG_COMBO_PHY0_P2_BASE + 0xDE)
2754 #define REG_COMBO_PHY0_P2_6F_H       (REG_COMBO_PHY0_P2_BASE + 0xDF)
2755 #define REG_COMBO_PHY0_P2_70_L       (REG_COMBO_PHY0_P2_BASE + 0xE0)
2756 #define REG_COMBO_PHY0_P2_70_H       (REG_COMBO_PHY0_P2_BASE + 0xE1)
2757 #define REG_COMBO_PHY0_P2_71_L       (REG_COMBO_PHY0_P2_BASE + 0xE2)
2758 #define REG_COMBO_PHY0_P2_71_H       (REG_COMBO_PHY0_P2_BASE + 0xE3)
2759 #define REG_COMBO_PHY0_P2_72_L       (REG_COMBO_PHY0_P2_BASE + 0xE4)
2760 #define REG_COMBO_PHY0_P2_72_H       (REG_COMBO_PHY0_P2_BASE + 0xE5)
2761 #define REG_COMBO_PHY0_P2_73_L       (REG_COMBO_PHY0_P2_BASE + 0xE6)
2762 #define REG_COMBO_PHY0_P2_73_H       (REG_COMBO_PHY0_P2_BASE + 0xE7)
2763 #define REG_COMBO_PHY0_P2_74_L       (REG_COMBO_PHY0_P2_BASE + 0xE8)
2764 #define REG_COMBO_PHY0_P2_74_H       (REG_COMBO_PHY0_P2_BASE + 0xE9)
2765 #define REG_COMBO_PHY0_P2_75_L       (REG_COMBO_PHY0_P2_BASE + 0xEA)
2766 #define REG_COMBO_PHY0_P2_75_H       (REG_COMBO_PHY0_P2_BASE + 0xEB)
2767 #define REG_COMBO_PHY0_P2_76_L       (REG_COMBO_PHY0_P2_BASE + 0xEC)
2768 #define REG_COMBO_PHY0_P2_76_H       (REG_COMBO_PHY0_P2_BASE + 0xED)
2769 #define REG_COMBO_PHY0_P2_77_L       (REG_COMBO_PHY0_P2_BASE + 0xEE)
2770 #define REG_COMBO_PHY0_P2_77_H       (REG_COMBO_PHY0_P2_BASE + 0xEF)
2771 #define REG_COMBO_PHY0_P2_78_L       (REG_COMBO_PHY0_P2_BASE + 0xF0)
2772 #define REG_COMBO_PHY0_P2_78_H       (REG_COMBO_PHY0_P2_BASE + 0xF1)
2773 #define REG_COMBO_PHY0_P2_79_L       (REG_COMBO_PHY0_P2_BASE + 0xF2)
2774 #define REG_COMBO_PHY0_P2_79_H       (REG_COMBO_PHY0_P2_BASE + 0xF3)
2775 #define REG_COMBO_PHY0_P2_7A_L       (REG_COMBO_PHY0_P2_BASE + 0xF4)
2776 #define REG_COMBO_PHY0_P2_7A_H       (REG_COMBO_PHY0_P2_BASE + 0xF5)
2777 #define REG_COMBO_PHY0_P2_7B_L       (REG_COMBO_PHY0_P2_BASE + 0xF6)
2778 #define REG_COMBO_PHY0_P2_7B_H       (REG_COMBO_PHY0_P2_BASE + 0xF7)
2779 #define REG_COMBO_PHY0_P2_7C_L       (REG_COMBO_PHY0_P2_BASE + 0xF8)
2780 #define REG_COMBO_PHY0_P2_7C_H       (REG_COMBO_PHY0_P2_BASE + 0xF9)
2781 #define REG_COMBO_PHY0_P2_7D_L       (REG_COMBO_PHY0_P2_BASE + 0xFA)
2782 #define REG_COMBO_PHY0_P2_7D_H       (REG_COMBO_PHY0_P2_BASE + 0xFB)
2783 #define REG_COMBO_PHY0_P2_7E_L       (REG_COMBO_PHY0_P2_BASE + 0xFC)
2784 #define REG_COMBO_PHY0_P2_7E_H       (REG_COMBO_PHY0_P2_BASE + 0xFD)
2785 #define REG_COMBO_PHY0_P2_7F_L       (REG_COMBO_PHY0_P2_BASE + 0xFE)
2786 #define REG_COMBO_PHY0_P2_7F_H       (REG_COMBO_PHY0_P2_BASE + 0xFF)
2787 
2788 // COMBO_PHY1_P2
2789 #define REG_COMBO_PHY1_P2_00_L       (REG_COMBO_PHY1_P2_BASE + 0x00)
2790 #define REG_COMBO_PHY1_P2_00_H       (REG_COMBO_PHY1_P2_BASE + 0x01)
2791 #define REG_COMBO_PHY1_P2_01_L       (REG_COMBO_PHY1_P2_BASE + 0x02)
2792 #define REG_COMBO_PHY1_P2_01_H       (REG_COMBO_PHY1_P2_BASE + 0x03)
2793 #define REG_COMBO_PHY1_P2_02_L       (REG_COMBO_PHY1_P2_BASE + 0x04)
2794 #define REG_COMBO_PHY1_P2_02_H       (REG_COMBO_PHY1_P2_BASE + 0x05)
2795 #define REG_COMBO_PHY1_P2_03_L       (REG_COMBO_PHY1_P2_BASE + 0x06)
2796 #define REG_COMBO_PHY1_P2_03_H       (REG_COMBO_PHY1_P2_BASE + 0x07)
2797 #define REG_COMBO_PHY1_P2_04_L       (REG_COMBO_PHY1_P2_BASE + 0x08)
2798 #define REG_COMBO_PHY1_P2_04_H       (REG_COMBO_PHY1_P2_BASE + 0x09)
2799 #define REG_COMBO_PHY1_P2_05_L       (REG_COMBO_PHY1_P2_BASE + 0x0A)
2800 #define REG_COMBO_PHY1_P2_05_H       (REG_COMBO_PHY1_P2_BASE + 0x0B)
2801 #define REG_COMBO_PHY1_P2_06_L       (REG_COMBO_PHY1_P2_BASE + 0x0C)
2802 #define REG_COMBO_PHY1_P2_06_H       (REG_COMBO_PHY1_P2_BASE + 0x0D)
2803 #define REG_COMBO_PHY1_P2_07_L       (REG_COMBO_PHY1_P2_BASE + 0x0E)
2804 #define REG_COMBO_PHY1_P2_07_H       (REG_COMBO_PHY1_P2_BASE + 0x0F)
2805 #define REG_COMBO_PHY1_P2_08_L       (REG_COMBO_PHY1_P2_BASE + 0x10)
2806 #define REG_COMBO_PHY1_P2_08_H       (REG_COMBO_PHY1_P2_BASE + 0x11)
2807 #define REG_COMBO_PHY1_P2_09_L       (REG_COMBO_PHY1_P2_BASE + 0x12)
2808 #define REG_COMBO_PHY1_P2_09_H       (REG_COMBO_PHY1_P2_BASE + 0x13)
2809 #define REG_COMBO_PHY1_P2_0A_L       (REG_COMBO_PHY1_P2_BASE + 0x14)
2810 #define REG_COMBO_PHY1_P2_0A_H       (REG_COMBO_PHY1_P2_BASE + 0x15)
2811 #define REG_COMBO_PHY1_P2_0B_L       (REG_COMBO_PHY1_P2_BASE + 0x16)
2812 #define REG_COMBO_PHY1_P2_0B_H       (REG_COMBO_PHY1_P2_BASE + 0x17)
2813 #define REG_COMBO_PHY1_P2_0C_L       (REG_COMBO_PHY1_P2_BASE + 0x18)
2814 #define REG_COMBO_PHY1_P2_0C_H       (REG_COMBO_PHY1_P2_BASE + 0x19)
2815 #define REG_COMBO_PHY1_P2_0D_L       (REG_COMBO_PHY1_P2_BASE + 0x1A)
2816 #define REG_COMBO_PHY1_P2_0D_H       (REG_COMBO_PHY1_P2_BASE + 0x1B)
2817 #define REG_COMBO_PHY1_P2_0E_L       (REG_COMBO_PHY1_P2_BASE + 0x1C)
2818 #define REG_COMBO_PHY1_P2_0E_H       (REG_COMBO_PHY1_P2_BASE + 0x1D)
2819 #define REG_COMBO_PHY1_P2_0F_L       (REG_COMBO_PHY1_P2_BASE + 0x1E)
2820 #define REG_COMBO_PHY1_P2_0F_H       (REG_COMBO_PHY1_P2_BASE + 0x1F)
2821 #define REG_COMBO_PHY1_P2_10_L       (REG_COMBO_PHY1_P2_BASE + 0x20)
2822 #define REG_COMBO_PHY1_P2_10_H       (REG_COMBO_PHY1_P2_BASE + 0x21)
2823 #define REG_COMBO_PHY1_P2_11_L       (REG_COMBO_PHY1_P2_BASE + 0x22)
2824 #define REG_COMBO_PHY1_P2_11_H       (REG_COMBO_PHY1_P2_BASE + 0x23)
2825 #define REG_COMBO_PHY1_P2_12_L       (REG_COMBO_PHY1_P2_BASE + 0x24)
2826 #define REG_COMBO_PHY1_P2_12_H       (REG_COMBO_PHY1_P2_BASE + 0x25)
2827 #define REG_COMBO_PHY1_P2_13_L       (REG_COMBO_PHY1_P2_BASE + 0x26)
2828 #define REG_COMBO_PHY1_P2_13_H       (REG_COMBO_PHY1_P2_BASE + 0x27)
2829 #define REG_COMBO_PHY1_P2_14_L       (REG_COMBO_PHY1_P2_BASE + 0x28)
2830 #define REG_COMBO_PHY1_P2_14_H       (REG_COMBO_PHY1_P2_BASE + 0x29)
2831 #define REG_COMBO_PHY1_P2_15_L       (REG_COMBO_PHY1_P2_BASE + 0x2A)
2832 #define REG_COMBO_PHY1_P2_15_H       (REG_COMBO_PHY1_P2_BASE + 0x2B)
2833 #define REG_COMBO_PHY1_P2_16_L       (REG_COMBO_PHY1_P2_BASE + 0x2C)
2834 #define REG_COMBO_PHY1_P2_16_H       (REG_COMBO_PHY1_P2_BASE + 0x2D)
2835 #define REG_COMBO_PHY1_P2_17_L       (REG_COMBO_PHY1_P2_BASE + 0x2E)
2836 #define REG_COMBO_PHY1_P2_17_H       (REG_COMBO_PHY1_P2_BASE + 0x2F)
2837 #define REG_COMBO_PHY1_P2_18_L       (REG_COMBO_PHY1_P2_BASE + 0x30)
2838 #define REG_COMBO_PHY1_P2_18_H       (REG_COMBO_PHY1_P2_BASE + 0x31)
2839 #define REG_COMBO_PHY1_P2_19_L       (REG_COMBO_PHY1_P2_BASE + 0x32)
2840 #define REG_COMBO_PHY1_P2_19_H       (REG_COMBO_PHY1_P2_BASE + 0x33)
2841 #define REG_COMBO_PHY1_P2_1A_L       (REG_COMBO_PHY1_P2_BASE + 0x34)
2842 #define REG_COMBO_PHY1_P2_1A_H       (REG_COMBO_PHY1_P2_BASE + 0x35)
2843 #define REG_COMBO_PHY1_P2_1B_L       (REG_COMBO_PHY1_P2_BASE + 0x36)
2844 #define REG_COMBO_PHY1_P2_1B_H       (REG_COMBO_PHY1_P2_BASE + 0x37)
2845 #define REG_COMBO_PHY1_P2_1C_L       (REG_COMBO_PHY1_P2_BASE + 0x38)
2846 #define REG_COMBO_PHY1_P2_1C_H       (REG_COMBO_PHY1_P2_BASE + 0x39)
2847 #define REG_COMBO_PHY1_P2_1D_L       (REG_COMBO_PHY1_P2_BASE + 0x3A)
2848 #define REG_COMBO_PHY1_P2_1D_H       (REG_COMBO_PHY1_P2_BASE + 0x3B)
2849 #define REG_COMBO_PHY1_P2_1E_L       (REG_COMBO_PHY1_P2_BASE + 0x3C)
2850 #define REG_COMBO_PHY1_P2_1E_H       (REG_COMBO_PHY1_P2_BASE + 0x3D)
2851 #define REG_COMBO_PHY1_P2_1F_L       (REG_COMBO_PHY1_P2_BASE + 0x3E)
2852 #define REG_COMBO_PHY1_P2_1F_H       (REG_COMBO_PHY1_P2_BASE + 0x3F)
2853 #define REG_COMBO_PHY1_P2_20_L       (REG_COMBO_PHY1_P2_BASE + 0x40)
2854 #define REG_COMBO_PHY1_P2_20_H       (REG_COMBO_PHY1_P2_BASE + 0x41)
2855 #define REG_COMBO_PHY1_P2_21_L       (REG_COMBO_PHY1_P2_BASE + 0x42)
2856 #define REG_COMBO_PHY1_P2_21_H       (REG_COMBO_PHY1_P2_BASE + 0x43)
2857 #define REG_COMBO_PHY1_P2_22_L       (REG_COMBO_PHY1_P2_BASE + 0x44)
2858 #define REG_COMBO_PHY1_P2_22_H       (REG_COMBO_PHY1_P2_BASE + 0x45)
2859 #define REG_COMBO_PHY1_P2_23_L       (REG_COMBO_PHY1_P2_BASE + 0x46)
2860 #define REG_COMBO_PHY1_P2_23_H       (REG_COMBO_PHY1_P2_BASE + 0x47)
2861 #define REG_COMBO_PHY1_P2_24_L       (REG_COMBO_PHY1_P2_BASE + 0x48)
2862 #define REG_COMBO_PHY1_P2_24_H       (REG_COMBO_PHY1_P2_BASE + 0x49)
2863 #define REG_COMBO_PHY1_P2_25_L       (REG_COMBO_PHY1_P2_BASE + 0x4A)
2864 #define REG_COMBO_PHY1_P2_25_H       (REG_COMBO_PHY1_P2_BASE + 0x4B)
2865 #define REG_COMBO_PHY1_P2_26_L       (REG_COMBO_PHY1_P2_BASE + 0x4C)
2866 #define REG_COMBO_PHY1_P2_26_H       (REG_COMBO_PHY1_P2_BASE + 0x4D)
2867 #define REG_COMBO_PHY1_P2_27_L       (REG_COMBO_PHY1_P2_BASE + 0x4E)
2868 #define REG_COMBO_PHY1_P2_27_H       (REG_COMBO_PHY1_P2_BASE + 0x4F)
2869 #define REG_COMBO_PHY1_P2_28_L       (REG_COMBO_PHY1_P2_BASE + 0x50)
2870 #define REG_COMBO_PHY1_P2_28_H       (REG_COMBO_PHY1_P2_BASE + 0x51)
2871 #define REG_COMBO_PHY1_P2_29_L       (REG_COMBO_PHY1_P2_BASE + 0x52)
2872 #define REG_COMBO_PHY1_P2_29_H       (REG_COMBO_PHY1_P2_BASE + 0x53)
2873 #define REG_COMBO_PHY1_P2_2A_L       (REG_COMBO_PHY1_P2_BASE + 0x54)
2874 #define REG_COMBO_PHY1_P2_2A_H       (REG_COMBO_PHY1_P2_BASE + 0x55)
2875 #define REG_COMBO_PHY1_P2_2B_L       (REG_COMBO_PHY1_P2_BASE + 0x56)
2876 #define REG_COMBO_PHY1_P2_2B_H       (REG_COMBO_PHY1_P2_BASE + 0x57)
2877 #define REG_COMBO_PHY1_P2_2C_L       (REG_COMBO_PHY1_P2_BASE + 0x58)
2878 #define REG_COMBO_PHY1_P2_2C_H       (REG_COMBO_PHY1_P2_BASE + 0x59)
2879 #define REG_COMBO_PHY1_P2_2D_L       (REG_COMBO_PHY1_P2_BASE + 0x5A)
2880 #define REG_COMBO_PHY1_P2_2D_H       (REG_COMBO_PHY1_P2_BASE + 0x5B)
2881 #define REG_COMBO_PHY1_P2_2E_L       (REG_COMBO_PHY1_P2_BASE + 0x5C)
2882 #define REG_COMBO_PHY1_P2_2E_H       (REG_COMBO_PHY1_P2_BASE + 0x5D)
2883 #define REG_COMBO_PHY1_P2_2F_L       (REG_COMBO_PHY1_P2_BASE + 0x5E)
2884 #define REG_COMBO_PHY1_P2_2F_H       (REG_COMBO_PHY1_P2_BASE + 0x5F)
2885 #define REG_COMBO_PHY1_P2_30_L       (REG_COMBO_PHY1_P2_BASE + 0x60)
2886 #define REG_COMBO_PHY1_P2_30_H       (REG_COMBO_PHY1_P2_BASE + 0x61)
2887 #define REG_COMBO_PHY1_P2_31_L       (REG_COMBO_PHY1_P2_BASE + 0x62)
2888 #define REG_COMBO_PHY1_P2_31_H       (REG_COMBO_PHY1_P2_BASE + 0x63)
2889 #define REG_COMBO_PHY1_P2_32_L       (REG_COMBO_PHY1_P2_BASE + 0x64)
2890 #define REG_COMBO_PHY1_P2_32_H       (REG_COMBO_PHY1_P2_BASE + 0x65)
2891 #define REG_COMBO_PHY1_P2_33_L       (REG_COMBO_PHY1_P2_BASE + 0x66)
2892 #define REG_COMBO_PHY1_P2_33_H       (REG_COMBO_PHY1_P2_BASE + 0x67)
2893 #define REG_COMBO_PHY1_P2_34_L       (REG_COMBO_PHY1_P2_BASE + 0x68)
2894 #define REG_COMBO_PHY1_P2_34_H       (REG_COMBO_PHY1_P2_BASE + 0x69)
2895 #define REG_COMBO_PHY1_P2_35_L       (REG_COMBO_PHY1_P2_BASE + 0x6A)
2896 #define REG_COMBO_PHY1_P2_35_H       (REG_COMBO_PHY1_P2_BASE + 0x6B)
2897 #define REG_COMBO_PHY1_P2_36_L       (REG_COMBO_PHY1_P2_BASE + 0x6C)
2898 #define REG_COMBO_PHY1_P2_36_H       (REG_COMBO_PHY1_P2_BASE + 0x6D)
2899 #define REG_COMBO_PHY1_P2_37_L       (REG_COMBO_PHY1_P2_BASE + 0x6E)
2900 #define REG_COMBO_PHY1_P2_37_H       (REG_COMBO_PHY1_P2_BASE + 0x6F)
2901 #define REG_COMBO_PHY1_P2_38_L       (REG_COMBO_PHY1_P2_BASE + 0x70)
2902 #define REG_COMBO_PHY1_P2_38_H       (REG_COMBO_PHY1_P2_BASE + 0x71)
2903 #define REG_COMBO_PHY1_P2_39_L       (REG_COMBO_PHY1_P2_BASE + 0x72)
2904 #define REG_COMBO_PHY1_P2_39_H       (REG_COMBO_PHY1_P2_BASE + 0x73)
2905 #define REG_COMBO_PHY1_P2_3A_L       (REG_COMBO_PHY1_P2_BASE + 0x74)
2906 #define REG_COMBO_PHY1_P2_3A_H       (REG_COMBO_PHY1_P2_BASE + 0x75)
2907 #define REG_COMBO_PHY1_P2_3B_L       (REG_COMBO_PHY1_P2_BASE + 0x76)
2908 #define REG_COMBO_PHY1_P2_3B_H       (REG_COMBO_PHY1_P2_BASE + 0x77)
2909 #define REG_COMBO_PHY1_P2_3C_L       (REG_COMBO_PHY1_P2_BASE + 0x78)
2910 #define REG_COMBO_PHY1_P2_3C_H       (REG_COMBO_PHY1_P2_BASE + 0x79)
2911 #define REG_COMBO_PHY1_P2_3D_L       (REG_COMBO_PHY1_P2_BASE + 0x7A)
2912 #define REG_COMBO_PHY1_P2_3D_H       (REG_COMBO_PHY1_P2_BASE + 0x7B)
2913 #define REG_COMBO_PHY1_P2_3E_L       (REG_COMBO_PHY1_P2_BASE + 0x7C)
2914 #define REG_COMBO_PHY1_P2_3E_H       (REG_COMBO_PHY1_P2_BASE + 0x7D)
2915 #define REG_COMBO_PHY1_P2_3F_L       (REG_COMBO_PHY1_P2_BASE + 0x7E)
2916 #define REG_COMBO_PHY1_P2_3F_H       (REG_COMBO_PHY1_P2_BASE + 0x7F)
2917 #define REG_COMBO_PHY1_P2_40_L       (REG_COMBO_PHY1_P2_BASE + 0x80)
2918 #define REG_COMBO_PHY1_P2_40_H       (REG_COMBO_PHY1_P2_BASE + 0x81)
2919 #define REG_COMBO_PHY1_P2_41_L       (REG_COMBO_PHY1_P2_BASE + 0x82)
2920 #define REG_COMBO_PHY1_P2_41_H       (REG_COMBO_PHY1_P2_BASE + 0x83)
2921 #define REG_COMBO_PHY1_P2_42_L       (REG_COMBO_PHY1_P2_BASE + 0x84)
2922 #define REG_COMBO_PHY1_P2_42_H       (REG_COMBO_PHY1_P2_BASE + 0x85)
2923 #define REG_COMBO_PHY1_P2_43_L       (REG_COMBO_PHY1_P2_BASE + 0x86)
2924 #define REG_COMBO_PHY1_P2_43_H       (REG_COMBO_PHY1_P2_BASE + 0x87)
2925 #define REG_COMBO_PHY1_P2_44_L       (REG_COMBO_PHY1_P2_BASE + 0x88)
2926 #define REG_COMBO_PHY1_P2_44_H       (REG_COMBO_PHY1_P2_BASE + 0x89)
2927 #define REG_COMBO_PHY1_P2_45_L       (REG_COMBO_PHY1_P2_BASE + 0x8A)
2928 #define REG_COMBO_PHY1_P2_45_H       (REG_COMBO_PHY1_P2_BASE + 0x8B)
2929 #define REG_COMBO_PHY1_P2_46_L       (REG_COMBO_PHY1_P2_BASE + 0x8C)
2930 #define REG_COMBO_PHY1_P2_46_H       (REG_COMBO_PHY1_P2_BASE + 0x8D)
2931 #define REG_COMBO_PHY1_P2_47_L       (REG_COMBO_PHY1_P2_BASE + 0x8E)
2932 #define REG_COMBO_PHY1_P2_47_H       (REG_COMBO_PHY1_P2_BASE + 0x8F)
2933 #define REG_COMBO_PHY1_P2_48_L       (REG_COMBO_PHY1_P2_BASE + 0x90)
2934 #define REG_COMBO_PHY1_P2_48_H       (REG_COMBO_PHY1_P2_BASE + 0x91)
2935 #define REG_COMBO_PHY1_P2_49_L       (REG_COMBO_PHY1_P2_BASE + 0x92)
2936 #define REG_COMBO_PHY1_P2_49_H       (REG_COMBO_PHY1_P2_BASE + 0x93)
2937 #define REG_COMBO_PHY1_P2_4A_L       (REG_COMBO_PHY1_P2_BASE + 0x94)
2938 #define REG_COMBO_PHY1_P2_4A_H       (REG_COMBO_PHY1_P2_BASE + 0x95)
2939 #define REG_COMBO_PHY1_P2_4B_L       (REG_COMBO_PHY1_P2_BASE + 0x96)
2940 #define REG_COMBO_PHY1_P2_4B_H       (REG_COMBO_PHY1_P2_BASE + 0x97)
2941 #define REG_COMBO_PHY1_P2_4C_L       (REG_COMBO_PHY1_P2_BASE + 0x98)
2942 #define REG_COMBO_PHY1_P2_4C_H       (REG_COMBO_PHY1_P2_BASE + 0x99)
2943 #define REG_COMBO_PHY1_P2_4D_L       (REG_COMBO_PHY1_P2_BASE + 0x9A)
2944 #define REG_COMBO_PHY1_P2_4D_H       (REG_COMBO_PHY1_P2_BASE + 0x9B)
2945 #define REG_COMBO_PHY1_P2_4E_L       (REG_COMBO_PHY1_P2_BASE + 0x9C)
2946 #define REG_COMBO_PHY1_P2_4E_H       (REG_COMBO_PHY1_P2_BASE + 0x9D)
2947 #define REG_COMBO_PHY1_P2_4F_L       (REG_COMBO_PHY1_P2_BASE + 0x9E)
2948 #define REG_COMBO_PHY1_P2_4F_H       (REG_COMBO_PHY1_P2_BASE + 0x9F)
2949 #define REG_COMBO_PHY1_P2_50_L       (REG_COMBO_PHY1_P2_BASE + 0xA0)
2950 #define REG_COMBO_PHY1_P2_50_H       (REG_COMBO_PHY1_P2_BASE + 0xA1)
2951 #define REG_COMBO_PHY1_P2_51_L       (REG_COMBO_PHY1_P2_BASE + 0xA2)
2952 #define REG_COMBO_PHY1_P2_51_H       (REG_COMBO_PHY1_P2_BASE + 0xA3)
2953 #define REG_COMBO_PHY1_P2_52_L       (REG_COMBO_PHY1_P2_BASE + 0xA4)
2954 #define REG_COMBO_PHY1_P2_52_H       (REG_COMBO_PHY1_P2_BASE + 0xA5)
2955 #define REG_COMBO_PHY1_P2_53_L       (REG_COMBO_PHY1_P2_BASE + 0xA6)
2956 #define REG_COMBO_PHY1_P2_53_H       (REG_COMBO_PHY1_P2_BASE + 0xA7)
2957 #define REG_COMBO_PHY1_P2_54_L       (REG_COMBO_PHY1_P2_BASE + 0xA8)
2958 #define REG_COMBO_PHY1_P2_54_H       (REG_COMBO_PHY1_P2_BASE + 0xA9)
2959 #define REG_COMBO_PHY1_P2_55_L       (REG_COMBO_PHY1_P2_BASE + 0xAA)
2960 #define REG_COMBO_PHY1_P2_55_H       (REG_COMBO_PHY1_P2_BASE + 0xAB)
2961 #define REG_COMBO_PHY1_P2_56_L       (REG_COMBO_PHY1_P2_BASE + 0xAC)
2962 #define REG_COMBO_PHY1_P2_56_H       (REG_COMBO_PHY1_P2_BASE + 0xAD)
2963 #define REG_COMBO_PHY1_P2_57_L       (REG_COMBO_PHY1_P2_BASE + 0xAE)
2964 #define REG_COMBO_PHY1_P2_57_H       (REG_COMBO_PHY1_P2_BASE + 0xAF)
2965 #define REG_COMBO_PHY1_P2_58_L       (REG_COMBO_PHY1_P2_BASE + 0xB0)
2966 #define REG_COMBO_PHY1_P2_58_H       (REG_COMBO_PHY1_P2_BASE + 0xB1)
2967 #define REG_COMBO_PHY1_P2_59_L       (REG_COMBO_PHY1_P2_BASE + 0xB2)
2968 #define REG_COMBO_PHY1_P2_59_H       (REG_COMBO_PHY1_P2_BASE + 0xB3)
2969 #define REG_COMBO_PHY1_P2_5A_L       (REG_COMBO_PHY1_P2_BASE + 0xB4)
2970 #define REG_COMBO_PHY1_P2_5A_H       (REG_COMBO_PHY1_P2_BASE + 0xB5)
2971 #define REG_COMBO_PHY1_P2_5B_L       (REG_COMBO_PHY1_P2_BASE + 0xB6)
2972 #define REG_COMBO_PHY1_P2_5B_H       (REG_COMBO_PHY1_P2_BASE + 0xB7)
2973 #define REG_COMBO_PHY1_P2_5C_L       (REG_COMBO_PHY1_P2_BASE + 0xB8)
2974 #define REG_COMBO_PHY1_P2_5C_H       (REG_COMBO_PHY1_P2_BASE + 0xB9)
2975 #define REG_COMBO_PHY1_P2_5D_L       (REG_COMBO_PHY1_P2_BASE + 0xBA)
2976 #define REG_COMBO_PHY1_P2_5D_H       (REG_COMBO_PHY1_P2_BASE + 0xBB)
2977 #define REG_COMBO_PHY1_P2_5E_L       (REG_COMBO_PHY1_P2_BASE + 0xBC)
2978 #define REG_COMBO_PHY1_P2_5E_H       (REG_COMBO_PHY1_P2_BASE + 0xBD)
2979 #define REG_COMBO_PHY1_P2_5F_L       (REG_COMBO_PHY1_P2_BASE + 0xBE)
2980 #define REG_COMBO_PHY1_P2_5F_H       (REG_COMBO_PHY1_P2_BASE + 0xBF)
2981 #define REG_COMBO_PHY1_P2_60_L       (REG_COMBO_PHY1_P2_BASE + 0xC0)
2982 #define REG_COMBO_PHY1_P2_60_H       (REG_COMBO_PHY1_P2_BASE + 0xC1)
2983 #define REG_COMBO_PHY1_P2_61_L       (REG_COMBO_PHY1_P2_BASE + 0xC2)
2984 #define REG_COMBO_PHY1_P2_61_H       (REG_COMBO_PHY1_P2_BASE + 0xC3)
2985 #define REG_COMBO_PHY1_P2_62_L       (REG_COMBO_PHY1_P2_BASE + 0xC4)
2986 #define REG_COMBO_PHY1_P2_62_H       (REG_COMBO_PHY1_P2_BASE + 0xC5)
2987 #define REG_COMBO_PHY1_P2_63_L       (REG_COMBO_PHY1_P2_BASE + 0xC6)
2988 #define REG_COMBO_PHY1_P2_63_H       (REG_COMBO_PHY1_P2_BASE + 0xC7)
2989 #define REG_COMBO_PHY1_P2_64_L       (REG_COMBO_PHY1_P2_BASE + 0xC8)
2990 #define REG_COMBO_PHY1_P2_64_H       (REG_COMBO_PHY1_P2_BASE + 0xC9)
2991 #define REG_COMBO_PHY1_P2_65_L       (REG_COMBO_PHY1_P2_BASE + 0xCA)
2992 #define REG_COMBO_PHY1_P2_65_H       (REG_COMBO_PHY1_P2_BASE + 0xCB)
2993 #define REG_COMBO_PHY1_P2_66_L       (REG_COMBO_PHY1_P2_BASE + 0xCC)
2994 #define REG_COMBO_PHY1_P2_66_H       (REG_COMBO_PHY1_P2_BASE + 0xCD)
2995 #define REG_COMBO_PHY1_P2_67_L       (REG_COMBO_PHY1_P2_BASE + 0xCE)
2996 #define REG_COMBO_PHY1_P2_67_H       (REG_COMBO_PHY1_P2_BASE + 0xCF)
2997 #define REG_COMBO_PHY1_P2_68_L       (REG_COMBO_PHY1_P2_BASE + 0xD0)
2998 #define REG_COMBO_PHY1_P2_68_H       (REG_COMBO_PHY1_P2_BASE + 0xD1)
2999 #define REG_COMBO_PHY1_P2_69_L       (REG_COMBO_PHY1_P2_BASE + 0xD2)
3000 #define REG_COMBO_PHY1_P2_69_H       (REG_COMBO_PHY1_P2_BASE + 0xD3)
3001 #define REG_COMBO_PHY1_P2_6A_L       (REG_COMBO_PHY1_P2_BASE + 0xD4)
3002 #define REG_COMBO_PHY1_P2_6A_H       (REG_COMBO_PHY1_P2_BASE + 0xD5)
3003 #define REG_COMBO_PHY1_P2_6B_L       (REG_COMBO_PHY1_P2_BASE + 0xD6)
3004 #define REG_COMBO_PHY1_P2_6B_H       (REG_COMBO_PHY1_P2_BASE + 0xD7)
3005 #define REG_COMBO_PHY1_P2_6C_L       (REG_COMBO_PHY1_P2_BASE + 0xD8)
3006 #define REG_COMBO_PHY1_P2_6C_H       (REG_COMBO_PHY1_P2_BASE + 0xD9)
3007 #define REG_COMBO_PHY1_P2_6D_L       (REG_COMBO_PHY1_P2_BASE + 0xDA)
3008 #define REG_COMBO_PHY1_P2_6D_H       (REG_COMBO_PHY1_P2_BASE + 0xDB)
3009 #define REG_COMBO_PHY1_P2_6E_L       (REG_COMBO_PHY1_P2_BASE + 0xDC)
3010 #define REG_COMBO_PHY1_P2_6E_H       (REG_COMBO_PHY1_P2_BASE + 0xDD)
3011 #define REG_COMBO_PHY1_P2_6F_L       (REG_COMBO_PHY1_P2_BASE + 0xDE)
3012 #define REG_COMBO_PHY1_P2_6F_H       (REG_COMBO_PHY1_P2_BASE + 0xDF)
3013 #define REG_COMBO_PHY1_P2_70_L       (REG_COMBO_PHY1_P2_BASE + 0xE0)
3014 #define REG_COMBO_PHY1_P2_70_H       (REG_COMBO_PHY1_P2_BASE + 0xE1)
3015 #define REG_COMBO_PHY1_P2_71_L       (REG_COMBO_PHY1_P2_BASE + 0xE2)
3016 #define REG_COMBO_PHY1_P2_71_H       (REG_COMBO_PHY1_P2_BASE + 0xE3)
3017 #define REG_COMBO_PHY1_P2_72_L       (REG_COMBO_PHY1_P2_BASE + 0xE4)
3018 #define REG_COMBO_PHY1_P2_72_H       (REG_COMBO_PHY1_P2_BASE + 0xE5)
3019 #define REG_COMBO_PHY1_P2_73_L       (REG_COMBO_PHY1_P2_BASE + 0xE6)
3020 #define REG_COMBO_PHY1_P2_73_H       (REG_COMBO_PHY1_P2_BASE + 0xE7)
3021 #define REG_COMBO_PHY1_P2_74_L       (REG_COMBO_PHY1_P2_BASE + 0xE8)
3022 #define REG_COMBO_PHY1_P2_74_H       (REG_COMBO_PHY1_P2_BASE + 0xE9)
3023 #define REG_COMBO_PHY1_P2_75_L       (REG_COMBO_PHY1_P2_BASE + 0xEA)
3024 #define REG_COMBO_PHY1_P2_75_H       (REG_COMBO_PHY1_P2_BASE + 0xEB)
3025 #define REG_COMBO_PHY1_P2_76_L       (REG_COMBO_PHY1_P2_BASE + 0xEC)
3026 #define REG_COMBO_PHY1_P2_76_H       (REG_COMBO_PHY1_P2_BASE + 0xED)
3027 #define REG_COMBO_PHY1_P2_77_L       (REG_COMBO_PHY1_P2_BASE + 0xEE)
3028 #define REG_COMBO_PHY1_P2_77_H       (REG_COMBO_PHY1_P2_BASE + 0xEF)
3029 #define REG_COMBO_PHY1_P2_78_L       (REG_COMBO_PHY1_P2_BASE + 0xF0)
3030 #define REG_COMBO_PHY1_P2_78_H       (REG_COMBO_PHY1_P2_BASE + 0xF1)
3031 #define REG_COMBO_PHY1_P2_79_L       (REG_COMBO_PHY1_P2_BASE + 0xF2)
3032 #define REG_COMBO_PHY1_P2_79_H       (REG_COMBO_PHY1_P2_BASE + 0xF3)
3033 #define REG_COMBO_PHY1_P2_7A_L       (REG_COMBO_PHY1_P2_BASE + 0xF4)
3034 #define REG_COMBO_PHY1_P2_7A_H       (REG_COMBO_PHY1_P2_BASE + 0xF5)
3035 #define REG_COMBO_PHY1_P2_7B_L       (REG_COMBO_PHY1_P2_BASE + 0xF6)
3036 #define REG_COMBO_PHY1_P2_7B_H       (REG_COMBO_PHY1_P2_BASE + 0xF7)
3037 #define REG_COMBO_PHY1_P2_7C_L       (REG_COMBO_PHY1_P2_BASE + 0xF8)
3038 #define REG_COMBO_PHY1_P2_7C_H       (REG_COMBO_PHY1_P2_BASE + 0xF9)
3039 #define REG_COMBO_PHY1_P2_7D_L       (REG_COMBO_PHY1_P2_BASE + 0xFA)
3040 #define REG_COMBO_PHY1_P2_7D_H       (REG_COMBO_PHY1_P2_BASE + 0xFB)
3041 #define REG_COMBO_PHY1_P2_7E_L       (REG_COMBO_PHY1_P2_BASE + 0xFC)
3042 #define REG_COMBO_PHY1_P2_7E_H       (REG_COMBO_PHY1_P2_BASE + 0xFD)
3043 #define REG_COMBO_PHY1_P2_7F_L       (REG_COMBO_PHY1_P2_BASE + 0xFE)
3044 #define REG_COMBO_PHY1_P2_7F_H       (REG_COMBO_PHY1_P2_BASE + 0xFF)
3045 
3046 // COMBO_PHY0_P3
3047 #define REG_COMBO_PHY0_P3_00_L       (REG_COMBO_PHY0_P3_BASE + 0x00)
3048 #define REG_COMBO_PHY0_P3_00_H       (REG_COMBO_PHY0_P3_BASE + 0x01)
3049 #define REG_COMBO_PHY0_P3_01_L       (REG_COMBO_PHY0_P3_BASE + 0x02)
3050 #define REG_COMBO_PHY0_P3_01_H       (REG_COMBO_PHY0_P3_BASE + 0x03)
3051 #define REG_COMBO_PHY0_P3_02_L       (REG_COMBO_PHY0_P3_BASE + 0x04)
3052 #define REG_COMBO_PHY0_P3_02_H       (REG_COMBO_PHY0_P3_BASE + 0x05)
3053 #define REG_COMBO_PHY0_P3_03_L       (REG_COMBO_PHY0_P3_BASE + 0x06)
3054 #define REG_COMBO_PHY0_P3_03_H       (REG_COMBO_PHY0_P3_BASE + 0x07)
3055 #define REG_COMBO_PHY0_P3_04_L       (REG_COMBO_PHY0_P3_BASE + 0x08)
3056 #define REG_COMBO_PHY0_P3_04_H       (REG_COMBO_PHY0_P3_BASE + 0x09)
3057 #define REG_COMBO_PHY0_P3_05_L       (REG_COMBO_PHY0_P3_BASE + 0x0A)
3058 #define REG_COMBO_PHY0_P3_05_H       (REG_COMBO_PHY0_P3_BASE + 0x0B)
3059 #define REG_COMBO_PHY0_P3_06_L       (REG_COMBO_PHY0_P3_BASE + 0x0C)
3060 #define REG_COMBO_PHY0_P3_06_H       (REG_COMBO_PHY0_P3_BASE + 0x0D)
3061 #define REG_COMBO_PHY0_P3_07_L       (REG_COMBO_PHY0_P3_BASE + 0x0E)
3062 #define REG_COMBO_PHY0_P3_07_H       (REG_COMBO_PHY0_P3_BASE + 0x0F)
3063 #define REG_COMBO_PHY0_P3_08_L       (REG_COMBO_PHY0_P3_BASE + 0x10)
3064 #define REG_COMBO_PHY0_P3_08_H       (REG_COMBO_PHY0_P3_BASE + 0x11)
3065 #define REG_COMBO_PHY0_P3_09_L       (REG_COMBO_PHY0_P3_BASE + 0x12)
3066 #define REG_COMBO_PHY0_P3_09_H       (REG_COMBO_PHY0_P3_BASE + 0x13)
3067 #define REG_COMBO_PHY0_P3_0A_L       (REG_COMBO_PHY0_P3_BASE + 0x14)
3068 #define REG_COMBO_PHY0_P3_0A_H       (REG_COMBO_PHY0_P3_BASE + 0x15)
3069 #define REG_COMBO_PHY0_P3_0B_L       (REG_COMBO_PHY0_P3_BASE + 0x16)
3070 #define REG_COMBO_PHY0_P3_0B_H       (REG_COMBO_PHY0_P3_BASE + 0x17)
3071 #define REG_COMBO_PHY0_P3_0C_L       (REG_COMBO_PHY0_P3_BASE + 0x18)
3072 #define REG_COMBO_PHY0_P3_0C_H       (REG_COMBO_PHY0_P3_BASE + 0x19)
3073 #define REG_COMBO_PHY0_P3_0D_L       (REG_COMBO_PHY0_P3_BASE + 0x1A)
3074 #define REG_COMBO_PHY0_P3_0D_H       (REG_COMBO_PHY0_P3_BASE + 0x1B)
3075 #define REG_COMBO_PHY0_P3_0E_L       (REG_COMBO_PHY0_P3_BASE + 0x1C)
3076 #define REG_COMBO_PHY0_P3_0E_H       (REG_COMBO_PHY0_P3_BASE + 0x1D)
3077 #define REG_COMBO_PHY0_P3_0F_L       (REG_COMBO_PHY0_P3_BASE + 0x1E)
3078 #define REG_COMBO_PHY0_P3_0F_H       (REG_COMBO_PHY0_P3_BASE + 0x1F)
3079 #define REG_COMBO_PHY0_P3_10_L       (REG_COMBO_PHY0_P3_BASE + 0x20)
3080 #define REG_COMBO_PHY0_P3_10_H       (REG_COMBO_PHY0_P3_BASE + 0x21)
3081 #define REG_COMBO_PHY0_P3_11_L       (REG_COMBO_PHY0_P3_BASE + 0x22)
3082 #define REG_COMBO_PHY0_P3_11_H       (REG_COMBO_PHY0_P3_BASE + 0x23)
3083 #define REG_COMBO_PHY0_P3_12_L       (REG_COMBO_PHY0_P3_BASE + 0x24)
3084 #define REG_COMBO_PHY0_P3_12_H       (REG_COMBO_PHY0_P3_BASE + 0x25)
3085 #define REG_COMBO_PHY0_P3_13_L       (REG_COMBO_PHY0_P3_BASE + 0x26)
3086 #define REG_COMBO_PHY0_P3_13_H       (REG_COMBO_PHY0_P3_BASE + 0x27)
3087 #define REG_COMBO_PHY0_P3_14_L       (REG_COMBO_PHY0_P3_BASE + 0x28)
3088 #define REG_COMBO_PHY0_P3_14_H       (REG_COMBO_PHY0_P3_BASE + 0x29)
3089 #define REG_COMBO_PHY0_P3_15_L       (REG_COMBO_PHY0_P3_BASE + 0x2A)
3090 #define REG_COMBO_PHY0_P3_15_H       (REG_COMBO_PHY0_P3_BASE + 0x2B)
3091 #define REG_COMBO_PHY0_P3_16_L       (REG_COMBO_PHY0_P3_BASE + 0x2C)
3092 #define REG_COMBO_PHY0_P3_16_H       (REG_COMBO_PHY0_P3_BASE + 0x2D)
3093 #define REG_COMBO_PHY0_P3_17_L       (REG_COMBO_PHY0_P3_BASE + 0x2E)
3094 #define REG_COMBO_PHY0_P3_17_H       (REG_COMBO_PHY0_P3_BASE + 0x2F)
3095 #define REG_COMBO_PHY0_P3_18_L       (REG_COMBO_PHY0_P3_BASE + 0x30)
3096 #define REG_COMBO_PHY0_P3_18_H       (REG_COMBO_PHY0_P3_BASE + 0x31)
3097 #define REG_COMBO_PHY0_P3_19_L       (REG_COMBO_PHY0_P3_BASE + 0x32)
3098 #define REG_COMBO_PHY0_P3_19_H       (REG_COMBO_PHY0_P3_BASE + 0x33)
3099 #define REG_COMBO_PHY0_P3_1A_L       (REG_COMBO_PHY0_P3_BASE + 0x34)
3100 #define REG_COMBO_PHY0_P3_1A_H       (REG_COMBO_PHY0_P3_BASE + 0x35)
3101 #define REG_COMBO_PHY0_P3_1B_L       (REG_COMBO_PHY0_P3_BASE + 0x36)
3102 #define REG_COMBO_PHY0_P3_1B_H       (REG_COMBO_PHY0_P3_BASE + 0x37)
3103 #define REG_COMBO_PHY0_P3_1C_L       (REG_COMBO_PHY0_P3_BASE + 0x38)
3104 #define REG_COMBO_PHY0_P3_1C_H       (REG_COMBO_PHY0_P3_BASE + 0x39)
3105 #define REG_COMBO_PHY0_P3_1D_L       (REG_COMBO_PHY0_P3_BASE + 0x3A)
3106 #define REG_COMBO_PHY0_P3_1D_H       (REG_COMBO_PHY0_P3_BASE + 0x3B)
3107 #define REG_COMBO_PHY0_P3_1E_L       (REG_COMBO_PHY0_P3_BASE + 0x3C)
3108 #define REG_COMBO_PHY0_P3_1E_H       (REG_COMBO_PHY0_P3_BASE + 0x3D)
3109 #define REG_COMBO_PHY0_P3_1F_L       (REG_COMBO_PHY0_P3_BASE + 0x3E)
3110 #define REG_COMBO_PHY0_P3_1F_H       (REG_COMBO_PHY0_P3_BASE + 0x3F)
3111 #define REG_COMBO_PHY0_P3_20_L       (REG_COMBO_PHY0_P3_BASE + 0x40)
3112 #define REG_COMBO_PHY0_P3_20_H       (REG_COMBO_PHY0_P3_BASE + 0x41)
3113 #define REG_COMBO_PHY0_P3_21_L       (REG_COMBO_PHY0_P3_BASE + 0x42)
3114 #define REG_COMBO_PHY0_P3_21_H       (REG_COMBO_PHY0_P3_BASE + 0x43)
3115 #define REG_COMBO_PHY0_P3_22_L       (REG_COMBO_PHY0_P3_BASE + 0x44)
3116 #define REG_COMBO_PHY0_P3_22_H       (REG_COMBO_PHY0_P3_BASE + 0x45)
3117 #define REG_COMBO_PHY0_P3_23_L       (REG_COMBO_PHY0_P3_BASE + 0x46)
3118 #define REG_COMBO_PHY0_P3_23_H       (REG_COMBO_PHY0_P3_BASE + 0x47)
3119 #define REG_COMBO_PHY0_P3_24_L       (REG_COMBO_PHY0_P3_BASE + 0x48)
3120 #define REG_COMBO_PHY0_P3_24_H       (REG_COMBO_PHY0_P3_BASE + 0x49)
3121 #define REG_COMBO_PHY0_P3_25_L       (REG_COMBO_PHY0_P3_BASE + 0x4A)
3122 #define REG_COMBO_PHY0_P3_25_H       (REG_COMBO_PHY0_P3_BASE + 0x4B)
3123 #define REG_COMBO_PHY0_P3_26_L       (REG_COMBO_PHY0_P3_BASE + 0x4C)
3124 #define REG_COMBO_PHY0_P3_26_H       (REG_COMBO_PHY0_P3_BASE + 0x4D)
3125 #define REG_COMBO_PHY0_P3_27_L       (REG_COMBO_PHY0_P3_BASE + 0x4E)
3126 #define REG_COMBO_PHY0_P3_27_H       (REG_COMBO_PHY0_P3_BASE + 0x4F)
3127 #define REG_COMBO_PHY0_P3_28_L       (REG_COMBO_PHY0_P3_BASE + 0x50)
3128 #define REG_COMBO_PHY0_P3_28_H       (REG_COMBO_PHY0_P3_BASE + 0x51)
3129 #define REG_COMBO_PHY0_P3_29_L       (REG_COMBO_PHY0_P3_BASE + 0x52)
3130 #define REG_COMBO_PHY0_P3_29_H       (REG_COMBO_PHY0_P3_BASE + 0x53)
3131 #define REG_COMBO_PHY0_P3_2A_L       (REG_COMBO_PHY0_P3_BASE + 0x54)
3132 #define REG_COMBO_PHY0_P3_2A_H       (REG_COMBO_PHY0_P3_BASE + 0x55)
3133 #define REG_COMBO_PHY0_P3_2B_L       (REG_COMBO_PHY0_P3_BASE + 0x56)
3134 #define REG_COMBO_PHY0_P3_2B_H       (REG_COMBO_PHY0_P3_BASE + 0x57)
3135 #define REG_COMBO_PHY0_P3_2C_L       (REG_COMBO_PHY0_P3_BASE + 0x58)
3136 #define REG_COMBO_PHY0_P3_2C_H       (REG_COMBO_PHY0_P3_BASE + 0x59)
3137 #define REG_COMBO_PHY0_P3_2D_L       (REG_COMBO_PHY0_P3_BASE + 0x5A)
3138 #define REG_COMBO_PHY0_P3_2D_H       (REG_COMBO_PHY0_P3_BASE + 0x5B)
3139 #define REG_COMBO_PHY0_P3_2E_L       (REG_COMBO_PHY0_P3_BASE + 0x5C)
3140 #define REG_COMBO_PHY0_P3_2E_H       (REG_COMBO_PHY0_P3_BASE + 0x5D)
3141 #define REG_COMBO_PHY0_P3_2F_L       (REG_COMBO_PHY0_P3_BASE + 0x5E)
3142 #define REG_COMBO_PHY0_P3_2F_H       (REG_COMBO_PHY0_P3_BASE + 0x5F)
3143 #define REG_COMBO_PHY0_P3_30_L       (REG_COMBO_PHY0_P3_BASE + 0x60)
3144 #define REG_COMBO_PHY0_P3_30_H       (REG_COMBO_PHY0_P3_BASE + 0x61)
3145 #define REG_COMBO_PHY0_P3_31_L       (REG_COMBO_PHY0_P3_BASE + 0x62)
3146 #define REG_COMBO_PHY0_P3_31_H       (REG_COMBO_PHY0_P3_BASE + 0x63)
3147 #define REG_COMBO_PHY0_P3_32_L       (REG_COMBO_PHY0_P3_BASE + 0x64)
3148 #define REG_COMBO_PHY0_P3_32_H       (REG_COMBO_PHY0_P3_BASE + 0x65)
3149 #define REG_COMBO_PHY0_P3_33_L       (REG_COMBO_PHY0_P3_BASE + 0x66)
3150 #define REG_COMBO_PHY0_P3_33_H       (REG_COMBO_PHY0_P3_BASE + 0x67)
3151 #define REG_COMBO_PHY0_P3_34_L       (REG_COMBO_PHY0_P3_BASE + 0x68)
3152 #define REG_COMBO_PHY0_P3_34_H       (REG_COMBO_PHY0_P3_BASE + 0x69)
3153 #define REG_COMBO_PHY0_P3_35_L       (REG_COMBO_PHY0_P3_BASE + 0x6A)
3154 #define REG_COMBO_PHY0_P3_35_H       (REG_COMBO_PHY0_P3_BASE + 0x6B)
3155 #define REG_COMBO_PHY0_P3_36_L       (REG_COMBO_PHY0_P3_BASE + 0x6C)
3156 #define REG_COMBO_PHY0_P3_36_H       (REG_COMBO_PHY0_P3_BASE + 0x6D)
3157 #define REG_COMBO_PHY0_P3_37_L       (REG_COMBO_PHY0_P3_BASE + 0x6E)
3158 #define REG_COMBO_PHY0_P3_37_H       (REG_COMBO_PHY0_P3_BASE + 0x6F)
3159 #define REG_COMBO_PHY0_P3_38_L       (REG_COMBO_PHY0_P3_BASE + 0x70)
3160 #define REG_COMBO_PHY0_P3_38_H       (REG_COMBO_PHY0_P3_BASE + 0x71)
3161 #define REG_COMBO_PHY0_P3_39_L       (REG_COMBO_PHY0_P3_BASE + 0x72)
3162 #define REG_COMBO_PHY0_P3_39_H       (REG_COMBO_PHY0_P3_BASE + 0x73)
3163 #define REG_COMBO_PHY0_P3_3A_L       (REG_COMBO_PHY0_P3_BASE + 0x74)
3164 #define REG_COMBO_PHY0_P3_3A_H       (REG_COMBO_PHY0_P3_BASE + 0x75)
3165 #define REG_COMBO_PHY0_P3_3B_L       (REG_COMBO_PHY0_P3_BASE + 0x76)
3166 #define REG_COMBO_PHY0_P3_3B_H       (REG_COMBO_PHY0_P3_BASE + 0x77)
3167 #define REG_COMBO_PHY0_P3_3C_L       (REG_COMBO_PHY0_P3_BASE + 0x78)
3168 #define REG_COMBO_PHY0_P3_3C_H       (REG_COMBO_PHY0_P3_BASE + 0x79)
3169 #define REG_COMBO_PHY0_P3_3D_L       (REG_COMBO_PHY0_P3_BASE + 0x7A)
3170 #define REG_COMBO_PHY0_P3_3D_H       (REG_COMBO_PHY0_P3_BASE + 0x7B)
3171 #define REG_COMBO_PHY0_P3_3E_L       (REG_COMBO_PHY0_P3_BASE + 0x7C)
3172 #define REG_COMBO_PHY0_P3_3E_H       (REG_COMBO_PHY0_P3_BASE + 0x7D)
3173 #define REG_COMBO_PHY0_P3_3F_L       (REG_COMBO_PHY0_P3_BASE + 0x7E)
3174 #define REG_COMBO_PHY0_P3_3F_H       (REG_COMBO_PHY0_P3_BASE + 0x7F)
3175 #define REG_COMBO_PHY0_P3_40_L       (REG_COMBO_PHY0_P3_BASE + 0x80)
3176 #define REG_COMBO_PHY0_P3_40_H       (REG_COMBO_PHY0_P3_BASE + 0x81)
3177 #define REG_COMBO_PHY0_P3_41_L       (REG_COMBO_PHY0_P3_BASE + 0x82)
3178 #define REG_COMBO_PHY0_P3_41_H       (REG_COMBO_PHY0_P3_BASE + 0x83)
3179 #define REG_COMBO_PHY0_P3_42_L       (REG_COMBO_PHY0_P3_BASE + 0x84)
3180 #define REG_COMBO_PHY0_P3_42_H       (REG_COMBO_PHY0_P3_BASE + 0x85)
3181 #define REG_COMBO_PHY0_P3_43_L       (REG_COMBO_PHY0_P3_BASE + 0x86)
3182 #define REG_COMBO_PHY0_P3_43_H       (REG_COMBO_PHY0_P3_BASE + 0x87)
3183 #define REG_COMBO_PHY0_P3_44_L       (REG_COMBO_PHY0_P3_BASE + 0x88)
3184 #define REG_COMBO_PHY0_P3_44_H       (REG_COMBO_PHY0_P3_BASE + 0x89)
3185 #define REG_COMBO_PHY0_P3_45_L       (REG_COMBO_PHY0_P3_BASE + 0x8A)
3186 #define REG_COMBO_PHY0_P3_45_H       (REG_COMBO_PHY0_P3_BASE + 0x8B)
3187 #define REG_COMBO_PHY0_P3_46_L       (REG_COMBO_PHY0_P3_BASE + 0x8C)
3188 #define REG_COMBO_PHY0_P3_46_H       (REG_COMBO_PHY0_P3_BASE + 0x8D)
3189 #define REG_COMBO_PHY0_P3_47_L       (REG_COMBO_PHY0_P3_BASE + 0x8E)
3190 #define REG_COMBO_PHY0_P3_47_H       (REG_COMBO_PHY0_P3_BASE + 0x8F)
3191 #define REG_COMBO_PHY0_P3_48_L       (REG_COMBO_PHY0_P3_BASE + 0x90)
3192 #define REG_COMBO_PHY0_P3_48_H       (REG_COMBO_PHY0_P3_BASE + 0x91)
3193 #define REG_COMBO_PHY0_P3_49_L       (REG_COMBO_PHY0_P3_BASE + 0x92)
3194 #define REG_COMBO_PHY0_P3_49_H       (REG_COMBO_PHY0_P3_BASE + 0x93)
3195 #define REG_COMBO_PHY0_P3_4A_L       (REG_COMBO_PHY0_P3_BASE + 0x94)
3196 #define REG_COMBO_PHY0_P3_4A_H       (REG_COMBO_PHY0_P3_BASE + 0x95)
3197 #define REG_COMBO_PHY0_P3_4B_L       (REG_COMBO_PHY0_P3_BASE + 0x96)
3198 #define REG_COMBO_PHY0_P3_4B_H       (REG_COMBO_PHY0_P3_BASE + 0x97)
3199 #define REG_COMBO_PHY0_P3_4C_L       (REG_COMBO_PHY0_P3_BASE + 0x98)
3200 #define REG_COMBO_PHY0_P3_4C_H       (REG_COMBO_PHY0_P3_BASE + 0x99)
3201 #define REG_COMBO_PHY0_P3_4D_L       (REG_COMBO_PHY0_P3_BASE + 0x9A)
3202 #define REG_COMBO_PHY0_P3_4D_H       (REG_COMBO_PHY0_P3_BASE + 0x9B)
3203 #define REG_COMBO_PHY0_P3_4E_L       (REG_COMBO_PHY0_P3_BASE + 0x9C)
3204 #define REG_COMBO_PHY0_P3_4E_H       (REG_COMBO_PHY0_P3_BASE + 0x9D)
3205 #define REG_COMBO_PHY0_P3_4F_L       (REG_COMBO_PHY0_P3_BASE + 0x9E)
3206 #define REG_COMBO_PHY0_P3_4F_H       (REG_COMBO_PHY0_P3_BASE + 0x9F)
3207 #define REG_COMBO_PHY0_P3_50_L       (REG_COMBO_PHY0_P3_BASE + 0xA0)
3208 #define REG_COMBO_PHY0_P3_50_H       (REG_COMBO_PHY0_P3_BASE + 0xA1)
3209 #define REG_COMBO_PHY0_P3_51_L       (REG_COMBO_PHY0_P3_BASE + 0xA2)
3210 #define REG_COMBO_PHY0_P3_51_H       (REG_COMBO_PHY0_P3_BASE + 0xA3)
3211 #define REG_COMBO_PHY0_P3_52_L       (REG_COMBO_PHY0_P3_BASE + 0xA4)
3212 #define REG_COMBO_PHY0_P3_52_H       (REG_COMBO_PHY0_P3_BASE + 0xA5)
3213 #define REG_COMBO_PHY0_P3_53_L       (REG_COMBO_PHY0_P3_BASE + 0xA6)
3214 #define REG_COMBO_PHY0_P3_53_H       (REG_COMBO_PHY0_P3_BASE + 0xA7)
3215 #define REG_COMBO_PHY0_P3_54_L       (REG_COMBO_PHY0_P3_BASE + 0xA8)
3216 #define REG_COMBO_PHY0_P3_54_H       (REG_COMBO_PHY0_P3_BASE + 0xA9)
3217 #define REG_COMBO_PHY0_P3_55_L       (REG_COMBO_PHY0_P3_BASE + 0xAA)
3218 #define REG_COMBO_PHY0_P3_55_H       (REG_COMBO_PHY0_P3_BASE + 0xAB)
3219 #define REG_COMBO_PHY0_P3_56_L       (REG_COMBO_PHY0_P3_BASE + 0xAC)
3220 #define REG_COMBO_PHY0_P3_56_H       (REG_COMBO_PHY0_P3_BASE + 0xAD)
3221 #define REG_COMBO_PHY0_P3_57_L       (REG_COMBO_PHY0_P3_BASE + 0xAE)
3222 #define REG_COMBO_PHY0_P3_57_H       (REG_COMBO_PHY0_P3_BASE + 0xAF)
3223 #define REG_COMBO_PHY0_P3_58_L       (REG_COMBO_PHY0_P3_BASE + 0xB0)
3224 #define REG_COMBO_PHY0_P3_58_H       (REG_COMBO_PHY0_P3_BASE + 0xB1)
3225 #define REG_COMBO_PHY0_P3_59_L       (REG_COMBO_PHY0_P3_BASE + 0xB2)
3226 #define REG_COMBO_PHY0_P3_59_H       (REG_COMBO_PHY0_P3_BASE + 0xB3)
3227 #define REG_COMBO_PHY0_P3_5A_L       (REG_COMBO_PHY0_P3_BASE + 0xB4)
3228 #define REG_COMBO_PHY0_P3_5A_H       (REG_COMBO_PHY0_P3_BASE + 0xB5)
3229 #define REG_COMBO_PHY0_P3_5B_L       (REG_COMBO_PHY0_P3_BASE + 0xB6)
3230 #define REG_COMBO_PHY0_P3_5B_H       (REG_COMBO_PHY0_P3_BASE + 0xB7)
3231 #define REG_COMBO_PHY0_P3_5C_L       (REG_COMBO_PHY0_P3_BASE + 0xB8)
3232 #define REG_COMBO_PHY0_P3_5C_H       (REG_COMBO_PHY0_P3_BASE + 0xB9)
3233 #define REG_COMBO_PHY0_P3_5D_L       (REG_COMBO_PHY0_P3_BASE + 0xBA)
3234 #define REG_COMBO_PHY0_P3_5D_H       (REG_COMBO_PHY0_P3_BASE + 0xBB)
3235 #define REG_COMBO_PHY0_P3_5E_L       (REG_COMBO_PHY0_P3_BASE + 0xBC)
3236 #define REG_COMBO_PHY0_P3_5E_H       (REG_COMBO_PHY0_P3_BASE + 0xBD)
3237 #define REG_COMBO_PHY0_P3_5F_L       (REG_COMBO_PHY0_P3_BASE + 0xBE)
3238 #define REG_COMBO_PHY0_P3_5F_H       (REG_COMBO_PHY0_P3_BASE + 0xBF)
3239 #define REG_COMBO_PHY0_P3_60_L       (REG_COMBO_PHY0_P3_BASE + 0xC0)
3240 #define REG_COMBO_PHY0_P3_60_H       (REG_COMBO_PHY0_P3_BASE + 0xC1)
3241 #define REG_COMBO_PHY0_P3_61_L       (REG_COMBO_PHY0_P3_BASE + 0xC2)
3242 #define REG_COMBO_PHY0_P3_61_H       (REG_COMBO_PHY0_P3_BASE + 0xC3)
3243 #define REG_COMBO_PHY0_P3_62_L       (REG_COMBO_PHY0_P3_BASE + 0xC4)
3244 #define REG_COMBO_PHY0_P3_62_H       (REG_COMBO_PHY0_P3_BASE + 0xC5)
3245 #define REG_COMBO_PHY0_P3_63_L       (REG_COMBO_PHY0_P3_BASE + 0xC6)
3246 #define REG_COMBO_PHY0_P3_63_H       (REG_COMBO_PHY0_P3_BASE + 0xC7)
3247 #define REG_COMBO_PHY0_P3_64_L       (REG_COMBO_PHY0_P3_BASE + 0xC8)
3248 #define REG_COMBO_PHY0_P3_64_H       (REG_COMBO_PHY0_P3_BASE + 0xC9)
3249 #define REG_COMBO_PHY0_P3_65_L       (REG_COMBO_PHY0_P3_BASE + 0xCA)
3250 #define REG_COMBO_PHY0_P3_65_H       (REG_COMBO_PHY0_P3_BASE + 0xCB)
3251 #define REG_COMBO_PHY0_P3_66_L       (REG_COMBO_PHY0_P3_BASE + 0xCC)
3252 #define REG_COMBO_PHY0_P3_66_H       (REG_COMBO_PHY0_P3_BASE + 0xCD)
3253 #define REG_COMBO_PHY0_P3_67_L       (REG_COMBO_PHY0_P3_BASE + 0xCE)
3254 #define REG_COMBO_PHY0_P3_67_H       (REG_COMBO_PHY0_P3_BASE + 0xCF)
3255 #define REG_COMBO_PHY0_P3_68_L       (REG_COMBO_PHY0_P3_BASE + 0xD0)
3256 #define REG_COMBO_PHY0_P3_68_H       (REG_COMBO_PHY0_P3_BASE + 0xD1)
3257 #define REG_COMBO_PHY0_P3_69_L       (REG_COMBO_PHY0_P3_BASE + 0xD2)
3258 #define REG_COMBO_PHY0_P3_69_H       (REG_COMBO_PHY0_P3_BASE + 0xD3)
3259 #define REG_COMBO_PHY0_P3_6A_L       (REG_COMBO_PHY0_P3_BASE + 0xD4)
3260 #define REG_COMBO_PHY0_P3_6A_H       (REG_COMBO_PHY0_P3_BASE + 0xD5)
3261 #define REG_COMBO_PHY0_P3_6B_L       (REG_COMBO_PHY0_P3_BASE + 0xD6)
3262 #define REG_COMBO_PHY0_P3_6B_H       (REG_COMBO_PHY0_P3_BASE + 0xD7)
3263 #define REG_COMBO_PHY0_P3_6C_L       (REG_COMBO_PHY0_P3_BASE + 0xD8)
3264 #define REG_COMBO_PHY0_P3_6C_H       (REG_COMBO_PHY0_P3_BASE + 0xD9)
3265 #define REG_COMBO_PHY0_P3_6D_L       (REG_COMBO_PHY0_P3_BASE + 0xDA)
3266 #define REG_COMBO_PHY0_P3_6D_H       (REG_COMBO_PHY0_P3_BASE + 0xDB)
3267 #define REG_COMBO_PHY0_P3_6E_L       (REG_COMBO_PHY0_P3_BASE + 0xDC)
3268 #define REG_COMBO_PHY0_P3_6E_H       (REG_COMBO_PHY0_P3_BASE + 0xDD)
3269 #define REG_COMBO_PHY0_P3_6F_L       (REG_COMBO_PHY0_P3_BASE + 0xDE)
3270 #define REG_COMBO_PHY0_P3_6F_H       (REG_COMBO_PHY0_P3_BASE + 0xDF)
3271 #define REG_COMBO_PHY0_P3_70_L       (REG_COMBO_PHY0_P3_BASE + 0xE0)
3272 #define REG_COMBO_PHY0_P3_70_H       (REG_COMBO_PHY0_P3_BASE + 0xE1)
3273 #define REG_COMBO_PHY0_P3_71_L       (REG_COMBO_PHY0_P3_BASE + 0xE2)
3274 #define REG_COMBO_PHY0_P3_71_H       (REG_COMBO_PHY0_P3_BASE + 0xE3)
3275 #define REG_COMBO_PHY0_P3_72_L       (REG_COMBO_PHY0_P3_BASE + 0xE4)
3276 #define REG_COMBO_PHY0_P3_72_H       (REG_COMBO_PHY0_P3_BASE + 0xE5)
3277 #define REG_COMBO_PHY0_P3_73_L       (REG_COMBO_PHY0_P3_BASE + 0xE6)
3278 #define REG_COMBO_PHY0_P3_73_H       (REG_COMBO_PHY0_P3_BASE + 0xE7)
3279 #define REG_COMBO_PHY0_P3_74_L       (REG_COMBO_PHY0_P3_BASE + 0xE8)
3280 #define REG_COMBO_PHY0_P3_74_H       (REG_COMBO_PHY0_P3_BASE + 0xE9)
3281 #define REG_COMBO_PHY0_P3_75_L       (REG_COMBO_PHY0_P3_BASE + 0xEA)
3282 #define REG_COMBO_PHY0_P3_75_H       (REG_COMBO_PHY0_P3_BASE + 0xEB)
3283 #define REG_COMBO_PHY0_P3_76_L       (REG_COMBO_PHY0_P3_BASE + 0xEC)
3284 #define REG_COMBO_PHY0_P3_76_H       (REG_COMBO_PHY0_P3_BASE + 0xED)
3285 #define REG_COMBO_PHY0_P3_77_L       (REG_COMBO_PHY0_P3_BASE + 0xEE)
3286 #define REG_COMBO_PHY0_P3_77_H       (REG_COMBO_PHY0_P3_BASE + 0xEF)
3287 #define REG_COMBO_PHY0_P3_78_L       (REG_COMBO_PHY0_P3_BASE + 0xF0)
3288 #define REG_COMBO_PHY0_P3_78_H       (REG_COMBO_PHY0_P3_BASE + 0xF1)
3289 #define REG_COMBO_PHY0_P3_79_L       (REG_COMBO_PHY0_P3_BASE + 0xF2)
3290 #define REG_COMBO_PHY0_P3_79_H       (REG_COMBO_PHY0_P3_BASE + 0xF3)
3291 #define REG_COMBO_PHY0_P3_7A_L       (REG_COMBO_PHY0_P3_BASE + 0xF4)
3292 #define REG_COMBO_PHY0_P3_7A_H       (REG_COMBO_PHY0_P3_BASE + 0xF5)
3293 #define REG_COMBO_PHY0_P3_7B_L       (REG_COMBO_PHY0_P3_BASE + 0xF6)
3294 #define REG_COMBO_PHY0_P3_7B_H       (REG_COMBO_PHY0_P3_BASE + 0xF7)
3295 #define REG_COMBO_PHY0_P3_7C_L       (REG_COMBO_PHY0_P3_BASE + 0xF8)
3296 #define REG_COMBO_PHY0_P3_7C_H       (REG_COMBO_PHY0_P3_BASE + 0xF9)
3297 #define REG_COMBO_PHY0_P3_7D_L       (REG_COMBO_PHY0_P3_BASE + 0xFA)
3298 #define REG_COMBO_PHY0_P3_7D_H       (REG_COMBO_PHY0_P3_BASE + 0xFB)
3299 #define REG_COMBO_PHY0_P3_7E_L       (REG_COMBO_PHY0_P3_BASE + 0xFC)
3300 #define REG_COMBO_PHY0_P3_7E_H       (REG_COMBO_PHY0_P3_BASE + 0xFD)
3301 #define REG_COMBO_PHY0_P3_7F_L       (REG_COMBO_PHY0_P3_BASE + 0xFE)
3302 #define REG_COMBO_PHY0_P3_7F_H       (REG_COMBO_PHY0_P3_BASE + 0xFF)
3303 
3304 // COMBO_PHY1_P3
3305 #define REG_COMBO_PHY1_P3_00_L       (REG_COMBO_PHY1_P3_BASE + 0x00)
3306 #define REG_COMBO_PHY1_P3_00_H       (REG_COMBO_PHY1_P3_BASE + 0x01)
3307 #define REG_COMBO_PHY1_P3_01_L       (REG_COMBO_PHY1_P3_BASE + 0x02)
3308 #define REG_COMBO_PHY1_P3_01_H       (REG_COMBO_PHY1_P3_BASE + 0x03)
3309 #define REG_COMBO_PHY1_P3_02_L       (REG_COMBO_PHY1_P3_BASE + 0x04)
3310 #define REG_COMBO_PHY1_P3_02_H       (REG_COMBO_PHY1_P3_BASE + 0x05)
3311 #define REG_COMBO_PHY1_P3_03_L       (REG_COMBO_PHY1_P3_BASE + 0x06)
3312 #define REG_COMBO_PHY1_P3_03_H       (REG_COMBO_PHY1_P3_BASE + 0x07)
3313 #define REG_COMBO_PHY1_P3_04_L       (REG_COMBO_PHY1_P3_BASE + 0x08)
3314 #define REG_COMBO_PHY1_P3_04_H       (REG_COMBO_PHY1_P3_BASE + 0x09)
3315 #define REG_COMBO_PHY1_P3_05_L       (REG_COMBO_PHY1_P3_BASE + 0x0A)
3316 #define REG_COMBO_PHY1_P3_05_H       (REG_COMBO_PHY1_P3_BASE + 0x0B)
3317 #define REG_COMBO_PHY1_P3_06_L       (REG_COMBO_PHY1_P3_BASE + 0x0C)
3318 #define REG_COMBO_PHY1_P3_06_H       (REG_COMBO_PHY1_P3_BASE + 0x0D)
3319 #define REG_COMBO_PHY1_P3_07_L       (REG_COMBO_PHY1_P3_BASE + 0x0E)
3320 #define REG_COMBO_PHY1_P3_07_H       (REG_COMBO_PHY1_P3_BASE + 0x0F)
3321 #define REG_COMBO_PHY1_P3_08_L       (REG_COMBO_PHY1_P3_BASE + 0x10)
3322 #define REG_COMBO_PHY1_P3_08_H       (REG_COMBO_PHY1_P3_BASE + 0x11)
3323 #define REG_COMBO_PHY1_P3_09_L       (REG_COMBO_PHY1_P3_BASE + 0x12)
3324 #define REG_COMBO_PHY1_P3_09_H       (REG_COMBO_PHY1_P3_BASE + 0x13)
3325 #define REG_COMBO_PHY1_P3_0A_L       (REG_COMBO_PHY1_P3_BASE + 0x14)
3326 #define REG_COMBO_PHY1_P3_0A_H       (REG_COMBO_PHY1_P3_BASE + 0x15)
3327 #define REG_COMBO_PHY1_P3_0B_L       (REG_COMBO_PHY1_P3_BASE + 0x16)
3328 #define REG_COMBO_PHY1_P3_0B_H       (REG_COMBO_PHY1_P3_BASE + 0x17)
3329 #define REG_COMBO_PHY1_P3_0C_L       (REG_COMBO_PHY1_P3_BASE + 0x18)
3330 #define REG_COMBO_PHY1_P3_0C_H       (REG_COMBO_PHY1_P3_BASE + 0x19)
3331 #define REG_COMBO_PHY1_P3_0D_L       (REG_COMBO_PHY1_P3_BASE + 0x1A)
3332 #define REG_COMBO_PHY1_P3_0D_H       (REG_COMBO_PHY1_P3_BASE + 0x1B)
3333 #define REG_COMBO_PHY1_P3_0E_L       (REG_COMBO_PHY1_P3_BASE + 0x1C)
3334 #define REG_COMBO_PHY1_P3_0E_H       (REG_COMBO_PHY1_P3_BASE + 0x1D)
3335 #define REG_COMBO_PHY1_P3_0F_L       (REG_COMBO_PHY1_P3_BASE + 0x1E)
3336 #define REG_COMBO_PHY1_P3_0F_H       (REG_COMBO_PHY1_P3_BASE + 0x1F)
3337 #define REG_COMBO_PHY1_P3_10_L       (REG_COMBO_PHY1_P3_BASE + 0x20)
3338 #define REG_COMBO_PHY1_P3_10_H       (REG_COMBO_PHY1_P3_BASE + 0x21)
3339 #define REG_COMBO_PHY1_P3_11_L       (REG_COMBO_PHY1_P3_BASE + 0x22)
3340 #define REG_COMBO_PHY1_P3_11_H       (REG_COMBO_PHY1_P3_BASE + 0x23)
3341 #define REG_COMBO_PHY1_P3_12_L       (REG_COMBO_PHY1_P3_BASE + 0x24)
3342 #define REG_COMBO_PHY1_P3_12_H       (REG_COMBO_PHY1_P3_BASE + 0x25)
3343 #define REG_COMBO_PHY1_P3_13_L       (REG_COMBO_PHY1_P3_BASE + 0x26)
3344 #define REG_COMBO_PHY1_P3_13_H       (REG_COMBO_PHY1_P3_BASE + 0x27)
3345 #define REG_COMBO_PHY1_P3_14_L       (REG_COMBO_PHY1_P3_BASE + 0x28)
3346 #define REG_COMBO_PHY1_P3_14_H       (REG_COMBO_PHY1_P3_BASE + 0x29)
3347 #define REG_COMBO_PHY1_P3_15_L       (REG_COMBO_PHY1_P3_BASE + 0x2A)
3348 #define REG_COMBO_PHY1_P3_15_H       (REG_COMBO_PHY1_P3_BASE + 0x2B)
3349 #define REG_COMBO_PHY1_P3_16_L       (REG_COMBO_PHY1_P3_BASE + 0x2C)
3350 #define REG_COMBO_PHY1_P3_16_H       (REG_COMBO_PHY1_P3_BASE + 0x2D)
3351 #define REG_COMBO_PHY1_P3_17_L       (REG_COMBO_PHY1_P3_BASE + 0x2E)
3352 #define REG_COMBO_PHY1_P3_17_H       (REG_COMBO_PHY1_P3_BASE + 0x2F)
3353 #define REG_COMBO_PHY1_P3_18_L       (REG_COMBO_PHY1_P3_BASE + 0x30)
3354 #define REG_COMBO_PHY1_P3_18_H       (REG_COMBO_PHY1_P3_BASE + 0x31)
3355 #define REG_COMBO_PHY1_P3_19_L       (REG_COMBO_PHY1_P3_BASE + 0x32)
3356 #define REG_COMBO_PHY1_P3_19_H       (REG_COMBO_PHY1_P3_BASE + 0x33)
3357 #define REG_COMBO_PHY1_P3_1A_L       (REG_COMBO_PHY1_P3_BASE + 0x34)
3358 #define REG_COMBO_PHY1_P3_1A_H       (REG_COMBO_PHY1_P3_BASE + 0x35)
3359 #define REG_COMBO_PHY1_P3_1B_L       (REG_COMBO_PHY1_P3_BASE + 0x36)
3360 #define REG_COMBO_PHY1_P3_1B_H       (REG_COMBO_PHY1_P3_BASE + 0x37)
3361 #define REG_COMBO_PHY1_P3_1C_L       (REG_COMBO_PHY1_P3_BASE + 0x38)
3362 #define REG_COMBO_PHY1_P3_1C_H       (REG_COMBO_PHY1_P3_BASE + 0x39)
3363 #define REG_COMBO_PHY1_P3_1D_L       (REG_COMBO_PHY1_P3_BASE + 0x3A)
3364 #define REG_COMBO_PHY1_P3_1D_H       (REG_COMBO_PHY1_P3_BASE + 0x3B)
3365 #define REG_COMBO_PHY1_P3_1E_L       (REG_COMBO_PHY1_P3_BASE + 0x3C)
3366 #define REG_COMBO_PHY1_P3_1E_H       (REG_COMBO_PHY1_P3_BASE + 0x3D)
3367 #define REG_COMBO_PHY1_P3_1F_L       (REG_COMBO_PHY1_P3_BASE + 0x3E)
3368 #define REG_COMBO_PHY1_P3_1F_H       (REG_COMBO_PHY1_P3_BASE + 0x3F)
3369 #define REG_COMBO_PHY1_P3_20_L       (REG_COMBO_PHY1_P3_BASE + 0x40)
3370 #define REG_COMBO_PHY1_P3_20_H       (REG_COMBO_PHY1_P3_BASE + 0x41)
3371 #define REG_COMBO_PHY1_P3_21_L       (REG_COMBO_PHY1_P3_BASE + 0x42)
3372 #define REG_COMBO_PHY1_P3_21_H       (REG_COMBO_PHY1_P3_BASE + 0x43)
3373 #define REG_COMBO_PHY1_P3_22_L       (REG_COMBO_PHY1_P3_BASE + 0x44)
3374 #define REG_COMBO_PHY1_P3_22_H       (REG_COMBO_PHY1_P3_BASE + 0x45)
3375 #define REG_COMBO_PHY1_P3_23_L       (REG_COMBO_PHY1_P3_BASE + 0x46)
3376 #define REG_COMBO_PHY1_P3_23_H       (REG_COMBO_PHY1_P3_BASE + 0x47)
3377 #define REG_COMBO_PHY1_P3_24_L       (REG_COMBO_PHY1_P3_BASE + 0x48)
3378 #define REG_COMBO_PHY1_P3_24_H       (REG_COMBO_PHY1_P3_BASE + 0x49)
3379 #define REG_COMBO_PHY1_P3_25_L       (REG_COMBO_PHY1_P3_BASE + 0x4A)
3380 #define REG_COMBO_PHY1_P3_25_H       (REG_COMBO_PHY1_P3_BASE + 0x4B)
3381 #define REG_COMBO_PHY1_P3_26_L       (REG_COMBO_PHY1_P3_BASE + 0x4C)
3382 #define REG_COMBO_PHY1_P3_26_H       (REG_COMBO_PHY1_P3_BASE + 0x4D)
3383 #define REG_COMBO_PHY1_P3_27_L       (REG_COMBO_PHY1_P3_BASE + 0x4E)
3384 #define REG_COMBO_PHY1_P3_27_H       (REG_COMBO_PHY1_P3_BASE + 0x4F)
3385 #define REG_COMBO_PHY1_P3_28_L       (REG_COMBO_PHY1_P3_BASE + 0x50)
3386 #define REG_COMBO_PHY1_P3_28_H       (REG_COMBO_PHY1_P3_BASE + 0x51)
3387 #define REG_COMBO_PHY1_P3_29_L       (REG_COMBO_PHY1_P3_BASE + 0x52)
3388 #define REG_COMBO_PHY1_P3_29_H       (REG_COMBO_PHY1_P3_BASE + 0x53)
3389 #define REG_COMBO_PHY1_P3_2A_L       (REG_COMBO_PHY1_P3_BASE + 0x54)
3390 #define REG_COMBO_PHY1_P3_2A_H       (REG_COMBO_PHY1_P3_BASE + 0x55)
3391 #define REG_COMBO_PHY1_P3_2B_L       (REG_COMBO_PHY1_P3_BASE + 0x56)
3392 #define REG_COMBO_PHY1_P3_2B_H       (REG_COMBO_PHY1_P3_BASE + 0x57)
3393 #define REG_COMBO_PHY1_P3_2C_L       (REG_COMBO_PHY1_P3_BASE + 0x58)
3394 #define REG_COMBO_PHY1_P3_2C_H       (REG_COMBO_PHY1_P3_BASE + 0x59)
3395 #define REG_COMBO_PHY1_P3_2D_L       (REG_COMBO_PHY1_P3_BASE + 0x5A)
3396 #define REG_COMBO_PHY1_P3_2D_H       (REG_COMBO_PHY1_P3_BASE + 0x5B)
3397 #define REG_COMBO_PHY1_P3_2E_L       (REG_COMBO_PHY1_P3_BASE + 0x5C)
3398 #define REG_COMBO_PHY1_P3_2E_H       (REG_COMBO_PHY1_P3_BASE + 0x5D)
3399 #define REG_COMBO_PHY1_P3_2F_L       (REG_COMBO_PHY1_P3_BASE + 0x5E)
3400 #define REG_COMBO_PHY1_P3_2F_H       (REG_COMBO_PHY1_P3_BASE + 0x5F)
3401 #define REG_COMBO_PHY1_P3_30_L       (REG_COMBO_PHY1_P3_BASE + 0x60)
3402 #define REG_COMBO_PHY1_P3_30_H       (REG_COMBO_PHY1_P3_BASE + 0x61)
3403 #define REG_COMBO_PHY1_P3_31_L       (REG_COMBO_PHY1_P3_BASE + 0x62)
3404 #define REG_COMBO_PHY1_P3_31_H       (REG_COMBO_PHY1_P3_BASE + 0x63)
3405 #define REG_COMBO_PHY1_P3_32_L       (REG_COMBO_PHY1_P3_BASE + 0x64)
3406 #define REG_COMBO_PHY1_P3_32_H       (REG_COMBO_PHY1_P3_BASE + 0x65)
3407 #define REG_COMBO_PHY1_P3_33_L       (REG_COMBO_PHY1_P3_BASE + 0x66)
3408 #define REG_COMBO_PHY1_P3_33_H       (REG_COMBO_PHY1_P3_BASE + 0x67)
3409 #define REG_COMBO_PHY1_P3_34_L       (REG_COMBO_PHY1_P3_BASE + 0x68)
3410 #define REG_COMBO_PHY1_P3_34_H       (REG_COMBO_PHY1_P3_BASE + 0x69)
3411 #define REG_COMBO_PHY1_P3_35_L       (REG_COMBO_PHY1_P3_BASE + 0x6A)
3412 #define REG_COMBO_PHY1_P3_35_H       (REG_COMBO_PHY1_P3_BASE + 0x6B)
3413 #define REG_COMBO_PHY1_P3_36_L       (REG_COMBO_PHY1_P3_BASE + 0x6C)
3414 #define REG_COMBO_PHY1_P3_36_H       (REG_COMBO_PHY1_P3_BASE + 0x6D)
3415 #define REG_COMBO_PHY1_P3_37_L       (REG_COMBO_PHY1_P3_BASE + 0x6E)
3416 #define REG_COMBO_PHY1_P3_37_H       (REG_COMBO_PHY1_P3_BASE + 0x6F)
3417 #define REG_COMBO_PHY1_P3_38_L       (REG_COMBO_PHY1_P3_BASE + 0x70)
3418 #define REG_COMBO_PHY1_P3_38_H       (REG_COMBO_PHY1_P3_BASE + 0x71)
3419 #define REG_COMBO_PHY1_P3_39_L       (REG_COMBO_PHY1_P3_BASE + 0x72)
3420 #define REG_COMBO_PHY1_P3_39_H       (REG_COMBO_PHY1_P3_BASE + 0x73)
3421 #define REG_COMBO_PHY1_P3_3A_L       (REG_COMBO_PHY1_P3_BASE + 0x74)
3422 #define REG_COMBO_PHY1_P3_3A_H       (REG_COMBO_PHY1_P3_BASE + 0x75)
3423 #define REG_COMBO_PHY1_P3_3B_L       (REG_COMBO_PHY1_P3_BASE + 0x76)
3424 #define REG_COMBO_PHY1_P3_3B_H       (REG_COMBO_PHY1_P3_BASE + 0x77)
3425 #define REG_COMBO_PHY1_P3_3C_L       (REG_COMBO_PHY1_P3_BASE + 0x78)
3426 #define REG_COMBO_PHY1_P3_3C_H       (REG_COMBO_PHY1_P3_BASE + 0x79)
3427 #define REG_COMBO_PHY1_P3_3D_L       (REG_COMBO_PHY1_P3_BASE + 0x7A)
3428 #define REG_COMBO_PHY1_P3_3D_H       (REG_COMBO_PHY1_P3_BASE + 0x7B)
3429 #define REG_COMBO_PHY1_P3_3E_L       (REG_COMBO_PHY1_P3_BASE + 0x7C)
3430 #define REG_COMBO_PHY1_P3_3E_H       (REG_COMBO_PHY1_P3_BASE + 0x7D)
3431 #define REG_COMBO_PHY1_P3_3F_L       (REG_COMBO_PHY1_P3_BASE + 0x7E)
3432 #define REG_COMBO_PHY1_P3_3F_H       (REG_COMBO_PHY1_P3_BASE + 0x7F)
3433 #define REG_COMBO_PHY1_P3_40_L       (REG_COMBO_PHY1_P3_BASE + 0x80)
3434 #define REG_COMBO_PHY1_P3_40_H       (REG_COMBO_PHY1_P3_BASE + 0x81)
3435 #define REG_COMBO_PHY1_P3_41_L       (REG_COMBO_PHY1_P3_BASE + 0x82)
3436 #define REG_COMBO_PHY1_P3_41_H       (REG_COMBO_PHY1_P3_BASE + 0x83)
3437 #define REG_COMBO_PHY1_P3_42_L       (REG_COMBO_PHY1_P3_BASE + 0x84)
3438 #define REG_COMBO_PHY1_P3_42_H       (REG_COMBO_PHY1_P3_BASE + 0x85)
3439 #define REG_COMBO_PHY1_P3_43_L       (REG_COMBO_PHY1_P3_BASE + 0x86)
3440 #define REG_COMBO_PHY1_P3_43_H       (REG_COMBO_PHY1_P3_BASE + 0x87)
3441 #define REG_COMBO_PHY1_P3_44_L       (REG_COMBO_PHY1_P3_BASE + 0x88)
3442 #define REG_COMBO_PHY1_P3_44_H       (REG_COMBO_PHY1_P3_BASE + 0x89)
3443 #define REG_COMBO_PHY1_P3_45_L       (REG_COMBO_PHY1_P3_BASE + 0x8A)
3444 #define REG_COMBO_PHY1_P3_45_H       (REG_COMBO_PHY1_P3_BASE + 0x8B)
3445 #define REG_COMBO_PHY1_P3_46_L       (REG_COMBO_PHY1_P3_BASE + 0x8C)
3446 #define REG_COMBO_PHY1_P3_46_H       (REG_COMBO_PHY1_P3_BASE + 0x8D)
3447 #define REG_COMBO_PHY1_P3_47_L       (REG_COMBO_PHY1_P3_BASE + 0x8E)
3448 #define REG_COMBO_PHY1_P3_47_H       (REG_COMBO_PHY1_P3_BASE + 0x8F)
3449 #define REG_COMBO_PHY1_P3_48_L       (REG_COMBO_PHY1_P3_BASE + 0x90)
3450 #define REG_COMBO_PHY1_P3_48_H       (REG_COMBO_PHY1_P3_BASE + 0x91)
3451 #define REG_COMBO_PHY1_P3_49_L       (REG_COMBO_PHY1_P3_BASE + 0x92)
3452 #define REG_COMBO_PHY1_P3_49_H       (REG_COMBO_PHY1_P3_BASE + 0x93)
3453 #define REG_COMBO_PHY1_P3_4A_L       (REG_COMBO_PHY1_P3_BASE + 0x94)
3454 #define REG_COMBO_PHY1_P3_4A_H       (REG_COMBO_PHY1_P3_BASE + 0x95)
3455 #define REG_COMBO_PHY1_P3_4B_L       (REG_COMBO_PHY1_P3_BASE + 0x96)
3456 #define REG_COMBO_PHY1_P3_4B_H       (REG_COMBO_PHY1_P3_BASE + 0x97)
3457 #define REG_COMBO_PHY1_P3_4C_L       (REG_COMBO_PHY1_P3_BASE + 0x98)
3458 #define REG_COMBO_PHY1_P3_4C_H       (REG_COMBO_PHY1_P3_BASE + 0x99)
3459 #define REG_COMBO_PHY1_P3_4D_L       (REG_COMBO_PHY1_P3_BASE + 0x9A)
3460 #define REG_COMBO_PHY1_P3_4D_H       (REG_COMBO_PHY1_P3_BASE + 0x9B)
3461 #define REG_COMBO_PHY1_P3_4E_L       (REG_COMBO_PHY1_P3_BASE + 0x9C)
3462 #define REG_COMBO_PHY1_P3_4E_H       (REG_COMBO_PHY1_P3_BASE + 0x9D)
3463 #define REG_COMBO_PHY1_P3_4F_L       (REG_COMBO_PHY1_P3_BASE + 0x9E)
3464 #define REG_COMBO_PHY1_P3_4F_H       (REG_COMBO_PHY1_P3_BASE + 0x9F)
3465 #define REG_COMBO_PHY1_P3_50_L       (REG_COMBO_PHY1_P3_BASE + 0xA0)
3466 #define REG_COMBO_PHY1_P3_50_H       (REG_COMBO_PHY1_P3_BASE + 0xA1)
3467 #define REG_COMBO_PHY1_P3_51_L       (REG_COMBO_PHY1_P3_BASE + 0xA2)
3468 #define REG_COMBO_PHY1_P3_51_H       (REG_COMBO_PHY1_P3_BASE + 0xA3)
3469 #define REG_COMBO_PHY1_P3_52_L       (REG_COMBO_PHY1_P3_BASE + 0xA4)
3470 #define REG_COMBO_PHY1_P3_52_H       (REG_COMBO_PHY1_P3_BASE + 0xA5)
3471 #define REG_COMBO_PHY1_P3_53_L       (REG_COMBO_PHY1_P3_BASE + 0xA6)
3472 #define REG_COMBO_PHY1_P3_53_H       (REG_COMBO_PHY1_P3_BASE + 0xA7)
3473 #define REG_COMBO_PHY1_P3_54_L       (REG_COMBO_PHY1_P3_BASE + 0xA8)
3474 #define REG_COMBO_PHY1_P3_54_H       (REG_COMBO_PHY1_P3_BASE + 0xA9)
3475 #define REG_COMBO_PHY1_P3_55_L       (REG_COMBO_PHY1_P3_BASE + 0xAA)
3476 #define REG_COMBO_PHY1_P3_55_H       (REG_COMBO_PHY1_P3_BASE + 0xAB)
3477 #define REG_COMBO_PHY1_P3_56_L       (REG_COMBO_PHY1_P3_BASE + 0xAC)
3478 #define REG_COMBO_PHY1_P3_56_H       (REG_COMBO_PHY1_P3_BASE + 0xAD)
3479 #define REG_COMBO_PHY1_P3_57_L       (REG_COMBO_PHY1_P3_BASE + 0xAE)
3480 #define REG_COMBO_PHY1_P3_57_H       (REG_COMBO_PHY1_P3_BASE + 0xAF)
3481 #define REG_COMBO_PHY1_P3_58_L       (REG_COMBO_PHY1_P3_BASE + 0xB0)
3482 #define REG_COMBO_PHY1_P3_58_H       (REG_COMBO_PHY1_P3_BASE + 0xB1)
3483 #define REG_COMBO_PHY1_P3_59_L       (REG_COMBO_PHY1_P3_BASE + 0xB2)
3484 #define REG_COMBO_PHY1_P3_59_H       (REG_COMBO_PHY1_P3_BASE + 0xB3)
3485 #define REG_COMBO_PHY1_P3_5A_L       (REG_COMBO_PHY1_P3_BASE + 0xB4)
3486 #define REG_COMBO_PHY1_P3_5A_H       (REG_COMBO_PHY1_P3_BASE + 0xB5)
3487 #define REG_COMBO_PHY1_P3_5B_L       (REG_COMBO_PHY1_P3_BASE + 0xB6)
3488 #define REG_COMBO_PHY1_P3_5B_H       (REG_COMBO_PHY1_P3_BASE + 0xB7)
3489 #define REG_COMBO_PHY1_P3_5C_L       (REG_COMBO_PHY1_P3_BASE + 0xB8)
3490 #define REG_COMBO_PHY1_P3_5C_H       (REG_COMBO_PHY1_P3_BASE + 0xB9)
3491 #define REG_COMBO_PHY1_P3_5D_L       (REG_COMBO_PHY1_P3_BASE + 0xBA)
3492 #define REG_COMBO_PHY1_P3_5D_H       (REG_COMBO_PHY1_P3_BASE + 0xBB)
3493 #define REG_COMBO_PHY1_P3_5E_L       (REG_COMBO_PHY1_P3_BASE + 0xBC)
3494 #define REG_COMBO_PHY1_P3_5E_H       (REG_COMBO_PHY1_P3_BASE + 0xBD)
3495 #define REG_COMBO_PHY1_P3_5F_L       (REG_COMBO_PHY1_P3_BASE + 0xBE)
3496 #define REG_COMBO_PHY1_P3_5F_H       (REG_COMBO_PHY1_P3_BASE + 0xBF)
3497 #define REG_COMBO_PHY1_P3_60_L       (REG_COMBO_PHY1_P3_BASE + 0xC0)
3498 #define REG_COMBO_PHY1_P3_60_H       (REG_COMBO_PHY1_P3_BASE + 0xC1)
3499 #define REG_COMBO_PHY1_P3_61_L       (REG_COMBO_PHY1_P3_BASE + 0xC2)
3500 #define REG_COMBO_PHY1_P3_61_H       (REG_COMBO_PHY1_P3_BASE + 0xC3)
3501 #define REG_COMBO_PHY1_P3_62_L       (REG_COMBO_PHY1_P3_BASE + 0xC4)
3502 #define REG_COMBO_PHY1_P3_62_H       (REG_COMBO_PHY1_P3_BASE + 0xC5)
3503 #define REG_COMBO_PHY1_P3_63_L       (REG_COMBO_PHY1_P3_BASE + 0xC6)
3504 #define REG_COMBO_PHY1_P3_63_H       (REG_COMBO_PHY1_P3_BASE + 0xC7)
3505 #define REG_COMBO_PHY1_P3_64_L       (REG_COMBO_PHY1_P3_BASE + 0xC8)
3506 #define REG_COMBO_PHY1_P3_64_H       (REG_COMBO_PHY1_P3_BASE + 0xC9)
3507 #define REG_COMBO_PHY1_P3_65_L       (REG_COMBO_PHY1_P3_BASE + 0xCA)
3508 #define REG_COMBO_PHY1_P3_65_H       (REG_COMBO_PHY1_P3_BASE + 0xCB)
3509 #define REG_COMBO_PHY1_P3_66_L       (REG_COMBO_PHY1_P3_BASE + 0xCC)
3510 #define REG_COMBO_PHY1_P3_66_H       (REG_COMBO_PHY1_P3_BASE + 0xCD)
3511 #define REG_COMBO_PHY1_P3_67_L       (REG_COMBO_PHY1_P3_BASE + 0xCE)
3512 #define REG_COMBO_PHY1_P3_67_H       (REG_COMBO_PHY1_P3_BASE + 0xCF)
3513 #define REG_COMBO_PHY1_P3_68_L       (REG_COMBO_PHY1_P3_BASE + 0xD0)
3514 #define REG_COMBO_PHY1_P3_68_H       (REG_COMBO_PHY1_P3_BASE + 0xD1)
3515 #define REG_COMBO_PHY1_P3_69_L       (REG_COMBO_PHY1_P3_BASE + 0xD2)
3516 #define REG_COMBO_PHY1_P3_69_H       (REG_COMBO_PHY1_P3_BASE + 0xD3)
3517 #define REG_COMBO_PHY1_P3_6A_L       (REG_COMBO_PHY1_P3_BASE + 0xD4)
3518 #define REG_COMBO_PHY1_P3_6A_H       (REG_COMBO_PHY1_P3_BASE + 0xD5)
3519 #define REG_COMBO_PHY1_P3_6B_L       (REG_COMBO_PHY1_P3_BASE + 0xD6)
3520 #define REG_COMBO_PHY1_P3_6B_H       (REG_COMBO_PHY1_P3_BASE + 0xD7)
3521 #define REG_COMBO_PHY1_P3_6C_L       (REG_COMBO_PHY1_P3_BASE + 0xD8)
3522 #define REG_COMBO_PHY1_P3_6C_H       (REG_COMBO_PHY1_P3_BASE + 0xD9)
3523 #define REG_COMBO_PHY1_P3_6D_L       (REG_COMBO_PHY1_P3_BASE + 0xDA)
3524 #define REG_COMBO_PHY1_P3_6D_H       (REG_COMBO_PHY1_P3_BASE + 0xDB)
3525 #define REG_COMBO_PHY1_P3_6E_L       (REG_COMBO_PHY1_P3_BASE + 0xDC)
3526 #define REG_COMBO_PHY1_P3_6E_H       (REG_COMBO_PHY1_P3_BASE + 0xDD)
3527 #define REG_COMBO_PHY1_P3_6F_L       (REG_COMBO_PHY1_P3_BASE + 0xDE)
3528 #define REG_COMBO_PHY1_P3_6F_H       (REG_COMBO_PHY1_P3_BASE + 0xDF)
3529 #define REG_COMBO_PHY1_P3_70_L       (REG_COMBO_PHY1_P3_BASE + 0xE0)
3530 #define REG_COMBO_PHY1_P3_70_H       (REG_COMBO_PHY1_P3_BASE + 0xE1)
3531 #define REG_COMBO_PHY1_P3_71_L       (REG_COMBO_PHY1_P3_BASE + 0xE2)
3532 #define REG_COMBO_PHY1_P3_71_H       (REG_COMBO_PHY1_P3_BASE + 0xE3)
3533 #define REG_COMBO_PHY1_P3_72_L       (REG_COMBO_PHY1_P3_BASE + 0xE4)
3534 #define REG_COMBO_PHY1_P3_72_H       (REG_COMBO_PHY1_P3_BASE + 0xE5)
3535 #define REG_COMBO_PHY1_P3_73_L       (REG_COMBO_PHY1_P3_BASE + 0xE6)
3536 #define REG_COMBO_PHY1_P3_73_H       (REG_COMBO_PHY1_P3_BASE + 0xE7)
3537 #define REG_COMBO_PHY1_P3_74_L       (REG_COMBO_PHY1_P3_BASE + 0xE8)
3538 #define REG_COMBO_PHY1_P3_74_H       (REG_COMBO_PHY1_P3_BASE + 0xE9)
3539 #define REG_COMBO_PHY1_P3_75_L       (REG_COMBO_PHY1_P3_BASE + 0xEA)
3540 #define REG_COMBO_PHY1_P3_75_H       (REG_COMBO_PHY1_P3_BASE + 0xEB)
3541 #define REG_COMBO_PHY1_P3_76_L       (REG_COMBO_PHY1_P3_BASE + 0xEC)
3542 #define REG_COMBO_PHY1_P3_76_H       (REG_COMBO_PHY1_P3_BASE + 0xED)
3543 #define REG_COMBO_PHY1_P3_77_L       (REG_COMBO_PHY1_P3_BASE + 0xEE)
3544 #define REG_COMBO_PHY1_P3_77_H       (REG_COMBO_PHY1_P3_BASE + 0xEF)
3545 #define REG_COMBO_PHY1_P3_78_L       (REG_COMBO_PHY1_P3_BASE + 0xF0)
3546 #define REG_COMBO_PHY1_P3_78_H       (REG_COMBO_PHY1_P3_BASE + 0xF1)
3547 #define REG_COMBO_PHY1_P3_79_L       (REG_COMBO_PHY1_P3_BASE + 0xF2)
3548 #define REG_COMBO_PHY1_P3_79_H       (REG_COMBO_PHY1_P3_BASE + 0xF3)
3549 #define REG_COMBO_PHY1_P3_7A_L       (REG_COMBO_PHY1_P3_BASE + 0xF4)
3550 #define REG_COMBO_PHY1_P3_7A_H       (REG_COMBO_PHY1_P3_BASE + 0xF5)
3551 #define REG_COMBO_PHY1_P3_7B_L       (REG_COMBO_PHY1_P3_BASE + 0xF6)
3552 #define REG_COMBO_PHY1_P3_7B_H       (REG_COMBO_PHY1_P3_BASE + 0xF7)
3553 #define REG_COMBO_PHY1_P3_7C_L       (REG_COMBO_PHY1_P3_BASE + 0xF8)
3554 #define REG_COMBO_PHY1_P3_7C_H       (REG_COMBO_PHY1_P3_BASE + 0xF9)
3555 #define REG_COMBO_PHY1_P3_7D_L       (REG_COMBO_PHY1_P3_BASE + 0xFA)
3556 #define REG_COMBO_PHY1_P3_7D_H       (REG_COMBO_PHY1_P3_BASE + 0xFB)
3557 #define REG_COMBO_PHY1_P3_7E_L       (REG_COMBO_PHY1_P3_BASE + 0xFC)
3558 #define REG_COMBO_PHY1_P3_7E_H       (REG_COMBO_PHY1_P3_BASE + 0xFD)
3559 #define REG_COMBO_PHY1_P3_7F_L       (REG_COMBO_PHY1_P3_BASE + 0xFE)
3560 #define REG_COMBO_PHY1_P3_7F_H       (REG_COMBO_PHY1_P3_BASE + 0xFF)
3561 
3562 //=============================================================
3563 
3564 // DVI_DTOP_DUAL_P0
3565 #define REG_DVI_DTOP_DUAL_P0_00_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x00)
3566 #define REG_DVI_DTOP_DUAL_P0_00_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x01)
3567 #define REG_DVI_DTOP_DUAL_P0_01_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x02)
3568 #define REG_DVI_DTOP_DUAL_P0_01_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x03)
3569 #define REG_DVI_DTOP_DUAL_P0_02_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x04)
3570 #define REG_DVI_DTOP_DUAL_P0_02_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x05)
3571 #define REG_DVI_DTOP_DUAL_P0_03_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x06)
3572 #define REG_DVI_DTOP_DUAL_P0_03_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x07)
3573 #define REG_DVI_DTOP_DUAL_P0_04_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x08)
3574 #define REG_DVI_DTOP_DUAL_P0_04_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x09)
3575 #define REG_DVI_DTOP_DUAL_P0_05_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0A)
3576 #define REG_DVI_DTOP_DUAL_P0_05_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0B)
3577 #define REG_DVI_DTOP_DUAL_P0_06_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0C)
3578 #define REG_DVI_DTOP_DUAL_P0_06_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0D)
3579 #define REG_DVI_DTOP_DUAL_P0_07_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0E)
3580 #define REG_DVI_DTOP_DUAL_P0_07_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x0F)
3581 #define REG_DVI_DTOP_DUAL_P0_08_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x10)
3582 #define REG_DVI_DTOP_DUAL_P0_08_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x11)
3583 #define REG_DVI_DTOP_DUAL_P0_09_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x12)
3584 #define REG_DVI_DTOP_DUAL_P0_09_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x13)
3585 #define REG_DVI_DTOP_DUAL_P0_0A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x14)
3586 #define REG_DVI_DTOP_DUAL_P0_0A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x15)
3587 #define REG_DVI_DTOP_DUAL_P0_0B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x16)
3588 #define REG_DVI_DTOP_DUAL_P0_0B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x17)
3589 #define REG_DVI_DTOP_DUAL_P0_0C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x18)
3590 #define REG_DVI_DTOP_DUAL_P0_0C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x19)
3591 #define REG_DVI_DTOP_DUAL_P0_0D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1A)
3592 #define REG_DVI_DTOP_DUAL_P0_0D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1B)
3593 #define REG_DVI_DTOP_DUAL_P0_0E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1C)
3594 #define REG_DVI_DTOP_DUAL_P0_0E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1D)
3595 #define REG_DVI_DTOP_DUAL_P0_0F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1E)
3596 #define REG_DVI_DTOP_DUAL_P0_0F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x1F)
3597 #define REG_DVI_DTOP_DUAL_P0_10_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x20)
3598 #define REG_DVI_DTOP_DUAL_P0_10_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x21)
3599 #define REG_DVI_DTOP_DUAL_P0_11_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x22)
3600 #define REG_DVI_DTOP_DUAL_P0_11_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x23)
3601 #define REG_DVI_DTOP_DUAL_P0_12_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x24)
3602 #define REG_DVI_DTOP_DUAL_P0_12_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x25)
3603 #define REG_DVI_DTOP_DUAL_P0_13_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x26)
3604 #define REG_DVI_DTOP_DUAL_P0_13_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x27)
3605 #define REG_DVI_DTOP_DUAL_P0_14_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x28)
3606 #define REG_DVI_DTOP_DUAL_P0_14_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x29)
3607 #define REG_DVI_DTOP_DUAL_P0_15_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2A)
3608 #define REG_DVI_DTOP_DUAL_P0_15_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2B)
3609 #define REG_DVI_DTOP_DUAL_P0_16_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2C)
3610 #define REG_DVI_DTOP_DUAL_P0_16_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2D)
3611 #define REG_DVI_DTOP_DUAL_P0_17_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2E)
3612 #define REG_DVI_DTOP_DUAL_P0_17_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x2F)
3613 #define REG_DVI_DTOP_DUAL_P0_18_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x30)
3614 #define REG_DVI_DTOP_DUAL_P0_18_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x31)
3615 #define REG_DVI_DTOP_DUAL_P0_19_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x32)
3616 #define REG_DVI_DTOP_DUAL_P0_19_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x33)
3617 #define REG_DVI_DTOP_DUAL_P0_1A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x34)
3618 #define REG_DVI_DTOP_DUAL_P0_1A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x35)
3619 #define REG_DVI_DTOP_DUAL_P0_1B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x36)
3620 #define REG_DVI_DTOP_DUAL_P0_1B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x37)
3621 #define REG_DVI_DTOP_DUAL_P0_1C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x38)
3622 #define REG_DVI_DTOP_DUAL_P0_1C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x39)
3623 #define REG_DVI_DTOP_DUAL_P0_1D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3A)
3624 #define REG_DVI_DTOP_DUAL_P0_1D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3B)
3625 #define REG_DVI_DTOP_DUAL_P0_1E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3C)
3626 #define REG_DVI_DTOP_DUAL_P0_1E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3D)
3627 #define REG_DVI_DTOP_DUAL_P0_1F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3E)
3628 #define REG_DVI_DTOP_DUAL_P0_1F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x3F)
3629 #define REG_DVI_DTOP_DUAL_P0_20_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x40)
3630 #define REG_DVI_DTOP_DUAL_P0_20_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x41)
3631 #define REG_DVI_DTOP_DUAL_P0_21_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x42)
3632 #define REG_DVI_DTOP_DUAL_P0_21_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x43)
3633 #define REG_DVI_DTOP_DUAL_P0_22_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x44)
3634 #define REG_DVI_DTOP_DUAL_P0_22_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x45)
3635 #define REG_DVI_DTOP_DUAL_P0_23_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x46)
3636 #define REG_DVI_DTOP_DUAL_P0_23_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x47)
3637 #define REG_DVI_DTOP_DUAL_P0_24_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x48)
3638 #define REG_DVI_DTOP_DUAL_P0_24_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x49)
3639 #define REG_DVI_DTOP_DUAL_P0_25_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4A)
3640 #define REG_DVI_DTOP_DUAL_P0_25_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4B)
3641 #define REG_DVI_DTOP_DUAL_P0_26_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4C)
3642 #define REG_DVI_DTOP_DUAL_P0_26_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4D)
3643 #define REG_DVI_DTOP_DUAL_P0_27_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4E)
3644 #define REG_DVI_DTOP_DUAL_P0_27_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x4F)
3645 #define REG_DVI_DTOP_DUAL_P0_28_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x50)
3646 #define REG_DVI_DTOP_DUAL_P0_28_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x51)
3647 #define REG_DVI_DTOP_DUAL_P0_29_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x52)
3648 #define REG_DVI_DTOP_DUAL_P0_29_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x53)
3649 #define REG_DVI_DTOP_DUAL_P0_2A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x54)
3650 #define REG_DVI_DTOP_DUAL_P0_2A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x55)
3651 #define REG_DVI_DTOP_DUAL_P0_2B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x56)
3652 #define REG_DVI_DTOP_DUAL_P0_2B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x57)
3653 #define REG_DVI_DTOP_DUAL_P0_2C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x58)
3654 #define REG_DVI_DTOP_DUAL_P0_2C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x59)
3655 #define REG_DVI_DTOP_DUAL_P0_2D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5A)
3656 #define REG_DVI_DTOP_DUAL_P0_2D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5B)
3657 #define REG_DVI_DTOP_DUAL_P0_2E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5C)
3658 #define REG_DVI_DTOP_DUAL_P0_2E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5D)
3659 #define REG_DVI_DTOP_DUAL_P0_2F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5E)
3660 #define REG_DVI_DTOP_DUAL_P0_2F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x5F)
3661 #define REG_DVI_DTOP_DUAL_P0_30_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x60)
3662 #define REG_DVI_DTOP_DUAL_P0_30_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x61)
3663 #define REG_DVI_DTOP_DUAL_P0_31_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x62)
3664 #define REG_DVI_DTOP_DUAL_P0_31_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x63)
3665 #define REG_DVI_DTOP_DUAL_P0_32_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x64)
3666 #define REG_DVI_DTOP_DUAL_P0_32_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x65)
3667 #define REG_DVI_DTOP_DUAL_P0_33_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x66)
3668 #define REG_DVI_DTOP_DUAL_P0_33_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x67)
3669 #define REG_DVI_DTOP_DUAL_P0_34_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x68)
3670 #define REG_DVI_DTOP_DUAL_P0_34_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x69)
3671 #define REG_DVI_DTOP_DUAL_P0_35_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6A)
3672 #define REG_DVI_DTOP_DUAL_P0_35_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6B)
3673 #define REG_DVI_DTOP_DUAL_P0_36_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6C)
3674 #define REG_DVI_DTOP_DUAL_P0_36_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6D)
3675 #define REG_DVI_DTOP_DUAL_P0_37_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6E)
3676 #define REG_DVI_DTOP_DUAL_P0_37_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x6F)
3677 #define REG_DVI_DTOP_DUAL_P0_38_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x70)
3678 #define REG_DVI_DTOP_DUAL_P0_38_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x71)
3679 #define REG_DVI_DTOP_DUAL_P0_39_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x72)
3680 #define REG_DVI_DTOP_DUAL_P0_39_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x73)
3681 #define REG_DVI_DTOP_DUAL_P0_3A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x74)
3682 #define REG_DVI_DTOP_DUAL_P0_3A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x75)
3683 #define REG_DVI_DTOP_DUAL_P0_3B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x76)
3684 #define REG_DVI_DTOP_DUAL_P0_3B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x77)
3685 #define REG_DVI_DTOP_DUAL_P0_3C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x78)
3686 #define REG_DVI_DTOP_DUAL_P0_3C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x79)
3687 #define REG_DVI_DTOP_DUAL_P0_3D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7A)
3688 #define REG_DVI_DTOP_DUAL_P0_3D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7B)
3689 #define REG_DVI_DTOP_DUAL_P0_3E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7C)
3690 #define REG_DVI_DTOP_DUAL_P0_3E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7D)
3691 #define REG_DVI_DTOP_DUAL_P0_3F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7E)
3692 #define REG_DVI_DTOP_DUAL_P0_3F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x7F)
3693 #define REG_DVI_DTOP_DUAL_P0_40_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x80)
3694 #define REG_DVI_DTOP_DUAL_P0_40_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x81)
3695 #define REG_DVI_DTOP_DUAL_P0_41_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x82)
3696 #define REG_DVI_DTOP_DUAL_P0_41_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x83)
3697 #define REG_DVI_DTOP_DUAL_P0_42_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x84)
3698 #define REG_DVI_DTOP_DUAL_P0_42_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x85)
3699 #define REG_DVI_DTOP_DUAL_P0_43_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x86)
3700 #define REG_DVI_DTOP_DUAL_P0_43_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x87)
3701 #define REG_DVI_DTOP_DUAL_P0_44_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x88)
3702 #define REG_DVI_DTOP_DUAL_P0_44_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x89)
3703 #define REG_DVI_DTOP_DUAL_P0_45_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8A)
3704 #define REG_DVI_DTOP_DUAL_P0_45_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8B)
3705 #define REG_DVI_DTOP_DUAL_P0_46_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8C)
3706 #define REG_DVI_DTOP_DUAL_P0_46_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8D)
3707 #define REG_DVI_DTOP_DUAL_P0_47_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8E)
3708 #define REG_DVI_DTOP_DUAL_P0_47_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x8F)
3709 #define REG_DVI_DTOP_DUAL_P0_48_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x90)
3710 #define REG_DVI_DTOP_DUAL_P0_48_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x91)
3711 #define REG_DVI_DTOP_DUAL_P0_49_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x92)
3712 #define REG_DVI_DTOP_DUAL_P0_49_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x93)
3713 #define REG_DVI_DTOP_DUAL_P0_4A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x94)
3714 #define REG_DVI_DTOP_DUAL_P0_4A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x95)
3715 #define REG_DVI_DTOP_DUAL_P0_4B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x96)
3716 #define REG_DVI_DTOP_DUAL_P0_4B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x97)
3717 #define REG_DVI_DTOP_DUAL_P0_4C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x98)
3718 #define REG_DVI_DTOP_DUAL_P0_4C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x99)
3719 #define REG_DVI_DTOP_DUAL_P0_4D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9A)
3720 #define REG_DVI_DTOP_DUAL_P0_4D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9B)
3721 #define REG_DVI_DTOP_DUAL_P0_4E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9C)
3722 #define REG_DVI_DTOP_DUAL_P0_4E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9D)
3723 #define REG_DVI_DTOP_DUAL_P0_4F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9E)
3724 #define REG_DVI_DTOP_DUAL_P0_4F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0x9F)
3725 #define REG_DVI_DTOP_DUAL_P0_50_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA0)
3726 #define REG_DVI_DTOP_DUAL_P0_50_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA1)
3727 #define REG_DVI_DTOP_DUAL_P0_51_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA2)
3728 #define REG_DVI_DTOP_DUAL_P0_51_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA3)
3729 #define REG_DVI_DTOP_DUAL_P0_52_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA4)
3730 #define REG_DVI_DTOP_DUAL_P0_52_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA5)
3731 #define REG_DVI_DTOP_DUAL_P0_53_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA6)
3732 #define REG_DVI_DTOP_DUAL_P0_53_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA7)
3733 #define REG_DVI_DTOP_DUAL_P0_54_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA8)
3734 #define REG_DVI_DTOP_DUAL_P0_54_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xA9)
3735 #define REG_DVI_DTOP_DUAL_P0_55_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAA)
3736 #define REG_DVI_DTOP_DUAL_P0_55_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAB)
3737 #define REG_DVI_DTOP_DUAL_P0_56_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAC)
3738 #define REG_DVI_DTOP_DUAL_P0_56_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAD)
3739 #define REG_DVI_DTOP_DUAL_P0_57_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAE)
3740 #define REG_DVI_DTOP_DUAL_P0_57_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xAF)
3741 #define REG_DVI_DTOP_DUAL_P0_58_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB0)
3742 #define REG_DVI_DTOP_DUAL_P0_58_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB1)
3743 #define REG_DVI_DTOP_DUAL_P0_59_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB2)
3744 #define REG_DVI_DTOP_DUAL_P0_59_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB3)
3745 #define REG_DVI_DTOP_DUAL_P0_5A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB4)
3746 #define REG_DVI_DTOP_DUAL_P0_5A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB5)
3747 #define REG_DVI_DTOP_DUAL_P0_5B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB6)
3748 #define REG_DVI_DTOP_DUAL_P0_5B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB7)
3749 #define REG_DVI_DTOP_DUAL_P0_5C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB8)
3750 #define REG_DVI_DTOP_DUAL_P0_5C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xB9)
3751 #define REG_DVI_DTOP_DUAL_P0_5D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBA)
3752 #define REG_DVI_DTOP_DUAL_P0_5D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBB)
3753 #define REG_DVI_DTOP_DUAL_P0_5E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBC)
3754 #define REG_DVI_DTOP_DUAL_P0_5E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBD)
3755 #define REG_DVI_DTOP_DUAL_P0_5F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBE)
3756 #define REG_DVI_DTOP_DUAL_P0_5F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xBF)
3757 #define REG_DVI_DTOP_DUAL_P0_60_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC0)
3758 #define REG_DVI_DTOP_DUAL_P0_60_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC1)
3759 #define REG_DVI_DTOP_DUAL_P0_61_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC2)
3760 #define REG_DVI_DTOP_DUAL_P0_61_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC3)
3761 #define REG_DVI_DTOP_DUAL_P0_62_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC4)
3762 #define REG_DVI_DTOP_DUAL_P0_62_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC5)
3763 #define REG_DVI_DTOP_DUAL_P0_63_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC6)
3764 #define REG_DVI_DTOP_DUAL_P0_63_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC7)
3765 #define REG_DVI_DTOP_DUAL_P0_64_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC8)
3766 #define REG_DVI_DTOP_DUAL_P0_64_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xC9)
3767 #define REG_DVI_DTOP_DUAL_P0_65_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCA)
3768 #define REG_DVI_DTOP_DUAL_P0_65_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCB)
3769 #define REG_DVI_DTOP_DUAL_P0_66_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCC)
3770 #define REG_DVI_DTOP_DUAL_P0_66_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCD)
3771 #define REG_DVI_DTOP_DUAL_P0_67_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCE)
3772 #define REG_DVI_DTOP_DUAL_P0_67_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xCF)
3773 #define REG_DVI_DTOP_DUAL_P0_68_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD0)
3774 #define REG_DVI_DTOP_DUAL_P0_68_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD1)
3775 #define REG_DVI_DTOP_DUAL_P0_69_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD2)
3776 #define REG_DVI_DTOP_DUAL_P0_69_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD3)
3777 #define REG_DVI_DTOP_DUAL_P0_6A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD4)
3778 #define REG_DVI_DTOP_DUAL_P0_6A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD5)
3779 #define REG_DVI_DTOP_DUAL_P0_6B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD6)
3780 #define REG_DVI_DTOP_DUAL_P0_6B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD7)
3781 #define REG_DVI_DTOP_DUAL_P0_6C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD8)
3782 #define REG_DVI_DTOP_DUAL_P0_6C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xD9)
3783 #define REG_DVI_DTOP_DUAL_P0_6D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDA)
3784 #define REG_DVI_DTOP_DUAL_P0_6D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDB)
3785 #define REG_DVI_DTOP_DUAL_P0_6E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDC)
3786 #define REG_DVI_DTOP_DUAL_P0_6E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDD)
3787 #define REG_DVI_DTOP_DUAL_P0_6F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDE)
3788 #define REG_DVI_DTOP_DUAL_P0_6F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xDF)
3789 #define REG_DVI_DTOP_DUAL_P0_70_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE0)
3790 #define REG_DVI_DTOP_DUAL_P0_70_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE1)
3791 #define REG_DVI_DTOP_DUAL_P0_71_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE2)
3792 #define REG_DVI_DTOP_DUAL_P0_71_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE3)
3793 #define REG_DVI_DTOP_DUAL_P0_72_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE4)
3794 #define REG_DVI_DTOP_DUAL_P0_72_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE5)
3795 #define REG_DVI_DTOP_DUAL_P0_73_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE6)
3796 #define REG_DVI_DTOP_DUAL_P0_73_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE7)
3797 #define REG_DVI_DTOP_DUAL_P0_74_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE8)
3798 #define REG_DVI_DTOP_DUAL_P0_74_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xE9)
3799 #define REG_DVI_DTOP_DUAL_P0_75_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEA)
3800 #define REG_DVI_DTOP_DUAL_P0_75_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEB)
3801 #define REG_DVI_DTOP_DUAL_P0_76_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEC)
3802 #define REG_DVI_DTOP_DUAL_P0_76_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xED)
3803 #define REG_DVI_DTOP_DUAL_P0_77_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEE)
3804 #define REG_DVI_DTOP_DUAL_P0_77_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xEF)
3805 #define REG_DVI_DTOP_DUAL_P0_78_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF0)
3806 #define REG_DVI_DTOP_DUAL_P0_78_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF1)
3807 #define REG_DVI_DTOP_DUAL_P0_79_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF2)
3808 #define REG_DVI_DTOP_DUAL_P0_79_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF3)
3809 #define REG_DVI_DTOP_DUAL_P0_7A_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF4)
3810 #define REG_DVI_DTOP_DUAL_P0_7A_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF5)
3811 #define REG_DVI_DTOP_DUAL_P0_7B_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF6)
3812 #define REG_DVI_DTOP_DUAL_P0_7B_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF7)
3813 #define REG_DVI_DTOP_DUAL_P0_7C_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF8)
3814 #define REG_DVI_DTOP_DUAL_P0_7C_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xF9)
3815 #define REG_DVI_DTOP_DUAL_P0_7D_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFA)
3816 #define REG_DVI_DTOP_DUAL_P0_7D_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFB)
3817 #define REG_DVI_DTOP_DUAL_P0_7E_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFC)
3818 #define REG_DVI_DTOP_DUAL_P0_7E_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFD)
3819 #define REG_DVI_DTOP_DUAL_P0_7F_L       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFE)
3820 #define REG_DVI_DTOP_DUAL_P0_7F_H       (REG_DVI_DTOP_DUAL_P0_BASE + 0xFF)
3821 
3822 // DVI_RSV_DUAL_P0
3823 #define REG_DVI_RSV_DUAL_P0_00_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x00)
3824 #define REG_DVI_RSV_DUAL_P0_00_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x01)
3825 #define REG_DVI_RSV_DUAL_P0_01_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x02)
3826 #define REG_DVI_RSV_DUAL_P0_01_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x03)
3827 #define REG_DVI_RSV_DUAL_P0_02_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x04)
3828 #define REG_DVI_RSV_DUAL_P0_02_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x05)
3829 #define REG_DVI_RSV_DUAL_P0_03_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x06)
3830 #define REG_DVI_RSV_DUAL_P0_03_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x07)
3831 #define REG_DVI_RSV_DUAL_P0_04_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x08)
3832 #define REG_DVI_RSV_DUAL_P0_04_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x09)
3833 #define REG_DVI_RSV_DUAL_P0_05_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x0A)
3834 #define REG_DVI_RSV_DUAL_P0_05_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x0B)
3835 #define REG_DVI_RSV_DUAL_P0_06_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x0C)
3836 #define REG_DVI_RSV_DUAL_P0_06_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x0D)
3837 #define REG_DVI_RSV_DUAL_P0_07_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x0E)
3838 #define REG_DVI_RSV_DUAL_P0_07_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x0F)
3839 #define REG_DVI_RSV_DUAL_P0_08_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x10)
3840 #define REG_DVI_RSV_DUAL_P0_08_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x11)
3841 #define REG_DVI_RSV_DUAL_P0_09_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x12)
3842 #define REG_DVI_RSV_DUAL_P0_09_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x13)
3843 #define REG_DVI_RSV_DUAL_P0_0A_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x14)
3844 #define REG_DVI_RSV_DUAL_P0_0A_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x15)
3845 #define REG_DVI_RSV_DUAL_P0_0B_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x16)
3846 #define REG_DVI_RSV_DUAL_P0_0B_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x17)
3847 #define REG_DVI_RSV_DUAL_P0_0C_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x18)
3848 #define REG_DVI_RSV_DUAL_P0_0C_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x19)
3849 #define REG_DVI_RSV_DUAL_P0_0D_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x1A)
3850 #define REG_DVI_RSV_DUAL_P0_0D_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x1B)
3851 #define REG_DVI_RSV_DUAL_P0_0E_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x1C)
3852 #define REG_DVI_RSV_DUAL_P0_0E_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x1D)
3853 #define REG_DVI_RSV_DUAL_P0_0F_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x1E)
3854 #define REG_DVI_RSV_DUAL_P0_0F_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x1F)
3855 #define REG_DVI_RSV_DUAL_P0_10_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x20)
3856 #define REG_DVI_RSV_DUAL_P0_10_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x21)
3857 #define REG_DVI_RSV_DUAL_P0_11_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x22)
3858 #define REG_DVI_RSV_DUAL_P0_11_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x23)
3859 #define REG_DVI_RSV_DUAL_P0_12_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x24)
3860 #define REG_DVI_RSV_DUAL_P0_12_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x25)
3861 #define REG_DVI_RSV_DUAL_P0_13_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x26)
3862 #define REG_DVI_RSV_DUAL_P0_13_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x27)
3863 #define REG_DVI_RSV_DUAL_P0_14_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x28)
3864 #define REG_DVI_RSV_DUAL_P0_14_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x29)
3865 #define REG_DVI_RSV_DUAL_P0_15_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x2A)
3866 #define REG_DVI_RSV_DUAL_P0_15_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x2B)
3867 #define REG_DVI_RSV_DUAL_P0_16_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x2C)
3868 #define REG_DVI_RSV_DUAL_P0_16_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x2D)
3869 #define REG_DVI_RSV_DUAL_P0_17_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x2E)
3870 #define REG_DVI_RSV_DUAL_P0_17_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x2F)
3871 #define REG_DVI_RSV_DUAL_P0_18_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x30)
3872 #define REG_DVI_RSV_DUAL_P0_18_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x31)
3873 #define REG_DVI_RSV_DUAL_P0_19_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x32)
3874 #define REG_DVI_RSV_DUAL_P0_19_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x33)
3875 #define REG_DVI_RSV_DUAL_P0_1A_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x34)
3876 #define REG_DVI_RSV_DUAL_P0_1A_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x35)
3877 #define REG_DVI_RSV_DUAL_P0_1B_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x36)
3878 #define REG_DVI_RSV_DUAL_P0_1B_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x37)
3879 #define REG_DVI_RSV_DUAL_P0_1C_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x38)
3880 #define REG_DVI_RSV_DUAL_P0_1C_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x39)
3881 #define REG_DVI_RSV_DUAL_P0_1D_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x3A)
3882 #define REG_DVI_RSV_DUAL_P0_1D_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x3B)
3883 #define REG_DVI_RSV_DUAL_P0_1E_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x3C)
3884 #define REG_DVI_RSV_DUAL_P0_1E_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x3D)
3885 #define REG_DVI_RSV_DUAL_P0_1F_L       (REG_DVI_RSV_DUAL_P0_BASE + 0x3E)
3886 #define REG_DVI_RSV_DUAL_P0_1F_H       (REG_DVI_RSV_DUAL_P0_BASE + 0x3F)
3887 
3888 // HDCP_DUAL_P0
3889 #define REG_HDCP_DUAL_P0_00_L       (REG_HDCP_DUAL_P0_BASE + 0x00)
3890 #define REG_HDCP_DUAL_P0_00_H       (REG_HDCP_DUAL_P0_BASE + 0x01)
3891 #define REG_HDCP_DUAL_P0_01_L       (REG_HDCP_DUAL_P0_BASE + 0x02)
3892 #define REG_HDCP_DUAL_P0_01_H       (REG_HDCP_DUAL_P0_BASE + 0x03)
3893 #define REG_HDCP_DUAL_P0_02_L       (REG_HDCP_DUAL_P0_BASE + 0x04)
3894 #define REG_HDCP_DUAL_P0_02_H       (REG_HDCP_DUAL_P0_BASE + 0x05)
3895 #define REG_HDCP_DUAL_P0_03_L       (REG_HDCP_DUAL_P0_BASE + 0x06)
3896 #define REG_HDCP_DUAL_P0_03_H       (REG_HDCP_DUAL_P0_BASE + 0x07)
3897 #define REG_HDCP_DUAL_P0_04_L       (REG_HDCP_DUAL_P0_BASE + 0x08)
3898 #define REG_HDCP_DUAL_P0_04_H       (REG_HDCP_DUAL_P0_BASE + 0x09)
3899 #define REG_HDCP_DUAL_P0_05_L       (REG_HDCP_DUAL_P0_BASE + 0x0A)
3900 #define REG_HDCP_DUAL_P0_05_H       (REG_HDCP_DUAL_P0_BASE + 0x0B)
3901 #define REG_HDCP_DUAL_P0_06_L       (REG_HDCP_DUAL_P0_BASE + 0x0C)
3902 #define REG_HDCP_DUAL_P0_06_H       (REG_HDCP_DUAL_P0_BASE + 0x0D)
3903 #define REG_HDCP_DUAL_P0_07_L       (REG_HDCP_DUAL_P0_BASE + 0x0E)
3904 #define REG_HDCP_DUAL_P0_07_H       (REG_HDCP_DUAL_P0_BASE + 0x0F)
3905 #define REG_HDCP_DUAL_P0_08_L       (REG_HDCP_DUAL_P0_BASE + 0x10)
3906 #define REG_HDCP_DUAL_P0_08_H       (REG_HDCP_DUAL_P0_BASE + 0x11)
3907 #define REG_HDCP_DUAL_P0_09_L       (REG_HDCP_DUAL_P0_BASE + 0x12)
3908 #define REG_HDCP_DUAL_P0_09_H       (REG_HDCP_DUAL_P0_BASE + 0x13)
3909 #define REG_HDCP_DUAL_P0_0A_L       (REG_HDCP_DUAL_P0_BASE + 0x14)
3910 #define REG_HDCP_DUAL_P0_0A_H       (REG_HDCP_DUAL_P0_BASE + 0x15)
3911 #define REG_HDCP_DUAL_P0_0B_L       (REG_HDCP_DUAL_P0_BASE + 0x16)
3912 #define REG_HDCP_DUAL_P0_0B_H       (REG_HDCP_DUAL_P0_BASE + 0x17)
3913 #define REG_HDCP_DUAL_P0_0C_L       (REG_HDCP_DUAL_P0_BASE + 0x18)
3914 #define REG_HDCP_DUAL_P0_0C_H       (REG_HDCP_DUAL_P0_BASE + 0x19)
3915 #define REG_HDCP_DUAL_P0_0D_L       (REG_HDCP_DUAL_P0_BASE + 0x1A)
3916 #define REG_HDCP_DUAL_P0_0D_H       (REG_HDCP_DUAL_P0_BASE + 0x1B)
3917 #define REG_HDCP_DUAL_P0_0E_L       (REG_HDCP_DUAL_P0_BASE + 0x1C)
3918 #define REG_HDCP_DUAL_P0_0E_H       (REG_HDCP_DUAL_P0_BASE + 0x1D)
3919 #define REG_HDCP_DUAL_P0_0F_L       (REG_HDCP_DUAL_P0_BASE + 0x1E)
3920 #define REG_HDCP_DUAL_P0_0F_H       (REG_HDCP_DUAL_P0_BASE + 0x1F)
3921 #define REG_HDCP_DUAL_P0_10_L       (REG_HDCP_DUAL_P0_BASE + 0x20)
3922 #define REG_HDCP_DUAL_P0_10_H       (REG_HDCP_DUAL_P0_BASE + 0x21)
3923 #define REG_HDCP_DUAL_P0_11_L       (REG_HDCP_DUAL_P0_BASE + 0x22)
3924 #define REG_HDCP_DUAL_P0_11_H       (REG_HDCP_DUAL_P0_BASE + 0x23)
3925 #define REG_HDCP_DUAL_P0_12_L       (REG_HDCP_DUAL_P0_BASE + 0x24)
3926 #define REG_HDCP_DUAL_P0_12_H       (REG_HDCP_DUAL_P0_BASE + 0x25)
3927 #define REG_HDCP_DUAL_P0_13_L       (REG_HDCP_DUAL_P0_BASE + 0x26)
3928 #define REG_HDCP_DUAL_P0_13_H       (REG_HDCP_DUAL_P0_BASE + 0x27)
3929 #define REG_HDCP_DUAL_P0_14_L       (REG_HDCP_DUAL_P0_BASE + 0x28)
3930 #define REG_HDCP_DUAL_P0_14_H       (REG_HDCP_DUAL_P0_BASE + 0x29)
3931 #define REG_HDCP_DUAL_P0_15_L       (REG_HDCP_DUAL_P0_BASE + 0x2A)
3932 #define REG_HDCP_DUAL_P0_15_H       (REG_HDCP_DUAL_P0_BASE + 0x2B)
3933 #define REG_HDCP_DUAL_P0_16_L       (REG_HDCP_DUAL_P0_BASE + 0x2C)
3934 #define REG_HDCP_DUAL_P0_16_H       (REG_HDCP_DUAL_P0_BASE + 0x2D)
3935 #define REG_HDCP_DUAL_P0_17_L       (REG_HDCP_DUAL_P0_BASE + 0x2E)
3936 #define REG_HDCP_DUAL_P0_17_H       (REG_HDCP_DUAL_P0_BASE + 0x2F)
3937 #define REG_HDCP_DUAL_P0_18_L       (REG_HDCP_DUAL_P0_BASE + 0x30)
3938 #define REG_HDCP_DUAL_P0_18_H       (REG_HDCP_DUAL_P0_BASE + 0x31)
3939 #define REG_HDCP_DUAL_P0_19_L       (REG_HDCP_DUAL_P0_BASE + 0x32)
3940 #define REG_HDCP_DUAL_P0_19_H       (REG_HDCP_DUAL_P0_BASE + 0x33)
3941 #define REG_HDCP_DUAL_P0_1A_L       (REG_HDCP_DUAL_P0_BASE + 0x34)
3942 #define REG_HDCP_DUAL_P0_1A_H       (REG_HDCP_DUAL_P0_BASE + 0x35)
3943 #define REG_HDCP_DUAL_P0_1B_L       (REG_HDCP_DUAL_P0_BASE + 0x36)
3944 #define REG_HDCP_DUAL_P0_1B_H       (REG_HDCP_DUAL_P0_BASE + 0x37)
3945 #define REG_HDCP_DUAL_P0_1C_L       (REG_HDCP_DUAL_P0_BASE + 0x38)
3946 #define REG_HDCP_DUAL_P0_1C_H       (REG_HDCP_DUAL_P0_BASE + 0x39)
3947 #define REG_HDCP_DUAL_P0_1D_L       (REG_HDCP_DUAL_P0_BASE + 0x3A)
3948 #define REG_HDCP_DUAL_P0_1D_H       (REG_HDCP_DUAL_P0_BASE + 0x3B)
3949 #define REG_HDCP_DUAL_P0_1E_L       (REG_HDCP_DUAL_P0_BASE + 0x3C)
3950 #define REG_HDCP_DUAL_P0_1E_H       (REG_HDCP_DUAL_P0_BASE + 0x3D)
3951 #define REG_HDCP_DUAL_P0_1F_L       (REG_HDCP_DUAL_P0_BASE + 0x3E)
3952 #define REG_HDCP_DUAL_P0_1F_H       (REG_HDCP_DUAL_P0_BASE + 0x3F)
3953 #define REG_HDCP_DUAL_P0_20_L       (REG_HDCP_DUAL_P0_BASE + 0x40)
3954 #define REG_HDCP_DUAL_P0_20_H       (REG_HDCP_DUAL_P0_BASE + 0x41)
3955 #define REG_HDCP_DUAL_P0_21_L       (REG_HDCP_DUAL_P0_BASE + 0x42)
3956 #define REG_HDCP_DUAL_P0_21_H       (REG_HDCP_DUAL_P0_BASE + 0x43)
3957 #define REG_HDCP_DUAL_P0_22_L       (REG_HDCP_DUAL_P0_BASE + 0x44)
3958 #define REG_HDCP_DUAL_P0_22_H       (REG_HDCP_DUAL_P0_BASE + 0x45)
3959 #define REG_HDCP_DUAL_P0_23_L       (REG_HDCP_DUAL_P0_BASE + 0x46)
3960 #define REG_HDCP_DUAL_P0_23_H       (REG_HDCP_DUAL_P0_BASE + 0x47)
3961 #define REG_HDCP_DUAL_P0_24_L       (REG_HDCP_DUAL_P0_BASE + 0x48)
3962 #define REG_HDCP_DUAL_P0_24_H       (REG_HDCP_DUAL_P0_BASE + 0x49)
3963 #define REG_HDCP_DUAL_P0_25_L       (REG_HDCP_DUAL_P0_BASE + 0x4A)
3964 #define REG_HDCP_DUAL_P0_25_H       (REG_HDCP_DUAL_P0_BASE + 0x4B)
3965 #define REG_HDCP_DUAL_P0_26_L       (REG_HDCP_DUAL_P0_BASE + 0x4C)
3966 #define REG_HDCP_DUAL_P0_26_H       (REG_HDCP_DUAL_P0_BASE + 0x4D)
3967 #define REG_HDCP_DUAL_P0_27_L       (REG_HDCP_DUAL_P0_BASE + 0x4E)
3968 #define REG_HDCP_DUAL_P0_27_H       (REG_HDCP_DUAL_P0_BASE + 0x4F)
3969 #define REG_HDCP_DUAL_P0_28_L       (REG_HDCP_DUAL_P0_BASE + 0x50)
3970 #define REG_HDCP_DUAL_P0_28_H       (REG_HDCP_DUAL_P0_BASE + 0x51)
3971 #define REG_HDCP_DUAL_P0_29_L       (REG_HDCP_DUAL_P0_BASE + 0x52)
3972 #define REG_HDCP_DUAL_P0_29_H       (REG_HDCP_DUAL_P0_BASE + 0x53)
3973 #define REG_HDCP_DUAL_P0_2A_L       (REG_HDCP_DUAL_P0_BASE + 0x54)
3974 #define REG_HDCP_DUAL_P0_2A_H       (REG_HDCP_DUAL_P0_BASE + 0x55)
3975 #define REG_HDCP_DUAL_P0_2B_L       (REG_HDCP_DUAL_P0_BASE + 0x56)
3976 #define REG_HDCP_DUAL_P0_2B_H       (REG_HDCP_DUAL_P0_BASE + 0x57)
3977 #define REG_HDCP_DUAL_P0_2C_L       (REG_HDCP_DUAL_P0_BASE + 0x58)
3978 #define REG_HDCP_DUAL_P0_2C_H       (REG_HDCP_DUAL_P0_BASE + 0x59)
3979 #define REG_HDCP_DUAL_P0_2D_L       (REG_HDCP_DUAL_P0_BASE + 0x5A)
3980 #define REG_HDCP_DUAL_P0_2D_H       (REG_HDCP_DUAL_P0_BASE + 0x5B)
3981 #define REG_HDCP_DUAL_P0_2E_L       (REG_HDCP_DUAL_P0_BASE + 0x5C)
3982 #define REG_HDCP_DUAL_P0_2E_H       (REG_HDCP_DUAL_P0_BASE + 0x5D)
3983 #define REG_HDCP_DUAL_P0_2F_L       (REG_HDCP_DUAL_P0_BASE + 0x5E)
3984 #define REG_HDCP_DUAL_P0_2F_H       (REG_HDCP_DUAL_P0_BASE + 0x5F)
3985 #define REG_HDCP_DUAL_P0_30_L       (REG_HDCP_DUAL_P0_BASE + 0x60)
3986 #define REG_HDCP_DUAL_P0_30_H       (REG_HDCP_DUAL_P0_BASE + 0x61)
3987 #define REG_HDCP_DUAL_P0_31_L       (REG_HDCP_DUAL_P0_BASE + 0x62)
3988 #define REG_HDCP_DUAL_P0_31_H       (REG_HDCP_DUAL_P0_BASE + 0x63)
3989 #define REG_HDCP_DUAL_P0_32_L       (REG_HDCP_DUAL_P0_BASE + 0x64)
3990 #define REG_HDCP_DUAL_P0_32_H       (REG_HDCP_DUAL_P0_BASE + 0x65)
3991 #define REG_HDCP_DUAL_P0_33_L       (REG_HDCP_DUAL_P0_BASE + 0x66)
3992 #define REG_HDCP_DUAL_P0_33_H       (REG_HDCP_DUAL_P0_BASE + 0x67)
3993 #define REG_HDCP_DUAL_P0_34_L       (REG_HDCP_DUAL_P0_BASE + 0x68)
3994 #define REG_HDCP_DUAL_P0_34_H       (REG_HDCP_DUAL_P0_BASE + 0x69)
3995 #define REG_HDCP_DUAL_P0_35_L       (REG_HDCP_DUAL_P0_BASE + 0x6A)
3996 #define REG_HDCP_DUAL_P0_35_H       (REG_HDCP_DUAL_P0_BASE + 0x6B)
3997 #define REG_HDCP_DUAL_P0_36_L       (REG_HDCP_DUAL_P0_BASE + 0x6C)
3998 #define REG_HDCP_DUAL_P0_36_H       (REG_HDCP_DUAL_P0_BASE + 0x6D)
3999 #define REG_HDCP_DUAL_P0_37_L       (REG_HDCP_DUAL_P0_BASE + 0x6E)
4000 #define REG_HDCP_DUAL_P0_37_H       (REG_HDCP_DUAL_P0_BASE + 0x6F)
4001 #define REG_HDCP_DUAL_P0_38_L       (REG_HDCP_DUAL_P0_BASE + 0x70)
4002 #define REG_HDCP_DUAL_P0_38_H       (REG_HDCP_DUAL_P0_BASE + 0x71)
4003 #define REG_HDCP_DUAL_P0_39_L       (REG_HDCP_DUAL_P0_BASE + 0x72)
4004 #define REG_HDCP_DUAL_P0_39_H       (REG_HDCP_DUAL_P0_BASE + 0x73)
4005 #define REG_HDCP_DUAL_P0_3A_L       (REG_HDCP_DUAL_P0_BASE + 0x74)
4006 #define REG_HDCP_DUAL_P0_3A_H       (REG_HDCP_DUAL_P0_BASE + 0x75)
4007 #define REG_HDCP_DUAL_P0_3B_L       (REG_HDCP_DUAL_P0_BASE + 0x76)
4008 #define REG_HDCP_DUAL_P0_3B_H       (REG_HDCP_DUAL_P0_BASE + 0x77)
4009 #define REG_HDCP_DUAL_P0_3C_L       (REG_HDCP_DUAL_P0_BASE + 0x78)
4010 #define REG_HDCP_DUAL_P0_3C_H       (REG_HDCP_DUAL_P0_BASE + 0x79)
4011 #define REG_HDCP_DUAL_P0_3D_L       (REG_HDCP_DUAL_P0_BASE + 0x7A)
4012 #define REG_HDCP_DUAL_P0_3D_H       (REG_HDCP_DUAL_P0_BASE + 0x7B)
4013 #define REG_HDCP_DUAL_P0_3E_L       (REG_HDCP_DUAL_P0_BASE + 0x7C)
4014 #define REG_HDCP_DUAL_P0_3E_H       (REG_HDCP_DUAL_P0_BASE + 0x7D)
4015 #define REG_HDCP_DUAL_P0_3F_L       (REG_HDCP_DUAL_P0_BASE + 0x7E)
4016 #define REG_HDCP_DUAL_P0_3F_H       (REG_HDCP_DUAL_P0_BASE + 0x7F)
4017 #define REG_HDCP_DUAL_P0_40_L       (REG_HDCP_DUAL_P0_BASE + 0x80)
4018 #define REG_HDCP_DUAL_P0_40_H       (REG_HDCP_DUAL_P0_BASE + 0x81)
4019 #define REG_HDCP_DUAL_P0_41_L       (REG_HDCP_DUAL_P0_BASE + 0x82)
4020 #define REG_HDCP_DUAL_P0_41_H       (REG_HDCP_DUAL_P0_BASE + 0x83)
4021 #define REG_HDCP_DUAL_P0_42_L       (REG_HDCP_DUAL_P0_BASE + 0x84)
4022 #define REG_HDCP_DUAL_P0_42_H       (REG_HDCP_DUAL_P0_BASE + 0x85)
4023 #define REG_HDCP_DUAL_P0_43_L       (REG_HDCP_DUAL_P0_BASE + 0x86)
4024 #define REG_HDCP_DUAL_P0_43_H       (REG_HDCP_DUAL_P0_BASE + 0x87)
4025 #define REG_HDCP_DUAL_P0_44_L       (REG_HDCP_DUAL_P0_BASE + 0x88)
4026 #define REG_HDCP_DUAL_P0_44_H       (REG_HDCP_DUAL_P0_BASE + 0x89)
4027 #define REG_HDCP_DUAL_P0_45_L       (REG_HDCP_DUAL_P0_BASE + 0x8A)
4028 #define REG_HDCP_DUAL_P0_45_H       (REG_HDCP_DUAL_P0_BASE + 0x8B)
4029 #define REG_HDCP_DUAL_P0_46_L       (REG_HDCP_DUAL_P0_BASE + 0x8C)
4030 #define REG_HDCP_DUAL_P0_46_H       (REG_HDCP_DUAL_P0_BASE + 0x8D)
4031 #define REG_HDCP_DUAL_P0_47_L       (REG_HDCP_DUAL_P0_BASE + 0x8E)
4032 #define REG_HDCP_DUAL_P0_47_H       (REG_HDCP_DUAL_P0_BASE + 0x8F)
4033 #define REG_HDCP_DUAL_P0_48_L       (REG_HDCP_DUAL_P0_BASE + 0x90)
4034 #define REG_HDCP_DUAL_P0_48_H       (REG_HDCP_DUAL_P0_BASE + 0x91)
4035 #define REG_HDCP_DUAL_P0_49_L       (REG_HDCP_DUAL_P0_BASE + 0x92)
4036 #define REG_HDCP_DUAL_P0_49_H       (REG_HDCP_DUAL_P0_BASE + 0x93)
4037 #define REG_HDCP_DUAL_P0_4A_L       (REG_HDCP_DUAL_P0_BASE + 0x94)
4038 #define REG_HDCP_DUAL_P0_4A_H       (REG_HDCP_DUAL_P0_BASE + 0x95)
4039 #define REG_HDCP_DUAL_P0_4B_L       (REG_HDCP_DUAL_P0_BASE + 0x96)
4040 #define REG_HDCP_DUAL_P0_4B_H       (REG_HDCP_DUAL_P0_BASE + 0x97)
4041 #define REG_HDCP_DUAL_P0_4C_L       (REG_HDCP_DUAL_P0_BASE + 0x98)
4042 #define REG_HDCP_DUAL_P0_4C_H       (REG_HDCP_DUAL_P0_BASE + 0x99)
4043 #define REG_HDCP_DUAL_P0_4D_L       (REG_HDCP_DUAL_P0_BASE + 0x9A)
4044 #define REG_HDCP_DUAL_P0_4D_H       (REG_HDCP_DUAL_P0_BASE + 0x9B)
4045 #define REG_HDCP_DUAL_P0_4E_L       (REG_HDCP_DUAL_P0_BASE + 0x9C)
4046 #define REG_HDCP_DUAL_P0_4E_H       (REG_HDCP_DUAL_P0_BASE + 0x9D)
4047 #define REG_HDCP_DUAL_P0_4F_L       (REG_HDCP_DUAL_P0_BASE + 0x9E)
4048 #define REG_HDCP_DUAL_P0_4F_H       (REG_HDCP_DUAL_P0_BASE + 0x9F)
4049 #define REG_HDCP_DUAL_P0_50_L       (REG_HDCP_DUAL_P0_BASE + 0xA0)
4050 #define REG_HDCP_DUAL_P0_50_H       (REG_HDCP_DUAL_P0_BASE + 0xA1)
4051 #define REG_HDCP_DUAL_P0_51_L       (REG_HDCP_DUAL_P0_BASE + 0xA2)
4052 #define REG_HDCP_DUAL_P0_51_H       (REG_HDCP_DUAL_P0_BASE + 0xA3)
4053 #define REG_HDCP_DUAL_P0_52_L       (REG_HDCP_DUAL_P0_BASE + 0xA4)
4054 #define REG_HDCP_DUAL_P0_52_H       (REG_HDCP_DUAL_P0_BASE + 0xA5)
4055 #define REG_HDCP_DUAL_P0_53_L       (REG_HDCP_DUAL_P0_BASE + 0xA6)
4056 #define REG_HDCP_DUAL_P0_53_H       (REG_HDCP_DUAL_P0_BASE + 0xA7)
4057 #define REG_HDCP_DUAL_P0_54_L       (REG_HDCP_DUAL_P0_BASE + 0xA8)
4058 #define REG_HDCP_DUAL_P0_54_H       (REG_HDCP_DUAL_P0_BASE + 0xA9)
4059 #define REG_HDCP_DUAL_P0_55_L       (REG_HDCP_DUAL_P0_BASE + 0xAA)
4060 #define REG_HDCP_DUAL_P0_55_H       (REG_HDCP_DUAL_P0_BASE + 0xAB)
4061 #define REG_HDCP_DUAL_P0_56_L       (REG_HDCP_DUAL_P0_BASE + 0xAC)
4062 #define REG_HDCP_DUAL_P0_56_H       (REG_HDCP_DUAL_P0_BASE + 0xAD)
4063 #define REG_HDCP_DUAL_P0_57_L       (REG_HDCP_DUAL_P0_BASE + 0xAE)
4064 #define REG_HDCP_DUAL_P0_57_H       (REG_HDCP_DUAL_P0_BASE + 0xAF)
4065 #define REG_HDCP_DUAL_P0_58_L       (REG_HDCP_DUAL_P0_BASE + 0xB0)
4066 #define REG_HDCP_DUAL_P0_58_H       (REG_HDCP_DUAL_P0_BASE + 0xB1)
4067 #define REG_HDCP_DUAL_P0_59_L       (REG_HDCP_DUAL_P0_BASE + 0xB2)
4068 #define REG_HDCP_DUAL_P0_59_H       (REG_HDCP_DUAL_P0_BASE + 0xB3)
4069 #define REG_HDCP_DUAL_P0_5A_L       (REG_HDCP_DUAL_P0_BASE + 0xB4)
4070 #define REG_HDCP_DUAL_P0_5A_H       (REG_HDCP_DUAL_P0_BASE + 0xB5)
4071 #define REG_HDCP_DUAL_P0_5B_L       (REG_HDCP_DUAL_P0_BASE + 0xB6)
4072 #define REG_HDCP_DUAL_P0_5B_H       (REG_HDCP_DUAL_P0_BASE + 0xB7)
4073 #define REG_HDCP_DUAL_P0_5C_L       (REG_HDCP_DUAL_P0_BASE + 0xB8)
4074 #define REG_HDCP_DUAL_P0_5C_H       (REG_HDCP_DUAL_P0_BASE + 0xB9)
4075 #define REG_HDCP_DUAL_P0_5D_L       (REG_HDCP_DUAL_P0_BASE + 0xBA)
4076 #define REG_HDCP_DUAL_P0_5D_H       (REG_HDCP_DUAL_P0_BASE + 0xBB)
4077 #define REG_HDCP_DUAL_P0_5E_L       (REG_HDCP_DUAL_P0_BASE + 0xBC)
4078 #define REG_HDCP_DUAL_P0_5E_H       (REG_HDCP_DUAL_P0_BASE + 0xBD)
4079 #define REG_HDCP_DUAL_P0_5F_L       (REG_HDCP_DUAL_P0_BASE + 0xBE)
4080 #define REG_HDCP_DUAL_P0_5F_H       (REG_HDCP_DUAL_P0_BASE + 0xBF)
4081 #define REG_HDCP_DUAL_P0_60_L       (REG_HDCP_DUAL_P0_BASE + 0xC0)
4082 #define REG_HDCP_DUAL_P0_60_H       (REG_HDCP_DUAL_P0_BASE + 0xC1)
4083 #define REG_HDCP_DUAL_P0_61_L       (REG_HDCP_DUAL_P0_BASE + 0xC2)
4084 #define REG_HDCP_DUAL_P0_61_H       (REG_HDCP_DUAL_P0_BASE + 0xC3)
4085 #define REG_HDCP_DUAL_P0_62_L       (REG_HDCP_DUAL_P0_BASE + 0xC4)
4086 #define REG_HDCP_DUAL_P0_62_H       (REG_HDCP_DUAL_P0_BASE + 0xC5)
4087 #define REG_HDCP_DUAL_P0_63_L       (REG_HDCP_DUAL_P0_BASE + 0xC6)
4088 #define REG_HDCP_DUAL_P0_63_H       (REG_HDCP_DUAL_P0_BASE + 0xC7)
4089 #define REG_HDCP_DUAL_P0_64_L       (REG_HDCP_DUAL_P0_BASE + 0xC8)
4090 #define REG_HDCP_DUAL_P0_64_H       (REG_HDCP_DUAL_P0_BASE + 0xC9)
4091 #define REG_HDCP_DUAL_P0_65_L       (REG_HDCP_DUAL_P0_BASE + 0xCA)
4092 #define REG_HDCP_DUAL_P0_65_H       (REG_HDCP_DUAL_P0_BASE + 0xCB)
4093 #define REG_HDCP_DUAL_P0_66_L       (REG_HDCP_DUAL_P0_BASE + 0xCC)
4094 #define REG_HDCP_DUAL_P0_66_H       (REG_HDCP_DUAL_P0_BASE + 0xCD)
4095 #define REG_HDCP_DUAL_P0_67_L       (REG_HDCP_DUAL_P0_BASE + 0xCE)
4096 #define REG_HDCP_DUAL_P0_67_H       (REG_HDCP_DUAL_P0_BASE + 0xCF)
4097 #define REG_HDCP_DUAL_P0_68_L       (REG_HDCP_DUAL_P0_BASE + 0xD0)
4098 #define REG_HDCP_DUAL_P0_68_H       (REG_HDCP_DUAL_P0_BASE + 0xD1)
4099 
4100 // DVI_DTOP_DUAL_P1
4101 #define REG_DVI_DTOP_DUAL_P1_00_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x00)
4102 #define REG_DVI_DTOP_DUAL_P1_00_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x01)
4103 #define REG_DVI_DTOP_DUAL_P1_01_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x02)
4104 #define REG_DVI_DTOP_DUAL_P1_01_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x03)
4105 #define REG_DVI_DTOP_DUAL_P1_02_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x04)
4106 #define REG_DVI_DTOP_DUAL_P1_02_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x05)
4107 #define REG_DVI_DTOP_DUAL_P1_03_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x06)
4108 #define REG_DVI_DTOP_DUAL_P1_03_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x07)
4109 #define REG_DVI_DTOP_DUAL_P1_04_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x08)
4110 #define REG_DVI_DTOP_DUAL_P1_04_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x09)
4111 #define REG_DVI_DTOP_DUAL_P1_05_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0A)
4112 #define REG_DVI_DTOP_DUAL_P1_05_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0B)
4113 #define REG_DVI_DTOP_DUAL_P1_06_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0C)
4114 #define REG_DVI_DTOP_DUAL_P1_06_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0D)
4115 #define REG_DVI_DTOP_DUAL_P1_07_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0E)
4116 #define REG_DVI_DTOP_DUAL_P1_07_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x0F)
4117 #define REG_DVI_DTOP_DUAL_P1_08_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x10)
4118 #define REG_DVI_DTOP_DUAL_P1_08_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x11)
4119 #define REG_DVI_DTOP_DUAL_P1_09_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x12)
4120 #define REG_DVI_DTOP_DUAL_P1_09_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x13)
4121 #define REG_DVI_DTOP_DUAL_P1_0A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x14)
4122 #define REG_DVI_DTOP_DUAL_P1_0A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x15)
4123 #define REG_DVI_DTOP_DUAL_P1_0B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x16)
4124 #define REG_DVI_DTOP_DUAL_P1_0B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x17)
4125 #define REG_DVI_DTOP_DUAL_P1_0C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x18)
4126 #define REG_DVI_DTOP_DUAL_P1_0C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x19)
4127 #define REG_DVI_DTOP_DUAL_P1_0D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1A)
4128 #define REG_DVI_DTOP_DUAL_P1_0D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1B)
4129 #define REG_DVI_DTOP_DUAL_P1_0E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1C)
4130 #define REG_DVI_DTOP_DUAL_P1_0E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1D)
4131 #define REG_DVI_DTOP_DUAL_P1_0F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1E)
4132 #define REG_DVI_DTOP_DUAL_P1_0F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x1F)
4133 #define REG_DVI_DTOP_DUAL_P1_10_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x20)
4134 #define REG_DVI_DTOP_DUAL_P1_10_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x21)
4135 #define REG_DVI_DTOP_DUAL_P1_11_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x22)
4136 #define REG_DVI_DTOP_DUAL_P1_11_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x23)
4137 #define REG_DVI_DTOP_DUAL_P1_12_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x24)
4138 #define REG_DVI_DTOP_DUAL_P1_12_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x25)
4139 #define REG_DVI_DTOP_DUAL_P1_13_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x26)
4140 #define REG_DVI_DTOP_DUAL_P1_13_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x27)
4141 #define REG_DVI_DTOP_DUAL_P1_14_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x28)
4142 #define REG_DVI_DTOP_DUAL_P1_14_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x29)
4143 #define REG_DVI_DTOP_DUAL_P1_15_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2A)
4144 #define REG_DVI_DTOP_DUAL_P1_15_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2B)
4145 #define REG_DVI_DTOP_DUAL_P1_16_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2C)
4146 #define REG_DVI_DTOP_DUAL_P1_16_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2D)
4147 #define REG_DVI_DTOP_DUAL_P1_17_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2E)
4148 #define REG_DVI_DTOP_DUAL_P1_17_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x2F)
4149 #define REG_DVI_DTOP_DUAL_P1_18_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x30)
4150 #define REG_DVI_DTOP_DUAL_P1_18_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x31)
4151 #define REG_DVI_DTOP_DUAL_P1_19_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x32)
4152 #define REG_DVI_DTOP_DUAL_P1_19_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x33)
4153 #define REG_DVI_DTOP_DUAL_P1_1A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x34)
4154 #define REG_DVI_DTOP_DUAL_P1_1A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x35)
4155 #define REG_DVI_DTOP_DUAL_P1_1B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x36)
4156 #define REG_DVI_DTOP_DUAL_P1_1B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x37)
4157 #define REG_DVI_DTOP_DUAL_P1_1C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x38)
4158 #define REG_DVI_DTOP_DUAL_P1_1C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x39)
4159 #define REG_DVI_DTOP_DUAL_P1_1D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3A)
4160 #define REG_DVI_DTOP_DUAL_P1_1D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3B)
4161 #define REG_DVI_DTOP_DUAL_P1_1E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3C)
4162 #define REG_DVI_DTOP_DUAL_P1_1E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3D)
4163 #define REG_DVI_DTOP_DUAL_P1_1F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3E)
4164 #define REG_DVI_DTOP_DUAL_P1_1F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x3F)
4165 #define REG_DVI_DTOP_DUAL_P1_20_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x40)
4166 #define REG_DVI_DTOP_DUAL_P1_20_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x41)
4167 #define REG_DVI_DTOP_DUAL_P1_21_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x42)
4168 #define REG_DVI_DTOP_DUAL_P1_21_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x43)
4169 #define REG_DVI_DTOP_DUAL_P1_22_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x44)
4170 #define REG_DVI_DTOP_DUAL_P1_22_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x45)
4171 #define REG_DVI_DTOP_DUAL_P1_23_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x46)
4172 #define REG_DVI_DTOP_DUAL_P1_23_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x47)
4173 #define REG_DVI_DTOP_DUAL_P1_24_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x48)
4174 #define REG_DVI_DTOP_DUAL_P1_24_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x49)
4175 #define REG_DVI_DTOP_DUAL_P1_25_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4A)
4176 #define REG_DVI_DTOP_DUAL_P1_25_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4B)
4177 #define REG_DVI_DTOP_DUAL_P1_26_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4C)
4178 #define REG_DVI_DTOP_DUAL_P1_26_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4D)
4179 #define REG_DVI_DTOP_DUAL_P1_27_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4E)
4180 #define REG_DVI_DTOP_DUAL_P1_27_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x4F)
4181 #define REG_DVI_DTOP_DUAL_P1_28_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x50)
4182 #define REG_DVI_DTOP_DUAL_P1_28_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x51)
4183 #define REG_DVI_DTOP_DUAL_P1_29_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x52)
4184 #define REG_DVI_DTOP_DUAL_P1_29_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x53)
4185 #define REG_DVI_DTOP_DUAL_P1_2A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x54)
4186 #define REG_DVI_DTOP_DUAL_P1_2A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x55)
4187 #define REG_DVI_DTOP_DUAL_P1_2B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x56)
4188 #define REG_DVI_DTOP_DUAL_P1_2B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x57)
4189 #define REG_DVI_DTOP_DUAL_P1_2C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x58)
4190 #define REG_DVI_DTOP_DUAL_P1_2C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x59)
4191 #define REG_DVI_DTOP_DUAL_P1_2D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5A)
4192 #define REG_DVI_DTOP_DUAL_P1_2D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5B)
4193 #define REG_DVI_DTOP_DUAL_P1_2E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5C)
4194 #define REG_DVI_DTOP_DUAL_P1_2E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5D)
4195 #define REG_DVI_DTOP_DUAL_P1_2F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5E)
4196 #define REG_DVI_DTOP_DUAL_P1_2F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x5F)
4197 #define REG_DVI_DTOP_DUAL_P1_30_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x60)
4198 #define REG_DVI_DTOP_DUAL_P1_30_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x61)
4199 #define REG_DVI_DTOP_DUAL_P1_31_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x62)
4200 #define REG_DVI_DTOP_DUAL_P1_31_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x63)
4201 #define REG_DVI_DTOP_DUAL_P1_32_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x64)
4202 #define REG_DVI_DTOP_DUAL_P1_32_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x65)
4203 #define REG_DVI_DTOP_DUAL_P1_33_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x66)
4204 #define REG_DVI_DTOP_DUAL_P1_33_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x67)
4205 #define REG_DVI_DTOP_DUAL_P1_34_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x68)
4206 #define REG_DVI_DTOP_DUAL_P1_34_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x69)
4207 #define REG_DVI_DTOP_DUAL_P1_35_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6A)
4208 #define REG_DVI_DTOP_DUAL_P1_35_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6B)
4209 #define REG_DVI_DTOP_DUAL_P1_36_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6C)
4210 #define REG_DVI_DTOP_DUAL_P1_36_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6D)
4211 #define REG_DVI_DTOP_DUAL_P1_37_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6E)
4212 #define REG_DVI_DTOP_DUAL_P1_37_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x6F)
4213 #define REG_DVI_DTOP_DUAL_P1_38_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x70)
4214 #define REG_DVI_DTOP_DUAL_P1_38_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x71)
4215 #define REG_DVI_DTOP_DUAL_P1_39_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x72)
4216 #define REG_DVI_DTOP_DUAL_P1_39_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x73)
4217 #define REG_DVI_DTOP_DUAL_P1_3A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x74)
4218 #define REG_DVI_DTOP_DUAL_P1_3A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x75)
4219 #define REG_DVI_DTOP_DUAL_P1_3B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x76)
4220 #define REG_DVI_DTOP_DUAL_P1_3B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x77)
4221 #define REG_DVI_DTOP_DUAL_P1_3C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x78)
4222 #define REG_DVI_DTOP_DUAL_P1_3C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x79)
4223 #define REG_DVI_DTOP_DUAL_P1_3D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7A)
4224 #define REG_DVI_DTOP_DUAL_P1_3D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7B)
4225 #define REG_DVI_DTOP_DUAL_P1_3E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7C)
4226 #define REG_DVI_DTOP_DUAL_P1_3E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7D)
4227 #define REG_DVI_DTOP_DUAL_P1_3F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7E)
4228 #define REG_DVI_DTOP_DUAL_P1_3F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x7F)
4229 #define REG_DVI_DTOP_DUAL_P1_40_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x80)
4230 #define REG_DVI_DTOP_DUAL_P1_40_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x81)
4231 #define REG_DVI_DTOP_DUAL_P1_41_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x82)
4232 #define REG_DVI_DTOP_DUAL_P1_41_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x83)
4233 #define REG_DVI_DTOP_DUAL_P1_42_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x84)
4234 #define REG_DVI_DTOP_DUAL_P1_42_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x85)
4235 #define REG_DVI_DTOP_DUAL_P1_43_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x86)
4236 #define REG_DVI_DTOP_DUAL_P1_43_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x87)
4237 #define REG_DVI_DTOP_DUAL_P1_44_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x88)
4238 #define REG_DVI_DTOP_DUAL_P1_44_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x89)
4239 #define REG_DVI_DTOP_DUAL_P1_45_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8A)
4240 #define REG_DVI_DTOP_DUAL_P1_45_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8B)
4241 #define REG_DVI_DTOP_DUAL_P1_46_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8C)
4242 #define REG_DVI_DTOP_DUAL_P1_46_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8D)
4243 #define REG_DVI_DTOP_DUAL_P1_47_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8E)
4244 #define REG_DVI_DTOP_DUAL_P1_47_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x8F)
4245 #define REG_DVI_DTOP_DUAL_P1_48_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x90)
4246 #define REG_DVI_DTOP_DUAL_P1_48_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x91)
4247 #define REG_DVI_DTOP_DUAL_P1_49_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x92)
4248 #define REG_DVI_DTOP_DUAL_P1_49_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x93)
4249 #define REG_DVI_DTOP_DUAL_P1_4A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x94)
4250 #define REG_DVI_DTOP_DUAL_P1_4A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x95)
4251 #define REG_DVI_DTOP_DUAL_P1_4B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x96)
4252 #define REG_DVI_DTOP_DUAL_P1_4B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x97)
4253 #define REG_DVI_DTOP_DUAL_P1_4C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x98)
4254 #define REG_DVI_DTOP_DUAL_P1_4C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x99)
4255 #define REG_DVI_DTOP_DUAL_P1_4D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9A)
4256 #define REG_DVI_DTOP_DUAL_P1_4D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9B)
4257 #define REG_DVI_DTOP_DUAL_P1_4E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9C)
4258 #define REG_DVI_DTOP_DUAL_P1_4E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9D)
4259 #define REG_DVI_DTOP_DUAL_P1_4F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9E)
4260 #define REG_DVI_DTOP_DUAL_P1_4F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0x9F)
4261 #define REG_DVI_DTOP_DUAL_P1_50_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA0)
4262 #define REG_DVI_DTOP_DUAL_P1_50_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA1)
4263 #define REG_DVI_DTOP_DUAL_P1_51_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA2)
4264 #define REG_DVI_DTOP_DUAL_P1_51_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA3)
4265 #define REG_DVI_DTOP_DUAL_P1_52_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA4)
4266 #define REG_DVI_DTOP_DUAL_P1_52_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA5)
4267 #define REG_DVI_DTOP_DUAL_P1_53_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA6)
4268 #define REG_DVI_DTOP_DUAL_P1_53_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA7)
4269 #define REG_DVI_DTOP_DUAL_P1_54_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA8)
4270 #define REG_DVI_DTOP_DUAL_P1_54_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xA9)
4271 #define REG_DVI_DTOP_DUAL_P1_55_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAA)
4272 #define REG_DVI_DTOP_DUAL_P1_55_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAB)
4273 #define REG_DVI_DTOP_DUAL_P1_56_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAC)
4274 #define REG_DVI_DTOP_DUAL_P1_56_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAD)
4275 #define REG_DVI_DTOP_DUAL_P1_57_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAE)
4276 #define REG_DVI_DTOP_DUAL_P1_57_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xAF)
4277 #define REG_DVI_DTOP_DUAL_P1_58_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB0)
4278 #define REG_DVI_DTOP_DUAL_P1_58_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB1)
4279 #define REG_DVI_DTOP_DUAL_P1_59_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB2)
4280 #define REG_DVI_DTOP_DUAL_P1_59_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB3)
4281 #define REG_DVI_DTOP_DUAL_P1_5A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB4)
4282 #define REG_DVI_DTOP_DUAL_P1_5A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB5)
4283 #define REG_DVI_DTOP_DUAL_P1_5B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB6)
4284 #define REG_DVI_DTOP_DUAL_P1_5B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB7)
4285 #define REG_DVI_DTOP_DUAL_P1_5C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB8)
4286 #define REG_DVI_DTOP_DUAL_P1_5C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xB9)
4287 #define REG_DVI_DTOP_DUAL_P1_5D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBA)
4288 #define REG_DVI_DTOP_DUAL_P1_5D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBB)
4289 #define REG_DVI_DTOP_DUAL_P1_5E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBC)
4290 #define REG_DVI_DTOP_DUAL_P1_5E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBD)
4291 #define REG_DVI_DTOP_DUAL_P1_5F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBE)
4292 #define REG_DVI_DTOP_DUAL_P1_5F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xBF)
4293 #define REG_DVI_DTOP_DUAL_P1_60_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC0)
4294 #define REG_DVI_DTOP_DUAL_P1_60_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC1)
4295 #define REG_DVI_DTOP_DUAL_P1_61_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC2)
4296 #define REG_DVI_DTOP_DUAL_P1_61_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC3)
4297 #define REG_DVI_DTOP_DUAL_P1_62_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC4)
4298 #define REG_DVI_DTOP_DUAL_P1_62_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC5)
4299 #define REG_DVI_DTOP_DUAL_P1_63_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC6)
4300 #define REG_DVI_DTOP_DUAL_P1_63_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC7)
4301 #define REG_DVI_DTOP_DUAL_P1_64_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC8)
4302 #define REG_DVI_DTOP_DUAL_P1_64_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xC9)
4303 #define REG_DVI_DTOP_DUAL_P1_65_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCA)
4304 #define REG_DVI_DTOP_DUAL_P1_65_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCB)
4305 #define REG_DVI_DTOP_DUAL_P1_66_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCC)
4306 #define REG_DVI_DTOP_DUAL_P1_66_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCD)
4307 #define REG_DVI_DTOP_DUAL_P1_67_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCE)
4308 #define REG_DVI_DTOP_DUAL_P1_67_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xCF)
4309 #define REG_DVI_DTOP_DUAL_P1_68_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD0)
4310 #define REG_DVI_DTOP_DUAL_P1_68_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD1)
4311 #define REG_DVI_DTOP_DUAL_P1_69_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD2)
4312 #define REG_DVI_DTOP_DUAL_P1_69_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD3)
4313 #define REG_DVI_DTOP_DUAL_P1_6A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD4)
4314 #define REG_DVI_DTOP_DUAL_P1_6A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD5)
4315 #define REG_DVI_DTOP_DUAL_P1_6B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD6)
4316 #define REG_DVI_DTOP_DUAL_P1_6B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD7)
4317 #define REG_DVI_DTOP_DUAL_P1_6C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD8)
4318 #define REG_DVI_DTOP_DUAL_P1_6C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xD9)
4319 #define REG_DVI_DTOP_DUAL_P1_6D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDA)
4320 #define REG_DVI_DTOP_DUAL_P1_6D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDB)
4321 #define REG_DVI_DTOP_DUAL_P1_6E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDC)
4322 #define REG_DVI_DTOP_DUAL_P1_6E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDD)
4323 #define REG_DVI_DTOP_DUAL_P1_6F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDE)
4324 #define REG_DVI_DTOP_DUAL_P1_6F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xDF)
4325 #define REG_DVI_DTOP_DUAL_P1_70_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE0)
4326 #define REG_DVI_DTOP_DUAL_P1_70_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE1)
4327 #define REG_DVI_DTOP_DUAL_P1_71_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE2)
4328 #define REG_DVI_DTOP_DUAL_P1_71_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE3)
4329 #define REG_DVI_DTOP_DUAL_P1_72_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE4)
4330 #define REG_DVI_DTOP_DUAL_P1_72_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE5)
4331 #define REG_DVI_DTOP_DUAL_P1_73_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE6)
4332 #define REG_DVI_DTOP_DUAL_P1_73_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE7)
4333 #define REG_DVI_DTOP_DUAL_P1_74_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE8)
4334 #define REG_DVI_DTOP_DUAL_P1_74_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xE9)
4335 #define REG_DVI_DTOP_DUAL_P1_75_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEA)
4336 #define REG_DVI_DTOP_DUAL_P1_75_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEB)
4337 #define REG_DVI_DTOP_DUAL_P1_76_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEC)
4338 #define REG_DVI_DTOP_DUAL_P1_76_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xED)
4339 #define REG_DVI_DTOP_DUAL_P1_77_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEE)
4340 #define REG_DVI_DTOP_DUAL_P1_77_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xEF)
4341 #define REG_DVI_DTOP_DUAL_P1_78_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF0)
4342 #define REG_DVI_DTOP_DUAL_P1_78_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF1)
4343 #define REG_DVI_DTOP_DUAL_P1_79_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF2)
4344 #define REG_DVI_DTOP_DUAL_P1_79_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF3)
4345 #define REG_DVI_DTOP_DUAL_P1_7A_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF4)
4346 #define REG_DVI_DTOP_DUAL_P1_7A_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF5)
4347 #define REG_DVI_DTOP_DUAL_P1_7B_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF6)
4348 #define REG_DVI_DTOP_DUAL_P1_7B_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF7)
4349 #define REG_DVI_DTOP_DUAL_P1_7C_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF8)
4350 #define REG_DVI_DTOP_DUAL_P1_7C_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xF9)
4351 #define REG_DVI_DTOP_DUAL_P1_7D_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFA)
4352 #define REG_DVI_DTOP_DUAL_P1_7D_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFB)
4353 #define REG_DVI_DTOP_DUAL_P1_7E_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFC)
4354 #define REG_DVI_DTOP_DUAL_P1_7E_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFD)
4355 #define REG_DVI_DTOP_DUAL_P1_7F_L       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFE)
4356 #define REG_DVI_DTOP_DUAL_P1_7F_H       (REG_DVI_DTOP_DUAL_P1_BASE + 0xFF)
4357 
4358 // DVI_RSV_DUAL_P1
4359 #define REG_DVI_RSV_DUAL_P1_00_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x00)
4360 #define REG_DVI_RSV_DUAL_P1_00_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x01)
4361 #define REG_DVI_RSV_DUAL_P1_01_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x02)
4362 #define REG_DVI_RSV_DUAL_P1_01_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x03)
4363 #define REG_DVI_RSV_DUAL_P1_02_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x04)
4364 #define REG_DVI_RSV_DUAL_P1_02_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x05)
4365 #define REG_DVI_RSV_DUAL_P1_03_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x06)
4366 #define REG_DVI_RSV_DUAL_P1_03_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x07)
4367 #define REG_DVI_RSV_DUAL_P1_04_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x08)
4368 #define REG_DVI_RSV_DUAL_P1_04_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x09)
4369 #define REG_DVI_RSV_DUAL_P1_05_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x0A)
4370 #define REG_DVI_RSV_DUAL_P1_05_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x0B)
4371 #define REG_DVI_RSV_DUAL_P1_06_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x0C)
4372 #define REG_DVI_RSV_DUAL_P1_06_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x0D)
4373 #define REG_DVI_RSV_DUAL_P1_07_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x0E)
4374 #define REG_DVI_RSV_DUAL_P1_07_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x0F)
4375 #define REG_DVI_RSV_DUAL_P1_08_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x10)
4376 #define REG_DVI_RSV_DUAL_P1_08_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x11)
4377 #define REG_DVI_RSV_DUAL_P1_09_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x12)
4378 #define REG_DVI_RSV_DUAL_P1_09_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x13)
4379 #define REG_DVI_RSV_DUAL_P1_0A_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x14)
4380 #define REG_DVI_RSV_DUAL_P1_0A_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x15)
4381 #define REG_DVI_RSV_DUAL_P1_0B_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x16)
4382 #define REG_DVI_RSV_DUAL_P1_0B_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x17)
4383 #define REG_DVI_RSV_DUAL_P1_0C_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x18)
4384 #define REG_DVI_RSV_DUAL_P1_0C_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x19)
4385 #define REG_DVI_RSV_DUAL_P1_0D_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x1A)
4386 #define REG_DVI_RSV_DUAL_P1_0D_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x1B)
4387 #define REG_DVI_RSV_DUAL_P1_0E_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x1C)
4388 #define REG_DVI_RSV_DUAL_P1_0E_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x1D)
4389 #define REG_DVI_RSV_DUAL_P1_0F_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x1E)
4390 #define REG_DVI_RSV_DUAL_P1_0F_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x1F)
4391 #define REG_DVI_RSV_DUAL_P1_10_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x20)
4392 #define REG_DVI_RSV_DUAL_P1_10_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x21)
4393 #define REG_DVI_RSV_DUAL_P1_11_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x22)
4394 #define REG_DVI_RSV_DUAL_P1_11_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x23)
4395 #define REG_DVI_RSV_DUAL_P1_12_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x24)
4396 #define REG_DVI_RSV_DUAL_P1_12_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x25)
4397 #define REG_DVI_RSV_DUAL_P1_13_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x26)
4398 #define REG_DVI_RSV_DUAL_P1_13_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x27)
4399 #define REG_DVI_RSV_DUAL_P1_14_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x28)
4400 #define REG_DVI_RSV_DUAL_P1_14_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x29)
4401 #define REG_DVI_RSV_DUAL_P1_15_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x2A)
4402 #define REG_DVI_RSV_DUAL_P1_15_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x2B)
4403 #define REG_DVI_RSV_DUAL_P1_16_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x2C)
4404 #define REG_DVI_RSV_DUAL_P1_16_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x2D)
4405 #define REG_DVI_RSV_DUAL_P1_17_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x2E)
4406 #define REG_DVI_RSV_DUAL_P1_17_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x2F)
4407 #define REG_DVI_RSV_DUAL_P1_18_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x30)
4408 #define REG_DVI_RSV_DUAL_P1_18_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x31)
4409 #define REG_DVI_RSV_DUAL_P1_19_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x32)
4410 #define REG_DVI_RSV_DUAL_P1_19_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x33)
4411 #define REG_DVI_RSV_DUAL_P1_1A_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x34)
4412 #define REG_DVI_RSV_DUAL_P1_1A_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x35)
4413 #define REG_DVI_RSV_DUAL_P1_1B_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x36)
4414 #define REG_DVI_RSV_DUAL_P1_1B_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x37)
4415 #define REG_DVI_RSV_DUAL_P1_1C_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x38)
4416 #define REG_DVI_RSV_DUAL_P1_1C_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x39)
4417 #define REG_DVI_RSV_DUAL_P1_1D_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x3A)
4418 #define REG_DVI_RSV_DUAL_P1_1D_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x3B)
4419 #define REG_DVI_RSV_DUAL_P1_1E_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x3C)
4420 #define REG_DVI_RSV_DUAL_P1_1E_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x3D)
4421 #define REG_DVI_RSV_DUAL_P1_1F_L       (REG_DVI_RSV_DUAL_P1_BASE + 0x3E)
4422 #define REG_DVI_RSV_DUAL_P1_1F_H       (REG_DVI_RSV_DUAL_P1_BASE + 0x3F)
4423 
4424 // HDCP_DUAL_P1
4425 #define REG_HDCP_DUAL_P1_00_L       (REG_HDCP_DUAL_P1_BASE + 0x00)
4426 #define REG_HDCP_DUAL_P1_00_H       (REG_HDCP_DUAL_P1_BASE + 0x01)
4427 #define REG_HDCP_DUAL_P1_01_L       (REG_HDCP_DUAL_P1_BASE + 0x02)
4428 #define REG_HDCP_DUAL_P1_01_H       (REG_HDCP_DUAL_P1_BASE + 0x03)
4429 #define REG_HDCP_DUAL_P1_02_L       (REG_HDCP_DUAL_P1_BASE + 0x04)
4430 #define REG_HDCP_DUAL_P1_02_H       (REG_HDCP_DUAL_P1_BASE + 0x05)
4431 #define REG_HDCP_DUAL_P1_03_L       (REG_HDCP_DUAL_P1_BASE + 0x06)
4432 #define REG_HDCP_DUAL_P1_03_H       (REG_HDCP_DUAL_P1_BASE + 0x07)
4433 #define REG_HDCP_DUAL_P1_04_L       (REG_HDCP_DUAL_P1_BASE + 0x08)
4434 #define REG_HDCP_DUAL_P1_04_H       (REG_HDCP_DUAL_P1_BASE + 0x09)
4435 #define REG_HDCP_DUAL_P1_05_L       (REG_HDCP_DUAL_P1_BASE + 0x0A)
4436 #define REG_HDCP_DUAL_P1_05_H       (REG_HDCP_DUAL_P1_BASE + 0x0B)
4437 #define REG_HDCP_DUAL_P1_06_L       (REG_HDCP_DUAL_P1_BASE + 0x0C)
4438 #define REG_HDCP_DUAL_P1_06_H       (REG_HDCP_DUAL_P1_BASE + 0x0D)
4439 #define REG_HDCP_DUAL_P1_07_L       (REG_HDCP_DUAL_P1_BASE + 0x0E)
4440 #define REG_HDCP_DUAL_P1_07_H       (REG_HDCP_DUAL_P1_BASE + 0x0F)
4441 #define REG_HDCP_DUAL_P1_08_L       (REG_HDCP_DUAL_P1_BASE + 0x10)
4442 #define REG_HDCP_DUAL_P1_08_H       (REG_HDCP_DUAL_P1_BASE + 0x11)
4443 #define REG_HDCP_DUAL_P1_09_L       (REG_HDCP_DUAL_P1_BASE + 0x12)
4444 #define REG_HDCP_DUAL_P1_09_H       (REG_HDCP_DUAL_P1_BASE + 0x13)
4445 #define REG_HDCP_DUAL_P1_0A_L       (REG_HDCP_DUAL_P1_BASE + 0x14)
4446 #define REG_HDCP_DUAL_P1_0A_H       (REG_HDCP_DUAL_P1_BASE + 0x15)
4447 #define REG_HDCP_DUAL_P1_0B_L       (REG_HDCP_DUAL_P1_BASE + 0x16)
4448 #define REG_HDCP_DUAL_P1_0B_H       (REG_HDCP_DUAL_P1_BASE + 0x17)
4449 #define REG_HDCP_DUAL_P1_0C_L       (REG_HDCP_DUAL_P1_BASE + 0x18)
4450 #define REG_HDCP_DUAL_P1_0C_H       (REG_HDCP_DUAL_P1_BASE + 0x19)
4451 #define REG_HDCP_DUAL_P1_0D_L       (REG_HDCP_DUAL_P1_BASE + 0x1A)
4452 #define REG_HDCP_DUAL_P1_0D_H       (REG_HDCP_DUAL_P1_BASE + 0x1B)
4453 #define REG_HDCP_DUAL_P1_0E_L       (REG_HDCP_DUAL_P1_BASE + 0x1C)
4454 #define REG_HDCP_DUAL_P1_0E_H       (REG_HDCP_DUAL_P1_BASE + 0x1D)
4455 #define REG_HDCP_DUAL_P1_0F_L       (REG_HDCP_DUAL_P1_BASE + 0x1E)
4456 #define REG_HDCP_DUAL_P1_0F_H       (REG_HDCP_DUAL_P1_BASE + 0x1F)
4457 #define REG_HDCP_DUAL_P1_10_L       (REG_HDCP_DUAL_P1_BASE + 0x20)
4458 #define REG_HDCP_DUAL_P1_10_H       (REG_HDCP_DUAL_P1_BASE + 0x21)
4459 #define REG_HDCP_DUAL_P1_11_L       (REG_HDCP_DUAL_P1_BASE + 0x22)
4460 #define REG_HDCP_DUAL_P1_11_H       (REG_HDCP_DUAL_P1_BASE + 0x23)
4461 #define REG_HDCP_DUAL_P1_12_L       (REG_HDCP_DUAL_P1_BASE + 0x24)
4462 #define REG_HDCP_DUAL_P1_12_H       (REG_HDCP_DUAL_P1_BASE + 0x25)
4463 #define REG_HDCP_DUAL_P1_13_L       (REG_HDCP_DUAL_P1_BASE + 0x26)
4464 #define REG_HDCP_DUAL_P1_13_H       (REG_HDCP_DUAL_P1_BASE + 0x27)
4465 #define REG_HDCP_DUAL_P1_14_L       (REG_HDCP_DUAL_P1_BASE + 0x28)
4466 #define REG_HDCP_DUAL_P1_14_H       (REG_HDCP_DUAL_P1_BASE + 0x29)
4467 #define REG_HDCP_DUAL_P1_15_L       (REG_HDCP_DUAL_P1_BASE + 0x2A)
4468 #define REG_HDCP_DUAL_P1_15_H       (REG_HDCP_DUAL_P1_BASE + 0x2B)
4469 #define REG_HDCP_DUAL_P1_16_L       (REG_HDCP_DUAL_P1_BASE + 0x2C)
4470 #define REG_HDCP_DUAL_P1_16_H       (REG_HDCP_DUAL_P1_BASE + 0x2D)
4471 #define REG_HDCP_DUAL_P1_17_L       (REG_HDCP_DUAL_P1_BASE + 0x2E)
4472 #define REG_HDCP_DUAL_P1_17_H       (REG_HDCP_DUAL_P1_BASE + 0x2F)
4473 #define REG_HDCP_DUAL_P1_18_L       (REG_HDCP_DUAL_P1_BASE + 0x30)
4474 #define REG_HDCP_DUAL_P1_18_H       (REG_HDCP_DUAL_P1_BASE + 0x31)
4475 #define REG_HDCP_DUAL_P1_19_L       (REG_HDCP_DUAL_P1_BASE + 0x32)
4476 #define REG_HDCP_DUAL_P1_19_H       (REG_HDCP_DUAL_P1_BASE + 0x33)
4477 #define REG_HDCP_DUAL_P1_1A_L       (REG_HDCP_DUAL_P1_BASE + 0x34)
4478 #define REG_HDCP_DUAL_P1_1A_H       (REG_HDCP_DUAL_P1_BASE + 0x35)
4479 #define REG_HDCP_DUAL_P1_1B_L       (REG_HDCP_DUAL_P1_BASE + 0x36)
4480 #define REG_HDCP_DUAL_P1_1B_H       (REG_HDCP_DUAL_P1_BASE + 0x37)
4481 #define REG_HDCP_DUAL_P1_1C_L       (REG_HDCP_DUAL_P1_BASE + 0x38)
4482 #define REG_HDCP_DUAL_P1_1C_H       (REG_HDCP_DUAL_P1_BASE + 0x39)
4483 #define REG_HDCP_DUAL_P1_1D_L       (REG_HDCP_DUAL_P1_BASE + 0x3A)
4484 #define REG_HDCP_DUAL_P1_1D_H       (REG_HDCP_DUAL_P1_BASE + 0x3B)
4485 #define REG_HDCP_DUAL_P1_1E_L       (REG_HDCP_DUAL_P1_BASE + 0x3C)
4486 #define REG_HDCP_DUAL_P1_1E_H       (REG_HDCP_DUAL_P1_BASE + 0x3D)
4487 #define REG_HDCP_DUAL_P1_1F_L       (REG_HDCP_DUAL_P1_BASE + 0x3E)
4488 #define REG_HDCP_DUAL_P1_1F_H       (REG_HDCP_DUAL_P1_BASE + 0x3F)
4489 #define REG_HDCP_DUAL_P1_20_L       (REG_HDCP_DUAL_P1_BASE + 0x40)
4490 #define REG_HDCP_DUAL_P1_20_H       (REG_HDCP_DUAL_P1_BASE + 0x41)
4491 #define REG_HDCP_DUAL_P1_21_L       (REG_HDCP_DUAL_P1_BASE + 0x42)
4492 #define REG_HDCP_DUAL_P1_21_H       (REG_HDCP_DUAL_P1_BASE + 0x43)
4493 #define REG_HDCP_DUAL_P1_22_L       (REG_HDCP_DUAL_P1_BASE + 0x44)
4494 #define REG_HDCP_DUAL_P1_22_H       (REG_HDCP_DUAL_P1_BASE + 0x45)
4495 #define REG_HDCP_DUAL_P1_23_L       (REG_HDCP_DUAL_P1_BASE + 0x46)
4496 #define REG_HDCP_DUAL_P1_23_H       (REG_HDCP_DUAL_P1_BASE + 0x47)
4497 #define REG_HDCP_DUAL_P1_24_L       (REG_HDCP_DUAL_P1_BASE + 0x48)
4498 #define REG_HDCP_DUAL_P1_24_H       (REG_HDCP_DUAL_P1_BASE + 0x49)
4499 #define REG_HDCP_DUAL_P1_25_L       (REG_HDCP_DUAL_P1_BASE + 0x4A)
4500 #define REG_HDCP_DUAL_P1_25_H       (REG_HDCP_DUAL_P1_BASE + 0x4B)
4501 #define REG_HDCP_DUAL_P1_26_L       (REG_HDCP_DUAL_P1_BASE + 0x4C)
4502 #define REG_HDCP_DUAL_P1_26_H       (REG_HDCP_DUAL_P1_BASE + 0x4D)
4503 #define REG_HDCP_DUAL_P1_27_L       (REG_HDCP_DUAL_P1_BASE + 0x4E)
4504 #define REG_HDCP_DUAL_P1_27_H       (REG_HDCP_DUAL_P1_BASE + 0x4F)
4505 #define REG_HDCP_DUAL_P1_28_L       (REG_HDCP_DUAL_P1_BASE + 0x50)
4506 #define REG_HDCP_DUAL_P1_28_H       (REG_HDCP_DUAL_P1_BASE + 0x51)
4507 #define REG_HDCP_DUAL_P1_29_L       (REG_HDCP_DUAL_P1_BASE + 0x52)
4508 #define REG_HDCP_DUAL_P1_29_H       (REG_HDCP_DUAL_P1_BASE + 0x53)
4509 #define REG_HDCP_DUAL_P1_2A_L       (REG_HDCP_DUAL_P1_BASE + 0x54)
4510 #define REG_HDCP_DUAL_P1_2A_H       (REG_HDCP_DUAL_P1_BASE + 0x55)
4511 #define REG_HDCP_DUAL_P1_2B_L       (REG_HDCP_DUAL_P1_BASE + 0x56)
4512 #define REG_HDCP_DUAL_P1_2B_H       (REG_HDCP_DUAL_P1_BASE + 0x57)
4513 #define REG_HDCP_DUAL_P1_2C_L       (REG_HDCP_DUAL_P1_BASE + 0x58)
4514 #define REG_HDCP_DUAL_P1_2C_H       (REG_HDCP_DUAL_P1_BASE + 0x59)
4515 #define REG_HDCP_DUAL_P1_2D_L       (REG_HDCP_DUAL_P1_BASE + 0x5A)
4516 #define REG_HDCP_DUAL_P1_2D_H       (REG_HDCP_DUAL_P1_BASE + 0x5B)
4517 #define REG_HDCP_DUAL_P1_2E_L       (REG_HDCP_DUAL_P1_BASE + 0x5C)
4518 #define REG_HDCP_DUAL_P1_2E_H       (REG_HDCP_DUAL_P1_BASE + 0x5D)
4519 #define REG_HDCP_DUAL_P1_2F_L       (REG_HDCP_DUAL_P1_BASE + 0x5E)
4520 #define REG_HDCP_DUAL_P1_2F_H       (REG_HDCP_DUAL_P1_BASE + 0x5F)
4521 #define REG_HDCP_DUAL_P1_30_L       (REG_HDCP_DUAL_P1_BASE + 0x60)
4522 #define REG_HDCP_DUAL_P1_30_H       (REG_HDCP_DUAL_P1_BASE + 0x61)
4523 #define REG_HDCP_DUAL_P1_31_L       (REG_HDCP_DUAL_P1_BASE + 0x62)
4524 #define REG_HDCP_DUAL_P1_31_H       (REG_HDCP_DUAL_P1_BASE + 0x63)
4525 #define REG_HDCP_DUAL_P1_32_L       (REG_HDCP_DUAL_P1_BASE + 0x64)
4526 #define REG_HDCP_DUAL_P1_32_H       (REG_HDCP_DUAL_P1_BASE + 0x65)
4527 #define REG_HDCP_DUAL_P1_33_L       (REG_HDCP_DUAL_P1_BASE + 0x66)
4528 #define REG_HDCP_DUAL_P1_33_H       (REG_HDCP_DUAL_P1_BASE + 0x67)
4529 #define REG_HDCP_DUAL_P1_34_L       (REG_HDCP_DUAL_P1_BASE + 0x68)
4530 #define REG_HDCP_DUAL_P1_34_H       (REG_HDCP_DUAL_P1_BASE + 0x69)
4531 #define REG_HDCP_DUAL_P1_35_L       (REG_HDCP_DUAL_P1_BASE + 0x6A)
4532 #define REG_HDCP_DUAL_P1_35_H       (REG_HDCP_DUAL_P1_BASE + 0x6B)
4533 #define REG_HDCP_DUAL_P1_36_L       (REG_HDCP_DUAL_P1_BASE + 0x6C)
4534 #define REG_HDCP_DUAL_P1_36_H       (REG_HDCP_DUAL_P1_BASE + 0x6D)
4535 #define REG_HDCP_DUAL_P1_37_L       (REG_HDCP_DUAL_P1_BASE + 0x6E)
4536 #define REG_HDCP_DUAL_P1_37_H       (REG_HDCP_DUAL_P1_BASE + 0x6F)
4537 #define REG_HDCP_DUAL_P1_38_L       (REG_HDCP_DUAL_P1_BASE + 0x70)
4538 #define REG_HDCP_DUAL_P1_38_H       (REG_HDCP_DUAL_P1_BASE + 0x71)
4539 #define REG_HDCP_DUAL_P1_39_L       (REG_HDCP_DUAL_P1_BASE + 0x72)
4540 #define REG_HDCP_DUAL_P1_39_H       (REG_HDCP_DUAL_P1_BASE + 0x73)
4541 #define REG_HDCP_DUAL_P1_3A_L       (REG_HDCP_DUAL_P1_BASE + 0x74)
4542 #define REG_HDCP_DUAL_P1_3A_H       (REG_HDCP_DUAL_P1_BASE + 0x75)
4543 #define REG_HDCP_DUAL_P1_3B_L       (REG_HDCP_DUAL_P1_BASE + 0x76)
4544 #define REG_HDCP_DUAL_P1_3B_H       (REG_HDCP_DUAL_P1_BASE + 0x77)
4545 #define REG_HDCP_DUAL_P1_3C_L       (REG_HDCP_DUAL_P1_BASE + 0x78)
4546 #define REG_HDCP_DUAL_P1_3C_H       (REG_HDCP_DUAL_P1_BASE + 0x79)
4547 #define REG_HDCP_DUAL_P1_3D_L       (REG_HDCP_DUAL_P1_BASE + 0x7A)
4548 #define REG_HDCP_DUAL_P1_3D_H       (REG_HDCP_DUAL_P1_BASE + 0x7B)
4549 #define REG_HDCP_DUAL_P1_3E_L       (REG_HDCP_DUAL_P1_BASE + 0x7C)
4550 #define REG_HDCP_DUAL_P1_3E_H       (REG_HDCP_DUAL_P1_BASE + 0x7D)
4551 #define REG_HDCP_DUAL_P1_3F_L       (REG_HDCP_DUAL_P1_BASE + 0x7E)
4552 #define REG_HDCP_DUAL_P1_3F_H       (REG_HDCP_DUAL_P1_BASE + 0x7F)
4553 #define REG_HDCP_DUAL_P1_40_L       (REG_HDCP_DUAL_P1_BASE + 0x80)
4554 #define REG_HDCP_DUAL_P1_40_H       (REG_HDCP_DUAL_P1_BASE + 0x81)
4555 #define REG_HDCP_DUAL_P1_41_L       (REG_HDCP_DUAL_P1_BASE + 0x82)
4556 #define REG_HDCP_DUAL_P1_41_H       (REG_HDCP_DUAL_P1_BASE + 0x83)
4557 #define REG_HDCP_DUAL_P1_42_L       (REG_HDCP_DUAL_P1_BASE + 0x84)
4558 #define REG_HDCP_DUAL_P1_42_H       (REG_HDCP_DUAL_P1_BASE + 0x85)
4559 #define REG_HDCP_DUAL_P1_43_L       (REG_HDCP_DUAL_P1_BASE + 0x86)
4560 #define REG_HDCP_DUAL_P1_43_H       (REG_HDCP_DUAL_P1_BASE + 0x87)
4561 #define REG_HDCP_DUAL_P1_44_L       (REG_HDCP_DUAL_P1_BASE + 0x88)
4562 #define REG_HDCP_DUAL_P1_44_H       (REG_HDCP_DUAL_P1_BASE + 0x89)
4563 #define REG_HDCP_DUAL_P1_45_L       (REG_HDCP_DUAL_P1_BASE + 0x8A)
4564 #define REG_HDCP_DUAL_P1_45_H       (REG_HDCP_DUAL_P1_BASE + 0x8B)
4565 #define REG_HDCP_DUAL_P1_46_L       (REG_HDCP_DUAL_P1_BASE + 0x8C)
4566 #define REG_HDCP_DUAL_P1_46_H       (REG_HDCP_DUAL_P1_BASE + 0x8D)
4567 #define REG_HDCP_DUAL_P1_47_L       (REG_HDCP_DUAL_P1_BASE + 0x8E)
4568 #define REG_HDCP_DUAL_P1_47_H       (REG_HDCP_DUAL_P1_BASE + 0x8F)
4569 #define REG_HDCP_DUAL_P1_48_L       (REG_HDCP_DUAL_P1_BASE + 0x90)
4570 #define REG_HDCP_DUAL_P1_48_H       (REG_HDCP_DUAL_P1_BASE + 0x91)
4571 #define REG_HDCP_DUAL_P1_49_L       (REG_HDCP_DUAL_P1_BASE + 0x92)
4572 #define REG_HDCP_DUAL_P1_49_H       (REG_HDCP_DUAL_P1_BASE + 0x93)
4573 #define REG_HDCP_DUAL_P1_4A_L       (REG_HDCP_DUAL_P1_BASE + 0x94)
4574 #define REG_HDCP_DUAL_P1_4A_H       (REG_HDCP_DUAL_P1_BASE + 0x95)
4575 #define REG_HDCP_DUAL_P1_4B_L       (REG_HDCP_DUAL_P1_BASE + 0x96)
4576 #define REG_HDCP_DUAL_P1_4B_H       (REG_HDCP_DUAL_P1_BASE + 0x97)
4577 #define REG_HDCP_DUAL_P1_4C_L       (REG_HDCP_DUAL_P1_BASE + 0x98)
4578 #define REG_HDCP_DUAL_P1_4C_H       (REG_HDCP_DUAL_P1_BASE + 0x99)
4579 #define REG_HDCP_DUAL_P1_4D_L       (REG_HDCP_DUAL_P1_BASE + 0x9A)
4580 #define REG_HDCP_DUAL_P1_4D_H       (REG_HDCP_DUAL_P1_BASE + 0x9B)
4581 #define REG_HDCP_DUAL_P1_4E_L       (REG_HDCP_DUAL_P1_BASE + 0x9C)
4582 #define REG_HDCP_DUAL_P1_4E_H       (REG_HDCP_DUAL_P1_BASE + 0x9D)
4583 #define REG_HDCP_DUAL_P1_4F_L       (REG_HDCP_DUAL_P1_BASE + 0x9E)
4584 #define REG_HDCP_DUAL_P1_4F_H       (REG_HDCP_DUAL_P1_BASE + 0x9F)
4585 #define REG_HDCP_DUAL_P1_50_L       (REG_HDCP_DUAL_P1_BASE + 0xA0)
4586 #define REG_HDCP_DUAL_P1_50_H       (REG_HDCP_DUAL_P1_BASE + 0xA1)
4587 #define REG_HDCP_DUAL_P1_51_L       (REG_HDCP_DUAL_P1_BASE + 0xA2)
4588 #define REG_HDCP_DUAL_P1_51_H       (REG_HDCP_DUAL_P1_BASE + 0xA3)
4589 #define REG_HDCP_DUAL_P1_52_L       (REG_HDCP_DUAL_P1_BASE + 0xA4)
4590 #define REG_HDCP_DUAL_P1_52_H       (REG_HDCP_DUAL_P1_BASE + 0xA5)
4591 #define REG_HDCP_DUAL_P1_53_L       (REG_HDCP_DUAL_P1_BASE + 0xA6)
4592 #define REG_HDCP_DUAL_P1_53_H       (REG_HDCP_DUAL_P1_BASE + 0xA7)
4593 #define REG_HDCP_DUAL_P1_54_L       (REG_HDCP_DUAL_P1_BASE + 0xA8)
4594 #define REG_HDCP_DUAL_P1_54_H       (REG_HDCP_DUAL_P1_BASE + 0xA9)
4595 #define REG_HDCP_DUAL_P1_55_L       (REG_HDCP_DUAL_P1_BASE + 0xAA)
4596 #define REG_HDCP_DUAL_P1_55_H       (REG_HDCP_DUAL_P1_BASE + 0xAB)
4597 #define REG_HDCP_DUAL_P1_56_L       (REG_HDCP_DUAL_P1_BASE + 0xAC)
4598 #define REG_HDCP_DUAL_P1_56_H       (REG_HDCP_DUAL_P1_BASE + 0xAD)
4599 #define REG_HDCP_DUAL_P1_57_L       (REG_HDCP_DUAL_P1_BASE + 0xAE)
4600 #define REG_HDCP_DUAL_P1_57_H       (REG_HDCP_DUAL_P1_BASE + 0xAF)
4601 #define REG_HDCP_DUAL_P1_58_L       (REG_HDCP_DUAL_P1_BASE + 0xB0)
4602 #define REG_HDCP_DUAL_P1_58_H       (REG_HDCP_DUAL_P1_BASE + 0xB1)
4603 #define REG_HDCP_DUAL_P1_59_L       (REG_HDCP_DUAL_P1_BASE + 0xB2)
4604 #define REG_HDCP_DUAL_P1_59_H       (REG_HDCP_DUAL_P1_BASE + 0xB3)
4605 #define REG_HDCP_DUAL_P1_5A_L       (REG_HDCP_DUAL_P1_BASE + 0xB4)
4606 #define REG_HDCP_DUAL_P1_5A_H       (REG_HDCP_DUAL_P1_BASE + 0xB5)
4607 #define REG_HDCP_DUAL_P1_5B_L       (REG_HDCP_DUAL_P1_BASE + 0xB6)
4608 #define REG_HDCP_DUAL_P1_5B_H       (REG_HDCP_DUAL_P1_BASE + 0xB7)
4609 #define REG_HDCP_DUAL_P1_5C_L       (REG_HDCP_DUAL_P1_BASE + 0xB8)
4610 #define REG_HDCP_DUAL_P1_5C_H       (REG_HDCP_DUAL_P1_BASE + 0xB9)
4611 #define REG_HDCP_DUAL_P1_5D_L       (REG_HDCP_DUAL_P1_BASE + 0xBA)
4612 #define REG_HDCP_DUAL_P1_5D_H       (REG_HDCP_DUAL_P1_BASE + 0xBB)
4613 #define REG_HDCP_DUAL_P1_5E_L       (REG_HDCP_DUAL_P1_BASE + 0xBC)
4614 #define REG_HDCP_DUAL_P1_5E_H       (REG_HDCP_DUAL_P1_BASE + 0xBD)
4615 #define REG_HDCP_DUAL_P1_5F_L       (REG_HDCP_DUAL_P1_BASE + 0xBE)
4616 #define REG_HDCP_DUAL_P1_5F_H       (REG_HDCP_DUAL_P1_BASE + 0xBF)
4617 #define REG_HDCP_DUAL_P1_60_L       (REG_HDCP_DUAL_P1_BASE + 0xC0)
4618 #define REG_HDCP_DUAL_P1_60_H       (REG_HDCP_DUAL_P1_BASE + 0xC1)
4619 #define REG_HDCP_DUAL_P1_61_L       (REG_HDCP_DUAL_P1_BASE + 0xC2)
4620 #define REG_HDCP_DUAL_P1_61_H       (REG_HDCP_DUAL_P1_BASE + 0xC3)
4621 #define REG_HDCP_DUAL_P1_62_L       (REG_HDCP_DUAL_P1_BASE + 0xC4)
4622 #define REG_HDCP_DUAL_P1_62_H       (REG_HDCP_DUAL_P1_BASE + 0xC5)
4623 #define REG_HDCP_DUAL_P1_63_L       (REG_HDCP_DUAL_P1_BASE + 0xC6)
4624 #define REG_HDCP_DUAL_P1_63_H       (REG_HDCP_DUAL_P1_BASE + 0xC7)
4625 #define REG_HDCP_DUAL_P1_64_L       (REG_HDCP_DUAL_P1_BASE + 0xC8)
4626 #define REG_HDCP_DUAL_P1_64_H       (REG_HDCP_DUAL_P1_BASE + 0xC9)
4627 #define REG_HDCP_DUAL_P1_65_L       (REG_HDCP_DUAL_P1_BASE + 0xCA)
4628 #define REG_HDCP_DUAL_P1_65_H       (REG_HDCP_DUAL_P1_BASE + 0xCB)
4629 #define REG_HDCP_DUAL_P1_66_L       (REG_HDCP_DUAL_P1_BASE + 0xCC)
4630 #define REG_HDCP_DUAL_P1_66_H       (REG_HDCP_DUAL_P1_BASE + 0xCD)
4631 #define REG_HDCP_DUAL_P1_67_L       (REG_HDCP_DUAL_P1_BASE + 0xCE)
4632 #define REG_HDCP_DUAL_P1_67_H       (REG_HDCP_DUAL_P1_BASE + 0xCF)
4633 #define REG_HDCP_DUAL_P1_68_L       (REG_HDCP_DUAL_P1_BASE + 0xD0)
4634 #define REG_HDCP_DUAL_P1_68_H       (REG_HDCP_DUAL_P1_BASE + 0xD1)
4635 
4636 // DVI_DTOP_DUAL_P2
4637 #define REG_DVI_DTOP_DUAL_P2_00_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x00)
4638 #define REG_DVI_DTOP_DUAL_P2_00_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x01)
4639 #define REG_DVI_DTOP_DUAL_P2_01_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x02)
4640 #define REG_DVI_DTOP_DUAL_P2_01_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x03)
4641 #define REG_DVI_DTOP_DUAL_P2_02_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x04)
4642 #define REG_DVI_DTOP_DUAL_P2_02_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x05)
4643 #define REG_DVI_DTOP_DUAL_P2_03_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x06)
4644 #define REG_DVI_DTOP_DUAL_P2_03_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x07)
4645 #define REG_DVI_DTOP_DUAL_P2_04_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x08)
4646 #define REG_DVI_DTOP_DUAL_P2_04_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x09)
4647 #define REG_DVI_DTOP_DUAL_P2_05_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0A)
4648 #define REG_DVI_DTOP_DUAL_P2_05_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0B)
4649 #define REG_DVI_DTOP_DUAL_P2_06_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0C)
4650 #define REG_DVI_DTOP_DUAL_P2_06_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0D)
4651 #define REG_DVI_DTOP_DUAL_P2_07_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0E)
4652 #define REG_DVI_DTOP_DUAL_P2_07_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x0F)
4653 #define REG_DVI_DTOP_DUAL_P2_08_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x10)
4654 #define REG_DVI_DTOP_DUAL_P2_08_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x11)
4655 #define REG_DVI_DTOP_DUAL_P2_09_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x12)
4656 #define REG_DVI_DTOP_DUAL_P2_09_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x13)
4657 #define REG_DVI_DTOP_DUAL_P2_0A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x14)
4658 #define REG_DVI_DTOP_DUAL_P2_0A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x15)
4659 #define REG_DVI_DTOP_DUAL_P2_0B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x16)
4660 #define REG_DVI_DTOP_DUAL_P2_0B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x17)
4661 #define REG_DVI_DTOP_DUAL_P2_0C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x18)
4662 #define REG_DVI_DTOP_DUAL_P2_0C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x19)
4663 #define REG_DVI_DTOP_DUAL_P2_0D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1A)
4664 #define REG_DVI_DTOP_DUAL_P2_0D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1B)
4665 #define REG_DVI_DTOP_DUAL_P2_0E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1C)
4666 #define REG_DVI_DTOP_DUAL_P2_0E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1D)
4667 #define REG_DVI_DTOP_DUAL_P2_0F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1E)
4668 #define REG_DVI_DTOP_DUAL_P2_0F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x1F)
4669 #define REG_DVI_DTOP_DUAL_P2_10_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x20)
4670 #define REG_DVI_DTOP_DUAL_P2_10_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x21)
4671 #define REG_DVI_DTOP_DUAL_P2_11_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x22)
4672 #define REG_DVI_DTOP_DUAL_P2_11_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x23)
4673 #define REG_DVI_DTOP_DUAL_P2_12_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x24)
4674 #define REG_DVI_DTOP_DUAL_P2_12_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x25)
4675 #define REG_DVI_DTOP_DUAL_P2_13_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x26)
4676 #define REG_DVI_DTOP_DUAL_P2_13_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x27)
4677 #define REG_DVI_DTOP_DUAL_P2_14_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x28)
4678 #define REG_DVI_DTOP_DUAL_P2_14_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x29)
4679 #define REG_DVI_DTOP_DUAL_P2_15_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2A)
4680 #define REG_DVI_DTOP_DUAL_P2_15_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2B)
4681 #define REG_DVI_DTOP_DUAL_P2_16_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2C)
4682 #define REG_DVI_DTOP_DUAL_P2_16_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2D)
4683 #define REG_DVI_DTOP_DUAL_P2_17_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2E)
4684 #define REG_DVI_DTOP_DUAL_P2_17_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x2F)
4685 #define REG_DVI_DTOP_DUAL_P2_18_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x30)
4686 #define REG_DVI_DTOP_DUAL_P2_18_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x31)
4687 #define REG_DVI_DTOP_DUAL_P2_19_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x32)
4688 #define REG_DVI_DTOP_DUAL_P2_19_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x33)
4689 #define REG_DVI_DTOP_DUAL_P2_1A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x34)
4690 #define REG_DVI_DTOP_DUAL_P2_1A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x35)
4691 #define REG_DVI_DTOP_DUAL_P2_1B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x36)
4692 #define REG_DVI_DTOP_DUAL_P2_1B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x37)
4693 #define REG_DVI_DTOP_DUAL_P2_1C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x38)
4694 #define REG_DVI_DTOP_DUAL_P2_1C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x39)
4695 #define REG_DVI_DTOP_DUAL_P2_1D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3A)
4696 #define REG_DVI_DTOP_DUAL_P2_1D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3B)
4697 #define REG_DVI_DTOP_DUAL_P2_1E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3C)
4698 #define REG_DVI_DTOP_DUAL_P2_1E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3D)
4699 #define REG_DVI_DTOP_DUAL_P2_1F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3E)
4700 #define REG_DVI_DTOP_DUAL_P2_1F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x3F)
4701 #define REG_DVI_DTOP_DUAL_P2_20_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x40)
4702 #define REG_DVI_DTOP_DUAL_P2_20_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x41)
4703 #define REG_DVI_DTOP_DUAL_P2_21_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x42)
4704 #define REG_DVI_DTOP_DUAL_P2_21_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x43)
4705 #define REG_DVI_DTOP_DUAL_P2_22_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x44)
4706 #define REG_DVI_DTOP_DUAL_P2_22_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x45)
4707 #define REG_DVI_DTOP_DUAL_P2_23_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x46)
4708 #define REG_DVI_DTOP_DUAL_P2_23_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x47)
4709 #define REG_DVI_DTOP_DUAL_P2_24_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x48)
4710 #define REG_DVI_DTOP_DUAL_P2_24_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x49)
4711 #define REG_DVI_DTOP_DUAL_P2_25_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4A)
4712 #define REG_DVI_DTOP_DUAL_P2_25_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4B)
4713 #define REG_DVI_DTOP_DUAL_P2_26_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4C)
4714 #define REG_DVI_DTOP_DUAL_P2_26_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4D)
4715 #define REG_DVI_DTOP_DUAL_P2_27_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4E)
4716 #define REG_DVI_DTOP_DUAL_P2_27_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x4F)
4717 #define REG_DVI_DTOP_DUAL_P2_28_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x50)
4718 #define REG_DVI_DTOP_DUAL_P2_28_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x51)
4719 #define REG_DVI_DTOP_DUAL_P2_29_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x52)
4720 #define REG_DVI_DTOP_DUAL_P2_29_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x53)
4721 #define REG_DVI_DTOP_DUAL_P2_2A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x54)
4722 #define REG_DVI_DTOP_DUAL_P2_2A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x55)
4723 #define REG_DVI_DTOP_DUAL_P2_2B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x56)
4724 #define REG_DVI_DTOP_DUAL_P2_2B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x57)
4725 #define REG_DVI_DTOP_DUAL_P2_2C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x58)
4726 #define REG_DVI_DTOP_DUAL_P2_2C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x59)
4727 #define REG_DVI_DTOP_DUAL_P2_2D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5A)
4728 #define REG_DVI_DTOP_DUAL_P2_2D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5B)
4729 #define REG_DVI_DTOP_DUAL_P2_2E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5C)
4730 #define REG_DVI_DTOP_DUAL_P2_2E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5D)
4731 #define REG_DVI_DTOP_DUAL_P2_2F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5E)
4732 #define REG_DVI_DTOP_DUAL_P2_2F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x5F)
4733 #define REG_DVI_DTOP_DUAL_P2_30_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x60)
4734 #define REG_DVI_DTOP_DUAL_P2_30_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x61)
4735 #define REG_DVI_DTOP_DUAL_P2_31_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x62)
4736 #define REG_DVI_DTOP_DUAL_P2_31_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x63)
4737 #define REG_DVI_DTOP_DUAL_P2_32_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x64)
4738 #define REG_DVI_DTOP_DUAL_P2_32_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x65)
4739 #define REG_DVI_DTOP_DUAL_P2_33_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x66)
4740 #define REG_DVI_DTOP_DUAL_P2_33_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x67)
4741 #define REG_DVI_DTOP_DUAL_P2_34_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x68)
4742 #define REG_DVI_DTOP_DUAL_P2_34_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x69)
4743 #define REG_DVI_DTOP_DUAL_P2_35_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6A)
4744 #define REG_DVI_DTOP_DUAL_P2_35_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6B)
4745 #define REG_DVI_DTOP_DUAL_P2_36_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6C)
4746 #define REG_DVI_DTOP_DUAL_P2_36_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6D)
4747 #define REG_DVI_DTOP_DUAL_P2_37_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6E)
4748 #define REG_DVI_DTOP_DUAL_P2_37_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x6F)
4749 #define REG_DVI_DTOP_DUAL_P2_38_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x70)
4750 #define REG_DVI_DTOP_DUAL_P2_38_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x71)
4751 #define REG_DVI_DTOP_DUAL_P2_39_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x72)
4752 #define REG_DVI_DTOP_DUAL_P2_39_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x73)
4753 #define REG_DVI_DTOP_DUAL_P2_3A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x74)
4754 #define REG_DVI_DTOP_DUAL_P2_3A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x75)
4755 #define REG_DVI_DTOP_DUAL_P2_3B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x76)
4756 #define REG_DVI_DTOP_DUAL_P2_3B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x77)
4757 #define REG_DVI_DTOP_DUAL_P2_3C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x78)
4758 #define REG_DVI_DTOP_DUAL_P2_3C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x79)
4759 #define REG_DVI_DTOP_DUAL_P2_3D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7A)
4760 #define REG_DVI_DTOP_DUAL_P2_3D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7B)
4761 #define REG_DVI_DTOP_DUAL_P2_3E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7C)
4762 #define REG_DVI_DTOP_DUAL_P2_3E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7D)
4763 #define REG_DVI_DTOP_DUAL_P2_3F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7E)
4764 #define REG_DVI_DTOP_DUAL_P2_3F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x7F)
4765 #define REG_DVI_DTOP_DUAL_P2_40_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x80)
4766 #define REG_DVI_DTOP_DUAL_P2_40_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x81)
4767 #define REG_DVI_DTOP_DUAL_P2_41_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x82)
4768 #define REG_DVI_DTOP_DUAL_P2_41_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x83)
4769 #define REG_DVI_DTOP_DUAL_P2_42_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x84)
4770 #define REG_DVI_DTOP_DUAL_P2_42_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x85)
4771 #define REG_DVI_DTOP_DUAL_P2_43_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x86)
4772 #define REG_DVI_DTOP_DUAL_P2_43_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x87)
4773 #define REG_DVI_DTOP_DUAL_P2_44_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x88)
4774 #define REG_DVI_DTOP_DUAL_P2_44_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x89)
4775 #define REG_DVI_DTOP_DUAL_P2_45_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8A)
4776 #define REG_DVI_DTOP_DUAL_P2_45_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8B)
4777 #define REG_DVI_DTOP_DUAL_P2_46_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8C)
4778 #define REG_DVI_DTOP_DUAL_P2_46_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8D)
4779 #define REG_DVI_DTOP_DUAL_P2_47_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8E)
4780 #define REG_DVI_DTOP_DUAL_P2_47_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x8F)
4781 #define REG_DVI_DTOP_DUAL_P2_48_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x90)
4782 #define REG_DVI_DTOP_DUAL_P2_48_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x91)
4783 #define REG_DVI_DTOP_DUAL_P2_49_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x92)
4784 #define REG_DVI_DTOP_DUAL_P2_49_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x93)
4785 #define REG_DVI_DTOP_DUAL_P2_4A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x94)
4786 #define REG_DVI_DTOP_DUAL_P2_4A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x95)
4787 #define REG_DVI_DTOP_DUAL_P2_4B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x96)
4788 #define REG_DVI_DTOP_DUAL_P2_4B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x97)
4789 #define REG_DVI_DTOP_DUAL_P2_4C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x98)
4790 #define REG_DVI_DTOP_DUAL_P2_4C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x99)
4791 #define REG_DVI_DTOP_DUAL_P2_4D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9A)
4792 #define REG_DVI_DTOP_DUAL_P2_4D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9B)
4793 #define REG_DVI_DTOP_DUAL_P2_4E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9C)
4794 #define REG_DVI_DTOP_DUAL_P2_4E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9D)
4795 #define REG_DVI_DTOP_DUAL_P2_4F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9E)
4796 #define REG_DVI_DTOP_DUAL_P2_4F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0x9F)
4797 #define REG_DVI_DTOP_DUAL_P2_50_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA0)
4798 #define REG_DVI_DTOP_DUAL_P2_50_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA1)
4799 #define REG_DVI_DTOP_DUAL_P2_51_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA2)
4800 #define REG_DVI_DTOP_DUAL_P2_51_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA3)
4801 #define REG_DVI_DTOP_DUAL_P2_52_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA4)
4802 #define REG_DVI_DTOP_DUAL_P2_52_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA5)
4803 #define REG_DVI_DTOP_DUAL_P2_53_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA6)
4804 #define REG_DVI_DTOP_DUAL_P2_53_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA7)
4805 #define REG_DVI_DTOP_DUAL_P2_54_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA8)
4806 #define REG_DVI_DTOP_DUAL_P2_54_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xA9)
4807 #define REG_DVI_DTOP_DUAL_P2_55_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAA)
4808 #define REG_DVI_DTOP_DUAL_P2_55_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAB)
4809 #define REG_DVI_DTOP_DUAL_P2_56_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAC)
4810 #define REG_DVI_DTOP_DUAL_P2_56_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAD)
4811 #define REG_DVI_DTOP_DUAL_P2_57_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAE)
4812 #define REG_DVI_DTOP_DUAL_P2_57_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xAF)
4813 #define REG_DVI_DTOP_DUAL_P2_58_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB0)
4814 #define REG_DVI_DTOP_DUAL_P2_58_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB1)
4815 #define REG_DVI_DTOP_DUAL_P2_59_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB2)
4816 #define REG_DVI_DTOP_DUAL_P2_59_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB3)
4817 #define REG_DVI_DTOP_DUAL_P2_5A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB4)
4818 #define REG_DVI_DTOP_DUAL_P2_5A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB5)
4819 #define REG_DVI_DTOP_DUAL_P2_5B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB6)
4820 #define REG_DVI_DTOP_DUAL_P2_5B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB7)
4821 #define REG_DVI_DTOP_DUAL_P2_5C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB8)
4822 #define REG_DVI_DTOP_DUAL_P2_5C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xB9)
4823 #define REG_DVI_DTOP_DUAL_P2_5D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBA)
4824 #define REG_DVI_DTOP_DUAL_P2_5D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBB)
4825 #define REG_DVI_DTOP_DUAL_P2_5E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBC)
4826 #define REG_DVI_DTOP_DUAL_P2_5E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBD)
4827 #define REG_DVI_DTOP_DUAL_P2_5F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBE)
4828 #define REG_DVI_DTOP_DUAL_P2_5F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xBF)
4829 #define REG_DVI_DTOP_DUAL_P2_60_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC0)
4830 #define REG_DVI_DTOP_DUAL_P2_60_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC1)
4831 #define REG_DVI_DTOP_DUAL_P2_61_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC2)
4832 #define REG_DVI_DTOP_DUAL_P2_61_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC3)
4833 #define REG_DVI_DTOP_DUAL_P2_62_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC4)
4834 #define REG_DVI_DTOP_DUAL_P2_62_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC5)
4835 #define REG_DVI_DTOP_DUAL_P2_63_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC6)
4836 #define REG_DVI_DTOP_DUAL_P2_63_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC7)
4837 #define REG_DVI_DTOP_DUAL_P2_64_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC8)
4838 #define REG_DVI_DTOP_DUAL_P2_64_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xC9)
4839 #define REG_DVI_DTOP_DUAL_P2_65_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCA)
4840 #define REG_DVI_DTOP_DUAL_P2_65_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCB)
4841 #define REG_DVI_DTOP_DUAL_P2_66_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCC)
4842 #define REG_DVI_DTOP_DUAL_P2_66_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCD)
4843 #define REG_DVI_DTOP_DUAL_P2_67_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCE)
4844 #define REG_DVI_DTOP_DUAL_P2_67_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xCF)
4845 #define REG_DVI_DTOP_DUAL_P2_68_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD0)
4846 #define REG_DVI_DTOP_DUAL_P2_68_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD1)
4847 #define REG_DVI_DTOP_DUAL_P2_69_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD2)
4848 #define REG_DVI_DTOP_DUAL_P2_69_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD3)
4849 #define REG_DVI_DTOP_DUAL_P2_6A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD4)
4850 #define REG_DVI_DTOP_DUAL_P2_6A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD5)
4851 #define REG_DVI_DTOP_DUAL_P2_6B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD6)
4852 #define REG_DVI_DTOP_DUAL_P2_6B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD7)
4853 #define REG_DVI_DTOP_DUAL_P2_6C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD8)
4854 #define REG_DVI_DTOP_DUAL_P2_6C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xD9)
4855 #define REG_DVI_DTOP_DUAL_P2_6D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDA)
4856 #define REG_DVI_DTOP_DUAL_P2_6D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDB)
4857 #define REG_DVI_DTOP_DUAL_P2_6E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDC)
4858 #define REG_DVI_DTOP_DUAL_P2_6E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDD)
4859 #define REG_DVI_DTOP_DUAL_P2_6F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDE)
4860 #define REG_DVI_DTOP_DUAL_P2_6F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xDF)
4861 #define REG_DVI_DTOP_DUAL_P2_70_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE0)
4862 #define REG_DVI_DTOP_DUAL_P2_70_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE1)
4863 #define REG_DVI_DTOP_DUAL_P2_71_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE2)
4864 #define REG_DVI_DTOP_DUAL_P2_71_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE3)
4865 #define REG_DVI_DTOP_DUAL_P2_72_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE4)
4866 #define REG_DVI_DTOP_DUAL_P2_72_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE5)
4867 #define REG_DVI_DTOP_DUAL_P2_73_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE6)
4868 #define REG_DVI_DTOP_DUAL_P2_73_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE7)
4869 #define REG_DVI_DTOP_DUAL_P2_74_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE8)
4870 #define REG_DVI_DTOP_DUAL_P2_74_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xE9)
4871 #define REG_DVI_DTOP_DUAL_P2_75_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEA)
4872 #define REG_DVI_DTOP_DUAL_P2_75_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEB)
4873 #define REG_DVI_DTOP_DUAL_P2_76_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEC)
4874 #define REG_DVI_DTOP_DUAL_P2_76_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xED)
4875 #define REG_DVI_DTOP_DUAL_P2_77_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEE)
4876 #define REG_DVI_DTOP_DUAL_P2_77_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xEF)
4877 #define REG_DVI_DTOP_DUAL_P2_78_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF0)
4878 #define REG_DVI_DTOP_DUAL_P2_78_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF1)
4879 #define REG_DVI_DTOP_DUAL_P2_79_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF2)
4880 #define REG_DVI_DTOP_DUAL_P2_79_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF3)
4881 #define REG_DVI_DTOP_DUAL_P2_7A_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF4)
4882 #define REG_DVI_DTOP_DUAL_P2_7A_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF5)
4883 #define REG_DVI_DTOP_DUAL_P2_7B_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF6)
4884 #define REG_DVI_DTOP_DUAL_P2_7B_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF7)
4885 #define REG_DVI_DTOP_DUAL_P2_7C_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF8)
4886 #define REG_DVI_DTOP_DUAL_P2_7C_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xF9)
4887 #define REG_DVI_DTOP_DUAL_P2_7D_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFA)
4888 #define REG_DVI_DTOP_DUAL_P2_7D_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFB)
4889 #define REG_DVI_DTOP_DUAL_P2_7E_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFC)
4890 #define REG_DVI_DTOP_DUAL_P2_7E_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFD)
4891 #define REG_DVI_DTOP_DUAL_P2_7F_L       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFE)
4892 #define REG_DVI_DTOP_DUAL_P2_7F_H       (REG_DVI_DTOP_DUAL_P2_BASE + 0xFF)
4893 
4894 // DVI_RSV_DUAL_P2
4895 #define REG_DVI_RSV_DUAL_P2_00_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x00)
4896 #define REG_DVI_RSV_DUAL_P2_00_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x01)
4897 #define REG_DVI_RSV_DUAL_P2_01_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x02)
4898 #define REG_DVI_RSV_DUAL_P2_01_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x03)
4899 #define REG_DVI_RSV_DUAL_P2_02_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x04)
4900 #define REG_DVI_RSV_DUAL_P2_02_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x05)
4901 #define REG_DVI_RSV_DUAL_P2_03_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x06)
4902 #define REG_DVI_RSV_DUAL_P2_03_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x07)
4903 #define REG_DVI_RSV_DUAL_P2_04_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x08)
4904 #define REG_DVI_RSV_DUAL_P2_04_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x09)
4905 #define REG_DVI_RSV_DUAL_P2_05_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x0A)
4906 #define REG_DVI_RSV_DUAL_P2_05_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x0B)
4907 #define REG_DVI_RSV_DUAL_P2_06_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x0C)
4908 #define REG_DVI_RSV_DUAL_P2_06_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x0D)
4909 #define REG_DVI_RSV_DUAL_P2_07_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x0E)
4910 #define REG_DVI_RSV_DUAL_P2_07_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x0F)
4911 #define REG_DVI_RSV_DUAL_P2_08_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x10)
4912 #define REG_DVI_RSV_DUAL_P2_08_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x11)
4913 #define REG_DVI_RSV_DUAL_P2_09_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x12)
4914 #define REG_DVI_RSV_DUAL_P2_09_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x13)
4915 #define REG_DVI_RSV_DUAL_P2_0A_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x14)
4916 #define REG_DVI_RSV_DUAL_P2_0A_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x15)
4917 #define REG_DVI_RSV_DUAL_P2_0B_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x16)
4918 #define REG_DVI_RSV_DUAL_P2_0B_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x17)
4919 #define REG_DVI_RSV_DUAL_P2_0C_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x18)
4920 #define REG_DVI_RSV_DUAL_P2_0C_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x19)
4921 #define REG_DVI_RSV_DUAL_P2_0D_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x1A)
4922 #define REG_DVI_RSV_DUAL_P2_0D_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x1B)
4923 #define REG_DVI_RSV_DUAL_P2_0E_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x1C)
4924 #define REG_DVI_RSV_DUAL_P2_0E_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x1D)
4925 #define REG_DVI_RSV_DUAL_P2_0F_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x1E)
4926 #define REG_DVI_RSV_DUAL_P2_0F_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x1F)
4927 #define REG_DVI_RSV_DUAL_P2_10_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x20)
4928 #define REG_DVI_RSV_DUAL_P2_10_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x21)
4929 #define REG_DVI_RSV_DUAL_P2_11_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x22)
4930 #define REG_DVI_RSV_DUAL_P2_11_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x23)
4931 #define REG_DVI_RSV_DUAL_P2_12_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x24)
4932 #define REG_DVI_RSV_DUAL_P2_12_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x25)
4933 #define REG_DVI_RSV_DUAL_P2_13_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x26)
4934 #define REG_DVI_RSV_DUAL_P2_13_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x27)
4935 #define REG_DVI_RSV_DUAL_P2_14_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x28)
4936 #define REG_DVI_RSV_DUAL_P2_14_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x29)
4937 #define REG_DVI_RSV_DUAL_P2_15_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x2A)
4938 #define REG_DVI_RSV_DUAL_P2_15_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x2B)
4939 #define REG_DVI_RSV_DUAL_P2_16_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x2C)
4940 #define REG_DVI_RSV_DUAL_P2_16_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x2D)
4941 #define REG_DVI_RSV_DUAL_P2_17_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x2E)
4942 #define REG_DVI_RSV_DUAL_P2_17_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x2F)
4943 #define REG_DVI_RSV_DUAL_P2_18_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x30)
4944 #define REG_DVI_RSV_DUAL_P2_18_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x31)
4945 #define REG_DVI_RSV_DUAL_P2_19_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x32)
4946 #define REG_DVI_RSV_DUAL_P2_19_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x33)
4947 #define REG_DVI_RSV_DUAL_P2_1A_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x34)
4948 #define REG_DVI_RSV_DUAL_P2_1A_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x35)
4949 #define REG_DVI_RSV_DUAL_P2_1B_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x36)
4950 #define REG_DVI_RSV_DUAL_P2_1B_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x37)
4951 #define REG_DVI_RSV_DUAL_P2_1C_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x38)
4952 #define REG_DVI_RSV_DUAL_P2_1C_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x39)
4953 #define REG_DVI_RSV_DUAL_P2_1D_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x3A)
4954 #define REG_DVI_RSV_DUAL_P2_1D_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x3B)
4955 #define REG_DVI_RSV_DUAL_P2_1E_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x3C)
4956 #define REG_DVI_RSV_DUAL_P2_1E_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x3D)
4957 #define REG_DVI_RSV_DUAL_P2_1F_L       (REG_DVI_RSV_DUAL_P2_BASE + 0x3E)
4958 #define REG_DVI_RSV_DUAL_P2_1F_H       (REG_DVI_RSV_DUAL_P2_BASE + 0x3F)
4959 
4960 // HDCP_DUAL_P2
4961 #define REG_HDCP_DUAL_P2_00_L       (REG_HDCP_DUAL_P2_BASE + 0x00)
4962 #define REG_HDCP_DUAL_P2_00_H       (REG_HDCP_DUAL_P2_BASE + 0x01)
4963 #define REG_HDCP_DUAL_P2_01_L       (REG_HDCP_DUAL_P2_BASE + 0x02)
4964 #define REG_HDCP_DUAL_P2_01_H       (REG_HDCP_DUAL_P2_BASE + 0x03)
4965 #define REG_HDCP_DUAL_P2_02_L       (REG_HDCP_DUAL_P2_BASE + 0x04)
4966 #define REG_HDCP_DUAL_P2_02_H       (REG_HDCP_DUAL_P2_BASE + 0x05)
4967 #define REG_HDCP_DUAL_P2_03_L       (REG_HDCP_DUAL_P2_BASE + 0x06)
4968 #define REG_HDCP_DUAL_P2_03_H       (REG_HDCP_DUAL_P2_BASE + 0x07)
4969 #define REG_HDCP_DUAL_P2_04_L       (REG_HDCP_DUAL_P2_BASE + 0x08)
4970 #define REG_HDCP_DUAL_P2_04_H       (REG_HDCP_DUAL_P2_BASE + 0x09)
4971 #define REG_HDCP_DUAL_P2_05_L       (REG_HDCP_DUAL_P2_BASE + 0x0A)
4972 #define REG_HDCP_DUAL_P2_05_H       (REG_HDCP_DUAL_P2_BASE + 0x0B)
4973 #define REG_HDCP_DUAL_P2_06_L       (REG_HDCP_DUAL_P2_BASE + 0x0C)
4974 #define REG_HDCP_DUAL_P2_06_H       (REG_HDCP_DUAL_P2_BASE + 0x0D)
4975 #define REG_HDCP_DUAL_P2_07_L       (REG_HDCP_DUAL_P2_BASE + 0x0E)
4976 #define REG_HDCP_DUAL_P2_07_H       (REG_HDCP_DUAL_P2_BASE + 0x0F)
4977 #define REG_HDCP_DUAL_P2_08_L       (REG_HDCP_DUAL_P2_BASE + 0x10)
4978 #define REG_HDCP_DUAL_P2_08_H       (REG_HDCP_DUAL_P2_BASE + 0x11)
4979 #define REG_HDCP_DUAL_P2_09_L       (REG_HDCP_DUAL_P2_BASE + 0x12)
4980 #define REG_HDCP_DUAL_P2_09_H       (REG_HDCP_DUAL_P2_BASE + 0x13)
4981 #define REG_HDCP_DUAL_P2_0A_L       (REG_HDCP_DUAL_P2_BASE + 0x14)
4982 #define REG_HDCP_DUAL_P2_0A_H       (REG_HDCP_DUAL_P2_BASE + 0x15)
4983 #define REG_HDCP_DUAL_P2_0B_L       (REG_HDCP_DUAL_P2_BASE + 0x16)
4984 #define REG_HDCP_DUAL_P2_0B_H       (REG_HDCP_DUAL_P2_BASE + 0x17)
4985 #define REG_HDCP_DUAL_P2_0C_L       (REG_HDCP_DUAL_P2_BASE + 0x18)
4986 #define REG_HDCP_DUAL_P2_0C_H       (REG_HDCP_DUAL_P2_BASE + 0x19)
4987 #define REG_HDCP_DUAL_P2_0D_L       (REG_HDCP_DUAL_P2_BASE + 0x1A)
4988 #define REG_HDCP_DUAL_P2_0D_H       (REG_HDCP_DUAL_P2_BASE + 0x1B)
4989 #define REG_HDCP_DUAL_P2_0E_L       (REG_HDCP_DUAL_P2_BASE + 0x1C)
4990 #define REG_HDCP_DUAL_P2_0E_H       (REG_HDCP_DUAL_P2_BASE + 0x1D)
4991 #define REG_HDCP_DUAL_P2_0F_L       (REG_HDCP_DUAL_P2_BASE + 0x1E)
4992 #define REG_HDCP_DUAL_P2_0F_H       (REG_HDCP_DUAL_P2_BASE + 0x1F)
4993 #define REG_HDCP_DUAL_P2_10_L       (REG_HDCP_DUAL_P2_BASE + 0x20)
4994 #define REG_HDCP_DUAL_P2_10_H       (REG_HDCP_DUAL_P2_BASE + 0x21)
4995 #define REG_HDCP_DUAL_P2_11_L       (REG_HDCP_DUAL_P2_BASE + 0x22)
4996 #define REG_HDCP_DUAL_P2_11_H       (REG_HDCP_DUAL_P2_BASE + 0x23)
4997 #define REG_HDCP_DUAL_P2_12_L       (REG_HDCP_DUAL_P2_BASE + 0x24)
4998 #define REG_HDCP_DUAL_P2_12_H       (REG_HDCP_DUAL_P2_BASE + 0x25)
4999 #define REG_HDCP_DUAL_P2_13_L       (REG_HDCP_DUAL_P2_BASE + 0x26)
5000 #define REG_HDCP_DUAL_P2_13_H       (REG_HDCP_DUAL_P2_BASE + 0x27)
5001 #define REG_HDCP_DUAL_P2_14_L       (REG_HDCP_DUAL_P2_BASE + 0x28)
5002 #define REG_HDCP_DUAL_P2_14_H       (REG_HDCP_DUAL_P2_BASE + 0x29)
5003 #define REG_HDCP_DUAL_P2_15_L       (REG_HDCP_DUAL_P2_BASE + 0x2A)
5004 #define REG_HDCP_DUAL_P2_15_H       (REG_HDCP_DUAL_P2_BASE + 0x2B)
5005 #define REG_HDCP_DUAL_P2_16_L       (REG_HDCP_DUAL_P2_BASE + 0x2C)
5006 #define REG_HDCP_DUAL_P2_16_H       (REG_HDCP_DUAL_P2_BASE + 0x2D)
5007 #define REG_HDCP_DUAL_P2_17_L       (REG_HDCP_DUAL_P2_BASE + 0x2E)
5008 #define REG_HDCP_DUAL_P2_17_H       (REG_HDCP_DUAL_P2_BASE + 0x2F)
5009 #define REG_HDCP_DUAL_P2_18_L       (REG_HDCP_DUAL_P2_BASE + 0x30)
5010 #define REG_HDCP_DUAL_P2_18_H       (REG_HDCP_DUAL_P2_BASE + 0x31)
5011 #define REG_HDCP_DUAL_P2_19_L       (REG_HDCP_DUAL_P2_BASE + 0x32)
5012 #define REG_HDCP_DUAL_P2_19_H       (REG_HDCP_DUAL_P2_BASE + 0x33)
5013 #define REG_HDCP_DUAL_P2_1A_L       (REG_HDCP_DUAL_P2_BASE + 0x34)
5014 #define REG_HDCP_DUAL_P2_1A_H       (REG_HDCP_DUAL_P2_BASE + 0x35)
5015 #define REG_HDCP_DUAL_P2_1B_L       (REG_HDCP_DUAL_P2_BASE + 0x36)
5016 #define REG_HDCP_DUAL_P2_1B_H       (REG_HDCP_DUAL_P2_BASE + 0x37)
5017 #define REG_HDCP_DUAL_P2_1C_L       (REG_HDCP_DUAL_P2_BASE + 0x38)
5018 #define REG_HDCP_DUAL_P2_1C_H       (REG_HDCP_DUAL_P2_BASE + 0x39)
5019 #define REG_HDCP_DUAL_P2_1D_L       (REG_HDCP_DUAL_P2_BASE + 0x3A)
5020 #define REG_HDCP_DUAL_P2_1D_H       (REG_HDCP_DUAL_P2_BASE + 0x3B)
5021 #define REG_HDCP_DUAL_P2_1E_L       (REG_HDCP_DUAL_P2_BASE + 0x3C)
5022 #define REG_HDCP_DUAL_P2_1E_H       (REG_HDCP_DUAL_P2_BASE + 0x3D)
5023 #define REG_HDCP_DUAL_P2_1F_L       (REG_HDCP_DUAL_P2_BASE + 0x3E)
5024 #define REG_HDCP_DUAL_P2_1F_H       (REG_HDCP_DUAL_P2_BASE + 0x3F)
5025 #define REG_HDCP_DUAL_P2_20_L       (REG_HDCP_DUAL_P2_BASE + 0x40)
5026 #define REG_HDCP_DUAL_P2_20_H       (REG_HDCP_DUAL_P2_BASE + 0x41)
5027 #define REG_HDCP_DUAL_P2_21_L       (REG_HDCP_DUAL_P2_BASE + 0x42)
5028 #define REG_HDCP_DUAL_P2_21_H       (REG_HDCP_DUAL_P2_BASE + 0x43)
5029 #define REG_HDCP_DUAL_P2_22_L       (REG_HDCP_DUAL_P2_BASE + 0x44)
5030 #define REG_HDCP_DUAL_P2_22_H       (REG_HDCP_DUAL_P2_BASE + 0x45)
5031 #define REG_HDCP_DUAL_P2_23_L       (REG_HDCP_DUAL_P2_BASE + 0x46)
5032 #define REG_HDCP_DUAL_P2_23_H       (REG_HDCP_DUAL_P2_BASE + 0x47)
5033 #define REG_HDCP_DUAL_P2_24_L       (REG_HDCP_DUAL_P2_BASE + 0x48)
5034 #define REG_HDCP_DUAL_P2_24_H       (REG_HDCP_DUAL_P2_BASE + 0x49)
5035 #define REG_HDCP_DUAL_P2_25_L       (REG_HDCP_DUAL_P2_BASE + 0x4A)
5036 #define REG_HDCP_DUAL_P2_25_H       (REG_HDCP_DUAL_P2_BASE + 0x4B)
5037 #define REG_HDCP_DUAL_P2_26_L       (REG_HDCP_DUAL_P2_BASE + 0x4C)
5038 #define REG_HDCP_DUAL_P2_26_H       (REG_HDCP_DUAL_P2_BASE + 0x4D)
5039 #define REG_HDCP_DUAL_P2_27_L       (REG_HDCP_DUAL_P2_BASE + 0x4E)
5040 #define REG_HDCP_DUAL_P2_27_H       (REG_HDCP_DUAL_P2_BASE + 0x4F)
5041 #define REG_HDCP_DUAL_P2_28_L       (REG_HDCP_DUAL_P2_BASE + 0x50)
5042 #define REG_HDCP_DUAL_P2_28_H       (REG_HDCP_DUAL_P2_BASE + 0x51)
5043 #define REG_HDCP_DUAL_P2_29_L       (REG_HDCP_DUAL_P2_BASE + 0x52)
5044 #define REG_HDCP_DUAL_P2_29_H       (REG_HDCP_DUAL_P2_BASE + 0x53)
5045 #define REG_HDCP_DUAL_P2_2A_L       (REG_HDCP_DUAL_P2_BASE + 0x54)
5046 #define REG_HDCP_DUAL_P2_2A_H       (REG_HDCP_DUAL_P2_BASE + 0x55)
5047 #define REG_HDCP_DUAL_P2_2B_L       (REG_HDCP_DUAL_P2_BASE + 0x56)
5048 #define REG_HDCP_DUAL_P2_2B_H       (REG_HDCP_DUAL_P2_BASE + 0x57)
5049 #define REG_HDCP_DUAL_P2_2C_L       (REG_HDCP_DUAL_P2_BASE + 0x58)
5050 #define REG_HDCP_DUAL_P2_2C_H       (REG_HDCP_DUAL_P2_BASE + 0x59)
5051 #define REG_HDCP_DUAL_P2_2D_L       (REG_HDCP_DUAL_P2_BASE + 0x5A)
5052 #define REG_HDCP_DUAL_P2_2D_H       (REG_HDCP_DUAL_P2_BASE + 0x5B)
5053 #define REG_HDCP_DUAL_P2_2E_L       (REG_HDCP_DUAL_P2_BASE + 0x5C)
5054 #define REG_HDCP_DUAL_P2_2E_H       (REG_HDCP_DUAL_P2_BASE + 0x5D)
5055 #define REG_HDCP_DUAL_P2_2F_L       (REG_HDCP_DUAL_P2_BASE + 0x5E)
5056 #define REG_HDCP_DUAL_P2_2F_H       (REG_HDCP_DUAL_P2_BASE + 0x5F)
5057 #define REG_HDCP_DUAL_P2_30_L       (REG_HDCP_DUAL_P2_BASE + 0x60)
5058 #define REG_HDCP_DUAL_P2_30_H       (REG_HDCP_DUAL_P2_BASE + 0x61)
5059 #define REG_HDCP_DUAL_P2_31_L       (REG_HDCP_DUAL_P2_BASE + 0x62)
5060 #define REG_HDCP_DUAL_P2_31_H       (REG_HDCP_DUAL_P2_BASE + 0x63)
5061 #define REG_HDCP_DUAL_P2_32_L       (REG_HDCP_DUAL_P2_BASE + 0x64)
5062 #define REG_HDCP_DUAL_P2_32_H       (REG_HDCP_DUAL_P2_BASE + 0x65)
5063 #define REG_HDCP_DUAL_P2_33_L       (REG_HDCP_DUAL_P2_BASE + 0x66)
5064 #define REG_HDCP_DUAL_P2_33_H       (REG_HDCP_DUAL_P2_BASE + 0x67)
5065 #define REG_HDCP_DUAL_P2_34_L       (REG_HDCP_DUAL_P2_BASE + 0x68)
5066 #define REG_HDCP_DUAL_P2_34_H       (REG_HDCP_DUAL_P2_BASE + 0x69)
5067 #define REG_HDCP_DUAL_P2_35_L       (REG_HDCP_DUAL_P2_BASE + 0x6A)
5068 #define REG_HDCP_DUAL_P2_35_H       (REG_HDCP_DUAL_P2_BASE + 0x6B)
5069 #define REG_HDCP_DUAL_P2_36_L       (REG_HDCP_DUAL_P2_BASE + 0x6C)
5070 #define REG_HDCP_DUAL_P2_36_H       (REG_HDCP_DUAL_P2_BASE + 0x6D)
5071 #define REG_HDCP_DUAL_P2_37_L       (REG_HDCP_DUAL_P2_BASE + 0x6E)
5072 #define REG_HDCP_DUAL_P2_37_H       (REG_HDCP_DUAL_P2_BASE + 0x6F)
5073 #define REG_HDCP_DUAL_P2_38_L       (REG_HDCP_DUAL_P2_BASE + 0x70)
5074 #define REG_HDCP_DUAL_P2_38_H       (REG_HDCP_DUAL_P2_BASE + 0x71)
5075 #define REG_HDCP_DUAL_P2_39_L       (REG_HDCP_DUAL_P2_BASE + 0x72)
5076 #define REG_HDCP_DUAL_P2_39_H       (REG_HDCP_DUAL_P2_BASE + 0x73)
5077 #define REG_HDCP_DUAL_P2_3A_L       (REG_HDCP_DUAL_P2_BASE + 0x74)
5078 #define REG_HDCP_DUAL_P2_3A_H       (REG_HDCP_DUAL_P2_BASE + 0x75)
5079 #define REG_HDCP_DUAL_P2_3B_L       (REG_HDCP_DUAL_P2_BASE + 0x76)
5080 #define REG_HDCP_DUAL_P2_3B_H       (REG_HDCP_DUAL_P2_BASE + 0x77)
5081 #define REG_HDCP_DUAL_P2_3C_L       (REG_HDCP_DUAL_P2_BASE + 0x78)
5082 #define REG_HDCP_DUAL_P2_3C_H       (REG_HDCP_DUAL_P2_BASE + 0x79)
5083 #define REG_HDCP_DUAL_P2_3D_L       (REG_HDCP_DUAL_P2_BASE + 0x7A)
5084 #define REG_HDCP_DUAL_P2_3D_H       (REG_HDCP_DUAL_P2_BASE + 0x7B)
5085 #define REG_HDCP_DUAL_P2_3E_L       (REG_HDCP_DUAL_P2_BASE + 0x7C)
5086 #define REG_HDCP_DUAL_P2_3E_H       (REG_HDCP_DUAL_P2_BASE + 0x7D)
5087 #define REG_HDCP_DUAL_P2_3F_L       (REG_HDCP_DUAL_P2_BASE + 0x7E)
5088 #define REG_HDCP_DUAL_P2_3F_H       (REG_HDCP_DUAL_P2_BASE + 0x7F)
5089 #define REG_HDCP_DUAL_P2_40_L       (REG_HDCP_DUAL_P2_BASE + 0x80)
5090 #define REG_HDCP_DUAL_P2_40_H       (REG_HDCP_DUAL_P2_BASE + 0x81)
5091 #define REG_HDCP_DUAL_P2_41_L       (REG_HDCP_DUAL_P2_BASE + 0x82)
5092 #define REG_HDCP_DUAL_P2_41_H       (REG_HDCP_DUAL_P2_BASE + 0x83)
5093 #define REG_HDCP_DUAL_P2_42_L       (REG_HDCP_DUAL_P2_BASE + 0x84)
5094 #define REG_HDCP_DUAL_P2_42_H       (REG_HDCP_DUAL_P2_BASE + 0x85)
5095 #define REG_HDCP_DUAL_P2_43_L       (REG_HDCP_DUAL_P2_BASE + 0x86)
5096 #define REG_HDCP_DUAL_P2_43_H       (REG_HDCP_DUAL_P2_BASE + 0x87)
5097 #define REG_HDCP_DUAL_P2_44_L       (REG_HDCP_DUAL_P2_BASE + 0x88)
5098 #define REG_HDCP_DUAL_P2_44_H       (REG_HDCP_DUAL_P2_BASE + 0x89)
5099 #define REG_HDCP_DUAL_P2_45_L       (REG_HDCP_DUAL_P2_BASE + 0x8A)
5100 #define REG_HDCP_DUAL_P2_45_H       (REG_HDCP_DUAL_P2_BASE + 0x8B)
5101 #define REG_HDCP_DUAL_P2_46_L       (REG_HDCP_DUAL_P2_BASE + 0x8C)
5102 #define REG_HDCP_DUAL_P2_46_H       (REG_HDCP_DUAL_P2_BASE + 0x8D)
5103 #define REG_HDCP_DUAL_P2_47_L       (REG_HDCP_DUAL_P2_BASE + 0x8E)
5104 #define REG_HDCP_DUAL_P2_47_H       (REG_HDCP_DUAL_P2_BASE + 0x8F)
5105 #define REG_HDCP_DUAL_P2_48_L       (REG_HDCP_DUAL_P2_BASE + 0x90)
5106 #define REG_HDCP_DUAL_P2_48_H       (REG_HDCP_DUAL_P2_BASE + 0x91)
5107 #define REG_HDCP_DUAL_P2_49_L       (REG_HDCP_DUAL_P2_BASE + 0x92)
5108 #define REG_HDCP_DUAL_P2_49_H       (REG_HDCP_DUAL_P2_BASE + 0x93)
5109 #define REG_HDCP_DUAL_P2_4A_L       (REG_HDCP_DUAL_P2_BASE + 0x94)
5110 #define REG_HDCP_DUAL_P2_4A_H       (REG_HDCP_DUAL_P2_BASE + 0x95)
5111 #define REG_HDCP_DUAL_P2_4B_L       (REG_HDCP_DUAL_P2_BASE + 0x96)
5112 #define REG_HDCP_DUAL_P2_4B_H       (REG_HDCP_DUAL_P2_BASE + 0x97)
5113 #define REG_HDCP_DUAL_P2_4C_L       (REG_HDCP_DUAL_P2_BASE + 0x98)
5114 #define REG_HDCP_DUAL_P2_4C_H       (REG_HDCP_DUAL_P2_BASE + 0x99)
5115 #define REG_HDCP_DUAL_P2_4D_L       (REG_HDCP_DUAL_P2_BASE + 0x9A)
5116 #define REG_HDCP_DUAL_P2_4D_H       (REG_HDCP_DUAL_P2_BASE + 0x9B)
5117 #define REG_HDCP_DUAL_P2_4E_L       (REG_HDCP_DUAL_P2_BASE + 0x9C)
5118 #define REG_HDCP_DUAL_P2_4E_H       (REG_HDCP_DUAL_P2_BASE + 0x9D)
5119 #define REG_HDCP_DUAL_P2_4F_L       (REG_HDCP_DUAL_P2_BASE + 0x9E)
5120 #define REG_HDCP_DUAL_P2_4F_H       (REG_HDCP_DUAL_P2_BASE + 0x9F)
5121 #define REG_HDCP_DUAL_P2_50_L       (REG_HDCP_DUAL_P2_BASE + 0xA0)
5122 #define REG_HDCP_DUAL_P2_50_H       (REG_HDCP_DUAL_P2_BASE + 0xA1)
5123 #define REG_HDCP_DUAL_P2_51_L       (REG_HDCP_DUAL_P2_BASE + 0xA2)
5124 #define REG_HDCP_DUAL_P2_51_H       (REG_HDCP_DUAL_P2_BASE + 0xA3)
5125 #define REG_HDCP_DUAL_P2_52_L       (REG_HDCP_DUAL_P2_BASE + 0xA4)
5126 #define REG_HDCP_DUAL_P2_52_H       (REG_HDCP_DUAL_P2_BASE + 0xA5)
5127 #define REG_HDCP_DUAL_P2_53_L       (REG_HDCP_DUAL_P2_BASE + 0xA6)
5128 #define REG_HDCP_DUAL_P2_53_H       (REG_HDCP_DUAL_P2_BASE + 0xA7)
5129 #define REG_HDCP_DUAL_P2_54_L       (REG_HDCP_DUAL_P2_BASE + 0xA8)
5130 #define REG_HDCP_DUAL_P2_54_H       (REG_HDCP_DUAL_P2_BASE + 0xA9)
5131 #define REG_HDCP_DUAL_P2_55_L       (REG_HDCP_DUAL_P2_BASE + 0xAA)
5132 #define REG_HDCP_DUAL_P2_55_H       (REG_HDCP_DUAL_P2_BASE + 0xAB)
5133 #define REG_HDCP_DUAL_P2_56_L       (REG_HDCP_DUAL_P2_BASE + 0xAC)
5134 #define REG_HDCP_DUAL_P2_56_H       (REG_HDCP_DUAL_P2_BASE + 0xAD)
5135 #define REG_HDCP_DUAL_P2_57_L       (REG_HDCP_DUAL_P2_BASE + 0xAE)
5136 #define REG_HDCP_DUAL_P2_57_H       (REG_HDCP_DUAL_P2_BASE + 0xAF)
5137 #define REG_HDCP_DUAL_P2_58_L       (REG_HDCP_DUAL_P2_BASE + 0xB0)
5138 #define REG_HDCP_DUAL_P2_58_H       (REG_HDCP_DUAL_P2_BASE + 0xB1)
5139 #define REG_HDCP_DUAL_P2_59_L       (REG_HDCP_DUAL_P2_BASE + 0xB2)
5140 #define REG_HDCP_DUAL_P2_59_H       (REG_HDCP_DUAL_P2_BASE + 0xB3)
5141 #define REG_HDCP_DUAL_P2_5A_L       (REG_HDCP_DUAL_P2_BASE + 0xB4)
5142 #define REG_HDCP_DUAL_P2_5A_H       (REG_HDCP_DUAL_P2_BASE + 0xB5)
5143 #define REG_HDCP_DUAL_P2_5B_L       (REG_HDCP_DUAL_P2_BASE + 0xB6)
5144 #define REG_HDCP_DUAL_P2_5B_H       (REG_HDCP_DUAL_P2_BASE + 0xB7)
5145 #define REG_HDCP_DUAL_P2_5C_L       (REG_HDCP_DUAL_P2_BASE + 0xB8)
5146 #define REG_HDCP_DUAL_P2_5C_H       (REG_HDCP_DUAL_P2_BASE + 0xB9)
5147 #define REG_HDCP_DUAL_P2_5D_L       (REG_HDCP_DUAL_P2_BASE + 0xBA)
5148 #define REG_HDCP_DUAL_P2_5D_H       (REG_HDCP_DUAL_P2_BASE + 0xBB)
5149 #define REG_HDCP_DUAL_P2_5E_L       (REG_HDCP_DUAL_P2_BASE + 0xBC)
5150 #define REG_HDCP_DUAL_P2_5E_H       (REG_HDCP_DUAL_P2_BASE + 0xBD)
5151 #define REG_HDCP_DUAL_P2_5F_L       (REG_HDCP_DUAL_P2_BASE + 0xBE)
5152 #define REG_HDCP_DUAL_P2_5F_H       (REG_HDCP_DUAL_P2_BASE + 0xBF)
5153 #define REG_HDCP_DUAL_P2_60_L       (REG_HDCP_DUAL_P2_BASE + 0xC0)
5154 #define REG_HDCP_DUAL_P2_60_H       (REG_HDCP_DUAL_P2_BASE + 0xC1)
5155 #define REG_HDCP_DUAL_P2_61_L       (REG_HDCP_DUAL_P2_BASE + 0xC2)
5156 #define REG_HDCP_DUAL_P2_61_H       (REG_HDCP_DUAL_P2_BASE + 0xC3)
5157 #define REG_HDCP_DUAL_P2_62_L       (REG_HDCP_DUAL_P2_BASE + 0xC4)
5158 #define REG_HDCP_DUAL_P2_62_H       (REG_HDCP_DUAL_P2_BASE + 0xC5)
5159 #define REG_HDCP_DUAL_P2_63_L       (REG_HDCP_DUAL_P2_BASE + 0xC6)
5160 #define REG_HDCP_DUAL_P2_63_H       (REG_HDCP_DUAL_P2_BASE + 0xC7)
5161 #define REG_HDCP_DUAL_P2_64_L       (REG_HDCP_DUAL_P2_BASE + 0xC8)
5162 #define REG_HDCP_DUAL_P2_64_H       (REG_HDCP_DUAL_P2_BASE + 0xC9)
5163 #define REG_HDCP_DUAL_P2_65_L       (REG_HDCP_DUAL_P2_BASE + 0xCA)
5164 #define REG_HDCP_DUAL_P2_65_H       (REG_HDCP_DUAL_P2_BASE + 0xCB)
5165 #define REG_HDCP_DUAL_P2_66_L       (REG_HDCP_DUAL_P2_BASE + 0xCC)
5166 #define REG_HDCP_DUAL_P2_66_H       (REG_HDCP_DUAL_P2_BASE + 0xCD)
5167 #define REG_HDCP_DUAL_P2_67_L       (REG_HDCP_DUAL_P2_BASE + 0xCE)
5168 #define REG_HDCP_DUAL_P2_67_H       (REG_HDCP_DUAL_P2_BASE + 0xCF)
5169 #define REG_HDCP_DUAL_P2_68_L       (REG_HDCP_DUAL_P2_BASE + 0xD0)
5170 #define REG_HDCP_DUAL_P2_68_H       (REG_HDCP_DUAL_P2_BASE + 0xD1)
5171 
5172 // DVI_DTOP_DUAL_P3
5173 #define REG_DVI_DTOP_DUAL_P3_00_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x00)
5174 #define REG_DVI_DTOP_DUAL_P3_00_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x01)
5175 #define REG_DVI_DTOP_DUAL_P3_01_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x02)
5176 #define REG_DVI_DTOP_DUAL_P3_01_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x03)
5177 #define REG_DVI_DTOP_DUAL_P3_02_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x04)
5178 #define REG_DVI_DTOP_DUAL_P3_02_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x05)
5179 #define REG_DVI_DTOP_DUAL_P3_03_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x06)
5180 #define REG_DVI_DTOP_DUAL_P3_03_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x07)
5181 #define REG_DVI_DTOP_DUAL_P3_04_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x08)
5182 #define REG_DVI_DTOP_DUAL_P3_04_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x09)
5183 #define REG_DVI_DTOP_DUAL_P3_05_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0A)
5184 #define REG_DVI_DTOP_DUAL_P3_05_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0B)
5185 #define REG_DVI_DTOP_DUAL_P3_06_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0C)
5186 #define REG_DVI_DTOP_DUAL_P3_06_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0D)
5187 #define REG_DVI_DTOP_DUAL_P3_07_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0E)
5188 #define REG_DVI_DTOP_DUAL_P3_07_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x0F)
5189 #define REG_DVI_DTOP_DUAL_P3_08_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x10)
5190 #define REG_DVI_DTOP_DUAL_P3_08_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x11)
5191 #define REG_DVI_DTOP_DUAL_P3_09_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x12)
5192 #define REG_DVI_DTOP_DUAL_P3_09_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x13)
5193 #define REG_DVI_DTOP_DUAL_P3_0A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x14)
5194 #define REG_DVI_DTOP_DUAL_P3_0A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x15)
5195 #define REG_DVI_DTOP_DUAL_P3_0B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x16)
5196 #define REG_DVI_DTOP_DUAL_P3_0B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x17)
5197 #define REG_DVI_DTOP_DUAL_P3_0C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x18)
5198 #define REG_DVI_DTOP_DUAL_P3_0C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x19)
5199 #define REG_DVI_DTOP_DUAL_P3_0D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1A)
5200 #define REG_DVI_DTOP_DUAL_P3_0D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1B)
5201 #define REG_DVI_DTOP_DUAL_P3_0E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1C)
5202 #define REG_DVI_DTOP_DUAL_P3_0E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1D)
5203 #define REG_DVI_DTOP_DUAL_P3_0F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1E)
5204 #define REG_DVI_DTOP_DUAL_P3_0F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x1F)
5205 #define REG_DVI_DTOP_DUAL_P3_10_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x20)
5206 #define REG_DVI_DTOP_DUAL_P3_10_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x21)
5207 #define REG_DVI_DTOP_DUAL_P3_11_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x22)
5208 #define REG_DVI_DTOP_DUAL_P3_11_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x23)
5209 #define REG_DVI_DTOP_DUAL_P3_12_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x24)
5210 #define REG_DVI_DTOP_DUAL_P3_12_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x25)
5211 #define REG_DVI_DTOP_DUAL_P3_13_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x26)
5212 #define REG_DVI_DTOP_DUAL_P3_13_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x27)
5213 #define REG_DVI_DTOP_DUAL_P3_14_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x28)
5214 #define REG_DVI_DTOP_DUAL_P3_14_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x29)
5215 #define REG_DVI_DTOP_DUAL_P3_15_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2A)
5216 #define REG_DVI_DTOP_DUAL_P3_15_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2B)
5217 #define REG_DVI_DTOP_DUAL_P3_16_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2C)
5218 #define REG_DVI_DTOP_DUAL_P3_16_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2D)
5219 #define REG_DVI_DTOP_DUAL_P3_17_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2E)
5220 #define REG_DVI_DTOP_DUAL_P3_17_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x2F)
5221 #define REG_DVI_DTOP_DUAL_P3_18_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x30)
5222 #define REG_DVI_DTOP_DUAL_P3_18_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x31)
5223 #define REG_DVI_DTOP_DUAL_P3_19_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x32)
5224 #define REG_DVI_DTOP_DUAL_P3_19_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x33)
5225 #define REG_DVI_DTOP_DUAL_P3_1A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x34)
5226 #define REG_DVI_DTOP_DUAL_P3_1A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x35)
5227 #define REG_DVI_DTOP_DUAL_P3_1B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x36)
5228 #define REG_DVI_DTOP_DUAL_P3_1B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x37)
5229 #define REG_DVI_DTOP_DUAL_P3_1C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x38)
5230 #define REG_DVI_DTOP_DUAL_P3_1C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x39)
5231 #define REG_DVI_DTOP_DUAL_P3_1D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3A)
5232 #define REG_DVI_DTOP_DUAL_P3_1D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3B)
5233 #define REG_DVI_DTOP_DUAL_P3_1E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3C)
5234 #define REG_DVI_DTOP_DUAL_P3_1E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3D)
5235 #define REG_DVI_DTOP_DUAL_P3_1F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3E)
5236 #define REG_DVI_DTOP_DUAL_P3_1F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x3F)
5237 #define REG_DVI_DTOP_DUAL_P3_20_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x40)
5238 #define REG_DVI_DTOP_DUAL_P3_20_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x41)
5239 #define REG_DVI_DTOP_DUAL_P3_21_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x42)
5240 #define REG_DVI_DTOP_DUAL_P3_21_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x43)
5241 #define REG_DVI_DTOP_DUAL_P3_22_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x44)
5242 #define REG_DVI_DTOP_DUAL_P3_22_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x45)
5243 #define REG_DVI_DTOP_DUAL_P3_23_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x46)
5244 #define REG_DVI_DTOP_DUAL_P3_23_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x47)
5245 #define REG_DVI_DTOP_DUAL_P3_24_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x48)
5246 #define REG_DVI_DTOP_DUAL_P3_24_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x49)
5247 #define REG_DVI_DTOP_DUAL_P3_25_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4A)
5248 #define REG_DVI_DTOP_DUAL_P3_25_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4B)
5249 #define REG_DVI_DTOP_DUAL_P3_26_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4C)
5250 #define REG_DVI_DTOP_DUAL_P3_26_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4D)
5251 #define REG_DVI_DTOP_DUAL_P3_27_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4E)
5252 #define REG_DVI_DTOP_DUAL_P3_27_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x4F)
5253 #define REG_DVI_DTOP_DUAL_P3_28_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x50)
5254 #define REG_DVI_DTOP_DUAL_P3_28_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x51)
5255 #define REG_DVI_DTOP_DUAL_P3_29_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x52)
5256 #define REG_DVI_DTOP_DUAL_P3_29_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x53)
5257 #define REG_DVI_DTOP_DUAL_P3_2A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x54)
5258 #define REG_DVI_DTOP_DUAL_P3_2A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x55)
5259 #define REG_DVI_DTOP_DUAL_P3_2B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x56)
5260 #define REG_DVI_DTOP_DUAL_P3_2B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x57)
5261 #define REG_DVI_DTOP_DUAL_P3_2C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x58)
5262 #define REG_DVI_DTOP_DUAL_P3_2C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x59)
5263 #define REG_DVI_DTOP_DUAL_P3_2D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5A)
5264 #define REG_DVI_DTOP_DUAL_P3_2D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5B)
5265 #define REG_DVI_DTOP_DUAL_P3_2E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5C)
5266 #define REG_DVI_DTOP_DUAL_P3_2E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5D)
5267 #define REG_DVI_DTOP_DUAL_P3_2F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5E)
5268 #define REG_DVI_DTOP_DUAL_P3_2F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x5F)
5269 #define REG_DVI_DTOP_DUAL_P3_30_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x60)
5270 #define REG_DVI_DTOP_DUAL_P3_30_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x61)
5271 #define REG_DVI_DTOP_DUAL_P3_31_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x62)
5272 #define REG_DVI_DTOP_DUAL_P3_31_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x63)
5273 #define REG_DVI_DTOP_DUAL_P3_32_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x64)
5274 #define REG_DVI_DTOP_DUAL_P3_32_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x65)
5275 #define REG_DVI_DTOP_DUAL_P3_33_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x66)
5276 #define REG_DVI_DTOP_DUAL_P3_33_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x67)
5277 #define REG_DVI_DTOP_DUAL_P3_34_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x68)
5278 #define REG_DVI_DTOP_DUAL_P3_34_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x69)
5279 #define REG_DVI_DTOP_DUAL_P3_35_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6A)
5280 #define REG_DVI_DTOP_DUAL_P3_35_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6B)
5281 #define REG_DVI_DTOP_DUAL_P3_36_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6C)
5282 #define REG_DVI_DTOP_DUAL_P3_36_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6D)
5283 #define REG_DVI_DTOP_DUAL_P3_37_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6E)
5284 #define REG_DVI_DTOP_DUAL_P3_37_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x6F)
5285 #define REG_DVI_DTOP_DUAL_P3_38_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x70)
5286 #define REG_DVI_DTOP_DUAL_P3_38_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x71)
5287 #define REG_DVI_DTOP_DUAL_P3_39_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x72)
5288 #define REG_DVI_DTOP_DUAL_P3_39_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x73)
5289 #define REG_DVI_DTOP_DUAL_P3_3A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x74)
5290 #define REG_DVI_DTOP_DUAL_P3_3A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x75)
5291 #define REG_DVI_DTOP_DUAL_P3_3B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x76)
5292 #define REG_DVI_DTOP_DUAL_P3_3B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x77)
5293 #define REG_DVI_DTOP_DUAL_P3_3C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x78)
5294 #define REG_DVI_DTOP_DUAL_P3_3C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x79)
5295 #define REG_DVI_DTOP_DUAL_P3_3D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7A)
5296 #define REG_DVI_DTOP_DUAL_P3_3D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7B)
5297 #define REG_DVI_DTOP_DUAL_P3_3E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7C)
5298 #define REG_DVI_DTOP_DUAL_P3_3E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7D)
5299 #define REG_DVI_DTOP_DUAL_P3_3F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7E)
5300 #define REG_DVI_DTOP_DUAL_P3_3F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x7F)
5301 #define REG_DVI_DTOP_DUAL_P3_40_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x80)
5302 #define REG_DVI_DTOP_DUAL_P3_40_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x81)
5303 #define REG_DVI_DTOP_DUAL_P3_41_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x82)
5304 #define REG_DVI_DTOP_DUAL_P3_41_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x83)
5305 #define REG_DVI_DTOP_DUAL_P3_42_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x84)
5306 #define REG_DVI_DTOP_DUAL_P3_42_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x85)
5307 #define REG_DVI_DTOP_DUAL_P3_43_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x86)
5308 #define REG_DVI_DTOP_DUAL_P3_43_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x87)
5309 #define REG_DVI_DTOP_DUAL_P3_44_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x88)
5310 #define REG_DVI_DTOP_DUAL_P3_44_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x89)
5311 #define REG_DVI_DTOP_DUAL_P3_45_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8A)
5312 #define REG_DVI_DTOP_DUAL_P3_45_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8B)
5313 #define REG_DVI_DTOP_DUAL_P3_46_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8C)
5314 #define REG_DVI_DTOP_DUAL_P3_46_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8D)
5315 #define REG_DVI_DTOP_DUAL_P3_47_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8E)
5316 #define REG_DVI_DTOP_DUAL_P3_47_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x8F)
5317 #define REG_DVI_DTOP_DUAL_P3_48_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x90)
5318 #define REG_DVI_DTOP_DUAL_P3_48_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x91)
5319 #define REG_DVI_DTOP_DUAL_P3_49_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x92)
5320 #define REG_DVI_DTOP_DUAL_P3_49_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x93)
5321 #define REG_DVI_DTOP_DUAL_P3_4A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x94)
5322 #define REG_DVI_DTOP_DUAL_P3_4A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x95)
5323 #define REG_DVI_DTOP_DUAL_P3_4B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x96)
5324 #define REG_DVI_DTOP_DUAL_P3_4B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x97)
5325 #define REG_DVI_DTOP_DUAL_P3_4C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x98)
5326 #define REG_DVI_DTOP_DUAL_P3_4C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x99)
5327 #define REG_DVI_DTOP_DUAL_P3_4D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9A)
5328 #define REG_DVI_DTOP_DUAL_P3_4D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9B)
5329 #define REG_DVI_DTOP_DUAL_P3_4E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9C)
5330 #define REG_DVI_DTOP_DUAL_P3_4E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9D)
5331 #define REG_DVI_DTOP_DUAL_P3_4F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9E)
5332 #define REG_DVI_DTOP_DUAL_P3_4F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0x9F)
5333 #define REG_DVI_DTOP_DUAL_P3_50_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA0)
5334 #define REG_DVI_DTOP_DUAL_P3_50_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA1)
5335 #define REG_DVI_DTOP_DUAL_P3_51_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA2)
5336 #define REG_DVI_DTOP_DUAL_P3_51_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA3)
5337 #define REG_DVI_DTOP_DUAL_P3_52_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA4)
5338 #define REG_DVI_DTOP_DUAL_P3_52_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA5)
5339 #define REG_DVI_DTOP_DUAL_P3_53_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA6)
5340 #define REG_DVI_DTOP_DUAL_P3_53_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA7)
5341 #define REG_DVI_DTOP_DUAL_P3_54_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA8)
5342 #define REG_DVI_DTOP_DUAL_P3_54_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xA9)
5343 #define REG_DVI_DTOP_DUAL_P3_55_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAA)
5344 #define REG_DVI_DTOP_DUAL_P3_55_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAB)
5345 #define REG_DVI_DTOP_DUAL_P3_56_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAC)
5346 #define REG_DVI_DTOP_DUAL_P3_56_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAD)
5347 #define REG_DVI_DTOP_DUAL_P3_57_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAE)
5348 #define REG_DVI_DTOP_DUAL_P3_57_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xAF)
5349 #define REG_DVI_DTOP_DUAL_P3_58_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB0)
5350 #define REG_DVI_DTOP_DUAL_P3_58_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB1)
5351 #define REG_DVI_DTOP_DUAL_P3_59_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB2)
5352 #define REG_DVI_DTOP_DUAL_P3_59_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB3)
5353 #define REG_DVI_DTOP_DUAL_P3_5A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB4)
5354 #define REG_DVI_DTOP_DUAL_P3_5A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB5)
5355 #define REG_DVI_DTOP_DUAL_P3_5B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB6)
5356 #define REG_DVI_DTOP_DUAL_P3_5B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB7)
5357 #define REG_DVI_DTOP_DUAL_P3_5C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB8)
5358 #define REG_DVI_DTOP_DUAL_P3_5C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xB9)
5359 #define REG_DVI_DTOP_DUAL_P3_5D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBA)
5360 #define REG_DVI_DTOP_DUAL_P3_5D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBB)
5361 #define REG_DVI_DTOP_DUAL_P3_5E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBC)
5362 #define REG_DVI_DTOP_DUAL_P3_5E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBD)
5363 #define REG_DVI_DTOP_DUAL_P3_5F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBE)
5364 #define REG_DVI_DTOP_DUAL_P3_5F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xBF)
5365 #define REG_DVI_DTOP_DUAL_P3_60_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC0)
5366 #define REG_DVI_DTOP_DUAL_P3_60_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC1)
5367 #define REG_DVI_DTOP_DUAL_P3_61_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC2)
5368 #define REG_DVI_DTOP_DUAL_P3_61_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC3)
5369 #define REG_DVI_DTOP_DUAL_P3_62_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC4)
5370 #define REG_DVI_DTOP_DUAL_P3_62_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC5)
5371 #define REG_DVI_DTOP_DUAL_P3_63_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC6)
5372 #define REG_DVI_DTOP_DUAL_P3_63_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC7)
5373 #define REG_DVI_DTOP_DUAL_P3_64_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC8)
5374 #define REG_DVI_DTOP_DUAL_P3_64_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xC9)
5375 #define REG_DVI_DTOP_DUAL_P3_65_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCA)
5376 #define REG_DVI_DTOP_DUAL_P3_65_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCB)
5377 #define REG_DVI_DTOP_DUAL_P3_66_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCC)
5378 #define REG_DVI_DTOP_DUAL_P3_66_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCD)
5379 #define REG_DVI_DTOP_DUAL_P3_67_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCE)
5380 #define REG_DVI_DTOP_DUAL_P3_67_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xCF)
5381 #define REG_DVI_DTOP_DUAL_P3_68_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD0)
5382 #define REG_DVI_DTOP_DUAL_P3_68_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD1)
5383 #define REG_DVI_DTOP_DUAL_P3_69_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD2)
5384 #define REG_DVI_DTOP_DUAL_P3_69_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD3)
5385 #define REG_DVI_DTOP_DUAL_P3_6A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD4)
5386 #define REG_DVI_DTOP_DUAL_P3_6A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD5)
5387 #define REG_DVI_DTOP_DUAL_P3_6B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD6)
5388 #define REG_DVI_DTOP_DUAL_P3_6B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD7)
5389 #define REG_DVI_DTOP_DUAL_P3_6C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD8)
5390 #define REG_DVI_DTOP_DUAL_P3_6C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xD9)
5391 #define REG_DVI_DTOP_DUAL_P3_6D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDA)
5392 #define REG_DVI_DTOP_DUAL_P3_6D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDB)
5393 #define REG_DVI_DTOP_DUAL_P3_6E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDC)
5394 #define REG_DVI_DTOP_DUAL_P3_6E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDD)
5395 #define REG_DVI_DTOP_DUAL_P3_6F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDE)
5396 #define REG_DVI_DTOP_DUAL_P3_6F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xDF)
5397 #define REG_DVI_DTOP_DUAL_P3_70_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE0)
5398 #define REG_DVI_DTOP_DUAL_P3_70_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE1)
5399 #define REG_DVI_DTOP_DUAL_P3_71_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE2)
5400 #define REG_DVI_DTOP_DUAL_P3_71_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE3)
5401 #define REG_DVI_DTOP_DUAL_P3_72_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE4)
5402 #define REG_DVI_DTOP_DUAL_P3_72_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE5)
5403 #define REG_DVI_DTOP_DUAL_P3_73_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE6)
5404 #define REG_DVI_DTOP_DUAL_P3_73_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE7)
5405 #define REG_DVI_DTOP_DUAL_P3_74_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE8)
5406 #define REG_DVI_DTOP_DUAL_P3_74_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xE9)
5407 #define REG_DVI_DTOP_DUAL_P3_75_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEA)
5408 #define REG_DVI_DTOP_DUAL_P3_75_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEB)
5409 #define REG_DVI_DTOP_DUAL_P3_76_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEC)
5410 #define REG_DVI_DTOP_DUAL_P3_76_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xED)
5411 #define REG_DVI_DTOP_DUAL_P3_77_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEE)
5412 #define REG_DVI_DTOP_DUAL_P3_77_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xEF)
5413 #define REG_DVI_DTOP_DUAL_P3_78_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF0)
5414 #define REG_DVI_DTOP_DUAL_P3_78_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF1)
5415 #define REG_DVI_DTOP_DUAL_P3_79_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF2)
5416 #define REG_DVI_DTOP_DUAL_P3_79_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF3)
5417 #define REG_DVI_DTOP_DUAL_P3_7A_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF4)
5418 #define REG_DVI_DTOP_DUAL_P3_7A_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF5)
5419 #define REG_DVI_DTOP_DUAL_P3_7B_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF6)
5420 #define REG_DVI_DTOP_DUAL_P3_7B_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF7)
5421 #define REG_DVI_DTOP_DUAL_P3_7C_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF8)
5422 #define REG_DVI_DTOP_DUAL_P3_7C_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xF9)
5423 #define REG_DVI_DTOP_DUAL_P3_7D_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFA)
5424 #define REG_DVI_DTOP_DUAL_P3_7D_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFB)
5425 #define REG_DVI_DTOP_DUAL_P3_7E_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFC)
5426 #define REG_DVI_DTOP_DUAL_P3_7E_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFD)
5427 #define REG_DVI_DTOP_DUAL_P3_7F_L       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFE)
5428 #define REG_DVI_DTOP_DUAL_P3_7F_H       (REG_DVI_DTOP_DUAL_P3_BASE + 0xFF)
5429 
5430 // DVI_RSV_DUAL_P3
5431 #define REG_DVI_RSV_DUAL_P3_00_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x00)
5432 #define REG_DVI_RSV_DUAL_P3_00_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x01)
5433 #define REG_DVI_RSV_DUAL_P3_01_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x02)
5434 #define REG_DVI_RSV_DUAL_P3_01_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x03)
5435 #define REG_DVI_RSV_DUAL_P3_02_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x04)
5436 #define REG_DVI_RSV_DUAL_P3_02_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x05)
5437 #define REG_DVI_RSV_DUAL_P3_03_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x06)
5438 #define REG_DVI_RSV_DUAL_P3_03_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x07)
5439 #define REG_DVI_RSV_DUAL_P3_04_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x08)
5440 #define REG_DVI_RSV_DUAL_P3_04_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x09)
5441 #define REG_DVI_RSV_DUAL_P3_05_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x0A)
5442 #define REG_DVI_RSV_DUAL_P3_05_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x0B)
5443 #define REG_DVI_RSV_DUAL_P3_06_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x0C)
5444 #define REG_DVI_RSV_DUAL_P3_06_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x0D)
5445 #define REG_DVI_RSV_DUAL_P3_07_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x0E)
5446 #define REG_DVI_RSV_DUAL_P3_07_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x0F)
5447 #define REG_DVI_RSV_DUAL_P3_08_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x10)
5448 #define REG_DVI_RSV_DUAL_P3_08_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x11)
5449 #define REG_DVI_RSV_DUAL_P3_09_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x12)
5450 #define REG_DVI_RSV_DUAL_P3_09_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x13)
5451 #define REG_DVI_RSV_DUAL_P3_0A_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x14)
5452 #define REG_DVI_RSV_DUAL_P3_0A_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x15)
5453 #define REG_DVI_RSV_DUAL_P3_0B_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x16)
5454 #define REG_DVI_RSV_DUAL_P3_0B_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x17)
5455 #define REG_DVI_RSV_DUAL_P3_0C_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x18)
5456 #define REG_DVI_RSV_DUAL_P3_0C_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x19)
5457 #define REG_DVI_RSV_DUAL_P3_0D_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x1A)
5458 #define REG_DVI_RSV_DUAL_P3_0D_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x1B)
5459 #define REG_DVI_RSV_DUAL_P3_0E_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x1C)
5460 #define REG_DVI_RSV_DUAL_P3_0E_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x1D)
5461 #define REG_DVI_RSV_DUAL_P3_0F_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x1E)
5462 #define REG_DVI_RSV_DUAL_P3_0F_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x1F)
5463 #define REG_DVI_RSV_DUAL_P3_10_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x20)
5464 #define REG_DVI_RSV_DUAL_P3_10_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x21)
5465 #define REG_DVI_RSV_DUAL_P3_11_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x22)
5466 #define REG_DVI_RSV_DUAL_P3_11_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x23)
5467 #define REG_DVI_RSV_DUAL_P3_12_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x24)
5468 #define REG_DVI_RSV_DUAL_P3_12_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x25)
5469 #define REG_DVI_RSV_DUAL_P3_13_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x26)
5470 #define REG_DVI_RSV_DUAL_P3_13_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x27)
5471 #define REG_DVI_RSV_DUAL_P3_14_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x28)
5472 #define REG_DVI_RSV_DUAL_P3_14_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x29)
5473 #define REG_DVI_RSV_DUAL_P3_15_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x2A)
5474 #define REG_DVI_RSV_DUAL_P3_15_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x2B)
5475 #define REG_DVI_RSV_DUAL_P3_16_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x2C)
5476 #define REG_DVI_RSV_DUAL_P3_16_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x2D)
5477 #define REG_DVI_RSV_DUAL_P3_17_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x2E)
5478 #define REG_DVI_RSV_DUAL_P3_17_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x2F)
5479 #define REG_DVI_RSV_DUAL_P3_18_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x30)
5480 #define REG_DVI_RSV_DUAL_P3_18_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x31)
5481 #define REG_DVI_RSV_DUAL_P3_19_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x32)
5482 #define REG_DVI_RSV_DUAL_P3_19_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x33)
5483 #define REG_DVI_RSV_DUAL_P3_1A_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x34)
5484 #define REG_DVI_RSV_DUAL_P3_1A_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x35)
5485 #define REG_DVI_RSV_DUAL_P3_1B_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x36)
5486 #define REG_DVI_RSV_DUAL_P3_1B_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x37)
5487 #define REG_DVI_RSV_DUAL_P3_1C_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x38)
5488 #define REG_DVI_RSV_DUAL_P3_1C_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x39)
5489 #define REG_DVI_RSV_DUAL_P3_1D_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x3A)
5490 #define REG_DVI_RSV_DUAL_P3_1D_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x3B)
5491 #define REG_DVI_RSV_DUAL_P3_1E_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x3C)
5492 #define REG_DVI_RSV_DUAL_P3_1E_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x3D)
5493 #define REG_DVI_RSV_DUAL_P3_1F_L       (REG_DVI_RSV_DUAL_P3_BASE + 0x3E)
5494 #define REG_DVI_RSV_DUAL_P3_1F_H       (REG_DVI_RSV_DUAL_P3_BASE + 0x3F)
5495 
5496 // HDCP_DUAL_P3
5497 #define REG_HDCP_DUAL_P3_00_L       (REG_HDCP_DUAL_P3_BASE + 0x00)
5498 #define REG_HDCP_DUAL_P3_00_H       (REG_HDCP_DUAL_P3_BASE + 0x01)
5499 #define REG_HDCP_DUAL_P3_01_L       (REG_HDCP_DUAL_P3_BASE + 0x02)
5500 #define REG_HDCP_DUAL_P3_01_H       (REG_HDCP_DUAL_P3_BASE + 0x03)
5501 #define REG_HDCP_DUAL_P3_02_L       (REG_HDCP_DUAL_P3_BASE + 0x04)
5502 #define REG_HDCP_DUAL_P3_02_H       (REG_HDCP_DUAL_P3_BASE + 0x05)
5503 #define REG_HDCP_DUAL_P3_03_L       (REG_HDCP_DUAL_P3_BASE + 0x06)
5504 #define REG_HDCP_DUAL_P3_03_H       (REG_HDCP_DUAL_P3_BASE + 0x07)
5505 #define REG_HDCP_DUAL_P3_04_L       (REG_HDCP_DUAL_P3_BASE + 0x08)
5506 #define REG_HDCP_DUAL_P3_04_H       (REG_HDCP_DUAL_P3_BASE + 0x09)
5507 #define REG_HDCP_DUAL_P3_05_L       (REG_HDCP_DUAL_P3_BASE + 0x0A)
5508 #define REG_HDCP_DUAL_P3_05_H       (REG_HDCP_DUAL_P3_BASE + 0x0B)
5509 #define REG_HDCP_DUAL_P3_06_L       (REG_HDCP_DUAL_P3_BASE + 0x0C)
5510 #define REG_HDCP_DUAL_P3_06_H       (REG_HDCP_DUAL_P3_BASE + 0x0D)
5511 #define REG_HDCP_DUAL_P3_07_L       (REG_HDCP_DUAL_P3_BASE + 0x0E)
5512 #define REG_HDCP_DUAL_P3_07_H       (REG_HDCP_DUAL_P3_BASE + 0x0F)
5513 #define REG_HDCP_DUAL_P3_08_L       (REG_HDCP_DUAL_P3_BASE + 0x10)
5514 #define REG_HDCP_DUAL_P3_08_H       (REG_HDCP_DUAL_P3_BASE + 0x11)
5515 #define REG_HDCP_DUAL_P3_09_L       (REG_HDCP_DUAL_P3_BASE + 0x12)
5516 #define REG_HDCP_DUAL_P3_09_H       (REG_HDCP_DUAL_P3_BASE + 0x13)
5517 #define REG_HDCP_DUAL_P3_0A_L       (REG_HDCP_DUAL_P3_BASE + 0x14)
5518 #define REG_HDCP_DUAL_P3_0A_H       (REG_HDCP_DUAL_P3_BASE + 0x15)
5519 #define REG_HDCP_DUAL_P3_0B_L       (REG_HDCP_DUAL_P3_BASE + 0x16)
5520 #define REG_HDCP_DUAL_P3_0B_H       (REG_HDCP_DUAL_P3_BASE + 0x17)
5521 #define REG_HDCP_DUAL_P3_0C_L       (REG_HDCP_DUAL_P3_BASE + 0x18)
5522 #define REG_HDCP_DUAL_P3_0C_H       (REG_HDCP_DUAL_P3_BASE + 0x19)
5523 #define REG_HDCP_DUAL_P3_0D_L       (REG_HDCP_DUAL_P3_BASE + 0x1A)
5524 #define REG_HDCP_DUAL_P3_0D_H       (REG_HDCP_DUAL_P3_BASE + 0x1B)
5525 #define REG_HDCP_DUAL_P3_0E_L       (REG_HDCP_DUAL_P3_BASE + 0x1C)
5526 #define REG_HDCP_DUAL_P3_0E_H       (REG_HDCP_DUAL_P3_BASE + 0x1D)
5527 #define REG_HDCP_DUAL_P3_0F_L       (REG_HDCP_DUAL_P3_BASE + 0x1E)
5528 #define REG_HDCP_DUAL_P3_0F_H       (REG_HDCP_DUAL_P3_BASE + 0x1F)
5529 #define REG_HDCP_DUAL_P3_10_L       (REG_HDCP_DUAL_P3_BASE + 0x20)
5530 #define REG_HDCP_DUAL_P3_10_H       (REG_HDCP_DUAL_P3_BASE + 0x21)
5531 #define REG_HDCP_DUAL_P3_11_L       (REG_HDCP_DUAL_P3_BASE + 0x22)
5532 #define REG_HDCP_DUAL_P3_11_H       (REG_HDCP_DUAL_P3_BASE + 0x23)
5533 #define REG_HDCP_DUAL_P3_12_L       (REG_HDCP_DUAL_P3_BASE + 0x24)
5534 #define REG_HDCP_DUAL_P3_12_H       (REG_HDCP_DUAL_P3_BASE + 0x25)
5535 #define REG_HDCP_DUAL_P3_13_L       (REG_HDCP_DUAL_P3_BASE + 0x26)
5536 #define REG_HDCP_DUAL_P3_13_H       (REG_HDCP_DUAL_P3_BASE + 0x27)
5537 #define REG_HDCP_DUAL_P3_14_L       (REG_HDCP_DUAL_P3_BASE + 0x28)
5538 #define REG_HDCP_DUAL_P3_14_H       (REG_HDCP_DUAL_P3_BASE + 0x29)
5539 #define REG_HDCP_DUAL_P3_15_L       (REG_HDCP_DUAL_P3_BASE + 0x2A)
5540 #define REG_HDCP_DUAL_P3_15_H       (REG_HDCP_DUAL_P3_BASE + 0x2B)
5541 #define REG_HDCP_DUAL_P3_16_L       (REG_HDCP_DUAL_P3_BASE + 0x2C)
5542 #define REG_HDCP_DUAL_P3_16_H       (REG_HDCP_DUAL_P3_BASE + 0x2D)
5543 #define REG_HDCP_DUAL_P3_17_L       (REG_HDCP_DUAL_P3_BASE + 0x2E)
5544 #define REG_HDCP_DUAL_P3_17_H       (REG_HDCP_DUAL_P3_BASE + 0x2F)
5545 #define REG_HDCP_DUAL_P3_18_L       (REG_HDCP_DUAL_P3_BASE + 0x30)
5546 #define REG_HDCP_DUAL_P3_18_H       (REG_HDCP_DUAL_P3_BASE + 0x31)
5547 #define REG_HDCP_DUAL_P3_19_L       (REG_HDCP_DUAL_P3_BASE + 0x32)
5548 #define REG_HDCP_DUAL_P3_19_H       (REG_HDCP_DUAL_P3_BASE + 0x33)
5549 #define REG_HDCP_DUAL_P3_1A_L       (REG_HDCP_DUAL_P3_BASE + 0x34)
5550 #define REG_HDCP_DUAL_P3_1A_H       (REG_HDCP_DUAL_P3_BASE + 0x35)
5551 #define REG_HDCP_DUAL_P3_1B_L       (REG_HDCP_DUAL_P3_BASE + 0x36)
5552 #define REG_HDCP_DUAL_P3_1B_H       (REG_HDCP_DUAL_P3_BASE + 0x37)
5553 #define REG_HDCP_DUAL_P3_1C_L       (REG_HDCP_DUAL_P3_BASE + 0x38)
5554 #define REG_HDCP_DUAL_P3_1C_H       (REG_HDCP_DUAL_P3_BASE + 0x39)
5555 #define REG_HDCP_DUAL_P3_1D_L       (REG_HDCP_DUAL_P3_BASE + 0x3A)
5556 #define REG_HDCP_DUAL_P3_1D_H       (REG_HDCP_DUAL_P3_BASE + 0x3B)
5557 #define REG_HDCP_DUAL_P3_1E_L       (REG_HDCP_DUAL_P3_BASE + 0x3C)
5558 #define REG_HDCP_DUAL_P3_1E_H       (REG_HDCP_DUAL_P3_BASE + 0x3D)
5559 #define REG_HDCP_DUAL_P3_1F_L       (REG_HDCP_DUAL_P3_BASE + 0x3E)
5560 #define REG_HDCP_DUAL_P3_1F_H       (REG_HDCP_DUAL_P3_BASE + 0x3F)
5561 #define REG_HDCP_DUAL_P3_20_L       (REG_HDCP_DUAL_P3_BASE + 0x40)
5562 #define REG_HDCP_DUAL_P3_20_H       (REG_HDCP_DUAL_P3_BASE + 0x41)
5563 #define REG_HDCP_DUAL_P3_21_L       (REG_HDCP_DUAL_P3_BASE + 0x42)
5564 #define REG_HDCP_DUAL_P3_21_H       (REG_HDCP_DUAL_P3_BASE + 0x43)
5565 #define REG_HDCP_DUAL_P3_22_L       (REG_HDCP_DUAL_P3_BASE + 0x44)
5566 #define REG_HDCP_DUAL_P3_22_H       (REG_HDCP_DUAL_P3_BASE + 0x45)
5567 #define REG_HDCP_DUAL_P3_23_L       (REG_HDCP_DUAL_P3_BASE + 0x46)
5568 #define REG_HDCP_DUAL_P3_23_H       (REG_HDCP_DUAL_P3_BASE + 0x47)
5569 #define REG_HDCP_DUAL_P3_24_L       (REG_HDCP_DUAL_P3_BASE + 0x48)
5570 #define REG_HDCP_DUAL_P3_24_H       (REG_HDCP_DUAL_P3_BASE + 0x49)
5571 #define REG_HDCP_DUAL_P3_25_L       (REG_HDCP_DUAL_P3_BASE + 0x4A)
5572 #define REG_HDCP_DUAL_P3_25_H       (REG_HDCP_DUAL_P3_BASE + 0x4B)
5573 #define REG_HDCP_DUAL_P3_26_L       (REG_HDCP_DUAL_P3_BASE + 0x4C)
5574 #define REG_HDCP_DUAL_P3_26_H       (REG_HDCP_DUAL_P3_BASE + 0x4D)
5575 #define REG_HDCP_DUAL_P3_27_L       (REG_HDCP_DUAL_P3_BASE + 0x4E)
5576 #define REG_HDCP_DUAL_P3_27_H       (REG_HDCP_DUAL_P3_BASE + 0x4F)
5577 #define REG_HDCP_DUAL_P3_28_L       (REG_HDCP_DUAL_P3_BASE + 0x50)
5578 #define REG_HDCP_DUAL_P3_28_H       (REG_HDCP_DUAL_P3_BASE + 0x51)
5579 #define REG_HDCP_DUAL_P3_29_L       (REG_HDCP_DUAL_P3_BASE + 0x52)
5580 #define REG_HDCP_DUAL_P3_29_H       (REG_HDCP_DUAL_P3_BASE + 0x53)
5581 #define REG_HDCP_DUAL_P3_2A_L       (REG_HDCP_DUAL_P3_BASE + 0x54)
5582 #define REG_HDCP_DUAL_P3_2A_H       (REG_HDCP_DUAL_P3_BASE + 0x55)
5583 #define REG_HDCP_DUAL_P3_2B_L       (REG_HDCP_DUAL_P3_BASE + 0x56)
5584 #define REG_HDCP_DUAL_P3_2B_H       (REG_HDCP_DUAL_P3_BASE + 0x57)
5585 #define REG_HDCP_DUAL_P3_2C_L       (REG_HDCP_DUAL_P3_BASE + 0x58)
5586 #define REG_HDCP_DUAL_P3_2C_H       (REG_HDCP_DUAL_P3_BASE + 0x59)
5587 #define REG_HDCP_DUAL_P3_2D_L       (REG_HDCP_DUAL_P3_BASE + 0x5A)
5588 #define REG_HDCP_DUAL_P3_2D_H       (REG_HDCP_DUAL_P3_BASE + 0x5B)
5589 #define REG_HDCP_DUAL_P3_2E_L       (REG_HDCP_DUAL_P3_BASE + 0x5C)
5590 #define REG_HDCP_DUAL_P3_2E_H       (REG_HDCP_DUAL_P3_BASE + 0x5D)
5591 #define REG_HDCP_DUAL_P3_2F_L       (REG_HDCP_DUAL_P3_BASE + 0x5E)
5592 #define REG_HDCP_DUAL_P3_2F_H       (REG_HDCP_DUAL_P3_BASE + 0x5F)
5593 #define REG_HDCP_DUAL_P3_30_L       (REG_HDCP_DUAL_P3_BASE + 0x60)
5594 #define REG_HDCP_DUAL_P3_30_H       (REG_HDCP_DUAL_P3_BASE + 0x61)
5595 #define REG_HDCP_DUAL_P3_31_L       (REG_HDCP_DUAL_P3_BASE + 0x62)
5596 #define REG_HDCP_DUAL_P3_31_H       (REG_HDCP_DUAL_P3_BASE + 0x63)
5597 #define REG_HDCP_DUAL_P3_32_L       (REG_HDCP_DUAL_P3_BASE + 0x64)
5598 #define REG_HDCP_DUAL_P3_32_H       (REG_HDCP_DUAL_P3_BASE + 0x65)
5599 #define REG_HDCP_DUAL_P3_33_L       (REG_HDCP_DUAL_P3_BASE + 0x66)
5600 #define REG_HDCP_DUAL_P3_33_H       (REG_HDCP_DUAL_P3_BASE + 0x67)
5601 #define REG_HDCP_DUAL_P3_34_L       (REG_HDCP_DUAL_P3_BASE + 0x68)
5602 #define REG_HDCP_DUAL_P3_34_H       (REG_HDCP_DUAL_P3_BASE + 0x69)
5603 #define REG_HDCP_DUAL_P3_35_L       (REG_HDCP_DUAL_P3_BASE + 0x6A)
5604 #define REG_HDCP_DUAL_P3_35_H       (REG_HDCP_DUAL_P3_BASE + 0x6B)
5605 #define REG_HDCP_DUAL_P3_36_L       (REG_HDCP_DUAL_P3_BASE + 0x6C)
5606 #define REG_HDCP_DUAL_P3_36_H       (REG_HDCP_DUAL_P3_BASE + 0x6D)
5607 #define REG_HDCP_DUAL_P3_37_L       (REG_HDCP_DUAL_P3_BASE + 0x6E)
5608 #define REG_HDCP_DUAL_P3_37_H       (REG_HDCP_DUAL_P3_BASE + 0x6F)
5609 #define REG_HDCP_DUAL_P3_38_L       (REG_HDCP_DUAL_P3_BASE + 0x70)
5610 #define REG_HDCP_DUAL_P3_38_H       (REG_HDCP_DUAL_P3_BASE + 0x71)
5611 #define REG_HDCP_DUAL_P3_39_L       (REG_HDCP_DUAL_P3_BASE + 0x72)
5612 #define REG_HDCP_DUAL_P3_39_H       (REG_HDCP_DUAL_P3_BASE + 0x73)
5613 #define REG_HDCP_DUAL_P3_3A_L       (REG_HDCP_DUAL_P3_BASE + 0x74)
5614 #define REG_HDCP_DUAL_P3_3A_H       (REG_HDCP_DUAL_P3_BASE + 0x75)
5615 #define REG_HDCP_DUAL_P3_3B_L       (REG_HDCP_DUAL_P3_BASE + 0x76)
5616 #define REG_HDCP_DUAL_P3_3B_H       (REG_HDCP_DUAL_P3_BASE + 0x77)
5617 #define REG_HDCP_DUAL_P3_3C_L       (REG_HDCP_DUAL_P3_BASE + 0x78)
5618 #define REG_HDCP_DUAL_P3_3C_H       (REG_HDCP_DUAL_P3_BASE + 0x79)
5619 #define REG_HDCP_DUAL_P3_3D_L       (REG_HDCP_DUAL_P3_BASE + 0x7A)
5620 #define REG_HDCP_DUAL_P3_3D_H       (REG_HDCP_DUAL_P3_BASE + 0x7B)
5621 #define REG_HDCP_DUAL_P3_3E_L       (REG_HDCP_DUAL_P3_BASE + 0x7C)
5622 #define REG_HDCP_DUAL_P3_3E_H       (REG_HDCP_DUAL_P3_BASE + 0x7D)
5623 #define REG_HDCP_DUAL_P3_3F_L       (REG_HDCP_DUAL_P3_BASE + 0x7E)
5624 #define REG_HDCP_DUAL_P3_3F_H       (REG_HDCP_DUAL_P3_BASE + 0x7F)
5625 #define REG_HDCP_DUAL_P3_40_L       (REG_HDCP_DUAL_P3_BASE + 0x80)
5626 #define REG_HDCP_DUAL_P3_40_H       (REG_HDCP_DUAL_P3_BASE + 0x81)
5627 #define REG_HDCP_DUAL_P3_41_L       (REG_HDCP_DUAL_P3_BASE + 0x82)
5628 #define REG_HDCP_DUAL_P3_41_H       (REG_HDCP_DUAL_P3_BASE + 0x83)
5629 #define REG_HDCP_DUAL_P3_42_L       (REG_HDCP_DUAL_P3_BASE + 0x84)
5630 #define REG_HDCP_DUAL_P3_42_H       (REG_HDCP_DUAL_P3_BASE + 0x85)
5631 #define REG_HDCP_DUAL_P3_43_L       (REG_HDCP_DUAL_P3_BASE + 0x86)
5632 #define REG_HDCP_DUAL_P3_43_H       (REG_HDCP_DUAL_P3_BASE + 0x87)
5633 #define REG_HDCP_DUAL_P3_44_L       (REG_HDCP_DUAL_P3_BASE + 0x88)
5634 #define REG_HDCP_DUAL_P3_44_H       (REG_HDCP_DUAL_P3_BASE + 0x89)
5635 #define REG_HDCP_DUAL_P3_45_L       (REG_HDCP_DUAL_P3_BASE + 0x8A)
5636 #define REG_HDCP_DUAL_P3_45_H       (REG_HDCP_DUAL_P3_BASE + 0x8B)
5637 #define REG_HDCP_DUAL_P3_46_L       (REG_HDCP_DUAL_P3_BASE + 0x8C)
5638 #define REG_HDCP_DUAL_P3_46_H       (REG_HDCP_DUAL_P3_BASE + 0x8D)
5639 #define REG_HDCP_DUAL_P3_47_L       (REG_HDCP_DUAL_P3_BASE + 0x8E)
5640 #define REG_HDCP_DUAL_P3_47_H       (REG_HDCP_DUAL_P3_BASE + 0x8F)
5641 #define REG_HDCP_DUAL_P3_48_L       (REG_HDCP_DUAL_P3_BASE + 0x90)
5642 #define REG_HDCP_DUAL_P3_48_H       (REG_HDCP_DUAL_P3_BASE + 0x91)
5643 #define REG_HDCP_DUAL_P3_49_L       (REG_HDCP_DUAL_P3_BASE + 0x92)
5644 #define REG_HDCP_DUAL_P3_49_H       (REG_HDCP_DUAL_P3_BASE + 0x93)
5645 #define REG_HDCP_DUAL_P3_4A_L       (REG_HDCP_DUAL_P3_BASE + 0x94)
5646 #define REG_HDCP_DUAL_P3_4A_H       (REG_HDCP_DUAL_P3_BASE + 0x95)
5647 #define REG_HDCP_DUAL_P3_4B_L       (REG_HDCP_DUAL_P3_BASE + 0x96)
5648 #define REG_HDCP_DUAL_P3_4B_H       (REG_HDCP_DUAL_P3_BASE + 0x97)
5649 #define REG_HDCP_DUAL_P3_4C_L       (REG_HDCP_DUAL_P3_BASE + 0x98)
5650 #define REG_HDCP_DUAL_P3_4C_H       (REG_HDCP_DUAL_P3_BASE + 0x99)
5651 #define REG_HDCP_DUAL_P3_4D_L       (REG_HDCP_DUAL_P3_BASE + 0x9A)
5652 #define REG_HDCP_DUAL_P3_4D_H       (REG_HDCP_DUAL_P3_BASE + 0x9B)
5653 #define REG_HDCP_DUAL_P3_4E_L       (REG_HDCP_DUAL_P3_BASE + 0x9C)
5654 #define REG_HDCP_DUAL_P3_4E_H       (REG_HDCP_DUAL_P3_BASE + 0x9D)
5655 #define REG_HDCP_DUAL_P3_4F_L       (REG_HDCP_DUAL_P3_BASE + 0x9E)
5656 #define REG_HDCP_DUAL_P3_4F_H       (REG_HDCP_DUAL_P3_BASE + 0x9F)
5657 #define REG_HDCP_DUAL_P3_50_L       (REG_HDCP_DUAL_P3_BASE + 0xA0)
5658 #define REG_HDCP_DUAL_P3_50_H       (REG_HDCP_DUAL_P3_BASE + 0xA1)
5659 #define REG_HDCP_DUAL_P3_51_L       (REG_HDCP_DUAL_P3_BASE + 0xA2)
5660 #define REG_HDCP_DUAL_P3_51_H       (REG_HDCP_DUAL_P3_BASE + 0xA3)
5661 #define REG_HDCP_DUAL_P3_52_L       (REG_HDCP_DUAL_P3_BASE + 0xA4)
5662 #define REG_HDCP_DUAL_P3_52_H       (REG_HDCP_DUAL_P3_BASE + 0xA5)
5663 #define REG_HDCP_DUAL_P3_53_L       (REG_HDCP_DUAL_P3_BASE + 0xA6)
5664 #define REG_HDCP_DUAL_P3_53_H       (REG_HDCP_DUAL_P3_BASE + 0xA7)
5665 #define REG_HDCP_DUAL_P3_54_L       (REG_HDCP_DUAL_P3_BASE + 0xA8)
5666 #define REG_HDCP_DUAL_P3_54_H       (REG_HDCP_DUAL_P3_BASE + 0xA9)
5667 #define REG_HDCP_DUAL_P3_55_L       (REG_HDCP_DUAL_P3_BASE + 0xAA)
5668 #define REG_HDCP_DUAL_P3_55_H       (REG_HDCP_DUAL_P3_BASE + 0xAB)
5669 #define REG_HDCP_DUAL_P3_56_L       (REG_HDCP_DUAL_P3_BASE + 0xAC)
5670 #define REG_HDCP_DUAL_P3_56_H       (REG_HDCP_DUAL_P3_BASE + 0xAD)
5671 #define REG_HDCP_DUAL_P3_57_L       (REG_HDCP_DUAL_P3_BASE + 0xAE)
5672 #define REG_HDCP_DUAL_P3_57_H       (REG_HDCP_DUAL_P3_BASE + 0xAF)
5673 #define REG_HDCP_DUAL_P3_58_L       (REG_HDCP_DUAL_P3_BASE + 0xB0)
5674 #define REG_HDCP_DUAL_P3_58_H       (REG_HDCP_DUAL_P3_BASE + 0xB1)
5675 #define REG_HDCP_DUAL_P3_59_L       (REG_HDCP_DUAL_P3_BASE + 0xB2)
5676 #define REG_HDCP_DUAL_P3_59_H       (REG_HDCP_DUAL_P3_BASE + 0xB3)
5677 #define REG_HDCP_DUAL_P3_5A_L       (REG_HDCP_DUAL_P3_BASE + 0xB4)
5678 #define REG_HDCP_DUAL_P3_5A_H       (REG_HDCP_DUAL_P3_BASE + 0xB5)
5679 #define REG_HDCP_DUAL_P3_5B_L       (REG_HDCP_DUAL_P3_BASE + 0xB6)
5680 #define REG_HDCP_DUAL_P3_5B_H       (REG_HDCP_DUAL_P3_BASE + 0xB7)
5681 #define REG_HDCP_DUAL_P3_5C_L       (REG_HDCP_DUAL_P3_BASE + 0xB8)
5682 #define REG_HDCP_DUAL_P3_5C_H       (REG_HDCP_DUAL_P3_BASE + 0xB9)
5683 #define REG_HDCP_DUAL_P3_5D_L       (REG_HDCP_DUAL_P3_BASE + 0xBA)
5684 #define REG_HDCP_DUAL_P3_5D_H       (REG_HDCP_DUAL_P3_BASE + 0xBB)
5685 #define REG_HDCP_DUAL_P3_5E_L       (REG_HDCP_DUAL_P3_BASE + 0xBC)
5686 #define REG_HDCP_DUAL_P3_5E_H       (REG_HDCP_DUAL_P3_BASE + 0xBD)
5687 #define REG_HDCP_DUAL_P3_5F_L       (REG_HDCP_DUAL_P3_BASE + 0xBE)
5688 #define REG_HDCP_DUAL_P3_5F_H       (REG_HDCP_DUAL_P3_BASE + 0xBF)
5689 #define REG_HDCP_DUAL_P3_60_L       (REG_HDCP_DUAL_P3_BASE + 0xC0)
5690 #define REG_HDCP_DUAL_P3_60_H       (REG_HDCP_DUAL_P3_BASE + 0xC1)
5691 #define REG_HDCP_DUAL_P3_61_L       (REG_HDCP_DUAL_P3_BASE + 0xC2)
5692 #define REG_HDCP_DUAL_P3_61_H       (REG_HDCP_DUAL_P3_BASE + 0xC3)
5693 #define REG_HDCP_DUAL_P3_62_L       (REG_HDCP_DUAL_P3_BASE + 0xC4)
5694 #define REG_HDCP_DUAL_P3_62_H       (REG_HDCP_DUAL_P3_BASE + 0xC5)
5695 #define REG_HDCP_DUAL_P3_63_L       (REG_HDCP_DUAL_P3_BASE + 0xC6)
5696 #define REG_HDCP_DUAL_P3_63_H       (REG_HDCP_DUAL_P3_BASE + 0xC7)
5697 #define REG_HDCP_DUAL_P3_64_L       (REG_HDCP_DUAL_P3_BASE + 0xC8)
5698 #define REG_HDCP_DUAL_P3_64_H       (REG_HDCP_DUAL_P3_BASE + 0xC9)
5699 #define REG_HDCP_DUAL_P3_65_L       (REG_HDCP_DUAL_P3_BASE + 0xCA)
5700 #define REG_HDCP_DUAL_P3_65_H       (REG_HDCP_DUAL_P3_BASE + 0xCB)
5701 #define REG_HDCP_DUAL_P3_66_L       (REG_HDCP_DUAL_P3_BASE + 0xCC)
5702 #define REG_HDCP_DUAL_P3_66_H       (REG_HDCP_DUAL_P3_BASE + 0xCD)
5703 #define REG_HDCP_DUAL_P3_67_L       (REG_HDCP_DUAL_P3_BASE + 0xCE)
5704 #define REG_HDCP_DUAL_P3_67_H       (REG_HDCP_DUAL_P3_BASE + 0xCF)
5705 #define REG_HDCP_DUAL_P3_68_L       (REG_HDCP_DUAL_P3_BASE + 0xD0)
5706 #define REG_HDCP_DUAL_P3_68_H       (REG_HDCP_DUAL_P3_BASE + 0xD1)
5707 
5708 //=============================================================
5709 
5710 // HDMI_DUAL_0
5711 #define REG_HDMI_DUAL_0_00_L       (REG_HDMI_DUAL_0_BASE + 0x00)
5712 #define REG_HDMI_DUAL_0_00_H       (REG_HDMI_DUAL_0_BASE + 0x01)
5713 #define REG_HDMI_DUAL_0_01_L       (REG_HDMI_DUAL_0_BASE + 0x02)
5714 #define REG_HDMI_DUAL_0_01_H       (REG_HDMI_DUAL_0_BASE + 0x03)
5715 #define REG_HDMI_DUAL_0_02_L       (REG_HDMI_DUAL_0_BASE + 0x04)
5716 #define REG_HDMI_DUAL_0_02_H       (REG_HDMI_DUAL_0_BASE + 0x05)
5717 #define REG_HDMI_DUAL_0_03_L       (REG_HDMI_DUAL_0_BASE + 0x06)
5718 #define REG_HDMI_DUAL_0_03_H       (REG_HDMI_DUAL_0_BASE + 0x07)
5719 #define REG_HDMI_DUAL_0_04_L       (REG_HDMI_DUAL_0_BASE + 0x08)
5720 #define REG_HDMI_DUAL_0_04_H       (REG_HDMI_DUAL_0_BASE + 0x09)
5721 #define REG_HDMI_DUAL_0_05_L       (REG_HDMI_DUAL_0_BASE + 0x0A)
5722 #define REG_HDMI_DUAL_0_05_H       (REG_HDMI_DUAL_0_BASE + 0x0B)
5723 #define REG_HDMI_DUAL_0_06_L       (REG_HDMI_DUAL_0_BASE + 0x0C)
5724 #define REG_HDMI_DUAL_0_06_H       (REG_HDMI_DUAL_0_BASE + 0x0D)
5725 #define REG_HDMI_DUAL_0_07_L       (REG_HDMI_DUAL_0_BASE + 0x0E)
5726 #define REG_HDMI_DUAL_0_07_H       (REG_HDMI_DUAL_0_BASE + 0x0F)
5727 #define REG_HDMI_DUAL_0_08_L       (REG_HDMI_DUAL_0_BASE + 0x10)
5728 #define REG_HDMI_DUAL_0_08_H       (REG_HDMI_DUAL_0_BASE + 0x11)
5729 #define REG_HDMI_DUAL_0_09_L       (REG_HDMI_DUAL_0_BASE + 0x12)
5730 #define REG_HDMI_DUAL_0_09_H       (REG_HDMI_DUAL_0_BASE + 0x13)
5731 #define REG_HDMI_DUAL_0_0A_L       (REG_HDMI_DUAL_0_BASE + 0x14)
5732 #define REG_HDMI_DUAL_0_0A_H       (REG_HDMI_DUAL_0_BASE + 0x15)
5733 #define REG_HDMI_DUAL_0_0B_L       (REG_HDMI_DUAL_0_BASE + 0x16)
5734 #define REG_HDMI_DUAL_0_0B_H       (REG_HDMI_DUAL_0_BASE + 0x17)
5735 #define REG_HDMI_DUAL_0_0C_L       (REG_HDMI_DUAL_0_BASE + 0x18)
5736 #define REG_HDMI_DUAL_0_0C_H       (REG_HDMI_DUAL_0_BASE + 0x19)
5737 #define REG_HDMI_DUAL_0_0D_L       (REG_HDMI_DUAL_0_BASE + 0x1A)
5738 #define REG_HDMI_DUAL_0_0D_H       (REG_HDMI_DUAL_0_BASE + 0x1B)
5739 #define REG_HDMI_DUAL_0_0E_L       (REG_HDMI_DUAL_0_BASE + 0x1C)
5740 #define REG_HDMI_DUAL_0_0E_H       (REG_HDMI_DUAL_0_BASE + 0x1D)
5741 #define REG_HDMI_DUAL_0_0F_L       (REG_HDMI_DUAL_0_BASE + 0x1E)
5742 #define REG_HDMI_DUAL_0_0F_H       (REG_HDMI_DUAL_0_BASE + 0x1F)
5743 #define REG_HDMI_DUAL_0_10_L       (REG_HDMI_DUAL_0_BASE + 0x20)
5744 #define REG_HDMI_DUAL_0_10_H       (REG_HDMI_DUAL_0_BASE + 0x21)
5745 #define REG_HDMI_DUAL_0_11_L       (REG_HDMI_DUAL_0_BASE + 0x22)
5746 #define REG_HDMI_DUAL_0_11_H       (REG_HDMI_DUAL_0_BASE + 0x23)
5747 #define REG_HDMI_DUAL_0_12_L       (REG_HDMI_DUAL_0_BASE + 0x24)
5748 #define REG_HDMI_DUAL_0_12_H       (REG_HDMI_DUAL_0_BASE + 0x25)
5749 #define REG_HDMI_DUAL_0_13_L       (REG_HDMI_DUAL_0_BASE + 0x26)
5750 #define REG_HDMI_DUAL_0_13_H       (REG_HDMI_DUAL_0_BASE + 0x27)
5751 #define REG_HDMI_DUAL_0_14_L       (REG_HDMI_DUAL_0_BASE + 0x28)
5752 #define REG_HDMI_DUAL_0_14_H       (REG_HDMI_DUAL_0_BASE + 0x29)
5753 #define REG_HDMI_DUAL_0_15_L       (REG_HDMI_DUAL_0_BASE + 0x2A)
5754 #define REG_HDMI_DUAL_0_15_H       (REG_HDMI_DUAL_0_BASE + 0x2B)
5755 #define REG_HDMI_DUAL_0_16_L       (REG_HDMI_DUAL_0_BASE + 0x2C)
5756 #define REG_HDMI_DUAL_0_16_H       (REG_HDMI_DUAL_0_BASE + 0x2D)
5757 #define REG_HDMI_DUAL_0_17_L       (REG_HDMI_DUAL_0_BASE + 0x2E)
5758 #define REG_HDMI_DUAL_0_17_H       (REG_HDMI_DUAL_0_BASE + 0x2F)
5759 #define REG_HDMI_DUAL_0_18_L       (REG_HDMI_DUAL_0_BASE + 0x30)
5760 #define REG_HDMI_DUAL_0_18_H       (REG_HDMI_DUAL_0_BASE + 0x31)
5761 #define REG_HDMI_DUAL_0_19_L       (REG_HDMI_DUAL_0_BASE + 0x32)
5762 #define REG_HDMI_DUAL_0_19_H       (REG_HDMI_DUAL_0_BASE + 0x33)
5763 #define REG_HDMI_DUAL_0_1A_L       (REG_HDMI_DUAL_0_BASE + 0x34)
5764 #define REG_HDMI_DUAL_0_1A_H       (REG_HDMI_DUAL_0_BASE + 0x35)
5765 #define REG_HDMI_DUAL_0_1B_L       (REG_HDMI_DUAL_0_BASE + 0x36)
5766 #define REG_HDMI_DUAL_0_1B_H       (REG_HDMI_DUAL_0_BASE + 0x37)
5767 #define REG_HDMI_DUAL_0_1C_L       (REG_HDMI_DUAL_0_BASE + 0x38)
5768 #define REG_HDMI_DUAL_0_1C_H       (REG_HDMI_DUAL_0_BASE + 0x39)
5769 #define REG_HDMI_DUAL_0_1D_L       (REG_HDMI_DUAL_0_BASE + 0x3A)
5770 #define REG_HDMI_DUAL_0_1D_H       (REG_HDMI_DUAL_0_BASE + 0x3B)
5771 #define REG_HDMI_DUAL_0_1E_L       (REG_HDMI_DUAL_0_BASE + 0x3C)
5772 #define REG_HDMI_DUAL_0_1E_H       (REG_HDMI_DUAL_0_BASE + 0x3D)
5773 #define REG_HDMI_DUAL_0_1F_L       (REG_HDMI_DUAL_0_BASE + 0x3E)
5774 #define REG_HDMI_DUAL_0_1F_H       (REG_HDMI_DUAL_0_BASE + 0x3F)
5775 #define REG_HDMI_DUAL_0_20_L       (REG_HDMI_DUAL_0_BASE + 0x40)
5776 #define REG_HDMI_DUAL_0_20_H       (REG_HDMI_DUAL_0_BASE + 0x41)
5777 #define REG_HDMI_DUAL_0_21_L       (REG_HDMI_DUAL_0_BASE + 0x42)
5778 #define REG_HDMI_DUAL_0_21_H       (REG_HDMI_DUAL_0_BASE + 0x43)
5779 #define REG_HDMI_DUAL_0_22_L       (REG_HDMI_DUAL_0_BASE + 0x44)
5780 #define REG_HDMI_DUAL_0_22_H       (REG_HDMI_DUAL_0_BASE + 0x45)
5781 #define REG_HDMI_DUAL_0_23_L       (REG_HDMI_DUAL_0_BASE + 0x46)
5782 #define REG_HDMI_DUAL_0_23_H       (REG_HDMI_DUAL_0_BASE + 0x47)
5783 #define REG_HDMI_DUAL_0_24_L       (REG_HDMI_DUAL_0_BASE + 0x48)
5784 #define REG_HDMI_DUAL_0_24_H       (REG_HDMI_DUAL_0_BASE + 0x49)
5785 #define REG_HDMI_DUAL_0_25_L       (REG_HDMI_DUAL_0_BASE + 0x4A)
5786 #define REG_HDMI_DUAL_0_25_H       (REG_HDMI_DUAL_0_BASE + 0x4B)
5787 #define REG_HDMI_DUAL_0_26_L       (REG_HDMI_DUAL_0_BASE + 0x4C)
5788 #define REG_HDMI_DUAL_0_26_H       (REG_HDMI_DUAL_0_BASE + 0x4D)
5789 #define REG_HDMI_DUAL_0_27_L       (REG_HDMI_DUAL_0_BASE + 0x4E)
5790 #define REG_HDMI_DUAL_0_27_H       (REG_HDMI_DUAL_0_BASE + 0x4F)
5791 #define REG_HDMI_DUAL_0_28_L       (REG_HDMI_DUAL_0_BASE + 0x50)
5792 #define REG_HDMI_DUAL_0_28_H       (REG_HDMI_DUAL_0_BASE + 0x51)
5793 #define REG_HDMI_DUAL_0_29_L       (REG_HDMI_DUAL_0_BASE + 0x52)
5794 #define REG_HDMI_DUAL_0_29_H       (REG_HDMI_DUAL_0_BASE + 0x53)
5795 #define REG_HDMI_DUAL_0_2A_L       (REG_HDMI_DUAL_0_BASE + 0x54)
5796 #define REG_HDMI_DUAL_0_2A_H       (REG_HDMI_DUAL_0_BASE + 0x55)
5797 #define REG_HDMI_DUAL_0_2B_L       (REG_HDMI_DUAL_0_BASE + 0x56)
5798 #define REG_HDMI_DUAL_0_2B_H       (REG_HDMI_DUAL_0_BASE + 0x57)
5799 #define REG_HDMI_DUAL_0_2C_L       (REG_HDMI_DUAL_0_BASE + 0x58)
5800 #define REG_HDMI_DUAL_0_2C_H       (REG_HDMI_DUAL_0_BASE + 0x59)
5801 #define REG_HDMI_DUAL_0_2D_L       (REG_HDMI_DUAL_0_BASE + 0x5A)
5802 #define REG_HDMI_DUAL_0_2D_H       (REG_HDMI_DUAL_0_BASE + 0x5B)
5803 #define REG_HDMI_DUAL_0_2E_L       (REG_HDMI_DUAL_0_BASE + 0x5C)
5804 #define REG_HDMI_DUAL_0_2E_H       (REG_HDMI_DUAL_0_BASE + 0x5D)
5805 #define REG_HDMI_DUAL_0_2F_L       (REG_HDMI_DUAL_0_BASE + 0x5E)
5806 #define REG_HDMI_DUAL_0_2F_H       (REG_HDMI_DUAL_0_BASE + 0x5F)
5807 #define REG_HDMI_DUAL_0_30_L       (REG_HDMI_DUAL_0_BASE + 0x60)
5808 #define REG_HDMI_DUAL_0_30_H       (REG_HDMI_DUAL_0_BASE + 0x61)
5809 #define REG_HDMI_DUAL_0_31_L       (REG_HDMI_DUAL_0_BASE + 0x62)
5810 #define REG_HDMI_DUAL_0_31_H       (REG_HDMI_DUAL_0_BASE + 0x63)
5811 #define REG_HDMI_DUAL_0_32_L       (REG_HDMI_DUAL_0_BASE + 0x64)
5812 #define REG_HDMI_DUAL_0_32_H       (REG_HDMI_DUAL_0_BASE + 0x65)
5813 #define REG_HDMI_DUAL_0_33_L       (REG_HDMI_DUAL_0_BASE + 0x66)
5814 #define REG_HDMI_DUAL_0_33_H       (REG_HDMI_DUAL_0_BASE + 0x67)
5815 #define REG_HDMI_DUAL_0_34_L       (REG_HDMI_DUAL_0_BASE + 0x68)
5816 #define REG_HDMI_DUAL_0_34_H       (REG_HDMI_DUAL_0_BASE + 0x69)
5817 #define REG_HDMI_DUAL_0_35_L       (REG_HDMI_DUAL_0_BASE + 0x6A)
5818 #define REG_HDMI_DUAL_0_35_H       (REG_HDMI_DUAL_0_BASE + 0x6B)
5819 #define REG_HDMI_DUAL_0_36_L       (REG_HDMI_DUAL_0_BASE + 0x6C)
5820 #define REG_HDMI_DUAL_0_36_H       (REG_HDMI_DUAL_0_BASE + 0x6D)
5821 #define REG_HDMI_DUAL_0_37_L       (REG_HDMI_DUAL_0_BASE + 0x6E)
5822 #define REG_HDMI_DUAL_0_37_H       (REG_HDMI_DUAL_0_BASE + 0x6F)
5823 #define REG_HDMI_DUAL_0_38_L       (REG_HDMI_DUAL_0_BASE + 0x70)
5824 #define REG_HDMI_DUAL_0_38_H       (REG_HDMI_DUAL_0_BASE + 0x71)
5825 #define REG_HDMI_DUAL_0_39_L       (REG_HDMI_DUAL_0_BASE + 0x72)
5826 #define REG_HDMI_DUAL_0_39_H       (REG_HDMI_DUAL_0_BASE + 0x73)
5827 #define REG_HDMI_DUAL_0_3A_L       (REG_HDMI_DUAL_0_BASE + 0x74)
5828 #define REG_HDMI_DUAL_0_3A_H       (REG_HDMI_DUAL_0_BASE + 0x75)
5829 #define REG_HDMI_DUAL_0_3B_L       (REG_HDMI_DUAL_0_BASE + 0x76)
5830 #define REG_HDMI_DUAL_0_3B_H       (REG_HDMI_DUAL_0_BASE + 0x77)
5831 #define REG_HDMI_DUAL_0_3C_L       (REG_HDMI_DUAL_0_BASE + 0x78)
5832 #define REG_HDMI_DUAL_0_3C_H       (REG_HDMI_DUAL_0_BASE + 0x79)
5833 #define REG_HDMI_DUAL_0_3D_L       (REG_HDMI_DUAL_0_BASE + 0x7A)
5834 #define REG_HDMI_DUAL_0_3D_H       (REG_HDMI_DUAL_0_BASE + 0x7B)
5835 #define REG_HDMI_DUAL_0_3E_L       (REG_HDMI_DUAL_0_BASE + 0x7C)
5836 #define REG_HDMI_DUAL_0_3E_H       (REG_HDMI_DUAL_0_BASE + 0x7D)
5837 #define REG_HDMI_DUAL_0_3F_L       (REG_HDMI_DUAL_0_BASE + 0x7E)
5838 #define REG_HDMI_DUAL_0_3F_H       (REG_HDMI_DUAL_0_BASE + 0x7F)
5839 #define REG_HDMI_DUAL_0_40_L       (REG_HDMI_DUAL_0_BASE + 0x80)
5840 #define REG_HDMI_DUAL_0_40_H       (REG_HDMI_DUAL_0_BASE + 0x81)
5841 #define REG_HDMI_DUAL_0_41_L       (REG_HDMI_DUAL_0_BASE + 0x82)
5842 #define REG_HDMI_DUAL_0_41_H       (REG_HDMI_DUAL_0_BASE + 0x83)
5843 #define REG_HDMI_DUAL_0_42_L       (REG_HDMI_DUAL_0_BASE + 0x84)
5844 #define REG_HDMI_DUAL_0_42_H       (REG_HDMI_DUAL_0_BASE + 0x85)
5845 #define REG_HDMI_DUAL_0_43_L       (REG_HDMI_DUAL_0_BASE + 0x86)
5846 #define REG_HDMI_DUAL_0_43_H       (REG_HDMI_DUAL_0_BASE + 0x87)
5847 #define REG_HDMI_DUAL_0_44_L       (REG_HDMI_DUAL_0_BASE + 0x88)
5848 #define REG_HDMI_DUAL_0_44_H       (REG_HDMI_DUAL_0_BASE + 0x89)
5849 #define REG_HDMI_DUAL_0_45_L       (REG_HDMI_DUAL_0_BASE + 0x8A)
5850 #define REG_HDMI_DUAL_0_45_H       (REG_HDMI_DUAL_0_BASE + 0x8B)
5851 #define REG_HDMI_DUAL_0_46_L       (REG_HDMI_DUAL_0_BASE + 0x8C)
5852 #define REG_HDMI_DUAL_0_46_H       (REG_HDMI_DUAL_0_BASE + 0x8D)
5853 #define REG_HDMI_DUAL_0_47_L       (REG_HDMI_DUAL_0_BASE + 0x8E)
5854 #define REG_HDMI_DUAL_0_47_H       (REG_HDMI_DUAL_0_BASE + 0x8F)
5855 #define REG_HDMI_DUAL_0_48_L       (REG_HDMI_DUAL_0_BASE + 0x90)
5856 #define REG_HDMI_DUAL_0_48_H       (REG_HDMI_DUAL_0_BASE + 0x91)
5857 #define REG_HDMI_DUAL_0_49_L       (REG_HDMI_DUAL_0_BASE + 0x92)
5858 #define REG_HDMI_DUAL_0_49_H       (REG_HDMI_DUAL_0_BASE + 0x93)
5859 #define REG_HDMI_DUAL_0_4A_L       (REG_HDMI_DUAL_0_BASE + 0x94)
5860 #define REG_HDMI_DUAL_0_4A_H       (REG_HDMI_DUAL_0_BASE + 0x95)
5861 #define REG_HDMI_DUAL_0_4B_L       (REG_HDMI_DUAL_0_BASE + 0x96)
5862 #define REG_HDMI_DUAL_0_4B_H       (REG_HDMI_DUAL_0_BASE + 0x97)
5863 #define REG_HDMI_DUAL_0_4C_L       (REG_HDMI_DUAL_0_BASE + 0x98)
5864 #define REG_HDMI_DUAL_0_4C_H       (REG_HDMI_DUAL_0_BASE + 0x99)
5865 #define REG_HDMI_DUAL_0_4D_L       (REG_HDMI_DUAL_0_BASE + 0x9A)
5866 #define REG_HDMI_DUAL_0_4D_H       (REG_HDMI_DUAL_0_BASE + 0x9B)
5867 #define REG_HDMI_DUAL_0_4E_L       (REG_HDMI_DUAL_0_BASE + 0x9C)
5868 #define REG_HDMI_DUAL_0_4E_H       (REG_HDMI_DUAL_0_BASE + 0x9D)
5869 #define REG_HDMI_DUAL_0_4F_L       (REG_HDMI_DUAL_0_BASE + 0x9E)
5870 #define REG_HDMI_DUAL_0_4F_H       (REG_HDMI_DUAL_0_BASE + 0x9F)
5871 #define REG_HDMI_DUAL_0_50_L       (REG_HDMI_DUAL_0_BASE + 0xA0)
5872 #define REG_HDMI_DUAL_0_50_H       (REG_HDMI_DUAL_0_BASE + 0xA1)
5873 #define REG_HDMI_DUAL_0_51_L       (REG_HDMI_DUAL_0_BASE + 0xA2)
5874 #define REG_HDMI_DUAL_0_51_H       (REG_HDMI_DUAL_0_BASE + 0xA3)
5875 #define REG_HDMI_DUAL_0_52_L       (REG_HDMI_DUAL_0_BASE + 0xA4)
5876 #define REG_HDMI_DUAL_0_52_H       (REG_HDMI_DUAL_0_BASE + 0xA5)
5877 #define REG_HDMI_DUAL_0_53_L       (REG_HDMI_DUAL_0_BASE + 0xA6)
5878 #define REG_HDMI_DUAL_0_53_H       (REG_HDMI_DUAL_0_BASE + 0xA7)
5879 #define REG_HDMI_DUAL_0_54_L       (REG_HDMI_DUAL_0_BASE + 0xA8)
5880 #define REG_HDMI_DUAL_0_54_H       (REG_HDMI_DUAL_0_BASE + 0xA9)
5881 #define REG_HDMI_DUAL_0_55_L       (REG_HDMI_DUAL_0_BASE + 0xAA)
5882 #define REG_HDMI_DUAL_0_55_H       (REG_HDMI_DUAL_0_BASE + 0xAB)
5883 #define REG_HDMI_DUAL_0_56_L       (REG_HDMI_DUAL_0_BASE + 0xAC)
5884 #define REG_HDMI_DUAL_0_56_H       (REG_HDMI_DUAL_0_BASE + 0xAD)
5885 #define REG_HDMI_DUAL_0_57_L       (REG_HDMI_DUAL_0_BASE + 0xAE)
5886 #define REG_HDMI_DUAL_0_57_H       (REG_HDMI_DUAL_0_BASE + 0xAF)
5887 #define REG_HDMI_DUAL_0_58_L       (REG_HDMI_DUAL_0_BASE + 0xB0)
5888 #define REG_HDMI_DUAL_0_58_H       (REG_HDMI_DUAL_0_BASE + 0xB1)
5889 #define REG_HDMI_DUAL_0_59_L       (REG_HDMI_DUAL_0_BASE + 0xB2)
5890 #define REG_HDMI_DUAL_0_59_H       (REG_HDMI_DUAL_0_BASE + 0xB3)
5891 #define REG_HDMI_DUAL_0_5A_L       (REG_HDMI_DUAL_0_BASE + 0xB4)
5892 #define REG_HDMI_DUAL_0_5A_H       (REG_HDMI_DUAL_0_BASE + 0xB5)
5893 #define REG_HDMI_DUAL_0_5B_L       (REG_HDMI_DUAL_0_BASE + 0xB6)
5894 #define REG_HDMI_DUAL_0_5B_H       (REG_HDMI_DUAL_0_BASE + 0xB7)
5895 #define REG_HDMI_DUAL_0_5C_L       (REG_HDMI_DUAL_0_BASE + 0xB8)
5896 #define REG_HDMI_DUAL_0_5C_H       (REG_HDMI_DUAL_0_BASE + 0xB9)
5897 #define REG_HDMI_DUAL_0_5D_L       (REG_HDMI_DUAL_0_BASE + 0xBA)
5898 #define REG_HDMI_DUAL_0_5D_H       (REG_HDMI_DUAL_0_BASE + 0xBB)
5899 #define REG_HDMI_DUAL_0_5E_L       (REG_HDMI_DUAL_0_BASE + 0xBC)
5900 #define REG_HDMI_DUAL_0_5E_H       (REG_HDMI_DUAL_0_BASE + 0xBD)
5901 #define REG_HDMI_DUAL_0_5F_L       (REG_HDMI_DUAL_0_BASE + 0xBE)
5902 #define REG_HDMI_DUAL_0_5F_H       (REG_HDMI_DUAL_0_BASE + 0xBF)
5903 #define REG_HDMI_DUAL_0_60_L       (REG_HDMI_DUAL_0_BASE + 0xC0)
5904 #define REG_HDMI_DUAL_0_60_H       (REG_HDMI_DUAL_0_BASE + 0xC1)
5905 #define REG_HDMI_DUAL_0_61_L       (REG_HDMI_DUAL_0_BASE + 0xC2)
5906 #define REG_HDMI_DUAL_0_61_H       (REG_HDMI_DUAL_0_BASE + 0xC3)
5907 #define REG_HDMI_DUAL_0_62_L       (REG_HDMI_DUAL_0_BASE + 0xC4)
5908 #define REG_HDMI_DUAL_0_62_H       (REG_HDMI_DUAL_0_BASE + 0xC5)
5909 #define REG_HDMI_DUAL_0_63_L       (REG_HDMI_DUAL_0_BASE + 0xC6)
5910 #define REG_HDMI_DUAL_0_63_H       (REG_HDMI_DUAL_0_BASE + 0xC7)
5911 #define REG_HDMI_DUAL_0_64_L       (REG_HDMI_DUAL_0_BASE + 0xC8)
5912 #define REG_HDMI_DUAL_0_64_H       (REG_HDMI_DUAL_0_BASE + 0xC9)
5913 #define REG_HDMI_DUAL_0_65_L       (REG_HDMI_DUAL_0_BASE + 0xCA)
5914 #define REG_HDMI_DUAL_0_65_H       (REG_HDMI_DUAL_0_BASE + 0xCB)
5915 #define REG_HDMI_DUAL_0_66_L       (REG_HDMI_DUAL_0_BASE + 0xCC)
5916 #define REG_HDMI_DUAL_0_66_H       (REG_HDMI_DUAL_0_BASE + 0xCD)
5917 #define REG_HDMI_DUAL_0_67_L       (REG_HDMI_DUAL_0_BASE + 0xCE)
5918 #define REG_HDMI_DUAL_0_67_H       (REG_HDMI_DUAL_0_BASE + 0xCF)
5919 #define REG_HDMI_DUAL_0_68_L       (REG_HDMI_DUAL_0_BASE + 0xD0)
5920 #define REG_HDMI_DUAL_0_68_H       (REG_HDMI_DUAL_0_BASE + 0xD1)
5921 #define REG_HDMI_DUAL_0_69_L       (REG_HDMI_DUAL_0_BASE + 0xD2)
5922 #define REG_HDMI_DUAL_0_69_H       (REG_HDMI_DUAL_0_BASE + 0xD3)
5923 #define REG_HDMI_DUAL_0_6A_L       (REG_HDMI_DUAL_0_BASE + 0xD4)
5924 #define REG_HDMI_DUAL_0_6A_H       (REG_HDMI_DUAL_0_BASE + 0xD5)
5925 #define REG_HDMI_DUAL_0_6B_L       (REG_HDMI_DUAL_0_BASE + 0xD6)
5926 #define REG_HDMI_DUAL_0_6B_H       (REG_HDMI_DUAL_0_BASE + 0xD7)
5927 #define REG_HDMI_DUAL_0_6C_L       (REG_HDMI_DUAL_0_BASE + 0xD8)
5928 #define REG_HDMI_DUAL_0_6C_H       (REG_HDMI_DUAL_0_BASE + 0xD9)
5929 #define REG_HDMI_DUAL_0_6D_L       (REG_HDMI_DUAL_0_BASE + 0xDA)
5930 #define REG_HDMI_DUAL_0_6D_H       (REG_HDMI_DUAL_0_BASE + 0xDB)
5931 #define REG_HDMI_DUAL_0_6E_L       (REG_HDMI_DUAL_0_BASE + 0xDC)
5932 #define REG_HDMI_DUAL_0_6E_H       (REG_HDMI_DUAL_0_BASE + 0xDD)
5933 #define REG_HDMI_DUAL_0_6F_L       (REG_HDMI_DUAL_0_BASE + 0xDE)
5934 #define REG_HDMI_DUAL_0_6F_H       (REG_HDMI_DUAL_0_BASE + 0xDF)
5935 #define REG_HDMI_DUAL_0_70_L       (REG_HDMI_DUAL_0_BASE + 0xE0)
5936 #define REG_HDMI_DUAL_0_70_H       (REG_HDMI_DUAL_0_BASE + 0xE1)
5937 #define REG_HDMI_DUAL_0_71_L       (REG_HDMI_DUAL_0_BASE + 0xE2)
5938 #define REG_HDMI_DUAL_0_71_H       (REG_HDMI_DUAL_0_BASE + 0xE3)
5939 #define REG_HDMI_DUAL_0_72_L       (REG_HDMI_DUAL_0_BASE + 0xE4)
5940 #define REG_HDMI_DUAL_0_72_H       (REG_HDMI_DUAL_0_BASE + 0xE5)
5941 #define REG_HDMI_DUAL_0_73_L       (REG_HDMI_DUAL_0_BASE + 0xE6)
5942 #define REG_HDMI_DUAL_0_73_H       (REG_HDMI_DUAL_0_BASE + 0xE7)
5943 #define REG_HDMI_DUAL_0_74_L       (REG_HDMI_DUAL_0_BASE + 0xE8)
5944 #define REG_HDMI_DUAL_0_74_H       (REG_HDMI_DUAL_0_BASE + 0xE9)
5945 #define REG_HDMI_DUAL_0_75_L       (REG_HDMI_DUAL_0_BASE + 0xEA)
5946 #define REG_HDMI_DUAL_0_75_H       (REG_HDMI_DUAL_0_BASE + 0xEB)
5947 #define REG_HDMI_DUAL_0_76_L       (REG_HDMI_DUAL_0_BASE + 0xEC)
5948 #define REG_HDMI_DUAL_0_76_H       (REG_HDMI_DUAL_0_BASE + 0xED)
5949 #define REG_HDMI_DUAL_0_77_L       (REG_HDMI_DUAL_0_BASE + 0xEE)
5950 #define REG_HDMI_DUAL_0_77_H       (REG_HDMI_DUAL_0_BASE + 0xEF)
5951 #define REG_HDMI_DUAL_0_78_L       (REG_HDMI_DUAL_0_BASE + 0xF0)
5952 #define REG_HDMI_DUAL_0_78_H       (REG_HDMI_DUAL_0_BASE + 0xF1)
5953 #define REG_HDMI_DUAL_0_79_L       (REG_HDMI_DUAL_0_BASE + 0xF2)
5954 #define REG_HDMI_DUAL_0_79_H       (REG_HDMI_DUAL_0_BASE + 0xF3)
5955 #define REG_HDMI_DUAL_0_7A_L       (REG_HDMI_DUAL_0_BASE + 0xF4)
5956 #define REG_HDMI_DUAL_0_7A_H       (REG_HDMI_DUAL_0_BASE + 0xF5)
5957 #define REG_HDMI_DUAL_0_7B_L       (REG_HDMI_DUAL_0_BASE + 0xF6)
5958 #define REG_HDMI_DUAL_0_7B_H       (REG_HDMI_DUAL_0_BASE + 0xF7)
5959 #define REG_HDMI_DUAL_0_7C_L       (REG_HDMI_DUAL_0_BASE + 0xF8)
5960 #define REG_HDMI_DUAL_0_7C_H       (REG_HDMI_DUAL_0_BASE + 0xF9)
5961 #define REG_HDMI_DUAL_0_7D_L       (REG_HDMI_DUAL_0_BASE + 0xFA)
5962 #define REG_HDMI_DUAL_0_7D_H       (REG_HDMI_DUAL_0_BASE + 0xFB)
5963 #define REG_HDMI_DUAL_0_7E_L       (REG_HDMI_DUAL_0_BASE + 0xFC)
5964 #define REG_HDMI_DUAL_0_7E_H       (REG_HDMI_DUAL_0_BASE + 0xFD)
5965 #define REG_HDMI_DUAL_0_7F_L       (REG_HDMI_DUAL_0_BASE + 0xFE)
5966 #define REG_HDMI_DUAL_0_7F_H       (REG_HDMI_DUAL_0_BASE + 0xFF)
5967 
5968 // HDMI2_DUAL_0
5969 #define REG_HDMI2_DUAL_0_00_L       (REG_HDMI2_DUAL_0_BASE + 0x00)
5970 #define REG_HDMI2_DUAL_0_00_H       (REG_HDMI2_DUAL_0_BASE + 0x01)
5971 #define REG_HDMI2_DUAL_0_01_L       (REG_HDMI2_DUAL_0_BASE + 0x02)
5972 #define REG_HDMI2_DUAL_0_01_H       (REG_HDMI2_DUAL_0_BASE + 0x03)
5973 #define REG_HDMI2_DUAL_0_02_L       (REG_HDMI2_DUAL_0_BASE + 0x04)
5974 #define REG_HDMI2_DUAL_0_02_H       (REG_HDMI2_DUAL_0_BASE + 0x05)
5975 #define REG_HDMI2_DUAL_0_03_L       (REG_HDMI2_DUAL_0_BASE + 0x06)
5976 #define REG_HDMI2_DUAL_0_03_H       (REG_HDMI2_DUAL_0_BASE + 0x07)
5977 #define REG_HDMI2_DUAL_0_04_L       (REG_HDMI2_DUAL_0_BASE + 0x08)
5978 #define REG_HDMI2_DUAL_0_04_H       (REG_HDMI2_DUAL_0_BASE + 0x09)
5979 #define REG_HDMI2_DUAL_0_05_L       (REG_HDMI2_DUAL_0_BASE + 0x0A)
5980 #define REG_HDMI2_DUAL_0_05_H       (REG_HDMI2_DUAL_0_BASE + 0x0B)
5981 #define REG_HDMI2_DUAL_0_06_L       (REG_HDMI2_DUAL_0_BASE + 0x0C)
5982 #define REG_HDMI2_DUAL_0_06_H       (REG_HDMI2_DUAL_0_BASE + 0x0D)
5983 #define REG_HDMI2_DUAL_0_07_L       (REG_HDMI2_DUAL_0_BASE + 0x0E)
5984 #define REG_HDMI2_DUAL_0_07_H       (REG_HDMI2_DUAL_0_BASE + 0x0F)
5985 #define REG_HDMI2_DUAL_0_08_L       (REG_HDMI2_DUAL_0_BASE + 0x10)
5986 #define REG_HDMI2_DUAL_0_08_H       (REG_HDMI2_DUAL_0_BASE + 0x11)
5987 #define REG_HDMI2_DUAL_0_09_L       (REG_HDMI2_DUAL_0_BASE + 0x12)
5988 #define REG_HDMI2_DUAL_0_09_H       (REG_HDMI2_DUAL_0_BASE + 0x13)
5989 #define REG_HDMI2_DUAL_0_0A_L       (REG_HDMI2_DUAL_0_BASE + 0x14)
5990 #define REG_HDMI2_DUAL_0_0A_H       (REG_HDMI2_DUAL_0_BASE + 0x15)
5991 #define REG_HDMI2_DUAL_0_0B_L       (REG_HDMI2_DUAL_0_BASE + 0x16)
5992 #define REG_HDMI2_DUAL_0_0B_H       (REG_HDMI2_DUAL_0_BASE + 0x17)
5993 #define REG_HDMI2_DUAL_0_0C_L       (REG_HDMI2_DUAL_0_BASE + 0x18)
5994 #define REG_HDMI2_DUAL_0_0C_H       (REG_HDMI2_DUAL_0_BASE + 0x19)
5995 #define REG_HDMI2_DUAL_0_0D_L       (REG_HDMI2_DUAL_0_BASE + 0x1A)
5996 #define REG_HDMI2_DUAL_0_0D_H       (REG_HDMI2_DUAL_0_BASE + 0x1B)
5997 #define REG_HDMI2_DUAL_0_0E_L       (REG_HDMI2_DUAL_0_BASE + 0x1C)
5998 #define REG_HDMI2_DUAL_0_0E_H       (REG_HDMI2_DUAL_0_BASE + 0x1D)
5999 #define REG_HDMI2_DUAL_0_0F_L       (REG_HDMI2_DUAL_0_BASE + 0x1E)
6000 #define REG_HDMI2_DUAL_0_0F_H       (REG_HDMI2_DUAL_0_BASE + 0x1F)
6001 #define REG_HDMI2_DUAL_0_10_L       (REG_HDMI2_DUAL_0_BASE + 0x20)
6002 #define REG_HDMI2_DUAL_0_10_H       (REG_HDMI2_DUAL_0_BASE + 0x21)
6003 #define REG_HDMI2_DUAL_0_11_L       (REG_HDMI2_DUAL_0_BASE + 0x22)
6004 #define REG_HDMI2_DUAL_0_11_H       (REG_HDMI2_DUAL_0_BASE + 0x23)
6005 #define REG_HDMI2_DUAL_0_12_L       (REG_HDMI2_DUAL_0_BASE + 0x24)
6006 #define REG_HDMI2_DUAL_0_12_H       (REG_HDMI2_DUAL_0_BASE + 0x25)
6007 #define REG_HDMI2_DUAL_0_13_L       (REG_HDMI2_DUAL_0_BASE + 0x26)
6008 #define REG_HDMI2_DUAL_0_13_H       (REG_HDMI2_DUAL_0_BASE + 0x27)
6009 #define REG_HDMI2_DUAL_0_14_L       (REG_HDMI2_DUAL_0_BASE + 0x28)
6010 #define REG_HDMI2_DUAL_0_14_H       (REG_HDMI2_DUAL_0_BASE + 0x29)
6011 #define REG_HDMI2_DUAL_0_15_L       (REG_HDMI2_DUAL_0_BASE + 0x2A)
6012 #define REG_HDMI2_DUAL_0_15_H       (REG_HDMI2_DUAL_0_BASE + 0x2B)
6013 #define REG_HDMI2_DUAL_0_16_L       (REG_HDMI2_DUAL_0_BASE + 0x2C)
6014 #define REG_HDMI2_DUAL_0_16_H       (REG_HDMI2_DUAL_0_BASE + 0x2D)
6015 #define REG_HDMI2_DUAL_0_17_L       (REG_HDMI2_DUAL_0_BASE + 0x2E)
6016 #define REG_HDMI2_DUAL_0_17_H       (REG_HDMI2_DUAL_0_BASE + 0x2F)
6017 #define REG_HDMI2_DUAL_0_18_L       (REG_HDMI2_DUAL_0_BASE + 0x30)
6018 #define REG_HDMI2_DUAL_0_18_H       (REG_HDMI2_DUAL_0_BASE + 0x31)
6019 #define REG_HDMI2_DUAL_0_19_L       (REG_HDMI2_DUAL_0_BASE + 0x32)
6020 #define REG_HDMI2_DUAL_0_19_H       (REG_HDMI2_DUAL_0_BASE + 0x33)
6021 #define REG_HDMI2_DUAL_0_1A_L       (REG_HDMI2_DUAL_0_BASE + 0x34)
6022 #define REG_HDMI2_DUAL_0_1A_H       (REG_HDMI2_DUAL_0_BASE + 0x35)
6023 #define REG_HDMI2_DUAL_0_1B_L       (REG_HDMI2_DUAL_0_BASE + 0x36)
6024 #define REG_HDMI2_DUAL_0_1B_H       (REG_HDMI2_DUAL_0_BASE + 0x37)
6025 #define REG_HDMI2_DUAL_0_1C_L       (REG_HDMI2_DUAL_0_BASE + 0x38)
6026 #define REG_HDMI2_DUAL_0_1C_H       (REG_HDMI2_DUAL_0_BASE + 0x39)
6027 #define REG_HDMI2_DUAL_0_1D_L       (REG_HDMI2_DUAL_0_BASE + 0x3A)
6028 #define REG_HDMI2_DUAL_0_1D_H       (REG_HDMI2_DUAL_0_BASE + 0x3B)
6029 #define REG_HDMI2_DUAL_0_1E_L       (REG_HDMI2_DUAL_0_BASE + 0x3C)
6030 #define REG_HDMI2_DUAL_0_1E_H       (REG_HDMI2_DUAL_0_BASE + 0x3D)
6031 #define REG_HDMI2_DUAL_0_1F_L       (REG_HDMI2_DUAL_0_BASE + 0x3E)
6032 #define REG_HDMI2_DUAL_0_1F_H       (REG_HDMI2_DUAL_0_BASE + 0x3F)
6033 #define REG_HDMI2_DUAL_0_20_L       (REG_HDMI2_DUAL_0_BASE + 0x40)
6034 #define REG_HDMI2_DUAL_0_20_H       (REG_HDMI2_DUAL_0_BASE + 0x41)
6035 #define REG_HDMI2_DUAL_0_21_L       (REG_HDMI2_DUAL_0_BASE + 0x42)
6036 #define REG_HDMI2_DUAL_0_21_H       (REG_HDMI2_DUAL_0_BASE + 0x43)
6037 #define REG_HDMI2_DUAL_0_22_L       (REG_HDMI2_DUAL_0_BASE + 0x44)
6038 #define REG_HDMI2_DUAL_0_22_H       (REG_HDMI2_DUAL_0_BASE + 0x45)
6039 #define REG_HDMI2_DUAL_0_23_L       (REG_HDMI2_DUAL_0_BASE + 0x46)
6040 #define REG_HDMI2_DUAL_0_23_H       (REG_HDMI2_DUAL_0_BASE + 0x47)
6041 #define REG_HDMI2_DUAL_0_24_L       (REG_HDMI2_DUAL_0_BASE + 0x48)
6042 #define REG_HDMI2_DUAL_0_24_H       (REG_HDMI2_DUAL_0_BASE + 0x49)
6043 #define REG_HDMI2_DUAL_0_25_L       (REG_HDMI2_DUAL_0_BASE + 0x4A)
6044 #define REG_HDMI2_DUAL_0_25_H       (REG_HDMI2_DUAL_0_BASE + 0x4B)
6045 #define REG_HDMI2_DUAL_0_26_L       (REG_HDMI2_DUAL_0_BASE + 0x4C)
6046 #define REG_HDMI2_DUAL_0_26_H       (REG_HDMI2_DUAL_0_BASE + 0x4D)
6047 #define REG_HDMI2_DUAL_0_27_L       (REG_HDMI2_DUAL_0_BASE + 0x4E)
6048 #define REG_HDMI2_DUAL_0_27_H       (REG_HDMI2_DUAL_0_BASE + 0x4F)
6049 #define REG_HDMI2_DUAL_0_28_L       (REG_HDMI2_DUAL_0_BASE + 0x50)
6050 #define REG_HDMI2_DUAL_0_28_H       (REG_HDMI2_DUAL_0_BASE + 0x51)
6051 #define REG_HDMI2_DUAL_0_29_L       (REG_HDMI2_DUAL_0_BASE + 0x52)
6052 #define REG_HDMI2_DUAL_0_29_H       (REG_HDMI2_DUAL_0_BASE + 0x53)
6053 #define REG_HDMI2_DUAL_0_2A_L       (REG_HDMI2_DUAL_0_BASE + 0x54)
6054 #define REG_HDMI2_DUAL_0_2A_H       (REG_HDMI2_DUAL_0_BASE + 0x55)
6055 #define REG_HDMI2_DUAL_0_2B_L       (REG_HDMI2_DUAL_0_BASE + 0x56)
6056 #define REG_HDMI2_DUAL_0_2B_H       (REG_HDMI2_DUAL_0_BASE + 0x57)
6057 #define REG_HDMI2_DUAL_0_2C_L       (REG_HDMI2_DUAL_0_BASE + 0x58)
6058 #define REG_HDMI2_DUAL_0_2C_H       (REG_HDMI2_DUAL_0_BASE + 0x59)
6059 #define REG_HDMI2_DUAL_0_2D_L       (REG_HDMI2_DUAL_0_BASE + 0x5A)
6060 #define REG_HDMI2_DUAL_0_2D_H       (REG_HDMI2_DUAL_0_BASE + 0x5B)
6061 #define REG_HDMI2_DUAL_0_2E_L       (REG_HDMI2_DUAL_0_BASE + 0x5C)
6062 #define REG_HDMI2_DUAL_0_2E_H       (REG_HDMI2_DUAL_0_BASE + 0x5D)
6063 #define REG_HDMI2_DUAL_0_2F_L       (REG_HDMI2_DUAL_0_BASE + 0x5E)
6064 #define REG_HDMI2_DUAL_0_2F_H       (REG_HDMI2_DUAL_0_BASE + 0x5F)
6065 #define REG_HDMI2_DUAL_0_30_L       (REG_HDMI2_DUAL_0_BASE + 0x60)
6066 #define REG_HDMI2_DUAL_0_30_H       (REG_HDMI2_DUAL_0_BASE + 0x61)
6067 #define REG_HDMI2_DUAL_0_31_L       (REG_HDMI2_DUAL_0_BASE + 0x62)
6068 #define REG_HDMI2_DUAL_0_31_H       (REG_HDMI2_DUAL_0_BASE + 0x63)
6069 #define REG_HDMI2_DUAL_0_32_L       (REG_HDMI2_DUAL_0_BASE + 0x64)
6070 #define REG_HDMI2_DUAL_0_32_H       (REG_HDMI2_DUAL_0_BASE + 0x65)
6071 #define REG_HDMI2_DUAL_0_33_L       (REG_HDMI2_DUAL_0_BASE + 0x66)
6072 #define REG_HDMI2_DUAL_0_33_H       (REG_HDMI2_DUAL_0_BASE + 0x67)
6073 #define REG_HDMI2_DUAL_0_34_L       (REG_HDMI2_DUAL_0_BASE + 0x68)
6074 #define REG_HDMI2_DUAL_0_34_H       (REG_HDMI2_DUAL_0_BASE + 0x69)
6075 #define REG_HDMI2_DUAL_0_35_L       (REG_HDMI2_DUAL_0_BASE + 0x6A)
6076 #define REG_HDMI2_DUAL_0_35_H       (REG_HDMI2_DUAL_0_BASE + 0x6B)
6077 #define REG_HDMI2_DUAL_0_36_L       (REG_HDMI2_DUAL_0_BASE + 0x6C)
6078 #define REG_HDMI2_DUAL_0_36_H       (REG_HDMI2_DUAL_0_BASE + 0x6D)
6079 #define REG_HDMI2_DUAL_0_37_L       (REG_HDMI2_DUAL_0_BASE + 0x6E)
6080 #define REG_HDMI2_DUAL_0_37_H       (REG_HDMI2_DUAL_0_BASE + 0x6F)
6081 #define REG_HDMI2_DUAL_0_38_L       (REG_HDMI2_DUAL_0_BASE + 0x70)
6082 #define REG_HDMI2_DUAL_0_38_H       (REG_HDMI2_DUAL_0_BASE + 0x71)
6083 #define REG_HDMI2_DUAL_0_39_L       (REG_HDMI2_DUAL_0_BASE + 0x72)
6084 #define REG_HDMI2_DUAL_0_39_H       (REG_HDMI2_DUAL_0_BASE + 0x73)
6085 #define REG_HDMI2_DUAL_0_3A_L       (REG_HDMI2_DUAL_0_BASE + 0x74)
6086 #define REG_HDMI2_DUAL_0_3A_H       (REG_HDMI2_DUAL_0_BASE + 0x75)
6087 #define REG_HDMI2_DUAL_0_3B_L       (REG_HDMI2_DUAL_0_BASE + 0x76)
6088 #define REG_HDMI2_DUAL_0_3B_H       (REG_HDMI2_DUAL_0_BASE + 0x77)
6089 #define REG_HDMI2_DUAL_0_3C_L       (REG_HDMI2_DUAL_0_BASE + 0x78)
6090 #define REG_HDMI2_DUAL_0_3C_H       (REG_HDMI2_DUAL_0_BASE + 0x79)
6091 #define REG_HDMI2_DUAL_0_3D_L       (REG_HDMI2_DUAL_0_BASE + 0x7A)
6092 #define REG_HDMI2_DUAL_0_3D_H       (REG_HDMI2_DUAL_0_BASE + 0x7B)
6093 #define REG_HDMI2_DUAL_0_3E_L       (REG_HDMI2_DUAL_0_BASE + 0x7C)
6094 #define REG_HDMI2_DUAL_0_3E_H       (REG_HDMI2_DUAL_0_BASE + 0x7D)
6095 #define REG_HDMI2_DUAL_0_3F_L       (REG_HDMI2_DUAL_0_BASE + 0x7E)
6096 #define REG_HDMI2_DUAL_0_3F_H       (REG_HDMI2_DUAL_0_BASE + 0x7F)
6097 #define REG_HDMI2_DUAL_0_40_L       (REG_HDMI2_DUAL_0_BASE + 0x80)
6098 #define REG_HDMI2_DUAL_0_40_H       (REG_HDMI2_DUAL_0_BASE + 0x81)
6099 #define REG_HDMI2_DUAL_0_41_L       (REG_HDMI2_DUAL_0_BASE + 0x82)
6100 #define REG_HDMI2_DUAL_0_41_H       (REG_HDMI2_DUAL_0_BASE + 0x83)
6101 #define REG_HDMI2_DUAL_0_42_L       (REG_HDMI2_DUAL_0_BASE + 0x84)
6102 #define REG_HDMI2_DUAL_0_42_H       (REG_HDMI2_DUAL_0_BASE + 0x85)
6103 #define REG_HDMI2_DUAL_0_43_L       (REG_HDMI2_DUAL_0_BASE + 0x86)
6104 #define REG_HDMI2_DUAL_0_43_H       (REG_HDMI2_DUAL_0_BASE + 0x87)
6105 #define REG_HDMI2_DUAL_0_44_L       (REG_HDMI2_DUAL_0_BASE + 0x88)
6106 #define REG_HDMI2_DUAL_0_44_H       (REG_HDMI2_DUAL_0_BASE + 0x89)
6107 #define REG_HDMI2_DUAL_0_45_L       (REG_HDMI2_DUAL_0_BASE + 0x8A)
6108 #define REG_HDMI2_DUAL_0_45_H       (REG_HDMI2_DUAL_0_BASE + 0x8B)
6109 #define REG_HDMI2_DUAL_0_46_L       (REG_HDMI2_DUAL_0_BASE + 0x8C)
6110 #define REG_HDMI2_DUAL_0_46_H       (REG_HDMI2_DUAL_0_BASE + 0x8D)
6111 #define REG_HDMI2_DUAL_0_47_L       (REG_HDMI2_DUAL_0_BASE + 0x8E)
6112 #define REG_HDMI2_DUAL_0_47_H       (REG_HDMI2_DUAL_0_BASE + 0x8F)
6113 #define REG_HDMI2_DUAL_0_48_L       (REG_HDMI2_DUAL_0_BASE + 0x90)
6114 #define REG_HDMI2_DUAL_0_48_H       (REG_HDMI2_DUAL_0_BASE + 0x91)
6115 #define REG_HDMI2_DUAL_0_49_L       (REG_HDMI2_DUAL_0_BASE + 0x92)
6116 #define REG_HDMI2_DUAL_0_49_H       (REG_HDMI2_DUAL_0_BASE + 0x93)
6117 #define REG_HDMI2_DUAL_0_4A_L       (REG_HDMI2_DUAL_0_BASE + 0x94)
6118 #define REG_HDMI2_DUAL_0_4A_H       (REG_HDMI2_DUAL_0_BASE + 0x95)
6119 #define REG_HDMI2_DUAL_0_4B_L       (REG_HDMI2_DUAL_0_BASE + 0x96)
6120 #define REG_HDMI2_DUAL_0_4B_H       (REG_HDMI2_DUAL_0_BASE + 0x97)
6121 #define REG_HDMI2_DUAL_0_4C_L       (REG_HDMI2_DUAL_0_BASE + 0x98)
6122 #define REG_HDMI2_DUAL_0_4C_H       (REG_HDMI2_DUAL_0_BASE + 0x99)
6123 #define REG_HDMI2_DUAL_0_4D_L       (REG_HDMI2_DUAL_0_BASE + 0x9A)
6124 #define REG_HDMI2_DUAL_0_4D_H       (REG_HDMI2_DUAL_0_BASE + 0x9B)
6125 #define REG_HDMI2_DUAL_0_4E_L       (REG_HDMI2_DUAL_0_BASE + 0x9C)
6126 #define REG_HDMI2_DUAL_0_4E_H       (REG_HDMI2_DUAL_0_BASE + 0x9D)
6127 #define REG_HDMI2_DUAL_0_4F_L       (REG_HDMI2_DUAL_0_BASE + 0x9E)
6128 #define REG_HDMI2_DUAL_0_4F_H       (REG_HDMI2_DUAL_0_BASE + 0x9F)
6129 #define REG_HDMI2_DUAL_0_50_L       (REG_HDMI2_DUAL_0_BASE + 0xA0)
6130 #define REG_HDMI2_DUAL_0_50_H       (REG_HDMI2_DUAL_0_BASE + 0xA1)
6131 #define REG_HDMI2_DUAL_0_51_L       (REG_HDMI2_DUAL_0_BASE + 0xA2)
6132 #define REG_HDMI2_DUAL_0_51_H       (REG_HDMI2_DUAL_0_BASE + 0xA3)
6133 #define REG_HDMI2_DUAL_0_52_L       (REG_HDMI2_DUAL_0_BASE + 0xA4)
6134 #define REG_HDMI2_DUAL_0_52_H       (REG_HDMI2_DUAL_0_BASE + 0xA5)
6135 #define REG_HDMI2_DUAL_0_53_L       (REG_HDMI2_DUAL_0_BASE + 0xA6)
6136 #define REG_HDMI2_DUAL_0_53_H       (REG_HDMI2_DUAL_0_BASE + 0xA7)
6137 #define REG_HDMI2_DUAL_0_54_L       (REG_HDMI2_DUAL_0_BASE + 0xA8)
6138 #define REG_HDMI2_DUAL_0_54_H       (REG_HDMI2_DUAL_0_BASE + 0xA9)
6139 #define REG_HDMI2_DUAL_0_55_L       (REG_HDMI2_DUAL_0_BASE + 0xAA)
6140 #define REG_HDMI2_DUAL_0_55_H       (REG_HDMI2_DUAL_0_BASE + 0xAB)
6141 #define REG_HDMI2_DUAL_0_56_L       (REG_HDMI2_DUAL_0_BASE + 0xAC)
6142 #define REG_HDMI2_DUAL_0_56_H       (REG_HDMI2_DUAL_0_BASE + 0xAD)
6143 #define REG_HDMI2_DUAL_0_57_L       (REG_HDMI2_DUAL_0_BASE + 0xAE)
6144 #define REG_HDMI2_DUAL_0_57_H       (REG_HDMI2_DUAL_0_BASE + 0xAF)
6145 #define REG_HDMI2_DUAL_0_58_L       (REG_HDMI2_DUAL_0_BASE + 0xB0)
6146 #define REG_HDMI2_DUAL_0_58_H       (REG_HDMI2_DUAL_0_BASE + 0xB1)
6147 #define REG_HDMI2_DUAL_0_59_L       (REG_HDMI2_DUAL_0_BASE + 0xB2)
6148 #define REG_HDMI2_DUAL_0_59_H       (REG_HDMI2_DUAL_0_BASE + 0xB3)
6149 #define REG_HDMI2_DUAL_0_5A_L       (REG_HDMI2_DUAL_0_BASE + 0xB4)
6150 #define REG_HDMI2_DUAL_0_5A_H       (REG_HDMI2_DUAL_0_BASE + 0xB5)
6151 #define REG_HDMI2_DUAL_0_5B_L       (REG_HDMI2_DUAL_0_BASE + 0xB6)
6152 #define REG_HDMI2_DUAL_0_5B_H       (REG_HDMI2_DUAL_0_BASE + 0xB7)
6153 #define REG_HDMI2_DUAL_0_5C_L       (REG_HDMI2_DUAL_0_BASE + 0xB8)
6154 #define REG_HDMI2_DUAL_0_5C_H       (REG_HDMI2_DUAL_0_BASE + 0xB9)
6155 #define REG_HDMI2_DUAL_0_5D_L       (REG_HDMI2_DUAL_0_BASE + 0xBA)
6156 #define REG_HDMI2_DUAL_0_5D_H       (REG_HDMI2_DUAL_0_BASE + 0xBB)
6157 #define REG_HDMI2_DUAL_0_5E_L       (REG_HDMI2_DUAL_0_BASE + 0xBC)
6158 #define REG_HDMI2_DUAL_0_5E_H       (REG_HDMI2_DUAL_0_BASE + 0xBD)
6159 #define REG_HDMI2_DUAL_0_5F_L       (REG_HDMI2_DUAL_0_BASE + 0xBE)
6160 #define REG_HDMI2_DUAL_0_5F_H       (REG_HDMI2_DUAL_0_BASE + 0xBF)
6161 #define REG_HDMI2_DUAL_0_60_L       (REG_HDMI2_DUAL_0_BASE + 0xC0)
6162 #define REG_HDMI2_DUAL_0_60_H       (REG_HDMI2_DUAL_0_BASE + 0xC1)
6163 #define REG_HDMI2_DUAL_0_61_L       (REG_HDMI2_DUAL_0_BASE + 0xC2)
6164 #define REG_HDMI2_DUAL_0_61_H       (REG_HDMI2_DUAL_0_BASE + 0xC3)
6165 #define REG_HDMI2_DUAL_0_62_L       (REG_HDMI2_DUAL_0_BASE + 0xC4)
6166 #define REG_HDMI2_DUAL_0_62_H       (REG_HDMI2_DUAL_0_BASE + 0xC5)
6167 #define REG_HDMI2_DUAL_0_63_L       (REG_HDMI2_DUAL_0_BASE + 0xC6)
6168 #define REG_HDMI2_DUAL_0_63_H       (REG_HDMI2_DUAL_0_BASE + 0xC7)
6169 #define REG_HDMI2_DUAL_0_64_L       (REG_HDMI2_DUAL_0_BASE + 0xC8)
6170 #define REG_HDMI2_DUAL_0_64_H       (REG_HDMI2_DUAL_0_BASE + 0xC9)
6171 #define REG_HDMI2_DUAL_0_65_L       (REG_HDMI2_DUAL_0_BASE + 0xCA)
6172 #define REG_HDMI2_DUAL_0_65_H       (REG_HDMI2_DUAL_0_BASE + 0xCB)
6173 #define REG_HDMI2_DUAL_0_66_L       (REG_HDMI2_DUAL_0_BASE + 0xCC)
6174 #define REG_HDMI2_DUAL_0_66_H       (REG_HDMI2_DUAL_0_BASE + 0xCD)
6175 #define REG_HDMI2_DUAL_0_67_L       (REG_HDMI2_DUAL_0_BASE + 0xCE)
6176 #define REG_HDMI2_DUAL_0_67_H       (REG_HDMI2_DUAL_0_BASE + 0xCF)
6177 #define REG_HDMI2_DUAL_0_68_L       (REG_HDMI2_DUAL_0_BASE + 0xD0)
6178 #define REG_HDMI2_DUAL_0_68_H       (REG_HDMI2_DUAL_0_BASE + 0xD1)
6179 #define REG_HDMI2_DUAL_0_69_L       (REG_HDMI2_DUAL_0_BASE + 0xD2)
6180 #define REG_HDMI2_DUAL_0_69_H       (REG_HDMI2_DUAL_0_BASE + 0xD3)
6181 #define REG_HDMI2_DUAL_0_6A_L       (REG_HDMI2_DUAL_0_BASE + 0xD4)
6182 #define REG_HDMI2_DUAL_0_6A_H       (REG_HDMI2_DUAL_0_BASE + 0xD5)
6183 #define REG_HDMI2_DUAL_0_6B_L       (REG_HDMI2_DUAL_0_BASE + 0xD6)
6184 #define REG_HDMI2_DUAL_0_6B_H       (REG_HDMI2_DUAL_0_BASE + 0xD7)
6185 #define REG_HDMI2_DUAL_0_6C_L       (REG_HDMI2_DUAL_0_BASE + 0xD8)
6186 #define REG_HDMI2_DUAL_0_6C_H       (REG_HDMI2_DUAL_0_BASE + 0xD9)
6187 #define REG_HDMI2_DUAL_0_6D_L       (REG_HDMI2_DUAL_0_BASE + 0xDA)
6188 #define REG_HDMI2_DUAL_0_6D_H       (REG_HDMI2_DUAL_0_BASE + 0xDB)
6189 #define REG_HDMI2_DUAL_0_6E_L       (REG_HDMI2_DUAL_0_BASE + 0xDC)
6190 #define REG_HDMI2_DUAL_0_6E_H       (REG_HDMI2_DUAL_0_BASE + 0xDD)
6191 #define REG_HDMI2_DUAL_0_6F_L       (REG_HDMI2_DUAL_0_BASE + 0xDE)
6192 #define REG_HDMI2_DUAL_0_6F_H       (REG_HDMI2_DUAL_0_BASE + 0xDF)
6193 #define REG_HDMI2_DUAL_0_70_L       (REG_HDMI2_DUAL_0_BASE + 0xE0)
6194 #define REG_HDMI2_DUAL_0_70_H       (REG_HDMI2_DUAL_0_BASE + 0xE1)
6195 #define REG_HDMI2_DUAL_0_71_L       (REG_HDMI2_DUAL_0_BASE + 0xE2)
6196 #define REG_HDMI2_DUAL_0_71_H       (REG_HDMI2_DUAL_0_BASE + 0xE3)
6197 #define REG_HDMI2_DUAL_0_72_L       (REG_HDMI2_DUAL_0_BASE + 0xE4)
6198 #define REG_HDMI2_DUAL_0_72_H       (REG_HDMI2_DUAL_0_BASE + 0xE5)
6199 #define REG_HDMI2_DUAL_0_73_L       (REG_HDMI2_DUAL_0_BASE + 0xE6)
6200 #define REG_HDMI2_DUAL_0_73_H       (REG_HDMI2_DUAL_0_BASE + 0xE7)
6201 #define REG_HDMI2_DUAL_0_74_L       (REG_HDMI2_DUAL_0_BASE + 0xE8)
6202 #define REG_HDMI2_DUAL_0_74_H       (REG_HDMI2_DUAL_0_BASE + 0xE9)
6203 #define REG_HDMI2_DUAL_0_75_L       (REG_HDMI2_DUAL_0_BASE + 0xEA)
6204 #define REG_HDMI2_DUAL_0_75_H       (REG_HDMI2_DUAL_0_BASE + 0xEB)
6205 #define REG_HDMI2_DUAL_0_76_L       (REG_HDMI2_DUAL_0_BASE + 0xEC)
6206 #define REG_HDMI2_DUAL_0_76_H       (REG_HDMI2_DUAL_0_BASE + 0xED)
6207 #define REG_HDMI2_DUAL_0_77_L       (REG_HDMI2_DUAL_0_BASE + 0xEE)
6208 #define REG_HDMI2_DUAL_0_77_H       (REG_HDMI2_DUAL_0_BASE + 0xEF)
6209 #define REG_HDMI2_DUAL_0_78_L       (REG_HDMI2_DUAL_0_BASE + 0xF0)
6210 #define REG_HDMI2_DUAL_0_78_H       (REG_HDMI2_DUAL_0_BASE + 0xF1)
6211 #define REG_HDMI2_DUAL_0_79_L       (REG_HDMI2_DUAL_0_BASE + 0xF2)
6212 #define REG_HDMI2_DUAL_0_79_H       (REG_HDMI2_DUAL_0_BASE + 0xF3)
6213 #define REG_HDMI2_DUAL_0_7A_L       (REG_HDMI2_DUAL_0_BASE + 0xF4)
6214 #define REG_HDMI2_DUAL_0_7A_H       (REG_HDMI2_DUAL_0_BASE + 0xF5)
6215 #define REG_HDMI2_DUAL_0_7B_L       (REG_HDMI2_DUAL_0_BASE + 0xF6)
6216 #define REG_HDMI2_DUAL_0_7B_H       (REG_HDMI2_DUAL_0_BASE + 0xF7)
6217 #define REG_HDMI2_DUAL_0_7C_L       (REG_HDMI2_DUAL_0_BASE + 0xF8)
6218 #define REG_HDMI2_DUAL_0_7C_H       (REG_HDMI2_DUAL_0_BASE + 0xF9)
6219 #define REG_HDMI2_DUAL_0_7D_L       (REG_HDMI2_DUAL_0_BASE + 0xFA)
6220 #define REG_HDMI2_DUAL_0_7D_H       (REG_HDMI2_DUAL_0_BASE + 0xFB)
6221 #define REG_HDMI2_DUAL_0_7E_L       (REG_HDMI2_DUAL_0_BASE + 0xFC)
6222 #define REG_HDMI2_DUAL_0_7E_H       (REG_HDMI2_DUAL_0_BASE + 0xFD)
6223 #define REG_HDMI2_DUAL_0_7F_L       (REG_HDMI2_DUAL_0_BASE + 0xFE)
6224 #define REG_HDMI2_DUAL_0_7F_H       (REG_HDMI2_DUAL_0_BASE + 0xFF)
6225 
6226 // HDMI3_DUAL_0
6227 #define REG_HDMI3_DUAL_0_00_L       (REG_HDMI3_DUAL_0_BASE + 0x00)
6228 #define REG_HDMI3_DUAL_0_00_H       (REG_HDMI3_DUAL_0_BASE + 0x01)
6229 #define REG_HDMI3_DUAL_0_01_L       (REG_HDMI3_DUAL_0_BASE + 0x02)
6230 #define REG_HDMI3_DUAL_0_01_H       (REG_HDMI3_DUAL_0_BASE + 0x03)
6231 #define REG_HDMI3_DUAL_0_02_L       (REG_HDMI3_DUAL_0_BASE + 0x04)
6232 #define REG_HDMI3_DUAL_0_02_H       (REG_HDMI3_DUAL_0_BASE + 0x05)
6233 #define REG_HDMI3_DUAL_0_03_L       (REG_HDMI3_DUAL_0_BASE + 0x06)
6234 #define REG_HDMI3_DUAL_0_03_H       (REG_HDMI3_DUAL_0_BASE + 0x07)
6235 #define REG_HDMI3_DUAL_0_04_L       (REG_HDMI3_DUAL_0_BASE + 0x08)
6236 #define REG_HDMI3_DUAL_0_04_H       (REG_HDMI3_DUAL_0_BASE + 0x09)
6237 #define REG_HDMI3_DUAL_0_05_L       (REG_HDMI3_DUAL_0_BASE + 0x0A)
6238 #define REG_HDMI3_DUAL_0_05_H       (REG_HDMI3_DUAL_0_BASE + 0x0B)
6239 #define REG_HDMI3_DUAL_0_06_L       (REG_HDMI3_DUAL_0_BASE + 0x0C)
6240 #define REG_HDMI3_DUAL_0_06_H       (REG_HDMI3_DUAL_0_BASE + 0x0D)
6241 #define REG_HDMI3_DUAL_0_07_L       (REG_HDMI3_DUAL_0_BASE + 0x0E)
6242 #define REG_HDMI3_DUAL_0_07_H       (REG_HDMI3_DUAL_0_BASE + 0x0F)
6243 #define REG_HDMI3_DUAL_0_08_L       (REG_HDMI3_DUAL_0_BASE + 0x10)
6244 #define REG_HDMI3_DUAL_0_08_H       (REG_HDMI3_DUAL_0_BASE + 0x11)
6245 #define REG_HDMI3_DUAL_0_09_L       (REG_HDMI3_DUAL_0_BASE + 0x12)
6246 #define REG_HDMI3_DUAL_0_09_H       (REG_HDMI3_DUAL_0_BASE + 0x13)
6247 #define REG_HDMI3_DUAL_0_0A_L       (REG_HDMI3_DUAL_0_BASE + 0x14)
6248 #define REG_HDMI3_DUAL_0_0A_H       (REG_HDMI3_DUAL_0_BASE + 0x15)
6249 #define REG_HDMI3_DUAL_0_0B_L       (REG_HDMI3_DUAL_0_BASE + 0x16)
6250 #define REG_HDMI3_DUAL_0_0B_H       (REG_HDMI3_DUAL_0_BASE + 0x17)
6251 #define REG_HDMI3_DUAL_0_0C_L       (REG_HDMI3_DUAL_0_BASE + 0x18)
6252 #define REG_HDMI3_DUAL_0_0C_H       (REG_HDMI3_DUAL_0_BASE + 0x19)
6253 #define REG_HDMI3_DUAL_0_0D_L       (REG_HDMI3_DUAL_0_BASE + 0x1A)
6254 #define REG_HDMI3_DUAL_0_0D_H       (REG_HDMI3_DUAL_0_BASE + 0x1B)
6255 #define REG_HDMI3_DUAL_0_0E_L       (REG_HDMI3_DUAL_0_BASE + 0x1C)
6256 #define REG_HDMI3_DUAL_0_0E_H       (REG_HDMI3_DUAL_0_BASE + 0x1D)
6257 #define REG_HDMI3_DUAL_0_0F_L       (REG_HDMI3_DUAL_0_BASE + 0x1E)
6258 #define REG_HDMI3_DUAL_0_0F_H       (REG_HDMI3_DUAL_0_BASE + 0x1F)
6259 #define REG_HDMI3_DUAL_0_10_L       (REG_HDMI3_DUAL_0_BASE + 0x20)
6260 #define REG_HDMI3_DUAL_0_10_H       (REG_HDMI3_DUAL_0_BASE + 0x21)
6261 #define REG_HDMI3_DUAL_0_11_L       (REG_HDMI3_DUAL_0_BASE + 0x22)
6262 #define REG_HDMI3_DUAL_0_11_H       (REG_HDMI3_DUAL_0_BASE + 0x23)
6263 #define REG_HDMI3_DUAL_0_12_L       (REG_HDMI3_DUAL_0_BASE + 0x24)
6264 #define REG_HDMI3_DUAL_0_12_H       (REG_HDMI3_DUAL_0_BASE + 0x25)
6265 #define REG_HDMI3_DUAL_0_13_L       (REG_HDMI3_DUAL_0_BASE + 0x26)
6266 #define REG_HDMI3_DUAL_0_13_H       (REG_HDMI3_DUAL_0_BASE + 0x27)
6267 #define REG_HDMI3_DUAL_0_14_L       (REG_HDMI3_DUAL_0_BASE + 0x28)
6268 #define REG_HDMI3_DUAL_0_14_H       (REG_HDMI3_DUAL_0_BASE + 0x29)
6269 #define REG_HDMI3_DUAL_0_15_L       (REG_HDMI3_DUAL_0_BASE + 0x2A)
6270 #define REG_HDMI3_DUAL_0_15_H       (REG_HDMI3_DUAL_0_BASE + 0x2B)
6271 #define REG_HDMI3_DUAL_0_16_L       (REG_HDMI3_DUAL_0_BASE + 0x2C)
6272 #define REG_HDMI3_DUAL_0_16_H       (REG_HDMI3_DUAL_0_BASE + 0x2D)
6273 #define REG_HDMI3_DUAL_0_17_L       (REG_HDMI3_DUAL_0_BASE + 0x2E)
6274 #define REG_HDMI3_DUAL_0_17_H       (REG_HDMI3_DUAL_0_BASE + 0x2F)
6275 #define REG_HDMI3_DUAL_0_18_L       (REG_HDMI3_DUAL_0_BASE + 0x30)
6276 #define REG_HDMI3_DUAL_0_18_H       (REG_HDMI3_DUAL_0_BASE + 0x31)
6277 #define REG_HDMI3_DUAL_0_19_L       (REG_HDMI3_DUAL_0_BASE + 0x32)
6278 #define REG_HDMI3_DUAL_0_19_H       (REG_HDMI3_DUAL_0_BASE + 0x33)
6279 #define REG_HDMI3_DUAL_0_1A_L       (REG_HDMI3_DUAL_0_BASE + 0x34)
6280 #define REG_HDMI3_DUAL_0_1A_H       (REG_HDMI3_DUAL_0_BASE + 0x35)
6281 #define REG_HDMI3_DUAL_0_1B_L       (REG_HDMI3_DUAL_0_BASE + 0x36)
6282 #define REG_HDMI3_DUAL_0_1B_H       (REG_HDMI3_DUAL_0_BASE + 0x37)
6283 #define REG_HDMI3_DUAL_0_1C_L       (REG_HDMI3_DUAL_0_BASE + 0x38)
6284 #define REG_HDMI3_DUAL_0_1C_H       (REG_HDMI3_DUAL_0_BASE + 0x39)
6285 #define REG_HDMI3_DUAL_0_1D_L       (REG_HDMI3_DUAL_0_BASE + 0x3A)
6286 #define REG_HDMI3_DUAL_0_1D_H       (REG_HDMI3_DUAL_0_BASE + 0x3B)
6287 #define REG_HDMI3_DUAL_0_1E_L       (REG_HDMI3_DUAL_0_BASE + 0x3C)
6288 #define REG_HDMI3_DUAL_0_1E_H       (REG_HDMI3_DUAL_0_BASE + 0x3D)
6289 #define REG_HDMI3_DUAL_0_1F_L       (REG_HDMI3_DUAL_0_BASE + 0x3E)
6290 #define REG_HDMI3_DUAL_0_1F_H       (REG_HDMI3_DUAL_0_BASE + 0x3F)
6291 #define REG_HDMI3_DUAL_0_20_L       (REG_HDMI3_DUAL_0_BASE + 0x40)
6292 #define REG_HDMI3_DUAL_0_20_H       (REG_HDMI3_DUAL_0_BASE + 0x41)
6293 #define REG_HDMI3_DUAL_0_21_L       (REG_HDMI3_DUAL_0_BASE + 0x42)
6294 #define REG_HDMI3_DUAL_0_21_H       (REG_HDMI3_DUAL_0_BASE + 0x43)
6295 #define REG_HDMI3_DUAL_0_22_L       (REG_HDMI3_DUAL_0_BASE + 0x44)
6296 #define REG_HDMI3_DUAL_0_22_H       (REG_HDMI3_DUAL_0_BASE + 0x45)
6297 #define REG_HDMI3_DUAL_0_23_L       (REG_HDMI3_DUAL_0_BASE + 0x46)
6298 #define REG_HDMI3_DUAL_0_23_H       (REG_HDMI3_DUAL_0_BASE + 0x47)
6299 #define REG_HDMI3_DUAL_0_24_L       (REG_HDMI3_DUAL_0_BASE + 0x48)
6300 #define REG_HDMI3_DUAL_0_24_H       (REG_HDMI3_DUAL_0_BASE + 0x49)
6301 #define REG_HDMI3_DUAL_0_25_L       (REG_HDMI3_DUAL_0_BASE + 0x4A)
6302 #define REG_HDMI3_DUAL_0_25_H       (REG_HDMI3_DUAL_0_BASE + 0x4B)
6303 #define REG_HDMI3_DUAL_0_26_L       (REG_HDMI3_DUAL_0_BASE + 0x4C)
6304 #define REG_HDMI3_DUAL_0_26_H       (REG_HDMI3_DUAL_0_BASE + 0x4D)
6305 #define REG_HDMI3_DUAL_0_27_L       (REG_HDMI3_DUAL_0_BASE + 0x4E)
6306 #define REG_HDMI3_DUAL_0_27_H       (REG_HDMI3_DUAL_0_BASE + 0x4F)
6307 #define REG_HDMI3_DUAL_0_28_L       (REG_HDMI3_DUAL_0_BASE + 0x50)
6308 #define REG_HDMI3_DUAL_0_28_H       (REG_HDMI3_DUAL_0_BASE + 0x51)
6309 #define REG_HDMI3_DUAL_0_29_L       (REG_HDMI3_DUAL_0_BASE + 0x52)
6310 #define REG_HDMI3_DUAL_0_29_H       (REG_HDMI3_DUAL_0_BASE + 0x53)
6311 #define REG_HDMI3_DUAL_0_2A_L       (REG_HDMI3_DUAL_0_BASE + 0x54)
6312 #define REG_HDMI3_DUAL_0_2A_H       (REG_HDMI3_DUAL_0_BASE + 0x55)
6313 #define REG_HDMI3_DUAL_0_2B_L       (REG_HDMI3_DUAL_0_BASE + 0x56)
6314 #define REG_HDMI3_DUAL_0_2B_H       (REG_HDMI3_DUAL_0_BASE + 0x57)
6315 #define REG_HDMI3_DUAL_0_2C_L       (REG_HDMI3_DUAL_0_BASE + 0x58)
6316 #define REG_HDMI3_DUAL_0_2C_H       (REG_HDMI3_DUAL_0_BASE + 0x59)
6317 #define REG_HDMI3_DUAL_0_2D_L       (REG_HDMI3_DUAL_0_BASE + 0x5A)
6318 #define REG_HDMI3_DUAL_0_2D_H       (REG_HDMI3_DUAL_0_BASE + 0x5B)
6319 #define REG_HDMI3_DUAL_0_2E_L       (REG_HDMI3_DUAL_0_BASE + 0x5C)
6320 #define REG_HDMI3_DUAL_0_2E_H       (REG_HDMI3_DUAL_0_BASE + 0x5D)
6321 #define REG_HDMI3_DUAL_0_2F_L       (REG_HDMI3_DUAL_0_BASE + 0x5E)
6322 #define REG_HDMI3_DUAL_0_2F_H       (REG_HDMI3_DUAL_0_BASE + 0x5F)
6323 #define REG_HDMI3_DUAL_0_30_L       (REG_HDMI3_DUAL_0_BASE + 0x60)
6324 #define REG_HDMI3_DUAL_0_30_H       (REG_HDMI3_DUAL_0_BASE + 0x61)
6325 #define REG_HDMI3_DUAL_0_31_L       (REG_HDMI3_DUAL_0_BASE + 0x62)
6326 #define REG_HDMI3_DUAL_0_31_H       (REG_HDMI3_DUAL_0_BASE + 0x63)
6327 #define REG_HDMI3_DUAL_0_32_L       (REG_HDMI3_DUAL_0_BASE + 0x64)
6328 #define REG_HDMI3_DUAL_0_32_H       (REG_HDMI3_DUAL_0_BASE + 0x65)
6329 #define REG_HDMI3_DUAL_0_33_L       (REG_HDMI3_DUAL_0_BASE + 0x66)
6330 #define REG_HDMI3_DUAL_0_33_H       (REG_HDMI3_DUAL_0_BASE + 0x67)
6331 #define REG_HDMI3_DUAL_0_34_L       (REG_HDMI3_DUAL_0_BASE + 0x68)
6332 #define REG_HDMI3_DUAL_0_34_H       (REG_HDMI3_DUAL_0_BASE + 0x69)
6333 #define REG_HDMI3_DUAL_0_35_L       (REG_HDMI3_DUAL_0_BASE + 0x6A)
6334 #define REG_HDMI3_DUAL_0_35_H       (REG_HDMI3_DUAL_0_BASE + 0x6B)
6335 #define REG_HDMI3_DUAL_0_36_L       (REG_HDMI3_DUAL_0_BASE + 0x6C)
6336 #define REG_HDMI3_DUAL_0_36_H       (REG_HDMI3_DUAL_0_BASE + 0x6D)
6337 #define REG_HDMI3_DUAL_0_37_L       (REG_HDMI3_DUAL_0_BASE + 0x6E)
6338 #define REG_HDMI3_DUAL_0_37_H       (REG_HDMI3_DUAL_0_BASE + 0x6F)
6339 #define REG_HDMI3_DUAL_0_38_L       (REG_HDMI3_DUAL_0_BASE + 0x70)
6340 #define REG_HDMI3_DUAL_0_38_H       (REG_HDMI3_DUAL_0_BASE + 0x71)
6341 #define REG_HDMI3_DUAL_0_39_L       (REG_HDMI3_DUAL_0_BASE + 0x72)
6342 #define REG_HDMI3_DUAL_0_39_H       (REG_HDMI3_DUAL_0_BASE + 0x73)
6343 #define REG_HDMI3_DUAL_0_3A_L       (REG_HDMI3_DUAL_0_BASE + 0x74)
6344 #define REG_HDMI3_DUAL_0_3A_H       (REG_HDMI3_DUAL_0_BASE + 0x75)
6345 #define REG_HDMI3_DUAL_0_3B_L       (REG_HDMI3_DUAL_0_BASE + 0x76)
6346 #define REG_HDMI3_DUAL_0_3B_H       (REG_HDMI3_DUAL_0_BASE + 0x77)
6347 #define REG_HDMI3_DUAL_0_3C_L       (REG_HDMI3_DUAL_0_BASE + 0x78)
6348 #define REG_HDMI3_DUAL_0_3C_H       (REG_HDMI3_DUAL_0_BASE + 0x79)
6349 #define REG_HDMI3_DUAL_0_3D_L       (REG_HDMI3_DUAL_0_BASE + 0x7A)
6350 #define REG_HDMI3_DUAL_0_3D_H       (REG_HDMI3_DUAL_0_BASE + 0x7B)
6351 #define REG_HDMI3_DUAL_0_3E_L       (REG_HDMI3_DUAL_0_BASE + 0x7C)
6352 #define REG_HDMI3_DUAL_0_3E_H       (REG_HDMI3_DUAL_0_BASE + 0x7D)
6353 #define REG_HDMI3_DUAL_0_3F_L       (REG_HDMI3_DUAL_0_BASE + 0x7E)
6354 #define REG_HDMI3_DUAL_0_3F_H       (REG_HDMI3_DUAL_0_BASE + 0x7F)
6355 #define REG_HDMI3_DUAL_0_40_L       (REG_HDMI3_DUAL_0_BASE + 0x80)
6356 #define REG_HDMI3_DUAL_0_40_H       (REG_HDMI3_DUAL_0_BASE + 0x81)
6357 #define REG_HDMI3_DUAL_0_41_L       (REG_HDMI3_DUAL_0_BASE + 0x82)
6358 #define REG_HDMI3_DUAL_0_41_H       (REG_HDMI3_DUAL_0_BASE + 0x83)
6359 #define REG_HDMI3_DUAL_0_42_L       (REG_HDMI3_DUAL_0_BASE + 0x84)
6360 #define REG_HDMI3_DUAL_0_42_H       (REG_HDMI3_DUAL_0_BASE + 0x85)
6361 #define REG_HDMI3_DUAL_0_43_L       (REG_HDMI3_DUAL_0_BASE + 0x86)
6362 #define REG_HDMI3_DUAL_0_43_H       (REG_HDMI3_DUAL_0_BASE + 0x87)
6363 #define REG_HDMI3_DUAL_0_44_L       (REG_HDMI3_DUAL_0_BASE + 0x88)
6364 #define REG_HDMI3_DUAL_0_44_H       (REG_HDMI3_DUAL_0_BASE + 0x89)
6365 #define REG_HDMI3_DUAL_0_45_L       (REG_HDMI3_DUAL_0_BASE + 0x8A)
6366 #define REG_HDMI3_DUAL_0_45_H       (REG_HDMI3_DUAL_0_BASE + 0x8B)
6367 #define REG_HDMI3_DUAL_0_46_L       (REG_HDMI3_DUAL_0_BASE + 0x8C)
6368 #define REG_HDMI3_DUAL_0_46_H       (REG_HDMI3_DUAL_0_BASE + 0x8D)
6369 #define REG_HDMI3_DUAL_0_47_L       (REG_HDMI3_DUAL_0_BASE + 0x8E)
6370 #define REG_HDMI3_DUAL_0_47_H       (REG_HDMI3_DUAL_0_BASE + 0x8F)
6371 #define REG_HDMI3_DUAL_0_48_L       (REG_HDMI3_DUAL_0_BASE + 0x90)
6372 #define REG_HDMI3_DUAL_0_48_H       (REG_HDMI3_DUAL_0_BASE + 0x91)
6373 #define REG_HDMI3_DUAL_0_49_L       (REG_HDMI3_DUAL_0_BASE + 0x92)
6374 #define REG_HDMI3_DUAL_0_49_H       (REG_HDMI3_DUAL_0_BASE + 0x93)
6375 #define REG_HDMI3_DUAL_0_4A_L       (REG_HDMI3_DUAL_0_BASE + 0x94)
6376 #define REG_HDMI3_DUAL_0_4A_H       (REG_HDMI3_DUAL_0_BASE + 0x95)
6377 #define REG_HDMI3_DUAL_0_4B_L       (REG_HDMI3_DUAL_0_BASE + 0x96)
6378 #define REG_HDMI3_DUAL_0_4B_H       (REG_HDMI3_DUAL_0_BASE + 0x97)
6379 #define REG_HDMI3_DUAL_0_4C_L       (REG_HDMI3_DUAL_0_BASE + 0x98)
6380 #define REG_HDMI3_DUAL_0_4C_H       (REG_HDMI3_DUAL_0_BASE + 0x99)
6381 #define REG_HDMI3_DUAL_0_4D_L       (REG_HDMI3_DUAL_0_BASE + 0x9A)
6382 #define REG_HDMI3_DUAL_0_4D_H       (REG_HDMI3_DUAL_0_BASE + 0x9B)
6383 #define REG_HDMI3_DUAL_0_4E_L       (REG_HDMI3_DUAL_0_BASE + 0x9C)
6384 #define REG_HDMI3_DUAL_0_4E_H       (REG_HDMI3_DUAL_0_BASE + 0x9D)
6385 #define REG_HDMI3_DUAL_0_4F_L       (REG_HDMI3_DUAL_0_BASE + 0x9E)
6386 #define REG_HDMI3_DUAL_0_4F_H       (REG_HDMI3_DUAL_0_BASE + 0x9F)
6387 #define REG_HDMI3_DUAL_0_50_L       (REG_HDMI3_DUAL_0_BASE + 0xA0)
6388 #define REG_HDMI3_DUAL_0_50_H       (REG_HDMI3_DUAL_0_BASE + 0xA1)
6389 #define REG_HDMI3_DUAL_0_51_L       (REG_HDMI3_DUAL_0_BASE + 0xA2)
6390 #define REG_HDMI3_DUAL_0_51_H       (REG_HDMI3_DUAL_0_BASE + 0xA3)
6391 #define REG_HDMI3_DUAL_0_52_L       (REG_HDMI3_DUAL_0_BASE + 0xA4)
6392 #define REG_HDMI3_DUAL_0_52_H       (REG_HDMI3_DUAL_0_BASE + 0xA5)
6393 #define REG_HDMI3_DUAL_0_53_L       (REG_HDMI3_DUAL_0_BASE + 0xA6)
6394 #define REG_HDMI3_DUAL_0_53_H       (REG_HDMI3_DUAL_0_BASE + 0xA7)
6395 #define REG_HDMI3_DUAL_0_54_L       (REG_HDMI3_DUAL_0_BASE + 0xA8)
6396 #define REG_HDMI3_DUAL_0_54_H       (REG_HDMI3_DUAL_0_BASE + 0xA9)
6397 #define REG_HDMI3_DUAL_0_55_L       (REG_HDMI3_DUAL_0_BASE + 0xAA)
6398 #define REG_HDMI3_DUAL_0_55_H       (REG_HDMI3_DUAL_0_BASE + 0xAB)
6399 #define REG_HDMI3_DUAL_0_56_L       (REG_HDMI3_DUAL_0_BASE + 0xAC)
6400 #define REG_HDMI3_DUAL_0_56_H       (REG_HDMI3_DUAL_0_BASE + 0xAD)
6401 #define REG_HDMI3_DUAL_0_57_L       (REG_HDMI3_DUAL_0_BASE + 0xAE)
6402 #define REG_HDMI3_DUAL_0_57_H       (REG_HDMI3_DUAL_0_BASE + 0xAF)
6403 #define REG_HDMI3_DUAL_0_58_L       (REG_HDMI3_DUAL_0_BASE + 0xB0)
6404 #define REG_HDMI3_DUAL_0_58_H       (REG_HDMI3_DUAL_0_BASE + 0xB1)
6405 #define REG_HDMI3_DUAL_0_59_L       (REG_HDMI3_DUAL_0_BASE + 0xB2)
6406 #define REG_HDMI3_DUAL_0_59_H       (REG_HDMI3_DUAL_0_BASE + 0xB3)
6407 #define REG_HDMI3_DUAL_0_5A_L       (REG_HDMI3_DUAL_0_BASE + 0xB4)
6408 #define REG_HDMI3_DUAL_0_5A_H       (REG_HDMI3_DUAL_0_BASE + 0xB5)
6409 #define REG_HDMI3_DUAL_0_5B_L       (REG_HDMI3_DUAL_0_BASE + 0xB6)
6410 #define REG_HDMI3_DUAL_0_5B_H       (REG_HDMI3_DUAL_0_BASE + 0xB7)
6411 #define REG_HDMI3_DUAL_0_5C_L       (REG_HDMI3_DUAL_0_BASE + 0xB8)
6412 #define REG_HDMI3_DUAL_0_5C_H       (REG_HDMI3_DUAL_0_BASE + 0xB9)
6413 #define REG_HDMI3_DUAL_0_5D_L       (REG_HDMI3_DUAL_0_BASE + 0xBA)
6414 #define REG_HDMI3_DUAL_0_5D_H       (REG_HDMI3_DUAL_0_BASE + 0xBB)
6415 #define REG_HDMI3_DUAL_0_5E_L       (REG_HDMI3_DUAL_0_BASE + 0xBC)
6416 #define REG_HDMI3_DUAL_0_5E_H       (REG_HDMI3_DUAL_0_BASE + 0xBD)
6417 #define REG_HDMI3_DUAL_0_5F_L       (REG_HDMI3_DUAL_0_BASE + 0xBE)
6418 #define REG_HDMI3_DUAL_0_5F_H       (REG_HDMI3_DUAL_0_BASE + 0xBF)
6419 #define REG_HDMI3_DUAL_0_60_L       (REG_HDMI3_DUAL_0_BASE + 0xC0)
6420 #define REG_HDMI3_DUAL_0_60_H       (REG_HDMI3_DUAL_0_BASE + 0xC1)
6421 #define REG_HDMI3_DUAL_0_61_L       (REG_HDMI3_DUAL_0_BASE + 0xC2)
6422 #define REG_HDMI3_DUAL_0_61_H       (REG_HDMI3_DUAL_0_BASE + 0xC3)
6423 #define REG_HDMI3_DUAL_0_62_L       (REG_HDMI3_DUAL_0_BASE + 0xC4)
6424 #define REG_HDMI3_DUAL_0_62_H       (REG_HDMI3_DUAL_0_BASE + 0xC5)
6425 #define REG_HDMI3_DUAL_0_63_L       (REG_HDMI3_DUAL_0_BASE + 0xC6)
6426 #define REG_HDMI3_DUAL_0_63_H       (REG_HDMI3_DUAL_0_BASE + 0xC7)
6427 #define REG_HDMI3_DUAL_0_64_L       (REG_HDMI3_DUAL_0_BASE + 0xC8)
6428 #define REG_HDMI3_DUAL_0_64_H       (REG_HDMI3_DUAL_0_BASE + 0xC9)
6429 #define REG_HDMI3_DUAL_0_65_L       (REG_HDMI3_DUAL_0_BASE + 0xCA)
6430 #define REG_HDMI3_DUAL_0_65_H       (REG_HDMI3_DUAL_0_BASE + 0xCB)
6431 #define REG_HDMI3_DUAL_0_66_L       (REG_HDMI3_DUAL_0_BASE + 0xCC)
6432 #define REG_HDMI3_DUAL_0_66_H       (REG_HDMI3_DUAL_0_BASE + 0xCD)
6433 #define REG_HDMI3_DUAL_0_67_L       (REG_HDMI3_DUAL_0_BASE + 0xCE)
6434 #define REG_HDMI3_DUAL_0_67_H       (REG_HDMI3_DUAL_0_BASE + 0xCF)
6435 #define REG_HDMI3_DUAL_0_68_L       (REG_HDMI3_DUAL_0_BASE + 0xD0)
6436 #define REG_HDMI3_DUAL_0_68_H       (REG_HDMI3_DUAL_0_BASE + 0xD1)
6437 #define REG_HDMI3_DUAL_0_69_L       (REG_HDMI3_DUAL_0_BASE + 0xD2)
6438 #define REG_HDMI3_DUAL_0_69_H       (REG_HDMI3_DUAL_0_BASE + 0xD3)
6439 #define REG_HDMI3_DUAL_0_6A_L       (REG_HDMI3_DUAL_0_BASE + 0xD4)
6440 #define REG_HDMI3_DUAL_0_6A_H       (REG_HDMI3_DUAL_0_BASE + 0xD5)
6441 #define REG_HDMI3_DUAL_0_6B_L       (REG_HDMI3_DUAL_0_BASE + 0xD6)
6442 #define REG_HDMI3_DUAL_0_6B_H       (REG_HDMI3_DUAL_0_BASE + 0xD7)
6443 #define REG_HDMI3_DUAL_0_6C_L       (REG_HDMI3_DUAL_0_BASE + 0xD8)
6444 #define REG_HDMI3_DUAL_0_6C_H       (REG_HDMI3_DUAL_0_BASE + 0xD9)
6445 #define REG_HDMI3_DUAL_0_6D_L       (REG_HDMI3_DUAL_0_BASE + 0xDA)
6446 #define REG_HDMI3_DUAL_0_6D_H       (REG_HDMI3_DUAL_0_BASE + 0xDB)
6447 #define REG_HDMI3_DUAL_0_6E_L       (REG_HDMI3_DUAL_0_BASE + 0xDC)
6448 #define REG_HDMI3_DUAL_0_6E_H       (REG_HDMI3_DUAL_0_BASE + 0xDD)
6449 #define REG_HDMI3_DUAL_0_6F_L       (REG_HDMI3_DUAL_0_BASE + 0xDE)
6450 #define REG_HDMI3_DUAL_0_6F_H       (REG_HDMI3_DUAL_0_BASE + 0xDF)
6451 #define REG_HDMI3_DUAL_0_70_L       (REG_HDMI3_DUAL_0_BASE + 0xE0)
6452 #define REG_HDMI3_DUAL_0_70_H       (REG_HDMI3_DUAL_0_BASE + 0xE1)
6453 #define REG_HDMI3_DUAL_0_71_L       (REG_HDMI3_DUAL_0_BASE + 0xE2)
6454 #define REG_HDMI3_DUAL_0_71_H       (REG_HDMI3_DUAL_0_BASE + 0xE3)
6455 #define REG_HDMI3_DUAL_0_72_L       (REG_HDMI3_DUAL_0_BASE + 0xE4)
6456 #define REG_HDMI3_DUAL_0_72_H       (REG_HDMI3_DUAL_0_BASE + 0xE5)
6457 #define REG_HDMI3_DUAL_0_73_L       (REG_HDMI3_DUAL_0_BASE + 0xE6)
6458 #define REG_HDMI3_DUAL_0_73_H       (REG_HDMI3_DUAL_0_BASE + 0xE7)
6459 #define REG_HDMI3_DUAL_0_74_L       (REG_HDMI3_DUAL_0_BASE + 0xE8)
6460 #define REG_HDMI3_DUAL_0_74_H       (REG_HDMI3_DUAL_0_BASE + 0xE9)
6461 #define REG_HDMI3_DUAL_0_75_L       (REG_HDMI3_DUAL_0_BASE + 0xEA)
6462 #define REG_HDMI3_DUAL_0_75_H       (REG_HDMI3_DUAL_0_BASE + 0xEB)
6463 #define REG_HDMI3_DUAL_0_76_L       (REG_HDMI3_DUAL_0_BASE + 0xEC)
6464 #define REG_HDMI3_DUAL_0_76_H       (REG_HDMI3_DUAL_0_BASE + 0xED)
6465 #define REG_HDMI3_DUAL_0_77_L       (REG_HDMI3_DUAL_0_BASE + 0xEE)
6466 #define REG_HDMI3_DUAL_0_77_H       (REG_HDMI3_DUAL_0_BASE + 0xEF)
6467 #define REG_HDMI3_DUAL_0_78_L       (REG_HDMI3_DUAL_0_BASE + 0xF0)
6468 #define REG_HDMI3_DUAL_0_78_H       (REG_HDMI3_DUAL_0_BASE + 0xF1)
6469 #define REG_HDMI3_DUAL_0_79_L       (REG_HDMI3_DUAL_0_BASE + 0xF2)
6470 #define REG_HDMI3_DUAL_0_79_H       (REG_HDMI3_DUAL_0_BASE + 0xF3)
6471 #define REG_HDMI3_DUAL_0_7A_L       (REG_HDMI3_DUAL_0_BASE + 0xF4)
6472 #define REG_HDMI3_DUAL_0_7A_H       (REG_HDMI3_DUAL_0_BASE + 0xF5)
6473 #define REG_HDMI3_DUAL_0_7B_L       (REG_HDMI3_DUAL_0_BASE + 0xF6)
6474 #define REG_HDMI3_DUAL_0_7B_H       (REG_HDMI3_DUAL_0_BASE + 0xF7)
6475 #define REG_HDMI3_DUAL_0_7C_L       (REG_HDMI3_DUAL_0_BASE + 0xF8)
6476 #define REG_HDMI3_DUAL_0_7C_H       (REG_HDMI3_DUAL_0_BASE + 0xF9)
6477 #define REG_HDMI3_DUAL_0_7D_L       (REG_HDMI3_DUAL_0_BASE + 0xFA)
6478 #define REG_HDMI3_DUAL_0_7D_H       (REG_HDMI3_DUAL_0_BASE + 0xFB)
6479 #define REG_HDMI3_DUAL_0_7E_L       (REG_HDMI3_DUAL_0_BASE + 0xFC)
6480 #define REG_HDMI3_DUAL_0_7E_H       (REG_HDMI3_DUAL_0_BASE + 0xFD)
6481 #define REG_HDMI3_DUAL_0_7F_L       (REG_HDMI3_DUAL_0_BASE + 0xFE)
6482 #define REG_HDMI3_DUAL_0_7F_H       (REG_HDMI3_DUAL_0_BASE + 0xFF)
6483 
6484 //=============================================================
6485 // COMBO_GP_TOP
6486 #define REG_COMBO_GP_TOP_00_L       (REG_COMBO_GP_TOP_BASE + 0x00)
6487 #define REG_COMBO_GP_TOP_00_H       (REG_COMBO_GP_TOP_BASE + 0x01)
6488 #define REG_COMBO_GP_TOP_01_L       (REG_COMBO_GP_TOP_BASE + 0x02)
6489 #define REG_COMBO_GP_TOP_01_H       (REG_COMBO_GP_TOP_BASE + 0x03)
6490 #define REG_COMBO_GP_TOP_02_L       (REG_COMBO_GP_TOP_BASE + 0x04)
6491 #define REG_COMBO_GP_TOP_02_H       (REG_COMBO_GP_TOP_BASE + 0x05)
6492 #define REG_COMBO_GP_TOP_03_L       (REG_COMBO_GP_TOP_BASE + 0x06)
6493 #define REG_COMBO_GP_TOP_03_H       (REG_COMBO_GP_TOP_BASE + 0x07)
6494 #define REG_COMBO_GP_TOP_04_L       (REG_COMBO_GP_TOP_BASE + 0x08)
6495 #define REG_COMBO_GP_TOP_04_H       (REG_COMBO_GP_TOP_BASE + 0x09)
6496 #define REG_COMBO_GP_TOP_05_L       (REG_COMBO_GP_TOP_BASE + 0x0A)
6497 #define REG_COMBO_GP_TOP_05_H       (REG_COMBO_GP_TOP_BASE + 0x0B)
6498 #define REG_COMBO_GP_TOP_06_L       (REG_COMBO_GP_TOP_BASE + 0x0C)
6499 #define REG_COMBO_GP_TOP_06_H       (REG_COMBO_GP_TOP_BASE + 0x0D)
6500 #define REG_COMBO_GP_TOP_07_L       (REG_COMBO_GP_TOP_BASE + 0x0E)
6501 #define REG_COMBO_GP_TOP_07_H       (REG_COMBO_GP_TOP_BASE + 0x0F)
6502 #define REG_COMBO_GP_TOP_08_L       (REG_COMBO_GP_TOP_BASE + 0x10)
6503 #define REG_COMBO_GP_TOP_08_H       (REG_COMBO_GP_TOP_BASE + 0x11)
6504 #define REG_COMBO_GP_TOP_09_L       (REG_COMBO_GP_TOP_BASE + 0x12)
6505 #define REG_COMBO_GP_TOP_09_H       (REG_COMBO_GP_TOP_BASE + 0x13)
6506 #define REG_COMBO_GP_TOP_0A_L       (REG_COMBO_GP_TOP_BASE + 0x14)
6507 #define REG_COMBO_GP_TOP_0A_H       (REG_COMBO_GP_TOP_BASE + 0x15)
6508 #define REG_COMBO_GP_TOP_0B_L       (REG_COMBO_GP_TOP_BASE + 0x16)
6509 #define REG_COMBO_GP_TOP_0B_H       (REG_COMBO_GP_TOP_BASE + 0x17)
6510 #define REG_COMBO_GP_TOP_0C_L       (REG_COMBO_GP_TOP_BASE + 0x18)
6511 #define REG_COMBO_GP_TOP_0C_H       (REG_COMBO_GP_TOP_BASE + 0x19)
6512 #define REG_COMBO_GP_TOP_0D_L       (REG_COMBO_GP_TOP_BASE + 0x1A)
6513 #define REG_COMBO_GP_TOP_0D_H       (REG_COMBO_GP_TOP_BASE + 0x1B)
6514 #define REG_COMBO_GP_TOP_0E_L       (REG_COMBO_GP_TOP_BASE + 0x1C)
6515 #define REG_COMBO_GP_TOP_0E_H       (REG_COMBO_GP_TOP_BASE + 0x1D)
6516 #define REG_COMBO_GP_TOP_0F_L       (REG_COMBO_GP_TOP_BASE + 0x1E)
6517 #define REG_COMBO_GP_TOP_0F_H       (REG_COMBO_GP_TOP_BASE + 0x1F)
6518 #define REG_COMBO_GP_TOP_10_L       (REG_COMBO_GP_TOP_BASE + 0x20)
6519 #define REG_COMBO_GP_TOP_10_H       (REG_COMBO_GP_TOP_BASE + 0x21)
6520 #define REG_COMBO_GP_TOP_11_L       (REG_COMBO_GP_TOP_BASE + 0x22)
6521 #define REG_COMBO_GP_TOP_11_H       (REG_COMBO_GP_TOP_BASE + 0x23)
6522 #define REG_COMBO_GP_TOP_12_L       (REG_COMBO_GP_TOP_BASE + 0x24)
6523 #define REG_COMBO_GP_TOP_12_H       (REG_COMBO_GP_TOP_BASE + 0x25)
6524 #define REG_COMBO_GP_TOP_13_L       (REG_COMBO_GP_TOP_BASE + 0x26)
6525 #define REG_COMBO_GP_TOP_13_H       (REG_COMBO_GP_TOP_BASE + 0x27)
6526 #define REG_COMBO_GP_TOP_14_L       (REG_COMBO_GP_TOP_BASE + 0x28)
6527 #define REG_COMBO_GP_TOP_14_H       (REG_COMBO_GP_TOP_BASE + 0x29)
6528 #define REG_COMBO_GP_TOP_15_L       (REG_COMBO_GP_TOP_BASE + 0x2A)
6529 #define REG_COMBO_GP_TOP_15_H       (REG_COMBO_GP_TOP_BASE + 0x2B)
6530 #define REG_COMBO_GP_TOP_16_L       (REG_COMBO_GP_TOP_BASE + 0x2C)
6531 #define REG_COMBO_GP_TOP_16_H       (REG_COMBO_GP_TOP_BASE + 0x2D)
6532 #define REG_COMBO_GP_TOP_17_L       (REG_COMBO_GP_TOP_BASE + 0x2E)
6533 #define REG_COMBO_GP_TOP_17_H       (REG_COMBO_GP_TOP_BASE + 0x2F)
6534 #define REG_COMBO_GP_TOP_18_L       (REG_COMBO_GP_TOP_BASE + 0x30)
6535 #define REG_COMBO_GP_TOP_18_H       (REG_COMBO_GP_TOP_BASE + 0x31)
6536 #define REG_COMBO_GP_TOP_19_L       (REG_COMBO_GP_TOP_BASE + 0x32)
6537 #define REG_COMBO_GP_TOP_19_H       (REG_COMBO_GP_TOP_BASE + 0x33)
6538 #define REG_COMBO_GP_TOP_1A_L       (REG_COMBO_GP_TOP_BASE + 0x34)
6539 #define REG_COMBO_GP_TOP_1A_H       (REG_COMBO_GP_TOP_BASE + 0x35)
6540 #define REG_COMBO_GP_TOP_1B_L       (REG_COMBO_GP_TOP_BASE + 0x36)
6541 #define REG_COMBO_GP_TOP_1B_H       (REG_COMBO_GP_TOP_BASE + 0x37)
6542 #define REG_COMBO_GP_TOP_1C_L       (REG_COMBO_GP_TOP_BASE + 0x38)
6543 #define REG_COMBO_GP_TOP_1C_H       (REG_COMBO_GP_TOP_BASE + 0x39)
6544 #define REG_COMBO_GP_TOP_1D_L       (REG_COMBO_GP_TOP_BASE + 0x3A)
6545 #define REG_COMBO_GP_TOP_1D_H       (REG_COMBO_GP_TOP_BASE + 0x3B)
6546 #define REG_COMBO_GP_TOP_1E_L       (REG_COMBO_GP_TOP_BASE + 0x3C)
6547 #define REG_COMBO_GP_TOP_1E_H       (REG_COMBO_GP_TOP_BASE + 0x3D)
6548 #define REG_COMBO_GP_TOP_1F_L       (REG_COMBO_GP_TOP_BASE + 0x3E)
6549 #define REG_COMBO_GP_TOP_1F_H       (REG_COMBO_GP_TOP_BASE + 0x3F)
6550 #define REG_COMBO_GP_TOP_20_L       (REG_COMBO_GP_TOP_BASE + 0x40)
6551 #define REG_COMBO_GP_TOP_20_H       (REG_COMBO_GP_TOP_BASE + 0x41)
6552 #define REG_COMBO_GP_TOP_21_L       (REG_COMBO_GP_TOP_BASE + 0x42)
6553 #define REG_COMBO_GP_TOP_21_H       (REG_COMBO_GP_TOP_BASE + 0x43)
6554 #define REG_COMBO_GP_TOP_22_L       (REG_COMBO_GP_TOP_BASE + 0x44)
6555 #define REG_COMBO_GP_TOP_22_H       (REG_COMBO_GP_TOP_BASE + 0x45)
6556 #define REG_COMBO_GP_TOP_23_L       (REG_COMBO_GP_TOP_BASE + 0x46)
6557 #define REG_COMBO_GP_TOP_23_H       (REG_COMBO_GP_TOP_BASE + 0x47)
6558 #define REG_COMBO_GP_TOP_24_L       (REG_COMBO_GP_TOP_BASE + 0x48)
6559 #define REG_COMBO_GP_TOP_24_H       (REG_COMBO_GP_TOP_BASE + 0x49)
6560 #define REG_COMBO_GP_TOP_25_L       (REG_COMBO_GP_TOP_BASE + 0x4A)
6561 #define REG_COMBO_GP_TOP_25_H       (REG_COMBO_GP_TOP_BASE + 0x4B)
6562 #define REG_COMBO_GP_TOP_26_L       (REG_COMBO_GP_TOP_BASE + 0x4C)
6563 #define REG_COMBO_GP_TOP_26_H       (REG_COMBO_GP_TOP_BASE + 0x4D)
6564 #define REG_COMBO_GP_TOP_27_L       (REG_COMBO_GP_TOP_BASE + 0x4E)
6565 #define REG_COMBO_GP_TOP_27_H       (REG_COMBO_GP_TOP_BASE + 0x4F)
6566 #define REG_COMBO_GP_TOP_28_L       (REG_COMBO_GP_TOP_BASE + 0x50)
6567 #define REG_COMBO_GP_TOP_28_H       (REG_COMBO_GP_TOP_BASE + 0x51)
6568 #define REG_COMBO_GP_TOP_29_L       (REG_COMBO_GP_TOP_BASE + 0x52)
6569 #define REG_COMBO_GP_TOP_29_H       (REG_COMBO_GP_TOP_BASE + 0x53)
6570 #define REG_COMBO_GP_TOP_2A_L       (REG_COMBO_GP_TOP_BASE + 0x54)
6571 #define REG_COMBO_GP_TOP_2A_H       (REG_COMBO_GP_TOP_BASE + 0x55)
6572 #define REG_COMBO_GP_TOP_2B_L       (REG_COMBO_GP_TOP_BASE + 0x56)
6573 #define REG_COMBO_GP_TOP_2B_H       (REG_COMBO_GP_TOP_BASE + 0x57)
6574 #define REG_COMBO_GP_TOP_2C_L       (REG_COMBO_GP_TOP_BASE + 0x58)
6575 #define REG_COMBO_GP_TOP_2C_H       (REG_COMBO_GP_TOP_BASE + 0x59)
6576 #define REG_COMBO_GP_TOP_2D_L       (REG_COMBO_GP_TOP_BASE + 0x5A)
6577 #define REG_COMBO_GP_TOP_2D_H       (REG_COMBO_GP_TOP_BASE + 0x5B)
6578 #define REG_COMBO_GP_TOP_2E_L       (REG_COMBO_GP_TOP_BASE + 0x5C)
6579 #define REG_COMBO_GP_TOP_2E_H       (REG_COMBO_GP_TOP_BASE + 0x5D)
6580 #define REG_COMBO_GP_TOP_2F_L       (REG_COMBO_GP_TOP_BASE + 0x5E)
6581 #define REG_COMBO_GP_TOP_2F_H       (REG_COMBO_GP_TOP_BASE + 0x5F)
6582 #define REG_COMBO_GP_TOP_30_L       (REG_COMBO_GP_TOP_BASE + 0x60)
6583 #define REG_COMBO_GP_TOP_30_H       (REG_COMBO_GP_TOP_BASE + 0x61)
6584 #define REG_COMBO_GP_TOP_31_L       (REG_COMBO_GP_TOP_BASE + 0x62)
6585 #define REG_COMBO_GP_TOP_31_H       (REG_COMBO_GP_TOP_BASE + 0x63)
6586 #define REG_COMBO_GP_TOP_32_L       (REG_COMBO_GP_TOP_BASE + 0x64)
6587 #define REG_COMBO_GP_TOP_32_H       (REG_COMBO_GP_TOP_BASE + 0x65)
6588 #define REG_COMBO_GP_TOP_33_L       (REG_COMBO_GP_TOP_BASE + 0x66)
6589 #define REG_COMBO_GP_TOP_33_H       (REG_COMBO_GP_TOP_BASE + 0x67)
6590 #define REG_COMBO_GP_TOP_34_L       (REG_COMBO_GP_TOP_BASE + 0x68)
6591 #define REG_COMBO_GP_TOP_34_H       (REG_COMBO_GP_TOP_BASE + 0x69)
6592 #define REG_COMBO_GP_TOP_35_L       (REG_COMBO_GP_TOP_BASE + 0x6A)
6593 #define REG_COMBO_GP_TOP_35_H       (REG_COMBO_GP_TOP_BASE + 0x6B)
6594 #define REG_COMBO_GP_TOP_36_L       (REG_COMBO_GP_TOP_BASE + 0x6C)
6595 #define REG_COMBO_GP_TOP_36_H       (REG_COMBO_GP_TOP_BASE + 0x6D)
6596 #define REG_COMBO_GP_TOP_37_L       (REG_COMBO_GP_TOP_BASE + 0x6E)
6597 #define REG_COMBO_GP_TOP_37_H       (REG_COMBO_GP_TOP_BASE + 0x6F)
6598 #define REG_COMBO_GP_TOP_38_L       (REG_COMBO_GP_TOP_BASE + 0x70)
6599 #define REG_COMBO_GP_TOP_38_H       (REG_COMBO_GP_TOP_BASE + 0x71)
6600 #define REG_COMBO_GP_TOP_39_L       (REG_COMBO_GP_TOP_BASE + 0x72)
6601 #define REG_COMBO_GP_TOP_39_H       (REG_COMBO_GP_TOP_BASE + 0x73)
6602 #define REG_COMBO_GP_TOP_3A_L       (REG_COMBO_GP_TOP_BASE + 0x74)
6603 #define REG_COMBO_GP_TOP_3A_H       (REG_COMBO_GP_TOP_BASE + 0x75)
6604 #define REG_COMBO_GP_TOP_3B_L       (REG_COMBO_GP_TOP_BASE + 0x76)
6605 #define REG_COMBO_GP_TOP_3B_H       (REG_COMBO_GP_TOP_BASE + 0x77)
6606 #define REG_COMBO_GP_TOP_3C_L       (REG_COMBO_GP_TOP_BASE + 0x78)
6607 #define REG_COMBO_GP_TOP_3C_H       (REG_COMBO_GP_TOP_BASE + 0x79)
6608 #define REG_COMBO_GP_TOP_3D_L       (REG_COMBO_GP_TOP_BASE + 0x7A)
6609 #define REG_COMBO_GP_TOP_3D_H       (REG_COMBO_GP_TOP_BASE + 0x7B)
6610 #define REG_COMBO_GP_TOP_3E_L       (REG_COMBO_GP_TOP_BASE + 0x7C)
6611 #define REG_COMBO_GP_TOP_3E_H       (REG_COMBO_GP_TOP_BASE + 0x7D)
6612 #define REG_COMBO_GP_TOP_3F_L       (REG_COMBO_GP_TOP_BASE + 0x7E)
6613 #define REG_COMBO_GP_TOP_3F_H       (REG_COMBO_GP_TOP_BASE + 0x7F)
6614 #define REG_COMBO_GP_TOP_40_L       (REG_COMBO_GP_TOP_BASE + 0x80)
6615 #define REG_COMBO_GP_TOP_40_H       (REG_COMBO_GP_TOP_BASE + 0x81)
6616 #define REG_COMBO_GP_TOP_41_L       (REG_COMBO_GP_TOP_BASE + 0x82)
6617 #define REG_COMBO_GP_TOP_41_H       (REG_COMBO_GP_TOP_BASE + 0x83)
6618 #define REG_COMBO_GP_TOP_42_L       (REG_COMBO_GP_TOP_BASE + 0x84)
6619 #define REG_COMBO_GP_TOP_42_H       (REG_COMBO_GP_TOP_BASE + 0x85)
6620 #define REG_COMBO_GP_TOP_43_L       (REG_COMBO_GP_TOP_BASE + 0x86)
6621 #define REG_COMBO_GP_TOP_43_H       (REG_COMBO_GP_TOP_BASE + 0x87)
6622 #define REG_COMBO_GP_TOP_44_L       (REG_COMBO_GP_TOP_BASE + 0x88)
6623 #define REG_COMBO_GP_TOP_44_H       (REG_COMBO_GP_TOP_BASE + 0x89)
6624 #define REG_COMBO_GP_TOP_45_L       (REG_COMBO_GP_TOP_BASE + 0x8A)
6625 #define REG_COMBO_GP_TOP_45_H       (REG_COMBO_GP_TOP_BASE + 0x8B)
6626 #define REG_COMBO_GP_TOP_46_L       (REG_COMBO_GP_TOP_BASE + 0x8C)
6627 #define REG_COMBO_GP_TOP_46_H       (REG_COMBO_GP_TOP_BASE + 0x8D)
6628 #define REG_COMBO_GP_TOP_47_L       (REG_COMBO_GP_TOP_BASE + 0x8E)
6629 #define REG_COMBO_GP_TOP_47_H       (REG_COMBO_GP_TOP_BASE + 0x8F)
6630 #define REG_COMBO_GP_TOP_48_L       (REG_COMBO_GP_TOP_BASE + 0x90)
6631 #define REG_COMBO_GP_TOP_48_H       (REG_COMBO_GP_TOP_BASE + 0x91)
6632 #define REG_COMBO_GP_TOP_49_L       (REG_COMBO_GP_TOP_BASE + 0x92)
6633 #define REG_COMBO_GP_TOP_49_H       (REG_COMBO_GP_TOP_BASE + 0x93)
6634 #define REG_COMBO_GP_TOP_4A_L       (REG_COMBO_GP_TOP_BASE + 0x94)
6635 #define REG_COMBO_GP_TOP_4A_H       (REG_COMBO_GP_TOP_BASE + 0x95)
6636 #define REG_COMBO_GP_TOP_4B_L       (REG_COMBO_GP_TOP_BASE + 0x96)
6637 #define REG_COMBO_GP_TOP_4B_H       (REG_COMBO_GP_TOP_BASE + 0x97)
6638 #define REG_COMBO_GP_TOP_4C_L       (REG_COMBO_GP_TOP_BASE + 0x98)
6639 #define REG_COMBO_GP_TOP_4C_H       (REG_COMBO_GP_TOP_BASE + 0x99)
6640 #define REG_COMBO_GP_TOP_4D_L       (REG_COMBO_GP_TOP_BASE + 0x9A)
6641 #define REG_COMBO_GP_TOP_4D_H       (REG_COMBO_GP_TOP_BASE + 0x9B)
6642 #define REG_COMBO_GP_TOP_4E_L       (REG_COMBO_GP_TOP_BASE + 0x9C)
6643 #define REG_COMBO_GP_TOP_4E_H       (REG_COMBO_GP_TOP_BASE + 0x9D)
6644 #define REG_COMBO_GP_TOP_4F_L       (REG_COMBO_GP_TOP_BASE + 0x9E)
6645 #define REG_COMBO_GP_TOP_4F_H       (REG_COMBO_GP_TOP_BASE + 0x9F)
6646 #define REG_COMBO_GP_TOP_50_L       (REG_COMBO_GP_TOP_BASE + 0xA0)
6647 #define REG_COMBO_GP_TOP_50_H       (REG_COMBO_GP_TOP_BASE + 0xA1)
6648 #define REG_COMBO_GP_TOP_51_L       (REG_COMBO_GP_TOP_BASE + 0xA2)
6649 #define REG_COMBO_GP_TOP_51_H       (REG_COMBO_GP_TOP_BASE + 0xA3)
6650 #define REG_COMBO_GP_TOP_52_L       (REG_COMBO_GP_TOP_BASE + 0xA4)
6651 #define REG_COMBO_GP_TOP_52_H       (REG_COMBO_GP_TOP_BASE + 0xA5)
6652 #define REG_COMBO_GP_TOP_53_L       (REG_COMBO_GP_TOP_BASE + 0xA6)
6653 #define REG_COMBO_GP_TOP_53_H       (REG_COMBO_GP_TOP_BASE + 0xA7)
6654 #define REG_COMBO_GP_TOP_54_L       (REG_COMBO_GP_TOP_BASE + 0xA8)
6655 #define REG_COMBO_GP_TOP_54_H       (REG_COMBO_GP_TOP_BASE + 0xA9)
6656 #define REG_COMBO_GP_TOP_55_L       (REG_COMBO_GP_TOP_BASE + 0xAA)
6657 #define REG_COMBO_GP_TOP_55_H       (REG_COMBO_GP_TOP_BASE + 0xAB)
6658 #define REG_COMBO_GP_TOP_56_L       (REG_COMBO_GP_TOP_BASE + 0xAC)
6659 #define REG_COMBO_GP_TOP_56_H       (REG_COMBO_GP_TOP_BASE + 0xAD)
6660 #define REG_COMBO_GP_TOP_57_L       (REG_COMBO_GP_TOP_BASE + 0xAE)
6661 #define REG_COMBO_GP_TOP_57_H       (REG_COMBO_GP_TOP_BASE + 0xAF)
6662 #define REG_COMBO_GP_TOP_58_L       (REG_COMBO_GP_TOP_BASE + 0xB0)
6663 #define REG_COMBO_GP_TOP_58_H       (REG_COMBO_GP_TOP_BASE + 0xB1)
6664 #define REG_COMBO_GP_TOP_59_L       (REG_COMBO_GP_TOP_BASE + 0xB2)
6665 #define REG_COMBO_GP_TOP_59_H       (REG_COMBO_GP_TOP_BASE + 0xB3)
6666 #define REG_COMBO_GP_TOP_5A_L       (REG_COMBO_GP_TOP_BASE + 0xB4)
6667 #define REG_COMBO_GP_TOP_5A_H       (REG_COMBO_GP_TOP_BASE + 0xB5)
6668 #define REG_COMBO_GP_TOP_5B_L       (REG_COMBO_GP_TOP_BASE + 0xB6)
6669 #define REG_COMBO_GP_TOP_5B_H       (REG_COMBO_GP_TOP_BASE + 0xB7)
6670 #define REG_COMBO_GP_TOP_5C_L       (REG_COMBO_GP_TOP_BASE + 0xB8)
6671 #define REG_COMBO_GP_TOP_5C_H       (REG_COMBO_GP_TOP_BASE + 0xB9)
6672 #define REG_COMBO_GP_TOP_5D_L       (REG_COMBO_GP_TOP_BASE + 0xBA)
6673 #define REG_COMBO_GP_TOP_5D_H       (REG_COMBO_GP_TOP_BASE + 0xBB)
6674 #define REG_COMBO_GP_TOP_5E_L       (REG_COMBO_GP_TOP_BASE + 0xBC)
6675 #define REG_COMBO_GP_TOP_5E_H       (REG_COMBO_GP_TOP_BASE + 0xBD)
6676 #define REG_COMBO_GP_TOP_5F_L       (REG_COMBO_GP_TOP_BASE + 0xBE)
6677 #define REG_COMBO_GP_TOP_5F_H       (REG_COMBO_GP_TOP_BASE + 0xBF)
6678 #define REG_COMBO_GP_TOP_60_L       (REG_COMBO_GP_TOP_BASE + 0xC0)
6679 #define REG_COMBO_GP_TOP_60_H       (REG_COMBO_GP_TOP_BASE + 0xC1)
6680 #define REG_COMBO_GP_TOP_61_L       (REG_COMBO_GP_TOP_BASE + 0xC2)
6681 #define REG_COMBO_GP_TOP_61_H       (REG_COMBO_GP_TOP_BASE + 0xC3)
6682 #define REG_COMBO_GP_TOP_62_L       (REG_COMBO_GP_TOP_BASE + 0xC4)
6683 #define REG_COMBO_GP_TOP_62_H       (REG_COMBO_GP_TOP_BASE + 0xC5)
6684 #define REG_COMBO_GP_TOP_63_L       (REG_COMBO_GP_TOP_BASE + 0xC6)
6685 #define REG_COMBO_GP_TOP_63_H       (REG_COMBO_GP_TOP_BASE + 0xC7)
6686 #define REG_COMBO_GP_TOP_64_L       (REG_COMBO_GP_TOP_BASE + 0xC8)
6687 #define REG_COMBO_GP_TOP_64_H       (REG_COMBO_GP_TOP_BASE + 0xC9)
6688 #define REG_COMBO_GP_TOP_65_L       (REG_COMBO_GP_TOP_BASE + 0xCA)
6689 #define REG_COMBO_GP_TOP_65_H       (REG_COMBO_GP_TOP_BASE + 0xCB)
6690 #define REG_COMBO_GP_TOP_66_L       (REG_COMBO_GP_TOP_BASE + 0xCC)
6691 #define REG_COMBO_GP_TOP_66_H       (REG_COMBO_GP_TOP_BASE + 0xCD)
6692 #define REG_COMBO_GP_TOP_67_L       (REG_COMBO_GP_TOP_BASE + 0xCE)
6693 #define REG_COMBO_GP_TOP_67_H       (REG_COMBO_GP_TOP_BASE + 0xCF)
6694 #define REG_COMBO_GP_TOP_68_L       (REG_COMBO_GP_TOP_BASE + 0xD0)
6695 #define REG_COMBO_GP_TOP_68_H       (REG_COMBO_GP_TOP_BASE + 0xD1)
6696 #define REG_COMBO_GP_TOP_69_L       (REG_COMBO_GP_TOP_BASE + 0xD2)
6697 #define REG_COMBO_GP_TOP_69_H       (REG_COMBO_GP_TOP_BASE + 0xD3)
6698 #define REG_COMBO_GP_TOP_6A_L       (REG_COMBO_GP_TOP_BASE + 0xD4)
6699 #define REG_COMBO_GP_TOP_6A_H       (REG_COMBO_GP_TOP_BASE + 0xD5)
6700 #define REG_COMBO_GP_TOP_6B_L       (REG_COMBO_GP_TOP_BASE + 0xD6)
6701 #define REG_COMBO_GP_TOP_6B_H       (REG_COMBO_GP_TOP_BASE + 0xD7)
6702 #define REG_COMBO_GP_TOP_6C_L       (REG_COMBO_GP_TOP_BASE + 0xD8)
6703 #define REG_COMBO_GP_TOP_6C_H       (REG_COMBO_GP_TOP_BASE + 0xD9)
6704 #define REG_COMBO_GP_TOP_6D_L       (REG_COMBO_GP_TOP_BASE + 0xDA)
6705 #define REG_COMBO_GP_TOP_6D_H       (REG_COMBO_GP_TOP_BASE + 0xDB)
6706 #define REG_COMBO_GP_TOP_6E_L       (REG_COMBO_GP_TOP_BASE + 0xDC)
6707 #define REG_COMBO_GP_TOP_6E_H       (REG_COMBO_GP_TOP_BASE + 0xDD)
6708 
6709 //=============================================================
6710 // SECURE_TZPC
6711 #define REG_SECURE_TZPC_00_L        (REG_SECURE_TZPC_BASE + 0x00)
6712 #define REG_SECURE_TZPC_00_H        (REG_SECURE_TZPC_BASE + 0x01)
6713 #define REG_SECURE_TZPC_01_L        (REG_SECURE_TZPC_BASE + 0x02)
6714 #define REG_SECURE_TZPC_01_H        (REG_SECURE_TZPC_BASE + 0x03)
6715 #define REG_SECURE_TZPC_02_L        (REG_SECURE_TZPC_BASE + 0x04)
6716 #define REG_SECURE_TZPC_02_H        (REG_SECURE_TZPC_BASE + 0x05)
6717 #define REG_SECURE_TZPC_03_L        (REG_SECURE_TZPC_BASE + 0x06)
6718 #define REG_SECURE_TZPC_03_H        (REG_SECURE_TZPC_BASE + 0x07)
6719 #define REG_SECURE_TZPC_04_L        (REG_SECURE_TZPC_BASE + 0x08)
6720 #define REG_SECURE_TZPC_04_H        (REG_SECURE_TZPC_BASE + 0x09)
6721 #define REG_SECURE_TZPC_05_L        (REG_SECURE_TZPC_BASE + 0x0A)
6722 #define REG_SECURE_TZPC_05_H        (REG_SECURE_TZPC_BASE + 0x0B)
6723 #define REG_SECURE_TZPC_06_L        (REG_SECURE_TZPC_BASE + 0x0C)
6724 #define REG_SECURE_TZPC_06_H        (REG_SECURE_TZPC_BASE + 0x0D)
6725 #define REG_SECURE_TZPC_07_L        (REG_SECURE_TZPC_BASE + 0x0E)
6726 #define REG_SECURE_TZPC_07_H        (REG_SECURE_TZPC_BASE + 0x0F)
6727 #define REG_SECURE_TZPC_08_L        (REG_SECURE_TZPC_BASE + 0x10)
6728 #define REG_SECURE_TZPC_08_H        (REG_SECURE_TZPC_BASE + 0x11)
6729 #define REG_SECURE_TZPC_09_L        (REG_SECURE_TZPC_BASE + 0x12)
6730 #define REG_SECURE_TZPC_09_H        (REG_SECURE_TZPC_BASE + 0x13)
6731 #define REG_SECURE_TZPC_0A_L        (REG_SECURE_TZPC_BASE + 0x14)
6732 #define REG_SECURE_TZPC_0A_H        (REG_SECURE_TZPC_BASE + 0x15)
6733 #define REG_SECURE_TZPC_0B_L        (REG_SECURE_TZPC_BASE + 0x16)
6734 #define REG_SECURE_TZPC_0B_H        (REG_SECURE_TZPC_BASE + 0x17)
6735 #define REG_SECURE_TZPC_0C_L        (REG_SECURE_TZPC_BASE + 0x18)
6736 #define REG_SECURE_TZPC_0C_H        (REG_SECURE_TZPC_BASE + 0x19)
6737 #define REG_SECURE_TZPC_0D_L        (REG_SECURE_TZPC_BASE + 0x1A)
6738 #define REG_SECURE_TZPC_0D_H        (REG_SECURE_TZPC_BASE + 0x1B)
6739 #define REG_SECURE_TZPC_0E_L        (REG_SECURE_TZPC_BASE + 0x1C)
6740 #define REG_SECURE_TZPC_0E_H        (REG_SECURE_TZPC_BASE + 0x1D)
6741 #define REG_SECURE_TZPC_0F_L        (REG_SECURE_TZPC_BASE + 0x1E)
6742 #define REG_SECURE_TZPC_0F_H        (REG_SECURE_TZPC_BASE + 0x1F)
6743 #define REG_SECURE_TZPC_10_L        (REG_SECURE_TZPC_BASE + 0x20)
6744 #define REG_SECURE_TZPC_10_H        (REG_SECURE_TZPC_BASE + 0x21)
6745 #define REG_SECURE_TZPC_11_L        (REG_SECURE_TZPC_BASE + 0x22)
6746 #define REG_SECURE_TZPC_11_H        (REG_SECURE_TZPC_BASE + 0x23)
6747 #define REG_SECURE_TZPC_12_L        (REG_SECURE_TZPC_BASE + 0x24)
6748 #define REG_SECURE_TZPC_12_H        (REG_SECURE_TZPC_BASE + 0x25)
6749 #define REG_SECURE_TZPC_13_L        (REG_SECURE_TZPC_BASE + 0x26)
6750 #define REG_SECURE_TZPC_13_H        (REG_SECURE_TZPC_BASE + 0x27)
6751 #define REG_SECURE_TZPC_14_L        (REG_SECURE_TZPC_BASE + 0x28)
6752 #define REG_SECURE_TZPC_14_H        (REG_SECURE_TZPC_BASE + 0x29)
6753 #define REG_SECURE_TZPC_15_L        (REG_SECURE_TZPC_BASE + 0x2A)
6754 #define REG_SECURE_TZPC_15_H        (REG_SECURE_TZPC_BASE + 0x2B)
6755 #define REG_SECURE_TZPC_16_L        (REG_SECURE_TZPC_BASE + 0x2C)
6756 #define REG_SECURE_TZPC_16_H        (REG_SECURE_TZPC_BASE + 0x2D)
6757 #define REG_SECURE_TZPC_17_L        (REG_SECURE_TZPC_BASE + 0x2E)
6758 #define REG_SECURE_TZPC_17_H        (REG_SECURE_TZPC_BASE + 0x2F)
6759 #define REG_SECURE_TZPC_18_L        (REG_SECURE_TZPC_BASE + 0x30)
6760 #define REG_SECURE_TZPC_18_H        (REG_SECURE_TZPC_BASE + 0x31)
6761 #define REG_SECURE_TZPC_19_L        (REG_SECURE_TZPC_BASE + 0x32)
6762 #define REG_SECURE_TZPC_19_H        (REG_SECURE_TZPC_BASE + 0x33)
6763 #define REG_SECURE_TZPC_1A_L        (REG_SECURE_TZPC_BASE + 0x34)
6764 #define REG_SECURE_TZPC_1A_H        (REG_SECURE_TZPC_BASE + 0x35)
6765 #define REG_SECURE_TZPC_1B_L        (REG_SECURE_TZPC_BASE + 0x36)
6766 #define REG_SECURE_TZPC_1B_H        (REG_SECURE_TZPC_BASE + 0x37)
6767 #define REG_SECURE_TZPC_1C_L        (REG_SECURE_TZPC_BASE + 0x38)
6768 #define REG_SECURE_TZPC_1C_H        (REG_SECURE_TZPC_BASE + 0x39)
6769 #define REG_SECURE_TZPC_1D_L        (REG_SECURE_TZPC_BASE + 0x3A)
6770 #define REG_SECURE_TZPC_1D_H        (REG_SECURE_TZPC_BASE + 0x3B)
6771 #define REG_SECURE_TZPC_1E_L        (REG_SECURE_TZPC_BASE + 0x3C)
6772 #define REG_SECURE_TZPC_1E_H        (REG_SECURE_TZPC_BASE + 0x3D)
6773 #define REG_SECURE_TZPC_1F_L        (REG_SECURE_TZPC_BASE + 0x3E)
6774 #define REG_SECURE_TZPC_1F_H        (REG_SECURE_TZPC_BASE + 0x3F)
6775 #define REG_SECURE_TZPC_20_L        (REG_SECURE_TZPC_BASE + 0x40)
6776 #define REG_SECURE_TZPC_20_H        (REG_SECURE_TZPC_BASE + 0x41)
6777 #define REG_SECURE_TZPC_21_L        (REG_SECURE_TZPC_BASE + 0x42)
6778 #define REG_SECURE_TZPC_21_H        (REG_SECURE_TZPC_BASE + 0x43)
6779 #define REG_SECURE_TZPC_22_L        (REG_SECURE_TZPC_BASE + 0x44)
6780 #define REG_SECURE_TZPC_22_H        (REG_SECURE_TZPC_BASE + 0x45)
6781 #define REG_SECURE_TZPC_23_L        (REG_SECURE_TZPC_BASE + 0x46)
6782 #define REG_SECURE_TZPC_23_H        (REG_SECURE_TZPC_BASE + 0x47)
6783 #define REG_SECURE_TZPC_24_L        (REG_SECURE_TZPC_BASE + 0x48)
6784 #define REG_SECURE_TZPC_24_H        (REG_SECURE_TZPC_BASE + 0x49)
6785 #define REG_SECURE_TZPC_25_L        (REG_SECURE_TZPC_BASE + 0x4A)
6786 #define REG_SECURE_TZPC_25_H        (REG_SECURE_TZPC_BASE + 0x4B)
6787 #define REG_SECURE_TZPC_26_L        (REG_SECURE_TZPC_BASE + 0x4C)
6788 #define REG_SECURE_TZPC_26_H        (REG_SECURE_TZPC_BASE + 0x4D)
6789 #define REG_SECURE_TZPC_27_L        (REG_SECURE_TZPC_BASE + 0x4E)
6790 #define REG_SECURE_TZPC_27_H        (REG_SECURE_TZPC_BASE + 0x4F)
6791 #define REG_SECURE_TZPC_28_L        (REG_SECURE_TZPC_BASE + 0x50)
6792 #define REG_SECURE_TZPC_28_H        (REG_SECURE_TZPC_BASE + 0x51)
6793 #define REG_SECURE_TZPC_29_L        (REG_SECURE_TZPC_BASE + 0x52)
6794 #define REG_SECURE_TZPC_29_H        (REG_SECURE_TZPC_BASE + 0x53)
6795 #define REG_SECURE_TZPC_2A_L        (REG_SECURE_TZPC_BASE + 0x54)
6796 #define REG_SECURE_TZPC_2A_H        (REG_SECURE_TZPC_BASE + 0x55)
6797 #define REG_SECURE_TZPC_2B_L        (REG_SECURE_TZPC_BASE + 0x56)
6798 #define REG_SECURE_TZPC_2B_H        (REG_SECURE_TZPC_BASE + 0x57)
6799 #define REG_SECURE_TZPC_2C_L        (REG_SECURE_TZPC_BASE + 0x58)
6800 #define REG_SECURE_TZPC_2C_H        (REG_SECURE_TZPC_BASE + 0x59)
6801 #define REG_SECURE_TZPC_2D_L        (REG_SECURE_TZPC_BASE + 0x5A)
6802 #define REG_SECURE_TZPC_2D_H        (REG_SECURE_TZPC_BASE + 0x5B)
6803 #define REG_SECURE_TZPC_2E_L        (REG_SECURE_TZPC_BASE + 0x5C)
6804 #define REG_SECURE_TZPC_2E_H        (REG_SECURE_TZPC_BASE + 0x5D)
6805 #define REG_SECURE_TZPC_2F_L        (REG_SECURE_TZPC_BASE + 0x5E)
6806 #define REG_SECURE_TZPC_2F_H        (REG_SECURE_TZPC_BASE + 0x5F)
6807 #define REG_SECURE_TZPC_30_L        (REG_SECURE_TZPC_BASE + 0x60)
6808 #define REG_SECURE_TZPC_30_H        (REG_SECURE_TZPC_BASE + 0x61)
6809 #define REG_SECURE_TZPC_31_L        (REG_SECURE_TZPC_BASE + 0x62)
6810 #define REG_SECURE_TZPC_31_H        (REG_SECURE_TZPC_BASE + 0x63)
6811 #define REG_SECURE_TZPC_32_L        (REG_SECURE_TZPC_BASE + 0x64)
6812 #define REG_SECURE_TZPC_32_H        (REG_SECURE_TZPC_BASE + 0x65)
6813 #define REG_SECURE_TZPC_33_L        (REG_SECURE_TZPC_BASE + 0x66)
6814 #define REG_SECURE_TZPC_33_H        (REG_SECURE_TZPC_BASE + 0x67)
6815 #define REG_SECURE_TZPC_34_L        (REG_SECURE_TZPC_BASE + 0x68)
6816 #define REG_SECURE_TZPC_34_H        (REG_SECURE_TZPC_BASE + 0x69)
6817 #define REG_SECURE_TZPC_35_L        (REG_SECURE_TZPC_BASE + 0x6A)
6818 #define REG_SECURE_TZPC_35_H        (REG_SECURE_TZPC_BASE + 0x6B)
6819 #define REG_SECURE_TZPC_36_L        (REG_SECURE_TZPC_BASE + 0x6C)
6820 #define REG_SECURE_TZPC_36_H        (REG_SECURE_TZPC_BASE + 0x6D)
6821 #define REG_SECURE_TZPC_37_L        (REG_SECURE_TZPC_BASE + 0x6E)
6822 #define REG_SECURE_TZPC_37_H        (REG_SECURE_TZPC_BASE + 0x6F)
6823 #define REG_SECURE_TZPC_38_L        (REG_SECURE_TZPC_BASE + 0x70)
6824 #define REG_SECURE_TZPC_38_H        (REG_SECURE_TZPC_BASE + 0x71)
6825 #define REG_SECURE_TZPC_39_L        (REG_SECURE_TZPC_BASE + 0x72)
6826 #define REG_SECURE_TZPC_39_H        (REG_SECURE_TZPC_BASE + 0x73)
6827 #define REG_SECURE_TZPC_3A_L        (REG_SECURE_TZPC_BASE + 0x74)
6828 #define REG_SECURE_TZPC_3A_H        (REG_SECURE_TZPC_BASE + 0x75)
6829 #define REG_SECURE_TZPC_3B_L        (REG_SECURE_TZPC_BASE + 0x76)
6830 #define REG_SECURE_TZPC_3B_H        (REG_SECURE_TZPC_BASE + 0x77)
6831 #define REG_SECURE_TZPC_3C_L        (REG_SECURE_TZPC_BASE + 0x78)
6832 #define REG_SECURE_TZPC_3C_H        (REG_SECURE_TZPC_BASE + 0x79)
6833 #define REG_SECURE_TZPC_3D_L        (REG_SECURE_TZPC_BASE + 0x7A)
6834 #define REG_SECURE_TZPC_3D_H        (REG_SECURE_TZPC_BASE + 0x7B)
6835 #define REG_SECURE_TZPC_3E_L        (REG_SECURE_TZPC_BASE + 0x7C)
6836 #define REG_SECURE_TZPC_3E_H        (REG_SECURE_TZPC_BASE + 0x7D)
6837 #define REG_SECURE_TZPC_3F_L        (REG_SECURE_TZPC_BASE + 0x7E)
6838 #define REG_SECURE_TZPC_3F_H        (REG_SECURE_TZPC_BASE + 0x7F)
6839 #define REG_SECURE_TZPC_40_L        (REG_SECURE_TZPC_BASE + 0x80)
6840 #define REG_SECURE_TZPC_40_H        (REG_SECURE_TZPC_BASE + 0x81)
6841 #define REG_SECURE_TZPC_41_L        (REG_SECURE_TZPC_BASE + 0x82)
6842 #define REG_SECURE_TZPC_41_H        (REG_SECURE_TZPC_BASE + 0x83)
6843 #define REG_SECURE_TZPC_42_L        (REG_SECURE_TZPC_BASE + 0x84)
6844 #define REG_SECURE_TZPC_42_H        (REG_SECURE_TZPC_BASE + 0x85)
6845 #define REG_SECURE_TZPC_43_L        (REG_SECURE_TZPC_BASE + 0x86)
6846 #define REG_SECURE_TZPC_43_H        (REG_SECURE_TZPC_BASE + 0x87)
6847 #define REG_SECURE_TZPC_44_L        (REG_SECURE_TZPC_BASE + 0x88)
6848 #define REG_SECURE_TZPC_44_H        (REG_SECURE_TZPC_BASE + 0x89)
6849 #define REG_SECURE_TZPC_45_L        (REG_SECURE_TZPC_BASE + 0x8A)
6850 #define REG_SECURE_TZPC_45_H        (REG_SECURE_TZPC_BASE + 0x8B)
6851 #define REG_SECURE_TZPC_46_L        (REG_SECURE_TZPC_BASE + 0x8C)
6852 #define REG_SECURE_TZPC_46_H        (REG_SECURE_TZPC_BASE + 0x8D)
6853 #define REG_SECURE_TZPC_47_L        (REG_SECURE_TZPC_BASE + 0x8E)
6854 #define REG_SECURE_TZPC_47_H        (REG_SECURE_TZPC_BASE + 0x8F)
6855 #define REG_SECURE_TZPC_48_L        (REG_SECURE_TZPC_BASE + 0x90)
6856 #define REG_SECURE_TZPC_48_H        (REG_SECURE_TZPC_BASE + 0x91)
6857 #define REG_SECURE_TZPC_49_L        (REG_SECURE_TZPC_BASE + 0x92)
6858 #define REG_SECURE_TZPC_49_H        (REG_SECURE_TZPC_BASE + 0x93)
6859 #define REG_SECURE_TZPC_4A_L        (REG_SECURE_TZPC_BASE + 0x94)
6860 #define REG_SECURE_TZPC_4A_H        (REG_SECURE_TZPC_BASE + 0x95)
6861 #define REG_SECURE_TZPC_4B_L        (REG_SECURE_TZPC_BASE + 0x96)
6862 #define REG_SECURE_TZPC_4B_H        (REG_SECURE_TZPC_BASE + 0x97)
6863 #define REG_SECURE_TZPC_4C_L        (REG_SECURE_TZPC_BASE + 0x98)
6864 #define REG_SECURE_TZPC_4C_H        (REG_SECURE_TZPC_BASE + 0x99)
6865 #define REG_SECURE_TZPC_4D_L        (REG_SECURE_TZPC_BASE + 0x9A)
6866 #define REG_SECURE_TZPC_4D_H        (REG_SECURE_TZPC_BASE + 0x9B)
6867 #define REG_SECURE_TZPC_4E_L        (REG_SECURE_TZPC_BASE + 0x9C)
6868 #define REG_SECURE_TZPC_4E_H        (REG_SECURE_TZPC_BASE + 0x9D)
6869 #define REG_SECURE_TZPC_4F_L        (REG_SECURE_TZPC_BASE + 0x9E)
6870 #define REG_SECURE_TZPC_4F_H        (REG_SECURE_TZPC_BASE + 0x9F)
6871 #define REG_SECURE_TZPC_50_L        (REG_SECURE_TZPC_BASE + 0xA0)
6872 #define REG_SECURE_TZPC_50_H        (REG_SECURE_TZPC_BASE + 0xA1)
6873 #define REG_SECURE_TZPC_51_L        (REG_SECURE_TZPC_BASE + 0xA2)
6874 #define REG_SECURE_TZPC_51_H        (REG_SECURE_TZPC_BASE + 0xA3)
6875 #define REG_SECURE_TZPC_52_L        (REG_SECURE_TZPC_BASE + 0xA4)
6876 #define REG_SECURE_TZPC_52_H        (REG_SECURE_TZPC_BASE + 0xA5)
6877 #define REG_SECURE_TZPC_53_L        (REG_SECURE_TZPC_BASE + 0xA6)
6878 #define REG_SECURE_TZPC_53_H        (REG_SECURE_TZPC_BASE + 0xA7)
6879 #define REG_SECURE_TZPC_54_L        (REG_SECURE_TZPC_BASE + 0xA8)
6880 #define REG_SECURE_TZPC_54_H        (REG_SECURE_TZPC_BASE + 0xA9)
6881 #define REG_SECURE_TZPC_55_L        (REG_SECURE_TZPC_BASE + 0xAA)
6882 #define REG_SECURE_TZPC_55_H        (REG_SECURE_TZPC_BASE + 0xAB)
6883 #define REG_SECURE_TZPC_56_L        (REG_SECURE_TZPC_BASE + 0xAC)
6884 #define REG_SECURE_TZPC_56_H        (REG_SECURE_TZPC_BASE + 0xAD)
6885 #define REG_SECURE_TZPC_57_L        (REG_SECURE_TZPC_BASE + 0xAE)
6886 #define REG_SECURE_TZPC_57_H        (REG_SECURE_TZPC_BASE + 0xAF)
6887 #define REG_SECURE_TZPC_58_L        (REG_SECURE_TZPC_BASE + 0xB0)
6888 #define REG_SECURE_TZPC_58_H        (REG_SECURE_TZPC_BASE + 0xB1)
6889 #define REG_SECURE_TZPC_59_L        (REG_SECURE_TZPC_BASE + 0xB2)
6890 #define REG_SECURE_TZPC_59_H        (REG_SECURE_TZPC_BASE + 0xB3)
6891 #define REG_SECURE_TZPC_5A_L        (REG_SECURE_TZPC_BASE + 0xB4)
6892 #define REG_SECURE_TZPC_5A_H        (REG_SECURE_TZPC_BASE + 0xB5)
6893 #define REG_SECURE_TZPC_5B_L        (REG_SECURE_TZPC_BASE + 0xB6)
6894 #define REG_SECURE_TZPC_5B_H        (REG_SECURE_TZPC_BASE + 0xB7)
6895 #define REG_SECURE_TZPC_5C_L        (REG_SECURE_TZPC_BASE + 0xB8)
6896 #define REG_SECURE_TZPC_5C_H        (REG_SECURE_TZPC_BASE + 0xB9)
6897 #define REG_SECURE_TZPC_5D_L        (REG_SECURE_TZPC_BASE + 0xBA)
6898 #define REG_SECURE_TZPC_5D_H        (REG_SECURE_TZPC_BASE + 0xBB)
6899 #define REG_SECURE_TZPC_5E_L        (REG_SECURE_TZPC_BASE + 0xBC)
6900 #define REG_SECURE_TZPC_5E_H        (REG_SECURE_TZPC_BASE + 0xBD)
6901 #define REG_SECURE_TZPC_5F_L        (REG_SECURE_TZPC_BASE + 0xBE)
6902 #define REG_SECURE_TZPC_5F_H        (REG_SECURE_TZPC_BASE + 0xBF)
6903 #define REG_SECURE_TZPC_60_L        (REG_SECURE_TZPC_BASE + 0xC0)
6904 #define REG_SECURE_TZPC_60_H        (REG_SECURE_TZPC_BASE + 0xC1)
6905 #define REG_SECURE_TZPC_61_L        (REG_SECURE_TZPC_BASE + 0xC2)
6906 #define REG_SECURE_TZPC_61_H        (REG_SECURE_TZPC_BASE + 0xC3)
6907 #define REG_SECURE_TZPC_62_L        (REG_SECURE_TZPC_BASE + 0xC4)
6908 #define REG_SECURE_TZPC_62_H        (REG_SECURE_TZPC_BASE + 0xC5)
6909 #define REG_SECURE_TZPC_63_L        (REG_SECURE_TZPC_BASE + 0xC6)
6910 #define REG_SECURE_TZPC_63_H        (REG_SECURE_TZPC_BASE + 0xC7)
6911 #define REG_SECURE_TZPC_64_L        (REG_SECURE_TZPC_BASE + 0xC8)
6912 #define REG_SECURE_TZPC_64_H        (REG_SECURE_TZPC_BASE + 0xC9)
6913 #define REG_SECURE_TZPC_65_L        (REG_SECURE_TZPC_BASE + 0xCA)
6914 #define REG_SECURE_TZPC_65_H        (REG_SECURE_TZPC_BASE + 0xCB)
6915 #define REG_SECURE_TZPC_66_L        (REG_SECURE_TZPC_BASE + 0xCC)
6916 #define REG_SECURE_TZPC_66_H        (REG_SECURE_TZPC_BASE + 0xCD)
6917 #define REG_SECURE_TZPC_67_L        (REG_SECURE_TZPC_BASE + 0xCE)
6918 #define REG_SECURE_TZPC_67_H        (REG_SECURE_TZPC_BASE + 0xCF)
6919 #define REG_SECURE_TZPC_68_L        (REG_SECURE_TZPC_BASE + 0xD0)
6920 #define REG_SECURE_TZPC_68_H        (REG_SECURE_TZPC_BASE + 0xD1)
6921 #define REG_SECURE_TZPC_69_L        (REG_SECURE_TZPC_BASE + 0xD2)
6922 #define REG_SECURE_TZPC_69_H        (REG_SECURE_TZPC_BASE + 0xD3)
6923 #define REG_SECURE_TZPC_6A_L        (REG_SECURE_TZPC_BASE + 0xD4)
6924 #define REG_SECURE_TZPC_6A_H        (REG_SECURE_TZPC_BASE + 0xD5)
6925 #define REG_SECURE_TZPC_6B_L        (REG_SECURE_TZPC_BASE + 0xD6)
6926 #define REG_SECURE_TZPC_6B_H        (REG_SECURE_TZPC_BASE + 0xD7)
6927 #define REG_SECURE_TZPC_6C_L        (REG_SECURE_TZPC_BASE + 0xD8)
6928 #define REG_SECURE_TZPC_6C_H        (REG_SECURE_TZPC_BASE + 0xD9)
6929 #define REG_SECURE_TZPC_6D_L        (REG_SECURE_TZPC_BASE + 0xDA)
6930 #define REG_SECURE_TZPC_6D_H        (REG_SECURE_TZPC_BASE + 0xDB)
6931 #define REG_SECURE_TZPC_6E_L        (REG_SECURE_TZPC_BASE + 0xDC)
6932 #define REG_SECURE_TZPC_6E_H        (REG_SECURE_TZPC_BASE + 0xDD)
6933 
6934 // CHIP_GPIO
6935 #define REG_CHIP_GPIO_08_L          (REG_CHIP_GPIO_BASE + 0x10)
6936 #define REG_CHIP_GPIO_08_H          (REG_CHIP_GPIO_BASE + 0x11)
6937 #define REG_CHIP_GPIO_09_L          (REG_CHIP_GPIO_BASE + 0x12)
6938 #define REG_CHIP_GPIO_09_H          (REG_CHIP_GPIO_BASE + 0x13)
6939 #define REG_CHIP_GPIO_0A_L          (REG_CHIP_GPIO_BASE + 0x14)
6940 #define REG_CHIP_GPIO_0A_H          (REG_CHIP_GPIO_BASE + 0x15)
6941 #define REG_CHIP_GPIO_0B_L          (REG_CHIP_GPIO_BASE + 0x16)
6942 #define REG_CHIP_GPIO_0B_H          (REG_CHIP_GPIO_BASE + 0x17)
6943 #define REG_CHIP_GPIO_0C_L          (REG_CHIP_GPIO_BASE + 0x18)
6944 #define REG_CHIP_GPIO_0C_H          (REG_CHIP_GPIO_BASE + 0x19)
6945 #define REG_CHIP_GPIO_0D_L          (REG_CHIP_GPIO_BASE + 0x1A)
6946 #define REG_CHIP_GPIO_0D_H          (REG_CHIP_GPIO_BASE + 0x1B)
6947 #define REG_CHIP_GPIO_0E_L          (REG_CHIP_GPIO_BASE + 0x1C)
6948 #define REG_CHIP_GPIO_0E_H          (REG_CHIP_GPIO_BASE + 0x1D)
6949 #define REG_CHIP_GPIO_0F_L          (REG_CHIP_GPIO_BASE + 0x1E)
6950 #define REG_CHIP_GPIO_0F_H          (REG_CHIP_GPIO_BASE + 0x1F)
6951 
6952 #define REG_CHIP_GPIO_50_L          (REG_CHIP_GPIO_BASE + 0xA0)
6953 #define REG_CHIP_GPIO_50_H          (REG_CHIP_GPIO_BASE + 0xA1)
6954 #define REG_CHIP_GPIO_51_L          (REG_CHIP_GPIO_BASE + 0xA2)
6955 #define REG_CHIP_GPIO_51_H          (REG_CHIP_GPIO_BASE + 0xA3)
6956 #define REG_CHIP_GPIO_52_L          (REG_CHIP_GPIO_BASE + 0xA4)
6957 #define REG_CHIP_GPIO_52_H          (REG_CHIP_GPIO_BASE + 0xA5)
6958 #define REG_CHIP_GPIO_53_L          (REG_CHIP_GPIO_BASE + 0xA6)
6959 #define REG_CHIP_GPIO_53_H          (REG_CHIP_GPIO_BASE + 0xA7)
6960 #define REG_CHIP_GPIO_54_L          (REG_CHIP_GPIO_BASE + 0xA8)
6961 #define REG_CHIP_GPIO_54_H          (REG_CHIP_GPIO_BASE + 0xA9)
6962 #define REG_CHIP_GPIO_55_L          (REG_CHIP_GPIO_BASE + 0xAA)
6963 #define REG_CHIP_GPIO_55_H          (REG_CHIP_GPIO_BASE + 0xAB)
6964 #define REG_CHIP_GPIO_56_L          (REG_CHIP_GPIO_BASE + 0xAC)
6965 #define REG_CHIP_GPIO_56_H          (REG_CHIP_GPIO_BASE + 0xAD)
6966 #define REG_CHIP_GPIO_57_L          (REG_CHIP_GPIO_BASE + 0xAE)
6967 #define REG_CHIP_GPIO_57_H          (REG_CHIP_GPIO_BASE + 0xAF)
6968 
6969 #endif
6970 
6971