1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 //alex_tung 95 #ifndef _HWREG_PM_SLEEP_EX_H_ 96 #define _HWREG_PM_SLEEP_EX_H_ 97 98 //============================================================= 99 //PM SLEEP 100 //#define REG_PM_SLEEP_BASE 0x0E00 101 102 #define REG_PM_SLEEP_00_L (REG_PM_SLEEP_BASE + 0x00) 103 #define REG_PM_SLEEP_00_H (REG_PM_SLEEP_BASE + 0x01) 104 #define REG_PM_SLEEP_01_L (REG_PM_SLEEP_BASE + 0x02) 105 #define REG_PM_SLEEP_01_H (REG_PM_SLEEP_BASE + 0x03) 106 #define REG_PM_SLEEP_02_L (REG_PM_SLEEP_BASE + 0x04) 107 #define REG_PM_SLEEP_02_H (REG_PM_SLEEP_BASE + 0x05) 108 #define REG_PM_SLEEP_03_L (REG_PM_SLEEP_BASE + 0x06) 109 #define REG_PM_SLEEP_03_H (REG_PM_SLEEP_BASE + 0x07) 110 #define REG_PM_SLEEP_04_L (REG_PM_SLEEP_BASE + 0x08) 111 #define REG_PM_SLEEP_04_H (REG_PM_SLEEP_BASE + 0x09) 112 #define REG_PM_SLEEP_05_L (REG_PM_SLEEP_BASE + 0x0A) 113 #define REG_PM_SLEEP_05_H (REG_PM_SLEEP_BASE + 0x0B) 114 #define REG_PM_SLEEP_06_L (REG_PM_SLEEP_BASE + 0x0C) 115 #define REG_PM_SLEEP_06_H (REG_PM_SLEEP_BASE + 0x0D) 116 #define REG_PM_SLEEP_07_L (REG_PM_SLEEP_BASE + 0x0E) 117 #define REG_PM_SLEEP_07_H (REG_PM_SLEEP_BASE + 0x0F) 118 #define REG_PM_SLEEP_08_L (REG_PM_SLEEP_BASE + 0x10) 119 #define REG_PM_SLEEP_08_H (REG_PM_SLEEP_BASE + 0x11) 120 #define REG_PM_SLEEP_09_L (REG_PM_SLEEP_BASE + 0x12) 121 #define REG_PM_SLEEP_09_H (REG_PM_SLEEP_BASE + 0x13) 122 #define REG_PM_SLEEP_0A_L (REG_PM_SLEEP_BASE + 0x14) 123 #define REG_PM_SLEEP_0A_H (REG_PM_SLEEP_BASE + 0x15) 124 #define REG_PM_SLEEP_0B_L (REG_PM_SLEEP_BASE + 0x16) 125 #define REG_PM_SLEEP_0B_H (REG_PM_SLEEP_BASE + 0x17) 126 #define REG_PM_SLEEP_0C_L (REG_PM_SLEEP_BASE + 0x18) 127 #define REG_PM_SLEEP_0C_H (REG_PM_SLEEP_BASE + 0x19) 128 #define REG_PM_SLEEP_0D_L (REG_PM_SLEEP_BASE + 0x1A) 129 #define REG_PM_SLEEP_0D_H (REG_PM_SLEEP_BASE + 0x1B) 130 #define REG_PM_SLEEP_0E_L (REG_PM_SLEEP_BASE + 0x1C) 131 #define REG_PM_SLEEP_0E_H (REG_PM_SLEEP_BASE + 0x1D) 132 #define REG_PM_SLEEP_0F_L (REG_PM_SLEEP_BASE + 0x1E) 133 #define REG_PM_SLEEP_0F_H (REG_PM_SLEEP_BASE + 0x1F) 134 #define REG_PM_SLEEP_10_L (REG_PM_SLEEP_BASE + 0x20) 135 #define REG_PM_SLEEP_10_H (REG_PM_SLEEP_BASE + 0x21) 136 #define REG_PM_SLEEP_11_L (REG_PM_SLEEP_BASE + 0x22) 137 #define REG_PM_SLEEP_11_H (REG_PM_SLEEP_BASE + 0x23) 138 #define REG_PM_SLEEP_12_L (REG_PM_SLEEP_BASE + 0x24) 139 #define REG_PM_SLEEP_12_H (REG_PM_SLEEP_BASE + 0x25) 140 #define REG_PM_SLEEP_13_L (REG_PM_SLEEP_BASE + 0x26) 141 #define REG_PM_SLEEP_13_H (REG_PM_SLEEP_BASE + 0x27) 142 #define REG_PM_SLEEP_14_L (REG_PM_SLEEP_BASE + 0x28) 143 #define REG_PM_SLEEP_14_H (REG_PM_SLEEP_BASE + 0x29) 144 #define REG_PM_SLEEP_15_L (REG_PM_SLEEP_BASE + 0x2A) 145 #define REG_PM_SLEEP_15_H (REG_PM_SLEEP_BASE + 0x2B) 146 #define REG_PM_SLEEP_16_L (REG_PM_SLEEP_BASE + 0x2C) 147 #define REG_PM_SLEEP_16_H (REG_PM_SLEEP_BASE + 0x2D) 148 #define REG_PM_SLEEP_17_L (REG_PM_SLEEP_BASE + 0x2E) 149 #define REG_PM_SLEEP_17_H (REG_PM_SLEEP_BASE + 0x2F) 150 #define REG_PM_SLEEP_18_L (REG_PM_SLEEP_BASE + 0x30) 151 #define REG_PM_SLEEP_18_H (REG_PM_SLEEP_BASE + 0x31) 152 #define REG_PM_SLEEP_19_L (REG_PM_SLEEP_BASE + 0x32) 153 #define REG_PM_SLEEP_19_H (REG_PM_SLEEP_BASE + 0x33) 154 #define REG_PM_SLEEP_1A_L (REG_PM_SLEEP_BASE + 0x34) 155 #define REG_PM_SLEEP_1A_H (REG_PM_SLEEP_BASE + 0x35) 156 #define REG_PM_SLEEP_1B_L (REG_PM_SLEEP_BASE + 0x36) 157 #define REG_PM_SLEEP_1B_H (REG_PM_SLEEP_BASE + 0x37) 158 #define REG_PM_SLEEP_1C_L (REG_PM_SLEEP_BASE + 0x38) 159 #define REG_PM_SLEEP_1C_H (REG_PM_SLEEP_BASE + 0x39) 160 #define REG_PM_SLEEP_1D_L (REG_PM_SLEEP_BASE + 0x3A) 161 #define REG_PM_SLEEP_1D_H (REG_PM_SLEEP_BASE + 0x3B) 162 #define REG_PM_SLEEP_1E_L (REG_PM_SLEEP_BASE + 0x3C) 163 #define REG_PM_SLEEP_1E_H (REG_PM_SLEEP_BASE + 0x3D) 164 #define REG_PM_SLEEP_1F_L (REG_PM_SLEEP_BASE + 0x3E) 165 #define REG_PM_SLEEP_1F_H (REG_PM_SLEEP_BASE + 0x3F) 166 #define REG_PM_SLEEP_20_L (REG_PM_SLEEP_BASE + 0x40) 167 #define REG_PM_SLEEP_20_H (REG_PM_SLEEP_BASE + 0x41) 168 #define REG_PM_SLEEP_21_L (REG_PM_SLEEP_BASE + 0x42) 169 #define REG_PM_SLEEP_21_H (REG_PM_SLEEP_BASE + 0x43) 170 #define REG_PM_SLEEP_22_L (REG_PM_SLEEP_BASE + 0x44) 171 #define REG_PM_SLEEP_22_H (REG_PM_SLEEP_BASE + 0x45) 172 #define REG_PM_SLEEP_23_L (REG_PM_SLEEP_BASE + 0x46) 173 #define REG_PM_SLEEP_23_H (REG_PM_SLEEP_BASE + 0x47) 174 #define REG_PM_SLEEP_24_L (REG_PM_SLEEP_BASE + 0x48) 175 #define REG_PM_SLEEP_24_H (REG_PM_SLEEP_BASE + 0x49) 176 #define REG_PM_SLEEP_25_L (REG_PM_SLEEP_BASE + 0x4A) 177 #define REG_PM_SLEEP_25_H (REG_PM_SLEEP_BASE + 0x4B) 178 #define REG_PM_SLEEP_26_L (REG_PM_SLEEP_BASE + 0x4C) 179 #define REG_PM_SLEEP_26_H (REG_PM_SLEEP_BASE + 0x4D) 180 #define REG_PM_SLEEP_27_L (REG_PM_SLEEP_BASE + 0x4E) 181 #define REG_PM_SLEEP_27_H (REG_PM_SLEEP_BASE + 0x4F) 182 #define REG_PM_SLEEP_28_L (REG_PM_SLEEP_BASE + 0x50) 183 #define REG_PM_SLEEP_28_H (REG_PM_SLEEP_BASE + 0x51) 184 #define REG_PM_SLEEP_29_L (REG_PM_SLEEP_BASE + 0x52) 185 #define REG_PM_SLEEP_29_H (REG_PM_SLEEP_BASE + 0x53) 186 #define REG_PM_SLEEP_2A_L (REG_PM_SLEEP_BASE + 0x54) 187 #define REG_PM_SLEEP_2A_H (REG_PM_SLEEP_BASE + 0x55) 188 #define REG_PM_SLEEP_2B_L (REG_PM_SLEEP_BASE + 0x56) 189 #define REG_PM_SLEEP_2B_H (REG_PM_SLEEP_BASE + 0x57) 190 #define REG_PM_SLEEP_2C_L (REG_PM_SLEEP_BASE + 0x58) 191 #define REG_PM_SLEEP_2C_H (REG_PM_SLEEP_BASE + 0x59) 192 #define REG_PM_SLEEP_2D_L (REG_PM_SLEEP_BASE + 0x5A) 193 #define REG_PM_SLEEP_2D_H (REG_PM_SLEEP_BASE + 0x5B) 194 #define REG_PM_SLEEP_2E_L (REG_PM_SLEEP_BASE + 0x5C) 195 #define REG_PM_SLEEP_2E_H (REG_PM_SLEEP_BASE + 0x5D) 196 #define REG_PM_SLEEP_2F_L (REG_PM_SLEEP_BASE + 0x5E) 197 #define REG_PM_SLEEP_2F_H (REG_PM_SLEEP_BASE + 0x5F) 198 #define REG_PM_SLEEP_30_L (REG_PM_SLEEP_BASE + 0x60) 199 #define REG_PM_SLEEP_30_H (REG_PM_SLEEP_BASE + 0x61) 200 #define REG_PM_SLEEP_31_L (REG_PM_SLEEP_BASE + 0x62) 201 #define REG_PM_SLEEP_31_H (REG_PM_SLEEP_BASE + 0x63) 202 #define REG_PM_SLEEP_32_L (REG_PM_SLEEP_BASE + 0x64) 203 #define REG_PM_SLEEP_32_H (REG_PM_SLEEP_BASE + 0x65) 204 #define REG_PM_SLEEP_33_L (REG_PM_SLEEP_BASE + 0x66) 205 #define REG_PM_SLEEP_33_H (REG_PM_SLEEP_BASE + 0x67) 206 #define REG_PM_SLEEP_34_L (REG_PM_SLEEP_BASE + 0x68) 207 #define REG_PM_SLEEP_34_H (REG_PM_SLEEP_BASE + 0x69) 208 #define REG_PM_SLEEP_35_L (REG_PM_SLEEP_BASE + 0x6A) 209 #define REG_PM_SLEEP_35_H (REG_PM_SLEEP_BASE + 0x6B) 210 #define REG_PM_SLEEP_36_L (REG_PM_SLEEP_BASE + 0x6C) 211 #define REG_PM_SLEEP_36_H (REG_PM_SLEEP_BASE + 0x6D) 212 #define REG_PM_SLEEP_37_L (REG_PM_SLEEP_BASE + 0x6E) 213 #define REG_PM_SLEEP_37_H (REG_PM_SLEEP_BASE + 0x6F) 214 #define REG_PM_SLEEP_38_L (REG_PM_SLEEP_BASE + 0x70) 215 #define REG_PM_SLEEP_38_H (REG_PM_SLEEP_BASE + 0x71) 216 #define REG_PM_SLEEP_39_L (REG_PM_SLEEP_BASE + 0x72) 217 #define REG_PM_SLEEP_39_H (REG_PM_SLEEP_BASE + 0x73) 218 #define REG_PM_SLEEP_3A_L (REG_PM_SLEEP_BASE + 0x74) 219 #define REG_PM_SLEEP_3A_H (REG_PM_SLEEP_BASE + 0x75) 220 #define REG_PM_SLEEP_3B_L (REG_PM_SLEEP_BASE + 0x76) 221 #define REG_PM_SLEEP_3B_H (REG_PM_SLEEP_BASE + 0x77) 222 #define REG_PM_SLEEP_3C_L (REG_PM_SLEEP_BASE + 0x78) 223 #define REG_PM_SLEEP_3C_H (REG_PM_SLEEP_BASE + 0x79) 224 #define REG_PM_SLEEP_3D_L (REG_PM_SLEEP_BASE + 0x7A) 225 #define REG_PM_SLEEP_3D_H (REG_PM_SLEEP_BASE + 0x7B) 226 #define REG_PM_SLEEP_3E_L (REG_PM_SLEEP_BASE + 0x7C) 227 #define REG_PM_SLEEP_3E_H (REG_PM_SLEEP_BASE + 0x7D) 228 #define REG_PM_SLEEP_3F_L (REG_PM_SLEEP_BASE + 0x7E) 229 #define REG_PM_SLEEP_3F_H (REG_PM_SLEEP_BASE + 0x7F) 230 #define REG_PM_SLEEP_40_L (REG_PM_SLEEP_BASE + 0x80) 231 #define REG_PM_SLEEP_40_H (REG_PM_SLEEP_BASE + 0x81) 232 #define REG_PM_SLEEP_41_L (REG_PM_SLEEP_BASE + 0x82) 233 #define REG_PM_SLEEP_41_H (REG_PM_SLEEP_BASE + 0x83) 234 #define REG_PM_SLEEP_42_L (REG_PM_SLEEP_BASE + 0x84) 235 #define REG_PM_SLEEP_42_H (REG_PM_SLEEP_BASE + 0x85) 236 #define REG_PM_SLEEP_43_L (REG_PM_SLEEP_BASE + 0x86) 237 #define REG_PM_SLEEP_43_H (REG_PM_SLEEP_BASE + 0x87) 238 #define REG_PM_SLEEP_44_L (REG_PM_SLEEP_BASE + 0x88) 239 #define REG_PM_SLEEP_44_H (REG_PM_SLEEP_BASE + 0x89) 240 #define REG_PM_SLEEP_45_L (REG_PM_SLEEP_BASE + 0x8A) 241 #define REG_PM_SLEEP_45_H (REG_PM_SLEEP_BASE + 0x8B) 242 #define REG_PM_SLEEP_46_L (REG_PM_SLEEP_BASE + 0x8C) 243 #define REG_PM_SLEEP_46_H (REG_PM_SLEEP_BASE + 0x8D) 244 #define REG_PM_SLEEP_47_L (REG_PM_SLEEP_BASE + 0x8E) 245 #define REG_PM_SLEEP_47_H (REG_PM_SLEEP_BASE + 0x8F) 246 #define REG_PM_SLEEP_48_L (REG_PM_SLEEP_BASE + 0x90) 247 #define REG_PM_SLEEP_48_H (REG_PM_SLEEP_BASE + 0x91) 248 #define REG_PM_SLEEP_49_L (REG_PM_SLEEP_BASE + 0x92) 249 #define REG_PM_SLEEP_49_H (REG_PM_SLEEP_BASE + 0x93) 250 #define REG_PM_SLEEP_4A_L (REG_PM_SLEEP_BASE + 0x94) 251 #define REG_PM_SLEEP_4A_H (REG_PM_SLEEP_BASE + 0x95) 252 #define REG_PM_SLEEP_4B_L (REG_PM_SLEEP_BASE + 0x96) 253 #define REG_PM_SLEEP_4B_H (REG_PM_SLEEP_BASE + 0x97) 254 #define REG_PM_SLEEP_4C_L (REG_PM_SLEEP_BASE + 0x98) 255 #define REG_PM_SLEEP_4C_H (REG_PM_SLEEP_BASE + 0x99) 256 #define REG_PM_SLEEP_4D_L (REG_PM_SLEEP_BASE + 0x9A) 257 #define REG_PM_SLEEP_4D_H (REG_PM_SLEEP_BASE + 0x9B) 258 #define REG_PM_SLEEP_4E_L (REG_PM_SLEEP_BASE + 0x9C) 259 #define REG_PM_SLEEP_4E_H (REG_PM_SLEEP_BASE + 0x9D) 260 #define REG_PM_SLEEP_4F_L (REG_PM_SLEEP_BASE + 0x9E) 261 #define REG_PM_SLEEP_4F_H (REG_PM_SLEEP_BASE + 0x9F) 262 #define REG_PM_SLEEP_50_L (REG_PM_SLEEP_BASE + 0xA0) 263 #define REG_PM_SLEEP_50_H (REG_PM_SLEEP_BASE + 0xA1) 264 #define REG_PM_SLEEP_51_L (REG_PM_SLEEP_BASE + 0xA2) 265 #define REG_PM_SLEEP_51_H (REG_PM_SLEEP_BASE + 0xA3) 266 #define REG_PM_SLEEP_52_L (REG_PM_SLEEP_BASE + 0xA4) 267 #define REG_PM_SLEEP_52_H (REG_PM_SLEEP_BASE + 0xA5) 268 #define REG_PM_SLEEP_53_L (REG_PM_SLEEP_BASE + 0xA6) 269 #define REG_PM_SLEEP_53_H (REG_PM_SLEEP_BASE + 0xA7) 270 #define REG_PM_SLEEP_54_L (REG_PM_SLEEP_BASE + 0xA8) 271 #define REG_PM_SLEEP_54_H (REG_PM_SLEEP_BASE + 0xA9) 272 #define REG_PM_SLEEP_55_L (REG_PM_SLEEP_BASE + 0xAA) 273 #define REG_PM_SLEEP_55_H (REG_PM_SLEEP_BASE + 0xAB) 274 #define REG_PM_SLEEP_56_L (REG_PM_SLEEP_BASE + 0xAC) 275 #define REG_PM_SLEEP_56_H (REG_PM_SLEEP_BASE + 0xAD) 276 #define REG_PM_SLEEP_57_L (REG_PM_SLEEP_BASE + 0xAE) 277 #define REG_PM_SLEEP_57_H (REG_PM_SLEEP_BASE + 0xAF) 278 #define REG_PM_SLEEP_58_L (REG_PM_SLEEP_BASE + 0xB0) 279 #define REG_PM_SLEEP_58_H (REG_PM_SLEEP_BASE + 0xB1) 280 #define REG_PM_SLEEP_59_L (REG_PM_SLEEP_BASE + 0xB2) 281 #define REG_PM_SLEEP_59_H (REG_PM_SLEEP_BASE + 0xB3) 282 #define REG_PM_SLEEP_5A_L (REG_PM_SLEEP_BASE + 0xB4) 283 #define REG_PM_SLEEP_5A_H (REG_PM_SLEEP_BASE + 0xB5) 284 #define REG_PM_SLEEP_5B_L (REG_PM_SLEEP_BASE + 0xB6) 285 #define REG_PM_SLEEP_5B_H (REG_PM_SLEEP_BASE + 0xB7) 286 #define REG_PM_SLEEP_5C_L (REG_PM_SLEEP_BASE + 0xB8) 287 #define REG_PM_SLEEP_5C_H (REG_PM_SLEEP_BASE + 0xB9) 288 #define REG_PM_SLEEP_5D_L (REG_PM_SLEEP_BASE + 0xBA) 289 #define REG_PM_SLEEP_5D_H (REG_PM_SLEEP_BASE + 0xBB) 290 #define REG_PM_SLEEP_5E_L (REG_PM_SLEEP_BASE + 0xBC) 291 #define REG_PM_SLEEP_5E_H (REG_PM_SLEEP_BASE + 0xBD) 292 #define REG_PM_SLEEP_5F_L (REG_PM_SLEEP_BASE + 0xBE) 293 #define REG_PM_SLEEP_5F_H (REG_PM_SLEEP_BASE + 0xBF) 294 #define REG_PM_SLEEP_60_L (REG_PM_SLEEP_BASE + 0xC0) 295 #define REG_PM_SLEEP_60_H (REG_PM_SLEEP_BASE + 0xC1) 296 #define REG_PM_SLEEP_61_L (REG_PM_SLEEP_BASE + 0xC2) 297 #define REG_PM_SLEEP_61_H (REG_PM_SLEEP_BASE + 0xC3) 298 #define REG_PM_SLEEP_62_L (REG_PM_SLEEP_BASE + 0xC4) 299 #define REG_PM_SLEEP_62_H (REG_PM_SLEEP_BASE + 0xC5) 300 #define REG_PM_SLEEP_63_L (REG_PM_SLEEP_BASE + 0xC6) 301 #define REG_PM_SLEEP_63_H (REG_PM_SLEEP_BASE + 0xC7) 302 #define REG_PM_SLEEP_64_L (REG_PM_SLEEP_BASE + 0xC8) 303 #define REG_PM_SLEEP_64_H (REG_PM_SLEEP_BASE + 0xC9) 304 #define REG_PM_SLEEP_65_L (REG_PM_SLEEP_BASE + 0xCA) 305 #define REG_PM_SLEEP_65_H (REG_PM_SLEEP_BASE + 0xCB) 306 #define REG_PM_SLEEP_66_L (REG_PM_SLEEP_BASE + 0xCC) 307 #define REG_PM_SLEEP_66_H (REG_PM_SLEEP_BASE + 0xCD) 308 #define REG_PM_SLEEP_67_L (REG_PM_SLEEP_BASE + 0xCE) 309 #define REG_PM_SLEEP_67_H (REG_PM_SLEEP_BASE + 0xCF) 310 #define REG_PM_SLEEP_68_L (REG_PM_SLEEP_BASE + 0xD0) 311 #define REG_PM_SLEEP_68_H (REG_PM_SLEEP_BASE + 0xD1) 312 #define REG_PM_SLEEP_69_L (REG_PM_SLEEP_BASE + 0xD2) 313 #define REG_PM_SLEEP_69_H (REG_PM_SLEEP_BASE + 0xD3) 314 #define REG_PM_SLEEP_6A_L (REG_PM_SLEEP_BASE + 0xD4) 315 #define REG_PM_SLEEP_6A_H (REG_PM_SLEEP_BASE + 0xD5) 316 #define REG_PM_SLEEP_6B_L (REG_PM_SLEEP_BASE + 0xD6) 317 #define REG_PM_SLEEP_6B_H (REG_PM_SLEEP_BASE + 0xD7) 318 #define REG_PM_SLEEP_6C_L (REG_PM_SLEEP_BASE + 0xD8) 319 #define REG_PM_SLEEP_6C_H (REG_PM_SLEEP_BASE + 0xD9) 320 #define REG_PM_SLEEP_6D_L (REG_PM_SLEEP_BASE + 0xDA) 321 #define REG_PM_SLEEP_6D_H (REG_PM_SLEEP_BASE + 0xDB) 322 #define REG_PM_SLEEP_6E_L (REG_PM_SLEEP_BASE + 0xDC) 323 #define REG_PM_SLEEP_6E_H (REG_PM_SLEEP_BASE + 0xDD) 324 #define REG_PM_SLEEP_6F_L (REG_PM_SLEEP_BASE + 0xDE) 325 #define REG_PM_SLEEP_6F_H (REG_PM_SLEEP_BASE + 0xDF) 326 #define REG_PM_SLEEP_70_L (REG_PM_SLEEP_BASE + 0xE0) 327 #define REG_PM_SLEEP_70_H (REG_PM_SLEEP_BASE + 0xE1) 328 #define REG_PM_SLEEP_71_L (REG_PM_SLEEP_BASE + 0xE2) 329 #define REG_PM_SLEEP_71_H (REG_PM_SLEEP_BASE + 0xE3) 330 #define REG_PM_SLEEP_72_L (REG_PM_SLEEP_BASE + 0xE4) 331 #define REG_PM_SLEEP_72_H (REG_PM_SLEEP_BASE + 0xE5) 332 #define REG_PM_SLEEP_73_L (REG_PM_SLEEP_BASE + 0xE6) 333 #define REG_PM_SLEEP_73_H (REG_PM_SLEEP_BASE + 0xE7) 334 #define REG_PM_SLEEP_74_L (REG_PM_SLEEP_BASE + 0xE8) 335 #define REG_PM_SLEEP_74_H (REG_PM_SLEEP_BASE + 0xE9) 336 #define REG_PM_SLEEP_75_L (REG_PM_SLEEP_BASE + 0xEA) 337 #define REG_PM_SLEEP_75_H (REG_PM_SLEEP_BASE + 0xEB) 338 #define REG_PM_SLEEP_76_L (REG_PM_SLEEP_BASE + 0xEC) 339 #define REG_PM_SLEEP_76_H (REG_PM_SLEEP_BASE + 0xED) 340 #define REG_PM_SLEEP_77_L (REG_PM_SLEEP_BASE + 0xEE) 341 #define REG_PM_SLEEP_77_H (REG_PM_SLEEP_BASE + 0xEF) 342 #define REG_PM_SLEEP_78_L (REG_PM_SLEEP_BASE + 0xF0) 343 #define REG_PM_SLEEP_78_H (REG_PM_SLEEP_BASE + 0xF1) 344 #define REG_PM_SLEEP_79_L (REG_PM_SLEEP_BASE + 0xF2) 345 #define REG_PM_SLEEP_79_H (REG_PM_SLEEP_BASE + 0xF3) 346 #define REG_PM_SLEEP_7A_L (REG_PM_SLEEP_BASE + 0xF4) 347 #define REG_PM_SLEEP_7A_H (REG_PM_SLEEP_BASE + 0xF5) 348 #define REG_PM_SLEEP_7B_L (REG_PM_SLEEP_BASE + 0xF6) 349 #define REG_PM_SLEEP_7B_H (REG_PM_SLEEP_BASE + 0xF7) 350 #define REG_PM_SLEEP_7C_L (REG_PM_SLEEP_BASE + 0xF8) 351 #define REG_PM_SLEEP_7C_H (REG_PM_SLEEP_BASE + 0xF9) 352 #define REG_PM_SLEEP_7D_L (REG_PM_SLEEP_BASE + 0xFA) 353 #define REG_PM_SLEEP_7D_H (REG_PM_SLEEP_BASE + 0xFB) 354 #define REG_PM_SLEEP_7E_L (REG_PM_SLEEP_BASE + 0xFC) 355 #define REG_PM_SLEEP_7E_H (REG_PM_SLEEP_BASE + 0xFD) 356 #define REG_PM_SLEEP_7F_L (REG_PM_SLEEP_BASE + 0xFE) 357 #define REG_PM_SLEEP_7F_H (REG_PM_SLEEP_BASE + 0xFF) 358 359 //============================================================= 360 //PM SCDC0 361 //#define REG_SCDC0_BASE 0x010200UL 362 #define REG_PM_SCDC0_00_L (REG_SCDC0_BASE + 0x00) 363 #define REG_PM_SCDC0_00_H (REG_SCDC0_BASE + 0x01) 364 #define REG_PM_SCDC0_01_L (REG_SCDC0_BASE + 0x02) 365 #define REG_PM_SCDC0_01_H (REG_SCDC0_BASE + 0x03) 366 #define REG_PM_SCDC0_02_L (REG_SCDC0_BASE + 0x04) 367 #define REG_PM_SCDC0_02_H (REG_SCDC0_BASE + 0x05) 368 #define REG_PM_SCDC0_03_L (REG_SCDC0_BASE + 0x06) 369 #define REG_PM_SCDC0_03_H (REG_SCDC0_BASE + 0x07) 370 #define REG_PM_SCDC0_04_L (REG_SCDC0_BASE + 0x08) 371 #define REG_PM_SCDC0_04_H (REG_SCDC0_BASE + 0x09) 372 #define REG_PM_SCDC0_05_L (REG_SCDC0_BASE + 0x0A) 373 #define REG_PM_SCDC0_05_H (REG_SCDC0_BASE + 0x0B) 374 #define REG_PM_SCDC0_06_L (REG_SCDC0_BASE + 0x0C) 375 #define REG_PM_SCDC0_06_H (REG_SCDC0_BASE + 0x0D) 376 #define REG_PM_SCDC0_07_L (REG_SCDC0_BASE + 0x0E) 377 #define REG_PM_SCDC0_07_H (REG_SCDC0_BASE + 0x0F) 378 #define REG_PM_SCDC0_0C_L (REG_SCDC0_BASE + 0x18) 379 #define REG_PM_SCDC0_0C_H (REG_SCDC0_BASE + 0x19) 380 381 //============================================================= 382 //PM SCDC1 383 //#define REG_SCDC1_BASE 0x010300UL 384 #define REG_PM_SCDC1_00_L (REG_SCDC1_BASE + 0x00) 385 #define REG_PM_SCDC1_00_H (REG_SCDC1_BASE + 0x01) 386 #define REG_PM_SCDC1_01_L (REG_SCDC1_BASE + 0x02) 387 #define REG_PM_SCDC1_01_H (REG_SCDC1_BASE + 0x03) 388 #define REG_PM_SCDC1_02_L (REG_SCDC1_BASE + 0x04) 389 #define REG_PM_SCDC1_02_H (REG_SCDC1_BASE + 0x05) 390 #define REG_PM_SCDC1_03_L (REG_SCDC1_BASE + 0x06) 391 #define REG_PM_SCDC1_03_H (REG_SCDC1_BASE + 0x07) 392 #define REG_PM_SCDC1_04_L (REG_SCDC1_BASE + 0x08) 393 #define REG_PM_SCDC1_04_H (REG_SCDC1_BASE + 0x09) 394 #define REG_PM_SCDC1_05_L (REG_SCDC1_BASE + 0x0A) 395 #define REG_PM_SCDC1_05_H (REG_SCDC1_BASE + 0x0B) 396 #define REG_PM_SCDC1_06_L (REG_SCDC1_BASE + 0x0C) 397 #define REG_PM_SCDC1_06_H (REG_SCDC1_BASE + 0x0D) 398 #define REG_PM_SCDC1_07_L (REG_SCDC1_BASE + 0x0E) 399 #define REG_PM_SCDC1_07_H (REG_SCDC1_BASE + 0x0F) 400 #define REG_PM_SCDC1_0C_L (REG_SCDC1_BASE + 0x18) 401 #define REG_PM_SCDC1_0C_H (REG_SCDC1_BASE + 0x19) 402 403 //============================================================= 404 //PM SCDC2 405 //#define REG_SCDC2_BASE 0x010400UL 406 #define REG_PM_SCDC2_00_L (REG_SCDC2_BASE + 0x00) 407 #define REG_PM_SCDC2_00_H (REG_SCDC2_BASE + 0x01) 408 #define REG_PM_SCDC2_01_L (REG_SCDC2_BASE + 0x02) 409 #define REG_PM_SCDC2_01_H (REG_SCDC2_BASE + 0x03) 410 #define REG_PM_SCDC2_02_L (REG_SCDC2_BASE + 0x04) 411 #define REG_PM_SCDC2_02_H (REG_SCDC2_BASE + 0x05) 412 #define REG_PM_SCDC2_03_L (REG_SCDC2_BASE + 0x06) 413 #define REG_PM_SCDC2_03_H (REG_SCDC2_BASE + 0x07) 414 #define REG_PM_SCDC2_04_L (REG_SCDC2_BASE + 0x08) 415 #define REG_PM_SCDC2_04_H (REG_SCDC2_BASE + 0x09) 416 #define REG_PM_SCDC2_05_L (REG_SCDC2_BASE + 0x0A) 417 #define REG_PM_SCDC2_05_H (REG_SCDC2_BASE + 0x0B) 418 #define REG_PM_SCDC2_06_L (REG_SCDC2_BASE + 0x0C) 419 #define REG_PM_SCDC2_06_H (REG_SCDC2_BASE + 0x0D) 420 #define REG_PM_SCDC2_07_L (REG_SCDC2_BASE + 0x0E) 421 #define REG_PM_SCDC2_07_H (REG_SCDC2_BASE + 0x0F) 422 #define REG_PM_SCDC2_0C_L (REG_SCDC2_BASE + 0x18) 423 #define REG_PM_SCDC2_0C_H (REG_SCDC2_BASE + 0x19) 424 425 //============================================================= 426 //PM SCDC3 427 //#define REG_SCDC3_BASE 0x010500UL 428 #define REG_PM_SCDC3_00_L (REG_SCDC3_BASE + 0x00) 429 #define REG_PM_SCDC3_00_H (REG_SCDC3_BASE + 0x01) 430 #define REG_PM_SCDC3_01_L (REG_SCDC3_BASE + 0x02) 431 #define REG_PM_SCDC3_01_H (REG_SCDC3_BASE + 0x03) 432 #define REG_PM_SCDC3_02_L (REG_SCDC3_BASE + 0x04) 433 #define REG_PM_SCDC3_02_H (REG_SCDC3_BASE + 0x05) 434 #define REG_PM_SCDC3_03_L (REG_SCDC3_BASE + 0x06) 435 #define REG_PM_SCDC3_03_H (REG_SCDC3_BASE + 0x07) 436 #define REG_PM_SCDC3_04_L (REG_SCDC3_BASE + 0x08) 437 #define REG_PM_SCDC3_04_H (REG_SCDC3_BASE + 0x09) 438 #define REG_PM_SCDC3_05_L (REG_SCDC3_BASE + 0x0A) 439 #define REG_PM_SCDC3_05_H (REG_SCDC3_BASE + 0x0B) 440 #define REG_PM_SCDC3_06_L (REG_SCDC3_BASE + 0x0C) 441 #define REG_PM_SCDC3_06_H (REG_SCDC3_BASE + 0x0D) 442 #define REG_PM_SCDC3_07_L (REG_SCDC3_BASE + 0x0E) 443 #define REG_PM_SCDC3_07_H (REG_SCDC3_BASE + 0x0F) 444 #define REG_PM_SCDC3_0C_L (REG_SCDC3_BASE + 0x18) 445 #define REG_PM_SCDC3_0C_H (REG_SCDC3_BASE + 0x19) 446 447 //============================================================= 448 //PM TOP 449 //#define REG_PM_TOP_BASE 0x001E00UL 450 #define REG_PM_TOP_BANK_01_L (REG_PM_TOP_BASE + 0x02) 451 #define REG_PM_TOP_BANK_01_H (REG_PM_TOP_BASE + 0x03) 452 453 //============================================================= 454 //PM EFUSE 455 //#define REG_EFUSE_BASE 0x002000UL 456 #define REG_PM_EFUSE_08_L (REG_EFUSE_BASE + 0x10) 457 #define REG_PM_EFUSE_08_H (REG_EFUSE_BASE + 0x11) 458 #define REG_PM_EFUSE_28_L (REG_EFUSE_BASE + 0x50) 459 #define REG_PM_EFUSE_28_H (REG_EFUSE_BASE + 0x51) 460 #define REG_PM_EFUSE_2C_L (REG_EFUSE_BASE + 0x58) 461 #define REG_PM_EFUSE_2C_H (REG_EFUSE_BASE + 0x59) 462 #define REG_PM_EFUSE_2D_L (REG_EFUSE_BASE + 0x5A) 463 #define REG_PM_EFUSE_2D_H (REG_EFUSE_BASE + 0x5B) 464 465 //============================================================= 466 // PM GPIO 467 //#define REG_PM_GPIO_BASE 0x000F00UL 468 #define REG_PM_GPIO_00_L (REG_PM_GPIO_BASE + 0x00) 469 #define REG_PM_GPIO_00_H (REG_PM_GPIO_BASE + 0x01) 470 #define REG_PM_GPIO_01_L (REG_PM_GPIO_BASE + 0x02) 471 #define REG_PM_GPIO_01_H (REG_PM_GPIO_BASE + 0x03) 472 #define REG_PM_GPIO_02_L (REG_PM_GPIO_BASE + 0x04) 473 #define REG_PM_GPIO_02_H (REG_PM_GPIO_BASE + 0x05) 474 #define REG_PM_GPIO_03_L (REG_PM_GPIO_BASE + 0x06) 475 #define REG_PM_GPIO_03_H (REG_PM_GPIO_BASE + 0x07) 476 #define REG_PM_GPIO_04_L (REG_PM_GPIO_BASE + 0x08) 477 #define REG_PM_GPIO_04_H (REG_PM_GPIO_BASE + 0x09) 478 #define REG_PM_GPIO_05_L (REG_PM_GPIO_BASE + 0x0A) 479 #define REG_PM_GPIO_05_H (REG_PM_GPIO_BASE + 0x0B) 480 #define REG_PM_GPIO_06_L (REG_PM_GPIO_BASE + 0x0C) 481 #define REG_PM_GPIO_06_H (REG_PM_GPIO_BASE + 0x0D) 482 #define REG_PM_GPIO_07_L (REG_PM_GPIO_BASE + 0x0E) 483 #define REG_PM_GPIO_07_H (REG_PM_GPIO_BASE + 0x0F) 484 #define REG_PM_GPIO_08_L (REG_PM_GPIO_BASE + 0x10) 485 #define REG_PM_GPIO_08_H (REG_PM_GPIO_BASE + 0x11) 486 #define REG_PM_GPIO_09_L (REG_PM_GPIO_BASE + 0x12) 487 #define REG_PM_GPIO_09_H (REG_PM_GPIO_BASE + 0x13) 488 #define REG_PM_GPIO_0A_L (REG_PM_GPIO_BASE + 0x14) 489 #define REG_PM_GPIO_0A_H (REG_PM_GPIO_BASE + 0x15) 490 #define REG_PM_GPIO_0B_L (REG_PM_GPIO_BASE + 0x16) 491 #define REG_PM_GPIO_0B_H (REG_PM_GPIO_BASE + 0x17) 492 #define REG_PM_GPIO_0C_L (REG_PM_GPIO_BASE + 0x18) 493 #define REG_PM_GPIO_0C_H (REG_PM_GPIO_BASE + 0x19) 494 #define REG_PM_GPIO_0D_L (REG_PM_GPIO_BASE + 0x1A) 495 #define REG_PM_GPIO_0D_H (REG_PM_GPIO_BASE + 0x1B) 496 #define REG_PM_GPIO_0E_L (REG_PM_GPIO_BASE + 0x1C) 497 #define REG_PM_GPIO_0E_H (REG_PM_GPIO_BASE + 0x1D) 498 #define REG_PM_GPIO_0F_L (REG_PM_GPIO_BASE + 0x1E) 499 #define REG_PM_GPIO_0F_H (REG_PM_GPIO_BASE + 0x1F) 500 #define REG_PM_GPIO_10_L (REG_PM_GPIO_BASE + 0x20) 501 #define REG_PM_GPIO_10_H (REG_PM_GPIO_BASE + 0x21) 502 #define REG_PM_GPIO_11_L (REG_PM_GPIO_BASE + 0x22) 503 #define REG_PM_GPIO_11_H (REG_PM_GPIO_BASE + 0x23) 504 #define REG_PM_GPIO_12_L (REG_PM_GPIO_BASE + 0x24) 505 #define REG_PM_GPIO_12_H (REG_PM_GPIO_BASE + 0x25) 506 #define REG_PM_GPIO_13_L (REG_PM_GPIO_BASE + 0x26) 507 #define REG_PM_GPIO_13_H (REG_PM_GPIO_BASE + 0x27) 508 #define REG_PM_GPIO_14_L (REG_PM_GPIO_BASE + 0x28) 509 #define REG_PM_GPIO_14_H (REG_PM_GPIO_BASE + 0x29) 510 #define REG_PM_GPIO_15_L (REG_PM_GPIO_BASE + 0x2A) 511 #define REG_PM_GPIO_15_H (REG_PM_GPIO_BASE + 0x2B) 512 #define REG_PM_GPIO_16_L (REG_PM_GPIO_BASE + 0x2C) 513 #define REG_PM_GPIO_16_H (REG_PM_GPIO_BASE + 0x2D) 514 #define REG_PM_GPIO_17_L (REG_PM_GPIO_BASE + 0x2E) 515 #define REG_PM_GPIO_17_H (REG_PM_GPIO_BASE + 0x2F) 516 517 //============================================================= 518 // PM PAD SAR 519 //#define REG_PAD_SAR_BASE 0x001400UL 520 #define REG_PAD_SAR_11_L (REG_PAD_SAR_BASE + 0x22) 521 #define REG_PAD_SAR_11_H (REG_PAD_SAR_BASE + 0x23) 522 #define REG_PAD_SAR_12_L (REG_PAD_SAR_BASE + 0x24) 523 #define REG_PAD_SAR_12_H (REG_PAD_SAR_BASE + 0x25) 524 525 //============================================================= 526 // MHL CBUS 527 // #define REG_MHL_CBUS_BANK 0x001F00UL 528 #define REG_MHL_CBUS_00 (REG_MHL_CBUS_BANK + 0x00) 529 #define REG_MHL_CBUS_01 (REG_MHL_CBUS_BANK + 0x02) 530 #define REG_MHL_CBUS_02 (REG_MHL_CBUS_BANK + 0x04) 531 #define REG_MHL_CBUS_03 (REG_MHL_CBUS_BANK + 0x06) 532 #define REG_MHL_CBUS_04 (REG_MHL_CBUS_BANK + 0x08) 533 #define REG_MHL_CBUS_05 (REG_MHL_CBUS_BANK + 0x0A) 534 #define REG_MHL_CBUS_06 (REG_MHL_CBUS_BANK + 0x0C) 535 #define REG_MHL_CBUS_07 (REG_MHL_CBUS_BANK + 0x0E) 536 #define REG_MHL_CBUS_08 (REG_MHL_CBUS_BANK + 0x10) 537 #define REG_MHL_CBUS_09 (REG_MHL_CBUS_BANK + 0x12) 538 #define REG_MHL_CBUS_0A (REG_MHL_CBUS_BANK + 0x14) 539 #define REG_MHL_CBUS_0B (REG_MHL_CBUS_BANK + 0x16) 540 #define REG_MHL_CBUS_0C (REG_MHL_CBUS_BANK + 0x18) 541 #define REG_MHL_CBUS_0D (REG_MHL_CBUS_BANK + 0x1A) 542 #define REG_MHL_CBUS_0E (REG_MHL_CBUS_BANK + 0x1C) 543 #define REG_MHL_CBUS_0F (REG_MHL_CBUS_BANK + 0x1E) 544 #define REG_MHL_CBUS_10 (REG_MHL_CBUS_BANK + 0x20) 545 #define REG_MHL_CBUS_11 (REG_MHL_CBUS_BANK + 0x22) 546 #define REG_MHL_CBUS_12 (REG_MHL_CBUS_BANK + 0x24) 547 #define REG_MHL_CBUS_13 (REG_MHL_CBUS_BANK + 0x26) 548 #define REG_MHL_CBUS_14 (REG_MHL_CBUS_BANK + 0x28) 549 #define REG_MHL_CBUS_15 (REG_MHL_CBUS_BANK + 0x2A) 550 #define REG_MHL_CBUS_16 (REG_MHL_CBUS_BANK + 0x2C) 551 #define REG_MHL_CBUS_17 (REG_MHL_CBUS_BANK + 0x2E) 552 #define REG_MHL_CBUS_18 (REG_MHL_CBUS_BANK + 0x30) 553 #define REG_MHL_CBUS_19 (REG_MHL_CBUS_BANK + 0x32) 554 #define REG_MHL_CBUS_1A (REG_MHL_CBUS_BANK + 0x34) 555 #define REG_MHL_CBUS_1B (REG_MHL_CBUS_BANK + 0x36) 556 #define REG_MHL_CBUS_1C (REG_MHL_CBUS_BANK + 0x38) 557 #define REG_MHL_CBUS_1D (REG_MHL_CBUS_BANK + 0x3A) 558 #define REG_MHL_CBUS_1E (REG_MHL_CBUS_BANK + 0x3C) 559 #define REG_MHL_CBUS_1F (REG_MHL_CBUS_BANK + 0x3E) 560 #define REG_MHL_CBUS_20 (REG_MHL_CBUS_BANK + 0x40) 561 #define REG_MHL_CBUS_21 (REG_MHL_CBUS_BANK + 0x42) 562 #define REG_MHL_CBUS_22 (REG_MHL_CBUS_BANK + 0x44) 563 #define REG_MHL_CBUS_23 (REG_MHL_CBUS_BANK + 0x46) 564 #define REG_MHL_CBUS_24 (REG_MHL_CBUS_BANK + 0x48) 565 #define REG_MHL_CBUS_25 (REG_MHL_CBUS_BANK + 0x4A) 566 #define REG_MHL_CBUS_26 (REG_MHL_CBUS_BANK + 0x4C) 567 #define REG_MHL_CBUS_27 (REG_MHL_CBUS_BANK + 0x4E) 568 #define REG_MHL_CBUS_28 (REG_MHL_CBUS_BANK + 0x50) 569 #define REG_MHL_CBUS_29 (REG_MHL_CBUS_BANK + 0x52) 570 #define REG_MHL_CBUS_2A (REG_MHL_CBUS_BANK + 0x54) 571 #define REG_MHL_CBUS_2B (REG_MHL_CBUS_BANK + 0x56) 572 #define REG_MHL_CBUS_2C (REG_MHL_CBUS_BANK + 0x58) 573 #define REG_MHL_CBUS_2D (REG_MHL_CBUS_BANK + 0x5A) 574 #define REG_MHL_CBUS_2E (REG_MHL_CBUS_BANK + 0x5C) 575 #define REG_MHL_CBUS_2F (REG_MHL_CBUS_BANK + 0x5E) 576 #define REG_MHL_CBUS_30 (REG_MHL_CBUS_BANK + 0x60) 577 #define REG_MHL_CBUS_31 (REG_MHL_CBUS_BANK + 0x62) 578 #define REG_MHL_CBUS_32 (REG_MHL_CBUS_BANK + 0x64) 579 #define REG_MHL_CBUS_33 (REG_MHL_CBUS_BANK + 0x66) 580 #define REG_MHL_CBUS_34 (REG_MHL_CBUS_BANK + 0x68) 581 #define REG_MHL_CBUS_35 (REG_MHL_CBUS_BANK + 0x6A) 582 #define REG_MHL_CBUS_36 (REG_MHL_CBUS_BANK + 0x6C) 583 #define REG_MHL_CBUS_37 (REG_MHL_CBUS_BANK + 0x6E) 584 #define REG_MHL_CBUS_38 (REG_MHL_CBUS_BANK + 0x70) 585 #define REG_MHL_CBUS_39 (REG_MHL_CBUS_BANK + 0x72) 586 #define REG_MHL_CBUS_3A (REG_MHL_CBUS_BANK + 0x74) 587 #define REG_MHL_CBUS_3B (REG_MHL_CBUS_BANK + 0x76) 588 #define REG_MHL_CBUS_3C (REG_MHL_CBUS_BANK + 0x78) 589 #define REG_MHL_CBUS_3D (REG_MHL_CBUS_BANK + 0x7A) 590 #define REG_MHL_CBUS_3E (REG_MHL_CBUS_BANK + 0x7C) 591 #define REG_MHL_CBUS_3F (REG_MHL_CBUS_BANK + 0x7E) 592 #define REG_MHL_CBUS_40 (REG_MHL_CBUS_BANK + 0x80) 593 #define REG_MHL_CBUS_41 (REG_MHL_CBUS_BANK + 0x82) 594 #define REG_MHL_CBUS_42 (REG_MHL_CBUS_BANK + 0x84) 595 #define REG_MHL_CBUS_43 (REG_MHL_CBUS_BANK + 0x86) 596 #define REG_MHL_CBUS_44 (REG_MHL_CBUS_BANK + 0x88) 597 #define REG_MHL_CBUS_45 (REG_MHL_CBUS_BANK + 0x8A) 598 #define REG_MHL_CBUS_46 (REG_MHL_CBUS_BANK + 0x8C) 599 #define REG_MHL_CBUS_47 (REG_MHL_CBUS_BANK + 0x8E) 600 #define REG_MHL_CBUS_48 (REG_MHL_CBUS_BANK + 0x90) 601 #define REG_MHL_CBUS_49 (REG_MHL_CBUS_BANK + 0x92) 602 #define REG_MHL_CBUS_4A (REG_MHL_CBUS_BANK + 0x94) 603 #define REG_MHL_CBUS_4B (REG_MHL_CBUS_BANK + 0x96) 604 #define REG_MHL_CBUS_4C (REG_MHL_CBUS_BANK + 0x98) 605 #define REG_MHL_CBUS_4D (REG_MHL_CBUS_BANK + 0x9A) 606 #define REG_MHL_CBUS_4E (REG_MHL_CBUS_BANK + 0x9C) 607 #define REG_MHL_CBUS_4F (REG_MHL_CBUS_BANK + 0x9E) 608 #define REG_MHL_CBUS_50 (REG_MHL_CBUS_BANK + 0xA0) 609 #define REG_MHL_CBUS_51 (REG_MHL_CBUS_BANK + 0xA2) 610 #define REG_MHL_CBUS_52 (REG_MHL_CBUS_BANK + 0xA4) 611 #define REG_MHL_CBUS_53 (REG_MHL_CBUS_BANK + 0xA6) 612 #define REG_MHL_CBUS_54 (REG_MHL_CBUS_BANK + 0xA8) 613 #define REG_MHL_CBUS_55 (REG_MHL_CBUS_BANK + 0xAA) 614 #define REG_MHL_CBUS_56 (REG_MHL_CBUS_BANK + 0xAC) 615 #define REG_MHL_CBUS_57 (REG_MHL_CBUS_BANK + 0xAE) 616 #define REG_MHL_CBUS_58 (REG_MHL_CBUS_BANK + 0xB0) 617 #define REG_MHL_CBUS_59 (REG_MHL_CBUS_BANK + 0xB2) 618 #define REG_MHL_CBUS_5A (REG_MHL_CBUS_BANK + 0xB4) 619 #define REG_MHL_CBUS_5B (REG_MHL_CBUS_BANK + 0xB6) 620 #define REG_MHL_CBUS_5C (REG_MHL_CBUS_BANK + 0xB8) 621 #define REG_MHL_CBUS_5D (REG_MHL_CBUS_BANK + 0xBA) 622 #define REG_MHL_CBUS_5E (REG_MHL_CBUS_BANK + 0xBC) 623 #define REG_MHL_CBUS_5F (REG_MHL_CBUS_BANK + 0xBE) 624 #define REG_MHL_CBUS_60 (REG_MHL_CBUS_BANK + 0xC0) 625 #define REG_MHL_CBUS_61 (REG_MHL_CBUS_BANK + 0xC2) 626 #define REG_MHL_CBUS_62 (REG_MHL_CBUS_BANK + 0xC4) 627 #define REG_MHL_CBUS_63 (REG_MHL_CBUS_BANK + 0xC6) 628 #define REG_MHL_CBUS_64 (REG_MHL_CBUS_BANK + 0xC8) 629 #define REG_MHL_CBUS_65 (REG_MHL_CBUS_BANK + 0xCA) 630 #define REG_MHL_CBUS_66 (REG_MHL_CBUS_BANK + 0xCC) 631 #define REG_MHL_CBUS_67 (REG_MHL_CBUS_BANK + 0xCE) 632 #define REG_MHL_CBUS_68 (REG_MHL_CBUS_BANK + 0xD0) 633 #define REG_MHL_CBUS_69 (REG_MHL_CBUS_BANK + 0xD2) 634 #define REG_MHL_CBUS_6A (REG_MHL_CBUS_BANK + 0xD4) 635 #define REG_MHL_CBUS_6B (REG_MHL_CBUS_BANK + 0xD6) 636 #define REG_MHL_CBUS_6C (REG_MHL_CBUS_BANK + 0xD8) 637 #define REG_MHL_CBUS_6D (REG_MHL_CBUS_BANK + 0xDA) 638 #define REG_MHL_CBUS_6E (REG_MHL_CBUS_BANK + 0xDC) 639 #define REG_MHL_CBUS_6F (REG_MHL_CBUS_BANK + 0xDE) 640 #define REG_MHL_CBUS_70 (REG_MHL_CBUS_BANK + 0xE0) 641 #define REG_MHL_CBUS_71 (REG_MHL_CBUS_BANK + 0xE2) 642 #define REG_MHL_CBUS_72 (REG_MHL_CBUS_BANK + 0xE4) 643 #define REG_MHL_CBUS_73 (REG_MHL_CBUS_BANK + 0xE6) 644 #define REG_MHL_CBUS_74 (REG_MHL_CBUS_BANK + 0xE8) 645 #define REG_MHL_CBUS_75 (REG_MHL_CBUS_BANK + 0xEA) 646 #define REG_MHL_CBUS_76 (REG_MHL_CBUS_BANK + 0xEC) 647 #define REG_MHL_CBUS_77 (REG_MHL_CBUS_BANK + 0xEE) 648 #define REG_MHL_CBUS_78 (REG_MHL_CBUS_BANK + 0xF0) 649 #define REG_MHL_CBUS_79 (REG_MHL_CBUS_BANK + 0xF2) 650 #define REG_MHL_CBUS_7A (REG_MHL_CBUS_BANK + 0xF4) 651 #define REG_MHL_CBUS_7B (REG_MHL_CBUS_BANK + 0xF6) 652 #define REG_MHL_CBUS_7C (REG_MHL_CBUS_BANK + 0xF8) 653 #define REG_MHL_CBUS_7D (REG_MHL_CBUS_BANK + 0xFA) 654 #define REG_MHL_CBUS_7E (REG_MHL_CBUS_BANK + 0xFC) 655 #define REG_MHL_CBUS_7F (REG_MHL_CBUS_BANK + 0xFE) 656 657 //============================================================= 658 // PM MHL CBUS 659 // #define REG_PM_MHL_CBUS_BANK 0x002F00UL 660 #define REG_PM_MHL_CBUS_00 (REG_PM_MHL_CBUS_BANK + 0x00) 661 #define REG_PM_MHL_CBUS_01 (REG_PM_MHL_CBUS_BANK + 0x02) 662 #define REG_PM_MHL_CBUS_02 (REG_PM_MHL_CBUS_BANK + 0x04) 663 #define REG_PM_MHL_CBUS_03 (REG_PM_MHL_CBUS_BANK + 0x06) 664 #define REG_PM_MHL_CBUS_04 (REG_PM_MHL_CBUS_BANK + 0x08) 665 #define REG_PM_MHL_CBUS_05 (REG_PM_MHL_CBUS_BANK + 0x0A) 666 #define REG_PM_MHL_CBUS_06 (REG_PM_MHL_CBUS_BANK + 0x0C) 667 #define REG_PM_MHL_CBUS_07 (REG_PM_MHL_CBUS_BANK + 0x0E) 668 #define REG_PM_MHL_CBUS_08 (REG_PM_MHL_CBUS_BANK + 0x10) 669 #define REG_PM_MHL_CBUS_09 (REG_PM_MHL_CBUS_BANK + 0x12) 670 #define REG_PM_MHL_CBUS_0A (REG_PM_MHL_CBUS_BANK + 0x14) 671 #define REG_PM_MHL_CBUS_0B (REG_PM_MHL_CBUS_BANK + 0x16) 672 #define REG_PM_MHL_CBUS_0C (REG_PM_MHL_CBUS_BANK + 0x18) 673 #define REG_PM_MHL_CBUS_0D (REG_PM_MHL_CBUS_BANK + 0x1A) 674 #define REG_PM_MHL_CBUS_0E (REG_PM_MHL_CBUS_BANK + 0x1C) 675 #define REG_PM_MHL_CBUS_0F (REG_PM_MHL_CBUS_BANK + 0x1E) 676 #define REG_PM_MHL_CBUS_10 (REG_PM_MHL_CBUS_BANK + 0x20) 677 #define REG_PM_MHL_CBUS_11 (REG_PM_MHL_CBUS_BANK + 0x22) 678 #define REG_PM_MHL_CBUS_12 (REG_PM_MHL_CBUS_BANK + 0x24) 679 #define REG_PM_MHL_CBUS_13 (REG_PM_MHL_CBUS_BANK + 0x26) 680 #define REG_PM_MHL_CBUS_14 (REG_PM_MHL_CBUS_BANK + 0x28) 681 #define REG_PM_MHL_CBUS_15 (REG_PM_MHL_CBUS_BANK + 0x2A) 682 #define REG_PM_MHL_CBUS_16 (REG_PM_MHL_CBUS_BANK + 0x2C) 683 #define REG_PM_MHL_CBUS_17 (REG_PM_MHL_CBUS_BANK + 0x2E) 684 #define REG_PM_MHL_CBUS_18 (REG_PM_MHL_CBUS_BANK + 0x30) 685 #define REG_PM_MHL_CBUS_19 (REG_PM_MHL_CBUS_BANK + 0x32) 686 #define REG_PM_MHL_CBUS_1A (REG_PM_MHL_CBUS_BANK + 0x34) 687 #define REG_PM_MHL_CBUS_1B (REG_PM_MHL_CBUS_BANK + 0x36) 688 #define REG_PM_MHL_CBUS_1C (REG_PM_MHL_CBUS_BANK + 0x38) 689 #define REG_PM_MHL_CBUS_1D (REG_PM_MHL_CBUS_BANK + 0x3A) 690 #define REG_PM_MHL_CBUS_1E (REG_PM_MHL_CBUS_BANK + 0x3C) 691 #define REG_PM_MHL_CBUS_1F (REG_PM_MHL_CBUS_BANK + 0x3E) 692 #define REG_PM_MHL_CBUS_20 (REG_PM_MHL_CBUS_BANK + 0x40) 693 #define REG_PM_MHL_CBUS_21 (REG_PM_MHL_CBUS_BANK + 0x42) 694 #define REG_PM_MHL_CBUS_22 (REG_PM_MHL_CBUS_BANK + 0x44) 695 #define REG_PM_MHL_CBUS_23 (REG_PM_MHL_CBUS_BANK + 0x46) 696 #define REG_PM_MHL_CBUS_24 (REG_PM_MHL_CBUS_BANK + 0x48) 697 #define REG_PM_MHL_CBUS_25 (REG_PM_MHL_CBUS_BANK + 0x4A) 698 #define REG_PM_MHL_CBUS_26 (REG_PM_MHL_CBUS_BANK + 0x4C) 699 #define REG_PM_MHL_CBUS_27 (REG_PM_MHL_CBUS_BANK + 0x4E) 700 #define REG_PM_MHL_CBUS_28 (REG_PM_MHL_CBUS_BANK + 0x50) 701 #define REG_PM_MHL_CBUS_29 (REG_PM_MHL_CBUS_BANK + 0x52) 702 #define REG_PM_MHL_CBUS_2A (REG_PM_MHL_CBUS_BANK + 0x54) 703 #define REG_PM_MHL_CBUS_2B (REG_PM_MHL_CBUS_BANK + 0x56) 704 #define REG_PM_MHL_CBUS_2C (REG_PM_MHL_CBUS_BANK + 0x58) 705 #define REG_PM_MHL_CBUS_2D (REG_PM_MHL_CBUS_BANK + 0x5A) 706 #define REG_PM_MHL_CBUS_2E (REG_PM_MHL_CBUS_BANK + 0x5C) 707 #define REG_PM_MHL_CBUS_2F (REG_PM_MHL_CBUS_BANK + 0x5E) 708 #define REG_PM_MHL_CBUS_30 (REG_PM_MHL_CBUS_BANK + 0x60) 709 #define REG_PM_MHL_CBUS_31 (REG_PM_MHL_CBUS_BANK + 0x62) 710 #define REG_PM_MHL_CBUS_32 (REG_PM_MHL_CBUS_BANK + 0x64) 711 #define REG_PM_MHL_CBUS_33 (REG_PM_MHL_CBUS_BANK + 0x66) 712 #define REG_PM_MHL_CBUS_34 (REG_PM_MHL_CBUS_BANK + 0x68) 713 #define REG_PM_MHL_CBUS_35 (REG_PM_MHL_CBUS_BANK + 0x6A) 714 #define REG_PM_MHL_CBUS_36 (REG_PM_MHL_CBUS_BANK + 0x6C) 715 #define REG_PM_MHL_CBUS_37 (REG_PM_MHL_CBUS_BANK + 0x6E) 716 #define REG_PM_MHL_CBUS_38 (REG_PM_MHL_CBUS_BANK + 0x70) 717 #define REG_PM_MHL_CBUS_39 (REG_PM_MHL_CBUS_BANK + 0x72) 718 #define REG_PM_MHL_CBUS_3A (REG_PM_MHL_CBUS_BANK + 0x74) 719 #define REG_PM_MHL_CBUS_3B (REG_PM_MHL_CBUS_BANK + 0x76) 720 #define REG_PM_MHL_CBUS_3C (REG_PM_MHL_CBUS_BANK + 0x78) 721 #define REG_PM_MHL_CBUS_3D (REG_PM_MHL_CBUS_BANK + 0x7A) 722 #define REG_PM_MHL_CBUS_3E (REG_PM_MHL_CBUS_BANK + 0x7C) 723 #define REG_PM_MHL_CBUS_3F (REG_PM_MHL_CBUS_BANK + 0x7E) 724 #define REG_PM_MHL_CBUS_40 (REG_PM_MHL_CBUS_BANK + 0x80) 725 #define REG_PM_MHL_CBUS_41 (REG_PM_MHL_CBUS_BANK + 0x82) 726 #define REG_PM_MHL_CBUS_42 (REG_PM_MHL_CBUS_BANK + 0x84) 727 #define REG_PM_MHL_CBUS_43 (REG_PM_MHL_CBUS_BANK + 0x86) 728 #define REG_PM_MHL_CBUS_44 (REG_PM_MHL_CBUS_BANK + 0x88) 729 #define REG_PM_MHL_CBUS_45 (REG_PM_MHL_CBUS_BANK + 0x8A) 730 #define REG_PM_MHL_CBUS_46 (REG_PM_MHL_CBUS_BANK + 0x8C) 731 #define REG_PM_MHL_CBUS_47 (REG_PM_MHL_CBUS_BANK + 0x8E) 732 #define REG_PM_MHL_CBUS_48 (REG_PM_MHL_CBUS_BANK + 0x90) 733 #define REG_PM_MHL_CBUS_49 (REG_PM_MHL_CBUS_BANK + 0x92) 734 #define REG_PM_MHL_CBUS_4A (REG_PM_MHL_CBUS_BANK + 0x94) 735 #define REG_PM_MHL_CBUS_4B (REG_PM_MHL_CBUS_BANK + 0x96) 736 #define REG_PM_MHL_CBUS_4C (REG_PM_MHL_CBUS_BANK + 0x98) 737 #define REG_PM_MHL_CBUS_4D (REG_PM_MHL_CBUS_BANK + 0x9A) 738 #define REG_PM_MHL_CBUS_4E (REG_PM_MHL_CBUS_BANK + 0x9C) 739 #define REG_PM_MHL_CBUS_4F (REG_PM_MHL_CBUS_BANK + 0x9E) 740 #define REG_PM_MHL_CBUS_50 (REG_PM_MHL_CBUS_BANK + 0xA0) 741 #define REG_PM_MHL_CBUS_51 (REG_PM_MHL_CBUS_BANK + 0xA2) 742 #define REG_PM_MHL_CBUS_52 (REG_PM_MHL_CBUS_BANK + 0xA4) 743 #define REG_PM_MHL_CBUS_53 (REG_PM_MHL_CBUS_BANK + 0xA6) 744 #define REG_PM_MHL_CBUS_54 (REG_PM_MHL_CBUS_BANK + 0xA8) 745 #define REG_PM_MHL_CBUS_55 (REG_PM_MHL_CBUS_BANK + 0xAA) 746 #define REG_PM_MHL_CBUS_56 (REG_PM_MHL_CBUS_BANK + 0xAC) 747 #define REG_PM_MHL_CBUS_57 (REG_PM_MHL_CBUS_BANK + 0xAE) 748 #define REG_PM_MHL_CBUS_58 (REG_PM_MHL_CBUS_BANK + 0xB0) 749 #define REG_PM_MHL_CBUS_59 (REG_PM_MHL_CBUS_BANK + 0xB2) 750 #define REG_PM_MHL_CBUS_5A (REG_PM_MHL_CBUS_BANK + 0xB4) 751 #define REG_PM_MHL_CBUS_5B (REG_PM_MHL_CBUS_BANK + 0xB6) 752 #define REG_PM_MHL_CBUS_5C (REG_PM_MHL_CBUS_BANK + 0xB8) 753 #define REG_PM_MHL_CBUS_5D (REG_PM_MHL_CBUS_BANK + 0xBA) 754 #define REG_PM_MHL_CBUS_5E (REG_PM_MHL_CBUS_BANK + 0xBC) 755 #define REG_PM_MHL_CBUS_5F (REG_PM_MHL_CBUS_BANK + 0xBE) 756 #define REG_PM_MHL_CBUS_60 (REG_PM_MHL_CBUS_BANK + 0xC0) 757 #define REG_PM_MHL_CBUS_61 (REG_PM_MHL_CBUS_BANK + 0xC2) 758 #define REG_PM_MHL_CBUS_62 (REG_PM_MHL_CBUS_BANK + 0xC4) 759 #define REG_PM_MHL_CBUS_63 (REG_PM_MHL_CBUS_BANK + 0xC6) 760 #define REG_PM_MHL_CBUS_64 (REG_PM_MHL_CBUS_BANK + 0xC8) 761 #define REG_PM_MHL_CBUS_65 (REG_PM_MHL_CBUS_BANK + 0xCA) 762 #define REG_PM_MHL_CBUS_66 (REG_PM_MHL_CBUS_BANK + 0xCC) 763 #define REG_PM_MHL_CBUS_67 (REG_PM_MHL_CBUS_BANK + 0xCE) 764 #define REG_PM_MHL_CBUS_68 (REG_PM_MHL_CBUS_BANK + 0xD0) 765 #define REG_PM_MHL_CBUS_69 (REG_PM_MHL_CBUS_BANK + 0xD2) 766 #define REG_PM_MHL_CBUS_6A (REG_PM_MHL_CBUS_BANK + 0xD4) 767 #define REG_PM_MHL_CBUS_6B (REG_PM_MHL_CBUS_BANK + 0xD6) 768 #define REG_PM_MHL_CBUS_6C (REG_PM_MHL_CBUS_BANK + 0xD8) 769 #define REG_PM_MHL_CBUS_6D (REG_PM_MHL_CBUS_BANK + 0xDA) 770 #define REG_PM_MHL_CBUS_6E (REG_PM_MHL_CBUS_BANK + 0xDC) 771 #define REG_PM_MHL_CBUS_6F (REG_PM_MHL_CBUS_BANK + 0xDE) 772 #define REG_PM_MHL_CBUS_70 (REG_PM_MHL_CBUS_BANK + 0xE0) 773 #define REG_PM_MHL_CBUS_71 (REG_PM_MHL_CBUS_BANK + 0xE2) 774 #define REG_PM_MHL_CBUS_72 (REG_PM_MHL_CBUS_BANK + 0xE4) 775 #define REG_PM_MHL_CBUS_73 (REG_PM_MHL_CBUS_BANK + 0xE6) 776 #define REG_PM_MHL_CBUS_74 (REG_PM_MHL_CBUS_BANK + 0xE8) 777 #define REG_PM_MHL_CBUS_75 (REG_PM_MHL_CBUS_BANK + 0xEA) 778 #define REG_PM_MHL_CBUS_76 (REG_PM_MHL_CBUS_BANK + 0xEC) 779 #define REG_PM_MHL_CBUS_77 (REG_PM_MHL_CBUS_BANK + 0xEE) 780 #define REG_PM_MHL_CBUS_78 (REG_PM_MHL_CBUS_BANK + 0xF0) 781 #define REG_PM_MHL_CBUS_79 (REG_PM_MHL_CBUS_BANK + 0xF2) 782 #define REG_PM_MHL_CBUS_7A (REG_PM_MHL_CBUS_BANK + 0xF4) 783 #define REG_PM_MHL_CBUS_7B (REG_PM_MHL_CBUS_BANK + 0xF6) 784 #define REG_PM_MHL_CBUS_7C (REG_PM_MHL_CBUS_BANK + 0xF8) 785 #define REG_PM_MHL_CBUS_7D (REG_PM_MHL_CBUS_BANK + 0xFA) 786 #define REG_PM_MHL_CBUS_7E (REG_PM_MHL_CBUS_BANK + 0xFC) 787 #define REG_PM_MHL_CBUS_7F (REG_PM_MHL_CBUS_BANK + 0xFE) 788 789 #endif 790 791