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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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93 ////////////////////////////////////////////////////////////////////////////////
94 #define MHAL_ADC_C
95 //-------------------------------------------------------------------------------------------------
96 // Include Files
97 //-------------------------------------------------------------------------------------------------
98 // Common Definition
99 #ifdef MSOS_TYPE_LINUX_KERNEL
100 #include <linux/delay.h>
101 #endif
102 #include "MsCommon.h"
103 #include "MsIRQ.h"
104 #include "MsOS.h"
105 #include "mhal_xc_chip_config.h"
106 #if 0
107 #include "drvXC_IOPort.h"
108 #include "xc_Analog_Reg.h"
109 #include "xc_hwreg_utility2.h"
110
111 #include "apiXC.h"
112 #include "apiXC_Adc.h"
113 #include "apiXC_Auto.h"
114 #include "drvXC_ADC_Internal.h"
115 #endif
MDrv_XC_ADC_Set_Freerun(void * pInstance,MS_BOOL bEnable)116 void MDrv_XC_ADC_Set_Freerun(void *pInstance, MS_BOOL bEnable)
117 {
118 //do nothing
119 return;
120 }
121
Hal_ADC_SourceSwitch(void * pInstance,MS_BOOL bSwitch)122 void Hal_ADC_SourceSwitch(void *pInstance, MS_BOOL bSwitch)
123 {
124 }
125
126 #if 0
127
128 // Internal Definition
129 #include "drvXC_IOPort.h"
130 #include "xc_Analog_Reg.h"
131 #include "xc_hwreg_utility2.h"
132 #include "hwreg_adc_atop.h"
133 #include "hwreg_adc_dtop.h"
134 #include "apiXC.h"
135 #include "apiXC_Adc.h"
136 #include "drvXC_ADC_Internal.h"
137 #include "mhal_adc.h"
138 #include "mhal_ip.h"
139
140 //-------------------------------------------------------------------------------------------------
141 // Driver Compiler Options
142 //-------------------------------------------------------------------------------------------------
143
144
145 //-------------------------------------------------------------------------------------------------
146 // Local Defines
147 //-------------------------------------------------------------------------------------------------
148
149
150 //-------------------------------------------------------------------------------------------------
151 // Local Structures
152 //-------------------------------------------------------------------------------------------------
153 typedef struct
154 {
155 MS_U8 u8L_BkAtop_00;
156 MS_U8 u8L_BkAtop_01;
157 MS_U8 u8L_BkAtop_03;
158 MS_U8 u8L_BkAtop_0C;
159 MS_U8 u8L_BkAtop_2C;
160 MS_U8 u8L_BkAtop_1F;
161 MS_U8 u8H_BkAtop_2D;
162 MS_U8 u8L_BkDtop_06;
163 MS_U8 u8H_BkChipTop_1F;
164 MS_U8 u8L_BkChipTop_55;
165 MS_U8 u8L_BkIpMux_1;
166 MS_U8 u8L_SC_BK1_21;
167 MS_U8 u8L_SC_BK10_19;
168 MS_U16 u16L_BkAtop_05;
169 MS_U16 u16L_BkAtop_5E;
170 MS_U16 u16BkAtop_1C;
171 MS_U16 u16BkAtop_05;
172 MS_U16 u16BkAtop_06;
173 MS_U16 u16BkDtop_01;
174 MS_U16 u16BkDtop_02;
175 MS_U16 u16SC_BK1_02;
176 MS_U16 u16SC_BK1_03;
177 MS_U16 u16SC_BK1_04;
178 MS_U16 u16SC_BK1_05;
179 MS_U16 u16SC_BK1_06;
180 MS_U16 u16SC_BK1_07;
181 MS_U16 u16SC_BK1_0E;
182 MS_U16 u16SC_BK12_01;
183 MS_U16 u16SC_BK12_03;
184 MS_U16 u16SC_BK12_04;
185 MS_U16 u16SC_BK12_0E;
186 MS_U16 u16SC_BK12_0F;
187 MS_U16 u16SC_BK12_16;
188 MS_U16 u16SC_BK12_17;
189 MS_U32 u32SC_BK12_10;
190 MS_U32 u32SC_BK12_12;
191 MS_U32 u32SC_BK12_14;
192 MS_U16 u16SC_BK12_07;
193 MS_U32 u32SC_BK12_08;
194 MS_U32 u32SC_BK12_0A;
195 MS_U32 u32SC_BK12_0C;
196 MS_U16 u16SC_BK02_04;
197 MS_U16 u16SC_BK02_05;
198 MS_U16 u16SC_BK02_08;
199 MS_U16 u16SC_BK02_09;
200 MS_U16 u16SC_BK23_07;
201 MS_U16 u16SC_BK23_08;
202 MS_U16 u16SC_BK23_09;
203 MS_U16 u16SC_BK23_0A;
204 MS_U16 u16SC_BK12_1A;
205 MS_U16 u16SC_BK12_1B;
206 MS_U16 u16SC_BK06_01;
207 MS_U16 u16SC_BK06_21;
208 MS_U16 u16SC_BK12_44;
209 MS_U16 u16SC_BK12_47;
210 } XC_Adc_BackupSetting;
211
212
213 typedef struct
214 {
215 MS_U8 u8ADC_Power_04L;
216 MS_U8 u8ADC_Power_04H;
217 MS_U8 u8ADC_Power_05L;
218 MS_U8 u8ADC_Power_06L;
219 MS_U8 u8ADC_Power_06H;
220 MS_U8 u8ADC_Power_60L;
221 MS_U8 u8ADC_Power_60H;
222 MS_U8 u8ADC_Power_69L;
223 MS_U8 u8ADC_Power_69H;
224 MS_U8 u8ADC_Power_40L;
225 }ADC_ATOP_POWERON_TBL_t;
226
227 //-------------------------------------------------------------------------------------------------
228 // Global Variables
229 //-------------------------------------------------------------------------------------------------
230
231 MS_U8 MST_ADCSetModeRGB_SOG_TBL[][REG_ADDR_SIZE+REG_MASK_SIZE+ADC_TABLE_SetMode_NUMS*REG_DATA_SIZE]=
232 { // Reg Mask Ignore Value
233 { DRV_ADC_REG(REG_ADC_ATOP_34_L), 0x0F, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
234 0x00, 0x01/*ADC_TABLE_FREQ_SECTION2*/,
235 0x00, 0x02/*ADC_TABLE_FREQ_SECTION3*/,
236 0x00, 0x04/*ADC_TABLE_FREQ_SECTION4*/,
237 0x00, 0x05/*ADC_TABLE_FREQ_SECTION5*/,
238 0x00, 0x06/*ADC_TABLE_FREQ_SECTION6*/,
239 0x00, 0x07/*ADC_TABLE_FREQ_SECTION7*/,
240 0x00, 0x08/*ADC_TABLE_FREQ_SECTION8*/,
241 0x00, 0x09/*ADC_TABLE_FREQ_SECTION9*/,
242 0x00, 0x0A/*ADC_TABLE_FREQ_SECTION10*/,
243 0x00, 0x0A/*ADC_TABLE_FREQ_SECTION11*/,
244 0x00, 0x0B/*ADC_TABLE_FREQ_SECTION12*/,
245 0x00, 0x0B/*ADC_TABLE_FREQ_SECTION13*/,
246 0x00, 0x0C/*ADC_TABLE_FREQ_SECTION14*/,
247 0x00, 0x0C/*ADC_TABLE_FREQ_SECTION15*/,
248 0x00, 0x0D/*ADC_TABLE_FREQ_SECTION16*/,
249 0x00, 0x0E/*ADC_TABLE_FREQ_SECTION17*/,},
250 { DRV_ADC_REG(REG_ADC_ATOP_34_L), 0xF0, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
251 0x00, 0x10/*ADC_TABLE_FREQ_SECTION2*/,
252 0x00, 0x20/*ADC_TABLE_FREQ_SECTION3*/,
253 0x00, 0x40/*ADC_TABLE_FREQ_SECTION4*/,
254 0x00, 0x50/*ADC_TABLE_FREQ_SECTION5*/,
255 0x00, 0x60/*ADC_TABLE_FREQ_SECTION6*/,
256 0x00, 0x70/*ADC_TABLE_FREQ_SECTION7*/,
257 0x00, 0x80/*ADC_TABLE_FREQ_SECTION8*/,
258 0x00, 0x90/*ADC_TABLE_FREQ_SECTION9*/,
259 0x00, 0xA0/*ADC_TABLE_FREQ_SECTION10*/,
260 0x00, 0xA0/*ADC_TABLE_FREQ_SECTION11*/,
261 0x00, 0xB0/*ADC_TABLE_FREQ_SECTION12*/,
262 0x00, 0xB0/*ADC_TABLE_FREQ_SECTION13*/,
263 0x00, 0xC0/*ADC_TABLE_FREQ_SECTION14*/,
264 0x00, 0xC0/*ADC_TABLE_FREQ_SECTION15*/,
265 0x00, 0xD0/*ADC_TABLE_FREQ_SECTION16*/,
266 0x00, 0xE0/*ADC_TABLE_FREQ_SECTION17*/,},
267 { DRV_ADC_REG(REG_ADC_ATOP_34_H), 0x0F, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
268 0x00, 0x01/*ADC_TABLE_FREQ_SECTION2*/,
269 0x00, 0x02/*ADC_TABLE_FREQ_SECTION3*/,
270 0x00, 0x04/*ADC_TABLE_FREQ_SECTION4*/,
271 0x00, 0x05/*ADC_TABLE_FREQ_SECTION5*/,
272 0x00, 0x06/*ADC_TABLE_FREQ_SECTION6*/,
273 0x00, 0x07/*ADC_TABLE_FREQ_SECTION7*/,
274 0x00, 0x08/*ADC_TABLE_FREQ_SECTION8*/,
275 0x00, 0x09/*ADC_TABLE_FREQ_SECTION9*/,
276 0x00, 0x0A/*ADC_TABLE_FREQ_SECTION10*/,
277 0x00, 0x0A/*ADC_TABLE_FREQ_SECTION11*/,
278 0x00, 0x0B/*ADC_TABLE_FREQ_SECTION12*/,
279 0x00, 0x0B/*ADC_TABLE_FREQ_SECTION13*/,
280 0x00, 0x0C/*ADC_TABLE_FREQ_SECTION14*/,
281 0x00, 0x0C/*ADC_TABLE_FREQ_SECTION15*/,
282 0x00, 0x0D/*ADC_TABLE_FREQ_SECTION16*/,
283 0x00, 0x0E/*ADC_TABLE_FREQ_SECTION17*/,},
284 { DRV_ADC_REG(REG_ADC_ATOP_34_H), 0xF0, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
285 0x00, 0x10/*ADC_TABLE_FREQ_SECTION2*/,
286 0x00, 0x20/*ADC_TABLE_FREQ_SECTION3*/,
287 0x00, 0x40/*ADC_TABLE_FREQ_SECTION4*/,
288 0x00, 0x50/*ADC_TABLE_FREQ_SECTION5*/,
289 0x00, 0x60/*ADC_TABLE_FREQ_SECTION6*/,
290 0x00, 0x70/*ADC_TABLE_FREQ_SECTION7*/,
291 0x00, 0x80/*ADC_TABLE_FREQ_SECTION8*/,
292 0x00, 0x90/*ADC_TABLE_FREQ_SECTION9*/,
293 0x00, 0xA0/*ADC_TABLE_FREQ_SECTION10*/,
294 0x00, 0xA0/*ADC_TABLE_FREQ_SECTION11*/,
295 0x00, 0xB0/*ADC_TABLE_FREQ_SECTION12*/,
296 0x00, 0xB0/*ADC_TABLE_FREQ_SECTION13*/,
297 0x00, 0xC0/*ADC_TABLE_FREQ_SECTION14*/,
298 0x00, 0xC0/*ADC_TABLE_FREQ_SECTION15*/,
299 0x00, 0xD0/*ADC_TABLE_FREQ_SECTION16*/,
300 0x00, 0xE0/*ADC_TABLE_FREQ_SECTION17*/,},
301 { DRV_ADC_REG(REG_ADC_ATOP_35_L), 0x0F, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
302 0x00, 0x01/*ADC_TABLE_FREQ_SECTION2*/,
303 0x00, 0x02/*ADC_TABLE_FREQ_SECTION3*/,
304 0x00, 0x04/*ADC_TABLE_FREQ_SECTION4*/,
305 0x00, 0x05/*ADC_TABLE_FREQ_SECTION5*/,
306 0x00, 0x06/*ADC_TABLE_FREQ_SECTION6*/,
307 0x00, 0x07/*ADC_TABLE_FREQ_SECTION7*/,
308 0x00, 0x08/*ADC_TABLE_FREQ_SECTION8*/,
309 0x00, 0x09/*ADC_TABLE_FREQ_SECTION9*/,
310 0x00, 0x0A/*ADC_TABLE_FREQ_SECTION10*/,
311 0x00, 0x0A/*ADC_TABLE_FREQ_SECTION11*/,
312 0x00, 0x0B/*ADC_TABLE_FREQ_SECTION12*/,
313 0x00, 0x0B/*ADC_TABLE_FREQ_SECTION13*/,
314 0x00, 0x0C/*ADC_TABLE_FREQ_SECTION14*/,
315 0x00, 0x0C/*ADC_TABLE_FREQ_SECTION15*/,
316 0x00, 0x0D/*ADC_TABLE_FREQ_SECTION16*/,
317 0x00, 0x0E/*ADC_TABLE_FREQ_SECTION17*/,},
318 { DRV_ADC_REG(REG_ADC_ATOP_35_L), 0xF0, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
319 0x00, 0x10/*ADC_TABLE_FREQ_SECTION2*/,
320 0x00, 0x20/*ADC_TABLE_FREQ_SECTION3*/,
321 0x00, 0x40/*ADC_TABLE_FREQ_SECTION4*/,
322 0x00, 0x50/*ADC_TABLE_FREQ_SECTION5*/,
323 0x00, 0x60/*ADC_TABLE_FREQ_SECTION6*/,
324 0x00, 0x70/*ADC_TABLE_FREQ_SECTION7*/,
325 0x00, 0x80/*ADC_TABLE_FREQ_SECTION8*/,
326 0x00, 0x90/*ADC_TABLE_FREQ_SECTION9*/,
327 0x00, 0xA0/*ADC_TABLE_FREQ_SECTION10*/,
328 0x00, 0xA0/*ADC_TABLE_FREQ_SECTION11*/,
329 0x00, 0xB0/*ADC_TABLE_FREQ_SECTION12*/,
330 0x00, 0xB0/*ADC_TABLE_FREQ_SECTION13*/,
331 0x00, 0xC0/*ADC_TABLE_FREQ_SECTION14*/,
332 0x00, 0xC0/*ADC_TABLE_FREQ_SECTION15*/,
333 0x00, 0xD0/*ADC_TABLE_FREQ_SECTION16*/,
334 0x00, 0xE0/*ADC_TABLE_FREQ_SECTION17*/,},
335 { DRV_ADC_REG(REG_ADC_DTOP_17_H), 0x0F, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
336 0x00, 0x00/*ADC_TABLE_FREQ_SECTION2*/,
337 0x00, 0x00/*ADC_TABLE_FREQ_SECTION3*/,
338 0x00, 0x00/*ADC_TABLE_FREQ_SECTION4*/,
339 0x00, 0x00/*ADC_TABLE_FREQ_SECTION5*/,
340 0x00, 0x00/*ADC_TABLE_FREQ_SECTION6*/,
341 0x00, 0x00/*ADC_TABLE_FREQ_SECTION7*/,
342 0x00, 0x00/*ADC_TABLE_FREQ_SECTION8*/,
343 0x00, 0x00/*ADC_TABLE_FREQ_SECTION9*/,
344 0x00, 0x00/*ADC_TABLE_FREQ_SECTION10*/,
345 0x00, 0x00/*ADC_TABLE_FREQ_SECTION11*/,
346 0x00, 0x00/*ADC_TABLE_FREQ_SECTION12*/,
347 0x00, 0x00/*ADC_TABLE_FREQ_SECTION13*/,
348 0x00, 0x00/*ADC_TABLE_FREQ_SECTION14*/,
349 0x00, 0x00/*ADC_TABLE_FREQ_SECTION15*/,
350 0x00, 0x00/*ADC_TABLE_FREQ_SECTION16*/,
351 0x00, 0x00/*ADC_TABLE_FREQ_SECTION17*/,},
352 { DRV_ADC_REG(REG_ADC_DTOP_17_L), 0xFF, 0x00, 0xF0/*ADC_TABLE_FREQ_SECTION1*/,
353 0x00, 0xF0/*ADC_TABLE_FREQ_SECTION2*/,
354 0x00, 0xF0/*ADC_TABLE_FREQ_SECTION3*/,
355 0x00, 0xD0/*ADC_TABLE_FREQ_SECTION4*/,
356 0x00, 0xD0/*ADC_TABLE_FREQ_SECTION5*/,
357 0x00, 0x80/*ADC_TABLE_FREQ_SECTION6*/,
358 0x00, 0xD0/*ADC_TABLE_FREQ_SECTION7*/,
359 0x00, 0x95/*ADC_TABLE_FREQ_SECTION8*/,
360 0x00, 0x95/*ADC_TABLE_FREQ_SECTION9*/,
361 0x00, 0x88/*ADC_TABLE_FREQ_SECTION10*/,
362 0x00, 0x88/*ADC_TABLE_FREQ_SECTION11*/,
363 0x00, 0x80/*ADC_TABLE_FREQ_SECTION12*/,
364 0x00, 0x80/*ADC_TABLE_FREQ_SECTION13*/,
365 0x00, 0x80/*ADC_TABLE_FREQ_SECTION14*/,
366 0x00, 0x60/*ADC_TABLE_FREQ_SECTION15*/,
367 0x00, 0x30/*ADC_TABLE_FREQ_SECTION16*/,
368 0x00, 0x30/*ADC_TABLE_FREQ_SECTION17*/,},
369 { DRV_ADC_REG(REG_ADC_DTOP_18_L), 0xFF, 0x00, 0x80/*ADC_TABLE_FREQ_SECTION1*/,
370 0x00, 0x80/*ADC_TABLE_FREQ_SECTION2*/,
371 0x00, 0x80/*ADC_TABLE_FREQ_SECTION3*/,
372 0x00, 0x80/*ADC_TABLE_FREQ_SECTION4*/,
373 0x00, 0x80/*ADC_TABLE_FREQ_SECTION5*/,
374 0x00, 0x40/*ADC_TABLE_FREQ_SECTION6*/,
375 0x00, 0x40/*ADC_TABLE_FREQ_SECTION7*/,
376 0x00, 0x40/*ADC_TABLE_FREQ_SECTION8*/,
377 0x00, 0x40/*ADC_TABLE_FREQ_SECTION9*/,
378 0x00, 0x30/*ADC_TABLE_FREQ_SECTION10*/,
379 0x00, 0x30/*ADC_TABLE_FREQ_SECTION11*/,
380 0x00, 0x20/*ADC_TABLE_FREQ_SECTION12*/,
381 0x00, 0x20/*ADC_TABLE_FREQ_SECTION13*/,
382 0x00, 0x20/*ADC_TABLE_FREQ_SECTION14*/,
383 0x00, 0x20/*ADC_TABLE_FREQ_SECTION15*/,
384 0x00, 0x20/*ADC_TABLE_FREQ_SECTION16*/,
385 0x00, 0x20/*ADC_TABLE_FREQ_SECTION17*/,},
386 { DRV_ADC_REG(REG_ADC_DTOP_19_H), 0x60, 0x00, 0x40/*ADC_TABLE_FREQ_SECTION1*/,
387 0x00, 0x40/*ADC_TABLE_FREQ_SECTION2*/,
388 0x00, 0x40/*ADC_TABLE_FREQ_SECTION3*/,
389 0x00, 0x40/*ADC_TABLE_FREQ_SECTION4*/,
390 0x00, 0x40/*ADC_TABLE_FREQ_SECTION5*/,
391 0x00, 0x40/*ADC_TABLE_FREQ_SECTION6*/,
392 0x00, 0x40/*ADC_TABLE_FREQ_SECTION7*/,
393 0x00, 0x20/*ADC_TABLE_FREQ_SECTION8*/,
394 0x00, 0x20/*ADC_TABLE_FREQ_SECTION9*/,
395 0x00, 0x20/*ADC_TABLE_FREQ_SECTION10*/,
396 0x00, 0x20/*ADC_TABLE_FREQ_SECTION11*/,
397 0x00, 0x00/*ADC_TABLE_FREQ_SECTION12*/,
398 0x00, 0x00/*ADC_TABLE_FREQ_SECTION13*/,
399 0x00, 0x00/*ADC_TABLE_FREQ_SECTION14*/,
400 0x00, 0x00/*ADC_TABLE_FREQ_SECTION15*/,
401 0x00, 0x00/*ADC_TABLE_FREQ_SECTION16*/,
402 0x00, 0x00/*ADC_TABLE_FREQ_SECTION17*/,},
403 { DRV_ADC_REG(REG_ADC_ATOP_0D_L), 0x10, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
404 0x00, 0x00/*ADC_TABLE_FREQ_SECTION2*/,
405 0x00, 0x00/*ADC_TABLE_FREQ_SECTION3*/,
406 0x00, 0x00/*ADC_TABLE_FREQ_SECTION4*/,
407 0x00, 0x00/*ADC_TABLE_FREQ_SECTION5*/,
408 0x00, 0x00/*ADC_TABLE_FREQ_SECTION6*/,
409 0x00, 0x00/*ADC_TABLE_FREQ_SECTION7*/,
410 0x00, 0x00/*ADC_TABLE_FREQ_SECTION8*/,
411 0x00, 0x00/*ADC_TABLE_FREQ_SECTION9*/,
412 0x00, 0x00/*ADC_TABLE_FREQ_SECTION10*/,
413 0x00, 0x00/*ADC_TABLE_FREQ_SECTION11*/,
414 0x00, 0x00/*ADC_TABLE_FREQ_SECTION12*/,
415 0x00, 0x00/*ADC_TABLE_FREQ_SECTION13*/,
416 0x00, 0x00/*ADC_TABLE_FREQ_SECTION14*/,
417 0x00, 0x10/*ADC_TABLE_FREQ_SECTION15*/,
418 0x00, 0x10/*ADC_TABLE_FREQ_SECTION16*/,
419 0x00, 0x10/*ADC_TABLE_FREQ_SECTION17*/,},
420 { DRV_ADC_REG(REG_ADC_ATOP_0C_L), 0x07, 0x00, 0x01/*ADC_TABLE_FREQ_SECTION1*/,
421 0x00, 0x01/*ADC_TABLE_FREQ_SECTION2*/,
422 0x00, 0x01/*ADC_TABLE_FREQ_SECTION3*/,
423 0x00, 0x01/*ADC_TABLE_FREQ_SECTION4*/,
424 0x00, 0x01/*ADC_TABLE_FREQ_SECTION5*/,
425 0x00, 0x00/*ADC_TABLE_FREQ_SECTION6*/,
426 0x00, 0x00/*ADC_TABLE_FREQ_SECTION7*/,
427 0x00, 0x00/*ADC_TABLE_FREQ_SECTION8*/,
428 0x00, 0x00/*ADC_TABLE_FREQ_SECTION9*/,
429 0x00, 0x00/*ADC_TABLE_FREQ_SECTION10*/,
430 0x00, 0x00/*ADC_TABLE_FREQ_SECTION11*/,
431 0x00, 0x00/*ADC_TABLE_FREQ_SECTION12*/,
432 0x00, 0x00/*ADC_TABLE_FREQ_SECTION13*/,
433 0x00, 0x00/*ADC_TABLE_FREQ_SECTION14*/,
434 0x00, 0x00/*ADC_TABLE_FREQ_SECTION15*/,
435 0x00, 0x00/*ADC_TABLE_FREQ_SECTION16*/,
436 0x00, 0x00/*ADC_TABLE_FREQ_SECTION17*/,},
437 { DRV_ADC_REG(REG_ADC_ATOP_09_H), 0x18, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
438 0x00, 0x00/*ADC_TABLE_FREQ_SECTION2*/,
439 0x00, 0x00/*ADC_TABLE_FREQ_SECTION3*/,
440 0x00, 0x00/*ADC_TABLE_FREQ_SECTION4*/,
441 0x00, 0x00/*ADC_TABLE_FREQ_SECTION5*/,
442 0x00, 0x00/*ADC_TABLE_FREQ_SECTION6*/,
443 0x00, 0x00/*ADC_TABLE_FREQ_SECTION7*/,
444 0x00, 0x08/*ADC_TABLE_FREQ_SECTION8*/,
445 0x00, 0x08/*ADC_TABLE_FREQ_SECTION9*/,
446 0x00, 0x08/*ADC_TABLE_FREQ_SECTION10*/,
447 0x00, 0x08/*ADC_TABLE_FREQ_SECTION11*/,
448 0x00, 0x10/*ADC_TABLE_FREQ_SECTION12*/,
449 0x00, 0x10/*ADC_TABLE_FREQ_SECTION13*/,
450 0x00, 0x10/*ADC_TABLE_FREQ_SECTION14*/,
451 0x00, 0x18/*ADC_TABLE_FREQ_SECTION15*/,
452 0x00, 0x18/*ADC_TABLE_FREQ_SECTION16*/,
453 0x00, 0x18/*ADC_TABLE_FREQ_SECTION17*/,},
454 { DRV_ADC_REG(REG_ADC_ATOP_0A_L), 0x04, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
455 0x00, 0x00/*ADC_TABLE_FREQ_SECTION2*/,
456 0x00, 0x00/*ADC_TABLE_FREQ_SECTION3*/,
457 0x00, 0x00/*ADC_TABLE_FREQ_SECTION4*/,
458 0x00, 0x00/*ADC_TABLE_FREQ_SECTION5*/,
459 0x00, 0x00/*ADC_TABLE_FREQ_SECTION6*/,
460 0x00, 0x00/*ADC_TABLE_FREQ_SECTION7*/,
461 0x00, 0x00/*ADC_TABLE_FREQ_SECTION8*/,
462 0x00, 0x00/*ADC_TABLE_FREQ_SECTION9*/,
463 0x00, 0x00/*ADC_TABLE_FREQ_SECTION10*/,
464 0x00, 0x00/*ADC_TABLE_FREQ_SECTION11*/,
465 0x00, 0x00/*ADC_TABLE_FREQ_SECTION12*/,
466 0x00, 0x00/*ADC_TABLE_FREQ_SECTION13*/,
467 0x00, 0x00/*ADC_TABLE_FREQ_SECTION14*/,
468 0x00, 0x04/*ADC_TABLE_FREQ_SECTION15*/,
469 0x00, 0x04/*ADC_TABLE_FREQ_SECTION16*/,
470 0x00, 0x04/*ADC_TABLE_FREQ_SECTION17*/,},
471 { DRV_ADC_REG(REG_ADC_ATOP_61_H), 0x60, 0x00, 0x00/*ADC_TABLE_FREQ_SECTION1*/,
472 0x00, 0x00/*ADC_TABLE_FREQ_SECTION2*/,
473 0x00, 0x00/*ADC_TABLE_FREQ_SECTION3*/,
474 0x00, 0x00/*ADC_TABLE_FREQ_SECTION4*/,
475 0x00, 0x00/*ADC_TABLE_FREQ_SECTION5*/,
476 0x00, 0x00/*ADC_TABLE_FREQ_SECTION6*/,
477 0x00, 0x00/*ADC_TABLE_FREQ_SECTION7*/,
478 0x00, 0x00/*ADC_TABLE_FREQ_SECTION8*/,
479 0x00, 0x00/*ADC_TABLE_FREQ_SECTION9*/,
480 0x00, 0x00/*ADC_TABLE_FREQ_SECTION10*/,
481 0x00, 0x00/*ADC_TABLE_FREQ_SECTION11*/,
482 0x00, 0x00/*ADC_TABLE_FREQ_SECTION12*/,
483 0x00, 0x00/*ADC_TABLE_FREQ_SECTION13*/,
484 0x00, 0x00/*ADC_TABLE_FREQ_SECTION14*/,
485 0x00, 0x20/*ADC_TABLE_FREQ_SECTION15*/,
486 0x00, 0x20/*ADC_TABLE_FREQ_SECTION16*/,
487 0x00, 0x20/*ADC_TABLE_FREQ_SECTION17*/,},
488 { DRV_ADC_REG(REG_ADC_ATOP_09_H), 0x07, 0x00, 0x02/*ADC_TABLE_FREQ_SECTION1*/,
489 0x00, 0x02/*ADC_TABLE_FREQ_SECTION2*/,
490 0x00, 0x02/*ADC_TABLE_FREQ_SECTION3*/,
491 0x00, 0x02/*ADC_TABLE_FREQ_SECTION4*/,
492 0x00, 0x02/*ADC_TABLE_FREQ_SECTION5*/,
493 0x00, 0x01/*ADC_TABLE_FREQ_SECTION6*/,
494 0x00, 0x01/*ADC_TABLE_FREQ_SECTION7*/,
495 0x00, 0x02/*ADC_TABLE_FREQ_SECTION8*/,
496 0x00, 0x02/*ADC_TABLE_FREQ_SECTION9*/,
497 0x00, 0x02/*ADC_TABLE_FREQ_SECTION10*/,
498 0x00, 0x02/*ADC_TABLE_FREQ_SECTION11*/,
499 0x00, 0x04/*ADC_TABLE_FREQ_SECTION12*/,
500 0x00, 0x04/*ADC_TABLE_FREQ_SECTION13*/,
501 0x00, 0x04/*ADC_TABLE_FREQ_SECTION14*/,
502 0x00, 0x06/*ADC_TABLE_FREQ_SECTION15*/,
503 0x00, 0x06/*ADC_TABLE_FREQ_SECTION16*/,
504 0x00, 0x06/*ADC_TABLE_FREQ_SECTION17*/,},
505 { DRV_ADC_REG(REG_TABLE_END), 0x00, 0x00, 0x00 }
506 };
507
508
509
510
511 //-------------------------------------------------------------------------------------------------
512 // Local Variables
513 //-------------------------------------------------------------------------------------------------
514 static XC_Adc_BackupSetting _stAutoAdcSetting;
515
516 //-------------------------------------------------------------------------------------------------
517 // Debug Functions
518 //-------------------------------------------------------------------------------------------------
519
520
521 //-------------------------------------------------------------------------------------------------
522 // Local Functions
523 //-------------------------------------------------------------------------------------------------
524
525
526 //-------------------------------------------------------------------------------------------------
527 // Global Functions
528 //-------------------------------------------------------------------------------------------------
529
530 /******************************************************************************/
531 ///ADC soft reset
532 /******************************************************************************/
533 void Hal_ADC_reset(MS_U16 u16Reset)
534 {
535
536 // Remove ADC reset after T3
537 /*
538 W2BYTE(REG_ADC_ATOP_07_L, u16Reset);
539 W2BYTE(REG_ADC_ATOP_07_L, 0x0000);
540 */
541 }
542
543 /******************************************************************************/
544 ///This function will set ADC registers for different port
545 ///@param enInputSourceType \b IN: source type
546 ///@param u8InputClock \b IN: pixel clock
547 /******************************************************************************/
548 //=========================================================//
549 // Function : Hal_ADC_ext_clk_en
550 // Description:
551 //=========================================================//
552 void Hal_ADC_ext_clk_en(MS_BOOL benable)
553 {
554 W2BYTEMSK(REG_ADC_ATOP_58_L, (benable ? BIT(7):0), BIT(7));
555 }
556
557 //=========================================================//
558 // Function : Hal_ADC_hdmi_vco_ctrl
559 // Description:
560 //=========================================================//
561 void Hal_ADC_hdmi_vco_ctrl(MS_U16 u16InputClock)
562 {
563 if (u16InputClock > 108)
564 {
565 W2BYTEMSK(REG_ADC_ATOP_4C_L, (0x02<<8), HBMASK);
566 }
567 else
568 {
569 W2BYTEMSK(REG_ADC_ATOP_4C_L, (0x0E<<8), HBMASK);
570 }
571
572 }
573 //=========================================================//
574 // Function : Hal_ADC_vco_ctrl
575 // Description:
576 //=========================================================//
577 void Hal_ADC_vco_ctrl(MS_U16 u16InputClock)
578 {
579 MS_U8 u8Value;
580
581 // VCO range/Settling time
582 if (u16InputClock > 150)
583 {
584 // high
585 u8Value = 0x02;
586 }
587 else if (u16InputClock > 20)
588 {
589 // middle
590 u8Value = 0x01;
591 }
592 else
593 {
594 // low
595 u8Value = 0x00;
596 }
597 // set multiplier of ADC PLL clock
598 W2BYTEMSK(REG_ADC_ATOP_0C_L, u8Value, (BIT(2)|BIT(1)|BIT(0)));
599 }
600
601 void Hal_ADC_set_vco_ctrl(MS_BOOL bIsDVIPort, MS_U16 u16InputClock)
602 {
603 // enable external clock
604 Hal_ADC_ext_clk_en(ENABLE);
605
606 if ( bIsDVIPort )
607 {
608 Hal_ADC_hdmi_vco_ctrl(u16InputClock);
609 }
610 else
611 {
612 Hal_ADC_vco_ctrl(u16InputClock);
613 }
614
615 // disable external clock
616 Hal_ADC_ext_clk_en(DISABLE);
617 }
618
619 /******************************************************************************/
620 ///This function sets PLL clock divider ratio
621 ///@param u16Value \b IN: PLL clock divider ratio
622 /******************************************************************************/
623 void Hal_ADC_dtop_clk_setting ( MS_U16 u16Value )
624 {
625 // limit set ADC PLL
626 if((u16Value > 3) && (u16Value < ADC_MAX_CLK))
627 {
628 u16Value -= 3; // actual - 3
629 W2BYTE(REG_ADC_DTOP_00_L, u16Value);
630 }
631 }
632
633 /******************************************************************************/
634 ///This function return phase steps of current chip
635 ///@param u8Value \b IN: phase steps
636 /******************************************************************************/
637 MS_U16 Hal_ADC_get_phase_range(void)
638 {
639 return 128;
640 }
641
642 MS_U8 Hal_ADC_get_phase(void)
643 {
644 return ( (MS_U8) R2BYTEMSK(REG_ADC_DTOP_03_L,LBMASK) ) ;
645 }
646
647 MS_U16 Hal_ADC_get_phaseEx(void)
648 {
649 return ( (MS_U16) R2BYTEMSK(REG_ADC_DTOP_03_L,LBMASK) ) ;
650 }
651
652 /******************************************************************************/
653 ///This function sets PLL phase
654 ///@param u8Value \b IN: PLL phase divider ratio
655 /******************************************************************************/
656 void Hal_ADC_set_phase( MS_U8 u8Value )
657 {
658 W2BYTEMSK(REG_ADC_DTOP_03_L, u8Value, LBMASK);
659 }
660
661 void Hal_ADC_set_phaseEx( MS_U16 u16Value )
662 {
663 W2BYTEMSK(REG_ADC_DTOP_03_L, u16Value, LBMASK);
664 }
665
666 /******************************************************************************/
667 ///This function sets ADC offset
668 ///@param *pstADCSetting \b IN: pointer to ADC settings
669 /******************************************************************************/
670 void Hal_ADC_offset_setting ( XC_AdcGainOffsetSetting *pstADCSetting )
671 {
672 W2BYTEMSK(REG_ADC_DTOP_08_L, (~(pstADCSetting->u16RedOffset))<<8, HBMASK);
673 W2BYTEMSK(REG_ADC_DTOP_09_L, (~(pstADCSetting->u16GreenOffset))<<8, HBMASK);
674 W2BYTEMSK(REG_ADC_DTOP_0A_L, (~(pstADCSetting->u16BlueOffset))<<8, HBMASK);
675 }
676
677 /******************************************************************************/
678 ///This function sets ADC gain
679 ///@param *pstADCSetting \b IN: pointer to ADC settings
680 /******************************************************************************/
681 void Hal_ADC_gain_setting ( XC_AdcGainOffsetSetting *pstADCSetting )
682 {
683 W2BYTEMSK(REG_ADC_DTOP_08_L, ~(pstADCSetting->u16RedGain), LBMASK);
684 W2BYTEMSK(REG_ADC_DTOP_09_L, ~(pstADCSetting->u16GreenGain), LBMASK);
685 W2BYTEMSK(REG_ADC_DTOP_0A_L, ~(pstADCSetting->u16BlueGain), LBMASK);
686 }
687
688 /******************************************************************************/
689 ///This function enable/disable output double buffer
690 ///@param bEnable \b IN:
691 ///- Enable: Turn on ADC double buffer
692 ///- Disable: Turn off ADC double buffer
693 /******************************************************************************/
694 void Hal_ADC_doublebuffer_setting(MS_BOOL bEnable)
695 {
696 W2BYTEMSK(REG_ADC_DTOP_07_L, (bEnable ? BIT(0):0), BIT(0));
697 }
698
699 /******************************************************************************/
700 ///This function recalibrates ADC offset. This function should be called
701 ///after mode changed.
702 ///@param bFlag \b IN:
703 ///- 0: Turn on
704 ///- 1: Turn off
705 /******************************************************************************/
706 void Hal_ADC_dtop_calibration_target_setting(MS_BOOL bIsYPbPrFlag)
707 {
708 if(bIsYPbPrFlag)
709 {
710 // Use code 16 as offset CAL target
711 W2BYTEMSK(REG_ADC_DTOP_10_L, BIT(15), BIT(15));
712 }
713 else
714 {
715 // Use code 0 as offset CAL target
716 W2BYTEMSK(REG_ADC_DTOP_10_L, 0, BIT(15));
717 }
718 }
719 void Hal_ADC_dtop_sw_mode_setting(MS_BOOL bEnable, MS_BOOL bIsAutoSWMode)
720 {
721 if(bEnable)
722 {
723 if (bIsAutoSWMode) //normal procedure
724 {
725 W2BYTEMSK(REG_ADC_DTOP_10_L, 0x00, 0xF3);
726 }
727 else
728 {
729 W2BYTEMSK(REG_ADC_DTOP_10_L, 0x50, 0xF3);
730 }
731
732 }
733 else //used when doing YPbPr calibration with software mode
734 {
735 W2BYTEMSK(REG_ADC_DTOP_10_L, 0x00, 0xF3);
736 }
737 }
738
739 void Hal_ADC_Set_Source_Calibration(ADC_INPUTSOURCE_TYPE enADC_SourceType)
740 {
741 return;
742 }
743
744 /******************************************************************************/
745 ///This function sets clamp placement
746 ///@param u8Value \b IN:
747 /******************************************************************************/
748 void Hal_ADC_clamp_placement_setting(MS_U16 u16InputClockMHz)
749 {
750 if(u16InputClockMHz>= 40)
751 {
752 /* Vclamp_dly */
753 W2BYTEMSK(REG_ADC_DTOP_0B_L, 0x38, LBMASK);
754 }
755 else
756 {
757 W2BYTEMSK(REG_ADC_DTOP_0B_L, 0x08, LBMASK);
758 }
759 }
760
761
762 void Hal_XC_ADC_Set_VClamp_level(ADC_VClamp_Level_Type type)
763 {
764 MS_U16 VClampSetting=E_ADC_VClamp_0_85V;
765 switch(type)
766 {
767 case E_ADC_VClamp_0_85V:
768 VClampSetting = 0x2;
769 break;
770 case E_ADC_VClamp_0_9V:
771 VClampSetting = 0x3;
772 break;
773 case E_ADC_VClamp_0_95V:
774 VClampSetting = 0x4;
775 break;
776 case E_ADC_VClamp_1_0V:
777 VClampSetting = 0x5;
778 break;
779 case E_ADC_VClamp_1_05V:
780 VClampSetting = 0x6;
781 break;
782 case E_ADC_VClamp_1_2V:
783 VClampSetting = 0x1;
784 break;
785 case E_ADC_VClamp_1_5V:
786 VClampSetting = 0x8;
787 break;
788 }
789 W2BYTEMSK(REG_ADC_ATOP_2D_L, VClampSetting << 8, HBMASK);
790 }
791
792 /******************************************************************************/
793 ///This function sets input HSync polarity
794 ///@param u8Value \b IN:
795 /******************************************************************************/
796 void Hal_ADC_hpolarity_setting(MS_BOOL bHightActive)
797 {
798 W2BYTEMSK(REG_ADC_DTOP_07_L, (bHightActive ? BIT(7):0), BIT(7));
799 }
800
801 /******************************************************************************/
802 ///This function power off ADC
803 /******************************************************************************/
804 void Hal_ADC_poweroff(void)
805 {
806 // W2BYTE(REG_ADC_ATOP_04_L, 0xFFFE); // Bit-0 is relative to DRAM.
807 // W2BYTEMSK(REG_ADC_ATOP_05_L, 0xFF, LBMASK);
808 W2BYTE(REG_ADC_ATOP_06_L, 0xFFFF);
809 // W2BYTE(REG_ADC_ATOP_60_L, 0xFFFF); // Bit-4 is relative to DRAM
810 // W2BYTE(REG_ADC_ATOP_69_L, 0xFFFF); // Bit-4 is relative to DRAM
811 W2BYTEMSK(REG_ADC_ATOP_70_L, 0x0F, LBMASK); // reg_cvbso1_pd
812
813 W2BYTEMSK(REG_ADC_ATOP_4C_L, BIT(5), BIT(5));
814 // W2BYTEMSK(REG_ADC_ATOP_40_L, BIT(6), BIT(6));
815 }
816
817 //----------------------------------------------------------------------
818 //
819 //----------------------------------------------------------------------
820 void Hal_ADC_dtop_internaldc_setting(ADC_Internal_Voltage InternalVoltage)
821 {
822 MS_U16 u16regvalue = 0;
823
824 switch ( InternalVoltage )
825 {
826 case E_ADC_Internal_0V:
827 u16regvalue = 0x00;
828 break;
829 case E_ADC_Internal_0_1V:
830 u16regvalue = 0x20;
831 break;
832 case E_ADC_Internal_0_6V:
833 u16regvalue = 0x30; //switch internal to 0.6V
834 break;
835 default:
836 u16regvalue = 0x00;
837 break;
838 }
839
840 W2BYTEMSK(REG_ADC_DTOP_13_L, InternalVoltage, 0x30);
841 }
842
843 void Hal_ADC_ExitExternalCalibration(ADC_INPUTSOURCE_TYPE eADC_Source,XC_AdcGainOffsetSetting* InitialGainOffset)
844 {
845 if ( eADC_Source == ADC_INPUTSOURCE_ONLY_RGB)
846 {
847
848 }
849 else if ( eADC_Source == ADC_INPUTSOURCE_ONLY_YPBPR)
850 {
851
852
853 }
854 else if (eADC_Source == ADC_INPUTSOURCE_ONLY_SCART )
855 {
856 W2BYTEMSK(REG_ADC_ATOP_42_L, BIT(5) , BIT(5));
857 }
858 else
859 {
860 // Undefined.
861 }
862
863 }
864
865 #endif
866
867 // If define this function to false, driver layer will cause dead_error_condition (if condition always be false)
868 // So we need implement this function
Hal_ADC_InitExternalCalibration(void * pInstance,MS_U32 enAdcSource)869 MS_BOOL Hal_ADC_InitExternalCalibration(void *pInstance, MS_U32 enAdcSource)
870 {
871 return FALSE;
872 }
873
874 #if 0
875 void Hal_ADC_InitInternalCalibration(SCALER_WIN eWindow)
876 {
877 XC_AdcGainOffsetSetting gain_offset_setting;
878
879 MS_U8 u8Bank;
880 u8Bank = MDrv_ReadByte(BK_SELECT_00);
881
882 if(eWindow == SUB_WINDOW)
883 {
884 // 444 format
885 MDrv_WriteByte( BK_SELECT_00, REG_BANK_SCMI);
886 MDrv_WriteRegBit(L_BK_SCMI(0x41), TRUE, BIT(5));
887 MDrv_WriteRegBit(L_BK_SCMI(0x43), FALSE, BIT(4));
888 //MDrv_WriteRegBit(H_BK_SCMI(0x43), 0x0, (BIT(4)|BIT(5)));//disable mirror
889
890 // 10-bit
891 MDrv_WriteByte( BK_SELECT_00, REG_BANK_SCMI);
892 MDrv_WriteByteMask(H_BK_SCMI(0x41), 0x01, BIT(0)|BIT(1)|BIT(2));
893 MDrv_WriteByteMask(H_BK_SCMI(0x41), 0x00, BIT(4)|BIT(5)|BIT(6));
894 MDrv_WriteRegBit(L_BK_SCMI(0x44), TRUE, BIT(1));
895
896 MDrv_WriteByte( BK_SELECT_00, REG_BANK_IP1F1 );
897 MDrv_WriteByte(L_BK_IP1F1(0x0E), 0x11); // enable auto gain function
898
899 // Disable NR
900 //SC_W2BYTEMSK(REG_SC_BK06_21_L, 0, BIT(1)|BIT(0));
901 //SC_W2BYTEMSK(REG_SC_BK06_01_L, 0, BIT(1)|BIT(0));
902
903 //framebuffer number
904 //SC_W2BYTEMSK(REG_SC_BK12_04_L, 0, BIT(6)|BIT(7));
905 //SC_W2BYTEMSK(REG_SC_BK12_07_L, 0, BIT(13));
906 SC_W2BYTEMSK(REG_SC_BK12_44_L, 0, BIT(6)|BIT(7));
907 SC_W2BYTEMSK(REG_SC_BK12_47_L, 0, BIT(13));
908 }
909 else
910 {
911 // 444 format
912 MDrv_WriteByte( BK_SELECT_00, REG_BANK_SCMI);
913 MDrv_WriteRegBit(L_BK_SCMI(0x01), TRUE, BIT(5));
914 MDrv_WriteRegBit(L_BK_SCMI(0x03), FALSE, BIT(4));
915 //MDrv_WriteRegBit(H_BK_SCMI(0x03), 0x0, (BIT(4)|BIT(5)));//disable mirror
916
917 // 10-bit
918 MDrv_WriteByte( BK_SELECT_00, REG_BANK_SCMI);
919 MDrv_WriteByteMask(H_BK_SCMI(0x01), 0x01, BIT(0)|BIT(1)|BIT(2));
920 MDrv_WriteByteMask(H_BK_SCMI(0x01), 0x00, BIT(4)|BIT(5)|BIT(6));
921 MDrv_WriteRegBit(L_BK_SCMI(0x04), TRUE, BIT(1));
922
923 MDrv_WriteByte( BK_SELECT_00, REG_BANK_IP1F2 );
924 MDrv_WriteByte(L_BK_IP1F2(0x0E), 0x11); // enable auto gain function
925
926 // Disable NR
927 SC_W2BYTEMSK(REG_SC_BK06_21_L, 0, BIT(1)|BIT(0));
928 SC_W2BYTEMSK(REG_SC_BK06_01_L, 0, BIT(1)|BIT(0));
929
930 //framebuffer number
931 SC_W2BYTEMSK(REG_SC_BK12_04_L, 0, BIT(6)|BIT(7));
932 SC_W2BYTEMSK(REG_SC_BK12_07_L, 0, BIT(13));
933 //SC_W2BYTEMSK(REG_SC_BK12_44_L, 0, BIT(6)|BIT(7));
934 //SC_W2BYTEMSK(REG_SC_BK12_47_L, 0, BIT(13));
935 }
936
937
938 // Set gain offset as middle core.
939 gain_offset_setting.u16BlueGain = gain_offset_setting.u16GreenGain =
940 gain_offset_setting.u16RedGain = 0x80;
941
942 gain_offset_setting.u16BlueOffset = gain_offset_setting.u16GreenOffset =
943 gain_offset_setting.u16RedOffset = 0x80;
944
945 Hal_ADC_offset_setting(&gain_offset_setting);
946 Hal_ADC_gain_setting(&gain_offset_setting);
947
948
949 MDrv_Write2Byte(REG_ADC_ATOP_00_L ,0x0001 );
950 MDrv_Write2Byte(REG_ADC_ATOP_04_L ,0xFE00 );
951 MDrv_Write2Byte(REG_ADC_ATOP_05_L ,0x009B );
952 MDrv_Write2Byte(REG_ADC_ATOP_06_L ,0xEBF0);
953
954 W2BYTEMSK( L_BK_IPMUX(0x01) , 0xF0, 0xF0 ); //select pattern generator source
955 if(eADC_Source == ADC_INPUTSOURCE_ONLY_SCART )
956 {
957 MDrv_Write2Byte(REG_ADC_ATOP_03_L ,0x0000 );
958 MDrv_Write2Byte(REG_ADC_ATOP_5E_L ,0x0200);
959 MDrv_WriteByte(L_BK_CHIPTOP(0x55),0x00);
960 }
961
962 MDrv_WriteByte(REG_ADC_ATOP_1C_H, 0xF8); // Turn on SOG input low bandwidth filter
963
964 MDrv_WriteByte(BK_SELECT_00, u8Bank);
965
966 }
967
968
969 void Hal_ADC_clk_gen_setting(ADC_Gen_Clock_Type clocktype)
970 {
971
972 W2BYTEMSK(REG_ADC_ATOP_01_L, 0x0f, 0x0f );
973
974 W2BYTEMSK(REG_ADC_ATOP_1C_L, BIT(5), BIT(5) ); /// turn off ADC a SoG comparator
975 W2BYTEMSK(REG_ADC_ATOP_1F_L, BIT(5), BIT(5) ); /// turn off ADC a SoG comparator
976
977
978 switch(clocktype)
979 {
980 case E_ADC_Gen_480P_Clk:
981 default:
982 W2BYTEMSK(REG_ADC_ATOP_0C_L, 0x00, 0x07 );
983 W2BYTE(REG_ADC_DTOP_01_L, 0x0040);
984 W2BYTE(REG_ADC_DTOP_02_L, 0x0000);
985 break;
986 case E_ADC_Gen_720P_Clk:
987 W2BYTEMSK(REG_ADC_ATOP_0C_L, 0x01, 0x07 );
988 W2BYTE(REG_ADC_DTOP_01_L, 0xB82E);
989 W2BYTE(REG_ADC_DTOP_02_L, 0x0052);
990 break;
991 case E_ADC_Gen_1080P_Clk:
992 W2BYTEMSK(REG_ADC_ATOP_0C_L, 0x10, 0x07 );
993 W2BYTE(REG_ADC_DTOP_01_L, 0x0723);
994 W2BYTE(REG_ADC_DTOP_02_L, 0x0086);
995 break;
996 }
997
998 W2BYTEMSK(REG_ADC_DTOP_06_L, 0x80, 0x80);
999 }
1000
1001 //----------------------------------------------------------------------
1002 // RGB Gain setting
1003 //----------------------------------------------------------------------
1004 void Hal_ADC_dtop_gain_r_setting(MS_U16 u16value)
1005 {
1006 W2BYTEMSK(REG_ADC_DTOP_08_L, u16value, LBMASK);
1007 }
1008 void Hal_ADC_dtop_gain_g_setting(MS_U16 u16value)
1009 {
1010 W2BYTEMSK(REG_ADC_DTOP_09_L, u16value, LBMASK);
1011 }
1012 void Hal_ADC_dtop_gain_b_setting(MS_U16 u16value)
1013 {
1014 W2BYTEMSK(REG_ADC_DTOP_0A_L, u16value, LBMASK);
1015 }
1016 //----------------------------------------------------------------------
1017 // RGB Offset setting
1018 //----------------------------------------------------------------------
1019 // MDrv_WriteByte( H_BK_ADC_DTOP(0x08),DcOffset_R);
1020 // MDrv_WriteByte( H_BK_ADC_DTOP(0x09),DcOffset_G);
1021 // MDrv_WriteByte( H_BK_ADC_DTOP(0x0A),DcOffset_B);
1022
1023 void Hal_ADC_dtop_offset_r_setting(MS_U16 u16value)
1024 {
1025 W2BYTEMSK(REG_ADC_DTOP_08_L, u16value<<8, HBMASK);
1026 }
1027 void Hal_ADC_dtop_offset_g_setting(MS_U16 u16value)
1028 {
1029 W2BYTEMSK(REG_ADC_DTOP_09_L, u16value<<8, HBMASK);
1030 }
1031 void Hal_ADC_dtop_offset_b_setting(MS_U16 u16value)
1032 {
1033 W2BYTEMSK(REG_ADC_DTOP_0A_L, u16value<<8, HBMASK);
1034 }
1035
1036 #endif
1037
1038 /******************************************************************************/
1039 /// Power
1040 /******************************************************************************/
1041 /******************************************************************************/
1042 ///Initialize ADC
1043 /******************************************************************************/
Hal_ADC_init(void * pInstance,MS_U16 u16XTAL_CLK,MS_BOOL IsShareGrd,MS_U16 eScartIDPortSelection)1044 void Hal_ADC_init(void *pInstance, MS_U16 u16XTAL_CLK,MS_BOOL IsShareGrd, MS_U16 eScartIDPortSelection)
1045 {
1046 return;
1047
1048 /*
1049 MS_U8 u8MPLL_LOOP_2nd_DIVIDER;
1050
1051 // ShareGrd setting only for T3.
1052 UNUSED(IsShareGrd);
1053 UNUSED(eScartIDPortSelection);
1054
1055 W2BYTEMSK(REG_ADC_ATOP_04_L, 0x00, HBMASK); //
1056 W2BYTEMSK(REG_ADC_ATOP_05_L, 0x00, LBMASK); //
1057 W2BYTEMSK(REG_ADC_ATOP_0B_L, 0x00, LBMASK);
1058
1059 // PLL
1060 W2BYTEMSK(REG_ADC_ATOP_0C_L, 0x01, LBMASK); // VCO
1061 W2BYTEMSK(REG_ADC_ATOP_12_L, 0x01, LBMASK); // ADC_B VCO S3 may not need to programming this because S3 only has one ADC
1062
1063 W2BYTEMSK(REG_ADC_ATOP_1C_L, 0x10, LBMASK); // SOG trigger lenel
1064
1065 // enhance SOG performance
1066 W2BYTEMSK(REG_ADC_ATOP_21_L, 0x40<<8, HBMASK); // To increse hysteresis
1067 W2BYTEMSK(REG_ADC_ATOP_22_L, 0x30, LBMASK); // To increse SOG clamping ability
1068
1069 W2BYTEMSK(REG_ADC_ATOP_46_L, 0x80, LBMASK); // DAC gain, 0x20
1070 W2BYTEMSK(REG_ADC_ATOP_46_L, 0x10<<8, HBMASK); // LVDS/RSDS/TTL output logic regulator voltage contrl
1071 W2BYTEMSK(REG_ADC_ATOP_2E_L, 0x00, LBMASK); // I-clamp setting
1072
1073 W2BYTEMSK(REG_ADC_ATOP_60_L, 0x00, LBMASK); //DVI //HDMI Port A/B
1074 W2BYTEMSK(REG_ADC_ATOP_60_L, 0x00, HBMASK);
1075 W2BYTEMSK(REG_ADC_ATOP_69_L, 0x00, LBMASK); //DVI2 //HDMI Port C
1076 W2BYTEMSK(REG_ADC_ATOP_69_L, 0x00, HBMASK);
1077
1078 W2BYTEMSK(REG_ADC_ATOP_0B_L, 0x00, LBMASK);
1079
1080 W2BYTEMSK(REG_ADC_DTOP_01_L, 0x81, LBMASK); // PLL loop filer control
1081 W2BYTEMSK(REG_ADC_DTOP_01_L, 0x09<<8, HBMASK); // PLL loop filer control
1082 W2BYTEMSK(REG_ADC_DTOP_02_L, 0x03, LBMASK); // PLL loop filer control
1083 W2BYTEMSK(REG_ADC_DTOP_04_L, 0x05, LBMASK); // setting time
1084 W2BYTEMSK(REG_ADC_DTOP_04_L, 0x95<<8, HBMASK); // PLL control for composite sync input
1085 W2BYTEMSK(REG_ADC_DTOP_0B_L, 0x10, LBMASK); // clamp placement
1086 W2BYTEMSK(REG_ADC_DTOP_0B_L, 0x08<<8, HBMASK); // clamp duration
1087
1088
1089 u8MPLL_LOOP_2nd_DIVIDER = (MS_U8)((215000UL*2 + (u16XTAL_CLK/2)) / u16XTAL_CLK );
1090 W2BYTEMSK(REG_ADC_ATOP_0A_L, u8MPLL_LOOP_2nd_DIVIDER, LBMASK);
1091 */
1092 }
1093
1094 #if 0
1095 void Hal_XC_ADC_poweron_source(ADC_INPUTSOURCE_TYPE enADC_SourceType)
1096 {
1097 ADC_ATOP_POWERON_TBL_t adc_tbl;
1098 MS_ADC_POWER_ON_TYPE enADCPowerType = MS_ADC_POWER_ALL_OFF;
1099 MS_U8 u8Src_En = 0;
1100
1101 switch (enADC_SourceType)
1102 {
1103 case ADC_INPUTSOURCE_ONLY_DVI:
1104
1105 u8Src_En |= En_DVI;
1106 enADCPowerType = MS_DVI_POWER_ON;
1107 break;
1108 case ADC_INPUTSOURCE_ONLY_RGB:
1109 case ADC_INPUTSOURCE_ONLY_YPBPR:
1110 u8Src_En |= (En_ADC_A | En_ADC_AMUX);
1111 enADCPowerType = MS_ADC_A_POWER_ON;
1112 break;
1113 case ADC_INPUTSOURCE_ONLY_SCART:
1114 u8Src_En |= (En_VD|En_FB_RGB|EN_ADC_FB);
1115 enADCPowerType = MS_VDA_FBLANK_POWER_ON;
1116 break;
1117 case ADC_INPUTSOURCE_ONLY_SVIDEO:
1118 u8Src_En |= En_VD|En_VD_YC|En_FB_RGB;
1119 u8Src_En &= ~En_ADC_AMUX;
1120 enADCPowerType = MS_VDA_SV_POWER_ON;
1121 break;
1122 case ADC_INPUTSOURCE_ONLY_CVBS:
1123 case ADC_INPUTSOURCE_ONLY_MVOP:
1124 u8Src_En |= En_VD;
1125 u8Src_En &= ~En_ADC_AMUX;
1126 enADCPowerType = MS_VDA_CVBS_POWER_ON;
1127 break;
1128 default:
1129 u8Src_En |= En_VD;
1130 u8Src_En &= ~En_ADC_AMUX;
1131 enADCPowerType = MS_VDA_CVBS_POWER_ON;
1132 break;
1133 }
1134
1135 // Enable ADC source
1136 W2BYTEMSK(REG_ADC_ATOP_00_L, u8Src_En, 0x00FF);
1137
1138 // Source Power On
1139 adc_tbl.u8ADC_Power_04L = (BIT(7) | BIT(6) | BIT(0));
1140 adc_tbl.u8ADC_Power_04H = (BIT(0));
1141 adc_tbl.u8ADC_Power_05L = (BIT(6) | BIT(5) | BIT(2));
1142 adc_tbl.u8ADC_Power_06L = (BIT(0));
1143 adc_tbl.u8ADC_Power_06H = (BIT(4) | BIT(2));
1144 adc_tbl.u8ADC_Power_60L = (BIT(6) | BIT(4));
1145 adc_tbl.u8ADC_Power_60H = (0x00);
1146 adc_tbl.u8ADC_Power_69L = (BIT(6) | BIT(4));
1147 adc_tbl.u8ADC_Power_69H = (0x00);
1148 adc_tbl.u8ADC_Power_40L = BIT(6);
1149
1150 switch (enADCPowerType)
1151 {
1152 case MS_ADC_A_POWER_ON:
1153 adc_tbl.u8ADC_Power_04L |= (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1));
1154 adc_tbl.u8ADC_Power_06L |= (BIT(3)|BIT(2)|BIT(1));
1155 break;
1156
1157 case MS_VDA_CVBS_POWER_ON:
1158 adc_tbl.u8ADC_Power_04H |= (BIT(7)|BIT(4)|BIT(1));
1159 adc_tbl.u8ADC_Power_05L |= (BIT(4)|BIT(3)|BIT(1));
1160 adc_tbl.u8ADC_Power_06L |= (BIT(7)|BIT(6));
1161 break;
1162
1163 case MS_VDA_SV_POWER_ON:
1164 adc_tbl.u8ADC_Power_04L |= (BIT(5));
1165 adc_tbl.u8ADC_Power_04H |= (BIT(7)|BIT(6)|BIT(4)|BIT(1));
1166 adc_tbl.u8ADC_Power_05L |= (BIT(4)|BIT(3)|BIT(1)|BIT(0));
1167 adc_tbl.u8ADC_Power_06L |= (BIT(7)|BIT(6));
1168 break;
1169
1170 case MS_VDA_FBLANK_POWER_ON:
1171 adc_tbl.u8ADC_Power_04L |= (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1));
1172 adc_tbl.u8ADC_Power_04H |= (BIT(7)|BIT(4)|BIT(1));
1173 adc_tbl.u8ADC_Power_05L |= (BIT(4)|BIT(3)|BIT(1));
1174 adc_tbl.u8ADC_Power_06L |= (BIT(7)|BIT(6)|BIT(3)|BIT(2)|BIT(1));
1175 adc_tbl.u8ADC_Power_06H |= (BIT(6));
1176 adc_tbl.u8ADC_Power_40L = 0;
1177 break;
1178
1179 case MS_DVI_POWER_ON:
1180 adc_tbl.u8ADC_Power_06H |= (BIT(7)|BIT(5)|BIT(3)|BIT(1)|BIT(0));
1181 adc_tbl.u8ADC_Power_60L |= (BIT(7)|BIT(5)|BIT(3)|BIT(2)|BIT(1)|BIT(0));
1182 adc_tbl.u8ADC_Power_60H |= (BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0));
1183 adc_tbl.u8ADC_Power_69L |= (BIT(7)|BIT(5)|BIT(3)|BIT(2)|BIT(1)|BIT(0));
1184 adc_tbl.u8ADC_Power_69H |= (BIT(6)|BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0));
1185 break;
1186 /*
1187 case MS_ADC_VD_BLEND_POWER_ON:
1188 adc_tbl.u8ADC_Power_04L |= (BIT(5)|BIT(4)|BIT(3)|BIT(2)|BIT(1));
1189 adc_tbl.u8ADC_Power_04H |= (BIT(7)|BIT(4)|BIT(1));
1190 adc_tbl.u8ADC_Power_05L |= (BIT(4)|BIT(3)|BIT(1));
1191 adc_tbl.u8ADC_Power_06L |= (BIT(7)|BIT(6)|BIT(3)|BIT(2)|BIT(1));
1192 adc_tbl.u8ADC_Power_06H |= (BIT(6));
1193 adc_tbl.u8ADC_Power_40L = 0;
1194 break;
1195 */
1196 default:
1197 break;
1198 }
1199
1200 // Always turn DVI/HDCP clk on for all source.
1201 // Blue-ray BD1400 will stop playing if power off DVI/HDCP clk and HDMI cable plug-in.
1202 // This will cause component video still.
1203 adc_tbl.u8ADC_Power_06H |= (BIT(1));
1204 adc_tbl.u8ADC_Power_60L |= (BIT(7)|BIT(5));
1205 //////////////////////////////////////////////////////
1206
1207 adc_tbl.u8ADC_Power_04L &= ~(BIT(5) | BIT(4) | BIT(3));
1208 adc_tbl.u8ADC_Power_04L |= ~(R2BYTEMSK(REG_ADC_ATOP_04_L, LBMASK));
1209 adc_tbl.u8ADC_Power_04H &= ~BIT(4);
1210 adc_tbl.u8ADC_Power_04H |= ~(R2BYTEMSK(REG_ADC_ATOP_04_L, HBMASK));
1211 adc_tbl.u8ADC_Power_05L &= ~(BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0));
1212 adc_tbl.u8ADC_Power_05L |= ~(R2BYTEMSK(REG_ADC_ATOP_05_L, LBMASK));
1213 //adc_tbl.u8ADC_Power_40L = (R2BYTEMSK(REG_ADC_ATOP_40_L, LBMASK) & 0x40;
1214
1215 //W2BYTEMSK(REG_ADC_ATOP_04_L, (0xFF & ~(adc_tbl.u8ADC_Power_04L)), LBMASK);
1216 //W2BYTEMSK(REG_ADC_ATOP_04_L, (0xFF & ~(adc_tbl.u8ADC_Power_04H))<<8, HBMASK);
1217 //W2BYTEMSK(REG_ADC_ATOP_05_L, (0xFF & ~(adc_tbl.u8ADC_Power_05L)), LBMASK);
1218 W2BYTEMSK(REG_ADC_ATOP_06_L, (0xFF & ~(adc_tbl.u8ADC_Power_06L)), LBMASK);
1219 W2BYTEMSK(REG_ADC_ATOP_06_L, (0xFF & ~(adc_tbl.u8ADC_Power_06H))<<8, HBMASK);
1220 //W2BYTEMSK(REG_ADC_ATOP_60_L, (0xFF & ~(adc_tbl.u8ADC_Power_60L)), LBMASK);
1221 //W2BYTEMSK(REG_ADC_ATOP_60_L, (0xFF & ~(adc_tbl.u8ADC_Power_60H))<<8, HBMASK);
1222 //W2BYTEMSK(REG_ADC_ATOP_69_L, (0xFF & ~(adc_tbl.u8ADC_Power_69L)), LBMASK);
1223 //W2BYTEMSK(REG_ADC_ATOP_69_L, (0xFF & ~(adc_tbl.u8ADC_Power_69H))<<8, HBMASK);
1224 //W2BYTEMSK(REG_ADC_ATOP_40_L, adc_tbl.u8ADC_Power_40L , BIT(6));
1225 }
1226
1227 void Hal_ADC_Set_Source(ADC_INPUTSOURCE_TYPE enADC_SourceType, E_MUX_INPUTPORT* enInputPortType, MS_U8 u8PortCount)
1228 {
1229 switch(enADC_SourceType)
1230 {
1231 case ADC_INPUTSOURCE_ONLY_RGB:
1232
1233 /* Vclamp */
1234 W2BYTEMSK(REG_ADC_ATOP_2C_L, 0x00, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0))); // G clamp to VP3
1235 /* clamp placement */ /* clamp duration */
1236 W2BYTE(REG_ADC_DTOP_0B_L, 0x810);
1237
1238 /* PLL multiplier */
1239 W2BYTEMSK(REG_ADC_ATOP_0C_L, 0x01, (BIT(2) | BIT(1) | BIT(0)));
1240 /* PLL phase setting time */
1241 W2BYTEMSK(REG_ADC_DTOP_04_L, 0x05, (BIT(3) | BIT(2) | BIT(1) | BIT(0)));
1242 /* SOG level */
1243 W2BYTEMSK(REG_ADC_ATOP_1C_L, 0x25, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)));
1244 /* ADC GenCtrl */
1245 W2BYTEMSK(REG_ADC_DTOP_07_L, 0x02, LBMASK);
1246 break;
1247
1248 case ADC_INPUTSOURCE_ONLY_YPBPR:
1249
1250 /* New mid-clamp */
1251 W2BYTEMSK(REG_ADC_ATOP_2C_L, 0x77, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0))); //0x77 2007-12-4
1252 /* clamp placement */ /* clamp duration */
1253 W2BYTE(REG_ADC_DTOP_0B_L, 0x530);
1254
1255 /* PLL multiplier */
1256 W2BYTEMSK(REG_ADC_ATOP_0C_L, 0x00, (BIT(2) | BIT(1) | BIT(0)));
1257 /* PLL phase setting time */
1258 W2BYTEMSK(REG_ADC_DTOP_04_L, 0x08, (BIT(3) | BIT(2) | BIT(1) | BIT(0)));
1259 /* SOG level */
1260 W2BYTEMSK(REG_ADC_ATOP_1C_L, 0x05, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)));
1261 /* ADC GenCtrl */
1262 W2BYTEMSK(REG_ADC_DTOP_07_L, 0x6A, LBMASK);
1263 break;
1264
1265 case ADC_INPUTSOURCE_ONLY_DVI:
1266
1267 W2BYTEMSK(REG_ADC_ATOP_2C_L, 0x00, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0))); // G clamp to VP3
1268 Hal_ADC_reset(REST_ADC|REST_DVI|REST_HDCP);
1269 break;
1270
1271 case ADC_INPUTSOURCE_ONLY_SVIDEO:
1272 case ADC_INPUTSOURCE_ONLY_SCART:
1273 case ADC_INPUTSOURCE_ONLY_CVBS:
1274
1275 /* Vclamp */
1276 W2BYTEMSK(REG_ADC_ATOP_2C_L, 0x00, (BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0))); // G clamp to VP3
1277 /* PLL multiplier */
1278 W2BYTEMSK(REG_ADC_ATOP_0C_L, 0x01, LBMASK);
1279 /* PLL phase setting time */
1280 W2BYTEMSK(REG_ADC_DTOP_04_L, 0x05, LBMASK);
1281 /* SOG level */
1282 W2BYTEMSK(REG_ADC_ATOP_1C_L, 0x05, (BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0)));
1283 break;
1284 default:
1285 break;
1286 }
1287
1288 //U3 first version need ADC to turn off its jitter-finetune function for VD case.
1289 if(enADC_SourceType &
1290 ( ADC_INPUTSOURCE_ONLY_CVBS | ADC_INPUTSOURCE_ONLY_SCART
1291 | ADC_INPUTSOURCE_ONLY_SVIDEO | ADC_INPUTSOURCE_ONLY_ATV ))
1292 {
1293 W2BYTEMSK(REG_ADC_ATOP_13_L, BIT(6), BIT(6));
1294 }
1295 else
1296 {
1297 W2BYTEMSK(REG_ADC_ATOP_13_L, 0, BIT(6));
1298 }
1299
1300 #ifdef MSOS_TYPE_LINUX_KERNEL
1301 mdelay(2);
1302 #else
1303 MsOS_DelayTask(2);
1304 #endif
1305
1306 }
1307
1308 // Only support input port is CVBS or DAC
1309
1310
1311 //MS_BOOL bEnable,MS_BOOL bIsSvideoSource, MS_BOOL bIsDACSource, E_MUX_INPUTPORT* enPorts, MS_U8 u8Port_Count)
1312
1313 void Hal_ADC_set_cvbs_out(E_ADC_CVBSOUT_TYPE e_cvbs_out_type)
1314 {
1315 MS_U16 u16channel = 0xF , u16clamp = 0 , u16test = 0 ;
1316
1317 if ( e_cvbs_out_type != ADC_CVBSOUT_DISABLE_1 || e_cvbs_out_type != ADC_CVBSOUT_DISABLE_2)
1318 {
1319 // Need refine.
1320 // It should not read mux from hardware and set.
1321 if ( e_cvbs_out_type == ADC_CVBSOUT_VIF_VE_1 || e_cvbs_out_type == ADC_CVBSOUT_VIF_VE_2 ||
1322 e_cvbs_out_type == ADC_CVBSOUT_VIF_VIF_1 || e_cvbs_out_type == ADC_CVBSOUT_VIF_VIF_2)
1323 {
1324 u16channel = 0x5C;
1325 }
1326 else if ( e_cvbs_out_type == ADC_CVBSOUT_SV_ON_1 || e_cvbs_out_type == ADC_CVBSOUT_SV_OFF_1 ||
1327 e_cvbs_out_type == ADC_CVBSOUT_SV_ON_2 || e_cvbs_out_type == ADC_CVBSOUT_SV_OFF_2
1328 )
1329 {
1330 u16channel = 0x5C;
1331 }
1332 else if ( e_cvbs_out_type == ADC_CVBSOUT_CVBS_ON_1 || e_cvbs_out_type == ADC_CVBSOUT_CVBS_OFF_1 ||
1333 e_cvbs_out_type == ADC_CVBSOUT_CVBS_ON_2 || e_cvbs_out_type == ADC_CVBSOUT_CVBS_OFF_2
1334 )
1335 {
1336 u16channel = 0x14;
1337 u16clamp = 0x03;
1338 u16test = 0x0A;
1339 }
1340 else
1341 {
1342 // Undefined
1343 }
1344 }
1345 else
1346 {
1347 // Turn off cvbs out.
1348 u16channel = 0x0F;
1349 }
1350
1351 if ( e_cvbs_out_type == ADC_CVBSOUT_VIF_VE_1 || e_cvbs_out_type == ADC_CVBSOUT_VIF_VE_2)
1352 {
1353 MDrv_WriteRegBit(REG_ADC_ATOP_46_L,DISABLE,BIT(6));
1354 }
1355 else
1356 {
1357 MDrv_WriteRegBit(REG_ADC_ATOP_46_L,ENABLE,BIT(6));
1358 }
1359
1360 // For channel 1
1361 if ( e_cvbs_out_type >= ADC_CVBSOUT_DISABLE_1 && e_cvbs_out_type <= ADC_CVBSOUT_VIF_VIF_1 )
1362 {
1363
1364 if (e_cvbs_out_type == ADC_CVBSOUT_VIF_VE_1 || e_cvbs_out_type == ADC_CVBSOUT_VIF_VIF_1 )
1365 {
1366 W2BYTE(REG_ADC_ATOP_39_L, 0x0B0B );
1367 }
1368
1369 W2BYTEMSK(REG_ADC_ATOP_38_L, u16channel & 0xFF, LBMASK);
1370 W2BYTEMSK(REG_ADC_ATOP_3A_L, u16clamp & 0xFF, LBMASK);
1371 W2BYTEMSK(REG_ADC_ATOP_3B_L, u16test<<8, HBMASK);
1372 }
1373 else // For channel 2
1374 {
1375
1376 if (e_cvbs_out_type == ADC_CVBSOUT_VIF_VE_2 || e_cvbs_out_type == ADC_CVBSOUT_VIF_VIF_2 )
1377 {
1378 W2BYTE(REG_ADC_ATOP_3D_L, 0x0B0B );
1379 }
1380 W2BYTEMSK(REG_ADC_ATOP_3C_L, u16channel & 0xFF, LBMASK);
1381 W2BYTEMSK(REG_ADC_ATOP_3E_L, u16clamp & 0xFF, LBMASK);
1382 W2BYTEMSK(REG_ADC_ATOP_3F_L, u16test<<8, HBMASK);
1383 }
1384
1385 }
1386
1387 /*
1388 // Define the ADC filter BW table
1389 // Table rule :
1390 // Bandwidth frequency from small to large
1391 */
1392 MS_U16 tAdcFilterBW[17][2] = // {MHz, Reg.Value},
1393 {
1394 { 7, 0x0F},
1395 { 15, 0x0E},
1396 { 16, 0x0D},
1397 { 17, 0x0C},
1398 { 18, 0x0B},
1399 { 20, 0x0A},
1400 { 22, 0x09},
1401 { 24, 0x08},
1402 { 26, 0x07},
1403 { 28, 0x06},
1404 { 30, 0x05},
1405 { 60, 0x04},
1406 {125, 0x03},
1407 {150, 0x02},
1408 {190, 0x01},
1409 {250, 0x00},
1410 {0xFFFF, 0x00},
1411 };
1412
1413 void Hal_ADC_set_mode(ADC_INPUTSOURCE_TYPE enADCInput, MS_U16 u16PixelClockPerSecond, MS_U16 u16HorizontalTotal, MS_U16 u16SamplingRatio)
1414 {
1415 MS_U8 u8Loop;
1416
1417 u16PixelClockPerSecond = ADC_FILTER_BW_DCLK(((enADCInput & ADC_INPUTSOURCE_ONLY_RGB)!= 0)?TRUE:FALSE, u16PixelClockPerSecond);
1418
1419 //MDrv_ADC_pll_setting
1420 for(u8Loop = 0 ; u8Loop < sizeof(tAdcFilterBW)/(sizeof(MS_U16)*2); u8Loop++)
1421 {
1422 if(tAdcFilterBW[u8Loop][0] > u16PixelClockPerSecond)
1423 {
1424 W2BYTEMSK(REG_ADC_ATOP_1C_L, (((tAdcFilterBW[u8Loop][1])<<4)<<8), 0xF000);
1425 break;
1426 }
1427 }
1428
1429 /* MDrv_ADC_sog_filter_setting */
1430 if (u16PixelClockPerSecond > ADC_SOG_FILTER_THRSHLD)
1431 {
1432 W2BYTEMSK(REG_ADC_ATOP_1C_L, 0 , BIT(11));
1433 }
1434 else
1435 {
1436 W2BYTEMSK(REG_ADC_ATOP_1C_L, BIT(11) , BIT(11));
1437 }
1438
1439 Hal_ADC_dtop_clk_setting (u16HorizontalTotal * u16SamplingRatio);
1440
1441 //Hal_ADC_clamp_duration_setting( u16HorizontalTotal/50 );
1442 W2BYTEMSK(REG_ADC_DTOP_0B_L, (u16HorizontalTotal/50)<<8, HBMASK);
1443
1444 }
1445
1446 void Hal_ADC_get_default_gain_offset(ADC_INPUTSOURCE_TYPE adc_src,XC_AdcGainOffsetSetting* ADCSetting)
1447 {
1448 switch(adc_src)
1449 {
1450 case ADC_INPUTSOURCE_ONLY_RGB: // RGB source
1451 case ADC_INPUTSOURCE_ONLY_YPBPR:
1452 case ADC_INPUTSOURCE_ONLY_SCART:
1453 default:
1454 ADCSetting->u16RedGain = ADCSetting->u16GreenGain = ADCSetting->u16BlueGain = 0x80;
1455 ADCSetting->u16RedOffset = ADCSetting->u16GreenOffset = ADCSetting->u16BlueOffset = 0x80;
1456 break;
1457 }
1458
1459 }
1460
1461
1462 MS_U16 Hal_ADC_get_center_gain(void)
1463 {
1464 return 0x0080;
1465 }
1466
1467 MS_U16 Hal_ADC_get_center_offset(void)
1468 {
1469 return 0x0080;
1470 }
1471
1472 MS_U8 Hal_ADC_get_offset_bit_cnt(void)
1473 {
1474 return 8;
1475 }
1476
1477 MS_U8 Hal_ADC_get_gain_bit_cnt(void)
1478 {
1479 return 8;
1480 }
1481
1482 void Hal_ADC_auto_adc_backup(SCALER_WIN eWindow)
1483 {
1484 MS_U8 u8Bank;
1485
1486 u8Bank = MDrv_ReadByte(BK_SELECT_00);
1487
1488 if(eWindow == SUB_WINDOW)
1489 {
1490 MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F1);
1491 }
1492 else
1493 {
1494 MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F2);
1495 }
1496 _stAutoAdcSetting.u8L_BkAtop_00 = MDrv_ReadByte(REG_ADC_ATOP_00_L );
1497 _stAutoAdcSetting.u8L_BkAtop_01 = MDrv_ReadByte(REG_ADC_ATOP_01_L );
1498 _stAutoAdcSetting.u8L_BkAtop_0C = MDrv_ReadByte(REG_ADC_ATOP_0C_L );
1499 _stAutoAdcSetting.u8L_BkAtop_2C = MDrv_ReadByte(REG_ADC_ATOP_2C_L );
1500 _stAutoAdcSetting.u8L_BkAtop_1F = MDrv_ReadByte(REG_ADC_ATOP_1F_L );
1501 _stAutoAdcSetting.u8H_BkAtop_2D = MDrv_ReadByte(REG_ADC_ATOP_2D_H );
1502 _stAutoAdcSetting.u8L_BkDtop_06 = MDrv_ReadByte(REG_ADC_DTOP_06_L );
1503 _stAutoAdcSetting.u8L_BkAtop_03 = MDrv_ReadByte(REG_ADC_ATOP_03_L );
1504 _stAutoAdcSetting.u16L_BkAtop_05 = MDrv_Read2Byte(REG_ADC_ATOP_05_L );
1505 _stAutoAdcSetting.u16L_BkAtop_5E = MDrv_Read2Byte(REG_ADC_ATOP_5E_L );
1506 _stAutoAdcSetting.u8H_BkChipTop_1F = MDrv_ReadByte(H_BK_CHIPTOP(0x1f));
1507 _stAutoAdcSetting.u8L_BkChipTop_55 = MDrv_ReadByte(L_BK_CHIPTOP(0x55));
1508 _stAutoAdcSetting.u8L_BkIpMux_1 = MDrv_ReadByte(L_BK_IPMUX(0x01) );
1509 if(eWindow == SUB_WINDOW)
1510 {
1511 _stAutoAdcSetting.u8L_SC_BK1_21 = MDrv_ReadByte(L_BK_IP1F1(0x21) );
1512 }
1513 else
1514 {
1515 _stAutoAdcSetting.u8L_SC_BK1_21 = MDrv_ReadByte(L_BK_IP1F2(0x21) );
1516 }
1517
1518 _stAutoAdcSetting.u16BkAtop_1C = MDrv_Read2Byte(REG_ADC_ATOP_1C_L );
1519 _stAutoAdcSetting.u16BkAtop_05 = MDrv_Read2Byte(REG_ADC_ATOP_05_L);
1520 _stAutoAdcSetting.u16BkAtop_06 = MDrv_Read2Byte(REG_ADC_ATOP_06_L );
1521 _stAutoAdcSetting.u16BkDtop_01 = MDrv_Read2Byte(REG_ADC_DTOP_01_L );
1522 _stAutoAdcSetting.u16BkDtop_02 = MDrv_Read2Byte(REG_ADC_DTOP_02_L );
1523
1524 if(eWindow == SUB_WINDOW)
1525 {
1526 _stAutoAdcSetting.u16SC_BK1_02 = SC_R2BYTE(REG_SC_BK03_02_L);
1527 _stAutoAdcSetting.u16SC_BK1_03 = SC_R2BYTE(REG_SC_BK03_03_L);
1528 _stAutoAdcSetting.u16SC_BK1_04 = SC_R2BYTE(REG_SC_BK03_04_L);
1529 _stAutoAdcSetting.u16SC_BK1_05 = SC_R2BYTE(REG_SC_BK03_05_L);
1530 _stAutoAdcSetting.u16SC_BK1_06 = SC_R2BYTE(REG_SC_BK03_06_L);
1531 _stAutoAdcSetting.u16SC_BK1_07 = SC_R2BYTE(REG_SC_BK03_07_L);
1532 _stAutoAdcSetting.u16SC_BK1_0E = SC_R2BYTE(REG_SC_BK03_0E_L);
1533
1534 _stAutoAdcSetting.u16SC_BK12_01 = SC_R2BYTE(REG_SC_BK12_41_L);
1535 _stAutoAdcSetting.u16SC_BK12_03 = SC_R2BYTE(REG_SC_BK12_43_L);
1536 _stAutoAdcSetting.u16SC_BK12_04 = SC_R2BYTE(REG_SC_BK12_44_L);
1537 _stAutoAdcSetting.u16SC_BK12_0E = SC_R2BYTE(REG_SC_BK12_4E_L);
1538 _stAutoAdcSetting.u16SC_BK12_0F = SC_R2BYTE(REG_SC_BK12_4F_L);
1539 _stAutoAdcSetting.u16SC_BK12_16 = SC_R2BYTE(REG_SC_BK12_56_L);
1540 _stAutoAdcSetting.u16SC_BK12_17 = SC_R2BYTE(REG_SC_BK12_57_L);
1541
1542 //scaling
1543 _stAutoAdcSetting.u16SC_BK02_04 = SC_R2BYTE(REG_SC_BK04_04_L);
1544 _stAutoAdcSetting.u16SC_BK02_05 = SC_R2BYTE(REG_SC_BK04_05_L);
1545 _stAutoAdcSetting.u16SC_BK02_08 = SC_R2BYTE(REG_SC_BK04_08_L);
1546 _stAutoAdcSetting.u16SC_BK02_09 = SC_R2BYTE(REG_SC_BK04_09_L);
1547 _stAutoAdcSetting.u16SC_BK23_07 = SC_R2BYTE(REG_SC_BK23_27_L);
1548 _stAutoAdcSetting.u16SC_BK23_08 = SC_R2BYTE(REG_SC_BK23_28_L);
1549 _stAutoAdcSetting.u16SC_BK23_09 = SC_R2BYTE(REG_SC_BK23_29_L);
1550 _stAutoAdcSetting.u16SC_BK23_0A = SC_R2BYTE(REG_SC_BK23_2A_L);
1551
1552 //DNR base
1553 _stAutoAdcSetting.u32SC_BK12_08 = SC_R4BYTE(REG_SC_BK12_48_L);
1554 _stAutoAdcSetting.u32SC_BK12_0A = SC_R4BYTE(REG_SC_BK12_4A_L);
1555 _stAutoAdcSetting.u32SC_BK12_0C = SC_R4BYTE(REG_SC_BK12_4C_L);
1556 //OPM Base
1557 _stAutoAdcSetting.u32SC_BK12_10 = SC_R4BYTE(REG_SC_BK12_50_L);
1558 _stAutoAdcSetting.u32SC_BK12_12 = SC_R4BYTE(REG_SC_BK12_52_L);
1559 _stAutoAdcSetting.u32SC_BK12_14 = SC_R4BYTE(REG_SC_BK12_54_L);
1560
1561 _stAutoAdcSetting.u16SC_BK06_01 = SC_R2BYTE(REG_SC_BK06_01_L);
1562 _stAutoAdcSetting.u16SC_BK06_21 = SC_R2BYTE(REG_SC_BK06_21_L);
1563 _stAutoAdcSetting.u16SC_BK12_07 = SC_R2BYTE(REG_SC_BK12_07_L);
1564 _stAutoAdcSetting.u16SC_BK12_44 = SC_R2BYTE(REG_SC_BK12_44_L);
1565 _stAutoAdcSetting.u16SC_BK12_47 = SC_R2BYTE(REG_SC_BK12_47_L);
1566 _stAutoAdcSetting.u16SC_BK12_1A = SC_R2BYTE(REG_SC_BK12_5A_L);
1567 _stAutoAdcSetting.u16SC_BK12_1B = SC_R2BYTE(REG_SC_BK12_5B_L);
1568 }
1569 else
1570 {
1571 _stAutoAdcSetting.u16SC_BK1_02 = SC_R2BYTE(REG_SC_BK01_02_L);
1572 _stAutoAdcSetting.u16SC_BK1_03 = SC_R2BYTE(REG_SC_BK01_03_L);
1573 _stAutoAdcSetting.u16SC_BK1_04 = SC_R2BYTE(REG_SC_BK01_04_L);
1574 _stAutoAdcSetting.u16SC_BK1_05 = SC_R2BYTE(REG_SC_BK01_05_L);
1575 _stAutoAdcSetting.u16SC_BK1_06 = SC_R2BYTE(REG_SC_BK01_06_L);
1576 _stAutoAdcSetting.u16SC_BK1_07 = SC_R2BYTE(REG_SC_BK01_07_L);
1577 _stAutoAdcSetting.u16SC_BK1_0E = SC_R2BYTE(REG_SC_BK01_0E_L);
1578
1579 _stAutoAdcSetting.u16SC_BK12_01 = SC_R2BYTE(REG_SC_BK12_01_L);
1580 _stAutoAdcSetting.u16SC_BK12_03 = SC_R2BYTE(REG_SC_BK12_03_L);
1581 _stAutoAdcSetting.u16SC_BK12_04 = SC_R2BYTE(REG_SC_BK12_04_L);
1582 _stAutoAdcSetting.u16SC_BK12_0E = SC_R2BYTE(REG_SC_BK12_0E_L);
1583 _stAutoAdcSetting.u16SC_BK12_0F = SC_R2BYTE(REG_SC_BK12_0F_L);
1584 _stAutoAdcSetting.u16SC_BK12_16 = SC_R2BYTE(REG_SC_BK12_16_L);
1585 _stAutoAdcSetting.u16SC_BK12_17 = SC_R2BYTE(REG_SC_BK12_17_L);
1586
1587 //scaling
1588 _stAutoAdcSetting.u16SC_BK02_04 = SC_R2BYTE(REG_SC_BK02_04_L);
1589 _stAutoAdcSetting.u16SC_BK02_05 = SC_R2BYTE(REG_SC_BK02_05_L);
1590 _stAutoAdcSetting.u16SC_BK02_08 = SC_R2BYTE(REG_SC_BK02_08_L);
1591 _stAutoAdcSetting.u16SC_BK02_09 = SC_R2BYTE(REG_SC_BK02_09_L);
1592 _stAutoAdcSetting.u16SC_BK23_07 = SC_R2BYTE(REG_SC_BK23_07_L);
1593 _stAutoAdcSetting.u16SC_BK23_08 = SC_R2BYTE(REG_SC_BK23_08_L);
1594 _stAutoAdcSetting.u16SC_BK23_09 = SC_R2BYTE(REG_SC_BK23_09_L);
1595 _stAutoAdcSetting.u16SC_BK23_0A = SC_R2BYTE(REG_SC_BK23_0A_L);
1596
1597 //DNR base
1598 _stAutoAdcSetting.u32SC_BK12_08 = SC_R4BYTE(REG_SC_BK12_08_L);
1599 _stAutoAdcSetting.u32SC_BK12_0A = SC_R4BYTE(REG_SC_BK12_0A_L);
1600 _stAutoAdcSetting.u32SC_BK12_0C = SC_R4BYTE(REG_SC_BK12_0C_L);
1601 //OPM Base
1602 _stAutoAdcSetting.u32SC_BK12_10 = SC_R4BYTE(REG_SC_BK12_10_L);
1603 _stAutoAdcSetting.u32SC_BK12_12 = SC_R4BYTE(REG_SC_BK12_12_L);
1604 _stAutoAdcSetting.u32SC_BK12_14 = SC_R4BYTE(REG_SC_BK12_14_L);
1605
1606 _stAutoAdcSetting.u16SC_BK06_01 = SC_R2BYTE(REG_SC_BK06_01_L);
1607 _stAutoAdcSetting.u16SC_BK06_21 = SC_R2BYTE(REG_SC_BK06_21_L);
1608 _stAutoAdcSetting.u16SC_BK12_07 = SC_R2BYTE(REG_SC_BK12_07_L);
1609 _stAutoAdcSetting.u16SC_BK12_44 = SC_R2BYTE(REG_SC_BK12_44_L);
1610 _stAutoAdcSetting.u16SC_BK12_47 = SC_R2BYTE(REG_SC_BK12_47_L);
1611 _stAutoAdcSetting.u16SC_BK12_1A = SC_R2BYTE(REG_SC_BK12_1A_L);
1612 _stAutoAdcSetting.u16SC_BK12_1B = SC_R2BYTE(REG_SC_BK12_1B_L);
1613 }
1614
1615 MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);
1616 _stAutoAdcSetting.u8L_SC_BK10_19 = MDrv_ReadByte(L_BK_VOP(0x19) );
1617
1618 MDrv_WriteByteMask(REG_ADC_ATOP_5C_L, 0x30,0x30); //ldo
1619
1620 MDrv_WriteByte(BK_SELECT_00, u8Bank);
1621 }
1622
1623 void Hal_ADC_auto_adc_restore(void)
1624 {
1625 MS_U8 u8Bank;
1626
1627 u8Bank = MDrv_ReadByte(BK_SELECT_00);
1628
1629 if(eWindow == SUB_WINDOW)
1630 {
1631 MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F1);
1632 }
1633 else
1634 {
1635 MDrv_WriteByte(BK_SELECT_00, REG_BANK_IP1F2);
1636 }
1637 MDrv_WriteByte(REG_ADC_ATOP_00_L, _stAutoAdcSetting.u8L_BkAtop_00);
1638 MDrv_WriteByte(REG_ADC_ATOP_01_L, _stAutoAdcSetting.u8L_BkAtop_01);
1639 MDrv_WriteByte(REG_ADC_ATOP_0C_L, _stAutoAdcSetting.u8L_BkAtop_0C);
1640 MDrv_WriteByte(REG_ADC_ATOP_2C_L, _stAutoAdcSetting.u8L_BkAtop_2C);
1641 MDrv_WriteByte(REG_ADC_ATOP_1F_L, _stAutoAdcSetting.u8L_BkAtop_1F);
1642 MDrv_WriteByte(REG_ADC_ATOP_2D_H, _stAutoAdcSetting.u8H_BkAtop_2D);
1643 MDrv_WriteByte(REG_ADC_ATOP_03_L, _stAutoAdcSetting.u8L_BkAtop_03);
1644 MDrv_Write2Byte(REG_ADC_ATOP_05_L, _stAutoAdcSetting.u16L_BkAtop_05);
1645 MDrv_Write2Byte(REG_ADC_ATOP_5E_L, _stAutoAdcSetting.u16L_BkAtop_5E);
1646 MDrv_WriteByte(REG_ADC_DTOP_06_L, _stAutoAdcSetting.u8L_BkDtop_06);
1647 MDrv_WriteByte(H_BK_CHIPTOP(0x1f), _stAutoAdcSetting.u8H_BkChipTop_1F);
1648 MDrv_WriteByte(L_BK_CHIPTOP(0x55), _stAutoAdcSetting.u8L_BkChipTop_55);
1649 MDrv_WriteByte(L_BK_IPMUX(0x01), _stAutoAdcSetting.u8L_BkIpMux_1);
1650
1651 if(eWindow == SUB_WINDOW)
1652 {
1653 MDrv_WriteByte(L_BK_IP1F1(0x21), _stAutoAdcSetting.u8L_SC_BK1_21);
1654 }
1655 else
1656 {
1657 MDrv_WriteByte(L_BK_IP1F2(0x21), _stAutoAdcSetting.u8L_SC_BK1_21);
1658 }
1659
1660 MDrv_Write2Byte(REG_ADC_ATOP_1C_L, _stAutoAdcSetting.u16BkAtop_1C);
1661 MDrv_Write2Byte(REG_ADC_ATOP_05_L, _stAutoAdcSetting.u16BkAtop_05);
1662 MDrv_Write2Byte(REG_ADC_ATOP_06_L, _stAutoAdcSetting.u16BkAtop_06);
1663 MDrv_Write2Byte(REG_ADC_DTOP_01_L, _stAutoAdcSetting.u16BkDtop_01);
1664 MDrv_Write2Byte(REG_ADC_DTOP_02_L, _stAutoAdcSetting.u16BkDtop_02);
1665
1666 if(eWindow == SUB_WINDOW)
1667 {
1668 MDrv_Write2Byte(L_BK_IP1F1(0x02), _stAutoAdcSetting.u16SC_BK1_02);
1669 MDrv_Write2Byte(L_BK_IP1F1(0x03), _stAutoAdcSetting.u16SC_BK1_03);
1670 MDrv_Write2Byte(L_BK_IP1F1(0x04), _stAutoAdcSetting.u16SC_BK1_04);
1671 MDrv_Write2Byte(L_BK_IP1F1(0x05), _stAutoAdcSetting.u16SC_BK1_05);
1672 MDrv_Write2Byte(L_BK_IP1F1(0x06), _stAutoAdcSetting.u16SC_BK1_06);
1673 MDrv_Write2Byte(L_BK_IP1Fr(0x07), _stAutoAdcSetting.u16SC_BK1_07);
1674 MDrv_Write2Byte(L_BK_IP1F1(0x0E), _stAutoAdcSetting.u16SC_BK1_0E);
1675
1676 MDrv_WriteByte(BK_SELECT_00, REG_BANK_SCMI);
1677 MDrv_Write2Byte(L_BK_SCMI(0x41), _stAutoAdcSetting.u16SC_BK12_01);
1678 MDrv_Write2Byte(L_BK_SCMI(0x43), _stAutoAdcSetting.u16SC_BK12_03);
1679 MDrv_Write2Byte(L_BK_SCMI(0x44), _stAutoAdcSetting.u16SC_BK12_04);
1680 MDrv_Write2Byte(L_BK_SCMI(0x4E), _stAutoAdcSetting.u16SC_BK12_0E);
1681 MDrv_Write2Byte(L_BK_SCMI(0x4F), _stAutoAdcSetting.u16SC_BK12_0F);
1682 MDrv_Write2Byte(L_BK_SCMI(0x56), _stAutoAdcSetting.u16SC_BK12_16);
1683 MDrv_Write2Byte(L_BK_SCMI(0x57), _stAutoAdcSetting.u16SC_BK12_17);
1684
1685 //scaling
1686 SC_W2BYTE(REG_SC_BK04_04_L, _stAutoAdcSetting.u16SC_BK02_04);
1687 SC_W2BYTE(REG_SC_BK04_05_L, _stAutoAdcSetting.u16SC_BK02_05);
1688 SC_W2BYTE(REG_SC_BK04_08_L, _stAutoAdcSetting.u16SC_BK02_08);
1689 SC_W2BYTE(REG_SC_BK04_09_L, _stAutoAdcSetting.u16SC_BK02_09);
1690 SC_W2BYTE(REG_SC_BK23_27_L, _stAutoAdcSetting.u16SC_BK23_07);
1691 SC_W2BYTE(REG_SC_BK23_28_L, _stAutoAdcSetting.u16SC_BK23_08);
1692 SC_W2BYTE(REG_SC_BK23_29_L, _stAutoAdcSetting.u16SC_BK23_09);
1693 SC_W2BYTE(REG_SC_BK23_2A_L, _stAutoAdcSetting.u16SC_BK23_0A);
1694
1695 //DNR,OPM Base
1696 SC_W4BYTE(REG_SC_BK12_48_L, _stAutoAdcSetting.u32SC_BK12_08);
1697 SC_W4BYTE(REG_SC_BK12_4A_L, _stAutoAdcSetting.u32SC_BK12_0A);
1698 SC_W4BYTE(REG_SC_BK12_4C_L, _stAutoAdcSetting.u32SC_BK12_0C);
1699 SC_W4BYTE(REG_SC_BK12_50_L, _stAutoAdcSetting.u32SC_BK12_10);
1700 SC_W4BYTE(REG_SC_BK12_52_L, _stAutoAdcSetting.u32SC_BK12_12);
1701 SC_W4BYTE(REG_SC_BK12_54_L, _stAutoAdcSetting.u32SC_BK12_14);
1702 SC_W2BYTE(REG_SC_BK12_5A_L, _stAutoAdcSetting.u16SC_BK12_1A);
1703 SC_W2BYTE(REG_SC_BK12_5B_L, _stAutoAdcSetting.u16SC_BK12_1B);
1704
1705 SC_W2BYTE(REG_SC_BK06_01_L, _stAutoAdcSetting.u16SC_BK06_01);
1706 SC_W2BYTE(REG_SC_BK06_21_L, _stAutoAdcSetting.u16SC_BK06_21);
1707 SC_W2BYTE(REG_SC_BK12_07_L, _stAutoAdcSetting.u16SC_BK12_07);
1708 SC_W2BYTE(REG_SC_BK12_44_L, _stAutoAdcSetting.u16SC_BK12_44);
1709 SC_W2BYTE(REG_SC_BK12_47_L, _stAutoAdcSetting.u16SC_BK12_47);
1710 }
1711 else
1712 {
1713 MDrv_Write2Byte(L_BK_IP1F2(0x02), _stAutoAdcSetting.u16SC_BK1_02);
1714 MDrv_Write2Byte(L_BK_IP1F2(0x03), _stAutoAdcSetting.u16SC_BK1_03);
1715 MDrv_Write2Byte(L_BK_IP1F2(0x04), _stAutoAdcSetting.u16SC_BK1_04);
1716 MDrv_Write2Byte(L_BK_IP1F2(0x05), _stAutoAdcSetting.u16SC_BK1_05);
1717 MDrv_Write2Byte(L_BK_IP1F2(0x06), _stAutoAdcSetting.u16SC_BK1_06);
1718 MDrv_Write2Byte(L_BK_IP1F2(0x07), _stAutoAdcSetting.u16SC_BK1_07);
1719 MDrv_Write2Byte(L_BK_IP1F2(0x0E), _stAutoAdcSetting.u16SC_BK1_0E);
1720
1721 MDrv_WriteByte(BK_SELECT_00, REG_BANK_SCMI);
1722 MDrv_Write2Byte(L_BK_SCMI(0x01), _stAutoAdcSetting.u16SC_BK12_01);
1723 MDrv_Write2Byte(L_BK_SCMI(0x03), _stAutoAdcSetting.u16SC_BK12_03);
1724 MDrv_Write2Byte(L_BK_SCMI(0x04), _stAutoAdcSetting.u16SC_BK12_04);
1725 MDrv_Write2Byte(L_BK_SCMI(0x0E), _stAutoAdcSetting.u16SC_BK12_0E);
1726 MDrv_Write2Byte(L_BK_SCMI(0x0F), _stAutoAdcSetting.u16SC_BK12_0F);
1727 MDrv_Write2Byte(L_BK_SCMI(0x16), _stAutoAdcSetting.u16SC_BK12_16);
1728 MDrv_Write2Byte(L_BK_SCMI(0x17), _stAutoAdcSetting.u16SC_BK12_17);
1729
1730 //scaling
1731 SC_W2BYTE(REG_SC_BK02_04_L, _stAutoAdcSetting.u16SC_BK02_04);
1732 SC_W2BYTE(REG_SC_BK02_05_L, _stAutoAdcSetting.u16SC_BK02_05);
1733 SC_W2BYTE(REG_SC_BK02_08_L, _stAutoAdcSetting.u16SC_BK02_08);
1734 SC_W2BYTE(REG_SC_BK02_09_L, _stAutoAdcSetting.u16SC_BK02_09);
1735 SC_W2BYTE(REG_SC_BK23_07_L, _stAutoAdcSetting.u16SC_BK23_07);
1736 SC_W2BYTE(REG_SC_BK23_08_L, _stAutoAdcSetting.u16SC_BK23_08);
1737 SC_W2BYTE(REG_SC_BK23_09_L, _stAutoAdcSetting.u16SC_BK23_09);
1738 SC_W2BYTE(REG_SC_BK23_0A_L, _stAutoAdcSetting.u16SC_BK23_0A);
1739
1740 //DNR,OPM Base
1741 SC_W4BYTE(REG_SC_BK12_08_L, _stAutoAdcSetting.u32SC_BK12_08);
1742 SC_W4BYTE(REG_SC_BK12_0A_L, _stAutoAdcSetting.u32SC_BK12_0A);
1743 SC_W4BYTE(REG_SC_BK12_0C_L, _stAutoAdcSetting.u32SC_BK12_0C);
1744 SC_W4BYTE(REG_SC_BK12_10_L, _stAutoAdcSetting.u32SC_BK12_10);
1745 SC_W4BYTE(REG_SC_BK12_12_L, _stAutoAdcSetting.u32SC_BK12_12);
1746 SC_W4BYTE(REG_SC_BK12_14_L, _stAutoAdcSetting.u32SC_BK12_14);
1747 SC_W2BYTE(REG_SC_BK12_1A_L, _stAutoAdcSetting.u16SC_BK12_1A);
1748 SC_W2BYTE(REG_SC_BK12_1B_L, _stAutoAdcSetting.u16SC_BK12_1B);
1749
1750 SC_W2BYTE(REG_SC_BK06_01_L, _stAutoAdcSetting.u16SC_BK06_01);
1751 SC_W2BYTE(REG_SC_BK06_21_L, _stAutoAdcSetting.u16SC_BK06_21);
1752 SC_W2BYTE(REG_SC_BK12_07_L, _stAutoAdcSetting.u16SC_BK12_07);
1753 SC_W2BYTE(REG_SC_BK12_44_L, _stAutoAdcSetting.u16SC_BK12_44);
1754 SC_W2BYTE(REG_SC_BK12_47_L, _stAutoAdcSetting.u16SC_BK12_47);
1755 }
1756
1757 MDrv_WriteByteMask(REG_ADC_ATOP_5C_L, 0x00,0x70);
1758
1759 MDrv_WriteByte(BK_SELECT_00, REG_BANK_VOP);
1760 MDrv_WriteByte(L_BK_VOP(0x19),_stAutoAdcSetting.u8L_SC_BK10_19 );
1761
1762 MDrv_WriteByte(BK_SELECT_00, u8Bank);
1763 }
1764
1765 MS_BOOL Hal_ADC_is_scart_rgb(void)
1766 {
1767 MS_BOOL bRGB;
1768 MS_U8 u8Flag;
1769
1770 u8Flag = MDrv_ReadByte(REG_ADC_ATOP_45_H);
1771
1772 if((u8Flag & 0x50) == 0x10)
1773 bRGB = TRUE;
1774 else
1775 bRGB = FALSE;
1776
1777 MDrv_WriteByteMask(REG_ADC_ATOP_45_H, 0x20, 0x20);
1778
1779 return bRGB;
1780 }
1781
1782 MS_U16 Hal_ADC_get_clk (void)
1783 {
1784 //u16Value -= 3; // actual - 3
1785 //ADC PLL divider ratio (htotal-3), (write sequence LSB -> MSB)
1786 return (R2BYTEMSK(REG_ADC_DTOP_00_L, 0xFFFF)+3);//(REG_ADC_DTOP_00_L, u16Value);
1787 }
1788
1789 MS_BOOL Hal_ADC_set_SoG_Calibration(void)
1790 {
1791 // Reset SoG Online/Offline calibration depend on chip
1792 return TRUE;
1793 }
1794
1795 /******************************************************************************/
1796 ///This function return SOG level range
1797 ///@param u32Min \b OUT: min of SOG level
1798 ///@param u32Max \b OUT: max of SOG level
1799 ///@param u32Recommend_value \b OUT: recommend value
1800 /******************************************************************************/
1801 void Hal_ADC_get_SoG_LevelRange(MS_U32 *u32Min, MS_U32 *u32Max, MS_U32 *u32Recommend_value)
1802 {
1803 *u32Min = 0;
1804 *u32Max = 0;
1805 *u32Recommend_value = 0;
1806 }
1807
1808 /******************************************************************************/
1809 ///This function Set SOG Level
1810 ///@param u32Value \b IN: set SOG value
1811 /******************************************************************************/
1812 void Hal_ADC_set_SoG_Level(MS_U32 u32Value)
1813 {
1814 UNUSED(u32Value);
1815 }
1816
1817 /******************************************************************************/
1818 ///select RGB input pipe delay, this reg will decide the H start of SCART RGB
1819 ///@param u32Value \b IN: set PIPE Delay value
1820 /******************************************************************************/
1821 void Hal_ADC_set_RGB_PIPE_Delay(MS_U8 u8Value)
1822 {
1823 W2BYTEMSK(REG_ADC_ATOP_43_L, (u8Value<<8), 0x7F00);
1824 }
1825
1826 /******************************************************************************/
1827 ///This function set Scart RGB Sync on Green clamp delay.
1828 ///@param u16Value \b IN: set clamp delay value
1829 /******************************************************************************/
1830 void Hal_ADC_set_ScartRGB_SOG_ClampDelay(MS_U16 u16Clpdly, MS_U16 u16Caldur)
1831 {
1832 return;
1833 W2BYTEMSK(REG_ADC_DTOP_17_L, u16Clpdly, 0x0FFF);
1834 W2BYTEMSK(REG_ADC_DTOP_18_L, u16Caldur, 0x00FF);
1835 }
1836
1837 /******************************************************************************/
1838 ///This function set YPbPr Loose LPF.
1839 ///@param benable \b IN: enable or disable
1840 /******************************************************************************/
1841 void Hal_ADC_set_YPbPrLooseLPF(MS_BOOL benable)
1842 {
1843 //Obsolate in u4
1844 }
1845
1846 /******************************************************************************/
1847 ///This function set SOG BW
1848 ///@param u16value \b IN: value of SOG BW
1849 /******************************************************************************/
1850 void Hal_ADC_Set_SOGBW(MS_U16 u16value)
1851 {
1852 u16value = u16value;
1853 }
1854
1855 /******************************************************************************/
1856 ///Set negative clamping duration..
1857 ///@param u16Value \b IN: set clamp delay value
1858 /******************************************************************************/
1859 void Hal_ADC_dtop_iClampDuration_setting(MS_U16 u16value)
1860 {
1861 W2BYTEMSK(REG_ADC_DTOP_18_L, u16value, LBMASK);
1862 }
1863
1864 /******************************************************************************/
1865 ///Set postive clamping duration..
1866 ///@param u16Value \b IN: set clamp delay value
1867 /******************************************************************************/
1868 void Hal_ADC_dtop_vClampDuration_setting(MS_U16 u16value)
1869 {
1870 W2BYTEMSK(REG_ADC_DTOP_08_L, u16value, LBMASK);
1871 }
1872 #endif
1873
1874 #undef MHAL_ADC_C
1875
1876