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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 //============================================================================== 95 // [mhal_hdmi.h] 96 // Date: 20081203 97 // Descriptions: Add a new layer for HW setting 98 //============================================================================== 99 #ifndef MHAL_HDMI_H 100 #define MHAL_HDMI_H 101 102 #include "hwreg_ddc.h" 103 #include "hwreg_adc_atop.h" 104 #include "hwreg_adc_dtop.h" 105 #include "hwreg_hdcp.h" 106 #include "hwreg_hdmi.h" 107 #include "hwreg_sc.h" 108 109 #include "drvXC_HDMI_if.h" 110 #include "apiXC.h" 111 112 //============================================================================== 113 //============================================================================== 114 /* DDC SRAM SEL (After T3) */ 115 #define DDC_RAM_SRAM_DVI 0U 116 #define DDC_RAM_SRAM_ADC 1U 117 #define DDC_RAM_SRAM_DVI0 0U 118 #define DDC_RAM_SRAM_DVI1 1U 119 #define DDC_RAM_SRAM_DVI2 2U 120 #define DDC_RAM_SRAM_DVI3 3U 121 122 #define DDC_OFFSET_SRAM_DVI0 0U 123 #define DDC_OFFSET_SRAM_DVI1 2U 124 #define DDC_OFFSET_SRAM_DVI2 4U 125 #define DDC_OFFSET_SRAM_DVI3 6U 126 #define DDC_OFFSET_SRAM_ADC 8U 127 128 #define INPUT_PORT_DVI_END INPUT_PORT_DVI0 129 130 #define ABS_MINUS(a, b) ((a > b)? (a -b): (b -a)) 131 132 #define HDMI_GET_PORT_SELECT(a) ((MS_U8)(a - INPUT_PORT_DVI0)) 133 134 //============================================================================== 135 //============================================================================== 136 137 #define IRQ_DVI_CK_CHG BIT(0) //#[0] 138 #define IRQ_HDMI_MODE_CHG BIT(1) //#[1] 139 #define IRQ_SCART_ID0_CHG BIT(2) //#[2] 140 #define IRQ_SCART_ID1_CHG BIT(3) //#[3] 141 #define IRQ_SAR_DET_UPD BIT(4) //#[4] 142 #define IRQ_RESERVE (BIT(7)|BIT(6)|BIT(5)) //#[5:7] 143 #define IRQ_ALL_BIT (BIT(4)|BIT(3)|BIT(2)|BIT(1)|BIT(0)) 144 145 #define TMDS_DIGITAL_LOCK_CNT_POWER 5U 146 #define TMDS_DIGITAL_LOSE_RANGE 3U 147 148 #define TMDS_POWER_SWITCH_IRQ_ENABLE 0U 149 150 #define TMDS_CLOCK_CMP_VALUE0 0x06U 151 #define TMDS_CLOCK_CMP_VALUE1 0x65U 152 153 #define TMDS_COARSE_TUNE_14_MIN 0x11U 154 #define TMDS_COARSE_TUNE_20_MIN 0x00U 155 #define TMDS_COARSE_TUNE_20_MAX 0x1FU 156 #define TMDS_COARSE_TUNE_20_START 0x12U 157 #define TMDS_COARSE_TUNE_14_DETECT_TIME 0xFFU 158 #define TMDS_COARSE_TUNE_20_DETECT_TIME 0x50U 159 #define TMDS_COARSE_TUNE_14_AABA_NUMBER 0x50U 160 #define TMDS_COARSE_TUNE_20_AABA_NUMBER 0x19U 161 #define TMDS_FINE_TUNE_AABA_14_NUMBER 0x3FFFU 162 #define TMDS_FINE_TUNE_AABA_20_NUMBER 0x1FFFU 163 #define TMDS_FINE_TUNE_UNDER_14_THRESHOLD 0x1U 164 #define TMDS_FINE_TUNE_UNDER_20_THRESHOLD 0x1FFU 165 #define TMDS_CONTINUE_START 0xFU 166 #define TMDS_CONTINUOUS_NUMBER 0x350U 167 168 #define HDMI_UNDER_150M_EQ_SETTING_VALUE 3U 169 #define HDMI_OVER_150M_EQ_SETTING_VALUE 7U 170 #define HDMI_EQ_14_SETTING_VALUE 14U 171 #define HDMI_EQ_20_SETTING_VALUE 0x19U 172 173 #define HDMI_MHL_EQ_SETTING_VALUE 4U 174 175 #define TMDS_SCDC_ACCESS_ADDERSS_A8 BIT(6) 176 177 #define HDMI_AUTO_EQ_CHECK_INTERVAL 30U 178 179 #define HDMI_EQ_CAL_TRIGGER_COUNT 1000U 180 #define HDMI_EQ_CAL_MEASURE_COUNT 250U 181 182 #define TMDS_5V_DETECT_GPIO_ENABLE 1 183 184 #define TMDS_DE_FILTER_HDMI14_VALUE 0xCU 185 #define TMDS_DE_FILTER_HDMI20_VALUE 0x5U 186 187 #define TMDS_HDCP_WINDOW_END_VALUE 0x3U 188 #define TMDS_HDCP2_SOURCE_READ_OFFSET 130U 189 190 #define TMDS_14_CHECK_ERROR_INTERVAL 0x1U 191 #define TMDS_14_CHECK_ERROR_TIMES 0x80U 192 #define TMDS_20_CHECK_ERROR_INTERVAL 0x1U 193 #define TMDS_20_CHECK_ERROR_TIMES 0x80U 194 #define TMDS_AUTO_EQ_PROCESS_INTERVAL 500U 195 196 #define HDMI_DECORD_ERROR_THRESHOLD 0x8006U 197 #define HDMI_AUTO_EQ_ENABLE_THRESHOLD 140U 198 #define HDMI_CLOCK_UNSTABLE_OFFSET 2U 199 200 #define HDMI_CHECK_SCRAMBLE_INTERVAL 20U 201 202 typedef struct 203 { 204 MS_BOOL bNoInputFlag; 205 MS_BOOL bHDMI20Flag; 206 MS_BOOL bYUV420Flag; 207 MS_BOOL bHDMIModeFlag; 208 MS_BOOL bAutoEQEnable; 209 MS_BOOL bAutoEQRetrigger; 210 MS_BOOL bTimingStableFlag; 211 MS_BOOL bPowerOnLane; 212 MS_BOOL bIsRepeater; 213 MS_BOOL bPowerSavingFlag; 214 MS_U8 ucAutoEQState; 215 MS_U8 ucSourceVersion; 216 MS_U8 ucCheckErrorInterval; 217 MS_U8 ucAutoEQ14Mode; 218 MS_U8 ucCheckScrambleCounter; 219 MS_U8 ucHDCPState; 220 MS_U8 ucHDCPInt; 221 MS_U16 usClockCount; 222 MS_U16 usCheckErrorTimes; 223 MS_U16 usAutoEQProcCounter; 224 } stHDMI_POLLING_INFO; 225 226 enum HDMI_AUTO_EQ_STATE_TYPE 227 { 228 HDMI_AUTO_EQ_START = 0, 229 HDMI_AUTO_EQ_WAIT_DONE, 230 HDMI_AUTO_EQ_FINISH_PROCESS, 231 HDMI_AUTO_EQ_CHECK_STABLE, 232 HDMI_AUTO_EQ_CHECK_DONE, 233 HDMI_AUTO_EQ_14_CLEAR_STATUS, 234 HDMI_AUTO_EQ_14_CHECK_STATUS, 235 HDMI_AUTO_EQ_14_CHANGE_SETTING, 236 HDMI_AUTO_EQ_20_CLEAR_STATUS, 237 HDMI_AUTO_EQ_20_CHECK_STATUS, 238 HDMI_AUTO_EQ_STABLE_DONE, 239 }; 240 241 enum HDMI_SOURCE_VERSION_TYPE 242 { 243 HDMI_SOURCE_VERSION_NOT_SURE = 0, 244 HDMI_SOURCE_VERSION_HDMI14, 245 HDMI_SOURCE_VERSION_HDMI20, 246 }; 247 248 enum HDMI_HDCP_STATE 249 { 250 HDMI_HDCP_NO_ENCRYPTION = 0, 251 HDMI_HDCP_1_4, 252 HDMI_HDCP_2_2, 253 }; 254 255 enum HDMI_HDCP_ENCRYPTION_STATE 256 { 257 HDMI_HDCP_NOT_ENCRYPTION = 0, 258 HDMI_HDCP_1_4_ENCRYPTION, 259 HDMI_HDCP_2_2_ENCRYPTION, 260 }; 261 262 enum HDMI_5V_DETECT_GPIO_TYPE 263 { 264 HDMI_5V_DETECT_GPIO_NONE = 0, 265 HDMI_5V_DETECT_GPIO_INDEX00, 266 HDMI_5V_DETECT_GPIO_INDEX01, 267 HDMI_5V_DETECT_GPIO_INDEX02, 268 HDMI_5V_DETECT_GPIO_INDEX03, 269 HDMI_5V_DETECT_GPIO_INDEX04, 270 HDMI_5V_DETECT_GPIO_INDEX05, 271 HDMI_5V_DETECT_GPIO_INDEX06, 272 HDMI_5V_DETECT_GPIO_INDEX07, 273 HDMI_5V_DETECT_GPIO_INDEX08, 274 HDMI_5V_DETECT_GPIO_INDEX09, 275 HDMI_5V_DETECT_GPIO_INDEX10, 276 HDMI_5V_DETECT_GPIO_INDEX11, 277 HDMI_5V_DETECT_GPIO_INDEX12, 278 HDMI_5V_DETECT_GPIO_INDEX13, 279 HDMI_5V_DETECT_GPIO_INDEX14, 280 HDMI_5V_DETECT_GPIO_INDEX15, 281 HDMI_5V_DETECT_GPIO_INDEX16, 282 HDMI_5V_DETECT_GPIO_INDEX17, 283 HDMI_5V_DETECT_GPIO_INDEX18, 284 HDMI_5V_DETECT_GPIO_INDEX19, 285 HDMI_5V_DETECT_GPIO_INDEX20, 286 HDMI_5V_DETECT_GPIO_INDEX21, 287 HDMI_5V_DETECT_GPIO_INDEX22, 288 HDMI_5V_DETECT_GPIO_INDEX23, 289 HDMI_5V_DETECT_GPIO_INDEX24, 290 HDMI_5V_DETECT_GPIO_INDEX25, 291 }; 292 293 enum HDMI_AUTO_EQ_14_MODE_TYPE 294 { 295 HDMI_AUTO_EQ_14_MODE0 = 0, 296 HDMI_AUTO_EQ_14_MODE1, 297 HDMI_AUTO_EQ_14_MODE_MASK, 298 }; 299 300 enum HDMI_STATUS_FLAG_TYPE 301 { 302 HDMI_STATUS_MPEG_PACKET_RECEIVE_FLAG = BIT(0), 303 HDMI_STATUS_AUDIO_PACKET_RECEIVE_FLAG = BIT(1), 304 HDMI_STATUS_SPD_PACKET_RECEIVE_FLAG = BIT(2), 305 HDMI_STATUS_AVI_PACKET_RECEIVE_FLAG = BIT(3), 306 HDMI_STATUS_GCP_PACKET_RECEIVE_FLAG = BIT(4), 307 HDMI_STATUS_AUDIO_SAMPLE_PACKET_RECEIVE_FLAG = BIT(5), 308 HDMI_STATUS_ACR_PACKET_RECEIVE_FLAG = BIT(6), 309 HDMI_STATUS_VS_PACKET_RECEIVE_FLAG = BIT(7), 310 HDMI_STATUS_NULL_PACKET_RECEIVE_FLAG = BIT(8), 311 HDMI_STATUS_ISRC2_PACKET_RECEIVE_FLAG = BIT(9), 312 HDMI_STATUS_ISRC1_PACKET_RECEIVE_FLAG = BIT(10), 313 HDMI_STATUS_ACP_PACKET_RECEIVE_FLAG = BIT(11), 314 HDMI_STATUS_DSD_PACKET_RECEIVE_FLAG = BIT(12), 315 HDMI_STATUS_GM_PACKET_RECEIVE_FLAG = BIT(13), 316 HDMI_STATUS_HBR_PACKET_RECEIVE_FLAG = BIT(14), 317 HDMI_STATUS_VBI_PACKET_RECEIVE_FLAG = BIT(15), 318 HDMI_STATUS_HDR_PACKET_RECEIVE_FLAG = BIT(16), 319 HDMI_STATUS_RESERVED_PACKET_RECEIVE_FLAG = BIT(17), 320 HDMI_STATUS_EDR_VALID_FLAG = BIT(18), 321 }; 322 323 enum HDMI_INFO_SOURCE_TYPE 324 { 325 HDMI_INFO_SOURCE0 = 0, 326 HDMI_INFO_SOURCE_MAX, 327 HDMI_INFO_SOURCE1, 328 }; 329 330 enum HDMI_CHECK_PACKET_TYPE 331 { 332 HDMI_CHECK_PACKET_CLEAR_RECEIVE_STATUS = 0, 333 HDMI_CHECK_PACKET_WAIT_AVI_PACKET, 334 HDMI_CHECK_PACKET_MEASURE_PACKET_INTERVAL, 335 HDMI_CHECK_PACKET_UPDATE_RECEIVE_STATUS, 336 }; 337 338 #define HDMI_PACKET_RECEIVE_INTERVAL_MIN 4 339 #define HDMI_PACKET_RECEIVE_INTERVAL_MAX 11 340 341 //============================================================================== 342 //============================================================================== 343 #ifdef MHAL_HDMI_C 344 #define INTERFACE 345 #else 346 #define INTERFACE extern 347 #endif 348 349 INTERFACE MS_BOOL Hal_HDCP_GetEncryptionFlag(E_MUX_INPUTPORT enInputPortType); 350 INTERFACE MS_U16 Hal_HDMI_Func_Caps(void); 351 ////--------------> for HDCP 352 //INTERFACE void Hal_HDCP_clearflag( void ); 353 INTERFACE void Hal_HDCP_ddc_en(E_MUX_INPUTPORT enInputPortType, MS_BOOL bEnable); 354 INTERFACE void Hal_HDCP_Vsync_end_en( MS_BOOL bEnalbe ); 355 356 ////--------------> for HDMI 357 INTERFACE void Hal_HDMI_pullhpd(MS_BOOL bHighLow, E_MUX_INPUTPORT enInputPortType, MS_BOOL bInverse, MS_U8 ucMHLSupportPath); 358 INTERFACE void Hal_HDMI_init(MS_BOOL bImmeswitchSupport, MS_U8 ucMHLSupportPath); 359 //INTERFACE void Hal_HDMI_init( void ); 360 INTERFACE void Hal_HDMI_exit(E_MUX_INPUTPORT enInputPortType); 361 362 INTERFACE void Hal_HDMI_Set_EQ(E_MUX_INPUTPORT enInputPortType, MS_HDMI_EQ enEq, MS_U8 u8EQValue); 363 INTERFACE void Hal_HDMI_Audio_MUTE_Enable(MS_U16 u16MuteEvent, MS_U16 u16MuteMask); 364 INTERFACE void Hal_HDMI_Audio_Status_Clear(void); 365 366 INTERFACE MS_U16 Hal_HDMI_gcontrol_info(HDMI_GControl_INFO_t gcontrol, MS_U8 ucHDMIInfoSource); 367 INTERFACE MS_U16 Hal_HDMI_pll_ctrl1(HDMI_PLL_CTRL_t pllctrl, MS_BOOL bread, MS_U16 u16value); 368 INTERFACE MS_U16 Hal_HDMI_pll_ctrl2(HDMI_PLL_CTRL2_t pllctrl, MS_BOOL bread, MS_U16 u16value); 369 INTERFACE MS_U16 Hal_HDMI_GetHDEInfo(MS_U8 ucHDMIInfoSource); 370 INTERFACE MS_U16 Hal_HDMI_GetDataInfo(E_HDMI_GET_DATA_INFO enInfo, MS_U8 ucHDMIInfoSource); 371 INTERFACE void Hal_DVI_Accumulator_Monitor( void ); 372 373 INTERFACE void Hal_DVI_HF_adjust( void ); 374 375 ////--------------> for HDMI Audio 376 INTERFACE void Hal_HDMI_audio_output(MS_BOOL bEnable); 377 378 ////--------------> for DVI 379 INTERFACE MS_BOOL Hal_DVI_clk_lessthan70mhz_usingportc( MS_BOOL bIsPortC); 380 INTERFACE MS_U16 Hal_DVI_ChannelPhaseStatus( MS_U8 u8Channel); 381 INTERFACE MS_BOOL Hal_DVI_clk_stable_usingportc(MS_BOOL bIsPortC); 382 INTERFACE MS_BOOL Hal_DVI_clklose_det(E_MUX_INPUTPORT enInputPortType); 383 INTERFACE void Hal_DVI_IMMESWITCH_PS_SW_Path(void); 384 INTERFACE void Hal_DVI_sw_reset(MS_U16 u16Reset); 385 INTERFACE MS_U16 Hal_DVI_irq_info(E_MUX_INPUTPORT enInputPortType, MS_U16 irqbit); 386 INTERFACE void Hal_DVI_irq_mask(E_MUX_INPUTPORT enInputPortType, MS_U16 irqbit); 387 INTERFACE void Hal_DVI_irq_forcemode(E_MUX_INPUTPORT enInputPortType, MS_U16 irqbit); 388 INTERFACE void Hal_DVI_irq_clear(E_MUX_INPUTPORT enInputPortType, MS_U16 irqbit); 389 INTERFACE void Hal_DVI_ClkPullLow(MS_BOOL bPullLow, E_MUX_INPUTPORT enInputPortType); 390 INTERFACE void Hal_DVI_SwitchSrc(E_MUX_INPUTPORT enInputPortType, MS_U8 ucHDMIInfoSource); 391 392 INTERFACE MS_U8 Hal_HDMI_err_status_update(MS_U8 ucHDMIInfoSource, MS_U8 u8value, MS_BOOL bread); 393 INTERFACE void Hal_HDMI_pkt_reset(E_MUX_INPUTPORT enInputPortType, HDMI_REST_t breset); 394 INTERFACE void Hal_HDMI_hpd_en(MS_BOOL benable); 395 INTERFACE void Hal_HDCP_initproductionkey( MS_U8 * pu8HdcpKeyData ); 396 INTERFACE void Hal_HDCP_clearflag(E_MUX_INPUTPORT enInputPortType); 397 INTERFACE void Hal_HDMI_audio_output( MS_BOOL bEnable ); 398 INTERFACE MS_U32 Hal_HDMI_packet_info(MS_U8 ucHDMIInfoSource); 399 INTERFACE MS_U8 Hal_HDMI_audio_content_protection_info(MS_U8 ucHDMIInfoSource); 400 INTERFACE EN_AVI_INFOFRAME_VERSION Hal_HDMI_avi_infoframe_info_ver(MS_U8 ucHDMIInfoSource); 401 INTERFACE MS_U8 Hal_HDMI_avi_infoframe_info(MS_U8 ucHDMIInfoSource, MS_U8 u8byte); 402 INTERFACE MS_BOOL Hal_HDMI_get_packet_value(MS_U8 ucHDMIInfoSource, MS_HDMI_PACKET_STATE_t u8state, MS_U8 u8byte_idx, MS_U8 *pu8Value); 403 404 INTERFACE MS_U8 Hal_HDMI_audio_channel_status(MS_U8 ucHDMIInfoSource, MS_U8 u8byte); 405 INTERFACE MS_U16 Hal_HDCP_getstatus(E_MUX_INPUTPORT enInputPortType); 406 INTERFACE void Hal_DVI_adc_adjust( MS_BOOL bClockLessThan70MHz); 407 408 INTERFACE void Hal_HDMI_packet_ctrl(MS_U8 ucHDMIInfoSource, MS_U16 u16pkt); 409 INTERFACE MS_U8 Hal_HDMI_audio_payload_info(MS_U8 ucHDMIInfoSource, MS_U8 u8byte); 410 411 // DDC 412 INTERFACE void HAL_HDMI_DDCRam_SelectPort(E_XC_DDCRAM_PROG_TYPE eDDCRamType); 413 INTERFACE void HAL_HDMI_DDCRAM_SetPhyAddr(XC_DDCRAM_PROG_INFO *pstDDCRam_Info); 414 415 416 // HDMI 1.4 new feature: 417 INTERFACE E_HDMI_ADDITIONAL_VIDEO_FORMAT Hal_HDMI_Check_Additional_Format(MS_U8 ucHDMIInfoSource); 418 INTERFACE E_XC_3D_INPUT_MODE Hal_HDMI_Get_3D_Structure(MS_U8 ucHDMIInfoSource); 419 INTERFACE E_HDMI_3D_EXT_DATA_T Hal_HDMI_Get_3D_Ext_Data(MS_U8 ucHDMIInfoSource); 420 INTERFACE void Hal_HDMI_Get_3D_Meta_Field(MS_U8 ucHDMIInfoSource, sHDMI_3D_META_FIELD *pdata); 421 INTERFACE MS_U8 Hal_HDMI_Get_VIC_Code(MS_U8 ucHDMIInfoSource); 422 INTERFACE E_HDMI_VIC_4Kx2K_CODE Hal_HDMI_Get_4Kx2K_VIC_Code(MS_U8 ucHDMIInfoSource); 423 INTERFACE void Hal_HDMI_Set_YUV422to444_Bypass(MS_BOOL btrue); 424 INTERFACE MS_BOOL Hal_HDMI_Is_Input_Large_166MHz(MS_U8 ucHDMIInfoSource); 425 INTERFACE void Hal_HDMI_AVG_ScaleringDown(MS_U8 ucHDMIInfoSource, MS_BOOL btrue); 426 INTERFACE void Hal_HDMI_ARC_PINControl(E_MUX_INPUTPORT enInputPortType, MS_BOOL bEnable, MS_BOOL bDrivingHigh); 427 INTERFACE void Hal_DVI_Software_Reset(E_MUX_INPUTPORT enInputPortType, MS_U16 u16Reset); 428 429 MS_BOOL Hal_DVI_GetPowerSavingStatus(E_MUX_INPUTPORT enInputPortType); 430 MS_BOOL Hal_DVI_GetDEStableStatus(E_MUX_INPUTPORT enInputPortType); 431 void Hal_DVI_EnhanceImmeswitch(E_MUX_INPUTPORT enInputPortType, MS_BOOL bflag); 432 void Hal_DVI_ForceAllPortsEnterPS(void); 433 434 //EX_ADD 435 INTERFACE MS_U16 Hal_HDMI_GetTMDSFreq(void); 436 INTERFACE MS_BOOL Hal_HDMI_CheckHDMI20_Setting(E_MUX_INPUTPORT enInputPortType); 437 INTERFACE void Hal_HDMI_StablePolling(MS_U8 ucMHLSupportPath, stHDMI_POLLING_INFO *stHDMIPollingInfo); 438 439 INTERFACE void Hal_HDMI_Set5VDetectGPIOSelect(MS_U32 ul5VDetectGPIOIndex); 440 441 INTERFACE void Hal_HDMI_SwitchVSDBtoHDRPacket(MS_BOOL bEnableHDR); 442 443 INTERFACE MS_BOOL Hal_HDMI_Get_InfoFrame(MS_U8 ucHDMIInfoSource, MS_HDMI_PACKET_STATE_t u8state, void *pData); 444 445 //INTERFACE void Hal_HDCP22_InitCBFunc(HDCP22_Recv_CBF pCBFunc, void* pContext); 446 INTERFACE void Hal_HDCP22_SetReadyBit(MS_U8 ucPortIdx, MS_BOOL bIsReady); 447 INTERFACE void Hal_HDCP22_PortInit(MS_U8 ucPortIdx); 448 INTERFACE MS_BOOL Hal_HDCP22_PollingWriteDone(MS_U8 ucPortIdx); 449 INTERFACE MS_BOOL Hal_HDCP22_PollingReadDone(MS_U8 ucPortIdx); 450 INTERFACE void Hal_HDCP22_EnableCipher(MS_U8 ucPortType, MS_U8 ucPortIdx, MS_BOOL bIsEnable); 451 INTERFACE void Hal_HDCP22_FillCipherKey(MS_U8 ucPortIdx, MS_U8 *pucSessionKey, MS_U8 *pucRiv); 452 INTERFACE void Hal_HDCP22_FetchMsg(MS_U8 ucPortIdx, MS_U8* pucData, MS_U32 dwDataLen); 453 INTERFACE MS_BOOL Hal_HDCP22_RecvMsg(MS_U8 ucPortIdx, MS_U8 *ucMsgData); 454 INTERFACE void Hal_HDCP22_SendMsg(MS_U8 ucPortType, MS_U8 ucPortIdx, MS_U8* pucData, MS_U32 dwDataLen, void* pDummy, MS_U8* ubRecIDListSetDone); 455 /*************************** HDCP Repeater ***************************/ 456 INTERFACE MS_BOOL Hal_HDCP_WriteX74(E_MUX_INPUTPORT enInputPortType, MS_U8 ubOffset, MS_U8 ubData); 457 INTERFACE MS_U8 Hal_HDCP_ReadX74(E_MUX_INPUTPORT enInputPortType, MS_U8 ubOffset); 458 INTERFACE void Hal_HDCP_SetReady(E_MUX_INPUTPORT enInputPortType, MS_BOOL bIsReady); 459 INTERFACE void Hal_HDCP_WriteKSVList(E_MUX_INPUTPORT enInputPortType, MS_U8* pucData, MS_U32 dwDataLen); 460 INTERFACE void Hal_HDCP_ClearStatus(E_MUX_INPUTPORT enInputPortType, MS_U16 usInt); 461 INTERFACE void Hal_HDCP_WriteDoneInterruptEnable(E_MUX_INPUTPORT enInputPortType, MS_BOOL bEnableIRQ); 462 /*************************** HDCP Repeater ***************************/ 463 464 #undef INTERFACE 465 #endif /* MHAL_HDMI_H */ 466 467