1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HWREG_DIP_H_ 96 #define _HWREG_DIP_H_ 97 98 //TrustZone 99 #define REG_TZPC_NONPM_BASE 0x123900UL 100 #define REG_TZPC_NONPM_DIP (REG_TZPC_NONPM_BASE + (0x74<<1) ) 101 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) ) 102 103 //CLOCK 104 #define REG_CLOCK_BASE (0x100B00UL) 105 106 #define REG_MFDEC_LINEBUFFER (REG_CLOCK_BASE + (0x57<<1) ) 107 #define MFDEC_MAIN_LB (BMASK(3:0)) 108 #define ENABLE_MFDEC_LB (0) 109 #define MFDEC_SUB_LB (BMASK(7:4)) 110 111 112 //MFDec 113 #define REG_MFDEC_BASE (0x112200UL) 114 115 #define MFDEC_ID0 (0) 116 #define MFDEC_ID1 (1) 117 118 #define REG_MFDEC_ENA(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x00<<1) ) 119 #define MFDEC_ENABLE (BIT(0)) 120 #define MFDEC_HMIRROR (BIT(1)) 121 #define MFDEC_VMIRROR (BIT(2)) 122 #define MFDEC_VP9_MODE (BIT(3)) 123 #define MFDEC_HVD_MODE (BIT(4)) 124 #define MFDEC_UNCOMP_MODE (BIT(5)) 125 #define MFDEC_BYPASS_MODE (BIT(9)) 126 #define MFDEC_RIU_MODE (BIT(12)) 127 #define MFDEC_RIU1_MODE (BIT(13)) 128 #define REG_MFDEC_ENA_MASK (MFDEC_RIU1_MODE|MFDEC_RIU_MODE|MFDEC_BYPASS_MODE|MFDEC_UNCOMP_MODE|MFDEC_HVD_MODE|MFDEC_VP9_MODE|MFDEC_VMIRROR|MFDEC_HMIRROR|MFDEC_ENABLE) 129 130 #define REG_MFDEC_FB_MIU(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x01<<1) ) 131 #define MFDEC_LUMA_FB_MIU (BMASK(1:0)) 132 #define MFDEC_LUMA_FB_MIU_SHIFT (0) 133 #define MFDEC_CHROMA_FB_MIU (BMASK(3:2)) 134 #define MFDEC_CHROMA_FB_SHIFT (2) 135 #define MFDEC_BITLEN_FB_MIU (BMASK(5:4)) 136 #define MFDEC_BITLEN_FB_MIU_SHIFT (4) 137 #define MFDEC_MIF0_BURST_LEN (BMASK(11:8)) 138 #define MFDEC_MIF0_BURST_SHIFT (8) 139 #define MFDEC_MIF1_BURST_LEN (BMASK(15:12)) 140 #define MFDEC_MIF1_BURST_SHIFT (12) 141 142 #define REG_MFDEC_X_START(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x02<<1) ) 143 #define MFDEC_X_START (BMASK(7:0)) 144 145 #define REG_MFDEC_Y_START(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x03<<1) ) 146 #define MFDEC_Y_START (BMASK(11:0)) 147 148 #define REG_MFDEC_H_SIZE(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x04<<1) ) 149 #define MFDEC_H_SIZE (BMASK(8:0)) 150 151 #define REG_MFDEC_V_SIZE(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x05<<1) ) 152 #define MFDEC_V_SIZE (BMASK(11:0)) 153 154 #define REG_MFDEC_FB_PITCH(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x06<<1) ) 155 #define MFDEC_FB_PITCH (BMASK(9:0)) 156 157 #define REG_MFDEC_BITLEN_FB_PITCH(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x07<<1) ) 158 #define MFDEC_BITLEN_FB_FIXED_PAT_MASK (BMASK(15:8)) 159 #define MFDEC_BITLEN_FB_PITCH_MASK (BMASK(7:0)) 160 161 #define REG_MFDEC_LUMA_FB_BASE_L(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x08<<1) ) 162 #define MFDEC_LUMA_FB_BASE_L (BMASK(15:0)) 163 #define REG_MFDEC_LUMA_FB_BASE_H(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x09<<1) ) 164 #define MFDEC_LUMA_FB_BASE_H (BMASK(12:0)) 165 #define MFDEC_LUMA_FB_BASE_H_SHIFT (12) 166 167 #define REG_MFDEC_CHROMA_FB_BASE_L(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x0A<<1) ) 168 #define MFDEC_CHROMA_FB_BASE_L (BMASK(15:0)) 169 #define REG_MFDEC_CHROMA_FB_BASE_H(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x0B<<1) ) 170 #define MFDEC_CHROMA_FB_BASE_H (BMASK(12:0)) 171 172 #define REG_MFDEC_BITLEN_FB_BASE_L(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x0C<<1) ) 173 #define MFDEC_BITLEN_FB_BASE_L (BMASK(15:0)) 174 #define REG_MFDEC_BITLEN_FB_BASE_H(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x0D<<1) ) 175 #define MFDEC_BITLEN_FB_BASE_H (BMASK(12:0)) 176 177 #define REG_MFDEC_CW_LEN2(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x20<<1) ) 178 #define MFDEC_CW_LEN2_MASK (BMASK(11:0)) 179 180 #define REG_MFDEC_CW_LEN3(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x21<<1) ) 181 #define MFDEC_CW_LEN3_MASK (BMASK(11:0)) 182 183 #define REG_MFDEC_CW_LEN4(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x22<<1) ) 184 #define MFDEC_CW_LEN4_MASK (BMASK(11:0)) 185 186 #define REG_MFDEC_CW_LEN5(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x23<<1) ) 187 #define MFDEC_CW_LEN5_MASK (BMASK(11:0)) 188 189 #define REG_MFDEC_CW_BASE(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x24<<1) ) 190 #define MFDEC_CW_BASE (BMASK(11:0)) 191 192 #define REG_MFDEC_CW_MAX(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x25<<1) ) 193 #define MFDEC_CW_MAX (BMASK(11:0)) 194 195 #define REG_MFDEC_SYMB_BASE(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x26<<1) ) 196 #define MFDEC_SYMB_BASE (BMASK(4:0)) 197 #define MFDEC_SYMB_MAX (BMASK(12:8)) 198 199 #define REG_MFDEC_HUF_TAB(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x27<<1) ) 200 201 #define REG_MFDEC_DBUS_L(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x12<<1) ) 202 #define REG_MFDEC_DBUS_H(id) (REG_MFDEC_BASE + ((0x40<<1)*id) + (0x13<<1) ) 203 204 #define MFDEC_X_START_ALIGN (16) 205 #define MFDEC_HSIZE_ALIGN (16) 206 #define MFDEC_ADDR_ALIGN (8) 207 #define MFDEC_FB_PITCH_ALIGN (8) 208 #define MFEDC_TABLE_INDEX_COUNT (48) 209 210 #endif 211