1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 //==============================================================================
95 // [mhal_sc.c]
96 // Date: 20081203
97 // Descriptions: Add a new layer for HW setting
98 //==============================================================================
99 #define MHAL_SC_C
100
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <asm/div64.h>
103 #include <linux/slab.h>
104 #else
105 #define do_div(x,y) ((x)/=(y))
106 #endif
107
108 // Common Definition
109 #include "MsCommon.h"
110 #include "MsIRQ.h"
111 #include "MsOS.h"
112 #include "mhal_xc_chip_config.h"
113 #include "utopia.h"
114 #include "xc_hwreg_utility2.h"
115 #include "xc_Analog_Reg.h"
116 #include "drvXC_IOPort.h"
117 #include "apiXC.h"
118 #include "apiXC_DWIN.h"
119 #include "apiXC_PCMonitor.h"
120 #include "drv_sc_ip.h"
121 #include "mvideo_context.h"
122 #include "mhal_sc.h"
123 #include "mhal_menuload.h"
124 #include "halCHIP.h"
125 #include "drv_sc_menuload.h"
126 #include "drv_sc_isr.h"
127 #include "drv_sc_DIP_scaling.h"
128 #include "mhal_dip.h"
129 #include "mhal_mux.h"
130 #include "hwreg_ipmux.h"
131 #include "drvMIU.h"
132 #include "mdrv_sc_dynamicscaling.h"
133 #ifdef UTOPIA_V2
134 #include "XC_DWIN_private.h"
135 #include "utopia_dapi.h"
136 #endif
137
138 #ifdef MSOS_TYPE_LINUX_KERNEL
139 #include <linux/string.h>
140 #else
141 #include <string.h>
142 #endif
143
144 #define SC_DBG(x) //x
145 #define FPLL_DBG(x) //x
146 #define UHD_WIDTH 3840UL
147 #define FHD_WIDTH 1920UL
148 #ifdef UTOPIA_V2
149 #define g_DIPSrcInfo pDipResPri->g_DIPSrcInfo
150 #endif
151 #ifdef MSOS_TYPE_LINUX_KERNEL
152 #define H_DIP_PostScalingRatio(Input, Output) { u64_result = ((MS_U64)(Input)) * 1048576ul;do_div(u64_result,(Output));}
153 #define V_DIP_PostScalingRatio(Input, Output) { u64_result = ((MS_U64)(Input)) * 1048576ul;do_div(u64_result,(Output));}
154 #else
155 #define H_DIP_PostScalingRatio(Input, Output) ((MS_U32)( ((MS_U64)(Input)) * 1048576ul / (Output)))
156 #define V_DIP_PostScalingRatio(Input, Output) ((MS_U32)( ((MS_U64)(Input)) * 1048576ul / (Output)))
157 #endif
158
159 //TrustZone
160 #define REG_TZPC_NONPM_BASE 0x123900UL
161 #define REG_TZPC_NONPM_DIP (REG_TZPC_NONPM_BASE + (0x74<<1) )
162 #define REG_TZPC_NONPM_DWIN0 (REG_TZPC_NONPM_BASE + (0x79<<1) )
163
164 #define new_chakra
165 static MS_U8 DipWBufCnt=0,Dwin0WBufCnt=0,Dwin1WBufCnt=0;
166 static SCALER_DIP_SOURCE_TYPE DipSource = SCALER_DIP_SOURCE_TYPE_OP_SUB;
167 static SCALER_DIP_SOURCE_TYPE Dwin0Source = SCALER_DIP_SOURCE_TYPE_OP_SUB;
168 static SCALER_DIP_SOURCE_TYPE Dwin1Source = SCALER_DIP_SOURCE_TYPE_OP_SUB;
169 static MS_BOOL bPIPmode = FALSE;
170 static InterruptCb pDipIntCb;
171 static InterruptCb pDwin0IntCb;
172 static InterruptCb pDwin1IntCb;
173 static MS_BOOL bDipIsr = FALSE,bDwin0Isr = FALSE,bDwin1Isr = FALSE,bDIPRotation = FALSE,bAttached = FALSE;
174 static EN_DRV_XC_DWIN_DATA_FMT DipRFmt;
175 static MS_U16 DipSrcWidth = 0,Dwin0SrcWidth = 0,Dwin1SrcWidth = 0;
176 static MS_BOOL bDipHMirror = FALSE,bDWIN0HMirror = FALSE,bDWIN1HMirror = FALSE;
177 static MS_BOOL bDipUVSwap = FALSE,bDWIN0UVSwap = FALSE,bDWIN1UVSwap = FALSE;
178 static MS_BOOL bDipYCSwap = FALSE,bDWIN0YCSwap = FALSE,bDWIN1YCSwap = FALSE;
179 static MS_BOOL bDipR2Y = FALSE,bDwin0R2Y = FALSE,bDwin1R2Y = FALSE;
180 static EN_DRV_XC_DWIN_DATA_FMT DipFmt,Dwin0Fmt,Dwin1Fmt;
181 static SCALER_DIP_WIN DIPRotation = MAX_DIP_WINDOW;
182 //==============================================================================
183 //==============================================================================
184 #include "drvCMDQ.h"
185 #define CMDQ_WRITE_RIU_COMMAND (0x57)
186 #define MAX_CMDQ_NUM 1024
187 #define BANK_REG_MAX 0x80
188
189 static MS_U32 g_u16Ptr_CMQ[MAX_DIP_WINDOW] = {0};
190 static CAF_Struct DIP_CMDQ_BUFF [MAX_CMDQ_NUM];
191 static CAF_Struct DWIN0_CMDQ_BUFF [MAX_CMDQ_NUM];
192 static CAF_Struct DWIN1_CMDQ_BUFF [MAX_CMDQ_NUM];
193 static MS_U16 u16RegBK34Table[BANK_REG_MAX]= {0};
194 static MS_U16 u16RegBK36Table[BANK_REG_MAX]= {0};
195 static MS_U16 cmdq_ready_value,cmdq_wait_value;
196
197
198 MS_BOOL g_bCMDQ_Enable[MAX_DIP_WINDOW] = {FALSE};
199 MS_BOOL g_bCMDQ_Init = FALSE;
200 MS_U32 g_u32Wait_Reg[MAX_DIP_WINDOW] = {0x120332,0x120334,0x120338};
201
202 static MS_S32 g_s32DIPCMDQ_Init_Mutex[MAX_DIP_WINDOW] = {0};
203
204 #define DIPCMDQ_INIT_MUTEX_LOCK(eWindow) MsOS_ObtainMutex(g_s32DIPCMDQ_Init_Mutex[eWindow],MSOS_WAIT_FOREVER)
205 #define DIPCMDQ_INIT_MUTEX_UNLOCK(eWindow) MsOS_ReleaseMutex(g_s32DIPCMDQ_Init_Mutex[eWindow])
206 #define DIPCMDQ_INIT_MUTEX_DELETE(eWindow) MsOS_DeleteMutex(g_s32DIPCMDQ_Init_Mutex[eWindow])
207
208 #define XIU_BITMASK 0x10012E //Bank 0x1001_17[0] = 1 -' enable bit operation
209
210 #define DIP_WAIT()\
211 ({\
212 if (g_bCMDQ_Enable[eWindow] == TRUE)\
213 HAL_XC_DIP_CMDQWaitCommand(eWindow);\
214 })
215
216 #define DIP_W2BYTE(u32Id,u32Reg,u16Val)\
217 ({\
218 if((u32Reg&0xff00) == 0x3400)\
219 {\
220 u16RegBK34Table[((u32Reg&0xff)>>1)] = u16Val;\
221 }\
222 else if((u32Reg&0xff00) == 0x3600)\
223 {\
224 u16RegBK36Table[((u32Reg&0xff)>>1)] = u16Val;\
225 }\
226 if (g_bCMDQ_Enable[eWindow] == TRUE)\
227 CMDQ_DIP_W2BYTE(u32Id, u32Reg, u16Val, eWindow);\
228 else\
229 SC_W2BYTE(u32Id, u32Reg, u16Val);\
230 })
231
232 #define MDrv_DIP_Read2Byte(u32Reg)\
233 ({\
234 MDrv_Read2Byte(u32Reg);\
235 })
236
237 #define DIP_W4BYTE(u32Id,u32Reg,u32Val)\
238 ({\
239 if((u32Reg&0xff00) == 0x3400)\
240 {\
241 u16RegBK34Table[((u32Reg&0xff)>>1)] = u32Val&0x00FF;\
242 u16RegBK34Table[(((u32Reg+2)&0xff)>>1)] = (u32Val&0xFF00)>>16;\
243 }\
244 else if((u32Reg&0xff00) == 0x3600)\
245 {\
246 u16RegBK36Table[((u32Reg&0xff)>>1)] = u32Val&0x00FF;\
247 u16RegBK36Table[(((u32Reg+2)&0xff)>>1)] = (u32Val&0xFF00)>>16;\
248 }\
249 if (g_bCMDQ_Enable[eWindow] == TRUE)\
250 CMDQ_DIP_W4BYTE(u32Id, u32Reg, u32Val, eWindow);\
251 else\
252 SC_W4BYTE(u32Id, u32Reg, u32Val);\
253 })
254
255 #define DIP_W2BYTEMSK(u32Id,u32Reg,u16Val,u16Mask)\
256 ({\
257 if((u32Reg&0xff00) == 0x3400)\
258 {\
259 u16RegBK34Table[((u32Reg&0xff)>>1)] &= u16Mask;\
260 u16RegBK34Table[((u32Reg&0xff)>>1)] |= u16Val;\
261 }\
262 else if((u32Reg&0xff00) == 0x3600)\
263 {\
264 u16RegBK36Table[((u32Reg&0xff)>>1)] &= u16Mask;\
265 u16RegBK36Table[((u32Reg&0xff)>>1)] |= u16Val;\
266 }\
267 if (g_bCMDQ_Enable[eWindow] == TRUE)\
268 CMDQ_DIP_W2BYTEMSK(u32Id, u32Reg, u16Val, u16Mask, eWindow);\
269 else\
270 SC_W2BYTEMSK(u32Id, u32Reg, u16Val, u16Mask);\
271 })
272
273 #define MDrv_DIP_WriteByteMask(u32Reg,u8Val,u8Msk)\
274 ({\
275 if (g_bCMDQ_Enable[eWindow] == TRUE)\
276 MDrv_CMDQ_WriteByteMask(u32Reg, u8Val, u8Msk, eWindow);\
277 else\
278 MDrv_WriteByteMask(u32Reg, u8Val, u8Msk);\
279 })
280
281 #define MDrv_DIP_Write2ByteMask(u32Reg,u16Val,u16Mask)\
282 ({\
283 if (g_bCMDQ_Enable[eWindow] == TRUE)\
284 MDrv_CMDQ_Write2ByteMask(u32Reg, u16Val, u16Mask, eWindow);\
285 else\
286 MDrv_Write2ByteMask(u32Reg, u16Val, u16Mask);\
287 })
288
289 #define MDrv_DIP_WriteRegBit(u32Reg,bEnable,u8Mask)\
290 ({\
291 if (g_bCMDQ_Enable[eWindow] == TRUE)\
292 MDrv_CMDQ_WriteRegBit(u32Reg, bEnable, u8Mask, eWindow);\
293 else\
294 MDrv_WriteRegBit(u32Reg, bEnable, u8Mask);\
295 })
296
DIP_R2BYTE(MS_U32 u32Id,MS_U32 u32Reg,SCALER_DIP_WIN eWindow)297 static MS_U16 DIP_R2BYTE(MS_U32 u32Id,MS_U32 u32Reg,SCALER_DIP_WIN eWindow)
298 {
299 MS_U16 u16val=0;
300 MS_U32 u32idx=(u32Reg&0xff)>>1;
301
302 if(g_bCMDQ_Enable[eWindow] == TRUE)
303 {
304 if((u32Reg&0xff00)==0x3400)
305 {
306 u16val=u16RegBK34Table[u32idx];
307 }
308 else if((u32Reg&0xff00)==0x3600)
309 {
310 u16val=u16RegBK36Table[u32idx];
311 }
312 }
313 else
314 {
315 u16val=SC_R2BYTE(u32Id, u32Reg);
316 }
317 return u16val;
318 }
319
DIP_R4BYTE(MS_U32 u32Id,MS_U32 u32Reg,SCALER_DIP_WIN eWindow)320 static MS_U32 DIP_R4BYTE(MS_U32 u32Id, MS_U32 u32Reg,SCALER_DIP_WIN eWindow)
321 {
322 MS_U32 u32val=0;
323 MS_U32 u32idx=(u32Reg&0xff)>>1;
324
325 if(g_bCMDQ_Enable[eWindow] == TRUE)
326 {
327 if((u32Reg&0xff00)==0x3400)
328 {
329 u32val=(u16RegBK34Table[u32idx])|(u16RegBK34Table[u32idx+1]<<16);
330 }
331 else if((u32Reg&0xff00)==0x3600)
332 {
333 u32val=(u16RegBK36Table[u32idx])|(u16RegBK36Table[u32idx+1]<<16);
334 }
335 }
336 else
337 {
338 u32val=SC_R4BYTE(u32Id, u32Reg);
339 }
340 return u32val;
341 }
342
DIP_R2BYTEMSK(MS_U32 u32Id,MS_U32 u32Reg,MS_U16 u16Mask,SCALER_DIP_WIN eWindow)343 static MS_U16 DIP_R2BYTEMSK(MS_U32 u32Id, MS_U32 u32Reg, MS_U16 u16Mask,SCALER_DIP_WIN eWindow)
344 {
345 MS_U16 u16val=0;
346 MS_U32 u32idx=(u32Reg&0xff)>>1;
347 if(g_bCMDQ_Enable[eWindow] == TRUE)
348 {
349 if((u32Reg&0xff00)==0x3400)
350 {
351 u16val=u16RegBK34Table[u32idx]&u16Mask;
352 }
353 else if((u32Reg&0xff00)==0x3600)
354 {
355 u16val=u16RegBK36Table[u32idx]&u16Mask;
356 }
357 }
358 else
359 {
360 u16val=SC_R2BYTEMSK(u32Id, u32Reg, u16Mask);
361 }
362 return u16val;
363 }
364
HAL_XC_DIP_CMDQWaitCommand(SCALER_DIP_WIN eWindow)365 static MS_BOOL HAL_XC_DIP_CMDQWaitCommand(SCALER_DIP_WIN eWindow)
366 {
367 #if DIP_CMDQ_ENABLE
368 #if !(defined(MSOS_TYPE_LINUX_KERNEL))
369 if (g_u16Ptr_CMQ[eWindow] >= MAX_CMDQ_NUM)
370 {
371 DIP_H_ERR("[%s]: eWindow %d CMDQ Buffer is Full,g_u16Ptr_CMQ[%ld]\n", __FUNCTION__,eWindow,g_u16Ptr_CMQ[eWindow]);
372 return FALSE;
373 }
374
375 if(eWindow == DIP_WINDOW)
376 {
377 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(DIP_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]]),SCALAR_SC2CMDQ_TRIG_2,FALSE);
378 }
379 else if(eWindow == DWIN0_WINDOW)
380 {
381 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(DWIN0_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]]),SCALAR_SC2CMDQ_TRIG_2,FALSE);
382 }
383 else if(eWindow == DWIN1_WINDOW)
384 {
385 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(DWIN1_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]]),SCALAR_SC2CMDQ_TRIG_2,FALSE);
386 }
387 g_u16Ptr_CMQ[eWindow]++;
388 #endif
389 #endif
390 return TRUE;
391 }
392
HAL_XC_DIP_CMDQPushCommand(MS_U8 operation,MS_U32 destionation_address,MS_U16 destionation_value,MS_U16 mask,SCALER_DIP_WIN eWindow)393 static MS_BOOL HAL_XC_DIP_CMDQPushCommand(MS_U8 operation, MS_U32 destionation_address, MS_U16 destionation_value, MS_U16 mask,SCALER_DIP_WIN eWindow)
394 {
395 MS_U16 idx=(destionation_address&0xff)>>1;
396
397 if (g_u16Ptr_CMQ[eWindow] >= MAX_CMDQ_NUM)
398 {
399 DIP_H_ERR("[%s]: eWindow %d CMDQ Buffer is Full\n", __FUNCTION__,eWindow);
400 return FALSE;
401 }
402
403 if((destionation_address&0xff00)==0x3400)
404 {
405 u16RegBK34Table[idx] &= mask;
406 u16RegBK34Table[idx] |= destionation_value;
407 }
408 else if((destionation_address&0xff00)==0x3600)
409 {
410 u16RegBK36Table[idx] &= mask;
411 u16RegBK36Table[idx] |= destionation_value;
412 }
413
414 if(eWindow == DIP_WINDOW)
415 {
416 DIP_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].operation = operation;
417 DIP_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].destionation_address = destionation_address;
418 DIP_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].destionation_value = destionation_value;
419 DIP_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].mask = ((~mask)&0xFFFF);
420 }
421 else if(eWindow == DWIN0_WINDOW)
422 {
423 DWIN0_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].operation = operation;
424 DWIN0_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].destionation_address = destionation_address;
425 DWIN0_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].destionation_value = destionation_value;
426 DWIN0_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].mask = ((~mask)&0xFFFF);
427 }
428 else if(eWindow == DWIN1_WINDOW)
429 {
430 DWIN1_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].operation = operation;
431 DWIN1_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].destionation_address = destionation_address;
432 DWIN1_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].destionation_value = destionation_value;
433 DWIN1_CMDQ_BUFF[g_u16Ptr_CMQ[eWindow]].mask = ((~mask)&0xFFFF);
434 }
435 g_u16Ptr_CMQ[eWindow]++;
436 return TRUE;
437 }
438
MDrv_CMDQ_WriteByteMask(MS_U32 u32Reg,MS_U8 u8Val,MS_U8 u8Mask,SCALER_DIP_WIN eWindow)439 static void MDrv_CMDQ_WriteByteMask(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Mask, SCALER_DIP_WIN eWindow)
440 {
441 MS_BOOL ret = FALSE;
442
443 ret = HAL_XC_DIP_CMDQPushCommand(CMDQ_WRITE_RIU_COMMAND, u32Reg, u8Val, u8Mask, eWindow);
444 if (ret == FALSE)
445 {
446 DIP_H_ERR("[%s] is error\n", __FUNCTION__);
447 }
448 }
449
MDrv_CMDQ_WriteRegBit(MS_U32 u32Reg,MS_BOOL bEnable,MS_U8 u8Mask,SCALER_DIP_WIN eWindow)450 static void MDrv_CMDQ_WriteRegBit(MS_U32 u32Reg, MS_BOOL bEnable, MS_U8 u8Mask, SCALER_DIP_WIN eWindow)
451 {
452 MS_BOOL ret = FALSE;
453
454 ret = HAL_XC_DIP_CMDQPushCommand(CMDQ_WRITE_RIU_COMMAND, u32Reg, (MS_U16) (bEnable? u8Mask:0), u8Mask, eWindow);
455 if (ret == FALSE)
456 {
457 DIP_H_ERR("[%s] is error\n", __FUNCTION__);
458 }
459 }
460
MDrv_CMDQ_Write2ByteMask(MS_U32 u32Reg,MS_U16 u16Val,MS_U16 u16Mask,SCALER_DIP_WIN eWindow)461 static void MDrv_CMDQ_Write2ByteMask(MS_U32 u32Reg, MS_U16 u16Val, MS_U16 u16Mask, SCALER_DIP_WIN eWindow)
462 {
463 MS_BOOL ret = FALSE;
464
465 if ( ((u32Reg) & 0x01) )
466 u32Reg = u32Reg -1;
467
468 ret = HAL_XC_DIP_CMDQPushCommand(CMDQ_WRITE_RIU_COMMAND, u32Reg, u16Val, u16Mask, eWindow);
469 if (ret == FALSE)
470 {
471 DIP_H_ERR("[%s] is error\n", __FUNCTION__);
472 }
473 }
474
475
MDrv_CMDQ_Write2Byte(MS_U32 u32Reg,MS_U16 u16Val,SCALER_DIP_WIN eWindow)476 static void MDrv_CMDQ_Write2Byte(MS_U32 u32Reg, MS_U16 u16Val, SCALER_DIP_WIN eWindow)
477 {
478 MS_BOOL ret = FALSE;
479
480 if ( ((u32Reg) & 0x01) )
481 u32Reg = u32Reg -1;
482
483 ret = HAL_XC_DIP_CMDQPushCommand(CMDQ_WRITE_RIU_COMMAND, u32Reg, u16Val, 0xFFFF, eWindow);
484 if (ret == FALSE)
485 {
486 DIP_H_ERR("[%s] is error\n", __FUNCTION__);
487 }
488 }
489
CMDQ_DIP_W2BYTE(MS_U32 u32Id,MS_U32 u32Reg,MS_U16 u16Val,SCALER_DIP_WIN eWindow)490 static void CMDQ_DIP_W2BYTE(MS_U32 u32Id, MS_U32 u32Reg, MS_U16 u16Val, SCALER_DIP_WIN eWindow)
491 {
492 #if ENABLE_REGISTER_SPREAD
493 MDrv_CMDQ_Write2Byte((REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ), u16Val, eWindow);
494 #else
495 MDrv_CMDQ_Write2Byte(REG_SCALER_BASE, ((u32Reg) >> 8) & 0x00FF + _XC_Device_Offset[u32Id], eWindow);
496 MDrv_CMDQ_Write2Byte((REG_SCALER_BASE +((u32Reg) & 0xFF) , u16Val, eWindow);
497 #endif
498 }
499
CMDQ_DIP_W4BYTE(MS_U32 u32Id,MS_U32 u32Reg,MS_U32 u32Val,SCALER_DIP_WIN eWindow)500 static void CMDQ_DIP_W4BYTE(MS_U32 u32Id, MS_U32 u32Reg, MS_U32 u32Val, SCALER_DIP_WIN eWindow)
501 {
502 #if ENABLE_REGISTER_SPREAD
503 MDrv_CMDQ_Write2Byte((REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ), (MS_U16)((u32Val) & 0x0000FFFF), eWindow);
504 MDrv_CMDQ_Write2Byte((REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) + 2 ), (MS_U16)(((u32Val) >> 16) & 0x0000FFFF), eWindow);
505 #else
506 MDrv_CMDQ_Write2Byte(REG_SCALER_BASE, ((u32Reg) >> 8) & 0x00FF + _XC_Device_Offset[u32Id], eWindow);
507 MDrv_CMDQ_Write2Byte((REG_SCALER_BASE + ((u32Reg) & 0xFF) ), (MS_U16)((u32Val) & 0x0000FFFF), eWindow);
508 MDrv_CMDQ_Write2Byte((REG_SCALER_BASE + ((u32Reg) & 0xFF) + 2 ), (MS_U16)(((u32Val) >> 16) & 0x0000FFFF), eWindow);
509 #endif
510 }
511
512
CMDQ_DIP_W2BYTEMSK(MS_U32 u32Id,MS_U32 u32Reg,MS_U16 u16Val,MS_U16 u16Mask,SCALER_DIP_WIN eWindow)513 static void CMDQ_DIP_W2BYTEMSK(MS_U32 u32Id, MS_U32 u32Reg, MS_U16 u16Val, MS_U16 u16Mask, SCALER_DIP_WIN eWindow)
514 {
515 #if ENABLE_REGISTER_SPREAD
516 MDrv_CMDQ_Write2ByteMask((REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + (_XC_Device_Offset[u32Id] << 8) ), u16Val, u16Mask, eWindow);
517 #else
518 MDrv_CMDQ_Write2Byte(REG_SCALER_BASE, ((u32Reg) >> 8) & 0x00FF + _XC_Device_Offset[u32Id], eWindow);
519 MDrv_CMDQ_Write2ByteMask((REG_SCALER_BASE +((u32Reg) & 0xFF) , u16Val, u16Mask, eWindow);
520 #endif
521 }
522
HAL_XC_DIP_CMDQInit(void * pInstance,SCALER_DIP_WIN eWindow)523 MS_BOOL HAL_XC_DIP_CMDQInit(void *pInstance,SCALER_DIP_WIN eWindow)
524 {
525 if(g_s32DIPCMDQ_Init_Mutex[eWindow] != 0)
526 {
527 if(eWindow == DIP_WINDOW)
528 g_s32DIPCMDQ_Init_Mutex[eWindow] = MsOS_CreateMutex(E_MSOS_FIFO, "DIP_CMDQ_INIT" , MSOS_PROCESS_SHARED);
529 else if(eWindow == DWIN0_WINDOW)
530 g_s32DIPCMDQ_Init_Mutex[eWindow] = MsOS_CreateMutex(E_MSOS_FIFO, "DWIN0_CMDQ_INIT" , MSOS_PROCESS_SHARED);
531 else if(eWindow == DWIN1_WINDOW)
532 g_s32DIPCMDQ_Init_Mutex[eWindow] = MsOS_CreateMutex(E_MSOS_FIFO, "DWIN1_CMDQ_INIT" , MSOS_PROCESS_SHARED);
533 }
534
535 if (g_s32DIPCMDQ_Init_Mutex[eWindow] < 0)
536 {
537 DIP_H_ERR("Error: [%s] line:%d, eWindow:%d MsOS_CreateMutex Fail[%ld]\n",
538 __FUNCTION__, __LINE__, eWindow, g_s32DIPCMDQ_Init_Mutex[eWindow]);
539
540 g_s32DIPCMDQ_Init_Mutex[eWindow] = 0;
541 return FALSE;
542 }
543
544
545 if (g_bCMDQ_Init == TRUE)
546 return TRUE;
547 //MDrv_DIP_WriteRegBit(XIU_BITMASK,BIT(0),BIT(0));
548
549 g_bCMDQ_Init = TRUE;
550
551 return TRUE;
552 }
553
554 #if DIP_CMDQ_ENABLE
HAL_XC_DIP_CMDQTriggerCommand(SCALER_DIP_WIN eWindow)555 static MS_BOOL HAL_XC_DIP_CMDQTriggerCommand(SCALER_DIP_WIN eWindow)
556 {
557 CH_Struct_Pointer dip_cmdq_st;
558 DRVCMDQ_RESULT sResult;
559 MS_U16 u16Index;
560
561 cmdq_ready_value = MDrv_DIP_Read2Byte(g_u32Wait_Reg[eWindow]);
562 if(cmdq_ready_value == 0xFFF)
563 cmdq_ready_value = 0;
564 cmdq_ready_value++;
565 MDrv_DIP_Write2ByteMask(g_u32Wait_Reg[eWindow],cmdq_ready_value,0xFFF);
566 #if 0 //for Debug
567 MS_U16 i=0;
568 for(i=0;i<g_u16Ptr_CMQ[eWindow];i++)
569 {
570 DIP_H_ERR("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,DIP_CMDQ_BUFF[i].operation,DIP_CMDQ_BUFF[i].destionation_address,DIP_CMDQ_BUFF[i].destionation_value,DIP_CMDQ_BUFF[i].mask);
571 }
572 #endif
573
574 dip_cmdq_st = (CH_Struct_Pointer) malloc(sizeof(CH_Struct));
575 dip_cmdq_st->Command_Number = g_u16Ptr_CMQ[eWindow];
576 if(eWindow == DIP_WINDOW)
577 dip_cmdq_st->Pointer_To_CAFArray = (CAF_Struct_Pointer)DIP_CMDQ_BUFF;
578 else if(eWindow == DWIN0_WINDOW)
579 dip_cmdq_st->Pointer_To_CAFArray = (CAF_Struct_Pointer)DWIN0_CMDQ_BUFF;
580 else if(eWindow == DWIN1_WINDOW)
581 dip_cmdq_st->Pointer_To_CAFArray = (CAF_Struct_Pointer)DWIN1_CMDQ_BUFF;
582
583 sResult = MDrv_CMDQ_Receive(dip_cmdq_st);
584
585 if (sResult != DRVCMDQ_OK)
586 {
587 DIP_H_ERR("[%s] ERROR, Return Error Code:%ld\n", __FUNCTION__, sResult);
588 for (u16Index = 0; u16Index<g_u16Ptr_CMQ[eWindow]; u16Index++)
589 {
590 if(eWindow == DIP_WINDOW)
591 DIP_H_ERR("opt:0x%x, dest:0x%lx, value:0x%x, mask:0x%x\n",
592 DIP_CMDQ_BUFF[u16Index].operation,
593 DIP_CMDQ_BUFF[u16Index].destionation_address,
594 DIP_CMDQ_BUFF[u16Index].destionation_value,
595 ~(DIP_CMDQ_BUFF[u16Index].mask));
596 else if(eWindow == DWIN0_WINDOW)
597 DIP_H_ERR("opt:0x%x, dest:0x%lx, value:0x%x, mask:0x%x\n",
598 DWIN0_CMDQ_BUFF[u16Index].operation,
599 DWIN0_CMDQ_BUFF[u16Index].destionation_address,
600 DWIN0_CMDQ_BUFF[u16Index].destionation_value,
601 ~(DWIN0_CMDQ_BUFF[u16Index].mask));
602 else if(eWindow == DWIN1_WINDOW)
603 DIP_H_ERR("opt:0x%x, dest:0x%lx, value:0x%x, mask:0x%x\n",
604 DWIN1_CMDQ_BUFF[u16Index].operation,
605 DWIN1_CMDQ_BUFF[u16Index].destionation_address,
606 DWIN1_CMDQ_BUFF[u16Index].destionation_value,
607 ~(DWIN1_CMDQ_BUFF[u16Index].mask));
608 }
609 return FALSE;
610 }
611
612 g_u16Ptr_CMQ[eWindow]= 0;
613 return TRUE;
614 }
615 #endif
616
HAL_XC_DIP_CMDQBegin(void * pInstance,SCALER_DIP_WIN eWindow)617 MS_BOOL HAL_XC_DIP_CMDQBegin(void *pInstance,SCALER_DIP_WIN eWindow)
618 {
619 #if DIP_CMDQ_ENABLE
620 #if !(defined(MSOS_TYPE_LINUX_KERNEL))
621 MS_U16 u16Index=0;
622
623 if(eWindow!=DIP_WINDOW)
624 DIP_H_ERR("Error:[%s],Line:%d,Not Support,eWindow%d\n",__FUNCTION__, __LINE__,eWindow);
625
626 if ( HAL_XC_DIP_CMDQInit(pInstance,eWindow) == FALSE)
627 {
628 DIP_H_ERR("Error:[%s],Line:%d, eWindow:%d, HAL_XC_DIP_CMDQInit Fail\n",
629 __FUNCTION__, __LINE__, eWindow);
630 return FALSE;
631 }
632
633 DIPCMDQ_INIT_MUTEX_LOCK(eWindow);
634
635 for(u16Index=0;u16Index<BANK_REG_MAX;u16Index++)
636 {
637 u16RegBK34Table[u16Index]= SC_R2BYTE(0, REG_SC_BK34_00_L+u16Index*2);
638 u16RegBK36Table[u16Index]= SC_R2BYTE(0, REG_SC_BK36_00_L+u16Index*2);
639 }
640 g_u16Ptr_CMQ[eWindow] = 0;
641 g_bCMDQ_Enable[eWindow] = TRUE;
642 #endif
643 #endif
644 return TRUE;
645 }
646
HAL_XC_DIP_CMDQEnd(void * pInstance,SCALER_DIP_WIN eWindow)647 MS_BOOL HAL_XC_DIP_CMDQEnd(void *pInstance,SCALER_DIP_WIN eWindow)
648 {
649 MS_BOOL bRet = TRUE;
650 #if DIP_CMDQ_ENABLE
651 #if !(defined(MSOS_TYPE_LINUX_KERNEL))
652 if(eWindow!=DIP_WINDOW)
653 DIP_H_ERR("Error:[%s],Line:%d,Not Support,eWindow%d\n",__FUNCTION__, __LINE__,eWindow);
654
655 bRet &= HAL_XC_DIP_CMDQTriggerCommand(eWindow);
656 if (bRet == FALSE)
657 DIP_H_ERR("[%s] ERROR: MDrv_DIPCMDQ_TriggerCommand\n", __FUNCTION__);
658
659 g_u16Ptr_CMQ[eWindow] = 0;
660 g_bCMDQ_Enable[eWindow] = FALSE;
661 DIPCMDQ_INIT_MUTEX_UNLOCK(eWindow);
662 #endif
663 #endif
664 return bRet;
665 }
666 //==============================================================================
667
668 //extern PQ_Function_Info s_PQ_Function_Info;
669 //extern MS_BOOL s_bKeepPixelPointerAppear;
670
Hal_SC_DWIN_set_422_cbcr_swap(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)671 void Hal_SC_DWIN_set_422_cbcr_swap(void *pInstance, MS_BOOL bEnable, SCALER_DIP_WIN eWindow)
672 {
673 if(eWindow == DIP_WINDOW)
674 {
675 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L, bEnable ? BIT(3) : 0, BIT(3));
676 }
677 else if( eWindow == DWIN0_WINDOW )
678 {
679 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, bEnable ? BIT(3) : 0, BIT(3));
680 }
681 else if( eWindow == DWIN1_WINDOW )
682 {
683 DIP_W2BYTEMSK(0, REG_SC_BK3C_44_L, bEnable ? BIT(3) : 0, BIT(3));
684 }
685 else
686 {
687 return;
688 }
689 }
690
Hal_SC_DWIN_set_pre_align_pixel(void * pInstance,MS_BOOL bEnable,MS_U16 pixels,SCALER_DIP_WIN eWindow)691 void Hal_SC_DWIN_set_pre_align_pixel(void *pInstance, MS_BOOL bEnable, MS_U16 pixels, SCALER_DIP_WIN eWindow)
692 {
693 if( eWindow == DIP_WINDOW )
694 {
695 if (bEnable)
696 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, BIT(1), BIT(1));
697 else
698 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, 0x00 , BIT(1));
699 }
700 else if( eWindow == DWIN0_WINDOW )
701 {
702 if (bEnable)
703 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, BIT(1), BIT(1));
704 else
705 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, 0x00 , BIT(1));
706 }
707 else if( eWindow == DWIN1_WINDOW )
708 {
709 if (bEnable)
710 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, BIT(1), BIT(1));
711 else
712 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, 0x00 , BIT(1));
713 }
714 else
715 {
716 return;
717 }
718 }
719
720 // This function will return 8/10/12/14/16 field mode or 8 frame mode.
721 // Otherwise it return IMAGE_STORE_2_FRAMES
Hal_SC_DWIN_GetFrameStoreMode(void * pInstance,SCALER_DIP_WIN eWindow,MS_BOOL bInterlace)722 XC_FRAME_STORE_NUMBER Hal_SC_DWIN_GetFrameStoreMode(void *pInstance, SCALER_DIP_WIN eWindow,MS_BOOL bInterlace)
723 {
724 if (bInterlace)
725 {
726 return IMAGE_STORE_4_FIELDS;
727 }
728 else
729 {
730 return IMAGE_STORE_2_FRAMES;
731 }
732 }
733
734
Hal_SC_DWIN_EnableR2YCSC(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)735 void Hal_SC_DWIN_EnableR2YCSC(void *pInstance, MS_BOOL bEnable, SCALER_DIP_WIN eWindow)
736 {
737 if( eWindow == DIP_WINDOW )
738 {
739 bDipR2Y = bEnable;
740 if( ((DipSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (DipSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)) && (bDipR2Y == FALSE) )
741 {
742 //enable 422 to 444
743 DIP_W2BYTEMSK(0, REG_SC_BK34_6C_L,BIT(9),BIT(9));
744 //enable source yc swap
745 DIP_W2BYTEMSK(0, REG_SC_BK34_7C_L,BIT(14),BIT(14));
746 }
747 else
748 {
749 //disable 422 to 444
750 DIP_W2BYTEMSK(0, REG_SC_BK34_6C_L,0,BIT(9));
751 //disable source yc swap
752 DIP_W2BYTEMSK(0, REG_SC_BK34_7C_L,0,BIT(14));
753 }
754 DIP_W2BYTEMSK(0, REG_SC_BK34_31_L, (bEnable ? BIT(0):0), BIT(0));
755 }
756 else if( eWindow == DWIN0_WINDOW )
757 {
758 bDwin0R2Y = bEnable;
759 if( ((Dwin0Source == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (Dwin0Source == SCALER_DIP_SOURCE_TYPE_OP_SUB)) && (bDwin0R2Y == FALSE) )
760 {
761 //enable 422 to 444
762 DIP_W2BYTEMSK(0, REG_SC_BK3B_78_L,BIT(9),BIT(9));
763 //enable source yc swap
764 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L,BIT(8),BIT(8));
765 }
766 else
767 {
768 //disable 422 to 444
769 DIP_W2BYTEMSK(0, REG_SC_BK3B_78_L,0,BIT(9));
770 //disable source yc swap
771 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L,0,BIT(8));
772 }
773 DIP_W2BYTEMSK(0, REG_SC_BK3B_45_L, (bEnable ? BIT(0):0), BIT(0));
774 }
775 else if( eWindow == DWIN1_WINDOW )
776 {
777 bDwin1R2Y = bEnable;
778 if( ((Dwin1Source == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (Dwin1Source == SCALER_DIP_SOURCE_TYPE_OP_SUB)) && (bDwin1R2Y == FALSE) )
779 {
780 //enable 422 to 444
781 DIP_W2BYTEMSK(0, REG_SC_BK3C_78_L,BIT(9),BIT(9));
782 //enable source yc swap
783 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L,BIT(8),BIT(8));
784 }
785 else
786 {
787 //disable 422 to 444
788 DIP_W2BYTEMSK(0, REG_SC_BK3C_78_L,0,BIT(9));
789 //disable source yc swap
790 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L,0,BIT(8));
791 }
792 DIP_W2BYTEMSK(0, REG_SC_BK3C_45_L, (bEnable ? BIT(0):0), BIT(0));
793 }
794 else
795 {
796 return;
797 }
798 }
799
Hal_SC_DWIN_Set_vsd_output_line_count(void * pInstance,MS_BOOL bEnable,MS_U32 u32LineCount,SCALER_DIP_WIN eWindow)800 void Hal_SC_DWIN_Set_vsd_output_line_count(void *pInstance, MS_BOOL bEnable,MS_U32 u32LineCount,SCALER_DIP_WIN eWindow)
801 {
802 MS_U16 u16OutputLineCount = 0x00;
803
804 if (bEnable)
805 {
806 u16OutputLineCount = BIT(15);
807 u16OutputLineCount |= (MS_U16)(u32LineCount & 0x1FFF);
808 }
809
810 if (eWindow == DIP_WINDOW)
811 {
812 DIP_W2BYTEMSK(0, REG_SC_BK34_37_L, u16OutputLineCount,0x81FF);
813 }
814 else if( eWindow == DWIN0_WINDOW )
815 {
816 DIP_W2BYTEMSK(0, REG_SC_BK3B_47_L, u16OutputLineCount,0x81FF);
817 }
818 else if( eWindow == DWIN1_WINDOW )
819 {
820 DIP_W2BYTEMSK(0, REG_SC_BK3C_47_L, u16OutputLineCount,0x81FF);
821 }
822 else
823 {
824 return;
825 }
826 }
827
828 /*
829 bEnable : Enable input line count.
830 bUserMode : 1 -> the input line count will ref u32UserLineCount
831 0 -> the input line count will ref V capture win
832 */
Hal_SC_DWIN_Set_vsd_input_line_count(void * pInstance,MS_BOOL bEnable,MS_BOOL bUserMode,MS_U32 u32UserLineCount,SCALER_DIP_WIN eWindow)833 void Hal_SC_DWIN_Set_vsd_input_line_count(void *pInstance, MS_BOOL bEnable,MS_BOOL bUserMode,MS_U32 u32UserLineCount,SCALER_DIP_WIN eWindow)
834 {
835 MS_U16 u16InputLineCount = 0x00;
836
837 if (bEnable)
838 {
839 u16InputLineCount = BIT(15);
840
841 if (bUserMode)
842 {
843 u16InputLineCount |= BIT(14);
844 u16InputLineCount |= (MS_U16)(u32UserLineCount & 0x1FFF);
845 }
846 }
847
848 if (eWindow == DIP_WINDOW)
849 {
850 DIP_W2BYTE(0, REG_SC_BK34_36_L, u16InputLineCount);
851 }
852 else if( eWindow == DWIN0_WINDOW )
853 {
854 DIP_W2BYTE(0, REG_SC_BK3B_46_L, u16InputLineCount);
855 }
856 else if( eWindow == DWIN1_WINDOW )
857 {
858 DIP_W2BYTE(0, REG_SC_BK3C_46_L, u16InputLineCount);
859 }
860 else
861 {
862 return;
863 }
864 }
865
866
Hal_SC_DWIN_sw_db(void * pInstance,P_SC_DIP_SWDB_INFO pDBreg,SCALER_DIP_WIN eWindow)867 void Hal_SC_DWIN_sw_db(void *pInstance, P_SC_DIP_SWDB_INFO pDBreg, SCALER_DIP_WIN eWindow)
868 {
869 if( eWindow == DIP_WINDOW )
870 {
871
872 if( pDBreg->u32H_PreScalingRatio & BIT(31))
873 DIP_W2BYTEMSK(0, REG_SC_BK34_6C_L, BIT(15),BIT(15));
874 else
875 DIP_W2BYTEMSK(0, REG_SC_BK34_6C_L, 0,BIT(15));
876
877 DIP_W4BYTE(0, REG_SC_BK34_2C_L, (pDBreg->u32H_PreScalingRatio & (~(BIT(31))))); // H pre-scaling
878 DIP_W4BYTE(0, REG_SC_BK34_08_L, pDBreg->u32V_PreScalingRatio); // V pre-scaling
879
880 DIP_W2BYTEMSK(0, REG_SC_BK34_60_L, BIT(1)|BIT(0),BIT(1)|BIT(0));
881 DIP_W2BYTE(0, REG_SC_BK34_61_L, pDBreg->u16H_CapStart+1);
882 DIP_W2BYTE(0, REG_SC_BK34_62_L, pDBreg->u16H_CapStart+pDBreg->u16H_CapSize);
883 DIP_W2BYTE(0, REG_SC_BK34_63_L, pDBreg->u16V_CapStart+1);
884 DIP_W2BYTE(0, REG_SC_BK34_64_L, pDBreg->u16V_CapStart+pDBreg->u16V_CapSize);
885 DipSrcWidth = pDBreg->u16H_CapStart + pDBreg->u16H_CapSize;
886 }
887 else if( eWindow == DWIN0_WINDOW )
888 {
889 if( pDBreg->u32H_PreScalingRatio & BIT(31))
890 DIP_W2BYTEMSK(0, REG_SC_BK3B_78_L, BIT(15),BIT(15));
891 else
892 DIP_W2BYTEMSK(0, REG_SC_BK3B_78_L, 0,BIT(15));
893
894 DIP_W4BYTE(0, REG_SC_BK3B_37_L, (pDBreg->u32H_PreScalingRatio & (~(BIT(31))))); // H pre-scaling
895 DIP_W4BYTE(0, REG_SC_BK3B_1B_L, pDBreg->u32V_PreScalingRatio); // V pre-scaling
896
897 DIP_W2BYTEMSK(0, REG_SC_BK3B_62_L, BIT(1)|BIT(0),BIT(1)|BIT(0));
898 DIP_W2BYTE(0, REG_SC_BK3B_63_L, pDBreg->u16H_CapStart+1);
899 DIP_W2BYTE(0, REG_SC_BK3B_64_L, pDBreg->u16H_CapStart+pDBreg->u16H_CapSize);
900 DIP_W2BYTE(0, REG_SC_BK3B_65_L, pDBreg->u16V_CapStart+1);
901 DIP_W2BYTE(0, REG_SC_BK3B_66_L, pDBreg->u16V_CapStart+pDBreg->u16V_CapSize);
902 Dwin0SrcWidth = pDBreg->u16H_CapStart + pDBreg->u16H_CapSize;
903 }
904 else if( eWindow == DWIN1_WINDOW )
905 {
906 if( pDBreg->u32H_PreScalingRatio & BIT(31))
907 DIP_W2BYTEMSK(0, REG_SC_BK3C_78_L, BIT(15),BIT(15));
908 else
909 DIP_W2BYTEMSK(0, REG_SC_BK3C_78_L, 0,BIT(15));
910
911 DIP_W4BYTE(0, REG_SC_BK3C_37_L, (pDBreg->u32H_PreScalingRatio & (~(BIT(31))))); // H pre-scaling
912 DIP_W4BYTE(0, REG_SC_BK3C_1B_L, pDBreg->u32V_PreScalingRatio); // V pre-scaling
913
914 DIP_W2BYTEMSK(0, REG_SC_BK3C_62_L, BIT(1)|BIT(0),BIT(1)|BIT(0));
915 DIP_W2BYTE(0, REG_SC_BK3C_63_L, pDBreg->u16H_CapStart+1);
916 DIP_W2BYTE(0, REG_SC_BK3C_64_L, pDBreg->u16H_CapStart+pDBreg->u16H_CapSize);
917 DIP_W2BYTE(0, REG_SC_BK3C_65_L, pDBreg->u16V_CapStart+1);
918 DIP_W2BYTE(0, REG_SC_BK3C_66_L, pDBreg->u16V_CapStart+pDBreg->u16V_CapSize);
919 Dwin1SrcWidth = pDBreg->u16H_CapStart + pDBreg->u16H_CapSize;
920 }
921 else
922 {
923 return;
924 }
925 }
Hal_SC_DWIN_get_sw_db(void * pInstance,P_SC_DIP_SWDB_INFO pDBreg,SCALER_DIP_WIN eWindow)926 void Hal_SC_DWIN_get_sw_db(void *pInstance, P_SC_DIP_SWDB_INFO pDBreg, SCALER_DIP_WIN eWindow)
927 {
928 if( eWindow == DIP_WINDOW )
929 {
930 pDBreg->u32H_PreScalingRatio = DIP_R4BYTE(0, REG_SC_BK34_2C_L,eWindow);
931 if( DIP_R2BYTE(0, REG_SC_BK34_6C_L,eWindow) & BIT(15) )
932 pDBreg->u32H_PreScalingRatio |= BIT(31);
933 pDBreg->u32V_PreScalingRatio = DIP_R4BYTE(0, REG_SC_BK34_08_L,eWindow);
934
935 pDBreg->u16H_CapStart = (DIP_R2BYTE(0, REG_SC_BK34_61_L,eWindow) - 1);
936 pDBreg->u16H_CapSize = (DIP_R2BYTE(0, REG_SC_BK34_62_L,eWindow) - pDBreg->u16H_CapStart);
937 pDBreg->u16V_CapStart = (DIP_R2BYTE(0, REG_SC_BK34_63_L,eWindow) - 1);
938 pDBreg->u16V_CapSize = (DIP_R2BYTE(0, REG_SC_BK34_64_L,eWindow) - pDBreg->u16V_CapStart);
939 }
940 else if( eWindow == DWIN0_WINDOW )
941 {
942 pDBreg->u32H_PreScalingRatio = DIP_R4BYTE(0, REG_SC_BK3B_37_L,eWindow);
943 if( DIP_R2BYTE(0, REG_SC_BK3B_78_L,eWindow) & BIT(15) )
944 pDBreg->u32H_PreScalingRatio |= BIT(31);
945 pDBreg->u32V_PreScalingRatio = DIP_R4BYTE(0, REG_SC_BK3B_1B_L,eWindow);
946
947 pDBreg->u16H_CapStart = (DIP_R2BYTE(0, REG_SC_BK3B_63_L,eWindow) - 1);
948 pDBreg->u16H_CapSize = (DIP_R2BYTE(0, REG_SC_BK3B_64_L,eWindow) - pDBreg->u16H_CapStart);
949 pDBreg->u16V_CapStart = (DIP_R2BYTE(0, REG_SC_BK3B_65_L,eWindow) - 1);
950 pDBreg->u16V_CapSize = (DIP_R2BYTE(0, REG_SC_BK3B_66_L,eWindow) - pDBreg->u16V_CapStart);
951 }
952 else if( eWindow == DWIN1_WINDOW )
953 {
954 pDBreg->u32H_PreScalingRatio = DIP_R4BYTE(0, REG_SC_BK3C_37_L,eWindow);
955 if( DIP_R2BYTE(0, REG_SC_BK3C_78_L,eWindow) & BIT(15) )
956 pDBreg->u32H_PreScalingRatio |= BIT(31);
957 pDBreg->u32V_PreScalingRatio = DIP_R4BYTE(0, REG_SC_BK3C_1B_L,eWindow);
958
959 pDBreg->u16H_CapStart = (DIP_R2BYTE(0, REG_SC_BK3C_63_L,eWindow) - 1);
960 pDBreg->u16H_CapSize = (DIP_R2BYTE(0, REG_SC_BK3C_64_L,eWindow) - pDBreg->u16H_CapStart);
961 pDBreg->u16V_CapStart = (DIP_R2BYTE(0, REG_SC_BK3C_65_L,eWindow) - 1);
962 pDBreg->u16V_CapSize = (DIP_R2BYTE(0, REG_SC_BK3C_66_L,eWindow) - pDBreg->u16V_CapStart);
963 }
964 else
965 {
966 return;
967 }
968 }
HAL_XC_DIP_Set444to422(void * pInstance,EN_DRV_XC_DWIN_DATA_FMT fmt,MS_BOOL bSrcYUVFmt,MS_BOOL bSrcFmt422,SCALER_DIP_WIN eWindow)969 void HAL_XC_DIP_Set444to422(void *pInstance, EN_DRV_XC_DWIN_DATA_FMT fmt,MS_BOOL bSrcYUVFmt,MS_BOOL bSrcFmt422,SCALER_DIP_WIN eWindow)
970 {
971
972 }
HAL_XC_DIP_SetFRC(void * pInstance,MS_BOOL bEnable,MS_U16 u16In,MS_U16 u16Out,SCALER_DIP_WIN eWindow)973 void HAL_XC_DIP_SetFRC(void *pInstance, MS_BOOL bEnable,MS_U16 u16In,MS_U16 u16Out,SCALER_DIP_WIN eWindow)
974 {
975 MS_U16 u16Ratio=0;
976 MS_U64 u64_result = 0;
977
978 if( eWindow == DIP_WINDOW )
979 {
980 if(bEnable)
981 {
982 if(u16In > u16Out)
983 {
984 u64_result = (u16In-u16Out)*64;
985 do_div(u64_result,u16In);
986 u16Ratio = u64_result;
987 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,u16Ratio,BMASK(5:0));
988 }
989 else
990 {
991 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0));
992 }
993 }
994 else
995 {
996 DIP_W2BYTEMSK(0, REG_SC_BK34_40_L,0,BMASK(5:0));
997 }
998 }
999 else if( eWindow == DWIN0_WINDOW )
1000 {
1001 if(bEnable)
1002 {
1003 if(u16In > u16Out)
1004 {
1005 u64_result = (u16In-u16Out)*64;
1006 do_div(u64_result,u16In);
1007 u16Ratio = u64_result;
1008 DIP_W2BYTEMSK(0, REG_SC_BK3B_4D_L,u16Ratio,BMASK(5:0));
1009 }
1010 else
1011 {
1012 DIP_W2BYTEMSK(0, REG_SC_BK3B_4D_L,0,BMASK(5:0));
1013 }
1014 }
1015 else
1016 {
1017 DIP_W2BYTEMSK(0, REG_SC_BK3B_4D_L,0,BMASK(5:0));
1018 }
1019 }
1020 else if( eWindow == DWIN1_WINDOW )
1021 {
1022 if(bEnable)
1023 {
1024 if(u16In > u16Out)
1025 {
1026 u64_result = (u16In-u16Out)*64;
1027 do_div(u64_result,u16In);
1028 u16Ratio = u64_result;
1029 DIP_W2BYTEMSK(0, REG_SC_BK3C_4D_L,u16Ratio,BMASK(5:0));
1030 }
1031 else
1032 {
1033 DIP_W2BYTEMSK(0, REG_SC_BK3C_4D_L,0,BMASK(5:0));
1034 }
1035 }
1036 else
1037 {
1038 DIP_W2BYTEMSK(0, REG_SC_BK3C_4D_L,0,BMASK(5:0));
1039 }
1040 }
1041 else
1042 {
1043 return;
1044 }
1045
1046 }
Hal_SC_DWIN_set_input_vsync_inverse(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)1047 void Hal_SC_DWIN_set_input_vsync_inverse(void *pInstance, MS_BOOL bEnable, SCALER_DIP_WIN eWindow)
1048 {
1049 if( eWindow == DIP_WINDOW )
1050 {
1051 DIP_W2BYTEMSK(0, REG_SC_BK34_01_L, (bEnable<<2), BIT(2) );
1052 }
1053 else if( eWindow == DWIN0_WINDOW )
1054 {
1055 DIP_W2BYTEMSK(0, REG_SC_BK3B_12_L, (bEnable<<2), BIT(2) );
1056 }
1057 else if( eWindow == DWIN1_WINDOW )
1058 {
1059 DIP_W2BYTEMSK(0, REG_SC_BK3C_12_L, (bEnable<<2), BIT(2) );
1060 }
1061 else
1062 {
1063 return;
1064 }
1065 }
1066
1067 //=============== DIP =====================//
1068 #define DWIN_CAPTURE_TIMEOUT_CNT 10 //consider 576i video, maximum time is 20+20x2 = 60 ms
1069
HAL_XC_DIP_GetBusSize(void * pInstance,SCALER_DIP_WIN eWindow)1070 MS_U16 HAL_XC_DIP_GetBusSize(void *pInstance, SCALER_DIP_WIN eWindow)
1071 {
1072 if( eWindow == DIP_WINDOW )
1073 {
1074 return DWIN_BYTE_PER_WORD;
1075 }
1076 else if( eWindow == DWIN0_WINDOW )
1077 {
1078 return DWIN_BYTE_PER_WORD;
1079 }
1080 else if( eWindow == DWIN1_WINDOW )
1081 {
1082 return DWIN_BYTE_PER_WORD;
1083 }
1084 else
1085 {
1086 return 0xFF;
1087 }
1088 }
1089
HAL_XC_DIP_SWReset(void * pInstance,SCALER_DIP_WIN eWindow)1090 void HAL_XC_DIP_SWReset(void *pInstance, SCALER_DIP_WIN eWindow)
1091 {
1092 if( eWindow == DIP_WINDOW )
1093 {
1094 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L,BIT(0), BIT(0));
1095 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L,0, BIT(0));
1096 }
1097 else if( eWindow == DWIN0_WINDOW )
1098 {
1099 DIP_W2BYTEMSK(0, REG_SC_BK3B_73_L,BIT(0), BIT(0));
1100 DIP_W2BYTEMSK(0, REG_SC_BK3B_73_L,0, BIT(0));
1101 }
1102 else if( eWindow == DWIN1_WINDOW )
1103 {
1104 DIP_W2BYTEMSK(0, REG_SC_BK3C_73_L,BIT(0), BIT(0));
1105 DIP_W2BYTEMSK(0, REG_SC_BK3C_73_L,0, BIT(0));
1106 }
1107 else
1108 {
1109 return;
1110 }
1111 }
1112
HAL_XC_DIP_Init(void * pInstance,SCALER_DIP_WIN eWindow)1113 void HAL_XC_DIP_Init(void *pInstance, SCALER_DIP_WIN eWindow)
1114 {
1115 if( eWindow == DIP_WINDOW )
1116 {
1117 //[15]intlac. src;[12:8]422to420 ratio;[6]dwin_en;[5:4]format(rgb888);[3]intlac_w;[2:0]frm_buf_num
1118 DIP_W2BYTE(0, REG_SC_BK36_01_L,0x0840);
1119 // [10]pdw_off;[9:8] reg_dip_pdw_src_sel;[7:0]alpha
1120 DIP_W2BYTE(0, REG_SC_BK36_02_L,0x0400);
1121 //[8] write once; [9] write once trig
1122 if(HAL_XC_DIP_GetBusSize(pInstance,eWindow) == DIP_BYTE_PER_WORD)
1123 DIP_W2BYTE(0, REG_SC_BK36_03_L,0x0000);
1124 else
1125 DIP_W2BYTE(0, REG_SC_BK36_03_L,0x0800);
1126 //When dip overstep memory next to dip,dip won't stop telling this wrong state with continuous interrupt.
1127 //The continuous interrupt will cause the high cpu possesion.
1128 //So we mask the related bit to ignore the wrong state.
1129 //Function HAL_XC_MIU_Protect will protect the memory next to dip being overstepped by dip in case "MIU_PROTECT == 1".
1130 DIP_W2BYTEMSK(0, REG_SC_BK36_04_L, BIT(4),BIT(4));
1131 //clear mirror state
1132 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L, 0 ,BIT(9));
1133 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L, 0 ,BIT(10));
1134 //[15:8]wreq max ; [7:0]wreq threshold
1135 DIP_W2BYTE(0, REG_SC_BK36_6F_L,0x200A);
1136 //tile request number
1137 DIP_W2BYTE(0, REG_SC_BK36_7E_L,0x0010);
1138 //Double buffer enable
1139 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,BIT(0),BIT(0));
1140 DIP_W2BYTEMSK(0, REG_SC_BK36_7F_L,BIT(7),BIT(7));
1141 //enable dip clk
1142 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_INVERT); // Not Invert
1143 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Disable clock
1144
1145 //enable OSD blending
1146 DIP_W2BYTEMSK(0, REG_SC_BK34_10_L, BIT(0) ,BIT(0));
1147
1148 //TEE clip
1149 DIP_W2BYTEMSK(0, REG_SC_BK34_0F_L,0x1000,BMASK(12:0));
1150 DIP_W2BYTEMSK(0, REG_SC_BK34_2F_L,0x1000,BMASK(12:0));
1151
1152 DIP_W2BYTEMSK(0, REG_SC_BK36_38_L,0xff, BMASK(7:0));
1153 DIP_W2BYTEMSK(0, REG_SC_BK36_48_L,0xff, BMASK(7:0));
1154
1155 #ifdef CONFIG_MSTAR_SRAMPD
1156 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4));
1157 #endif
1158 }
1159 else if( eWindow == DWIN0_WINDOW )
1160 {
1161 //[15]intlac. src;[12:8]422to420 ratio;[6]dwin_en;[5:4]format(rgb888);[3]intlac_w;[2:0]frm_buf_num
1162 DIP_W2BYTE(0, REG_SC_BK3B_01_L,0x0840);
1163 // [10]pdw_off;[9:8] reg_dip_pdw_src_sel;[7:0]alpha
1164 DIP_W2BYTE(0, REG_SC_BK3B_02_L,0x0400);
1165 //[8] write once; [9] write once trig[11]256mode
1166 if(HAL_XC_DIP_GetBusSize(pInstance,eWindow) == DIP_BYTE_PER_WORD)
1167 DIP_W2BYTE(0, REG_SC_BK3B_03_L,0x0000);
1168 else
1169 DIP_W2BYTE(0, REG_SC_BK3B_03_L,0x0800);
1170 //When dip overstep memory next to dip,dip won't stop telling this wrong state with continuous interrupt.
1171 //The continuous interrupt will cause the high cpu possesion.
1172 //So we mask the related bit to ignore the wrong state.
1173 //Function HAL_XC_MIU_Protect will protect the memory next to dip being overstepped by dip in case "MIU_PROTECT == 1".
1174 DIP_W2BYTEMSK(0, REG_SC_BK3B_04_L, BIT(4),BIT(4));
1175 //clear mirror state
1176 DIP_W2BYTEMSK(0, REG_SC_BK3B_0B_L, 0 ,BIT(9));
1177 DIP_W2BYTEMSK(0, REG_SC_BK3B_0B_L, 0 ,BIT(10));
1178 //[15:8]wreq max ; [7:0]wreq threshold
1179 DIP_W2BYTE(0, REG_SC_BK3B_6F_L,0x200A);
1180 //tile request number
1181 DIP_W2BYTE(0, REG_SC_BK3B_7E_L,0x0010);
1182 //Double buffer enable
1183 DIP_W2BYTEMSK(0, REG_SC_BK3B_72_L,BIT(0),BIT(0));
1184 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L,BIT(7),BIT(7));
1185 //set OP capture E_XC_DIP_VOP2/E_XC_DIP_OP2
1186 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, 2<<4, BMASK(5:4));
1187 //enable dwin0 clk
1188 MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_INVERT); // Not Invert
1189 MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable clock
1190
1191 //TEE clip
1192 DIP_W2BYTEMSK(0, REG_SC_BK3B_0D_L,0x1000,BMASK(12:0));
1193 DIP_W2BYTEMSK(0, REG_SC_BK3B_1E_L,0x1000,BMASK(12:0));
1194
1195 #ifdef CONFIG_MSTAR_SRAMPD
1196 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, BMASK(3:0) , BMASK(3:0));
1197 #endif
1198
1199 }
1200 else if( eWindow == DWIN1_WINDOW )
1201 {
1202 //[15]intlac. src;[12:8]422to420 ratio;[6]dwin_en;[5:4]format(rgb888);[3]intlac_w;[2:0]frm_buf_num
1203 DIP_W2BYTE(0, REG_SC_BK3C_01_L,0x0840);
1204 // [10]pdw_off;[9:8] reg_dip_pdw_src_sel;[7:0]alpha
1205 DIP_W2BYTE(0, REG_SC_BK3C_02_L,0x0400);
1206 //[8] write once; [9] write once trig[11]256mode
1207 if(HAL_XC_DIP_GetBusSize(pInstance,eWindow) == DIP_BYTE_PER_WORD)
1208 DIP_W2BYTE(0, REG_SC_BK3C_03_L,0x0000);
1209 else
1210 DIP_W2BYTE(0, REG_SC_BK3C_03_L,0x0800);
1211 //When dip overstep memory next to dip,dip won't stop telling this wrong state with continuous interrupt.
1212 //The continuous interrupt will cause the high cpu possesion.
1213 //So we mask the related bit to ignore the wrong state.
1214 //Function HAL_XC_MIU_Protect will protect the memory next to dip being overstepped by dip in case "MIU_PROTECT == 1".
1215 DIP_W2BYTEMSK(0, REG_SC_BK3C_04_L, BIT(4),BIT(4));
1216 //clear mirror state
1217 DIP_W2BYTEMSK(0, REG_SC_BK3C_0B_L, 0 ,BIT(9));
1218 DIP_W2BYTEMSK(0, REG_SC_BK3C_0B_L, 0 ,BIT(10));
1219 //[15:8]wreq max ; [7:0]wreq threshold
1220 DIP_W2BYTE(0, REG_SC_BK3C_6F_L,0x200A);
1221 //tile request number
1222 DIP_W2BYTE(0, REG_SC_BK3C_7E_L,0x0010);
1223 //Double buffer enable
1224 DIP_W2BYTEMSK(0, REG_SC_BK3C_72_L,BIT(0),BIT(0));
1225 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L,BIT(7),BIT(7));
1226 //set OP capture E_XC_DIP_VOP2/E_XC_DIP_OP2
1227 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, 2<<4, BMASK(5:4));
1228 //enable dwin1 clk
1229 MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_INVERT); // Not Invert
1230 MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable clock
1231
1232 //TEE clip
1233 DIP_W2BYTEMSK(0, REG_SC_BK3B_0D_L,0x1000,BMASK(12:0));
1234 DIP_W2BYTEMSK(0, REG_SC_BK3B_1E_L,0x1000,BMASK(12:0));
1235
1236 #ifdef CONFIG_MSTAR_SRAMPD
1237 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, BMASK(3:0) , BMASK(3:0));
1238 #endif
1239
1240 }
1241 DIP_W2BYTEMSK(0, REG_SC_BK36_1C_L, 0 ,BIT(14));
1242
1243 //force OP1 ACK 1
1244 //DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L,BIT(1),BIT(1));
1245 //for DIP R
1246 //read request maximum length and 2������, tile 420 used
1247 DIP_W2BYTE(0, REG_SC_BK36_7F_L,0x400F);
1248 //read request threshold
1249 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L,0xA,BMASK(5:0));
1250 //reg_dipr_tile_req_num_evd
1251 DIP_W2BYTEMSK(0, REG_SC_BK36_1C_L,0x7,BMASK(4:0));
1252
1253 //output capture setting
1254 DIP_W2BYTEMSK(0, REG_SC_BK10_23_L, BIT(4), BIT(4)); // Set to no osd for DIP select
1255 DIP_W2BYTEMSK(0, REG_SC_BK10_23_L, E_XC_DIP_VOP2<<12, BMASK(13:12));
1256 DIP_W2BYTEMSK(0, REG_SC_BK10_50_L, BIT(14), BMASK(14:13));
1257
1258 DIP_W2BYTEMSK(0, REG_SC_BK10_50_L, BIT(12), BIT(12)); // Set to with osd for DIP select
1259 DIP_W2BYTEMSK(0, REG_SC_BK10_50_L, E_XC_DIP_OP2<<8, BMASK(9:8));
1260 DIP_W2BYTEMSK(0, REG_SC_BK10_6B_L, BIT(13), BMASK(13:12));
1261
1262 //recv2dip_cap_en_main
1263 DIP_W2BYTEMSK(0, REG_SC_BK4A_05_L, BIT(1), BIT(1));
1264 //recv2dip_cap_en_sub
1265 DIP_W2BYTEMSK(0, REG_SC_BK4A_04_L, BIT(1), BIT(1));
1266
1267 //Sc2 op capture enable:
1268 DIP_W2BYTEMSK(0, REG_SC_BK90_50_L, BIT(12), BIT(12));
1269 //Sc2 op capture stage 0: before osdb 1: after osdb
1270 DIP_W2BYTEMSK(0, REG_SC_BK90_50_L, E_XC_DIP_OP2<<8, BMASK(9:8));// Set to with osd for DIP select
1271 }
1272
HAL_XC_DIP_EnableCaptureStream(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)1273 void HAL_XC_DIP_EnableCaptureStream(void *pInstance, MS_BOOL bEnable,SCALER_DIP_WIN eWindow)
1274 {
1275 MS_U16 u16IntrStus = 0;
1276 MS_XC_DIP_SOURCE_TYPE eHalSource;
1277 SCALER_DIP_SOURCE_TYPE eWindowSource = SCALER_DIP_SOURCE_TYPE_MAIN;
1278
1279 if( eWindow == DIP_WINDOW )
1280 {
1281 eWindowSource = DipSource;
1282 #ifdef CONFIG_MSTAR_SRAMPD
1283 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4));
1284 #endif
1285 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock
1286 }
1287 else if( eWindow == DWIN0_WINDOW )
1288 {
1289 eWindowSource = Dwin0Source;
1290 #ifdef CONFIG_MSTAR_SRAMPD
1291 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, 0 , BMASK(3:0));
1292 #endif
1293 MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock
1294 }
1295 else if( eWindow == DWIN1_WINDOW )
1296 {
1297 eWindowSource = Dwin1Source;
1298 #ifdef CONFIG_MSTAR_SRAMPD
1299 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, 0 , BMASK(3:0));
1300 #endif
1301 MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock
1302 }
1303
1304 switch(eWindowSource)
1305 {
1306 case SCALER_DIP_SOURCE_TYPE_DRAM:
1307 case SCALER_DIP_SOURCE_TYPE_SUB2 :
1308 case SCALER_DIP_SOURCE_TYPE_OP_CAPTURE:
1309 case SCALER_DIP_SOURCE_TYPE_SC2_OP_CAPTURE:
1310 case SCALER_DIP_SOURCE_TYPE_OSD:
1311 eHalSource = E_XC_DIP_SOURCE_TYPE_SUB2;
1312 break;
1313 case SCALER_DIP_SOURCE_TYPE_MAIN :
1314 eHalSource = E_XC_DIP_SOURCE_TYPE_MAIN;
1315 break;
1316 case SCALER_DIP_SOURCE_TYPE_SUB :
1317 eHalSource = E_XC_DIP_SOURCE_TYPE_MAIN;
1318 break;
1319 case SCALER_DIP_SOURCE_TYPE_OP_MAIN:
1320 case SCALER_DIP_SOURCE_TYPE_OP_SUB:
1321 eHalSource = E_XC_DIP_SOURCE_TYPE_OP;
1322 break;
1323 default:
1324 DIP_H_ERR("SCALER_DIP_SOURCE_TYPE does not support\n");
1325 return;
1326 }
1327
1328
1329 if(bEnable == TRUE)
1330 {
1331 //Control DIPR
1332 if(eWindowSource == SCALER_DIP_SOURCE_TYPE_DRAM)
1333 {
1334 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L,BIT(14), BIT(14));
1335 }
1336 else if( (eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_SUB) )
1337 {
1338 if( eWindow == DIP_WINDOW )
1339 {
1340 DIP_W2BYTEMSK(0, REG_SC_BK34_7C_L,((eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)?BIT(15):0),BIT(15));
1341 }
1342 else if( eWindow == DWIN0_WINDOW )
1343 {
1344 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, ((eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)?BIT(6):0),BIT(6));
1345 }
1346 else if( eWindow == DWIN1_WINDOW )
1347 {
1348 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, ((eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)?BIT(6):0),BIT(6));
1349 }
1350 }
1351 //new rotation enabel
1352 DIP_W2BYTEMSK(0, REG_SC_BK34_6E_L,bDIPRotation?BIT(11):0,BIT(11));
1353 //Enable last
1354 if( eWindow == DIP_WINDOW )
1355 {
1356 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, BITS(9:8,eHalSource),BMASK(10:8));
1357 }
1358 else if( eWindow == DWIN0_WINDOW )
1359 {
1360 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, BITS(9:8,eHalSource),BMASK(10:8));
1361 }
1362 else if( eWindow == DWIN1_WINDOW )
1363 {
1364 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, BITS(9:8,eHalSource),BMASK(10:8));
1365 }
1366 }
1367 else
1368 {
1369 //new rotation disable
1370 DIP_W2BYTEMSK(0, REG_SC_BK34_6E_L,0,BIT(11));
1371 //Disable first
1372 if( eWindow == DIP_WINDOW )
1373 {
1374 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, BIT(10), BMASK(10:8));
1375 //disable write once
1376 DIP_W2BYTEMSK(0, REG_SC_BK36_03_L, 0, BIT(8));
1377 }
1378 else if( eWindow == DWIN0_WINDOW )
1379 {
1380 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, BIT(10), BMASK(10:8));
1381 //disable write once
1382 DIP_W2BYTEMSK(0, REG_SC_BK3B_03_L, 0, BIT(8));
1383 }
1384 else if( eWindow == DWIN1_WINDOW )
1385 {
1386 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, BIT(10), BMASK(10:8));
1387 //disable write once
1388 DIP_W2BYTEMSK(0, REG_SC_BK3C_03_L, 0, BIT(8));
1389 }
1390
1391 if(eWindowSource == SCALER_DIP_SOURCE_TYPE_DRAM)
1392 {
1393 //Dipr disable
1394 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L,0, BIT(14));
1395 }
1396 }
1397
1398
1399 if (!bEnable)
1400 {
1401 //Auto clear status to zero
1402 u16IntrStus = HAL_XC_DIP_GetIntrStatus(pInstance, eWindow);
1403 HAL_XC_DIP_ClearIntr(pInstance, u16IntrStus,eWindow);
1404 HAL_XC_DIP_SWReset(pInstance, eWindow);
1405 }
1406 }
HAL_XC_DIP_EnableIntr(void * pInstance,MS_U16 u8mask,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)1407 void HAL_XC_DIP_EnableIntr(void *pInstance, MS_U16 u8mask, MS_BOOL bEnable,SCALER_DIP_WIN eWindow)
1408 {
1409 MS_U16 regval =0;
1410
1411 if( eWindow == DIP_WINDOW )
1412 {
1413 regval = DIP_R2BYTE(0, REG_SC_BK36_08_L,eWindow);
1414 }
1415 else if( eWindow == DWIN0_WINDOW )
1416 {
1417 regval = DIP_R2BYTE(0, REG_SC_BK3B_08_L,eWindow);
1418 }
1419 else if( eWindow == DWIN1_WINDOW )
1420 {
1421 regval = DIP_R2BYTE(0, REG_SC_BK3C_08_L,eWindow);
1422 }
1423
1424 if(bEnable)
1425 regval &= ~u8mask;
1426 else
1427 regval |= u8mask;
1428
1429 DIP_W2BYTEMSK(0, REG_SC_BK36_08_L, regval, BMASK(7:0));
1430 }
HAL_XC_DIP_ClearIntr(void * pInstance,MS_U16 u16mask,SCALER_DIP_WIN eWindow)1431 void HAL_XC_DIP_ClearIntr(void *pInstance, MS_U16 u16mask,SCALER_DIP_WIN eWindow)
1432 {
1433 MS_U16 regval =0;
1434
1435 if( eWindow == DIP_WINDOW )
1436 {
1437 SC_W2BYTEMSK(0, REG_SC_BK36_09_L,u16mask&BMASK(7:0), BMASK(7:0));
1438 regval = DIP_R2BYTE(0, REG_SC_BK36_03_L,eWindow);
1439 //only disable in capture one frame mode, cant disable in continous mode
1440 if((regval&BIT(8)) != 0)
1441 {
1442 #ifdef CONFIG_MSTAR_SRAMPD
1443 SC_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4));
1444 #endif
1445 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Disable clock
1446 }
1447 }
1448 else if( eWindow == DWIN0_WINDOW )
1449 {
1450 SC_W2BYTEMSK(0, REG_SC_BK3B_09_L,u16mask&BMASK(7:0), BMASK(7:0));
1451 regval = DIP_R2BYTE(0, REG_SC_BK3B_03_L,eWindow);
1452 //only disable in capture one frame mode, cant disable in continous mode
1453 if((regval&BIT(8)) != 0)
1454 {
1455 #ifdef CONFIG_MSTAR_SRAMPD
1456 SC_W2BYTEMSK(0, REG_SC_BK3B_7F_L, BMASK(3:0) , BMASK(3:0));
1457 #endif
1458 MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable clock
1459 }
1460 }
1461 else if( eWindow == DWIN1_WINDOW )
1462 {
1463 SC_W2BYTEMSK(0, REG_SC_BK3C_09_L,u16mask&BMASK(7:0), BMASK(7:0));
1464 regval = DIP_R2BYTE(0, REG_SC_BK3C_03_L,eWindow);
1465 //only disable in capture one frame mode, cant disable in continous mode
1466 if((regval&BIT(8)) != 0)
1467 {
1468 #ifdef CONFIG_MSTAR_SRAMPD
1469 SC_W2BYTEMSK(0, REG_SC_BK3C_7F_L, BMASK(3:0) , BMASK(3:0));
1470 #endif
1471 MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable clock
1472 }
1473 }
1474 else
1475 {
1476 return;
1477 }
1478
1479 }
HAL_XC_DIP_GetIntrStatus(void * pInstance,SCALER_DIP_WIN eWindow)1480 MS_U16 HAL_XC_DIP_GetIntrStatus(void *pInstance, SCALER_DIP_WIN eWindow)
1481 {
1482 MS_U16 u16IntrStus = 0;
1483 if( eWindow == DIP_WINDOW )
1484 {
1485 if(cmdq_wait_value != cmdq_ready_value)
1486 {
1487 cmdq_wait_value = MDrv_DIP_Read2Byte(g_u32Wait_Reg[eWindow]);
1488 #if 0
1489 MS_U32 timer1,timer2;
1490
1491 timer1 = MsOS_GetSystemTime();
1492 timer2 = MsOS_GetSystemTime();
1493 while( (cmdq_wait_value != cmdq_ready_value) && ((timer2 - timer1)<100))
1494 {
1495 cmdq_wait_value = MDrv_DIP_Read2Byte(g_u32Wait_Reg[eWindow]);
1496 MsOS_DelayTask(1);
1497 timer2 = MsOS_GetSystemTime();
1498 }
1499
1500 if(cmdq_wait_value != cmdq_ready_value)
1501 {
1502 DIP_H_ERR("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),cmdq_wait_value,cmdq_ready_value);
1503 }
1504 #endif
1505 if (cmdq_wait_value == cmdq_ready_value)
1506 {
1507 u16IntrStus = SC_R2BYTEMSK(0, REG_SC_BK36_0A_L,BMASK(7:0));
1508 }
1509 }
1510 else
1511 {
1512 u16IntrStus = SC_R2BYTEMSK(0, REG_SC_BK36_0A_L,BMASK(7:0));
1513 }
1514 }
1515 else if( eWindow == DWIN0_WINDOW )
1516 {
1517 u16IntrStus = SC_R2BYTEMSK(0, REG_SC_BK3B_0A_L,BMASK(7:0));
1518 }
1519 else if( eWindow == DWIN1_WINDOW )
1520 {
1521 u16IntrStus = SC_R2BYTEMSK(0, REG_SC_BK3C_0A_L,BMASK(7:0));
1522 }
1523
1524 return u16IntrStus;
1525 }
HAL_XC_DIP_CpatureOneFrame(void * pInstance,SCALER_DIP_WIN eWindow)1526 void HAL_XC_DIP_CpatureOneFrame(void *pInstance, SCALER_DIP_WIN eWindow)//MS_BOOL benable, SCALER_DIP_WIN eWindow)
1527 {
1528 MS_U16 regval = 0;
1529 MS_U16 u16Count = 0;
1530
1531 HAL_XC_DIP_CpatureOneFrame2(pInstance, eWindow);
1532
1533 do{
1534 regval = HAL_XC_DIP_GetIntrStatus(pInstance, eWindow);
1535 if(regval > 0x0)
1536 break;
1537 u16Count++;
1538 MsOS_DelayTask(1);
1539 }while(u16Count < DWIN_CAPTURE_TIMEOUT_CNT);
1540 //if(u16Count >= DWIN_CAPTURE_TIMEOUT_CNT)
1541 // DIP_H_ERR("!!!Alert !!! DWIN Capture, wait ack time out!\n");
1542
1543 }
HAL_XC_DIP_CpatureOneFrame2(void * pInstance,SCALER_DIP_WIN eWindow)1544 void HAL_XC_DIP_CpatureOneFrame2(void *pInstance, SCALER_DIP_WIN eWindow)//MS_BOOL benable, SCALER_DIP_WIN eWindow)
1545 {
1546 MS_XC_DIP_SOURCE_TYPE eHalSource;
1547 SCALER_DIP_SOURCE_TYPE eWindowSource = SCALER_DIP_SOURCE_TYPE_MAIN;
1548
1549 if( eWindow == DIP_WINDOW )
1550 {
1551 eWindowSource = DipSource;
1552 #ifdef CONFIG_MSTAR_SRAMPD
1553 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, 0 , BMASK(7:4));
1554 #endif
1555 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, DISABLE, CKG_IDCLK3_GATED); // Enable clock
1556 }
1557 else if( eWindow == DWIN0_WINDOW )
1558 {
1559 eWindowSource = Dwin0Source;
1560 #ifdef CONFIG_MSTAR_SRAMPD
1561 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, 0 , BMASK(3:0));
1562 #endif
1563 MDrv_DIP_WriteRegBit(REG_CKG_PDW0, DISABLE, CKG_PDW0_GATED); // Enable clock
1564 }
1565 else if( eWindow == DWIN1_WINDOW )
1566 {
1567 eWindowSource = Dwin1Source;
1568 #ifdef CONFIG_MSTAR_SRAMPD
1569 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, 0 , BMASK(3:0));
1570 #endif
1571 MDrv_DIP_WriteRegBit(REG_CKG_PDW1, DISABLE, CKG_PDW1_GATED); // Enable clock
1572 }
1573
1574 switch(eWindowSource)
1575 {
1576 case SCALER_DIP_SOURCE_TYPE_DRAM:
1577 case SCALER_DIP_SOURCE_TYPE_SUB2 :
1578 case SCALER_DIP_SOURCE_TYPE_OP_CAPTURE:
1579 case SCALER_DIP_SOURCE_TYPE_SC2_OP_CAPTURE:
1580 case SCALER_DIP_SOURCE_TYPE_OSD:
1581 eHalSource = E_XC_DIP_SOURCE_TYPE_SUB2;
1582 break;
1583 case SCALER_DIP_SOURCE_TYPE_MAIN :
1584 eHalSource = E_XC_DIP_SOURCE_TYPE_MAIN;
1585 break;
1586 case SCALER_DIP_SOURCE_TYPE_SUB :
1587 eHalSource = E_XC_DIP_SOURCE_TYPE_MAIN;
1588 break;
1589 case SCALER_DIP_SOURCE_TYPE_OP_MAIN:
1590 case SCALER_DIP_SOURCE_TYPE_OP_SUB:
1591 eHalSource = E_XC_DIP_SOURCE_TYPE_OP;
1592 break;
1593 default:
1594 DIP_H_ERR("SCALER_DIP_SOURCE_TYPE does not support\n");
1595 return;
1596 }
1597
1598
1599 //Control OP1 Bank and DIPR
1600 if(eWindowSource == SCALER_DIP_SOURCE_TYPE_DRAM)
1601 {
1602 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L,BIT(14), BIT(14));
1603 }
1604 else if( (eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_SUB) )
1605 {
1606 if( eWindow == DIP_WINDOW )
1607 {
1608 DIP_W2BYTEMSK(0, REG_SC_BK34_7C_L,((eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)?BIT(15):0),BIT(15));
1609 }
1610 else if( eWindow == DWIN0_WINDOW )
1611 {
1612 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, ((eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)?BIT(6):0),BIT(6));
1613 }
1614 else if( eWindow == DWIN1_WINDOW )
1615 {
1616 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, ((eWindowSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)?BIT(6):0),BIT(6));
1617 }
1618 }
1619
1620 //new rotation enabel
1621 DIP_W2BYTEMSK(0, REG_SC_BK34_6E_L,bDIPRotation?BIT(11):0,BIT(11));
1622 //Enable last
1623 if( eWindow == DIP_WINDOW )
1624 {
1625 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, BITS(9:8,eHalSource),BMASK(10:8));
1626 if(DipSource == SCALER_DIP_SOURCE_TYPE_DRAM)
1627 {
1628 //Dipr trigger
1629 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, BIT(15),BIT(15));
1630 }
1631 else
1632 {
1633 // Set the dwin write once (0x03 bit:8)
1634 DIP_W2BYTEMSK(0, REG_SC_BK36_03_L, BIT(8),BIT(8));
1635 //trigger
1636 DIP_W2BYTEMSK(0, REG_SC_BK36_03_L, BIT(9),BIT(9));
1637 }
1638 }
1639 else if( eWindow == DWIN0_WINDOW )
1640 {
1641 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, BITS(9:8,eHalSource),BMASK(10:8));
1642 if(Dwin0Source == SCALER_DIP_SOURCE_TYPE_DRAM)
1643 {
1644 //Dipr trigger
1645 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L,BIT(15), BIT(15));
1646 }
1647 else
1648 {
1649 // Set the dwin write once (0x03 bit:8)
1650 DIP_W2BYTEMSK(0, REG_SC_BK3B_03_L, BIT(8), BIT(8));
1651 //trigger
1652 DIP_W2BYTEMSK(0, REG_SC_BK3B_03_L, BIT(9), BIT(9));
1653 }
1654 }
1655 else if( eWindow == DWIN1_WINDOW )
1656 {
1657 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, BITS(9:8,eHalSource),BMASK(10:8));
1658 if(Dwin1Source == SCALER_DIP_SOURCE_TYPE_DRAM)
1659 {
1660 //Dipr trigger
1661 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L,BIT(15), BIT(15));
1662 }
1663 else
1664 {
1665 // Set the dwin write once (0x03 bit:8)
1666 DIP_W2BYTEMSK(0, REG_SC_BK3C_03_L, BIT(8), BIT(8));
1667 //trigger
1668 DIP_W2BYTEMSK(0, REG_SC_BK3C_03_L, BIT(9), BIT(9));
1669 }
1670 }
1671
1672 DIP_WAIT();
1673 DIP_W2BYTEMSK(0, REG_SC_BK36_29_L, BMASK(7:0), BMASK(7:0));
1674
1675 }
HAL_XC_DIP_SelectSourceScanType(void * pInstance,EN_XC_DWIN_SCAN_TYPE enScan,SCALER_DIP_WIN eWindow)1676 void HAL_XC_DIP_SelectSourceScanType(void *pInstance, EN_XC_DWIN_SCAN_TYPE enScan,SCALER_DIP_WIN eWindow)
1677 {
1678 if( eWindow == DIP_WINDOW )
1679 {
1680 DIP_W2BYTEMSK(0, REG_SC_BK36_01_L,enScan?BIT(15):0, BIT(15));
1681 }
1682 else if( eWindow == DWIN0_WINDOW )
1683 {
1684 DIP_W2BYTEMSK(0, REG_SC_BK3B_01_L,enScan?BIT(15):0, BIT(15));
1685 }
1686 else if( eWindow == DWIN1_WINDOW )
1687 {
1688 DIP_W2BYTEMSK(0, REG_SC_BK3C_01_L,enScan?BIT(15):0, BIT(15));
1689 }
1690 else
1691 {
1692 return;
1693 }
1694 }
HAL_XC_DIP_GetSourceScanType(void * pInstance,SCALER_DIP_WIN eWindow)1695 EN_XC_DWIN_SCAN_TYPE HAL_XC_DIP_GetSourceScanType(void *pInstance, SCALER_DIP_WIN eWindow)
1696 {
1697 EN_XC_DWIN_SCAN_TYPE eSacnType = GOPDWIN_SCAN_MODE_MAX;
1698 if( eWindow == DIP_WINDOW )
1699 {
1700 eSacnType = (EN_XC_DWIN_SCAN_TYPE)(DIP_R2BYTEMSK(0, REG_SC_BK36_01_L,BIT(15),eWindow)>>15);
1701 }
1702 else if( eWindow == DWIN0_WINDOW )
1703 {
1704 eSacnType = (EN_XC_DWIN_SCAN_TYPE)(DIP_R2BYTEMSK(0, REG_SC_BK3B_01_L,BIT(15),eWindow)>>15);
1705 }
1706 else if( eWindow == DWIN1_WINDOW )
1707 {
1708 eSacnType = (EN_XC_DWIN_SCAN_TYPE)(DIP_R2BYTEMSK(0, REG_SC_BK3C_01_L,BIT(15),eWindow)>>15);
1709 }
1710
1711 return eSacnType;
1712 }
HAL_XC_DIP_SetInterlaceWrite(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)1713 void HAL_XC_DIP_SetInterlaceWrite(void *pInstance, MS_BOOL bEnable,SCALER_DIP_WIN eWindow)
1714 {
1715 if( eWindow == DIP_WINDOW )
1716 {
1717 DIP_W2BYTEMSK(0, REG_SC_BK36_01_L, (bEnable?BIT(3):0) ,BIT(3));
1718 }
1719 else if( eWindow == DWIN0_WINDOW )
1720 {
1721 DIP_W2BYTEMSK(0, REG_SC_BK3B_01_L, (bEnable?BIT(3):0) ,BIT(3));
1722 }
1723 else if( eWindow == DWIN1_WINDOW )
1724 {
1725 DIP_W2BYTEMSK(0, REG_SC_BK3C_01_L, (bEnable?BIT(3):0) ,BIT(3));
1726 }
1727 else
1728 {
1729 return;
1730 }
1731 }
HAL_XC_DIP_GetInterlaceWrite(void * pInstance,SCALER_DIP_WIN eWindow)1732 MS_BOOL HAL_XC_DIP_GetInterlaceWrite(void *pInstance, SCALER_DIP_WIN eWindow)
1733 {
1734 MS_BOOL bInterW = FALSE;
1735 if( eWindow == DIP_WINDOW )
1736 {
1737 bInterW = (MS_BOOL)(DIP_R2BYTEMSK(0, REG_SC_BK36_01_L,BIT(3),eWindow)>>3);
1738 }
1739 else if( eWindow == DWIN0_WINDOW )
1740 {
1741 bInterW = (MS_BOOL)(DIP_R2BYTEMSK(0, REG_SC_BK3B_01_L,BIT(3),eWindow)>>3);
1742 }
1743 else if( eWindow == DWIN1_WINDOW )
1744 {
1745 bInterW = (MS_BOOL)(DIP_R2BYTEMSK(0, REG_SC_BK3C_01_L,BIT(3),eWindow)>>3);
1746 }
1747
1748 return bInterW;
1749 }
HAL_XC_DIP_SetDataFmt(void * pInstance,EN_DRV_XC_DWIN_DATA_FMT fmt,SCALER_DIP_WIN eWindow)1750 void HAL_XC_DIP_SetDataFmt(void *pInstance, EN_DRV_XC_DWIN_DATA_FMT fmt,SCALER_DIP_WIN eWindow)
1751 {
1752 MS_U16 u16Fmt = 0x0;
1753
1754 switch (fmt)
1755 {
1756 case XC_DWIN_DATA_FMT_YUV422 :
1757 case XC_DWIN_DATA_FMT_YC422 :
1758 u16Fmt = 0;
1759 break;
1760 case XC_DWIN_DATA_FMT_RGB565 :
1761 u16Fmt = 1;
1762 break;
1763 case XC_DWIN_DATA_FMT_ARGB8888 :
1764 u16Fmt = 2;
1765 break;
1766 case XC_DWIN_DATA_FMT_YUV420 :
1767 case XC_DWIN_DATA_FMT_YUV420_H265 :
1768 case XC_DWIN_DATA_FMT_YUV420_H265_10BITS:
1769 case XC_DWIN_DATA_FMT_YUV420_PLANER:
1770 case XC_DWIN_DATA_FMT_YUV420_SEMI_PLANER:
1771 u16Fmt = 3;
1772 break;
1773 default :
1774 u16Fmt = 0x0;
1775 break;
1776 }
1777 if( eWindow == DIP_WINDOW )
1778 {
1779 DipFmt = fmt;
1780 //set fmt
1781 DIP_W2BYTEMSK(0, REG_SC_BK36_01_L, BITS(5:4,u16Fmt),BMASK(5:4));
1782 //select yc separate
1783 DIP_W2BYTEMSK(0, REG_SC_BK36_03_L,((fmt == XC_DWIN_DATA_FMT_YC422)?BIT(6):0),BIT(6));
1784 //select de-tile for 420 semi planer
1785 DIP_W2BYTEMSK(0, REG_SC_BK36_03_L,((fmt == XC_DWIN_DATA_FMT_YUV420_SEMI_PLANER)?BIT(14):0),BIT(14));
1786 //select flash mode for 420 planer
1787 DIP_W2BYTEMSK(0, REG_SC_BK36_7E_L,((fmt == XC_DWIN_DATA_FMT_YUV420_PLANER)?BIT(14):0),BIT(14));
1788
1789 if( (fmt == XC_DWIN_DATA_FMT_RGB565) || (fmt == XC_DWIN_DATA_FMT_ARGB8888) )
1790 {
1791 //disable yc swap setting
1792 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L,0,BMASK(15:14));
1793 //disable 444 to 422
1794 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L,0,BIT(5));
1795 DIP_W2BYTEMSK(0, REG_SC_BK34_0B_L,0,BIT(12));
1796 }
1797 else
1798 {
1799 //disable rgb swap setting
1800 DIP_W2BYTEMSK(0, REG_SC_BK36_7E_L,0,BIT(13));
1801 //enable 444 to 422
1802 DIP_W2BYTEMSK(0, REG_SC_BK34_30_L, BIT(5),BIT(5));
1803 DIP_W2BYTEMSK(0, REG_SC_BK34_0B_L, BIT(12),BIT(12));
1804 }
1805 }
1806 else if( eWindow == DWIN0_WINDOW )
1807 {
1808 Dwin0Fmt = fmt;
1809 //set fmt
1810 DIP_W2BYTEMSK(0, REG_SC_BK3B_01_L, BITS(5:4,u16Fmt),BMASK(5:4));
1811 //select yc separate
1812 DIP_W2BYTEMSK(0, REG_SC_BK3B_03_L,((fmt == XC_DWIN_DATA_FMT_YC422)?BIT(6):0),BIT(6));
1813 //select de-tile for 420 semi planer
1814 DIP_W2BYTEMSK(0, REG_SC_BK3B_03_L,((fmt == XC_DWIN_DATA_FMT_YUV420_SEMI_PLANER)?BIT(14):0),BIT(14));
1815 //select flash mode for 420 planer
1816 DIP_W2BYTEMSK(0, REG_SC_BK3B_7E_L,((fmt == XC_DWIN_DATA_FMT_YUV420_PLANER)?BIT(14):0),BIT(14));
1817
1818 if( (fmt == XC_DWIN_DATA_FMT_RGB565) || (fmt == XC_DWIN_DATA_FMT_ARGB8888) )
1819 {
1820 //disable yc swap setting
1821 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L,0,BMASK(15:14));
1822 //disable 444 to 422
1823 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L,0,BIT(5)|BIT(0));
1824 }
1825 else
1826 {
1827 //disable rgb swap setting
1828 DIP_W2BYTEMSK(0, REG_SC_BK3B_7E_L,0,BIT(13));
1829 //enable 444 to 422
1830 DIP_W2BYTEMSK(0, REG_SC_BK3B_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0)));
1831 }
1832 }
1833 else if( eWindow == DWIN1_WINDOW )
1834 {
1835 Dwin1Fmt = fmt;
1836 //set fmt
1837 DIP_W2BYTEMSK(0, REG_SC_BK3C_01_L, BITS(5:4,u16Fmt),BMASK(5:4));
1838 //select yc separate
1839 DIP_W2BYTEMSK(0, REG_SC_BK3C_03_L,((fmt == XC_DWIN_DATA_FMT_YC422)?BIT(6):0),BIT(6));
1840 //select de-tile for 420 semi planer
1841 DIP_W2BYTEMSK(0, REG_SC_BK3C_03_L,((fmt == XC_DWIN_DATA_FMT_YUV420_SEMI_PLANER)?BIT(14):0),BIT(14));
1842 //select flash mode for 420 planer
1843 DIP_W2BYTEMSK(0, REG_SC_BK3C_7E_L,((fmt == XC_DWIN_DATA_FMT_YUV420_PLANER)?BIT(14):0),BIT(14));
1844
1845 if( (fmt == XC_DWIN_DATA_FMT_RGB565) || (fmt == XC_DWIN_DATA_FMT_ARGB8888) )
1846 {
1847 //disable yc swap setting
1848 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L,0,BMASK(15:14));
1849 //disable 444 to 422
1850 DIP_W2BYTEMSK(0, REG_SC_BK3C_44_L,0,BIT(5)|BIT(0));
1851 }
1852 else
1853 {
1854 //disable rgb swap setting
1855 DIP_W2BYTEMSK(0, REG_SC_BK3C_7E_L,0,BIT(13));
1856 //enable 444 to 422
1857 DIP_W2BYTEMSK(0, REG_SC_BK3C_44_L, (BIT(5)|BIT(0)),(BIT(5)|BIT(0)));
1858 }
1859 }
1860 else
1861 {
1862 return;
1863 }
1864 }
HAL_XC_DIP_GetDataFmt(void * pInstance,SCALER_DIP_WIN eWindow)1865 EN_DRV_XC_DWIN_DATA_FMT HAL_XC_DIP_GetDataFmt(void *pInstance, SCALER_DIP_WIN eWindow)
1866 {
1867 EN_DRV_XC_DWIN_DATA_FMT eFmt = XC_DWIN_DATA_FMT_MAX;
1868 if( eWindow == DIP_WINDOW )
1869 {
1870 return DipFmt;
1871 }
1872 else if( eWindow == DWIN0_WINDOW )
1873 {
1874 return Dwin0Fmt;
1875 }
1876 else if( eWindow == DWIN1_WINDOW )
1877 {
1878 return Dwin1Fmt;
1879 }
1880
1881 return eFmt;
1882 }
HAL_XC_DIP_GetBPP(void * pInstance,EN_DRV_XC_DWIN_DATA_FMT fbFmt,SCALER_DIP_WIN eWindow)1883 MS_U16 HAL_XC_DIP_GetBPP(void *pInstance, EN_DRV_XC_DWIN_DATA_FMT fbFmt,SCALER_DIP_WIN eWindow)
1884 {
1885 MS_U16 bpp=0;
1886
1887 switch ( fbFmt )
1888 {
1889 case XC_DWIN_DATA_FMT_YUV422 :
1890 case XC_DWIN_DATA_FMT_YC422 :
1891 case XC_DWIN_DATA_FMT_RGB565 :
1892 bpp = 2;
1893 break;
1894 case XC_DWIN_DATA_FMT_ARGB8888 :
1895 bpp = 4;
1896 break;
1897 case XC_DWIN_DATA_FMT_YUV420 :
1898 case XC_DWIN_DATA_FMT_YUV420_H265 :
1899 case XC_DWIN_DATA_FMT_YUV420_H265_10BITS :
1900 case XC_DWIN_DATA_FMT_YUV420_PLANER :
1901 case XC_DWIN_DATA_FMT_YUV420_SEMI_PLANER :
1902 bpp = 1;
1903 break;
1904 default :
1905 bpp = 0xFF;
1906 break;
1907 }
1908 return bpp;
1909 }
HAL_XC_DIP_WidthAlignCheck(void * pInstance,MS_U16 u16Width,MS_U16 u16Bpp,SCALER_DIP_WIN eWindow)1910 MS_U16 HAL_XC_DIP_WidthAlignCheck(void *pInstance, MS_U16 u16Width,MS_U16 u16Bpp,SCALER_DIP_WIN eWindow)
1911 {
1912 MS_U16 AlignFactor;
1913 MS_U16 u16BusSize = 0;
1914
1915 u16BusSize = HAL_XC_DIP_GetBusSize(pInstance, eWindow);
1916 AlignFactor = u16BusSize;
1917 return (u16Width + AlignFactor-1) & (~(AlignFactor-1));
1918 }
1919
HAL_XC_DIP_SetMux(void * pInstance,MS_U8 u8Data_Mux,MS_U8 u8Clk_Mux,SCALER_DIP_WIN eWindow)1920 void HAL_XC_DIP_SetMux(void *pInstance, MS_U8 u8Data_Mux, MS_U8 u8Clk_Mux,SCALER_DIP_WIN eWindow)
1921 {
1922 if( eWindow == DIP_WINDOW )
1923 {
1924 MDrv_DIP_WriteByteMask(REG_IPMUX_02_L, u8Data_Mux << 4, 0xF0);
1925 MDrv_DIP_WriteByteMask(REG_CKG_IDCLK3, u8Clk_Mux, CKG_IDCLK3_MASK);
1926 }
1927 else if( eWindow == DWIN0_WINDOW )
1928 {
1929 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 8,BMASK(11:8));
1930 MDrv_DIP_WriteByteMask(REG_CKG_PDW0, u8Clk_Mux, CKG_PDW0_MASK);
1931 }
1932 else if( eWindow == DWIN1_WINDOW )
1933 {
1934 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L,u8Data_Mux << 12,BMASK(15:12));
1935 MDrv_DIP_WriteByteMask(REG_CKG_PDW1, u8Clk_Mux, CKG_PDW1_MASK);
1936 }
1937 else
1938 {
1939 return;
1940 }
1941 }
HAL_XC_DIP_MuxDispatch(void * pInstance,SCALER_DIP_SOURCE_TYPE eSource,SCALER_DIP_WIN eWindow)1942 void HAL_XC_DIP_MuxDispatch(void *pInstance, SCALER_DIP_SOURCE_TYPE eSource,SCALER_DIP_WIN eWindow)
1943 {
1944 MS_U16 u16clk_usr_enable=0;
1945
1946 if( eWindow == DIP_WINDOW )
1947 {
1948 if(eSource == SCALER_DIP_SOURCE_TYPE_MAIN)
1949 {
1950 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_SC_VOP,SC_DWIN_IPMUX_SC_VOP<<2,eWindow);
1951 DIP_W2BYTEMSK(0, REG_SC_BK34_50_L, 0,BIT(15));
1952 }
1953 else if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
1954 {
1955 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_SC_VOP,SC_DWIN_IPMUX_EXT_VD<<2,eWindow);
1956 DIP_W2BYTEMSK(0, REG_SC_BK34_50_L, 0,BIT(15));
1957 }
1958 else if( (eSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (eSource == SCALER_DIP_SOURCE_TYPE_OP_SUB))
1959 {
1960
1961 }
1962 else if(eSource == SCALER_DIP_SOURCE_TYPE_DRAM)
1963 {
1964
1965 }
1966 else if(eSource == SCALER_DIP_SOURCE_TYPE_OP_CAPTURE)
1967 {
1968 u16clk_usr_enable = MDrv_DIP_Read2Byte(REG_CKG_IDCLK_USR_ENA) &CKG_IDCLK3_USR_ENA;
1969 if(u16clk_usr_enable==0)
1970 {
1971 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_CAPTURE,SC_DWIN_IPMUX_CAPTURE<<2,eWindow);
1972 }
1973 else
1974 {
1975 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_CAPTURE,SC_DWIN_IPMUX_HDMI_DVI<<2,eWindow);
1976 }
1977 }
1978 else if(eSource == SCALER_DIP_SOURCE_TYPE_SC2_OP_CAPTURE)
1979 {
1980 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_EXT_VD,SC_DWIN_IPMUX_EXT_VD<<2,eWindow);
1981 DIP_W2BYTEMSK(0, REG_SC_BK20_03_L, BIT(1),BIT(1));
1982 DIP_W2BYTEMSK(0, REG_SC_BK20_2F_L, BIT(15),BIT(15));
1983 }
1984 else if(eSource == SCALER_DIP_SOURCE_TYPE_OSD)
1985 {
1986 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_ADC_B,SC_DWIN_IPMUX_CAPTURE<<2,eWindow);
1987 }
1988 else
1989 DIP_H_DBUG("MApi_XC_DIP_SetDIPWinProperty eSource = %d is not correct\n",eSource);
1990 }
1991 else if( eWindow == DWIN0_WINDOW )
1992 {
1993 if(eSource == SCALER_DIP_SOURCE_TYPE_MAIN)
1994 {
1995 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_SC_VOP,SC_DWIN_IPMUX_SC_VOP<<2,eWindow);
1996 DIP_W2BYTEMSK(0, REG_SC_BK3B_7A_L, 0,BIT(15));
1997 DIP_W2BYTEMSK(0, REG_SC_BK3B_70_L, 0,BMASK(4:1));
1998 }
1999 else if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2000 {
2001 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_SC_VOP,SC_DWIN_IPMUX_ADC_B<<2,eWindow);
2002 DIP_W2BYTEMSK(0, REG_SC_BK3B_7A_L, BIT(15),BIT(15));
2003 DIP_W2BYTEMSK(0, REG_SC_BK3B_70_L, BIT(4)|BIT(1),BMASK(4:1));
2004 }
2005 else if( (eSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (eSource == SCALER_DIP_SOURCE_TYPE_OP_SUB))
2006 {
2007
2008 }
2009 else if(eSource == SCALER_DIP_SOURCE_TYPE_DRAM)
2010 {
2011
2012 }
2013 else if(eSource == SCALER_DIP_SOURCE_TYPE_OP_CAPTURE)
2014 {
2015 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_CAPTURE,SC_DWIN_IPMUX_CAPTURE<<2,eWindow);
2016 }
2017 else if(eSource == SCALER_DIP_SOURCE_TYPE_SC2_OP_CAPTURE)
2018 {
2019 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_EXT_VD,SC_DWIN_IPMUX_EXT_VD<<2,eWindow);
2020 DIP_W2BYTEMSK(0, REG_SC_BK20_03_L, BIT(1),BIT(1));
2021 DIP_W2BYTEMSK(0, REG_SC_BK20_2F_L, BIT(15),BIT(15));
2022 }
2023 else
2024 DIP_H_DBUG("MApi_XC_DIP_SetDIPWinProperty eSource = %d is not correct\n",eSource);
2025 }
2026 else if( eWindow == DWIN1_WINDOW )
2027 {
2028 if(eSource == SCALER_DIP_SOURCE_TYPE_MAIN)
2029 {
2030 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_SC_VOP,SC_DWIN_IPMUX_SC_VOP<<2,eWindow);
2031 DIP_W2BYTEMSK(0, REG_SC_BK3C_7A_L, 0,BIT(15));
2032 DIP_W2BYTEMSK(0, REG_SC_BK3C_70_L, 0,BMASK(4:1));
2033 }
2034 else if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2035 {
2036 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_SC_VOP,SC_DWIN_IPMUX_ADC_B<<2,eWindow);
2037 DIP_W2BYTEMSK(0, REG_SC_BK3C_7A_L, BIT(15),BIT(15));
2038 DIP_W2BYTEMSK(0, REG_SC_BK3C_70_L, BIT(4)|BIT(1),BMASK(4:1));
2039 }
2040 else if( (eSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (eSource == SCALER_DIP_SOURCE_TYPE_OP_SUB))
2041 {
2042
2043 }
2044 else if(eSource == SCALER_DIP_SOURCE_TYPE_DRAM)
2045 {
2046
2047 }
2048 else if(eSource == SCALER_DIP_SOURCE_TYPE_OP_CAPTURE)
2049 {
2050 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_CAPTURE,SC_DWIN_IPMUX_CAPTURE<<2,eWindow);
2051 }
2052 else if(eSource == SCALER_DIP_SOURCE_TYPE_SC2_OP_CAPTURE)
2053 {
2054 HAL_XC_DIP_SetMux(pInstance, SC_DWIN_IPMUX_EXT_VD,SC_DWIN_IPMUX_EXT_VD<<2,eWindow);
2055 DIP_W2BYTEMSK(0, REG_SC_BK20_03_L, BIT(1),BIT(1));
2056 DIP_W2BYTEMSK(0, REG_SC_BK20_2F_L, BIT(15),BIT(15));
2057 }
2058 else
2059 DIP_H_DBUG("MApi_XC_DIP_SetDIPWinProperty eSource = %d is not correct\n",eSource);
2060 }
2061 else
2062 {
2063 return;
2064 }
2065 }
2066
HAL_XC_DIP_AdjustScaling(void * pInstance,SCALER_DIP_WIN eWindow,SCALER_DIP_SOURCE_TYPE eSource)2067 void HAL_XC_DIP_AdjustScaling(void *pInstance,SCALER_DIP_WIN eWindow,SCALER_DIP_SOURCE_TYPE eSource)
2068 {
2069 #ifdef UTOPIA_V2
2070 DIP_INSTANCE_PRIVATE* pDipPri = NULL;
2071 DIP_SHARE_RESOURCE_PRIVATE* pDipResPri = NULL;
2072 UtopiaInstanceGetPrivate(pInstance, (void*)&pDipPri);
2073 UtopiaResourceGetPrivate(pDipPri->pShareResource,(void*)&(pDipResPri));
2074 #endif
2075 MS_U16 u16HSD_X = 0;
2076 SCALER_DIP_WIN eHVSPWindow = MAX_DIP_WINDOW;
2077 SC_DIP_SWDB_INFO DBreg;
2078 MS_U64 u64_result = 0;
2079
2080 eHVSPWindow = HAL_XC_DIP_GetHVSP(pInstance);
2081 Hal_SC_DWIN_get_sw_db(pInstance,&DBreg,eWindow);
2082
2083 if(eSource != SCALER_DIP_SOURCE_TYPE_DRAM)
2084 {
2085 // Hscaling
2086 if( (g_DIPSrcInfo[eWindow].u16PreHCusScalingDst > FHD_WIDTH) )
2087 {
2088 g_DIPSrcInfo[eWindow].u16PreHCusScalingDst = FHD_WIDTH;
2089 }
2090 }
2091
2092 //scaling down
2093 if( (g_DIPSrcInfo[eWindow].u16PreHCusScalingSrc > g_DIPSrcInfo[eWindow].u16PreHCusScalingDst) )
2094 {
2095 DBreg.u32H_PreScalingRatio = H_PreScalingDownRatioDIP(g_DIPSrcInfo[eWindow].u16PreHCusScalingSrc,g_DIPSrcInfo[eWindow].u16PreHCusScalingDst);
2096 DBreg.u32H_PreScalingRatio &= 0x7FFFFFL;
2097 DBreg.u32H_PreScalingRatio |= (BIT(31));
2098 u64_result = DBreg.u16H_CapStart*(g_DIPSrcInfo[eWindow].u16PreHCusScalingDst);
2099 do_div(u64_result,(g_DIPSrcInfo[eWindow].u16PreHCusScalingSrc));
2100 u16HSD_X = u64_result;
2101 DBreg.u16H_CapStart = u16HSD_X;
2102 DBreg.u16H_CapSize = g_DIPSrcInfo[eWindow].u16PreHCusScalingDst;
2103 }
2104 Hal_SC_DWIN_sw_db(pInstance,&DBreg,eWindow);
2105 }
HAL_XC_DIP_SetWinProperty(void * pInstance,MS_U8 u8BufCnt,MS_U16 u16Width,MS_U16 u16LineOft,MS_U16 u16Height,MS_PHY u64OffSet,SCALER_DIP_SOURCE_TYPE eSource,MS_BOOL bPIP,MS_BOOL b2P_Enable,SCALER_DIP_WIN eWindow)2106 void HAL_XC_DIP_SetWinProperty(void *pInstance, MS_U8 u8BufCnt,MS_U16 u16Width,MS_U16 u16LineOft,MS_U16 u16Height,MS_PHY u64OffSet, SCALER_DIP_SOURCE_TYPE eSource,MS_BOOL bPIP, MS_BOOL b2P_Enable, SCALER_DIP_WIN eWindow)
2107 {
2108 #ifdef UTOPIA_V2
2109 DIP_INSTANCE_PRIVATE* pDipPri = NULL;
2110 DIP_SHARE_RESOURCE_PRIVATE* pDipResPri = NULL;
2111 UtopiaInstanceGetPrivate(pInstance, (void*)&pDipPri);
2112 UtopiaResourceGetPrivate(pDipPri->pShareResource,(void*)&(pDipResPri));
2113 #endif
2114 MS_U64 u64_result = 0;
2115 bPIPmode = bPIP;
2116 MS_U16 u16SrcWith = 0;
2117 MS_U16 u16MaxWith = 0;
2118
2119 //2p to 1p
2120 if(eSource == SCALER_DIP_SOURCE_TYPE_MAIN)
2121 {
2122 if(b2P_Enable)
2123 {
2124 MS_BOOL bVideoPmode = TRUE;
2125
2126 u16MaxWith = DIP_R2BYTEMSK(0, REG_SC_BK01_07_L,BMASK(13:0),eWindow);
2127
2128 // bk0x1301_reg0x1e[11] , 1: i mode, 0: p mode
2129 bVideoPmode = (MDrv_ReadRegBit((REG_MVOP_BASE + 0x22), (BIT(7)))) ? FALSE : TRUE;
2130 if ((( bVideoPmode == TRUE) && (u16MaxWith == UHD_WIDTH)) ||
2131 (( bVideoPmode == FALSE) && (u16MaxWith == FHD_WIDTH))
2132 )
2133 {
2134 u16MaxWith = g_DIPSrcInfo[eWindow].stCapWin.width;
2135 }
2136 }
2137 else
2138 {
2139 u16MaxWith = DIP_R2BYTEMSK(0, REG_SC_BK01_07_L,BMASK(13:0),eWindow);
2140 }
2141 }
2142 else if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2143 {
2144 u16MaxWith = DIP_R2BYTEMSK(0, REG_SC_BK81_07_L,BMASK(12:0),eWindow);
2145 }
2146 else if(eSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN)
2147 {
2148 u16MaxWith = DIP_R2BYTEMSK(0, REG_SC_BK12_17_L,BMASK(13:0),eWindow);
2149 }
2150 else if(eSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)
2151 {
2152 u16MaxWith = DIP_R2BYTEMSK(0, REG_SC_BK12_57_L,BMASK(13:0),eWindow);
2153 }
2154 else if(eSource == SCALER_DIP_SOURCE_TYPE_OP_CAPTURE)
2155 {
2156 u16MaxWith = (DIP_R2BYTEMSK(0, REG_SC_BK10_05_L,BMASK(13:0),eWindow) - DIP_R2BYTEMSK(0, REG_SC_BK10_04_L,BMASK(13:0),eWindow)+1);
2157 }
2158 else if(eSource == SCALER_DIP_SOURCE_TYPE_DRAM)
2159 {
2160 u16MaxWith = DIP_R2BYTEMSK(0, REG_SC_BK36_27_L,BMASK(13:0),eWindow);
2161 }
2162
2163 HAL_XC_DIP_AdjustScaling(pInstance,eWindow,eSource);
2164
2165 if( eWindow == DIP_WINDOW )
2166 {
2167 DipWBufCnt = u8BufCnt;
2168 DipSource = eSource;
2169 u16SrcWith = DipSrcWidth;
2170 DIP_W2BYTEMSK(0, REG_SC_BK36_01_L, u8BufCnt-1,BMASK(2:0));
2171
2172 if(eSource == SCALER_DIP_SOURCE_TYPE_DRAM)
2173 {
2174 //1: from dipr
2175 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L,BIT(6),BIT(6));
2176 // dipr to dip
2177 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L,BIT(13),BMASK(13:12));
2178 //disable source yc swap
2179 DIP_W2BYTEMSK(0, REG_SC_BK34_7C_L,0,BIT(14));
2180 }
2181 else
2182 {
2183 //0: from IPMUX/OP1
2184 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L,0,BIT(6));
2185 //Monaco Mode DI input is 422
2186 if( ((eSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (eSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)) && (bDipR2Y == FALSE) )
2187 {
2188 //enable 422 to 444
2189 DIP_W2BYTEMSK(0, REG_SC_BK34_6C_L,BIT(9),BIT(9));
2190 //enable source yc swap
2191 DIP_W2BYTEMSK(0, REG_SC_BK34_7C_L,BIT(14),BIT(14));
2192 }
2193 else
2194 {
2195 //disable 422 to 444
2196 DIP_W2BYTEMSK(0, REG_SC_BK34_6C_L,0,BIT(9));
2197 //disable source yc swap
2198 DIP_W2BYTEMSK(0, REG_SC_BK34_7C_L,0,BIT(14));
2199 }
2200 }
2201
2202 if( (eSource == SCALER_DIP_SOURCE_TYPE_MAIN)||(eSource == SCALER_DIP_SOURCE_TYPE_SUB) )
2203 {
2204 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L, BIT(15), BMASK(15:14));
2205 }
2206 if( (bDIPRotation == TRUE) && (DIPRotation == eWindow) )
2207 {
2208 //width
2209 DIP_W2BYTE(0, REG_SC_BK36_2F_L, u16Width);
2210 //height
2211 DIP_W2BYTE(0, REG_SC_BK36_1F_L, u16Height);
2212 }
2213 else
2214 {
2215 //width
2216 DIP_W2BYTE(0, REG_SC_BK36_1F_L, u16Width);
2217 //height
2218 DIP_W2BYTE(0, REG_SC_BK36_2F_L, u16Height);
2219 }
2220 //pitch
2221 DIP_W2BYTE(0, REG_SC_BK36_3F_L, u16LineOft);
2222 //buffer offset
2223 DIP_W4BYTE(0, REG_SC_BK36_50_L,u64OffSet);
2224
2225 if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2226 {
2227 //reg_4k_h_size
2228 u64_result = u16MaxWith+1;
2229 do_div(u64_result,2);
2230 DIP_W2BYTEMSK(0, REG_SC_BK34_6D_L, u64_result,BMASK(11:0));
2231 DIP_W2BYTEMSK(0, REG_SC_BK34_6D_L, BIT(15),BIT(15));
2232 //dip_op_pre_sel (2: sc2 3: sc)
2233 DIP_W2BYTEMSK(0, REG_SC_BK34_67_L, 0x3 ,BMASK(1:0));
2234 DIP_W2BYTEMSK(0, REG_SC_BK34_31_L, BIT(4) ,BIT(4));
2235 }
2236 else if(eSource != SCALER_DIP_SOURCE_TYPE_SC2_OP_CAPTURE)
2237 {
2238 //reg_4k_h_size
2239 DIP_W2BYTEMSK(0, REG_SC_BK34_6D_L, ((u16MaxWith+1)/2),BMASK(11:0));
2240 DIP_W2BYTEMSK(0, REG_SC_BK34_6D_L, BIT(15),BIT(15));
2241 //dip_op_pre_sel (2: sc2 3: sc)
2242 DIP_W2BYTEMSK(0, REG_SC_BK34_67_L, 0x3 ,BMASK(1:0));
2243 DIP_W2BYTEMSK(0, REG_SC_BK34_31_L, 0 ,BIT(4));
2244 }
2245 else
2246 {
2247 //reg_4k_h_size
2248 DIP_W2BYTEMSK(0, REG_SC_BK34_6D_L, 0,BIT(15));
2249 //dip_op_pre_sel (2: sc2 3: sc)
2250 DIP_W2BYTEMSK(0, REG_SC_BK34_67_L, 0x2 ,BMASK(1:0));
2251 DIP_W2BYTEMSK(0, REG_SC_BK34_31_L, 0 ,BIT(4));
2252 }
2253 //DIP Clk gating seletion and source select
2254 if(eSource == SCALER_DIP_SOURCE_TYPE_MAIN)
2255 {
2256 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L, BIT(8),BMASK(8:7));
2257 DIP_W2BYTEMSK(0, REG_SC_BK34_67_L, 0,BMASK(4:2));//0: ip_main 1: ip_sub 4: sc2_ip_main
2258 }
2259 else if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2260 {
2261 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L, BIT(8),BMASK(8:7));
2262 DIP_W2BYTEMSK(0, REG_SC_BK34_67_L, BIT(4),BMASK(4:2));//0: ip_main 1: ip_sub 4: sc2_ip_main
2263 }
2264 else
2265 {
2266 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L, 0x0,BMASK(8:7));
2267 }
2268 }
2269 else if( eWindow == DWIN0_WINDOW )
2270 {
2271 Dwin0WBufCnt = u8BufCnt;
2272 Dwin0Source = eSource;
2273 u16SrcWith = Dwin0SrcWidth;
2274 DIP_W2BYTEMSK(0, REG_SC_BK3B_01_L, u8BufCnt-1,BMASK(2:0));
2275
2276 if(eSource == SCALER_DIP_SOURCE_TYPE_DRAM)
2277 {
2278 //1: from dipr
2279 DIP_W2BYTEMSK(0, REG_SC_BK3B_73_L,BIT(6),BIT(6));
2280 // dipr to dwin0
2281 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L,0,BMASK(13:12));
2282 //disable source yc swap
2283 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L,0,BIT(8));
2284 }
2285 else
2286 {
2287 //0: from IPMUX/OP1
2288 DIP_W2BYTEMSK(0, REG_SC_BK3B_73_L,0,BIT(6));
2289 //Monaco Mode DI input is 422
2290 if( ((eSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (eSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)) && (bDwin0R2Y == FALSE) )
2291 {
2292 //enable 422 to 444
2293 DIP_W2BYTEMSK(0, REG_SC_BK3B_78_L,BIT(9),BIT(9));
2294 //enable source yc swap
2295 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L,BIT(8),BIT(8));
2296 }
2297 else
2298 {
2299 //disable 422 to 444
2300 DIP_W2BYTEMSK(0, REG_SC_BK3B_78_L,0,BIT(9));
2301 //disable source yc swap
2302 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L,0,BIT(8));
2303 }
2304 }
2305
2306 if( (eSource == SCALER_DIP_SOURCE_TYPE_MAIN)||(eSource == SCALER_DIP_SOURCE_TYPE_SUB) )
2307 {
2308 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, BIT(5), BMASK(5:4));
2309 }
2310
2311 if( (bDIPRotation == TRUE) && (DIPRotation == eWindow) )
2312 {
2313 //width
2314 DIP_W2BYTE(0, REG_SC_BK3B_2F_L, u16Width);
2315 //height
2316 DIP_W2BYTE(0, REG_SC_BK3B_1F_L, u16Height);
2317 }
2318 else
2319 {
2320 //width
2321 DIP_W2BYTE(0, REG_SC_BK3B_1F_L, u16Width);
2322 //height
2323 DIP_W2BYTE(0, REG_SC_BK3B_2F_L, u16Height);
2324 }
2325 //pitch
2326 DIP_W2BYTE(0, REG_SC_BK3B_3F_L, u16LineOft);
2327 //buffer offset
2328 DIP_W4BYTE(0, REG_SC_BK3B_50_L,u64OffSet);
2329
2330 if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2331 {
2332 //reg_4k_h_size
2333 u64_result = u16MaxWith+1;
2334 do_div(u64_result,2);
2335 DIP_W2BYTEMSK(0, REG_SC_BK3B_79_L, u64_result,BMASK(11:0));
2336 DIP_W2BYTEMSK(0, REG_SC_BK3B_79_L, BIT(15),BIT(15));
2337 //dip_op_pre_sel (2: sc2 3: sc)
2338 DIP_W2BYTEMSK(0, REG_SC_BK3B_67_L, 0x3 ,BMASK(1:0));
2339 DIP_W2BYTEMSK(0, REG_SC_BK3B_39_L, BIT(15) ,BIT(15));
2340 }
2341 else if(eSource != SCALER_DIP_SOURCE_TYPE_SC2_OP_CAPTURE)
2342 {
2343 //reg_4k_h_size
2344 DIP_W2BYTEMSK(0, REG_SC_BK3B_79_L, ((u16MaxWith+1)/2),BMASK(11:0));
2345 DIP_W2BYTEMSK(0, REG_SC_BK3B_79_L, BIT(15),BIT(15));
2346 //dip_op_pre_sel (2: sc2 3: sc)
2347 DIP_W2BYTEMSK(0, REG_SC_BK3B_67_L, 0x3 ,BMASK(1:0));
2348 DIP_W2BYTEMSK(0, REG_SC_BK3B_39_L, 0 ,BIT(15));
2349 }
2350 else
2351 {
2352 //reg_4k_h_size
2353 DIP_W2BYTEMSK(0, REG_SC_BK3B_79_L, 0x0,BIT(15));
2354 //dip_op_pre_sel (2: sc2 3: sc)
2355 DIP_W2BYTEMSK(0, REG_SC_BK3B_67_L, 0x2 ,BMASK(1:0));
2356 DIP_W2BYTEMSK(0, REG_SC_BK3B_39_L, 0 ,BIT(15));
2357 }
2358 //DWIN0 Clk gating seletion and source select
2359 if(eSource == SCALER_DIP_SOURCE_TYPE_MAIN)
2360 {
2361 DIP_W2BYTEMSK(0, REG_SC_BK3B_73_L, BIT(8),BMASK(8:7));
2362 DIP_W2BYTEMSK(0, REG_SC_BK3B_67_L, 0,BMASK(4:2));//0: ip_main 1: ip_sub 4: sc2_ip_main
2363 }
2364 else if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2365 {
2366 DIP_W2BYTEMSK(0, REG_SC_BK3B_73_L, BIT(8),BMASK(8:7));
2367 DIP_W2BYTEMSK(0, REG_SC_BK3B_67_L, BIT(4),BMASK(4:2));//0: ip_main 1: ip_sub 4: sc2_ip_main
2368 }
2369 else
2370 {
2371 DIP_W2BYTEMSK(0, REG_SC_BK3B_73_L, 0x0,BMASK(8:7));
2372 }
2373 }
2374 else if( eWindow == DWIN1_WINDOW )
2375 {
2376 Dwin1WBufCnt = u8BufCnt;
2377 Dwin1Source = eSource;
2378 u16SrcWith = Dwin1SrcWidth;
2379 DIP_W2BYTEMSK(0, REG_SC_BK3C_01_L, u8BufCnt-1,BMASK(2:0));
2380
2381 if(eSource == SCALER_DIP_SOURCE_TYPE_DRAM)
2382 {
2383 //1: from dipr
2384 DIP_W2BYTEMSK(0, REG_SC_BK3C_73_L,BIT(6),BIT(6));
2385 //2. dipr to dwin1
2386 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L,BIT(12),BMASK(13:12));
2387 //disable source yc swap
2388 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L,0,BIT(8));
2389 }
2390 else
2391 {
2392 //0: from IPMUX/OP1
2393 DIP_W2BYTEMSK(0, REG_SC_BK3C_73_L,0,BIT(6));
2394 //Monaco Mode DI input is 422
2395 if( ((eSource == SCALER_DIP_SOURCE_TYPE_OP_MAIN) || (eSource == SCALER_DIP_SOURCE_TYPE_OP_SUB)) && (bDwin1R2Y == FALSE) )
2396 {
2397 //enable 422 to 444
2398 DIP_W2BYTEMSK(0, REG_SC_BK3C_78_L,BIT(9),BIT(9));
2399 //enable source yc swap
2400 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L,BIT(8),BIT(8));
2401 }
2402 else
2403 {
2404 //disable 422 to 444
2405 DIP_W2BYTEMSK(0, REG_SC_BK3C_78_L,0,BIT(9));
2406 //disable source yc swap
2407 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L,0,BIT(8));
2408 }
2409 }
2410
2411 if( (eSource == SCALER_DIP_SOURCE_TYPE_MAIN)||(eSource == SCALER_DIP_SOURCE_TYPE_SUB) )
2412 {
2413 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, BIT(5), BMASK(5:4));
2414 }
2415
2416 if( (bDIPRotation == TRUE) && (DIPRotation == eWindow) )
2417 {
2418 //width
2419 DIP_W2BYTE(0, REG_SC_BK3C_2F_L, u16Width);
2420 //height
2421 DIP_W2BYTE(0, REG_SC_BK3C_1F_L, u16Height);
2422 }
2423 else
2424 {
2425 //width
2426 DIP_W2BYTE(0, REG_SC_BK3C_1F_L, u16Width);
2427 //height
2428 DIP_W2BYTE(0, REG_SC_BK3C_2F_L, u16Height);
2429 }
2430 //pitch
2431 DIP_W2BYTE(0, REG_SC_BK3C_3F_L, u16LineOft);
2432 //buffer offset
2433 DIP_W4BYTE(0, REG_SC_BK3C_50_L,u64OffSet);
2434
2435 if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2436 {
2437 //reg_4k_h_size
2438 u64_result = u16MaxWith+1;
2439 do_div(u64_result,2);
2440 DIP_W2BYTEMSK(0, REG_SC_BK3C_79_L, u64_result ,BMASK(11:0));
2441 DIP_W2BYTEMSK(0, REG_SC_BK3C_79_L, BIT(15),BIT(15));
2442 //dip_op_pre_sel (2: sc2 3: sc)
2443 DIP_W2BYTEMSK(0, REG_SC_BK3C_67_L, 0x3 ,BMASK(1:0));
2444 DIP_W2BYTEMSK(0, REG_SC_BK3C_39_L, BIT(15) ,BIT(15));
2445 }
2446 else if(eSource != SCALER_DIP_SOURCE_TYPE_SC2_OP_CAPTURE)
2447 {
2448 //reg_4k_h_size
2449 DIP_W2BYTEMSK(0, REG_SC_BK3C_79_L, ((u16MaxWith+1)/2),BMASK(11:0));
2450 DIP_W2BYTEMSK(0, REG_SC_BK3C_79_L, BIT(15),BIT(15));
2451 //dip_op_pre_sel (2: sc2 3: sc)
2452 DIP_W2BYTEMSK(0, REG_SC_BK3C_67_L, 0x3 ,BMASK(1:0));
2453 DIP_W2BYTEMSK(0, REG_SC_BK3C_39_L, 0 ,BIT(15));
2454 }
2455 else
2456 {
2457 //reg_4k_h_size
2458 DIP_W2BYTEMSK(0, REG_SC_BK3C_79_L, 0x0,BIT(15));
2459 //dip_op_pre_sel (2: sc2 3: sc)
2460 DIP_W2BYTEMSK(0, REG_SC_BK3C_67_L, 0x2 ,BMASK(1:0));
2461 DIP_W2BYTEMSK(0, REG_SC_BK3C_39_L, 0 ,BIT(15));
2462 }
2463 //DWIN1 Clk gating seletion and source select
2464 if(eSource == SCALER_DIP_SOURCE_TYPE_MAIN)
2465 {
2466 DIP_W2BYTEMSK(0, REG_SC_BK3C_73_L, BIT(8),BMASK(8:7));
2467 DIP_W2BYTEMSK(0, REG_SC_BK3C_67_L, 0,BMASK(4:2));//0: ip_main 1: ip_sub 4: sc2_ip_main
2468 }
2469 else if(eSource == SCALER_DIP_SOURCE_TYPE_SUB)
2470 {
2471 DIP_W2BYTEMSK(0, REG_SC_BK3C_73_L, BIT(8),BMASK(8:7));
2472 DIP_W2BYTEMSK(0, REG_SC_BK3C_67_L, BIT(4),BMASK(4:2));//0: ip_main 1: ip_sub 4: sc2_ip_main
2473 }
2474 else
2475 {
2476 DIP_W2BYTEMSK(0, REG_SC_BK3C_73_L, 0x0,BMASK(8:7));
2477 }
2478 }
2479
2480 //Rotation
2481 if( (bDIPRotation == TRUE) && (DIPRotation == eWindow) ){
2482 u64_result = u16Height;
2483 do_div(u64_result,0x10);
2484 DIP_W2BYTEMSK(0, REG_SC_BK34_6E_L, u64_result,BMASK(7:0));
2485 }
2486 }
HAL_XC_DIP_SetWinProperty1(void * pInstance,MS_PHY u64OffSet,SCALER_DIP_WIN eWindow)2487 void HAL_XC_DIP_SetWinProperty1(void *pInstance, MS_PHY u64OffSet,SCALER_DIP_WIN eWindow)
2488 {
2489 if( eWindow == DIP_WINDOW )
2490 {
2491 DIP_W4BYTE(0, REG_SC_BK36_60_L,u64OffSet);
2492 }
2493 else if( eWindow == DWIN0_WINDOW )
2494 {
2495 DIP_W4BYTE(0, REG_SC_BK3B_60_L,u64OffSet);
2496 }
2497 else if( eWindow == DWIN1_WINDOW )
2498 {
2499 DIP_W4BYTE(0, REG_SC_BK3C_60_L,u64OffSet);
2500 }
2501 else
2502 {
2503 return;
2504 }
2505 }
HAL_XC_DIP_GetBufCnt(void * pInstance,SCALER_DIP_WIN eWindow)2506 MS_U8 HAL_XC_DIP_GetBufCnt(void *pInstance, SCALER_DIP_WIN eWindow)
2507 {
2508 MS_U8 u8BufCnt = 0;
2509 if( eWindow == DIP_WINDOW )
2510 {
2511 u8BufCnt = DipWBufCnt;
2512 }
2513 else if( eWindow == DWIN0_WINDOW )
2514 {
2515 u8BufCnt = Dwin0WBufCnt;
2516 }
2517 else if( eWindow == DWIN1_WINDOW )
2518 {
2519 u8BufCnt = Dwin1WBufCnt;
2520 }
2521 return (MS_U8) u8BufCnt;
2522 }
HAL_XC_DIP_SetBase0(void * pInstance,MS_PHY u64BufStart,MS_PHY u64BufEnd,SCALER_DIP_WIN eWindow)2523 void HAL_XC_DIP_SetBase0(void *pInstance,MS_PHY u64BufStart,MS_PHY u64BufEnd,SCALER_DIP_WIN eWindow)
2524 {
2525 MS_U16 u16BusSize = 0;
2526 MS_U64 u64_result = 0;
2527
2528 u16BusSize = HAL_XC_DIP_GetBusSize(pInstance, eWindow);
2529 if( eWindow == DIP_WINDOW )
2530 {
2531 //low bound
2532 u64_result = u64BufStart;
2533 do_div(u64_result,u16BusSize);
2534 DIP_W4BYTE(0, REG_SC_BK36_10_L, u64_result); // input address0
2535 //high bound
2536 u64_result = u64BufEnd;
2537 do_div(u64_result,u16BusSize);
2538 u64_result|=(1<<DWIN_W_LIMITE_OFT);
2539 //u64BufEnd /= u16BusSize;
2540 //u64BufEnd|=(1<<DWIN_W_LIMITE_OFT);
2541 DIP_W4BYTE(0, REG_SC_BK36_30_L, u64_result); // input address0
2542 }
2543 else if( eWindow == DWIN0_WINDOW )
2544 {
2545 //low bound
2546 u64_result = u64BufStart;
2547 do_div(u64_result,u16BusSize);
2548 DIP_W4BYTE(0, REG_SC_BK3B_10_L, u64_result); // input address0
2549 //high bound
2550 u64_result = u64BufEnd;
2551 do_div(u64_result,u16BusSize);
2552 u64_result|=(1<<DWIN_W_LIMITE_OFT);
2553 //u64BufEnd /= u16BusSize;
2554 //u64BufEnd|=(1<<DWIN_W_LIMITE_OFT);
2555 DIP_W4BYTE(0, REG_SC_BK3B_30_L, u64_result); // input address0
2556 }
2557 else if( eWindow == DWIN1_WINDOW )
2558 {
2559 //low bound
2560 u64_result = u64BufStart;
2561 do_div(u64_result,u16BusSize);
2562 DIP_W4BYTE(0, REG_SC_BK3C_10_L, u64_result); // input address0
2563 //high bound
2564 u64_result = u64BufEnd;
2565 do_div(u64_result,u16BusSize);
2566 u64_result|=(1<<DWIN_W_LIMITE_OFT);
2567 //u64BufEnd /= u16BusSize;
2568 //u64BufEnd|=(1<<DWIN_W_LIMITE_OFT);
2569 DIP_W4BYTE(0, REG_SC_BK3C_30_L, u64_result); // input address0
2570 }
2571 else
2572 {
2573 return;
2574 }
2575 }
HAL_XC_DIP_SetBase1(void * pInstance,MS_PHY u64BufStart,MS_PHY u64BufEnd,SCALER_DIP_WIN eWindow)2576 void HAL_XC_DIP_SetBase1(void *pInstance, MS_PHY u64BufStart,MS_PHY u64BufEnd,SCALER_DIP_WIN eWindow)
2577 {
2578 MS_U16 u16BusSize = 0;
2579 MS_U64 u64_result;
2580
2581
2582 u16BusSize = HAL_XC_DIP_GetBusSize(pInstance, eWindow);
2583 if( eWindow == DIP_WINDOW )
2584 {
2585 //low bound
2586 u64_result = u64BufStart;
2587 do_div(u64_result,u16BusSize);
2588 DIP_W4BYTE(0, REG_SC_BK36_20_L, u64_result); // input address0
2589 //high bound
2590 u64_result = u64BufEnd;
2591 do_div(u64_result,u16BusSize);
2592 u64_result|=(1<<DWIN_W_LIMITE_OFT);
2593 //u64BufEnd /= u16BusSize;
2594 //u64BufEnd|=(1<<DWIN_W_LIMITE_OFT);
2595 DIP_W4BYTE(0, REG_SC_BK36_40_L, u64_result); // input address0
2596 }
2597 else if( eWindow == DWIN0_WINDOW )
2598 {
2599 //low bound
2600 u64_result = u64BufStart;
2601 do_div(u64_result,u16BusSize);
2602 DIP_W4BYTE(0, REG_SC_BK3B_20_L, u64_result); // input address0
2603 //high bound
2604 u64_result = u64BufEnd;
2605 do_div(u64_result,u16BusSize);
2606 u64_result|=(1<<DWIN_W_LIMITE_OFT);
2607 //u64BufEnd /= u16BusSize;
2608 //u64BufEnd|=(1<<DWIN_W_LIMITE_OFT);
2609 DIP_W4BYTE(0, REG_SC_BK3B_40_L, u64_result); // input address0
2610 }
2611 else if( eWindow == DWIN1_WINDOW )
2612 {
2613 //low bound
2614 u64_result = u64BufStart;
2615 do_div(u64_result,u16BusSize);
2616 DIP_W4BYTE(0, REG_SC_BK3C_20_L, u64_result); // input address0
2617 //high bound
2618 u64_result = u64BufEnd;
2619 do_div(u64_result,u16BusSize);
2620 u64_result|=(1<<DWIN_W_LIMITE_OFT);
2621 //u64BufEnd /= u16BusSize;
2622 //u64BufEnd|=(1<<DWIN_W_LIMITE_OFT);
2623 DIP_W4BYTE(0, REG_SC_BK3C_40_L, u64_result); // input address0
2624 }
2625 else
2626 {
2627 return;
2628 }
2629 }
HAL_XC_DIP_SetMiuSel(void * pInstance,MS_U8 u8MIUSel,SCALER_DIP_WIN eWindow)2630 void HAL_XC_DIP_SetMiuSel(void *pInstance, MS_U8 u8MIUSel,SCALER_DIP_WIN eWindow)
2631 {
2632 if( eWindow == DIP_WINDOW )
2633 {
2634 // Scaler control MIU by itself
2635 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
2636 DIP_W2BYTEMSK(0, REG_SC_BK7F_11_L, BIT(11), BIT(11)); // IP select (Group6 BIT11)
2637 if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_0 )
2638 {
2639 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, 0, BIT(13));
2640 DIP_W2BYTEMSK(0, REG_SC_BK36_07_L, 0, BIT(15));
2641 }
2642 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_1 )
2643 {
2644 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, BIT(13), BIT(13));
2645 DIP_W2BYTEMSK(0, REG_SC_BK36_07_L, 0, BIT(15));
2646 }
2647 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_2 )
2648 {
2649 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, 0, BIT(13));
2650 DIP_W2BYTEMSK(0, REG_SC_BK36_07_L, BIT(15), BIT(15));
2651 }
2652 else
2653 {
2654 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, BIT(13), BIT(13));
2655 DIP_W2BYTEMSK(0, REG_SC_BK36_07_L, BIT(15), BIT(15));
2656 }
2657 }
2658 else if( eWindow == DWIN0_WINDOW )
2659 {
2660 // Scaler control MIU by itself
2661 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
2662 DIP_W2BYTEMSK(0, REG_SC_BK7F_11_L, BIT(11), BIT(11)); // IP select (Group6 BIT11)
2663 if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_0 )
2664 {
2665 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, 0, BIT(13));
2666 DIP_W2BYTEMSK(0, REG_SC_BK3B_07_L, 0, BIT(15));
2667 }
2668 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_1 )
2669 {
2670 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, BIT(13), BIT(13));
2671 DIP_W2BYTEMSK(0, REG_SC_BK3B_07_L, 0, BIT(15));
2672 }
2673 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_2 )
2674 {
2675 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, 0, BIT(13));
2676 DIP_W2BYTEMSK(0, REG_SC_BK3B_07_L, BIT(15), BIT(15));
2677 }
2678 else
2679 {
2680 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, BIT(13), BIT(13));
2681 DIP_W2BYTEMSK(0, REG_SC_BK3B_07_L, BIT(15), BIT(15));
2682 }
2683 }
2684 else if( eWindow == DWIN1_WINDOW )
2685 {
2686 // Scaler control MIU by itself
2687 // So MIU1 IP-select is set to 1. At this moment, MIU0 Miu select is not working.
2688 DIP_W2BYTEMSK(0, REG_SC_BK7F_11_L, BIT(11), BIT(11)); // IP select (Group6 BIT11)
2689 if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_0 )
2690 {
2691 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, 0, BIT(13));
2692 DIP_W2BYTEMSK(0, REG_SC_BK3C_07_L, 0, BIT(15));
2693 }
2694 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_1 )
2695 {
2696 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, BIT(13), BIT(13));
2697 DIP_W2BYTEMSK(0, REG_SC_BK3C_07_L, 0, BIT(15));
2698 }
2699 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_2 )
2700 {
2701 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, 0, BIT(13));
2702 DIP_W2BYTEMSK(0, REG_SC_BK3C_07_L, BIT(15), BIT(15));
2703 }
2704 else
2705 {
2706 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, BIT(13), BIT(13));
2707 DIP_W2BYTEMSK(0, REG_SC_BK3C_07_L, BIT(15), BIT(15));
2708 }
2709 }
2710 else
2711 {
2712 //DIPR
2713 if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_0 )
2714 {
2715 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L, 0, BIT(15));
2716 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, 0, BIT(14));
2717 DIP_W2BYTEMSK(0, REG_SC_BK36_76_L, 0, BMASK(14:13));
2718 }
2719 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_1 )
2720 {
2721 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L, BIT(15), BIT(15));
2722 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, 0, BIT(14));
2723 DIP_W2BYTEMSK(0, REG_SC_BK36_76_L, BIT(13), BMASK(14:13));
2724 }
2725 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_2 )
2726 {
2727 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L, 0, BIT(15));
2728 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, BIT(14), BIT(14));
2729 DIP_W2BYTEMSK(0, REG_SC_BK36_76_L, BIT(14), BMASK(14:13));
2730 }
2731 else
2732 {
2733 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L, BIT(15), BIT(15));
2734 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, BIT(14), BIT(14));
2735 DIP_W2BYTEMSK(0, REG_SC_BK36_76_L, BMASK(14:13), BMASK(14:13));
2736 }
2737 return;
2738 }
2739 }
2740
HAL_XC_DIP_SetDIPRMiuSel(void * pInstance,MS_U8 u8MIUSel,SCALER_DIP_WIN eWindow)2741 void HAL_XC_DIP_SetDIPRMiuSel(void *pInstance, MS_U8 u8MIUSel,SCALER_DIP_WIN eWindow)
2742 {
2743 //DIPR
2744 if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_0 )
2745 {
2746 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L, 0, BIT(15));
2747 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, 0, BIT(14));
2748 DIP_W2BYTEMSK(0, REG_SC_BK36_76_L, 0, BMASK(14:13));
2749 }
2750 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_1 )
2751 {
2752 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L, BIT(15), BIT(15));
2753 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, 0, BIT(14));
2754 DIP_W2BYTEMSK(0, REG_SC_BK36_76_L, BIT(13), BMASK(14:13));
2755 }
2756 else if( ((CHIP_MIU_ID)u8MIUSel) == E_CHIP_MIU_2 )
2757 {
2758 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L, 0, BIT(15));
2759 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, BIT(14), BIT(14));
2760 DIP_W2BYTEMSK(0, REG_SC_BK36_76_L, BIT(14), BMASK(14:13));
2761 }
2762 else
2763 {
2764 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L, BIT(15), BIT(15));
2765 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L, BIT(14), BIT(14));
2766 DIP_W2BYTEMSK(0, REG_SC_BK36_76_L, BMASK(14:13), BMASK(14:13));
2767 }
2768
2769 }
2770
HAL_XC_DIP_SetY2R(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)2771 void HAL_XC_DIP_SetY2R(void *pInstance, MS_BOOL bEnable,SCALER_DIP_WIN eWindow)
2772 {
2773 if( eWindow == DIP_WINDOW )
2774 {
2775 //enable y2r
2776 DIP_W2BYTEMSK(0, REG_SC_BK36_7E_L,(bEnable?BIT(11):0),BIT(11));
2777 }
2778 else if( eWindow == DWIN0_WINDOW )
2779 {
2780 //enable y2r
2781 DIP_W2BYTEMSK(0, REG_SC_BK3B_7E_L,(bEnable?BIT(11):0),BIT(11));
2782 }
2783 else if( eWindow == DWIN1_WINDOW )
2784 {
2785 //enable y2r
2786 DIP_W2BYTEMSK(0, REG_SC_BK3C_7E_L,(bEnable?BIT(11):0),BIT(11));
2787 }
2788 else
2789 {
2790 return;
2791 }
2792 }
2793
HAL_XC_DIP_SetAlphaValue(void * pInstance,MS_U8 u8AlphaVal,SCALER_DIP_WIN eWindow)2794 void HAL_XC_DIP_SetAlphaValue(void *pInstance, MS_U8 u8AlphaVal,SCALER_DIP_WIN eWindow)
2795 {
2796 if( eWindow == DIP_WINDOW )
2797 {
2798 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, u8AlphaVal,BMASK(7:0));
2799 }
2800 else if( eWindow == DWIN0_WINDOW )
2801 {
2802 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, u8AlphaVal,BMASK(7:0));
2803 }
2804 else if( eWindow == DWIN1_WINDOW )
2805 {
2806 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, u8AlphaVal,BMASK(7:0));
2807 }
2808 else
2809 {
2810 return;
2811 }
2812 }
HAL_XC_DIP_SetUVSwap(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)2813 void HAL_XC_DIP_SetUVSwap(void *pInstance, MS_BOOL bEnable,SCALER_DIP_WIN eWindow)
2814 {
2815 // do if do Hmirror
2816 if( eWindow == DIP_WINDOW )
2817 {
2818 bDipUVSwap = bEnable;
2819 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, (bDipHMirror?(!bDipUVSwap?BIT(14):0):(bDipUVSwap?BIT(14):0)), BIT(14));
2820 }
2821 else if( eWindow == DWIN0_WINDOW )
2822 {
2823 bDWIN0UVSwap = bEnable;
2824 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, (bDWIN0HMirror?(!bDWIN0UVSwap?BIT(14):0):(bDWIN0UVSwap?BIT(14):0)) ,BIT(14));
2825 }
2826 else if( eWindow == DWIN1_WINDOW )
2827 {
2828 bDWIN1UVSwap = bEnable;
2829 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, (bDWIN1HMirror?(!bDWIN1UVSwap?BIT(14):0):(bDWIN1UVSwap?BIT(14):0)) ,BIT(14));
2830 }
2831 else
2832 {
2833 return;
2834 }
2835 }
HAL_XC_DIP_SetYCSwap(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)2836 void HAL_XC_DIP_SetYCSwap(void *pInstance, MS_BOOL bEnable,SCALER_DIP_WIN eWindow)
2837 {
2838 if( eWindow == DIP_WINDOW )
2839 {
2840 bDipYCSwap = bEnable;
2841 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, (bDipHMirror?(!bDipYCSwap?BIT(15):0):(bDipYCSwap?BIT(15):0)), BIT(15));
2842 }
2843 else if( eWindow == DWIN0_WINDOW )
2844 {
2845 bDWIN0YCSwap = bEnable;
2846 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, (bDWIN0HMirror?(!bDWIN0YCSwap?BIT(15):0):(bDWIN0YCSwap?BIT(15):0)) ,BIT(15));
2847 }
2848 else if( eWindow == DWIN1_WINDOW )
2849 {
2850 bDWIN1YCSwap = bEnable;
2851 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, (bDWIN1HMirror?(!bDWIN1YCSwap?BIT(15):0):(bDWIN1YCSwap?BIT(15):0)) ,BIT(15));
2852 }
2853 else
2854 {
2855 return;
2856 }
2857 }
HAL_XC_DIP_SetRGBSwap(void * pInstance,MS_BOOL bEnable,SCALER_DIP_WIN eWindow)2858 void HAL_XC_DIP_SetRGBSwap(void *pInstance, MS_BOOL bEnable,SCALER_DIP_WIN eWindow)
2859 {
2860 if( eWindow == DIP_WINDOW )
2861 {
2862 DIP_W2BYTEMSK(0, REG_SC_BK36_7E_L, (bEnable?BIT(13):0) ,BIT(13));
2863 }
2864 else if( eWindow == DWIN0_WINDOW )
2865 {
2866 DIP_W2BYTEMSK(0, REG_SC_BK3B_7E_L, (bEnable?BIT(13):0) ,BIT(13));
2867 }
2868 else if( eWindow == DWIN1_WINDOW )
2869 {
2870 DIP_W2BYTEMSK(0, REG_SC_BK3C_7E_L, (bEnable?BIT(13):0) ,BIT(13));
2871 }
2872 else
2873 {
2874 return;
2875 }
2876 }
HAL_XC_DIP_SetOutputCapture(void * pInstance,MS_BOOL bEnable,EN_XC_DIP_OP_CAPTURE eOpCapture,SCALER_DIP_WIN eWindow)2877 void HAL_XC_DIP_SetOutputCapture(void *pInstance, MS_BOOL bEnable,EN_XC_DIP_OP_CAPTURE eOpCapture,SCALER_DIP_WIN eWindow)
2878 {
2879 MS_BOOL bCaptureEna;
2880 MS_U16 u16CaptureSrc;
2881
2882 bCaptureEna = bEnable;
2883 switch(eOpCapture)
2884 {
2885 case E_XC_DIP_VOP2: // compatible to previous IC, overlap is before osd blending
2886 u16CaptureSrc = 0;
2887 break;
2888 case E_XC_DIP_OP2:
2889 u16CaptureSrc = 1;
2890 break;
2891 case E_XC_DIP_VIP:
2892 u16CaptureSrc = 2;
2893 break;
2894 case E_XC_DIP_BRI:
2895 u16CaptureSrc = 3;
2896 break;
2897 default:
2898 u16CaptureSrc = 0;
2899 bCaptureEna = FALSE;
2900 break;
2901 }
2902
2903 if(bCaptureEna)
2904 {
2905 DIP_W2BYTEMSK(0, REG_SC_BK0F_57_L, BIT(11), BIT(11)); // Enable
2906 if( eWindow == DIP_WINDOW )
2907 {
2908 if(eOpCapture == E_XC_DIP_VOP2)
2909 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L, 2<<14, BMASK(15:14));
2910 else if(eOpCapture == E_XC_DIP_OP2)
2911 DIP_W2BYTEMSK(0, REG_SC_BK34_7F_L, 1<<14, BMASK(15:14));
2912 else
2913 DIP_H_DBUG("[DIP] OP capture source not support\n");
2914 }
2915 else if( eWindow == DWIN0_WINDOW )
2916 {
2917 if(eOpCapture == E_XC_DIP_VOP2)
2918 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, 2<<4, BMASK(5:4));
2919 else if(eOpCapture == E_XC_DIP_OP2)
2920 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, 1<<4, BMASK(5:4));
2921 else
2922 DIP_H_DBUG("[DIP] OP capture source not support\n");
2923 }
2924 else if( eWindow == DWIN1_WINDOW )
2925 {
2926 if(eOpCapture == E_XC_DIP_VOP2)
2927 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, 2<<4, BMASK(5:4));
2928 else if(eOpCapture == E_XC_DIP_OP2)
2929 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, 1<<4, BMASK(5:4));
2930 else
2931 DIP_H_DBUG("[DIP] OP capture source not support\n");
2932 }
2933 else
2934 {
2935 return;
2936 }
2937 }
2938 }
2939
HAL_XC_DIP_SetMirror(void * pInstance,MS_BOOL bHMirror,MS_BOOL bVMirror,SCALER_DIP_WIN eWindow)2940 void HAL_XC_DIP_SetMirror(void *pInstance, MS_BOOL bHMirror,MS_BOOL bVMirror,SCALER_DIP_WIN eWindow)
2941 {
2942 EN_DRV_XC_DWIN_DATA_FMT fmt = XC_DWIN_DATA_FMT_MAX;
2943 // pixel format will swap if set Hmirror,so here do swap pixel format
2944 fmt = HAL_XC_DIP_GetDataFmt(pInstance, eWindow);
2945 if ( (XC_DWIN_DATA_FMT_YUV422 == fmt)
2946 ||(XC_DWIN_DATA_FMT_YUV420 == fmt))
2947 {
2948 if( eWindow == DIP_WINDOW )
2949 {
2950 bDipHMirror = bHMirror;
2951 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, (bDipHMirror?(!bDipUVSwap?BIT(14):0):(bDipUVSwap?BIT(14):0)), BIT(14));
2952 }
2953 else if( eWindow == DWIN0_WINDOW )
2954 {
2955 bDWIN0HMirror = bHMirror;
2956 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, (bDWIN0HMirror?(!bDWIN0UVSwap?BIT(14):0):(bDWIN0UVSwap?BIT(14):0)), BIT(14));
2957 }
2958 else if( eWindow == DWIN1_WINDOW )
2959 {
2960 bDWIN1HMirror = bHMirror;
2961 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, (bDWIN1HMirror?(!bDWIN1UVSwap?BIT(14):0):(bDWIN1UVSwap?BIT(14):0)), BIT(14));
2962 }
2963 }
2964 else if (XC_DWIN_DATA_FMT_YC422 == fmt)
2965 {
2966 if( eWindow == DIP_WINDOW )
2967 {
2968 bDipHMirror = bHMirror;
2969 DIP_W2BYTEMSK(0, REG_SC_BK36_02_L, (bDipHMirror?(!bDipYCSwap?BIT(15):0):(bDipYCSwap?BIT(15):0)), BIT(15));
2970 }
2971 else if( eWindow == DWIN0_WINDOW )
2972 {
2973 bDWIN0HMirror = bHMirror;
2974 DIP_W2BYTEMSK(0, REG_SC_BK3B_02_L, (bDWIN0HMirror?(!bDWIN0YCSwap?BIT(15):0):(bDWIN0YCSwap?BIT(15):0)), BIT(15));
2975 }
2976 else if( eWindow == DWIN1_WINDOW )
2977 {
2978 bDWIN1HMirror = bHMirror;
2979 DIP_W2BYTEMSK(0, REG_SC_BK3C_02_L, (bDWIN1HMirror?(!bDWIN1YCSwap?BIT(15):0):(bDWIN1YCSwap?BIT(15):0)), BIT(15));
2980 }
2981 }
2982
2983 if( eWindow == DIP_WINDOW )
2984 {
2985 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L, (bHMirror?BIT(9):0) ,BIT(9));
2986 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L, (bVMirror?BIT(10):0) ,BIT(10));
2987 }
2988 else if( eWindow == DWIN0_WINDOW )
2989 {
2990 DIP_W2BYTEMSK(0, REG_SC_BK3B_0B_L, (bHMirror?BIT(9):0) ,BIT(9));
2991 DIP_W2BYTEMSK(0, REG_SC_BK3B_0B_L, (bVMirror?BIT(10):0) ,BIT(10));
2992 }
2993 else if( eWindow == DWIN1_WINDOW )
2994 {
2995 DIP_W2BYTEMSK(0, REG_SC_BK3C_0B_L, (bHMirror?BIT(9):0) ,BIT(9));
2996 DIP_W2BYTEMSK(0, REG_SC_BK3C_0B_L, (bVMirror?BIT(10):0) ,BIT(10));
2997 }
2998 else
2999 {
3000 return;
3001 }
3002 }
HAL_XC_DIP_SetDIPRProperty(void * pInstance,ST_XC_DIPR_PROPERTY * pstDIPRProperty,SCALER_DIP_WIN eWindow)3003 void HAL_XC_DIP_SetDIPRProperty(void *pInstance, ST_XC_DIPR_PROPERTY *pstDIPRProperty, SCALER_DIP_WIN eWindow)
3004 {
3005 MS_BOOL bYUV = TRUE;
3006 MS_U16 u16Fmt;
3007 MS_U64 u64_result = 0;
3008 DipRFmt = (EN_DRV_XC_DWIN_DATA_FMT)pstDIPRProperty->enDataFmt;
3009 switch ((EN_DRV_XC_DWIN_DATA_FMT)pstDIPRProperty->enDataFmt)
3010 {
3011 case XC_DWIN_DATA_FMT_YUV422 :
3012 case XC_DWIN_DATA_FMT_YC422 :
3013 u16Fmt = 0;
3014 break;
3015 case XC_DWIN_DATA_FMT_RGB565 :
3016 u16Fmt = 1;
3017 break;
3018 case XC_DWIN_DATA_FMT_ARGB8888 :
3019 u16Fmt = 2;
3020 break;
3021 case XC_DWIN_DATA_FMT_YUV420 :
3022 case XC_DWIN_DATA_FMT_YUV420_H265 :
3023 case XC_DWIN_DATA_FMT_YUV420_H265_10BITS :
3024 u16Fmt = 3;
3025 break;
3026 default :
3027 u16Fmt = 0x0;
3028 break;
3029 }
3030
3031 //select 420 to 422
3032 if( (pstDIPRProperty->enDataFmt == DIP_DATA_FMT_YUV420) || (pstDIPRProperty->enDataFmt == DIP_DATA_FMT_YUV420_H265)|| (pstDIPRProperty->enDataFmt == DIP_DATA_FMT_YUV420_H265_10BITS))
3033 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L,BIT(3),BIT(3));
3034 else
3035 DIP_W2BYTEMSK(0, REG_SC_BK36_7C_L,0,BIT(3));
3036 if( ((pstDIPRProperty->enDataFmt) == DIP_DATA_FMT_RGB565) || ((pstDIPRProperty->enDataFmt) == DIP_DATA_FMT_ARGB8888))
3037 bYUV = FALSE;
3038
3039 if( eWindow == DIP_WINDOW )
3040 {
3041 //select 422 to 444
3042 DIP_W2BYTEMSK(0, REG_SC_BK34_6C_L,(bYUV?BIT(9):0),BIT(9));
3043 }
3044 else if( eWindow == DWIN0_WINDOW )
3045 {
3046 //select 422 to 444
3047 DIP_W2BYTEMSK(0, REG_SC_BK3B_78_L,(bYUV?BIT(9):0),BIT(9));
3048 }
3049 else if( eWindow == DWIN1_WINDOW )
3050 {
3051 //select 422 to 444
3052 DIP_W2BYTEMSK(0, REG_SC_BK3C_78_L,(bYUV?BIT(9):0),BIT(9));
3053 }
3054
3055 if(bDIPRotation == FALSE)
3056 DIP_W2BYTEMSK(0, REG_SC_BK34_6F_L,0x3,BIT(1)|BIT(0));
3057
3058 //Y Buffer
3059 u64_result = pstDIPRProperty->u32YBufAddr;
3060 do_div(u64_result,DWIN_BYTE_PER_WORD);
3061 DIP_W4BYTE(0, REG_SC_BK36_78_L, u64_result);
3062 //C Buffer
3063 u64_result = pstDIPRProperty->u32CBufAddr;
3064 do_div(u64_result,DWIN_BYTE_PER_WORD);
3065 DIP_W4BYTE(0, REG_SC_BK36_7A_L, u64_result);
3066 //width
3067 DIP_W2BYTE(0, REG_SC_BK36_27_L, (pstDIPRProperty->u16Width));
3068 //height
3069 DIP_W2BYTE(0, REG_SC_BK36_37_L, (pstDIPRProperty->u16Height));
3070 //Line offset
3071 DIP_W2BYTE(0, REG_SC_BK36_74_L, (pstDIPRProperty->u16Pitch));
3072 //Data Fmt
3073 DIP_W2BYTEMSK(0, REG_SC_BK36_7D_L,(u16Fmt)<<6,BMASK(7:6));
3074
3075 if(pstDIPRProperty->enDataFmt == DIP_DATA_FMT_YUV420_H265_10BITS)
3076 {
3077 //Y Buffer for EVD 10 bits
3078 u64_result = pstDIPRProperty->u32YBufAddr10Bits;
3079 do_div(u64_result,DWIN_BYTE_PER_WORD);
3080 DIP_W4BYTE(0, REG_SC_BK36_12_L, u64_result);
3081 //C Buffer for EVD 10 bits
3082 u64_result = pstDIPRProperty->u32CBufAddr10Bits;
3083 do_div(u64_result,DWIN_BYTE_PER_WORD);
3084 DIP_W4BYTE(0, REG_SC_BK36_14_L, u64_result);
3085 //Line offset for EVD 10 bits
3086 DIP_W2BYTE(0, REG_SC_BK36_1D_L, (pstDIPRProperty->u16Pitch));
3087 //Enable DIPR H265 10 bits
3088 DIP_W2BYTEMSK(0, REG_SC_BK36_17_L,BIT(15),BIT(15));
3089 }
3090 else
3091 {
3092 //Disable DIPR H265 10 bits
3093 DIP_W2BYTEMSK(0, REG_SC_BK36_17_L,0x0,BIT(15));
3094 }
3095 if( (pstDIPRProperty->enDataFmt == DIP_DATA_FMT_YUV420_H265) || (pstDIPRProperty->enDataFmt == DIP_DATA_FMT_YUV420_H265_10BITS))
3096 {
3097 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,BIT(13),BIT(13));
3098 }
3099 else
3100 {
3101 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0,BIT(13));
3102 }
3103 if(pstDIPRProperty->enDataFmt == DIP_DATA_FMT_YUV420)
3104 {
3105 DIP_W2BYTEMSK(0, REG_SC_BK36_0C_L,BIT(6),BIT(6));
3106 }
3107 else
3108 {
3109 DIP_W2BYTEMSK(0, REG_SC_BK36_0C_L,0,BIT(6));
3110 }
3111 }
3112
HAL_XC_DIP_SetDIPRProperty_MFDEC(void * pInstance,ST_DIP_MFDEC_INFO stDIPR_MFDecInfo,SCALER_DIP_WIN eWindow)3113 void HAL_XC_DIP_SetDIPRProperty_MFDEC(void *pInstance, ST_DIP_MFDEC_INFO stDIPR_MFDecInfo, SCALER_DIP_WIN eWindow)
3114 {
3115 }
3116
HAL_XC_DIP_SetDIPRProperty_DI(void * pInstance,ST_XC_DIPR_PROPERTY * pstDIPRProperty,ST_DIP_DIPR_3DDI_SETTING * stDIPR_DIInfo,SCALER_DIP_WIN eWindow)3117 void HAL_XC_DIP_SetDIPRProperty_DI(void *pInstance, ST_XC_DIPR_PROPERTY *pstDIPRProperty, ST_DIP_DIPR_3DDI_SETTING *stDIPR_DIInfo, SCALER_DIP_WIN eWindow)
3118 {
3119 }
3120
3121
HAL_XC_DIP_Rotation(void * pInstance,MS_BOOL bRotation,EN_XC_DIP_ROTATION eRoDirection,MS_PHY u64StartAddr,SCALER_DIP_WIN eTmpWindow)3122 void HAL_XC_DIP_Rotation(void *pInstance, MS_BOOL bRotation,EN_XC_DIP_ROTATION eRoDirection,MS_PHY u64StartAddr,SCALER_DIP_WIN eTmpWindow)
3123 {
3124 MS_U16 u16BusSize = 0;
3125 SCALER_DIP_WIN eWindow = eTmpWindow;
3126 bDIPRotation = bRotation;
3127 DIPRotation = eTmpWindow;
3128
3129 u16BusSize = HAL_XC_DIP_GetBusSize(pInstance,eTmpWindow);
3130 if( (u16BusSize == DIP_BYTE_PER_WORD) && (bRotation == TRUE) )
3131 {
3132 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED);
3133 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK);
3134 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK);
3135 }
3136 else if( (u16BusSize == DWIN_BYTE_PER_WORD) && (bRotation == TRUE) )
3137 {
3138 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, 0x0, CKG_FMCLK_GATED);
3139 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_256, CKG_FMCLK_MASK);
3140 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_256, CKG_SC_ROT_MASK);
3141 }
3142 else
3143 {
3144 MDrv_DIP_WriteByteMask(REG_CKG_FMCLK, CKG_FMCLK_MIU_128, CKG_FMCLK_MASK);
3145 MDrv_DIP_WriteByteMask(REG_CKG_SC_ROT, CKG_SC_ROT_MIU_128, CKG_SC_ROT_MASK);
3146 }
3147 if(bRotation)
3148 {
3149 DIP_W2BYTEMSK(0, REG_SC_BKBF_20_L,BIT(11)|BIT(3),BIT(11)|BIT(3));
3150 }
3151 else
3152 {
3153 DIP_W2BYTEMSK(0, REG_SC_BKBF_20_L,0,BIT(11)|BIT(3));
3154 }
3155
3156 //reg_rotate_mode
3157 DIP_W2BYTEMSK(0, REG_SC_BK34_10_L,eRoDirection<<14,BIT(14));
3158 //rotate destination 0:dwin0 1:dwin1 2:dip
3159 if(eTmpWindow == DIP_WINDOW )
3160 {
3161 DIP_W2BYTEMSK(0, REG_SC_BK34_6E_L,BIT(15),BMASK(15:14));
3162 }
3163 else if(eTmpWindow == DWIN0_WINDOW )
3164 {
3165 DIP_W2BYTEMSK(0, REG_SC_BK34_6E_L,0x0,BMASK(15:14));
3166 }
3167 else if(eTmpWindow == DWIN1_WINDOW )
3168 {
3169 DIP_W2BYTEMSK(0, REG_SC_BK34_6E_L,BIT(14),BMASK(15:14));
3170 }
3171
3172 }
HAL_XC_DIP_SetPinpon(void * pInstance,MS_BOOL bPinpon,MS_PHY u64PinponAddr,MS_PHY u64OffSet,SCALER_DIP_WIN eWindow)3173 void HAL_XC_DIP_SetPinpon(void *pInstance, MS_BOOL bPinpon,MS_PHY u64PinponAddr,MS_PHY u64OffSet,SCALER_DIP_WIN eWindow)
3174 {
3175 MS_U16 u16BusSize = 0;
3176 MS_U64 u64_result = 0;
3177
3178 u16BusSize = HAL_XC_DIP_GetBusSize(pInstance, eWindow);
3179 if( eWindow == DIP_WINDOW )
3180 {
3181 u64_result = u64PinponAddr;
3182 do_div(u64_result,u16BusSize);
3183 DIP_W4BYTE(0, REG_SC_BK36_20_L, u64_result);
3184 DIP_W4BYTE(0, REG_SC_BK36_50_L,u64OffSet);
3185 }
3186 else if( eWindow == DWIN0_WINDOW )
3187 {
3188 u64_result = u64PinponAddr;
3189 do_div(u64_result,u16BusSize);
3190 DIP_W4BYTE(0, REG_SC_BK3B_20_L, u64_result);
3191 DIP_W4BYTE(0, REG_SC_BK3B_50_L,u64OffSet);
3192 }
3193 else if( eWindow == DWIN1_WINDOW )
3194 {
3195 u64_result = u64PinponAddr;
3196 do_div(u64_result,u16BusSize);
3197 DIP_W4BYTE(0, REG_SC_BK3C_20_L, u64_result);
3198 DIP_W4BYTE(0, REG_SC_BK3C_50_L,u64OffSet);
3199 }
3200 }
HAL_XC_DIP_GetHVSP(void * pInstance)3201 SCALER_DIP_WIN HAL_XC_DIP_GetHVSP(void* pInstance)
3202 {
3203 return MAX_DIP_WINDOW;
3204 }
HAL_XC_DIP_SetHVSP(void * pInstance,MS_BOOL bSelect,SCALER_DIP_WIN eWindow)3205 MS_BOOL HAL_XC_DIP_SetHVSP(void* pInstance,MS_BOOL bSelect, SCALER_DIP_WIN eWindow)
3206 {
3207 return FALSE;
3208 }
3209
HAL_XC_DIP_Set420TileBlock(void * pInstance,EN_XC_DIP_TILE_BLOCK eTileBlock,SCALER_DIP_WIN eWindow)3210 MS_BOOL HAL_XC_DIP_Set420TileBlock(void* pInstance,EN_XC_DIP_TILE_BLOCK eTileBlock,SCALER_DIP_WIN eWindow)
3211 {
3212
3213 if(eTileBlock == DIP_TILE_BLOCK_R_16_32)
3214 {
3215 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0x0,BIT(13));
3216 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0x0,BIT(15));
3217 }
3218 else if(eTileBlock == DIP_TILE_BLOCK_R_32_16)
3219 {
3220 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,BIT(13),BIT(13));
3221 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0x0,BIT(15));
3222 }
3223 else if(eTileBlock == DIP_TILE_BLOCK_R_32_32)
3224 {
3225 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0x0,BIT(13));
3226 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,BIT(15),BIT(15));
3227 }
3228 else if( (eTileBlock == DIP_TILE_BLOCK_W_16_32) && (eWindow == DIP_WINDOW) )
3229 {
3230 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0x0,BIT(12));
3231 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0x0,BIT(14));
3232 }
3233 else if( (eTileBlock == DIP_TILE_BLOCK_W_32_16) && (eWindow == DIP_WINDOW) )
3234 {
3235 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,BIT(12),BIT(12));
3236 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0x0,BIT(14));
3237 }
3238 else if( (eTileBlock == DIP_TILE_BLOCK_W_32_32) && (eWindow == DIP_WINDOW) )
3239 {
3240 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,0x0,BIT(12));
3241 DIP_W2BYTEMSK(0, REG_SC_BK36_0B_L,BIT(14),BIT(14));
3242 }
3243 else
3244 return FALSE;
3245
3246 return TRUE;
3247 }
3248
HAL_XC_DIP_CallBack(InterruptNum eIntNum)3249 static void HAL_XC_DIP_CallBack(InterruptNum eIntNum)
3250 {
3251 if( (SC_R2BYTEMSK(0, REG_SC_BK36_0A_L,BMASK(7:0)) > 0) && (pDipIntCb != NULL) )
3252 (void)(pDipIntCb)(eIntNum);
3253 if( (SC_R2BYTEMSK(0, REG_SC_BK3B_0A_L,BMASK(7:0)) > 0) && (pDwin0IntCb != NULL) )
3254 (void)(pDwin0IntCb)(eIntNum);
3255 if( (SC_R2BYTEMSK(0, REG_SC_BK3C_0A_L,BMASK(7:0)) > 0) && (pDwin1IntCb != NULL) )
3256 (void)(pDwin1IntCb)(eIntNum);
3257
3258 MsOS_EnableInterrupt(E_INT_IRQ_DIPW);
3259 }
HAL_XC_DIP_InterruptAttach(void * pInstance,InterruptCb pIntCb,SCALER_DIP_WIN eWindow)3260 void HAL_XC_DIP_InterruptAttach(void *pInstance, InterruptCb pIntCb,SCALER_DIP_WIN eWindow)
3261 {
3262 if(bAttached == FALSE)
3263 {
3264 MsOS_AttachInterrupt(E_INT_IRQ_DIPW,HAL_XC_DIP_CallBack);
3265 }
3266 bAttached = TRUE;
3267
3268 if( (bDipIsr == FALSE) && (bDwin0Isr == FALSE) && (bDwin1Isr == FALSE))
3269 {
3270 MsOS_EnableInterrupt(E_INT_IRQ_DIPW);
3271 }
3272
3273 if( eWindow == DIP_WINDOW )
3274 {
3275 pDipIntCb = pIntCb;
3276 bDipIsr = TRUE;
3277 }
3278 else if( eWindow == DWIN0_WINDOW )
3279 {
3280 pDwin0IntCb = pIntCb;
3281 bDwin0Isr = TRUE;
3282 }
3283 else if( eWindow == DWIN1_WINDOW )
3284 {
3285 pDwin1IntCb = pIntCb;
3286 bDwin1Isr = TRUE;
3287 }
3288 else
3289 {
3290 return;
3291 }
3292 }
HAL_XC_DIP_InterruptDetach(void * pInstance,SCALER_DIP_WIN eWindow)3293 void HAL_XC_DIP_InterruptDetach(void *pInstance, SCALER_DIP_WIN eWindow)
3294 {
3295 if( eWindow == DIP_WINDOW )
3296 {
3297 bDipIsr = FALSE;
3298 #ifdef CONFIG_MSTAR_SRAMPD
3299 DIP_W2BYTEMSK(0, REG_SC_BK34_7E_L, BMASK(7:4) , BMASK(7:4));
3300 #endif
3301 MDrv_DIP_WriteRegBit(REG_CKG_IDCLK3, CKG_IDCLK3_GATED, CKG_IDCLK3_GATED); // Disable clock
3302 }
3303 else if( eWindow == DWIN0_WINDOW )
3304 {
3305 bDwin0Isr = FALSE;
3306 #ifdef CONFIG_MSTAR_SRAMPD
3307 DIP_W2BYTEMSK(0, REG_SC_BK3B_7F_L, BMASK(3:0) , BMASK(3:0));
3308 #endif
3309 MDrv_DIP_WriteRegBit(REG_CKG_PDW0, CKG_PDW0_GATED, CKG_PDW0_GATED); // Disable clock
3310 }
3311 else if( eWindow == DWIN1_WINDOW )
3312 {
3313 bDwin1Isr = FALSE;
3314 #ifdef CONFIG_MSTAR_SRAMPD
3315 DIP_W2BYTEMSK(0, REG_SC_BK3C_7F_L, BMASK(3:0) , BMASK(3:0));
3316 #endif
3317 MDrv_DIP_WriteRegBit(REG_CKG_PDW1, CKG_PDW1_GATED, CKG_PDW1_GATED); // Disable clock
3318 }
3319 else
3320 {
3321 return;
3322 }
3323
3324 if( (bDipIsr == FALSE) && (bDwin0Isr == FALSE) && (bDwin1Isr == FALSE))
3325 {
3326 MsOS_DisableInterrupt(E_INT_IRQ_DIPW);
3327 //MsOS_DetachInterrupt(E_INT_IRQ_DIPW); // do not deattach, because deattach will take 100 ms to wait pthread join
3328 }
3329 }
3330
HAL_XC_DIP_2P_Width_Check(void * pInstance,XC_SETWIN_INFO * pstXC_SetWin_Info,SCALER_DIP_WIN eWindow)3331 void HAL_XC_DIP_2P_Width_Check(void *pInstance, XC_SETWIN_INFO *pstXC_SetWin_Info, SCALER_DIP_WIN eWindow)
3332 {
3333 MS_U16 u16bpp = 2;
3334 MS_U16 u16alignment = 16;
3335 MS_U16 u16tmp = 0,u16MaxWith=0;
3336 MS_U64 u64_result = 0;
3337 #ifdef UTOPIA_V2
3338 DIP_INSTANCE_PRIVATE* pDipPri = NULL;
3339 DIP_SHARE_RESOURCE_PRIVATE* pDipResPri = NULL;
3340 UtopiaInstanceGetPrivate(pInstance, (void*)&pDipPri);
3341 UtopiaResourceGetPrivate(pDipPri->pShareResource,(void*)&(pDipResPri));
3342 #endif
3343 EN_DRV_XC_DWIN_DATA_FMT fmt=XC_DWIN_DATA_FMT_MAX;
3344
3345 fmt = HAL_XC_DIP_GetDataFmt(pInstance, eWindow);
3346 u16bpp = HAL_XC_DIP_GetBPP(pInstance, fmt,eWindow);
3347
3348 u64_result = DWIN_BYTE_PER_WORD;
3349 do_div(u64_result,u16bpp);
3350 u16alignment = u64_result;
3351
3352 if(g_DIPSrcInfo[eWindow].enDIPSourceType==SCALER_DIP_SOURCE_TYPE_SUB)
3353 {
3354 u64_result = pstXC_SetWin_Info->u16PreHCusScalingDst;
3355 do_div(u64_result,u16alignment);
3356 u16tmp = u64_result;
3357 }
3358 else if(g_DIPSrcInfo[eWindow].enDIPSourceType==SCALER_DIP_SOURCE_TYPE_MAIN)
3359 {
3360 u16MaxWith = DIP_R2BYTEMSK(0, REG_SC_BK01_07_L,BMASK(13:0),eWindow);
3361 if( DIP_R2BYTEMSK(0, REG_SC_BK02_0A_L,BIT(15),eWindow) && (u16MaxWith > FHD_WIDTH) )
3362 {
3363 u64_result = pstXC_SetWin_Info->u16PreHCusScalingSrc;
3364 do_div(u64_result,2);
3365 if((pstXC_SetWin_Info->u16PreHCusScalingDst) > u64_result)
3366 {
3367 pstXC_SetWin_Info->u16PreHCusScalingDst = u64_result;
3368 }
3369 }
3370 u64_result = pstXC_SetWin_Info->u16PreHCusScalingDst;
3371 do_div(u64_result,u16alignment);
3372 u16tmp = u64_result;
3373 }
3374 else if(g_DIPSrcInfo[eWindow].enDIPSourceType == SCALER_DIP_SOURCE_TYPE_DRAM)
3375 {
3376 u64_result = pstXC_SetWin_Info->u16PreHCusScalingDst;
3377 do_div(u64_result,u16alignment);
3378 u16tmp = u64_result;
3379 }
3380 else
3381 {
3382 if((pstXC_SetWin_Info->u16PreHCusScalingDst) > FHD_WIDTH)
3383 {
3384 pstXC_SetWin_Info->u16PreHCusScalingDst = FHD_WIDTH;
3385 }
3386 u64_result = pstXC_SetWin_Info->u16PreHCusScalingDst;
3387 do_div(u64_result,u16alignment);
3388 u16tmp = u64_result;
3389 }
3390 pstXC_SetWin_Info->u16PreHCusScalingDst= u16tmp*u16alignment;
3391 }
3392
3393 #ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT
HAL_XC_DIP_Check_Clock(MS_U64 * u64ReqHdl,SCALER_DIP_WIN eWindow)3394 void HAL_XC_DIP_Check_Clock(MS_U64* u64ReqHdl,SCALER_DIP_WIN eWindow)
3395 {
3396 char string_DIP_Clock[12];
3397 char DIP_345M[] = "345M";
3398 char DIP_320M[] = "320M";
3399 char DIP_216M[] = "216M";
3400 char DIP_192M[] = "192M";
3401 char DIP_170M[] = "170M";
3402 char DIP_240M[] = "240M";
3403 char DIP_NotDefine[] = "Not Define";
3404 MS_U16 u16tmp=0;
3405
3406 //DIP clock
3407 u16tmp = MDrv_ReadByte(REG_CKG_FCLK)&CKG_FCLK_MASK;
3408 if(u16tmp == CKG_FCLK_345MHZ)
3409 {
3410 strcpy(string_DIP_Clock, DIP_345M);
3411 }
3412 else if(u16tmp == CKG_FCLK_320MHZ)
3413 {
3414 strcpy(string_DIP_Clock, DIP_320M);
3415 }
3416 else if(u16tmp == CKG_FCLK_240MHZ)
3417 {
3418 strcpy(string_DIP_Clock, DIP_240M);
3419 }
3420 else if(u16tmp == CKG_FCLK_216MHZ)
3421 {
3422 strcpy(string_DIP_Clock, DIP_216M);
3423 }
3424 else if(u16tmp == CKG_FCLK_192MHZ)
3425 {
3426 strcpy(string_DIP_Clock, DIP_192M);
3427 }
3428 else if(u16tmp == CKG_FCLK_170MHZ)
3429 {
3430 strcpy(string_DIP_Clock, DIP_170M);
3431 }
3432 else
3433 {
3434 strcpy(string_DIP_Clock, DIP_NotDefine);
3435 }
3436 MdbPrint(u64ReqHdl,"DIP Clock:%s\n",string_DIP_Clock);
3437 }
3438
HAL_XC_DIP_Check_Scale(MS_U64 * u64ReqHdl,MS_U16 * u16H_Scaling_Enable,MS_U32 * u32H_Scaling_Ratio,MS_U16 * u16V_Scaling_Enable,MS_U32 * u32V_Scaling_Ratio,SCALER_DIP_WIN eWindow)3439 void HAL_XC_DIP_Check_Scale(MS_U64* u64ReqHdl,MS_U16 *u16H_Scaling_Enable, MS_U32 *u32H_Scaling_Ratio, MS_U16 *u16V_Scaling_Enable, MS_U32 *u32V_Scaling_Ratio,SCALER_DIP_WIN eWindow)
3440 {
3441 if( eWindow == DIP_WINDOW )
3442 {
3443 //HV scaling enable/ratio
3444 *u16H_Scaling_Enable = (SC_R2BYTE(0, REG_SC_BK34_6C_L) & BIT(15)) >> 15 ;
3445 *u32H_Scaling_Ratio = SC_R4BYTE(0, REG_SC_BK34_2C_L) & BMASK(22:0);
3446 *u16V_Scaling_Enable = (SC_R4BYTE(0, REG_SC_BK34_08_L) & BIT(31)) >> 31;
3447 *u32V_Scaling_Ratio = SC_R4BYTE(0, REG_SC_BK34_08_L) & BMASK(22:0);
3448 }
3449 else if( eWindow == DWIN0_WINDOW )
3450 {
3451 //HV scaling enable/ratio
3452 *u16H_Scaling_Enable = (SC_R2BYTE(0, REG_SC_BK3B_78_L) & BIT(15)) >> 15 ;
3453 *u32H_Scaling_Ratio = SC_R4BYTE(0, REG_SC_BK3B_37_L) & BMASK(22:0);
3454 *u16V_Scaling_Enable = (SC_R4BYTE(0, REG_SC_BK3B_1B_L) & BIT(31)) >> 31;
3455 *u32V_Scaling_Ratio = SC_R4BYTE(0, REG_SC_BK3B_1B_L) & BMASK(22:0);
3456 }
3457 else if( eWindow == DWIN1_WINDOW )
3458 {
3459 //HV scaling enable/ratio
3460 *u16H_Scaling_Enable = (SC_R2BYTE(0, REG_SC_BK3C_78_L) & BIT(15)) >> 15 ;
3461 *u32H_Scaling_Ratio = SC_R4BYTE(0, REG_SC_BK3C_37_L) & BMASK(22:0);
3462 *u16V_Scaling_Enable = (SC_R4BYTE(0, REG_SC_BK3C_1B_L) & BIT(31)) >> 31;
3463 *u32V_Scaling_Ratio = SC_R4BYTE(0, REG_SC_BK3C_1B_L) & BMASK(22:0);
3464 }
3465 }
3466 #endif
3467
HAL_XC_DIP_Enable(void * pInstance,MS_BOOL bEnable)3468 void HAL_XC_DIP_Enable(void *pInstance, MS_BOOL bEnable)
3469 {
3470 if(bEnable)
3471 {
3472 #ifdef MSOS_TYPE_OPTEE
3473 MDrv_WriteRegBit(REG_TZPC_NONPM_DIP, 0, BMASK(1:0));
3474 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, 0, BMASK(11:8));
3475 #endif
3476 }
3477 else
3478 {
3479 #ifdef MSOS_TYPE_OPTEE
3480 MDrv_WriteRegBit(REG_TZPC_NONPM_DIP, BMASK(1:0), BMASK(1:0));
3481 MDrv_WriteRegBit(REG_TZPC_NONPM_DWIN0, BMASK(11:8), BMASK(11:8));
3482 #endif
3483 SC_W2BYTEMSK(0, REG_SC_BK36_02_L, BIT(10) , BIT(10));
3484 SC_W2BYTEMSK(0, REG_SC_BK3B_02_L, BIT(10) , BIT(10));
3485 SC_W2BYTEMSK(0, REG_SC_BK3C_02_L, BIT(10) , BIT(10));
3486 }
3487 }
3488
3489 //=============== DIP =====================//
3490
3491 #undef MHAL_SC_C
3492
3493