1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 79 #ifndef _LPLL_TBL_H_ 80 #define _LPLL_TBL_H_ 81 82 #define LPLL_REG_NUM 41 83 84 typedef enum 85 { 86 E_PNL_SUPPORTED_LPLL_TTL_100to150MHz, //0 87 E_PNL_SUPPORTED_LPLL_TTL_50to100MHz, //1 88 E_PNL_SUPPORTED_LPLL_TTL_25to50MHz, //2 89 E_PNL_SUPPORTED_LPLL_TTL_25to25MHz, //3 90 91 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to300MHz, //4 92 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to200MHz, //5 93 94 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_8LANE_150to300MHz, //6 95 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_8LANE_150to150MHz, //7 96 97 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_4LANE_75to150MHz, //8 98 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_4LANE_75to75MHz, //9 99 100 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_2LANE_37_5to75MHz, //10 101 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_2LANE_37_5to37_5MHz, //11 102 103 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to80MHz, //12 104 E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to40MHz, //13 105 106 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to300MHz, //14 107 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to200MHz, //15 108 109 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_200to300MHz, //16 110 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_150to200MHz, //17 111 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_150to150MHz, //18 112 113 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_100to150MHz, //19 114 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_75to100MHz, //20 115 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_75to75MHz, //21 116 117 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_50to75MHz, //22 118 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_37_5to50MHz, //23 119 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_37_5to37_5MHz, //24 120 121 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_50to80MHz, //25 122 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to50MHz, //26 123 E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to40MHz, //27 124 125 E_PNL_SUPPORTED_LPLL_EPI_24_12P_150to330MHz, //28 126 E_PNL_SUPPORTED_LPLL_EPI_24_12P_150to150MHz, //29 127 128 E_PNL_SUPPORTED_LPLL_EPI_28_12P_150to330MHz, //30 129 E_PNL_SUPPORTED_LPLL_EPI_28_12P_150to150MHz, //31 130 131 E_PNL_SUPPORTED_LPLL_EPI_28_6P_180to330MHz, //32 132 E_PNL_SUPPORTED_LPLL_EPI_28_6P_150to180MHz, //33 133 E_PNL_SUPPORTED_LPLL_EPI_28_6P_150to150MHz, //34 134 135 E_PNL_SUPPORTED_LPLL_EPI_28_8P_240to330MHz, //35 136 E_PNL_SUPPORTED_LPLL_EPI_28_8P_150to240MHz, //36 137 E_PNL_SUPPORTED_LPLL_EPI_28_8P_150to150MHz, //37 138 139 E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to330MHz, //38 140 E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz, //39 141 142 E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to330MHz, //40 143 E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz, //41 144 145 E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to330MHz, //42 146 E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz, //43 147 148 E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to330MHz, //44 149 E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz, //45 150 151 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz, //46 152 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz, //47 153 E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz, //48 154 155 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz, //49 156 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz, //50 157 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz, //51 158 E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz, //52 159 160 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz, //53 161 E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz, //54 162 163 E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz, //55 164 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz, //56 165 E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz, //57 166 167 E_PNL_SUPPORTED_LPLL_MAX, //58 168 } E_PNL_SUPPORTED_LPLL_TYPE; 169 170 typedef struct 171 { 172 MS_U8 address; 173 MS_U16 value; 174 MS_U16 mask; 175 }TBLStruct,*pTBLStruct; 176 177 TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= 178 { 179 { //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 180 //Address,Value,Mask 181 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 182 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 183 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 184 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 185 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 186 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 187 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 188 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 189 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 190 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 191 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 192 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 193 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 194 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 195 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 196 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 197 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 198 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 199 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 200 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 201 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 202 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 203 {0x33,0x0020,0x0020},//reg_lpll2_pd 204 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 205 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 206 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 207 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 208 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 209 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 210 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 211 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 212 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 213 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 214 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 215 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 216 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 217 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 218 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 219 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 220 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 221 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 222 }, 223 224 { //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 225 //Address,Value,Mask 226 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 227 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 228 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 229 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 230 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 231 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 232 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 233 {0x02,0x0400,0x0F00},//reg_lpll1_output_div_second[11:8] 234 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 235 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 236 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 237 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 238 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 239 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 240 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 241 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 242 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 243 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 244 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 245 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 246 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 247 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 248 {0x33,0x0020,0x0020},//reg_lpll2_pd 249 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 250 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 251 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 252 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 253 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 254 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 255 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 256 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 257 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 258 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 259 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 260 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 261 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 262 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 263 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 264 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 265 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 266 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 267 }, 268 269 { //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 270 //Address,Value,Mask 271 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 272 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 273 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 274 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 275 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 276 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 277 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 278 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 279 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 280 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 281 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 282 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 283 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 284 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 285 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 286 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 287 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 288 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 289 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 290 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 291 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 292 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 293 {0x33,0x0020,0x0020},//reg_lpll2_pd 294 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 295 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 296 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 297 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 298 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 299 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 300 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 301 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 302 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 303 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 304 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 305 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 306 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 307 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 308 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 309 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 310 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 311 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 312 }, 313 314 { //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 315 //Address,Value,Mask 316 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 317 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 318 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 319 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 320 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 321 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 322 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 323 {0x02,0x0800,0x0F00},//reg_lpll1_output_div_second[11:8] 324 {0x35,0x7000,0x7000},//reg_lpll1_skew_div 325 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 326 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 327 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 328 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 329 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 330 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 331 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 332 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 333 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 334 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 335 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 336 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 337 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 338 {0x33,0x0020,0x0020},//reg_lpll2_pd 339 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 340 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 341 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 342 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 343 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 344 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 345 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 346 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 347 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 348 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 349 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 350 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 351 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 352 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 353 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 354 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 355 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 356 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 357 }, 358 359 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to300MHz NO.4 360 //Address,Value,Mask 361 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 362 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 363 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 364 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 365 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 366 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 367 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 368 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 369 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 370 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 371 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 372 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 373 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 374 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 375 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 376 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 377 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 378 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 379 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 380 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 381 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 382 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 383 {0x33,0x0020,0x0020},//reg_lpll2_pd 384 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 385 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 386 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 387 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 388 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 389 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 390 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 391 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 392 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 393 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 394 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 395 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 396 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 397 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 398 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 399 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 400 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 401 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 402 }, 403 404 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to200MHz NO.5 405 //Address,Value,Mask 406 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 407 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 408 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 409 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 410 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 411 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 412 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 413 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 414 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 415 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 416 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 417 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 418 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 419 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 420 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 421 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 422 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 423 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 424 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 425 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 426 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 427 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 428 {0x33,0x0020,0x0020},//reg_lpll2_pd 429 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 430 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 431 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 432 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 433 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 434 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 435 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 436 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 437 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 438 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 439 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 440 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 441 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 442 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 443 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 444 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 445 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 446 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 447 }, 448 449 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_8LANE_150to300MHz NO.6 450 //Address,Value,Mask 451 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 452 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 453 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 454 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 455 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 456 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 457 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 458 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 459 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 460 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 461 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 462 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 463 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 464 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 465 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 466 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 467 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 468 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 469 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 470 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 471 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 472 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 473 {0x33,0x0020,0x0020},//reg_lpll2_pd 474 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 475 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 476 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 477 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 478 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 479 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 480 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 481 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 482 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 483 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 484 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 485 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 486 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 487 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 488 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 489 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 490 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 491 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 492 }, 493 494 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_8LANE_150to150MHz NO.7 495 //Address,Value,Mask 496 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 497 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 498 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 499 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 500 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 501 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 502 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 503 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 504 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 505 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 506 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 507 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 508 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 509 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 510 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 511 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 512 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 513 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 514 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 515 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 516 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 517 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 518 {0x33,0x0020,0x0020},//reg_lpll2_pd 519 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 520 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 521 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 522 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 523 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 524 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 525 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 526 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 527 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 528 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 529 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 530 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 531 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 532 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 533 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 534 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 535 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 536 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 537 }, 538 539 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_4LANE_75to150MHz NO.8 540 //Address,Value,Mask 541 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 542 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 543 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 544 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 545 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 546 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 547 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 548 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 549 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 550 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 551 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 552 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 553 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 554 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 555 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 556 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 557 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 558 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 559 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 560 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 561 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 562 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 563 {0x33,0x0020,0x0020},//reg_lpll2_pd 564 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 565 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 566 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 567 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 568 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 569 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 570 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 571 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 572 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 573 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 574 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 575 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 576 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 577 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 578 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 579 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 580 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 581 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 582 }, 583 584 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_4LANE_75to75MHz NO.9 585 //Address,Value,Mask 586 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 587 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 588 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 589 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 590 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 591 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 592 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 593 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 594 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 595 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 596 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 597 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 598 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 599 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 600 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 601 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 602 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 603 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 604 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 605 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 606 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 607 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 608 {0x33,0x0020,0x0020},//reg_lpll2_pd 609 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 610 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 611 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 612 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 613 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 614 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 615 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 616 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 617 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 618 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 619 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 620 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 621 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 622 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 623 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 624 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 625 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 626 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 627 }, 628 629 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_2LANE_37_5to75MHz NO.10 630 //Address,Value,Mask 631 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 632 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 633 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 634 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 635 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 636 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 637 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 638 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 639 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 640 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 641 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 642 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 643 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 644 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 645 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 646 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 647 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 648 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 649 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 650 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 651 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 652 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 653 {0x33,0x0020,0x0020},//reg_lpll2_pd 654 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 655 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 656 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 657 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 658 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 659 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 660 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 661 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 662 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 663 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 664 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 665 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 666 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 667 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 668 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 669 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 670 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 671 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 672 }, 673 674 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_2LANE_37_5to37_5MHz NO.11 675 //Address,Value,Mask 676 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 677 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 678 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 679 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 680 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 681 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 682 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 683 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 684 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 685 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 686 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 687 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 688 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 689 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 690 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 691 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 692 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 693 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 694 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 695 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 696 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 697 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 698 {0x33,0x0020,0x0020},//reg_lpll2_pd 699 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 700 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 701 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 702 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 703 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 704 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 705 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 706 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 707 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 708 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 709 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 710 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 711 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 712 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 713 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 714 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 715 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 716 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 717 }, 718 719 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to80MHz NO.12 720 //Address,Value,Mask 721 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 722 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 723 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 724 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 725 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 726 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 727 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 728 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 729 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 730 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 731 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 732 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 733 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 734 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 735 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 736 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 737 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 738 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 739 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 740 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 741 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 742 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 743 {0x33,0x0020,0x0020},//reg_lpll2_pd 744 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 745 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 746 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 747 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 748 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 749 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 750 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 751 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 752 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 753 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 754 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 755 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 756 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 757 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 758 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 759 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 760 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 761 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 762 }, 763 764 { //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to40MHz NO.13 765 //Address,Value,Mask 766 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 767 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 768 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 769 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 770 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 771 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 772 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 773 {0x02,0x0200,0x0F00},//reg_lpll1_output_div_second[11:8] 774 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 775 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 776 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 777 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 778 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 779 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 780 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 781 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 782 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 783 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 784 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 785 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 786 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 787 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 788 {0x33,0x0020,0x0020},//reg_lpll2_pd 789 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 790 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 791 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 792 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 793 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 794 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 795 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 796 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 797 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 798 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 799 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 800 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 801 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 802 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 803 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 804 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 805 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 806 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 807 }, 808 809 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to300MHz NO.14 810 //Address,Value,Mask 811 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 812 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 813 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 814 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 815 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 816 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 817 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 818 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 819 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 820 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 821 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 822 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 823 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 824 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 825 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 826 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 827 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 828 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 829 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 830 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 831 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 832 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 833 {0x33,0x0020,0x0020},//reg_lpll2_pd 834 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 835 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 836 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 837 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 838 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 839 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 840 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 841 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 842 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 843 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 844 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 845 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 846 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 847 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 848 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 849 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 850 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 851 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 852 }, 853 854 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to200MHz NO.15 855 //Address,Value,Mask 856 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 857 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 858 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 859 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 860 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 861 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 862 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 863 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 864 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 865 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 866 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 867 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 868 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 869 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 870 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 871 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 872 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 873 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 874 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 875 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 876 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 877 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 878 {0x33,0x0020,0x0020},//reg_lpll2_pd 879 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 880 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 881 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 882 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 883 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 884 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 885 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 886 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 887 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 888 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 889 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 890 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 891 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 892 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 893 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 894 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 895 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 896 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 897 }, 898 899 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_200to300MHz NO.16 900 //Address,Value,Mask 901 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 902 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 903 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 904 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 905 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 906 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 907 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 908 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 909 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 910 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 911 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 912 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 913 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 914 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 915 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 916 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 917 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 918 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 919 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 920 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 921 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 922 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 923 {0x33,0x0020,0x0020},//reg_lpll2_pd 924 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 925 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 926 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 927 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 928 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 929 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 930 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 931 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 932 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 933 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 934 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 935 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 936 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 937 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 938 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 939 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 940 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 941 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 942 }, 943 944 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_150to200MHz NO.17 945 //Address,Value,Mask 946 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 947 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 948 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 949 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 950 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 951 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 952 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 953 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 954 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 955 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 956 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 957 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 958 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 959 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 960 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 961 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 962 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 963 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 964 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 965 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 966 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 967 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 968 {0x33,0x0020,0x0020},//reg_lpll2_pd 969 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 970 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 971 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 972 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 973 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 974 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 975 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 976 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 977 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 978 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 979 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 980 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 981 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 982 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 983 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 984 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 985 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 986 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 987 }, 988 989 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_150to150MHz NO.18 990 //Address,Value,Mask 991 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 992 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 993 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 994 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 995 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 996 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 997 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 998 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 999 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1000 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1001 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1002 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1003 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1004 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1005 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1006 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1007 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1008 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1009 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1010 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1011 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1012 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1013 {0x33,0x0020,0x0020},//reg_lpll2_pd 1014 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1015 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1016 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1017 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1018 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1019 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1020 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1021 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1022 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1023 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1024 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1025 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1026 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1027 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1028 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1029 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1030 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1031 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1032 }, 1033 1034 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_100to150MHz NO.19 1035 //Address,Value,Mask 1036 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1037 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1038 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1039 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1040 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1041 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 1042 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1043 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1044 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1045 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1046 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1047 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1048 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1049 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1050 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1051 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1052 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1053 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1054 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1055 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1056 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1057 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1058 {0x33,0x0020,0x0020},//reg_lpll2_pd 1059 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1060 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1061 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1062 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1063 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1064 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1065 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1066 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1067 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1068 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1069 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1070 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1071 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1072 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1073 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1074 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1075 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1076 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1077 }, 1078 1079 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_75to100MHz NO.20 1080 //Address,Value,Mask 1081 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1082 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1083 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1084 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1085 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1086 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1087 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1088 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1089 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1090 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1091 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1092 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1093 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1094 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1095 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1096 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1097 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1098 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1099 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1100 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1101 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1102 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1103 {0x33,0x0020,0x0020},//reg_lpll2_pd 1104 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1105 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1106 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1107 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1108 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1109 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1110 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1111 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1112 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1113 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1114 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1115 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1116 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1117 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1118 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1119 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1120 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1121 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1122 }, 1123 1124 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_75to75MHz NO.21 1125 //Address,Value,Mask 1126 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1127 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1128 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1129 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1130 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1131 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1132 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1133 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1134 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1135 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1136 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1137 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1138 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1139 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1140 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1141 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1142 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1143 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1144 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1145 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1146 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1147 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1148 {0x33,0x0020,0x0020},//reg_lpll2_pd 1149 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1150 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1151 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1152 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1153 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1154 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1155 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1156 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1157 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1158 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1159 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1160 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1161 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1162 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1163 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1164 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1165 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1166 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1167 }, 1168 1169 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_50to75MHz NO.22 1170 //Address,Value,Mask 1171 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1172 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1173 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1174 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1175 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1176 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1177 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1178 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1179 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1180 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1181 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1182 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1183 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1184 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1185 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1186 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1187 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1188 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1189 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1190 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1191 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1192 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1193 {0x33,0x0020,0x0020},//reg_lpll2_pd 1194 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1195 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1196 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1197 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1198 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1199 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1200 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1201 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1202 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1203 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1204 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1205 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1206 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1207 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1208 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1209 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1210 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1211 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1212 }, 1213 1214 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_37_5to50MHz NO.23 1215 //Address,Value,Mask 1216 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1217 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1218 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1219 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1220 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1221 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1222 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1223 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1224 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1225 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1226 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1227 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1228 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1229 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1230 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1231 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1232 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1233 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1234 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1235 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1236 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1237 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1238 {0x33,0x0020,0x0020},//reg_lpll2_pd 1239 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1240 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1241 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1242 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1243 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1244 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1245 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1246 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1247 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1248 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1249 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1250 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1251 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1252 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1253 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1254 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1255 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1256 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1257 }, 1258 1259 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_37_5to37_5MHz NO.24 1260 //Address,Value,Mask 1261 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1262 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1263 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1264 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1265 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1266 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1267 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1268 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1269 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1270 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1271 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1272 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1273 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1274 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1275 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1276 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1277 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1278 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1279 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1280 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1281 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1282 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1283 {0x33,0x0020,0x0020},//reg_lpll2_pd 1284 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1285 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1286 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1287 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1288 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1289 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1290 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1291 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1292 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1293 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1294 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1295 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1296 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1297 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1298 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1299 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1300 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1301 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1302 }, 1303 1304 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_50to80MHz NO.25 1305 //Address,Value,Mask 1306 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1307 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1308 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1309 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1310 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1311 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1312 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1313 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1314 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1315 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1316 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1317 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1318 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1319 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1320 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1321 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1322 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1323 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1324 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1325 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1326 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1327 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1328 {0x33,0x0020,0x0020},//reg_lpll2_pd 1329 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1330 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1331 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1332 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1333 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1334 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1335 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1336 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1337 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1338 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1339 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1340 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1341 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1342 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1343 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1344 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1345 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1346 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1347 }, 1348 1349 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to50MHz NO.26 1350 //Address,Value,Mask 1351 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1352 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1353 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1354 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1355 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1356 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1357 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1358 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1359 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1360 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1361 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1362 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1363 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1364 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1365 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1366 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1367 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1368 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1369 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1370 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1371 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1372 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1373 {0x33,0x0020,0x0020},//reg_lpll2_pd 1374 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1375 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1376 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1377 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1378 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1379 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1380 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1381 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1382 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1383 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1384 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1385 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1386 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1387 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1388 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1389 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1390 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1391 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1392 }, 1393 1394 { //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to40MHz NO.27 1395 //Address,Value,Mask 1396 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1397 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1398 {0x01,0x0003,0x0003},//reg_lpll1_loop_div_first 1399 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1400 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1401 {0x02,0x3000,0x3000},//reg_lpll1_output_div_second[13:12] 1402 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1403 {0x02,0x0300,0x0F00},//reg_lpll1_output_div_second[11:8] 1404 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 1405 {0x2E,0x0004,0x0007},//reg_lpll1_fifo_div 1406 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1407 {0x2E,0x0000,0x1000},//reg_lpll1_en_fix_clk 1408 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1409 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1410 {0x03,0x0400,0x0400},//reg_lpll1_sdiv2p5_en 1411 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1412 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1413 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1414 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 1415 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1416 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1417 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1418 {0x33,0x0020,0x0020},//reg_lpll2_pd 1419 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1420 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1421 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1422 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 1423 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1424 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1425 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 1426 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1427 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1428 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1429 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1430 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1431 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 1432 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1433 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1434 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1435 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1436 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1437 }, 1438 1439 { //E_PNL_SUPPORTED_LPLL_EPI_24_12P_150to330MHz NO.28 1440 //Address,Value,Mask 1441 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1442 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1443 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1444 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1445 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1446 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1447 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1448 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1449 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1450 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1451 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1452 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1453 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1454 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1455 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1456 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1457 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1458 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1459 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1460 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1461 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1462 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1463 {0x33,0x0000,0x0020},//reg_lpll2_pd 1464 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1465 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1466 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1467 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1468 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1469 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1470 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1471 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1472 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1473 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1474 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1475 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1476 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1477 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1478 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1479 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1480 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1481 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1482 }, 1483 1484 { //E_PNL_SUPPORTED_LPLL_EPI_24_12P_150to150MHz NO.29 1485 //Address,Value,Mask 1486 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1487 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1488 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1489 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1490 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 1491 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1492 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1493 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1494 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1495 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1496 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1497 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1498 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1499 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1500 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1501 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1502 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1503 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1504 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1505 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1506 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1507 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1508 {0x33,0x0000,0x0020},//reg_lpll2_pd 1509 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1510 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1511 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1512 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1513 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1514 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1515 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1516 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1517 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1518 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1519 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1520 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1521 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1522 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1523 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1524 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1525 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1526 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1527 }, 1528 1529 { //E_PNL_SUPPORTED_LPLL_EPI_28_12P_150to330MHz NO.30 1530 //Address,Value,Mask 1531 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1532 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1533 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1534 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1535 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1536 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1537 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1538 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1539 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1540 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1541 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1542 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1543 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1544 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1545 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1546 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1547 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1548 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1549 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1550 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1551 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1552 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1553 {0x33,0x0000,0x0020},//reg_lpll2_pd 1554 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1555 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1556 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1557 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1558 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1559 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1560 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1561 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1562 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1563 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1564 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1565 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1566 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1567 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1568 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1569 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1570 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1571 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1572 }, 1573 1574 { //E_PNL_SUPPORTED_LPLL_EPI_28_12P_150to150MHz NO.31 1575 //Address,Value,Mask 1576 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1577 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1578 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1579 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1580 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1581 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1582 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1583 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1584 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1585 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1586 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1587 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1588 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1589 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1590 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1591 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1592 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1593 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1594 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1595 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1596 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1597 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1598 {0x33,0x0000,0x0020},//reg_lpll2_pd 1599 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1600 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1601 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1602 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1603 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1604 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1605 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1606 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1607 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1608 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1609 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1610 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1611 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1612 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1613 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1614 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1615 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1616 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1617 }, 1618 1619 { //E_PNL_SUPPORTED_LPLL_EPI_28_6P_180to330MHz NO.32 1620 //Address,Value,Mask 1621 {0x03,0x0014,0x001C},//reg_lpll1_ibias_ictrl 1622 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1623 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1624 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1625 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1626 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1627 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1628 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1629 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1630 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1631 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1632 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1633 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1634 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1635 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1636 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1637 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1638 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1639 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1640 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1641 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1642 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1643 {0x33,0x0000,0x0020},//reg_lpll2_pd 1644 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1645 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1646 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1647 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1648 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1649 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1650 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1651 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1652 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1653 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1654 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1655 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1656 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1657 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1658 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1659 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1660 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1661 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1662 }, 1663 1664 { //E_PNL_SUPPORTED_LPLL_EPI_28_6P_150to180MHz NO.33 1665 //Address,Value,Mask 1666 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1667 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1668 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1669 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1670 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1671 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1672 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1673 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1674 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1675 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1676 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1677 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1678 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1679 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1680 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1681 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1682 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1683 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1684 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1685 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1686 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1687 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1688 {0x33,0x0000,0x0020},//reg_lpll2_pd 1689 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1690 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1691 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1692 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1693 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1694 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1695 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1696 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1697 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1698 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1699 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1700 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1701 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1702 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1703 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1704 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1705 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1706 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1707 }, 1708 1709 { //E_PNL_SUPPORTED_LPLL_EPI_28_6P_150to150MHz NO.34 1710 //Address,Value,Mask 1711 {0x03,0x000C,0x001C},//reg_lpll1_ibias_ictrl 1712 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1713 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1714 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1715 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1716 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1717 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1718 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1719 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1720 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1721 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1722 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1723 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1724 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1725 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1726 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1727 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1728 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1729 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1730 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1731 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1732 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1733 {0x33,0x0000,0x0020},//reg_lpll2_pd 1734 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1735 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1736 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1737 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1738 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1739 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1740 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1741 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1742 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1743 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 1744 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1745 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1746 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1747 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1748 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1749 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1750 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1751 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1752 }, 1753 1754 { //E_PNL_SUPPORTED_LPLL_EPI_28_8P_240to330MHz NO.35 1755 //Address,Value,Mask 1756 {0x03,0x0008,0x001C},//reg_lpll1_ibias_ictrl 1757 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1758 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1759 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1760 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1761 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1762 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1763 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1764 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1765 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1766 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1767 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1768 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1769 {0x2E,0x8000,0x8000},//reg_lpll1_dual_lp_en 1770 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1771 {0x2E,0x0000,0x4000},//reg_lpll1_en_mini 1772 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1773 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1774 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1775 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1776 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1777 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1778 {0x33,0x0000,0x0020},//reg_lpll2_pd 1779 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1780 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1781 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1782 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1783 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1784 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1785 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1786 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1787 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1788 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1789 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1790 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1791 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1792 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1793 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1794 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1795 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1796 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1797 }, 1798 1799 { //E_PNL_SUPPORTED_LPLL_EPI_28_8P_150to240MHz NO.36 1800 //Address,Value,Mask 1801 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1802 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1803 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1804 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1805 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1806 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1807 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1808 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1809 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1810 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1811 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1812 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1813 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1814 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1815 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1816 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1817 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1818 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1819 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1820 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1821 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1822 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1823 {0x33,0x0000,0x0020},//reg_lpll2_pd 1824 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1825 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1826 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1827 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1828 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1829 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1830 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1831 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1832 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1833 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1834 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1835 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1836 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1837 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1838 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1839 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1840 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1841 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1842 }, 1843 1844 { //E_PNL_SUPPORTED_LPLL_EPI_28_8P_150to150MHz NO.37 1845 //Address,Value,Mask 1846 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1847 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1848 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 1849 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1850 {0x01,0x0700,0x0F00},//reg_lpll1_loop_div_second 1851 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1852 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1853 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1854 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1855 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1856 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 1857 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1858 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1859 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1860 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1861 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1862 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1863 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 1864 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1865 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1866 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1867 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1868 {0x33,0x0000,0x0020},//reg_lpll2_pd 1869 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1870 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1871 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1872 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1873 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1874 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1875 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1876 {0x39,0x0800,0x0800},//reg_lpll2_test[11] 1877 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1878 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1879 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1880 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 1881 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1882 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1883 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1884 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1885 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1886 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1887 }, 1888 1889 { //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to330MHz NO.38 1890 //Address,Value,Mask 1891 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1892 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1893 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1894 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1895 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1896 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1897 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1898 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1899 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1900 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1901 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1902 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1903 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1904 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1905 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1906 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1907 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1908 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1909 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1910 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1911 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1912 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1913 {0x33,0x0000,0x0020},//reg_lpll2_pd 1914 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1915 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1916 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1917 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1918 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1919 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1920 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1921 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1922 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1923 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1924 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1925 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1926 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1927 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1928 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1929 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1930 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1931 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1932 }, 1933 1934 { //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.39 1935 //Address,Value,Mask 1936 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1937 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1938 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1939 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1940 {0x01,0x0500,0x0F00},//reg_lpll1_loop_div_second 1941 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 1942 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1943 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 1944 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1945 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1946 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1947 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1948 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1949 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1950 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1951 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1952 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1953 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1954 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 1955 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 1956 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1957 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 1958 {0x33,0x0000,0x0020},//reg_lpll2_pd 1959 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1960 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 1961 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 1962 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 1963 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1964 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 1965 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 1966 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 1967 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1968 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 1969 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1970 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 1971 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 1972 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 1973 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 1974 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1975 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 1976 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 1977 }, 1978 1979 { //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to330MHz NO.40 1980 //Address,Value,Mask 1981 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 1982 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 1983 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 1984 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1985 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 1986 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 1987 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1988 {0x02,0x0500,0x0F00},//reg_lpll1_output_div_second[11:8] 1989 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 1990 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 1991 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 1992 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 1993 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1994 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 1995 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 1996 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 1997 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 1998 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 1999 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2000 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2001 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2002 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2003 {0x33,0x0000,0x0020},//reg_lpll2_pd 2004 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2005 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 2006 {0x30,0x0005,0x001F},//reg_lpll2_input_div_first 2007 {0x31,0x0001,0x0003},//reg_lpll2_loop_div_first 2008 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2009 {0x31,0x0900,0x1F00},//reg_lpll2_loop_div_second 2010 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2011 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2012 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2013 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2014 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2015 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2016 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2017 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2018 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2019 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2020 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2021 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2022 }, 2023 2024 { //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.41 2025 //Address,Value,Mask 2026 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2027 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2028 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2029 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2030 {0x01,0x0400,0x0F00},//reg_lpll1_loop_div_second 2031 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 2032 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2033 {0x02,0x0500,0x0F00},//reg_lpll1_output_div_second[11:8] 2034 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2035 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2036 {0x03,0x0800,0x0800},//reg_lpll1_fifo_div5_en 2037 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2038 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2039 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2040 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2041 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2042 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2043 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2044 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2045 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2046 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2047 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2048 {0x33,0x0000,0x0020},//reg_lpll2_pd 2049 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2050 {0x33,0x0004,0x0004},//reg_lpll2_ibias_ictrl 2051 {0x30,0x0005,0x001F},//reg_lpll2_input_div_first 2052 {0x31,0x0001,0x0003},//reg_lpll2_loop_div_first 2053 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2054 {0x31,0x0900,0x1F00},//reg_lpll2_loop_div_second 2055 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2056 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2057 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2058 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2059 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2060 {0x39,0x0100,0x0100},//reg_lpll2_test[8] 2061 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2062 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2063 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2064 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2065 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2066 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2067 }, 2068 2069 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to330MHz NO.42 2070 //Address,Value,Mask 2071 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2072 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2073 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2074 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2075 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 2076 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2077 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2078 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2079 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2080 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2081 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2082 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2083 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2084 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2085 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2086 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2087 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2088 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2089 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2090 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2091 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2092 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2093 {0x33,0x0000,0x0020},//reg_lpll2_pd 2094 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2095 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2096 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2097 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2098 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2099 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2100 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2101 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2102 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2103 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2104 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2105 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2106 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2107 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2108 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 2109 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2110 {0x38,0x0100,0x0100},//reg_lpll1_scalar2fifo_div2 2111 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2112 }, 2113 2114 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.43 2115 //Address,Value,Mask 2116 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2117 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2118 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2119 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2120 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 2121 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2122 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2123 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2124 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2125 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2126 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2127 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2128 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2129 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2130 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2131 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2132 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2133 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2134 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2135 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2136 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2137 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2138 {0x33,0x0000,0x0020},//reg_lpll2_pd 2139 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2140 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2141 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2142 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2143 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2144 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2145 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2146 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2147 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2148 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2149 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2150 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2151 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2152 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2153 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 2154 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2155 {0x38,0x0100,0x0100},//reg_lpll1_scalar2fifo_div2 2156 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2157 }, 2158 2159 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to330MHz NO.44 2160 //Address,Value,Mask 2161 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2162 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2163 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2164 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2165 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 2166 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2167 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2168 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2169 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2170 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2171 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2172 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2173 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2174 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2175 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2176 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2177 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2178 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2179 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2180 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2181 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2182 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2183 {0x33,0x0000,0x0020},//reg_lpll2_pd 2184 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2185 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2186 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2187 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2188 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2189 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2190 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2191 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2192 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2193 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2194 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2195 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2196 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2197 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2198 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 2199 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2200 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2201 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2202 }, 2203 2204 { //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz NO.45 2205 //Address,Value,Mask 2206 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2207 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2208 {0x01,0x0001,0x0003},//reg_lpll1_loop_div_first 2209 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2210 {0x01,0x0900,0x0F00},//reg_lpll1_loop_div_second 2211 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2212 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2213 {0x02,0x0000,0x0F00},//reg_lpll1_output_div_second[11:8] 2214 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2215 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2216 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2217 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2218 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2219 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2220 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2221 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2222 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2223 {0x2E,0x0040,0x0040},//reg_lpll1_en_fifo 2224 {0x36,0x8000,0x8000},//reg_lpll1__test[15] 2225 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2226 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2227 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2228 {0x33,0x0000,0x0020},//reg_lpll2_pd 2229 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2230 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2231 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2232 {0x31,0x0003,0x0003},//reg_lpll2_loop_div_first 2233 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2234 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2235 {0x32,0x0001,0x000F},//reg_lpll2_output_div_first 2236 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2237 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2238 {0x39,0x1000,0x1000},//reg_lpll2_test[12] 2239 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2240 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2241 {0x35,0x0020,0x0020},//reg_lpll_2ndpll_clk_sel 2242 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2243 {0x38,0x0200,0x0200},//reg_lpll1_scalar2fifo_en 2244 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2245 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2246 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2247 }, 2248 2249 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.46 2250 //Address,Value,Mask 2251 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2252 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2253 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2254 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2255 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2256 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 2257 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2258 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2259 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2260 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2261 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2262 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2263 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2264 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2265 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2266 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2267 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2268 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2269 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2270 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2271 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2272 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2273 {0x33,0x0020,0x0020},//reg_lpll2_pd 2274 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2275 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2276 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2277 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2278 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2279 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2280 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2281 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2282 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2283 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2284 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2285 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2286 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2287 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2288 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2289 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2290 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2291 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2292 }, 2293 2294 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.47 2295 //Address,Value,Mask 2296 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2297 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2298 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2299 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2300 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2301 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2302 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2303 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2304 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2305 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2306 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2307 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2308 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2309 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2310 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2311 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2312 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2313 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2314 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2315 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2316 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2317 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2318 {0x33,0x0020,0x0020},//reg_lpll2_pd 2319 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2320 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2321 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2322 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2323 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2324 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2325 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2326 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2327 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2328 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2329 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2330 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2331 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2332 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2333 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2334 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2335 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2336 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2337 }, 2338 2339 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.48 2340 //Address,Value,Mask 2341 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2342 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2343 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2344 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2345 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2346 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2347 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2348 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2349 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2350 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2351 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2352 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2353 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2354 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2355 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2356 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2357 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2358 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2359 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2360 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2361 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2362 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2363 {0x33,0x0020,0x0020},//reg_lpll2_pd 2364 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2365 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2366 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2367 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2368 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2369 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2370 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2371 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2372 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2373 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2374 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2375 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2376 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2377 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2378 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2379 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2380 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2381 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2382 }, 2383 2384 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.49 2385 //Address,Value,Mask 2386 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2387 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2388 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2389 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2390 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2391 {0x02,0x0000,0x3000},//reg_lpll1_output_div_second[13:12] 2392 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2393 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2394 {0x35,0x0000,0x7000},//reg_lpll1_skew_div 2395 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2396 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2397 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2398 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2399 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2400 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2401 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2402 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2403 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2404 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2405 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2406 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2407 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2408 {0x33,0x0020,0x0020},//reg_lpll2_pd 2409 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2410 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2411 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2412 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2413 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2414 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2415 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2416 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2417 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2418 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2419 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2420 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2421 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2422 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2423 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2424 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2425 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2426 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2427 }, 2428 2429 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.50 2430 //Address,Value,Mask 2431 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2432 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2433 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2434 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2435 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2436 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2437 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2438 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2439 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2440 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2441 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2442 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2443 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2444 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2445 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2446 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2447 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2448 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2449 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2450 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2451 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2452 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2453 {0x33,0x0020,0x0020},//reg_lpll2_pd 2454 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2455 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2456 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2457 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2458 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2459 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2460 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2461 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2462 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2463 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2464 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2465 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2466 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2467 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2468 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2469 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2470 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2471 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2472 }, 2473 2474 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.51 2475 //Address,Value,Mask 2476 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2477 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2478 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2479 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2480 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2481 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2482 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2483 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2484 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2485 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2486 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2487 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2488 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2489 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2490 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2491 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2492 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2493 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2494 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2495 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2496 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2497 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2498 {0x33,0x0020,0x0020},//reg_lpll2_pd 2499 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2500 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2501 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2502 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2503 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2504 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2505 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2506 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2507 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2508 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2509 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2510 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2511 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2512 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2513 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2514 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2515 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2516 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2517 }, 2518 2519 { //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.52 2520 //Address,Value,Mask 2521 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2522 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2523 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2524 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2525 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2526 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2527 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2528 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2529 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2530 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2531 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2532 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2533 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2534 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2535 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2536 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2537 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2538 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2539 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2540 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2541 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2542 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2543 {0x33,0x0020,0x0020},//reg_lpll2_pd 2544 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2545 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2546 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2547 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2548 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2549 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2550 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2551 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2552 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2553 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2554 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2555 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2556 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2557 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2558 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2559 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2560 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2561 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2562 }, 2563 2564 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.53 2565 //Address,Value,Mask 2566 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2567 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2568 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2569 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2570 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2571 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2572 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2573 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2574 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2575 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2576 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2577 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2578 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2579 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2580 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2581 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2582 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2583 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2584 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2585 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2586 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2587 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2588 {0x33,0x0020,0x0020},//reg_lpll2_pd 2589 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2590 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2591 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2592 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2593 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2594 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2595 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2596 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2597 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2598 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2599 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2600 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2601 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2602 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2603 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2604 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2605 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2606 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2607 }, 2608 2609 { //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.54 2610 //Address,Value,Mask 2611 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2612 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2613 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2614 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2615 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2616 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2617 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2618 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2619 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2620 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2621 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2622 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2623 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2624 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2625 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2626 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2627 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2628 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2629 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2630 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2631 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2632 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2633 {0x33,0x0020,0x0020},//reg_lpll2_pd 2634 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2635 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2636 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2637 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2638 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2639 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2640 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2641 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2642 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2643 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2644 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2645 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2646 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2647 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2648 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2649 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2650 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2651 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2652 }, 2653 2654 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz NO.55 2655 //Address,Value,Mask 2656 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2657 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2658 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2659 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2660 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2661 {0x02,0x1000,0x3000},//reg_lpll1_output_div_second[13:12] 2662 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2663 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2664 {0x35,0x1000,0x7000},//reg_lpll1_skew_div 2665 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2666 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2667 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2668 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2669 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2670 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2671 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2672 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2673 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2674 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2675 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2676 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2677 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2678 {0x33,0x0020,0x0020},//reg_lpll2_pd 2679 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2680 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2681 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2682 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2683 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2684 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2685 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2686 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2687 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2688 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2689 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2690 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2691 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2692 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2693 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2694 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2695 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2696 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2697 }, 2698 2699 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.56 2700 //Address,Value,Mask 2701 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2702 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2703 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2704 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2705 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2706 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2707 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2708 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2709 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2710 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2711 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2712 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2713 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2714 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2715 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2716 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2717 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2718 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2719 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2720 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2721 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2722 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2723 {0x33,0x0020,0x0020},//reg_lpll2_pd 2724 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2725 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2726 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2727 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2728 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2729 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2730 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2731 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2732 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2733 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2734 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2735 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2736 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2737 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2738 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2739 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2740 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2741 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2742 }, 2743 2744 { //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.57 2745 //Address,Value,Mask 2746 {0x03,0x0004,0x001C},//reg_lpll1_ibias_ictrl 2747 {0x15,0x0000,0x0003},//reg_lpll1_input_div_first 2748 {0x01,0x0002,0x0003},//reg_lpll1_loop_div_first 2749 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2750 {0x01,0x0300,0x0F00},//reg_lpll1_loop_div_second 2751 {0x02,0x2000,0x3000},//reg_lpll1_output_div_second[13:12] 2752 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2753 {0x02,0x0700,0x0F00},//reg_lpll1_output_div_second[11:8] 2754 {0x35,0x2000,0x7000},//reg_lpll1_skew_div 2755 {0x2E,0x0000,0x0007},//reg_lpll1_fifo_div 2756 {0x03,0x0000,0x0800},//reg_lpll1_fifo_div5_en 2757 {0x2E,0x1000,0x1000},//reg_lpll1_en_fix_clk 2758 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2759 {0x2E,0x0000,0x8000},//reg_lpll1_dual_lp_en 2760 {0x03,0x0000,0x0400},//reg_lpll1_sdiv2p5_en 2761 {0x2E,0x4000,0x4000},//reg_lpll1_en_mini 2762 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2763 {0x2E,0x0000,0x0040},//reg_lpll1_en_fifo 2764 {0x36,0x0000,0x8000},//reg_lpll1__test[15] 2765 {0x37,0x0000,0x0001},//reg_lpll1__test[16] 2766 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2767 {0x37,0x0000,0x0040},//reg_lpll1__test[22] 2768 {0x33,0x0020,0x0020},//reg_lpll2_pd 2769 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2770 {0x33,0x0000,0x0004},//reg_lpll2_ibias_ictrl 2771 {0x30,0x0000,0x001F},//reg_lpll2_input_div_first 2772 {0x31,0x0000,0x0003},//reg_lpll2_loop_div_first 2773 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2774 {0x31,0x0000,0x1F00},//reg_lpll2_loop_div_second 2775 {0x32,0x0000,0x000F},//reg_lpll2_output_div_first 2776 {0x39,0x0000,0x0800},//reg_lpll2_test[11] 2777 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2778 {0x39,0x0000,0x1000},//reg_lpll2_test[12] 2779 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2780 {0x39,0x0000,0x0100},//reg_lpll2_test[8] 2781 {0x35,0x0000,0x0020},//reg_lpll_2ndpll_clk_sel 2782 {0x2E,0x0010,0x0010},//reg_lpll_en_scalar 2783 {0x38,0x0000,0x0200},//reg_lpll1_scalar2fifo_en 2784 {0xFF,0x0032,0xFFFF},//wait_time(micro_second) 2785 {0x38,0x0000,0x0100},//reg_lpll1_scalar2fifo_div2 2786 {0x36,0x0000,0x0004},//reg_lpll1__test[2] 2787 }, 2788 2789 }; 2790 MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= 2791 { 2792 12, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 2793 12, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 2794 12, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 2795 12, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 2796 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to300MHz NO.4 2797 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to200MHz NO.5 2798 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_8LANE_150to300MHz NO.6 2799 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_8LANE_150to150MHz NO.7 2800 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_4LANE_75to150MHz NO.8 2801 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_4LANE_75to75MHz NO.9 2802 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_2LANE_37_5to75MHz NO.10 2803 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_2LANE_37_5to37_5MHz NO.11 2804 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to80MHz NO.12 2805 32, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to40MHz NO.13 2806 64, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to300MHz NO.14 2807 64, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to200MHz NO.15 2808 64, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_200to300MHz NO.16 2809 64, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_150to200MHz NO.17 2810 64, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_150to150MHz NO.18 2811 64, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_100to150MHz NO.19 2812 64, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_75to100MHz NO.20 2813 64, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_75to75MHz NO.21 2814 32, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_50to75MHz NO.22 2815 32, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_37_5to50MHz NO.23 2816 32, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_37_5to37_5MHz NO.24 2817 32, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_50to80MHz NO.25 2818 32, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to50MHz NO.26 2819 32, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to40MHz NO.27 2820 8, //E_PNL_SUPPORTED_LPLL_EPI_24_12P_150to330MHz NO.28 2821 8, //E_PNL_SUPPORTED_LPLL_EPI_24_12P_150to150MHz NO.29 2822 8, //E_PNL_SUPPORTED_LPLL_EPI_28_12P_150to330MHz NO.30 2823 8, //E_PNL_SUPPORTED_LPLL_EPI_28_12P_150to150MHz NO.31 2824 8, //E_PNL_SUPPORTED_LPLL_EPI_28_6P_180to330MHz NO.32 2825 8, //E_PNL_SUPPORTED_LPLL_EPI_28_6P_150to180MHz NO.33 2826 8, //E_PNL_SUPPORTED_LPLL_EPI_28_6P_150to150MHz NO.34 2827 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8P_240to330MHz NO.35 2828 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8P_150to240MHz NO.36 2829 8, //E_PNL_SUPPORTED_LPLL_EPI_28_8P_150to150MHz NO.37 2830 8, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to330MHz NO.38 2831 8, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.39 2832 72, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to330MHz NO.40 2833 72, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.41 2834 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to330MHz NO.42 2835 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.43 2836 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to330MHz NO.44 2837 8, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz NO.45 2838 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.46 2839 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.47 2840 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.48 2841 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.49 2842 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.50 2843 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.51 2844 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.52 2845 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.53 2846 12, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.54 2847 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz NO.55 2848 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.56 2849 12, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.57 2850 }; 2851 MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= 2852 { 2853 8, //E_PNL_SUPPORTED_LPLL_TTL_100to150MHz NO.0 2854 16, //E_PNL_SUPPORTED_LPLL_TTL_50to100MHz NO.1 2855 32, //E_PNL_SUPPORTED_LPLL_TTL_25to50MHz NO.2 2856 32, //E_PNL_SUPPORTED_LPLL_TTL_25to25MHz NO.3 2857 10, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to300MHz NO.4 2858 10, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_16LANE_200to200MHz NO.5 2859 10, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_8LANE_150to300MHz NO.6 2860 10, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_8LANE_150to150MHz NO.7 2861 20, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_4LANE_75to150MHz NO.8 2862 20, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_4LANE_75to75MHz NO.9 2863 40, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_2LANE_37_5to75MHz NO.10 2864 40, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_2LANE_37_5to37_5MHz NO.11 2865 40, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to80MHz NO.12 2866 40, //E_PNL_SUPPORTED_LPLL_VBY1_10BIT_1LANE_40to40MHz NO.13 2867 15, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to300MHz NO.14 2868 15, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_16LANE_200to200MHz NO.15 2869 15, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_200to300MHz NO.16 2870 30, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_150to200MHz NO.17 2871 30, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_8LANE_150to150MHz NO.18 2872 30, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_100to150MHz NO.19 2873 60, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_75to100MHz NO.20 2874 60, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_4LANE_75to75MHz NO.21 2875 30, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_50to75MHz NO.22 2876 60, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_37_5to50MHz NO.23 2877 60, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_2LANE_37_5to37_5MHz NO.24 2878 30, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_50to80MHz NO.25 2879 60, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to50MHz NO.26 2880 60, //E_PNL_SUPPORTED_LPLL_VBY1_8BIT_1LANE_40to40MHz NO.27 2881 4, //E_PNL_SUPPORTED_LPLL_EPI_24_12P_150to330MHz NO.28 2882 4, //E_PNL_SUPPORTED_LPLL_EPI_24_12P_150to150MHz NO.29 2883 4, //E_PNL_SUPPORTED_LPLL_EPI_28_12P_150to330MHz NO.30 2884 4, //E_PNL_SUPPORTED_LPLL_EPI_28_12P_150to150MHz NO.31 2885 4, //E_PNL_SUPPORTED_LPLL_EPI_28_6P_180to330MHz NO.32 2886 4, //E_PNL_SUPPORTED_LPLL_EPI_28_6P_150to180MHz NO.33 2887 4, //E_PNL_SUPPORTED_LPLL_EPI_28_6P_150to150MHz NO.34 2888 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8P_240to330MHz NO.35 2889 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8P_150to240MHz NO.36 2890 4, //E_PNL_SUPPORTED_LPLL_EPI_28_8P_150to150MHz NO.37 2891 4, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to330MHz NO.38 2892 4, //E_PNL_SUPPORTED_LPLL_USI_T_8BIT_12PAIR_150to150MHz NO.39 2893 25, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to330MHz NO.40 2894 25, //E_PNL_SUPPORTED_LPLL_USI_T_10BIT_12PAIR_150to150MHz NO.41 2895 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to330MHz NO.42 2896 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_12PAIR_150to150MHz NO.43 2897 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to330MHz NO.44 2898 4, //E_PNL_SUPPORTED_LPLL_ISP_8BIT_6PAIR_DUAL_150to150MHz NO.45 2899 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_100to150MHz NO.46 2900 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to100MHz NO.47 2901 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_1CH_50to50MHz NO.48 2902 7, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_100to150MHz NO.49 2903 14, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_50to100MHz NO.50 2904 28, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to50MHz NO.51 2905 28, //E_PNL_SUPPORTED_LPLL_HS_LVDS_2CH_25to25MHz NO.52 2906 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to80MHz NO.53 2907 14, //E_PNL_SUPPORTED_LPLL_LVDS_1CH_50to50MHz NO.54 2908 14, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_50to80MHz NO.55 2909 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to50MHz NO.56 2910 28, //E_PNL_SUPPORTED_LPLL_LVDS_2CH_25to25MHz NO.57 2911 }; 2912 2913 #endif //_LPLL_TBL_H_ 2914