1 #include "hwreg_frc_map.h"
2 #include "Maxim_2D_4K2K.h"
3
4 // 2D_4K2K
5 // 2D_FHD_RGB_BYPASS
MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS(void)6 void MFC_3D_2D_4K2K_2D_FHD_RGB_BYPASS(void)
7 {
8 // FSC_TOP
9 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass
10 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md
11 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass
12 // VSU
13 MDrv_WriteByteMask( REG_SC_BK4F_12, 0x00, 0xff); // vsp_scl_fac0
14 MDrv_WriteByteMask( REG_SC_BK4F_13, 0x00, 0xff); // vsp_scl_fac1
15 MDrv_WriteByteMask( REG_SC_BK4F_14, 0x08, 0xff); // vsp_scl_fac2
16 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x01, 0x01); // vsp_scl_en
17 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x02, 0x02); // vsp_shift_mode_en
18 MDrv_WriteByteMask( REG_SC_BK4F_06, 0x00, 0xff); // vsp_ini_scl_fac0
19 MDrv_WriteByteMask( REG_SC_BK4F_07, 0x00, 0xff); // vsp_ini_scl_fac1
20 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x0C, 0xff); // vsp_ini_scl_fac2
21 MDrv_WriteByteMask( REG_SC_BK4F_52, 0x38, 0xff); // vsp_vsize_in0
22 MDrv_WriteByteMask( REG_SC_BK4F_53, 0x04, 0xff); // vsp_vsize_in1
23 MDrv_WriteByteMask( REG_SC_BK4F_56, 0x70, 0xff); // vsp_vsize_out0
24 MDrv_WriteByteMask( REG_SC_BK4F_57, 0x08, 0xff); // vsp_vsize_out1
25 // HSU
26 MDrv_WriteByteMask( REG_SC_BK4F_0E, 0x00, 0xff); // hsp_scl_fac0
27 MDrv_WriteByteMask( REG_SC_BK4F_0F, 0x00, 0xff); // hsp_scl_fac1
28 MDrv_WriteByteMask( REG_SC_BK4F_10, 0x08, 0xff); // hsp_scl_fac2
29 MDrv_WriteByteMask( REG_SC_BK4F_11, 0x01, 0x01); // hsp_scl_en
30 MDrv_WriteByteMask( REG_SC_BK4F_11, 0x02, 0x02); // hsp_shift_mode_en
31 MDrv_WriteByteMask( REG_SC_BK4F_02, 0x00, 0xff); // hsp_ini_scl_fac0
32 MDrv_WriteByteMask( REG_SC_BK4F_03, 0x00, 0xff); // hsp_ini_scl_fac1
33 MDrv_WriteByteMask( REG_SC_BK4F_04, 0x0C, 0xff); // hsp_ini_scl_fac2
34 MDrv_WriteByteMask( REG_SC_BK4F_50, 0x80, 0xff); // hsp_hsize_in0
35 MDrv_WriteByteMask( REG_SC_BK4F_51, 0x07, 0xff); // hsp_hsize_in1
36 MDrv_WriteByteMask( REG_SC_BK4F_54, 0x00, 0xff); // hsp_hsize_out0
37 MDrv_WriteByteMask( REG_SC_BK4F_55, 0x0f, 0xff); // hsp_hsize_out1
38 // SPTF_D2LR
39 MDrv_WriteByteMask( REG_FRC_BK33A_60 , 0x00, 0xff); // gb_cut_st_l
40 MDrv_WriteByteMask( REG_FRC_BK33A_61 , 0x00, 0xff); // gb_cut_st_l
41 MDrv_WriteByteMask( REG_FRC_BK33A_62 , 0x80, 0xff); // gb_cut_end_l
42 MDrv_WriteByteMask( REG_FRC_BK33A_63 , 0x07, 0xff); // gb_cut_end_l
43 MDrv_WriteByteMask( REG_FRC_BK33A_64 , 0x80, 0xff); // gb_cut_st_r
44 MDrv_WriteByteMask( REG_FRC_BK33A_65 , 0x00, 0xff); // gb_cut_st_r
45 MDrv_WriteByteMask( REG_FRC_BK33A_66 , 0xff, 0xff); // gb_cut_end_r
46 MDrv_WriteByteMask( REG_FRC_BK33A_67 , 0x1f, 0xff); // gb_cut_end_r
47 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass
48 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo
49 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr
50 MDrv_WriteByteMask( REG_FRC_BK33A_52 , 0xc0, 0xff); // d2lr_output_h
51 MDrv_WriteByteMask( REG_FRC_BK33A_53 , 0x03, 0xff); // d2lr_output_h
52 MDrv_WriteByteMask( REG_FRC_BK33A_40 , 0x00, 0xff); // d2lr_w0_st
53 MDrv_WriteByteMask( REG_FRC_BK33A_41 , 0x00, 0xff); // d2lr_w0_st
54 MDrv_WriteByteMask( REG_FRC_BK33A_42 , 0x7f, 0xff); // d2lr_w0_end
55 MDrv_WriteByteMask( REG_FRC_BK33A_43 , 0x07, 0xff); // d2lr_w0_end
56 MDrv_WriteByteMask( REG_FRC_BK33A_44 , 0x00, 0xff); // d2lr_w1_st
57 MDrv_WriteByteMask( REG_FRC_BK33A_45 , 0x00, 0xff); // d2lr_w1_st
58 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end
59 MDrv_WriteByteMask( REG_FRC_BK33A_47 , 0x07, 0xff); // d2lr_w1_end
60 MDrv_WriteByteMask( REG_FRC_BK33A_48 , 0x00, 0xff); // d2lr_r0_st
61 MDrv_WriteByteMask( REG_FRC_BK33A_49 , 0x00, 0xff); // d2lr_r0_st
62 MDrv_WriteByteMask( REG_FRC_BK33A_4A , 0xbf, 0xff); // d2lr_r0_end
63 MDrv_WriteByteMask( REG_FRC_BK33A_4B , 0x04, 0xff); // d2lr_r0_end
64 MDrv_WriteByteMask( REG_FRC_BK33A_4C , 0xc0, 0xff); // d2lr_r1_st
65 MDrv_WriteByteMask( REG_FRC_BK33A_4D , 0x02, 0xff); // d2lr_r1_st
66 MDrv_WriteByteMask( REG_FRC_BK33A_4E , 0x7f, 0xff); // d2lr_r1_end
67 MDrv_WriteByteMask( REG_FRC_BK33A_4F , 0x07, 0xff); // d2lr_r1_end
68 // FSC_3D
69 MDrv_WriteByteMask( REG_SC_BK4F_21, 0x00, 0x40); // reg_3d_top_bot_en
70 MDrv_WriteByteMask( REG_SC_BK4F_21, 0x00, 0x80); // reg_3d_sbs_en
71 // IPM_OPM
72 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2
73 MDrv_WriteByteMask( REG_FRC_BK134_1D , 0x07, 0xff); // ipm_offset_f2
74 MDrv_WriteByteMask( REG_FRC_BK134_1E , 0x80, 0xff); // ipm_fetch_f2
75 MDrv_WriteByteMask( REG_FRC_BK134_1F , 0x07, 0xff); // ipm_fetch_f2
76 MDrv_WriteByteMask( REG_FRC_BK134_04 , 0x01, 0xff); // ipm_mem_config_f2
77 MDrv_WriteByteMask( REG_FRC_BK134_05 , 0x01, 0xff); // ipm_mem_config_f2
78 MDrv_WriteByteMask( REG_FRC_BK13A_04 , 0x03, 0xff); // ipm_mem_config_f2
79 MDrv_WriteByteMask( REG_FRC_BK13A_05 , 0x31, 0xff); // ipm_mem_config_f2
80 MDrv_WriteByteMask( REG_FRC_BK13A_84 , 0x03, 0xff); // ipm_mem_config_f2
81 MDrv_WriteByteMask( REG_FRC_BK13A_85 , 0x31, 0xff); // ipm_mem_config_f2
82 MDrv_WriteByteMask( REG_FRC_BK134_9C , 0x80, 0xff); // ipm_fetch_f1
83 MDrv_WriteByteMask( REG_FRC_BK134_9D , 0x07, 0xff); // ipm_fetch_f1
84 MDrv_WriteByteMask( REG_FRC_BK134_9E , 0x80, 0xff); // ipm_offset_f1
85 MDrv_WriteByteMask( REG_FRC_BK134_9F , 0x07, 0xff); // ipm_offset_f1
86 MDrv_WriteByteMask( REG_FRC_BK134_84 , 0x01, 0xff); // ipm_mem_config_f1
87 MDrv_WriteByteMask( REG_FRC_BK134_85 , 0x01, 0xff); // ipm_mem_config_f1
88 MDrv_WriteByteMask( REG_FRC_BK134_2C , 0x80, 0xff); // opm_offset_f2
89 MDrv_WriteByteMask( REG_FRC_BK134_2D , 0x07, 0xff); // opm_offset_f2
90 MDrv_WriteByteMask( REG_FRC_BK134_2E , 0x80, 0xff); // opm_fetch_f2
91 MDrv_WriteByteMask( REG_FRC_BK134_2F , 0x07, 0xff); // opm_fetch_f2
92 MDrv_WriteByteMask( REG_FRC_BK134_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
93 MDrv_WriteByteMask( REG_FRC_BK134_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
94 MDrv_WriteByteMask( REG_FRC_BK136_2C , 0x80, 0xff); // opm_offset_f1
95 MDrv_WriteByteMask( REG_FRC_BK136_2D , 0x07, 0xff); // opm_offset_f1
96 MDrv_WriteByteMask( REG_FRC_BK136_2E , 0x80, 0xff); // opm_fetch_f1
97 MDrv_WriteByteMask( REG_FRC_BK136_2F , 0x07, 0xff); // opm_fetch_f1
98 MDrv_WriteByteMask( REG_FRC_BK136_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
99 MDrv_WriteByteMask( REG_FRC_BK136_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
100 MDrv_WriteByteMask( REG_FRC_BK13A_2C , 0x80, 0xff); // opm_offset_f2
101 MDrv_WriteByteMask( REG_FRC_BK13A_2D , 0x07, 0xff); // opm_offset_f2
102 MDrv_WriteByteMask( REG_FRC_BK13A_2E , 0x80, 0xff); // opm_fetch_f2
103 MDrv_WriteByteMask( REG_FRC_BK13A_2F , 0x07, 0xff); // opm_fetch_f2
104 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
105 MDrv_WriteByteMask( REG_FRC_BK13A_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
106 MDrv_WriteByteMask( REG_FRC_BK13B_2C , 0x80, 0xff); // opm_offset_f1
107 MDrv_WriteByteMask( REG_FRC_BK13B_2D , 0x07, 0xff); // opm_offset_f1
108 MDrv_WriteByteMask( REG_FRC_BK13B_2E , 0x80, 0xff); // opm_fetch_f1
109 MDrv_WriteByteMask( REG_FRC_BK13B_2F , 0x07, 0xff); // opm_fetch_f1
110 MDrv_WriteByteMask( REG_FRC_BK13B_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
111 MDrv_WriteByteMask( REG_FRC_BK13B_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
112 MDrv_WriteByteMask( REG_FRC_BK13C_2C , 0x80, 0xff); // opm_offset_f2
113 MDrv_WriteByteMask( REG_FRC_BK13C_2D , 0x07, 0xff); // opm_offset_f2
114 MDrv_WriteByteMask( REG_FRC_BK13C_2E , 0x80, 0xff); // opm_fetch_f2
115 MDrv_WriteByteMask( REG_FRC_BK13C_2F , 0x07, 0xff); // opm_fetch_f2
116 MDrv_WriteByteMask( REG_FRC_BK13C_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
117 MDrv_WriteByteMask( REG_FRC_BK13C_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
118 MDrv_WriteByteMask( REG_FRC_BK13D_2C , 0x80, 0xff); // opm_offset_f1
119 MDrv_WriteByteMask( REG_FRC_BK13D_2D , 0x07, 0xff); // opm_offset_f1
120 MDrv_WriteByteMask( REG_FRC_BK13D_2E , 0x80, 0xff); // opm_fetch_f1
121 MDrv_WriteByteMask( REG_FRC_BK13D_2F , 0x07, 0xff); // opm_fetch_f1
122 MDrv_WriteByteMask( REG_FRC_BK13D_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
123 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
124 // IPM_OPM_vlen
125 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel
126 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel
127 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel
128 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel
129 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel
130 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x80, 0x80); // reg_opm_vlen_sel
131 MDrv_WriteByteMask( REG_FRC_BK134_62 , 0x70, 0xff); // reg_opm_vlen
132 MDrv_WriteByteMask( REG_FRC_BK134_63 , 0x08, 0x1f); // reg_opm_vlen
133 MDrv_WriteByteMask( REG_FRC_BK136_62 , 0x70, 0xff); // reg_opm_vlen
134 MDrv_WriteByteMask( REG_FRC_BK136_63 , 0x08, 0x1f); // reg_opm_vlen
135 MDrv_WriteByteMask( REG_FRC_BK13A_62 , 0x70, 0xff); // reg_opm_vlen
136 MDrv_WriteByteMask( REG_FRC_BK13A_63 , 0x08, 0x1f); // reg_opm_vlen
137 MDrv_WriteByteMask( REG_FRC_BK13B_62 , 0x70, 0xff); // reg_opm_vlen
138 MDrv_WriteByteMask( REG_FRC_BK13B_63 , 0x08, 0x1f); // reg_opm_vlen
139 MDrv_WriteByteMask( REG_FRC_BK13C_62 , 0x70, 0xff); // reg_opm_vlen
140 MDrv_WriteByteMask( REG_FRC_BK13C_63 , 0x08, 0x1f); // reg_opm_vlen
141 MDrv_WriteByteMask( REG_FRC_BK13D_62 , 0x70, 0xff); // reg_opm_vlen
142 MDrv_WriteByteMask( REG_FRC_BK13D_63 , 0x08, 0x1f); // reg_opm_vlen
143 MDrv_WriteByteMask( REG_FRC_BK134_CC , 0x70, 0xff); // reg_opm_vlen_new
144 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new
145 MDrv_WriteByteMask( REG_FRC_BK136_CC , 0x70, 0xff); // reg_opm_vlen_new
146 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new
147 MDrv_WriteByteMask( REG_FRC_BK13A_CC , 0x70, 0xff); // reg_opm_vlen_new
148 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new
149 MDrv_WriteByteMask( REG_FRC_BK13B_CC , 0x70, 0xff); // reg_opm_vlen_new
150 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new
151 MDrv_WriteByteMask( REG_FRC_BK13C_CC , 0x70, 0xff); // reg_opm_vlen_new
152 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new
153 MDrv_WriteByteMask( REG_FRC_BK13D_CC , 0x70, 0xff); // reg_opm_vlen_new
154 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x08, 0x1f); // reg_opm_vlen_new
155 MDrv_WriteByteMask( REG_FRC_BK134_BA , 0x38, 0xff); // reg_opm_meds_vlen
156 MDrv_WriteByteMask( REG_FRC_BK134_BB , 0x04, 0x1f); // reg_opm_meds_vlen
157 MDrv_WriteByteMask( REG_FRC_BK136_BA , 0x38, 0xff); // reg_opm_meds_vlen
158 MDrv_WriteByteMask( REG_FRC_BK136_BB , 0x04, 0x1f); // reg_opm_meds_vlen
159 MDrv_WriteByteMask( REG_FRC_BK13A_BA , 0x38, 0xff); // reg_opm_meds_vlen
160 MDrv_WriteByteMask( REG_FRC_BK13A_BB , 0x04, 0x1f); // reg_opm_meds_vlen
161 MDrv_WriteByteMask( REG_FRC_BK13B_BA , 0x38, 0xff); // reg_opm_meds_vlen
162 MDrv_WriteByteMask( REG_FRC_BK13B_BB , 0x04, 0x1f); // reg_opm_meds_vlen
163 MDrv_WriteByteMask( REG_FRC_BK13C_BA , 0x38, 0xff); // reg_opm_meds_vlen
164 MDrv_WriteByteMask( REG_FRC_BK13C_BB , 0x04, 0x1f); // reg_opm_meds_vlen
165 MDrv_WriteByteMask( REG_FRC_BK13D_BA , 0x38, 0xff); // reg_opm_meds_vlen
166 MDrv_WriteByteMask( REG_FRC_BK13D_BB , 0x04, 0x1f); // reg_opm_meds_vlen
167 MDrv_WriteByteMask( REG_FRC_BK134_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
168 MDrv_WriteByteMask( REG_FRC_BK134_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
169 MDrv_WriteByteMask( REG_FRC_BK136_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
170 MDrv_WriteByteMask( REG_FRC_BK136_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
171 MDrv_WriteByteMask( REG_FRC_BK13A_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
172 MDrv_WriteByteMask( REG_FRC_BK13A_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
173 MDrv_WriteByteMask( REG_FRC_BK13B_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
174 MDrv_WriteByteMask( REG_FRC_BK13B_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
175 MDrv_WriteByteMask( REG_FRC_BK13C_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
176 MDrv_WriteByteMask( REG_FRC_BK13C_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
177 MDrv_WriteByteMask( REG_FRC_BK13D_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
178 MDrv_WriteByteMask( REG_FRC_BK13D_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
179 // IPM_OPM_DSmode
180 MDrv_WriteByteMask( REG_FRC_BK13A_1C , 0xc0, 0xff); // reg_ipm_offset_f2
181 MDrv_WriteByteMask( REG_FRC_BK13A_1D , 0x03, 0xff); // reg_ipm_offset_f2
182 MDrv_WriteByteMask( REG_FRC_BK13A_1E , 0xc0, 0xff); // reg_ipm_fetch_num_f2
183 MDrv_WriteByteMask( REG_FRC_BK13A_1F , 0x03, 0xff); // reg_ipm_fetch_num_f2
184 MDrv_WriteByteMask( REG_FRC_BK13A_9C , 0xc0, 0xff); // reg_ipm_offset_f1
185 MDrv_WriteByteMask( REG_FRC_BK13A_9D , 0x03, 0xff); // reg_ipm_offset_f1
186 MDrv_WriteByteMask( REG_FRC_BK13A_9E , 0xc0, 0xff); // reg_ipm_fetch_num_f1
187 MDrv_WriteByteMask( REG_FRC_BK13A_9F , 0x03, 0xff); // reg_ipm_fetch_num_f1
188 MDrv_WriteByteMask( REG_FRC_BK134_BC , 0xc0, 0xff); // reg_opm_meds_offset
189 MDrv_WriteByteMask( REG_FRC_BK134_BD , 0x03, 0xff); // reg_opm_meds_offset
190 MDrv_WriteByteMask( REG_FRC_BK134_BE , 0xc0, 0xff); // reg_opm_meds_fetch_num
191 MDrv_WriteByteMask( REG_FRC_BK134_BF , 0x03, 0xff); // reg_opm_meds_fetch_num
192 // IPM_3D
193 MDrv_WriteByteMask( REG_FRC_BK135_1C , 0x00, 0xff); // reg_v_toggle_value
194 MDrv_WriteByteMask( REG_FRC_BK135_1D , 0x00, 0x0f); // reg_v_toggle_value
195 MDrv_WriteByteMask( REG_FRC_BK135_04 , 0x00, 0x30); // reg_v_toggle_en
196 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en
197 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x80, 0x80); // reg_ipm_meds_ud_en
198 MDrv_WriteByteMask( REG_FRC_BK134_26 , 0x38, 0xff); // reg_ipm_turn_back_line
199 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line
200 MDrv_WriteByteMask( REG_FRC_BK13A_26 , 0x1c, 0xff); // reg_ipm_turn_back_line_meds
201 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x02, 0x1f); // reg_ipm_turn_back_line_meds
202 // OPM_3D
203 MDrv_WriteByteMask( REG_FRC_BK134_60 , 0x00, 0x01); // reg_ipm_3d_en_f2
204 MDrv_WriteByteMask( REG_FRC_BK134_E0 , 0x00, 0x01); // reg_ipm_3d_en_f1
205 MDrv_WriteByteMask( REG_FRC_BK13A_60 , 0x00, 0x01); // reg_ipm_3d_en_mef3f4_f2
206 MDrv_WriteByteMask( REG_FRC_BK13A_E0 , 0x00, 0x01); // reg_ipm_3d_en_mef3f4_f1
207 MDrv_WriteByteMask( REG_FRC_BK134_66 , 0x00, 0x80); // reg_opm_3d_en_f2
208 MDrv_WriteByteMask( REG_FRC_BK136_66 , 0x00, 0x80); // reg_opm_3d_en_f1
209 MDrv_WriteByteMask( REG_FRC_BK13A_66 , 0x00, 0x80); // reg_opm_3d_en_mef3f4_f2
210 MDrv_WriteByteMask( REG_FRC_BK13B_66 , 0x00, 0x80); // reg_opm_3d_en_mef3f4_f1
211 MDrv_WriteByteMask( REG_FRC_BK13C_66 , 0x00, 0x80); // reg_opm_3d_en_mif3_f2
212 MDrv_WriteByteMask( REG_FRC_BK13D_66 , 0x00, 0x80); // reg_opm_3d_en_mif3_f1
213 MDrv_WriteByteMask( REG_FRC_BK134_67 , 0x00, 0x04); // reg_opm_passive_en_f2
214 MDrv_WriteByteMask( REG_FRC_BK136_67 , 0x00, 0x04); // reg_opm_passive_en_f1
215 MDrv_WriteByteMask( REG_FRC_BK13A_67 , 0x00, 0x04); // reg_opm_passive_en_f2
216 MDrv_WriteByteMask( REG_FRC_BK13B_67 , 0x00, 0x04); // reg_opm_passive_en_f1
217 MDrv_WriteByteMask( REG_FRC_BK13C_67 , 0x00, 0x04); // reg_opm_passive_en_f2
218 MDrv_WriteByteMask( REG_FRC_BK13D_67 , 0x00, 0x04); // reg_opm_passive_en_f1
219 MDrv_WriteByteMask( REG_FRC_BK134_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
220 MDrv_WriteByteMask( REG_FRC_BK136_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
221 MDrv_WriteByteMask( REG_FRC_BK13A_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
222 MDrv_WriteByteMask( REG_FRC_BK13B_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
223 MDrv_WriteByteMask( REG_FRC_BK13C_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
224 MDrv_WriteByteMask( REG_FRC_BK13D_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
225 // OPMRM
226 MDrv_WriteByteMask( REG_FRC_BK134_E8 , 0x01, 0x01); // reg_opm_ml_en
227 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x08, 0x08); // reg_rbk_free
228 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x10, 0x70); // reg_rbk_free_diff
229 MDrv_WriteByteMask( REG_FRC_BK134_32 , 0x00, 0x80); // reg_opm_2f_md
230 MDrv_WriteByteMask( REG_FRC_BK136_32 , 0x00, 0x80); // reg_opm_2f_md
231 MDrv_WriteByteMask( REG_FRC_BK134_33 , 0x00, 0x01); // reg_opm_3f_md
232 MDrv_WriteByteMask( REG_FRC_BK136_33 , 0x00, 0x01); // reg_opm_3f_md
233 MDrv_WriteByteMask( REG_FRC_BK134_CE , 0x00, 0x0f); // reg_opm_memc_md
234 MDrv_WriteByteMask( REG_FRC_BK134_CF , 0x00, 0x07); // reg_opm_memc_md
235 // HSD_MEDS
236 MDrv_WriteByteMask( REG_FRC_BK320_C2 , 0x33, 0xff); // reg_frc_ipm_hvsd_la_mode
237 MDrv_WriteByteMask( REG_FRC_BK320_C3 , 0x8e, 0xff); // reg_frc_ipm_hvsd_drop_mode
238 // MEMC_FSC
239 MDrv_WriteByteMask( REG_FRC_BK320_A4 , 0x00, 0xff); // reg_frc_xxxx
240 MDrv_WriteByteMask( REG_FRC_BK320_A5 , 0x0F, 0xff); // reg_frc_xxxx
241 MDrv_WriteByteMask( REG_FRC_BK320_A6 , 0x80, 0xff); // reg_frc_xxxx
242 MDrv_WriteByteMask( REG_FRC_BK320_A7 , 0x07, 0xff); // reg_frc_xxxx
243 // MLB
244 MDrv_WriteByteMask( REG_FRC_BK226_F4 , 0x01, 0xff); // reg_sadmvRangeL
245 MDrv_WriteByteMask( REG_FRC_BK226_F5 , 0x00, 0x03); // reg_sadmvRangeL
246 MDrv_WriteByteMask( REG_FRC_BK226_F8 , 0x01, 0xff); // reg_sadmvRangeU
247 MDrv_WriteByteMask( REG_FRC_BK226_F9 , 0x00, 0x01); // reg_sadmvRangeU
248 MDrv_WriteByteMask( REG_FRC_BK226_F6 , 0xff, 0xff); // reg_sadmvRangeR
249 MDrv_WriteByteMask( REG_FRC_BK226_F7 , 0x03, 0x03); // reg_sadmvRangeR
250 MDrv_WriteByteMask( REG_FRC_BK226_F2 , 0xff, 0xff); // reg_sadmvRangeD
251 MDrv_WriteByteMask( REG_FRC_BK226_F3 , 0x00, 0x01); // reg_sadmvRangeD
252 MDrv_WriteByteMask( REG_FRC_BK232_02 , 0x00, 0x02); // reg_pass3d_la
253 MDrv_WriteByteMask( REG_FRC_BK232_11 , 0x00, 0xc0); // reg_mask_en
254 // MV_PREPROC
255 MDrv_WriteByteMask( REG_FRC_BK22C_92 , 0x00, 0x03); // reg_mv_preprocess
256 // MFC_pipectrl
257 MDrv_WriteByteMask( REG_FRC_BK233_3E , 0x00, 0xff); // reg_ppctr_h_pixl_num_me
258 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me
259 MDrv_WriteByteMask( REG_FRC_BK233_40 , 0x38, 0xff); // reg_ppctr_v_line_num_me
260 MDrv_WriteByteMask( REG_FRC_BK233_41 , 0x04, 0x1f); // reg_ppctr_v_line_num_me
261 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi
262 MDrv_WriteByteMask( REG_FRC_BK233_47 , 0x0f, 0x1f); // reg_me_h_pixel_num_mi
263 MDrv_WriteByteMask( REG_FRC_BK233_48 , 0x70, 0xff); // reg_me_v_pixel_num_mi
264 MDrv_WriteByteMask( REG_FRC_BK233_49 , 0x08, 0x1f); // reg_me_v_pixel_num_mi
265 MDrv_WriteByteMask( REG_FRC_BK233_F8 , 0x00, 0xff); // reg_h_pixel_num_mlb
266 MDrv_WriteByteMask( REG_FRC_BK233_F9 , 0x0f, 0x1f); // reg_h_pixel_num_mlb
267 MDrv_WriteByteMask( REG_FRC_BK233_FA , 0x70, 0xff); // reg_v_pixel_num_mlb
268 MDrv_WriteByteMask( REG_FRC_BK233_FB , 0x08, 0x1f); // reg_v_pixel_num_mlb
269 MDrv_WriteByteMask( REG_FRC_BK233_3A , 0x00, 0xff); // reg_time_gen_sw_h_width
270 MDrv_WriteByteMask( REG_FRC_BK233_3B , 0x0f, 0x1f); // reg_time_gen_sw_h_width
271 MDrv_WriteByteMask( REG_FRC_BK233_3C , 0x1b, 0xff); // reg_time_gen_sw_v_width
272 MDrv_WriteByteMask( REG_FRC_BK233_3D , 0x02, 0x1f); // reg_time_gen_sw_v_width
273 MDrv_WriteByteMask( REG_FRC_BK233_42 , 0x80, 0xff); // reg_mlb_disp_pixel_latch
274 MDrv_WriteByteMask( REG_FRC_BK233_43 , 0x07, 0x1f); // reg_mlb_disp_pixel_latch
275 MDrv_WriteByteMask( REG_FRC_BK233_A8 , 0x00, 0xff); // reg_gmv_vertical_active_window_height
276 MDrv_WriteByteMask( REG_FRC_BK233_A9 , 0x01, 0x01); // reg_gmv_vertical_active_window_height
277 // MFC_VDUP
278 MDrv_WriteByteMask( REG_FRC_BK20A_04 , 0xC0, 0xFF); // reg_VDUP_width
279 MDrv_WriteByteMask( REG_FRC_BK20A_05 , 0x03, 0xFF); // reg_VDUP_width
280 MDrv_WriteByteMask( REG_FRC_BK20A_06 , 0x70, 0xFF); // reg_VDUP_height
281 MDrv_WriteByteMask( REG_FRC_BK20A_07 , 0x08, 0xFF); // reg_VDUP_height
282 // MFC
283 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable
284 MDrv_WriteByteMask( REG_FRC_BK226_70 , 0x00, 0x20); //
285 MDrv_WriteByteMask( REG_FRC_BK226_73 , 0x0f, 0x1f); // reg_h_pix_num_3D
286 MDrv_WriteByteMask( REG_FRC_BK226_72 , 0x00, 0xff); // reg_h_pix_num_3D
287 MDrv_WriteByteMask( REG_FRC_BK226_75 , 0x04, 0x1f); // reg_v_lin_num_3D
288 MDrv_WriteByteMask( REG_FRC_BK226_74 , 0x38, 0xff); // reg_v_lin_num_3D
289 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x08, 0x08); //
290 MDrv_WriteByteMask( REG_FRC_BK229_05 , 0x0f, 0xFF); // reg_h_pix_num_ME
291 MDrv_WriteByteMask( REG_FRC_BK229_04 , 0x00, 0xFF); // reg_h_pix_num_ME
292 MDrv_WriteByteMask( REG_FRC_BK229_07 , 0x08, 0x0F); // reg_v_lin_num_ME
293 MDrv_WriteByteMask( REG_FRC_BK229_06 , 0x70, 0xFF); // reg_v_lin_num_ME
294 MDrv_WriteByteMask( REG_FRC_BK229_91 , 0x0f, 0xFF); // reg_h_pix_num_MI
295 MDrv_WriteByteMask( REG_FRC_BK229_90 , 0x00, 0xFF); // reg_h_pix_num_MI
296 MDrv_WriteByteMask( REG_FRC_BK229_93 , 0x08, 0xFF); // reg_v_lin_num_MI
297 MDrv_WriteByteMask( REG_FRC_BK229_92 , 0x70, 0xFF); // reg_v_lin_num_MI
298 MDrv_WriteByteMask( REG_FRC_BK226_67 , 0x00, 0x01); // reg_422to444_en
299 MDrv_WriteByteMask( REG_FRC_BK232_D0 , 0x02, 0x02); // reg_rgb_bypass
300 MDrv_WriteByteMask( REG_FRC_BK226_60 , 0x00, 0x80); // reg_c_drop
301 MDrv_WriteByteMask( REG_FRC_BK229_9C , 0x00, 0x80); // reg_422_avgmode
302 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x00, 0x01); // reg_pipectrl_bypass
303 // MFC_Halo
304 MDrv_WriteByteMask( REG_FRC_BK22C_93 , 0x80, 0x80); // reg_halo_buf_frame_end_en
305 MDrv_WriteByteMask( REG_FRC_BK22C_A7 , 0x00, 0x02); // reg_halo_buf23_force_ready
306 // MFC_GMV
307 MDrv_WriteByteMask( REG_FRC_BK232_2A , 0x01, 0x01); // reg_gmv_in_ud_mode
308 // SNR
309 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en
310 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en
311 MDrv_WriteByteMask( REG_FRC_BK2E_E2 , 0x00, 0xff); // reg_snr_pix_num_LSB
312 MDrv_WriteByteMask( REG_FRC_BK2E_E3 , 0x0f, 0x1f); // reg_snr_pix_num_MSB
313 MDrv_WriteByteMask( REG_FRC_BK2E_E8 , 0x70, 0xff); // reg_snr_line_num_LSB
314 MDrv_WriteByteMask( REG_FRC_BK2E_E9 , 0x08, 0x0f); // reg_snr_line_num_MSB
315 // SNR_3D
316 MDrv_WriteByteMask( REG_FRC_BK2E_65 , 0x00, 0x20); // reg_line_switch
317 // SNR_VSU2X
318 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en
319 // FO_HSU
320 MDrv_WriteByteMask( REG_FRC_BK115_30 , 0x00, 0xff); // hfac_smd0
321 MDrv_WriteByteMask( REG_FRC_BK115_31 , 0x00, 0xff); // hfac_smd1
322 MDrv_WriteByteMask( REG_FRC_BK115_32 , 0x00, 0x3f); // hfac_smd2
323 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en
324 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en
325 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0
326 MDrv_WriteByteMask( REG_FRC_BK115_0D , 0x0f, 0x1f); // hsp_size_in1
327 MDrv_WriteByteMask( REG_FRC_BK115_0E , 0x00, 0xff); // hsp_size_out0
328 MDrv_WriteByteMask( REG_FRC_BK115_0F , 0x0f, 0x1f); // hsp_size_out1
329 // SPTP
330 MDrv_WriteByteMask( REG_FRC_BK3E_80 , 0xff, 0xff); // reg_sptp_mfc_dc_m1
331 MDrv_WriteByteMask( REG_FRC_BK3E_81 , 0x0e, 0x0f); // reg_sptp_mfc_dc_m1
332 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en
333 MDrv_WriteByteMask( REG_FRC_BK3E_84 , 0x01, 0x01); // reg_sptp_usr_en
334 MDrv_WriteByteMask( REG_FRC_BK3E_88 , 0x00, 0xff); // reg_sptp_f0_st
335 MDrv_WriteByteMask( REG_FRC_BK3E_89 , 0x00, 0x01); // reg_sptp_f0_st
336 MDrv_WriteByteMask( REG_FRC_BK3E_8A , 0xf1, 0xff); // reg_sptp_f0_end
337 MDrv_WriteByteMask( REG_FRC_BK3E_8B , 0x00, 0x01); // reg_sptp_f0_end
338 MDrv_WriteByteMask( REG_FRC_BK3E_8C , 0xee, 0xff); // reg_sptp_f1_st
339 MDrv_WriteByteMask( REG_FRC_BK3E_8D , 0x00, 0x01); // reg_sptp_f1_st
340 MDrv_WriteByteMask( REG_FRC_BK3E_8E , 0xdf, 0xff); // reg_sptp_f1_end
341 MDrv_WriteByteMask( REG_FRC_BK3E_8F , 0x01, 0x01); // reg_sptp_f1_end
342 MDrv_WriteByteMask( REG_FRC_BK3E_86 , 0x02, 0xff); // reg_sptp_gb_en
343 // CSC
344 }
345
346
347
348 /********************************************/
349 // 2D_FHD_YUV
MFC_3D_2D_4K2K_2D_FHD_YUV(void)350 void MFC_3D_2D_4K2K_2D_FHD_YUV(void)
351 {
352 // FSC_TOP
353 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass
354 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x02); // reg_hvsp_buffer_md
355 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass
356 // VSU
357 MDrv_WriteByteMask( REG_SC_BK4F_12, 0x00, 0xff); // vsp_scl_fac0
358 MDrv_WriteByteMask( REG_SC_BK4F_13, 0x00, 0xff); // vsp_scl_fac1
359 MDrv_WriteByteMask( REG_SC_BK4F_14, 0x08, 0xff); // vsp_scl_fac2
360 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x01, 0x01); // vsp_scl_en
361 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x02, 0x02); // vsp_shift_mode_en
362 MDrv_WriteByteMask( REG_SC_BK4F_06, 0x00, 0xff); // vsp_ini_scl_fac0
363 MDrv_WriteByteMask( REG_SC_BK4F_07, 0x00, 0xff); // vsp_ini_scl_fac1
364 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x0C, 0xff); // vsp_ini_scl_fac2
365 MDrv_WriteByteMask( REG_SC_BK4F_52, 0x38, 0xff); // vsp_vsize_in0
366 MDrv_WriteByteMask( REG_SC_BK4F_53, 0x04, 0xff); // vsp_vsize_in1
367 MDrv_WriteByteMask( REG_SC_BK4F_56, 0x70, 0xff); // vsp_vsize_out0
368 MDrv_WriteByteMask( REG_SC_BK4F_57, 0x08, 0xff); // vsp_vsize_out1
369 // HSU
370 MDrv_WriteByteMask( REG_SC_BK4F_0E, 0x00, 0xff); // hsp_scl_fac0
371 MDrv_WriteByteMask( REG_SC_BK4F_0F, 0x00, 0xff); // hsp_scl_fac1
372 MDrv_WriteByteMask( REG_SC_BK4F_10, 0x08, 0xff); // hsp_scl_fac2
373 MDrv_WriteByteMask( REG_SC_BK4F_11, 0x01, 0x01); // hsp_scl_en
374 MDrv_WriteByteMask( REG_SC_BK4F_11, 0x02, 0x02); // hsp_shift_mode_en
375 MDrv_WriteByteMask( REG_SC_BK4F_02, 0x00, 0xff); // hsp_ini_scl_fac0
376 MDrv_WriteByteMask( REG_SC_BK4F_03, 0x00, 0xff); // hsp_ini_scl_fac1
377 MDrv_WriteByteMask( REG_SC_BK4F_04, 0x0C, 0xff); // hsp_ini_scl_fac2
378 MDrv_WriteByteMask( REG_SC_BK4F_50, 0x80, 0xff); // hsp_hsize_in0
379 MDrv_WriteByteMask( REG_SC_BK4F_51, 0x07, 0xff); // hsp_hsize_in1
380 MDrv_WriteByteMask( REG_SC_BK4F_54, 0x00, 0xff); // hsp_hsize_out0
381 MDrv_WriteByteMask( REG_SC_BK4F_55, 0x0f, 0xff); // hsp_hsize_out1
382 // SPTF_D2LR
383 MDrv_WriteByteMask( REG_FRC_BK33A_60 , 0x00, 0xff); // gb_cut_st_l
384 MDrv_WriteByteMask( REG_FRC_BK33A_61 , 0x00, 0xff); // gb_cut_st_l
385 MDrv_WriteByteMask( REG_FRC_BK33A_62 , 0x80, 0xff); // gb_cut_end_l
386 MDrv_WriteByteMask( REG_FRC_BK33A_63 , 0x07, 0xff); // gb_cut_end_l
387 MDrv_WriteByteMask( REG_FRC_BK33A_64 , 0x80, 0xff); // gb_cut_st_r
388 MDrv_WriteByteMask( REG_FRC_BK33A_65 , 0x00, 0xff); // gb_cut_st_r
389 MDrv_WriteByteMask( REG_FRC_BK33A_66 , 0xff, 0xff); // gb_cut_end_r
390 MDrv_WriteByteMask( REG_FRC_BK33A_67 , 0x1f, 0xff); // gb_cut_end_r
391 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass
392 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo
393 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr
394 MDrv_WriteByteMask( REG_FRC_BK33A_52 , 0xc0, 0xff); // d2lr_output_h
395 MDrv_WriteByteMask( REG_FRC_BK33A_53 , 0x03, 0xff); // d2lr_output_h
396 MDrv_WriteByteMask( REG_FRC_BK33A_40 , 0x00, 0xff); // d2lr_w0_st
397 MDrv_WriteByteMask( REG_FRC_BK33A_41 , 0x00, 0xff); // d2lr_w0_st
398 MDrv_WriteByteMask( REG_FRC_BK33A_42 , 0x7f, 0xff); // d2lr_w0_end
399 MDrv_WriteByteMask( REG_FRC_BK33A_43 , 0x07, 0xff); // d2lr_w0_end
400 MDrv_WriteByteMask( REG_FRC_BK33A_44 , 0x00, 0xff); // d2lr_w1_st
401 MDrv_WriteByteMask( REG_FRC_BK33A_45 , 0x00, 0xff); // d2lr_w1_st
402 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0x7f, 0xff); // d2lr_w1_end
403 MDrv_WriteByteMask( REG_FRC_BK33A_47 , 0x07, 0xff); // d2lr_w1_end
404 MDrv_WriteByteMask( REG_FRC_BK33A_48 , 0x00, 0xff); // d2lr_r0_st
405 MDrv_WriteByteMask( REG_FRC_BK33A_49 , 0x00, 0xff); // d2lr_r0_st
406 MDrv_WriteByteMask( REG_FRC_BK33A_4A , 0xbf, 0xff); // d2lr_r0_end
407 MDrv_WriteByteMask( REG_FRC_BK33A_4B , 0x04, 0xff); // d2lr_r0_end
408 MDrv_WriteByteMask( REG_FRC_BK33A_4C , 0xc0, 0xff); // d2lr_r1_st
409 MDrv_WriteByteMask( REG_FRC_BK33A_4D , 0x02, 0xff); // d2lr_r1_st
410 MDrv_WriteByteMask( REG_FRC_BK33A_4E , 0x7f, 0xff); // d2lr_r1_end
411 MDrv_WriteByteMask( REG_FRC_BK33A_4F , 0x07, 0xff); // d2lr_r1_end
412 // FSC_3D
413 MDrv_WriteByteMask( REG_SC_BK4F_21, 0x00, 0x40); // reg_3d_top_bot_en
414 MDrv_WriteByteMask( REG_SC_BK4F_21, 0x00, 0x80); // reg_3d_sbs_en
415 // IPM_OPM
416 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2
417 MDrv_WriteByteMask( REG_FRC_BK134_1D , 0x07, 0xff); // ipm_offset_f2
418 MDrv_WriteByteMask( REG_FRC_BK134_1E , 0x80, 0xff); // ipm_fetch_f2
419 MDrv_WriteByteMask( REG_FRC_BK134_1F , 0x07, 0xff); // ipm_fetch_f2
420 MDrv_WriteByteMask( REG_FRC_BK134_04 , 0x00, 0xff); // ipm_mem_config_f2
421 MDrv_WriteByteMask( REG_FRC_BK134_05 , 0x01, 0xff); // ipm_mem_config_f2
422 MDrv_WriteByteMask( REG_FRC_BK13A_04 , 0x03, 0xff); // ipm_mem_config_f2
423 MDrv_WriteByteMask( REG_FRC_BK13A_05 , 0x31, 0xff); // ipm_mem_config_f2
424 MDrv_WriteByteMask( REG_FRC_BK13A_84 , 0x03, 0xff); // ipm_mem_config_f2
425 MDrv_WriteByteMask( REG_FRC_BK13A_85 , 0x31, 0xff); // ipm_mem_config_f2
426 MDrv_WriteByteMask( REG_FRC_BK134_9C , 0x80, 0xff); // ipm_fetch_f1
427 MDrv_WriteByteMask( REG_FRC_BK134_9D , 0x07, 0xff); // ipm_fetch_f1
428 MDrv_WriteByteMask( REG_FRC_BK134_9E , 0x80, 0xff); // ipm_offset_f1
429 MDrv_WriteByteMask( REG_FRC_BK134_9F , 0x07, 0xff); // ipm_offset_f1
430 MDrv_WriteByteMask( REG_FRC_BK134_84 , 0x00, 0xff); // ipm_mem_config_f1
431 MDrv_WriteByteMask( REG_FRC_BK134_85 , 0x01, 0xff); // ipm_mem_config_f1
432 MDrv_WriteByteMask( REG_FRC_BK134_2C , 0x80, 0xff); // opm_offset_f2
433 MDrv_WriteByteMask( REG_FRC_BK134_2D , 0x07, 0xff); // opm_offset_f2
434 MDrv_WriteByteMask( REG_FRC_BK134_2E , 0x80, 0xff); // opm_fetch_f2
435 MDrv_WriteByteMask( REG_FRC_BK134_2F , 0x07, 0xff); // opm_fetch_f2
436 MDrv_WriteByteMask( REG_FRC_BK134_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
437 MDrv_WriteByteMask( REG_FRC_BK134_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
438 MDrv_WriteByteMask( REG_FRC_BK136_2C , 0x80, 0xff); // opm_offset_f1
439 MDrv_WriteByteMask( REG_FRC_BK136_2D , 0x07, 0xff); // opm_offset_f1
440 MDrv_WriteByteMask( REG_FRC_BK136_2E , 0x80, 0xff); // opm_fetch_f1
441 MDrv_WriteByteMask( REG_FRC_BK136_2F , 0x07, 0xff); // opm_fetch_f1
442 MDrv_WriteByteMask( REG_FRC_BK136_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
443 MDrv_WriteByteMask( REG_FRC_BK136_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
444 MDrv_WriteByteMask( REG_FRC_BK13A_2C , 0x80, 0xff); // opm_offset_f2
445 MDrv_WriteByteMask( REG_FRC_BK13A_2D , 0x07, 0xff); // opm_offset_f2
446 MDrv_WriteByteMask( REG_FRC_BK13A_2E , 0x80, 0xff); // opm_fetch_f2
447 MDrv_WriteByteMask( REG_FRC_BK13A_2F , 0x07, 0xff); // opm_fetch_f2
448 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
449 MDrv_WriteByteMask( REG_FRC_BK13A_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
450 MDrv_WriteByteMask( REG_FRC_BK13B_2C , 0x80, 0xff); // opm_offset_f1
451 MDrv_WriteByteMask( REG_FRC_BK13B_2D , 0x07, 0xff); // opm_offset_f1
452 MDrv_WriteByteMask( REG_FRC_BK13B_2E , 0x80, 0xff); // opm_fetch_f1
453 MDrv_WriteByteMask( REG_FRC_BK13B_2F , 0x07, 0xff); // opm_fetch_f1
454 MDrv_WriteByteMask( REG_FRC_BK13B_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
455 MDrv_WriteByteMask( REG_FRC_BK13B_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
456 MDrv_WriteByteMask( REG_FRC_BK13C_2C , 0x80, 0xff); // opm_offset_f2
457 MDrv_WriteByteMask( REG_FRC_BK13C_2D , 0x07, 0xff); // opm_offset_f2
458 MDrv_WriteByteMask( REG_FRC_BK13C_2E , 0x80, 0xff); // opm_fetch_f2
459 MDrv_WriteByteMask( REG_FRC_BK13C_2F , 0x07, 0xff); // opm_fetch_f2
460 MDrv_WriteByteMask( REG_FRC_BK13C_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
461 MDrv_WriteByteMask( REG_FRC_BK13C_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
462 MDrv_WriteByteMask( REG_FRC_BK13D_2C , 0x80, 0xff); // opm_offset_f1
463 MDrv_WriteByteMask( REG_FRC_BK13D_2D , 0x07, 0xff); // opm_offset_f1
464 MDrv_WriteByteMask( REG_FRC_BK13D_2E , 0x80, 0xff); // opm_fetch_f1
465 MDrv_WriteByteMask( REG_FRC_BK13D_2F , 0x07, 0xff); // opm_fetch_f1
466 MDrv_WriteByteMask( REG_FRC_BK13D_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
467 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
468 // IPM_OPM_vlen
469 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel
470 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel
471 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel
472 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel
473 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel
474 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x80, 0x80); // reg_opm_vlen_sel
475 MDrv_WriteByteMask( REG_FRC_BK134_62 , 0x70, 0xff); // reg_opm_vlen
476 MDrv_WriteByteMask( REG_FRC_BK134_63 , 0x08, 0x1f); // reg_opm_vlen
477 MDrv_WriteByteMask( REG_FRC_BK136_62 , 0x70, 0xff); // reg_opm_vlen
478 MDrv_WriteByteMask( REG_FRC_BK136_63 , 0x08, 0x1f); // reg_opm_vlen
479 MDrv_WriteByteMask( REG_FRC_BK13A_62 , 0x70, 0xff); // reg_opm_vlen
480 MDrv_WriteByteMask( REG_FRC_BK13A_63 , 0x08, 0x1f); // reg_opm_vlen
481 MDrv_WriteByteMask( REG_FRC_BK13B_62 , 0x70, 0xff); // reg_opm_vlen
482 MDrv_WriteByteMask( REG_FRC_BK13B_63 , 0x08, 0x1f); // reg_opm_vlen
483 MDrv_WriteByteMask( REG_FRC_BK13C_62 , 0x70, 0xff); // reg_opm_vlen
484 MDrv_WriteByteMask( REG_FRC_BK13C_63 , 0x08, 0x1f); // reg_opm_vlen
485 MDrv_WriteByteMask( REG_FRC_BK13D_62 , 0x70, 0xff); // reg_opm_vlen
486 MDrv_WriteByteMask( REG_FRC_BK13D_63 , 0x08, 0x1f); // reg_opm_vlen
487 MDrv_WriteByteMask( REG_FRC_BK134_CC , 0x70, 0xff); // reg_opm_vlen_new
488 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new
489 MDrv_WriteByteMask( REG_FRC_BK136_CC , 0x70, 0xff); // reg_opm_vlen_new
490 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new
491 MDrv_WriteByteMask( REG_FRC_BK13A_CC , 0x70, 0xff); // reg_opm_vlen_new
492 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new
493 MDrv_WriteByteMask( REG_FRC_BK13B_CC , 0x70, 0xff); // reg_opm_vlen_new
494 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new
495 MDrv_WriteByteMask( REG_FRC_BK13C_CC , 0x70, 0xff); // reg_opm_vlen_new
496 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new
497 MDrv_WriteByteMask( REG_FRC_BK13D_CC , 0x70, 0xff); // reg_opm_vlen_new
498 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x08, 0x1f); // reg_opm_vlen_new
499 MDrv_WriteByteMask( REG_FRC_BK134_BA , 0x38, 0xff); // reg_opm_meds_vlen
500 MDrv_WriteByteMask( REG_FRC_BK134_BB , 0x04, 0x1f); // reg_opm_meds_vlen
501 MDrv_WriteByteMask( REG_FRC_BK136_BA , 0x38, 0xff); // reg_opm_meds_vlen
502 MDrv_WriteByteMask( REG_FRC_BK136_BB , 0x04, 0x1f); // reg_opm_meds_vlen
503 MDrv_WriteByteMask( REG_FRC_BK13A_BA , 0x38, 0xff); // reg_opm_meds_vlen
504 MDrv_WriteByteMask( REG_FRC_BK13A_BB , 0x04, 0x1f); // reg_opm_meds_vlen
505 MDrv_WriteByteMask( REG_FRC_BK13B_BA , 0x38, 0xff); // reg_opm_meds_vlen
506 MDrv_WriteByteMask( REG_FRC_BK13B_BB , 0x04, 0x1f); // reg_opm_meds_vlen
507 MDrv_WriteByteMask( REG_FRC_BK13C_BA , 0x38, 0xff); // reg_opm_meds_vlen
508 MDrv_WriteByteMask( REG_FRC_BK13C_BB , 0x04, 0x1f); // reg_opm_meds_vlen
509 MDrv_WriteByteMask( REG_FRC_BK13D_BA , 0x38, 0xff); // reg_opm_meds_vlen
510 MDrv_WriteByteMask( REG_FRC_BK13D_BB , 0x04, 0x1f); // reg_opm_meds_vlen
511 MDrv_WriteByteMask( REG_FRC_BK134_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
512 MDrv_WriteByteMask( REG_FRC_BK134_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
513 MDrv_WriteByteMask( REG_FRC_BK136_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
514 MDrv_WriteByteMask( REG_FRC_BK136_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
515 MDrv_WriteByteMask( REG_FRC_BK13A_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
516 MDrv_WriteByteMask( REG_FRC_BK13A_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
517 MDrv_WriteByteMask( REG_FRC_BK13B_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
518 MDrv_WriteByteMask( REG_FRC_BK13B_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
519 MDrv_WriteByteMask( REG_FRC_BK13C_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
520 MDrv_WriteByteMask( REG_FRC_BK13C_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
521 MDrv_WriteByteMask( REG_FRC_BK13D_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
522 MDrv_WriteByteMask( REG_FRC_BK13D_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
523 // IPM_OPM_DSmode
524 MDrv_WriteByteMask( REG_FRC_BK13A_1C , 0xc0, 0xff); // reg_ipm_offset_f2
525 MDrv_WriteByteMask( REG_FRC_BK13A_1D , 0x03, 0xff); // reg_ipm_offset_f2
526 MDrv_WriteByteMask( REG_FRC_BK13A_1E , 0xc0, 0xff); // reg_ipm_fetch_num_f2
527 MDrv_WriteByteMask( REG_FRC_BK13A_1F , 0x03, 0xff); // reg_ipm_fetch_num_f2
528 MDrv_WriteByteMask( REG_FRC_BK13A_9C , 0xc0, 0xff); // reg_ipm_offset_f1
529 MDrv_WriteByteMask( REG_FRC_BK13A_9D , 0x03, 0xff); // reg_ipm_offset_f1
530 MDrv_WriteByteMask( REG_FRC_BK13A_9E , 0xc0, 0xff); // reg_ipm_fetch_num_f1
531 MDrv_WriteByteMask( REG_FRC_BK13A_9F , 0x03, 0xff); // reg_ipm_fetch_num_f1
532 MDrv_WriteByteMask( REG_FRC_BK134_BC , 0xc0, 0xff); // reg_opm_meds_offset
533 MDrv_WriteByteMask( REG_FRC_BK134_BD , 0x03, 0xff); // reg_opm_meds_offset
534 MDrv_WriteByteMask( REG_FRC_BK134_BE , 0xc0, 0xff); // reg_opm_meds_fetch_num
535 MDrv_WriteByteMask( REG_FRC_BK134_BF , 0x03, 0xff); // reg_opm_meds_fetch_num
536 // IPM_3D
537 MDrv_WriteByteMask( REG_FRC_BK135_1C , 0x00, 0xff); // reg_v_toggle_value
538 MDrv_WriteByteMask( REG_FRC_BK135_1D , 0x00, 0x0f); // reg_v_toggle_value
539 MDrv_WriteByteMask( REG_FRC_BK135_04 , 0x00, 0x30); // reg_v_toggle_en
540 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en
541 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x80, 0x80); // reg_ipm_meds_ud_en
542 MDrv_WriteByteMask( REG_FRC_BK134_26 , 0x38, 0xff); // reg_ipm_turn_back_line
543 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line
544 MDrv_WriteByteMask( REG_FRC_BK13A_26 , 0x1c, 0xff); // reg_ipm_turn_back_line_meds
545 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x02, 0x1f); // reg_ipm_turn_back_line_meds
546 // OPM_3D
547 MDrv_WriteByteMask( REG_FRC_BK134_60 , 0x00, 0x01); // reg_ipm_3d_en_f2
548 MDrv_WriteByteMask( REG_FRC_BK134_E0 , 0x00, 0x01); // reg_ipm_3d_en_f1
549 MDrv_WriteByteMask( REG_FRC_BK13A_60 , 0x00, 0x01); // reg_ipm_3d_en_mef3f4_f2
550 MDrv_WriteByteMask( REG_FRC_BK13A_E0 , 0x00, 0x01); // reg_ipm_3d_en_mef3f4_f1
551 MDrv_WriteByteMask( REG_FRC_BK134_66 , 0x00, 0x80); // reg_opm_3d_en_f2
552 MDrv_WriteByteMask( REG_FRC_BK136_66 , 0x00, 0x80); // reg_opm_3d_en_f1
553 MDrv_WriteByteMask( REG_FRC_BK13A_66 , 0x00, 0x80); // reg_opm_3d_en_mef3f4_f2
554 MDrv_WriteByteMask( REG_FRC_BK13B_66 , 0x00, 0x80); // reg_opm_3d_en_mef3f4_f1
555 MDrv_WriteByteMask( REG_FRC_BK13C_66 , 0x00, 0x80); // reg_opm_3d_en_mif3_f2
556 MDrv_WriteByteMask( REG_FRC_BK13D_66 , 0x00, 0x80); // reg_opm_3d_en_mif3_f1
557 MDrv_WriteByteMask( REG_FRC_BK134_67 , 0x00, 0x04); // reg_opm_passive_en_f2
558 MDrv_WriteByteMask( REG_FRC_BK136_67 , 0x00, 0x04); // reg_opm_passive_en_f1
559 MDrv_WriteByteMask( REG_FRC_BK13A_67 , 0x00, 0x04); // reg_opm_passive_en_f2
560 MDrv_WriteByteMask( REG_FRC_BK13B_67 , 0x00, 0x04); // reg_opm_passive_en_f1
561 MDrv_WriteByteMask( REG_FRC_BK13C_67 , 0x00, 0x04); // reg_opm_passive_en_f2
562 MDrv_WriteByteMask( REG_FRC_BK13D_67 , 0x00, 0x04); // reg_opm_passive_en_f1
563 MDrv_WriteByteMask( REG_FRC_BK134_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
564 MDrv_WriteByteMask( REG_FRC_BK136_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
565 MDrv_WriteByteMask( REG_FRC_BK13A_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
566 MDrv_WriteByteMask( REG_FRC_BK13B_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
567 MDrv_WriteByteMask( REG_FRC_BK13C_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
568 MDrv_WriteByteMask( REG_FRC_BK13D_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
569 // OPMRM
570 MDrv_WriteByteMask( REG_FRC_BK134_E8 , 0x00, 0x01); // reg_opm_ml_en
571 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x00, 0x08); // reg_rbk_free
572 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x00, 0x70); // reg_rbk_free_diff
573 MDrv_WriteByteMask( REG_FRC_BK134_32 , 0x00, 0x80); // reg_opm_2f_md
574 MDrv_WriteByteMask( REG_FRC_BK136_32 , 0x00, 0x80); // reg_opm_2f_md
575 MDrv_WriteByteMask( REG_FRC_BK134_33 , 0x01, 0x01); // reg_opm_3f_md
576 MDrv_WriteByteMask( REG_FRC_BK136_33 , 0x01, 0x01); // reg_opm_3f_md
577 MDrv_WriteByteMask( REG_FRC_BK134_CE , 0x05, 0x0f); // reg_opm_memc_md
578 MDrv_WriteByteMask( REG_FRC_BK134_CF , 0x04, 0x07); // reg_opm_memc_md
579 // HSD_MEDS
580 MDrv_WriteByteMask( REG_FRC_BK320_C2 , 0x33, 0xff); // reg_frc_ipm_hvsd_la_mode
581 MDrv_WriteByteMask( REG_FRC_BK320_C3 , 0x8e, 0xff); // reg_frc_ipm_hvsd_drop_mode
582 // MEMC_FSC
583 MDrv_WriteByteMask( REG_FRC_BK320_A4 , 0x00, 0xff); // reg_frc_xxxx
584 MDrv_WriteByteMask( REG_FRC_BK320_A5 , 0x0F, 0xff); // reg_frc_xxxx
585 MDrv_WriteByteMask( REG_FRC_BK320_A6 , 0x80, 0xff); // reg_frc_xxxx
586 MDrv_WriteByteMask( REG_FRC_BK320_A7 , 0x07, 0xff); // reg_frc_xxxx
587 // MLB
588 MDrv_WriteByteMask( REG_FRC_BK226_F4 , 0x01, 0xff); // reg_sadmvRangeL
589 MDrv_WriteByteMask( REG_FRC_BK226_F5 , 0x00, 0x03); // reg_sadmvRangeL
590 MDrv_WriteByteMask( REG_FRC_BK226_F8 , 0x01, 0xff); // reg_sadmvRangeU
591 MDrv_WriteByteMask( REG_FRC_BK226_F9 , 0x00, 0x01); // reg_sadmvRangeU
592 MDrv_WriteByteMask( REG_FRC_BK226_F6 , 0xff, 0xff); // reg_sadmvRangeR
593 MDrv_WriteByteMask( REG_FRC_BK226_F7 , 0x03, 0x03); // reg_sadmvRangeR
594 MDrv_WriteByteMask( REG_FRC_BK226_F2 , 0xff, 0xff); // reg_sadmvRangeD
595 MDrv_WriteByteMask( REG_FRC_BK226_F3 , 0x00, 0x01); // reg_sadmvRangeD
596 MDrv_WriteByteMask( REG_FRC_BK232_02 , 0x00, 0x02); // reg_pass3d_la
597 MDrv_WriteByteMask( REG_FRC_BK232_11 , 0x00, 0xc0); // reg_mask_en
598 // MV_PREPROC
599 MDrv_WriteByteMask( REG_FRC_BK22C_92 , 0x00, 0x03); // reg_mv_preprocess
600 // MFC_pipectrl
601 MDrv_WriteByteMask( REG_FRC_BK233_3E , 0x00, 0xff); // reg_ppctr_h_pixl_num_me
602 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me
603 MDrv_WriteByteMask( REG_FRC_BK233_40 , 0x38, 0xff); // reg_ppctr_v_line_num_me
604 MDrv_WriteByteMask( REG_FRC_BK233_41 , 0x04, 0x1f); // reg_ppctr_v_line_num_me
605 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi
606 MDrv_WriteByteMask( REG_FRC_BK233_47 , 0x0f, 0x1f); // reg_me_h_pixel_num_mi
607 MDrv_WriteByteMask( REG_FRC_BK233_48 , 0x70, 0xff); // reg_me_v_pixel_num_mi
608 MDrv_WriteByteMask( REG_FRC_BK233_49 , 0x08, 0x1f); // reg_me_v_pixel_num_mi
609 MDrv_WriteByteMask( REG_FRC_BK233_F8 , 0x00, 0xff); // reg_h_pixel_num_mlb
610 MDrv_WriteByteMask( REG_FRC_BK233_F9 , 0x0f, 0x1f); // reg_h_pixel_num_mlb
611 MDrv_WriteByteMask( REG_FRC_BK233_FA , 0x70, 0xff); // reg_v_pixel_num_mlb
612 MDrv_WriteByteMask( REG_FRC_BK233_FB , 0x08, 0x1f); // reg_v_pixel_num_mlb
613 MDrv_WriteByteMask( REG_FRC_BK233_3A , 0x00, 0xff); // reg_time_gen_sw_h_width
614 MDrv_WriteByteMask( REG_FRC_BK233_3B , 0x0f, 0x1f); // reg_time_gen_sw_h_width
615 MDrv_WriteByteMask( REG_FRC_BK233_3C , 0x1b, 0xff); // reg_time_gen_sw_v_width
616 MDrv_WriteByteMask( REG_FRC_BK233_3D , 0x02, 0x1f); // reg_time_gen_sw_v_width
617 MDrv_WriteByteMask( REG_FRC_BK233_42 , 0x80, 0xff); // reg_mlb_disp_pixel_latch
618 MDrv_WriteByteMask( REG_FRC_BK233_43 , 0x07, 0x1f); // reg_mlb_disp_pixel_latch
619 MDrv_WriteByteMask( REG_FRC_BK233_A8 , 0x00, 0xff); // reg_gmv_vertical_active_window_height
620 MDrv_WriteByteMask( REG_FRC_BK233_A9 , 0x01, 0x01); // reg_gmv_vertical_active_window_height
621 // MFC_VDUP
622 MDrv_WriteByteMask( REG_FRC_BK20A_04 , 0xC0, 0xFF); // reg_VDUP_width
623 MDrv_WriteByteMask( REG_FRC_BK20A_05 , 0x03, 0xFF); // reg_VDUP_width
624 MDrv_WriteByteMask( REG_FRC_BK20A_06 , 0x70, 0xFF); // reg_VDUP_height
625 MDrv_WriteByteMask( REG_FRC_BK20A_07 , 0x08, 0xFF); // reg_VDUP_height
626 // MFC
627 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable
628 MDrv_WriteByteMask( REG_FRC_BK226_70 , 0x20, 0x20); //
629 MDrv_WriteByteMask( REG_FRC_BK226_73 , 0x0f, 0x1f); // reg_h_pix_num_3D
630 MDrv_WriteByteMask( REG_FRC_BK226_72 , 0x00, 0xff); // reg_h_pix_num_3D
631 MDrv_WriteByteMask( REG_FRC_BK226_75 , 0x04, 0x1f); // reg_v_lin_num_3D
632 MDrv_WriteByteMask( REG_FRC_BK226_74 , 0x38, 0xff); // reg_v_lin_num_3D
633 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x08, 0x08); //
634 MDrv_WriteByteMask( REG_FRC_BK229_05 , 0x0f, 0xFF); // reg_h_pix_num_ME
635 MDrv_WriteByteMask( REG_FRC_BK229_04 , 0x00, 0xFF); // reg_h_pix_num_ME
636 MDrv_WriteByteMask( REG_FRC_BK229_07 , 0x08, 0x0F); // reg_v_lin_num_ME
637 MDrv_WriteByteMask( REG_FRC_BK229_06 , 0x70, 0xFF); // reg_v_lin_num_ME
638 MDrv_WriteByteMask( REG_FRC_BK229_91 , 0x0f, 0xFF); // reg_h_pix_num_MI
639 MDrv_WriteByteMask( REG_FRC_BK229_90 , 0x00, 0xFF); // reg_h_pix_num_MI
640 MDrv_WriteByteMask( REG_FRC_BK229_93 , 0x08, 0xFF); // reg_v_lin_num_MI
641 MDrv_WriteByteMask( REG_FRC_BK229_92 , 0x70, 0xFF); // reg_v_lin_num_MI
642 MDrv_WriteByteMask( REG_FRC_BK226_67 , 0x01, 0x01); // reg_422to444_en
643 MDrv_WriteByteMask( REG_FRC_BK232_D0 , 0x00, 0x02); // reg_rgb_bypass
644 MDrv_WriteByteMask( REG_FRC_BK226_60 , 0x80, 0x80); // reg_c_drop
645 MDrv_WriteByteMask( REG_FRC_BK229_9C , 0x80, 0x80); // reg_422_avgmode
646 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x01, 0x01); // reg_pipectrl_bypass
647 // MFC_Halo
648 MDrv_WriteByteMask( REG_FRC_BK22C_93 , 0x80, 0x80); // reg_halo_buf_frame_end_en
649 MDrv_WriteByteMask( REG_FRC_BK22C_A7 , 0x00, 0x02); // reg_halo_buf23_force_ready
650 // MFC_GMV
651 MDrv_WriteByteMask( REG_FRC_BK232_2A , 0x01, 0x01); // reg_gmv_in_ud_mode
652 // SNR
653 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en
654 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en
655 MDrv_WriteByteMask( REG_FRC_BK2E_E2 , 0x00, 0xff); // reg_snr_pix_num_LSB
656 MDrv_WriteByteMask( REG_FRC_BK2E_E3 , 0x0f, 0x1f); // reg_snr_pix_num_MSB
657 MDrv_WriteByteMask( REG_FRC_BK2E_E8 , 0x70, 0xff); // reg_snr_line_num_LSB
658 MDrv_WriteByteMask( REG_FRC_BK2E_E9 , 0x08, 0x0f); // reg_snr_line_num_MSB
659 // SNR_3D
660 MDrv_WriteByteMask( REG_FRC_BK2E_65 , 0x00, 0x20); // reg_line_switch
661 // SNR_VSU2X
662 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en
663 // FO_HSU
664 MDrv_WriteByteMask( REG_FRC_BK115_30 , 0x00, 0xff); // hfac_smd0
665 MDrv_WriteByteMask( REG_FRC_BK115_31 , 0x00, 0xff); // hfac_smd1
666 MDrv_WriteByteMask( REG_FRC_BK115_32 , 0x00, 0x3f); // hfac_smd2
667 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en
668 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en
669 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0
670 MDrv_WriteByteMask( REG_FRC_BK115_0D , 0x0f, 0x1f); // hsp_size_in1
671 MDrv_WriteByteMask( REG_FRC_BK115_0E , 0x00, 0xff); // hsp_size_out0
672 MDrv_WriteByteMask( REG_FRC_BK115_0F , 0x0f, 0x1f); // hsp_size_out1
673 // SPTP
674 MDrv_WriteByteMask( REG_FRC_BK3E_80 , 0xff, 0xff); // reg_sptp_mfc_dc_m1
675 MDrv_WriteByteMask( REG_FRC_BK3E_81 , 0x0e, 0x0f); // reg_sptp_mfc_dc_m1
676 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en
677 MDrv_WriteByteMask( REG_FRC_BK3E_84 , 0x01, 0x01); // reg_sptp_usr_en
678 MDrv_WriteByteMask( REG_FRC_BK3E_88 , 0x00, 0xff); // reg_sptp_f0_st
679 MDrv_WriteByteMask( REG_FRC_BK3E_89 , 0x00, 0x01); // reg_sptp_f0_st
680 MDrv_WriteByteMask( REG_FRC_BK3E_8A , 0xf1, 0xff); // reg_sptp_f0_end
681 MDrv_WriteByteMask( REG_FRC_BK3E_8B , 0x00, 0x01); // reg_sptp_f0_end
682 MDrv_WriteByteMask( REG_FRC_BK3E_8C , 0xee, 0xff); // reg_sptp_f1_st
683 MDrv_WriteByteMask( REG_FRC_BK3E_8D , 0x00, 0x01); // reg_sptp_f1_st
684 MDrv_WriteByteMask( REG_FRC_BK3E_8E , 0xdf, 0xff); // reg_sptp_f1_end
685 MDrv_WriteByteMask( REG_FRC_BK3E_8F , 0x01, 0x01); // reg_sptp_f1_end
686 MDrv_WriteByteMask( REG_FRC_BK3E_86 , 0x02, 0xff); // reg_sptp_gb_en
687 // CSC
688 }
689
690
691
692 /********************************************/
693 // 2D_4K2K_RGB_BYPASS
MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS(void)694 void MFC_3D_2D_4K2K_2D_4K2K_RGB_BYPASS(void)
695 {
696 // FSC_TOP
697 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass
698 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md
699 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass
700 // VSU
701 MDrv_WriteByteMask( REG_SC_BK4F_12, 0x00, 0xff); // vsp_scl_fac0
702 MDrv_WriteByteMask( REG_SC_BK4F_13, 0x00, 0xff); // vsp_scl_fac1
703 MDrv_WriteByteMask( REG_SC_BK4F_14, 0x10, 0xff); // vsp_scl_fac2
704 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x01, 0x01); // vsp_scl_en
705 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x00, 0x02); // vsp_shift_mode_en
706 MDrv_WriteByteMask( REG_SC_BK4F_06, 0x00, 0xff); // vsp_ini_scl_fac0
707 MDrv_WriteByteMask( REG_SC_BK4F_07, 0x00, 0xff); // vsp_ini_scl_fac1
708 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2
709 MDrv_WriteByteMask( REG_SC_BK4F_52, 0x70, 0xff); // vsp_vsize_in0
710 MDrv_WriteByteMask( REG_SC_BK4F_53, 0x08, 0xff); // vsp_vsize_in1
711 MDrv_WriteByteMask( REG_SC_BK4F_56, 0x70, 0xff); // vsp_vsize_out0
712 MDrv_WriteByteMask( REG_SC_BK4F_57, 0x08, 0xff); // vsp_vsize_out1
713 // HSU
714 MDrv_WriteByteMask( REG_SC_BK4F_0E, 0x00, 0xff); // hsp_scl_fac0
715 MDrv_WriteByteMask( REG_SC_BK4F_0F, 0x00, 0xff); // hsp_scl_fac1
716 MDrv_WriteByteMask( REG_SC_BK4F_10, 0x10, 0xff); // hsp_scl_fac2
717 MDrv_WriteByteMask( REG_SC_BK4F_11, 0x01, 0x01); // hsp_scl_en
718 MDrv_WriteByteMask( REG_SC_BK4F_11, 0x00, 0x02); // hsp_shift_mode_en
719 MDrv_WriteByteMask( REG_SC_BK4F_02, 0x00, 0xff); // hsp_ini_scl_fac0
720 MDrv_WriteByteMask( REG_SC_BK4F_03, 0x00, 0xff); // hsp_ini_scl_fac1
721 MDrv_WriteByteMask( REG_SC_BK4F_04, 0x00, 0xff); // hsp_ini_scl_fac2
722 MDrv_WriteByteMask( REG_SC_BK4F_50, 0x00, 0xff); // hsp_hsize_in0
723 MDrv_WriteByteMask( REG_SC_BK4F_51, 0x0f, 0xff); // hsp_hsize_in1
724 MDrv_WriteByteMask( REG_SC_BK4F_54, 0x00, 0xff); // hsp_hsize_out0
725 MDrv_WriteByteMask( REG_SC_BK4F_55, 0x0f, 0xff); // hsp_hsize_out1
726 // SPTF_D2LR
727 MDrv_WriteByteMask( REG_FRC_BK33A_60 , 0x00, 0xff); // gb_cut_st_l
728 MDrv_WriteByteMask( REG_FRC_BK33A_61 , 0x00, 0xff); // gb_cut_st_l
729 MDrv_WriteByteMask( REG_FRC_BK33A_62 , 0x80, 0xff); // gb_cut_end_l
730 MDrv_WriteByteMask( REG_FRC_BK33A_63 , 0x07, 0xff); // gb_cut_end_l
731 MDrv_WriteByteMask( REG_FRC_BK33A_64 , 0x80, 0xff); // gb_cut_st_r
732 MDrv_WriteByteMask( REG_FRC_BK33A_65 , 0x00, 0xff); // gb_cut_st_r
733 MDrv_WriteByteMask( REG_FRC_BK33A_66 , 0xff, 0xff); // gb_cut_end_r
734 MDrv_WriteByteMask( REG_FRC_BK33A_67 , 0x1f, 0xff); // gb_cut_end_r
735 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass
736 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo
737 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr
738 MDrv_WriteByteMask( REG_FRC_BK33A_52 , 0x80, 0xff); // d2lr_output_h
739 MDrv_WriteByteMask( REG_FRC_BK33A_53 , 0x08, 0xff); // d2lr_output_h
740 MDrv_WriteByteMask( REG_FRC_BK33A_40 , 0x00, 0xff); // d2lr_w0_st
741 MDrv_WriteByteMask( REG_FRC_BK33A_41 , 0x00, 0xff); // d2lr_w0_st
742 MDrv_WriteByteMask( REG_FRC_BK33A_42 , 0xff, 0xff); // d2lr_w0_end
743 MDrv_WriteByteMask( REG_FRC_BK33A_43 , 0x0e, 0xff); // d2lr_w0_end
744 MDrv_WriteByteMask( REG_FRC_BK33A_44 , 0x00, 0xff); // d2lr_w1_st
745 MDrv_WriteByteMask( REG_FRC_BK33A_45 , 0x00, 0xff); // d2lr_w1_st
746 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end
747 MDrv_WriteByteMask( REG_FRC_BK33A_47 , 0x0e, 0xff); // d2lr_w1_end
748 MDrv_WriteByteMask( REG_FRC_BK33A_48 , 0x00, 0xff); // d2lr_r0_st
749 MDrv_WriteByteMask( REG_FRC_BK33A_49 , 0x00, 0xff); // d2lr_r0_st
750 MDrv_WriteByteMask( REG_FRC_BK33A_4A , 0x7f, 0xff); // d2lr_r0_end
751 MDrv_WriteByteMask( REG_FRC_BK33A_4B , 0x08, 0xff); // d2lr_r0_end
752 MDrv_WriteByteMask( REG_FRC_BK33A_4C , 0x80, 0xff); // d2lr_r1_st
753 MDrv_WriteByteMask( REG_FRC_BK33A_4D , 0x06, 0xff); // d2lr_r1_st
754 MDrv_WriteByteMask( REG_FRC_BK33A_4E , 0xff, 0xff); // d2lr_r1_end
755 MDrv_WriteByteMask( REG_FRC_BK33A_4F , 0x0e, 0xff); // d2lr_r1_end
756 // FSC_3D
757 MDrv_WriteByteMask( REG_SC_BK4F_21, 0x00, 0x40); // reg_3d_top_bot_en
758 MDrv_WriteByteMask( REG_SC_BK4F_21, 0x00, 0x80); // reg_3d_sbs_en
759 // IPM_OPM
760 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2
761 MDrv_WriteByteMask( REG_FRC_BK134_1D , 0x07, 0xff); // ipm_offset_f2
762 MDrv_WriteByteMask( REG_FRC_BK134_1E , 0x80, 0xff); // ipm_fetch_f2
763 MDrv_WriteByteMask( REG_FRC_BK134_1F , 0x07, 0xff); // ipm_fetch_f2
764 MDrv_WriteByteMask( REG_FRC_BK134_04 , 0x01, 0xff); // ipm_mem_config_f2
765 MDrv_WriteByteMask( REG_FRC_BK134_05 , 0x01, 0xff); // ipm_mem_config_f2
766 MDrv_WriteByteMask( REG_FRC_BK13A_04 , 0x03, 0xff); // ipm_mem_config_f2
767 MDrv_WriteByteMask( REG_FRC_BK13A_05 , 0x31, 0xff); // ipm_mem_config_f2
768 MDrv_WriteByteMask( REG_FRC_BK13A_84 , 0x03, 0xff); // ipm_mem_config_f2
769 MDrv_WriteByteMask( REG_FRC_BK13A_85 , 0x31, 0xff); // ipm_mem_config_f2
770 MDrv_WriteByteMask( REG_FRC_BK134_9C , 0x80, 0xff); // ipm_fetch_f1
771 MDrv_WriteByteMask( REG_FRC_BK134_9D , 0x07, 0xff); // ipm_fetch_f1
772 MDrv_WriteByteMask( REG_FRC_BK134_9E , 0x80, 0xff); // ipm_offset_f1
773 MDrv_WriteByteMask( REG_FRC_BK134_9F , 0x07, 0xff); // ipm_offset_f1
774 MDrv_WriteByteMask( REG_FRC_BK134_84 , 0x01, 0xff); // ipm_mem_config_f1
775 MDrv_WriteByteMask( REG_FRC_BK134_85 , 0x01, 0xff); // ipm_mem_config_f1
776 MDrv_WriteByteMask( REG_FRC_BK134_2C , 0x80, 0xff); // opm_offset_f2
777 MDrv_WriteByteMask( REG_FRC_BK134_2D , 0x07, 0xff); // opm_offset_f2
778 MDrv_WriteByteMask( REG_FRC_BK134_2E , 0x80, 0xff); // opm_fetch_f2
779 MDrv_WriteByteMask( REG_FRC_BK134_2F , 0x07, 0xff); // opm_fetch_f2
780 MDrv_WriteByteMask( REG_FRC_BK134_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
781 MDrv_WriteByteMask( REG_FRC_BK134_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
782 MDrv_WriteByteMask( REG_FRC_BK136_2C , 0x80, 0xff); // opm_offset_f1
783 MDrv_WriteByteMask( REG_FRC_BK136_2D , 0x07, 0xff); // opm_offset_f1
784 MDrv_WriteByteMask( REG_FRC_BK136_2E , 0x80, 0xff); // opm_fetch_f1
785 MDrv_WriteByteMask( REG_FRC_BK136_2F , 0x07, 0xff); // opm_fetch_f1
786 MDrv_WriteByteMask( REG_FRC_BK136_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
787 MDrv_WriteByteMask( REG_FRC_BK136_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
788 MDrv_WriteByteMask( REG_FRC_BK13A_2C , 0x80, 0xff); // opm_offset_f2
789 MDrv_WriteByteMask( REG_FRC_BK13A_2D , 0x07, 0xff); // opm_offset_f2
790 MDrv_WriteByteMask( REG_FRC_BK13A_2E , 0x80, 0xff); // opm_fetch_f2
791 MDrv_WriteByteMask( REG_FRC_BK13A_2F , 0x07, 0xff); // opm_fetch_f2
792 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
793 MDrv_WriteByteMask( REG_FRC_BK13A_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
794 MDrv_WriteByteMask( REG_FRC_BK13B_2C , 0x80, 0xff); // opm_offset_f1
795 MDrv_WriteByteMask( REG_FRC_BK13B_2D , 0x07, 0xff); // opm_offset_f1
796 MDrv_WriteByteMask( REG_FRC_BK13B_2E , 0x80, 0xff); // opm_fetch_f1
797 MDrv_WriteByteMask( REG_FRC_BK13B_2F , 0x07, 0xff); // opm_fetch_f1
798 MDrv_WriteByteMask( REG_FRC_BK13B_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
799 MDrv_WriteByteMask( REG_FRC_BK13B_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
800 MDrv_WriteByteMask( REG_FRC_BK13C_2C , 0x80, 0xff); // opm_offset_f2
801 MDrv_WriteByteMask( REG_FRC_BK13C_2D , 0x07, 0xff); // opm_offset_f2
802 MDrv_WriteByteMask( REG_FRC_BK13C_2E , 0x80, 0xff); // opm_fetch_f2
803 MDrv_WriteByteMask( REG_FRC_BK13C_2F , 0x07, 0xff); // opm_fetch_f2
804 MDrv_WriteByteMask( REG_FRC_BK13C_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
805 MDrv_WriteByteMask( REG_FRC_BK13C_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
806 MDrv_WriteByteMask( REG_FRC_BK13D_2C , 0x80, 0xff); // opm_offset_f1
807 MDrv_WriteByteMask( REG_FRC_BK13D_2D , 0x07, 0xff); // opm_offset_f1
808 MDrv_WriteByteMask( REG_FRC_BK13D_2E , 0x80, 0xff); // opm_fetch_f1
809 MDrv_WriteByteMask( REG_FRC_BK13D_2F , 0x07, 0xff); // opm_fetch_f1
810 MDrv_WriteByteMask( REG_FRC_BK13D_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
811 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
812 // IPM_OPM_vlen
813 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel
814 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel
815 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel
816 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel
817 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel
818 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x80, 0x80); // reg_opm_vlen_sel
819 MDrv_WriteByteMask( REG_FRC_BK134_62 , 0x70, 0xff); // reg_opm_vlen
820 MDrv_WriteByteMask( REG_FRC_BK134_63 , 0x08, 0x1f); // reg_opm_vlen
821 MDrv_WriteByteMask( REG_FRC_BK136_62 , 0x70, 0xff); // reg_opm_vlen
822 MDrv_WriteByteMask( REG_FRC_BK136_63 , 0x08, 0x1f); // reg_opm_vlen
823 MDrv_WriteByteMask( REG_FRC_BK13A_62 , 0x70, 0xff); // reg_opm_vlen
824 MDrv_WriteByteMask( REG_FRC_BK13A_63 , 0x08, 0x1f); // reg_opm_vlen
825 MDrv_WriteByteMask( REG_FRC_BK13B_62 , 0x70, 0xff); // reg_opm_vlen
826 MDrv_WriteByteMask( REG_FRC_BK13B_63 , 0x08, 0x1f); // reg_opm_vlen
827 MDrv_WriteByteMask( REG_FRC_BK13C_62 , 0x70, 0xff); // reg_opm_vlen
828 MDrv_WriteByteMask( REG_FRC_BK13C_63 , 0x08, 0x1f); // reg_opm_vlen
829 MDrv_WriteByteMask( REG_FRC_BK13D_62 , 0x70, 0xff); // reg_opm_vlen
830 MDrv_WriteByteMask( REG_FRC_BK13D_63 , 0x08, 0x1f); // reg_opm_vlen
831 MDrv_WriteByteMask( REG_FRC_BK134_CC , 0x70, 0xff); // reg_opm_vlen_new
832 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new
833 MDrv_WriteByteMask( REG_FRC_BK136_CC , 0x70, 0xff); // reg_opm_vlen_new
834 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new
835 MDrv_WriteByteMask( REG_FRC_BK13A_CC , 0x70, 0xff); // reg_opm_vlen_new
836 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new
837 MDrv_WriteByteMask( REG_FRC_BK13B_CC , 0x70, 0xff); // reg_opm_vlen_new
838 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new
839 MDrv_WriteByteMask( REG_FRC_BK13C_CC , 0x70, 0xff); // reg_opm_vlen_new
840 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new
841 MDrv_WriteByteMask( REG_FRC_BK13D_CC , 0x70, 0xff); // reg_opm_vlen_new
842 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x08, 0x1f); // reg_opm_vlen_new
843 MDrv_WriteByteMask( REG_FRC_BK134_BA , 0x38, 0xff); // reg_opm_meds_vlen
844 MDrv_WriteByteMask( REG_FRC_BK134_BB , 0x04, 0x1f); // reg_opm_meds_vlen
845 MDrv_WriteByteMask( REG_FRC_BK136_BA , 0x38, 0xff); // reg_opm_meds_vlen
846 MDrv_WriteByteMask( REG_FRC_BK136_BB , 0x04, 0x1f); // reg_opm_meds_vlen
847 MDrv_WriteByteMask( REG_FRC_BK13A_BA , 0x38, 0xff); // reg_opm_meds_vlen
848 MDrv_WriteByteMask( REG_FRC_BK13A_BB , 0x04, 0x1f); // reg_opm_meds_vlen
849 MDrv_WriteByteMask( REG_FRC_BK13B_BA , 0x38, 0xff); // reg_opm_meds_vlen
850 MDrv_WriteByteMask( REG_FRC_BK13B_BB , 0x04, 0x1f); // reg_opm_meds_vlen
851 MDrv_WriteByteMask( REG_FRC_BK13C_BA , 0x38, 0xff); // reg_opm_meds_vlen
852 MDrv_WriteByteMask( REG_FRC_BK13C_BB , 0x04, 0x1f); // reg_opm_meds_vlen
853 MDrv_WriteByteMask( REG_FRC_BK13D_BA , 0x38, 0xff); // reg_opm_meds_vlen
854 MDrv_WriteByteMask( REG_FRC_BK13D_BB , 0x04, 0x1f); // reg_opm_meds_vlen
855 MDrv_WriteByteMask( REG_FRC_BK134_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
856 MDrv_WriteByteMask( REG_FRC_BK134_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
857 MDrv_WriteByteMask( REG_FRC_BK136_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
858 MDrv_WriteByteMask( REG_FRC_BK136_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
859 MDrv_WriteByteMask( REG_FRC_BK13A_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
860 MDrv_WriteByteMask( REG_FRC_BK13A_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
861 MDrv_WriteByteMask( REG_FRC_BK13B_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
862 MDrv_WriteByteMask( REG_FRC_BK13B_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
863 MDrv_WriteByteMask( REG_FRC_BK13C_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
864 MDrv_WriteByteMask( REG_FRC_BK13C_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
865 MDrv_WriteByteMask( REG_FRC_BK13D_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
866 MDrv_WriteByteMask( REG_FRC_BK13D_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
867 // IPM_OPM_DSmode
868 MDrv_WriteByteMask( REG_FRC_BK13A_1C , 0xc0, 0xff); // reg_ipm_offset_f2
869 MDrv_WriteByteMask( REG_FRC_BK13A_1D , 0x03, 0xff); // reg_ipm_offset_f2
870 MDrv_WriteByteMask( REG_FRC_BK13A_1E , 0xc0, 0xff); // reg_ipm_fetch_num_f2
871 MDrv_WriteByteMask( REG_FRC_BK13A_1F , 0x03, 0xff); // reg_ipm_fetch_num_f2
872 MDrv_WriteByteMask( REG_FRC_BK13A_9C , 0xc0, 0xff); // reg_ipm_offset_f1
873 MDrv_WriteByteMask( REG_FRC_BK13A_9D , 0x03, 0xff); // reg_ipm_offset_f1
874 MDrv_WriteByteMask( REG_FRC_BK13A_9E , 0xc0, 0xff); // reg_ipm_fetch_num_f1
875 MDrv_WriteByteMask( REG_FRC_BK13A_9F , 0x03, 0xff); // reg_ipm_fetch_num_f1
876 MDrv_WriteByteMask( REG_FRC_BK134_BC , 0xc0, 0xff); // reg_opm_meds_offset
877 MDrv_WriteByteMask( REG_FRC_BK134_BD , 0x03, 0xff); // reg_opm_meds_offset
878 MDrv_WriteByteMask( REG_FRC_BK134_BE , 0xc0, 0xff); // reg_opm_meds_fetch_num
879 MDrv_WriteByteMask( REG_FRC_BK134_BF , 0x03, 0xff); // reg_opm_meds_fetch_num
880 // IPM_3D
881 MDrv_WriteByteMask( REG_FRC_BK135_1C , 0x00, 0xff); // reg_v_toggle_value
882 MDrv_WriteByteMask( REG_FRC_BK135_1D , 0x00, 0x0f); // reg_v_toggle_value
883 MDrv_WriteByteMask( REG_FRC_BK135_04 , 0x00, 0x30); // reg_v_toggle_en
884 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en
885 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x80, 0x80); // reg_ipm_meds_ud_en
886 MDrv_WriteByteMask( REG_FRC_BK134_26 , 0x38, 0xff); // reg_ipm_turn_back_line
887 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line
888 MDrv_WriteByteMask( REG_FRC_BK13A_26 , 0x1c, 0xff); // reg_ipm_turn_back_line_meds
889 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x02, 0x1f); // reg_ipm_turn_back_line_meds
890 // OPM_3D
891 MDrv_WriteByteMask( REG_FRC_BK134_60 , 0x00, 0x01); // reg_ipm_3d_en_f2
892 MDrv_WriteByteMask( REG_FRC_BK134_E0 , 0x00, 0x01); // reg_ipm_3d_en_f1
893 MDrv_WriteByteMask( REG_FRC_BK13A_60 , 0x00, 0x01); // reg_ipm_3d_en_mef3f4_f2
894 MDrv_WriteByteMask( REG_FRC_BK13A_E0 , 0x00, 0x01); // reg_ipm_3d_en_mef3f4_f1
895 MDrv_WriteByteMask( REG_FRC_BK134_66 , 0x00, 0x80); // reg_opm_3d_en_f2
896 MDrv_WriteByteMask( REG_FRC_BK136_66 , 0x00, 0x80); // reg_opm_3d_en_f1
897 MDrv_WriteByteMask( REG_FRC_BK13A_66 , 0x00, 0x80); // reg_opm_3d_en_mef3f4_f2
898 MDrv_WriteByteMask( REG_FRC_BK13B_66 , 0x00, 0x80); // reg_opm_3d_en_mef3f4_f1
899 MDrv_WriteByteMask( REG_FRC_BK13C_66 , 0x00, 0x80); // reg_opm_3d_en_mif3_f2
900 MDrv_WriteByteMask( REG_FRC_BK13D_66 , 0x00, 0x80); // reg_opm_3d_en_mif3_f1
901 MDrv_WriteByteMask( REG_FRC_BK134_67 , 0x00, 0x04); // reg_opm_passive_en_f2
902 MDrv_WriteByteMask( REG_FRC_BK136_67 , 0x00, 0x04); // reg_opm_passive_en_f1
903 MDrv_WriteByteMask( REG_FRC_BK13A_67 , 0x00, 0x04); // reg_opm_passive_en_f2
904 MDrv_WriteByteMask( REG_FRC_BK13B_67 , 0x00, 0x04); // reg_opm_passive_en_f1
905 MDrv_WriteByteMask( REG_FRC_BK13C_67 , 0x00, 0x04); // reg_opm_passive_en_f2
906 MDrv_WriteByteMask( REG_FRC_BK13D_67 , 0x00, 0x04); // reg_opm_passive_en_f1
907 MDrv_WriteByteMask( REG_FRC_BK134_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
908 MDrv_WriteByteMask( REG_FRC_BK136_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
909 MDrv_WriteByteMask( REG_FRC_BK13A_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
910 MDrv_WriteByteMask( REG_FRC_BK13B_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
911 MDrv_WriteByteMask( REG_FRC_BK13C_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
912 MDrv_WriteByteMask( REG_FRC_BK13D_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
913 // OPMRM
914 MDrv_WriteByteMask( REG_FRC_BK134_E8 , 0x01, 0x01); // reg_opm_ml_en
915 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x08, 0x08); // reg_rbk_free
916 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x10, 0x70); // reg_rbk_free_diff
917 MDrv_WriteByteMask( REG_FRC_BK134_32 , 0x00, 0x80); // reg_opm_2f_md
918 MDrv_WriteByteMask( REG_FRC_BK136_32 , 0x00, 0x80); // reg_opm_2f_md
919 MDrv_WriteByteMask( REG_FRC_BK134_33 , 0x00, 0x01); // reg_opm_3f_md
920 MDrv_WriteByteMask( REG_FRC_BK136_33 , 0x00, 0x01); // reg_opm_3f_md
921 MDrv_WriteByteMask( REG_FRC_BK134_CE , 0x00, 0x0f); // reg_opm_memc_md
922 MDrv_WriteByteMask( REG_FRC_BK134_CF , 0x00, 0x07); // reg_opm_memc_md
923 // HSD_MEDS
924 MDrv_WriteByteMask( REG_FRC_BK320_C2 , 0x33, 0xff); // reg_frc_ipm_hvsd_la_mode
925 MDrv_WriteByteMask( REG_FRC_BK320_C3 , 0x8e, 0xff); // reg_frc_ipm_hvsd_drop_mode
926 // MEMC_FSC
927 MDrv_WriteByteMask( REG_FRC_BK320_A4 , 0x00, 0xff); // reg_frc_xxxx
928 MDrv_WriteByteMask( REG_FRC_BK320_A5 , 0x0F, 0xff); // reg_frc_xxxx
929 MDrv_WriteByteMask( REG_FRC_BK320_A6 , 0x80, 0xff); // reg_frc_xxxx
930 MDrv_WriteByteMask( REG_FRC_BK320_A7 , 0x07, 0xff); // reg_frc_xxxx
931 // MLB
932 MDrv_WriteByteMask( REG_FRC_BK226_F4 , 0x01, 0xff); // reg_sadmvRangeL
933 MDrv_WriteByteMask( REG_FRC_BK226_F5 , 0x00, 0x03); // reg_sadmvRangeL
934 MDrv_WriteByteMask( REG_FRC_BK226_F8 , 0x01, 0xff); // reg_sadmvRangeU
935 MDrv_WriteByteMask( REG_FRC_BK226_F9 , 0x00, 0x01); // reg_sadmvRangeU
936 MDrv_WriteByteMask( REG_FRC_BK226_F6 , 0xff, 0xff); // reg_sadmvRangeR
937 MDrv_WriteByteMask( REG_FRC_BK226_F7 , 0x03, 0x03); // reg_sadmvRangeR
938 MDrv_WriteByteMask( REG_FRC_BK226_F2 , 0xff, 0xff); // reg_sadmvRangeD
939 MDrv_WriteByteMask( REG_FRC_BK226_F3 , 0x00, 0x01); // reg_sadmvRangeD
940 MDrv_WriteByteMask( REG_FRC_BK232_02 , 0x00, 0x02); // reg_pass3d_la
941 MDrv_WriteByteMask( REG_FRC_BK232_11 , 0x00, 0xc0); // reg_mask_en
942 // MV_PREPROC
943 MDrv_WriteByteMask( REG_FRC_BK22C_92 , 0x00, 0x03); // reg_mv_preprocess
944 // MFC_pipectrl
945 MDrv_WriteByteMask( REG_FRC_BK233_3E , 0x00, 0xff); // reg_ppctr_h_pixl_num_me
946 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me
947 MDrv_WriteByteMask( REG_FRC_BK233_40 , 0x38, 0xff); // reg_ppctr_v_line_num_me
948 MDrv_WriteByteMask( REG_FRC_BK233_41 , 0x04, 0x1f); // reg_ppctr_v_line_num_me
949 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi
950 MDrv_WriteByteMask( REG_FRC_BK233_47 , 0x0f, 0x1f); // reg_me_h_pixel_num_mi
951 MDrv_WriteByteMask( REG_FRC_BK233_48 , 0x70, 0xff); // reg_me_v_pixel_num_mi
952 MDrv_WriteByteMask( REG_FRC_BK233_49 , 0x08, 0x1f); // reg_me_v_pixel_num_mi
953 MDrv_WriteByteMask( REG_FRC_BK233_F8 , 0x00, 0xff); // reg_h_pixel_num_mlb
954 MDrv_WriteByteMask( REG_FRC_BK233_F9 , 0x0f, 0x1f); // reg_h_pixel_num_mlb
955 MDrv_WriteByteMask( REG_FRC_BK233_FA , 0x70, 0xff); // reg_v_pixel_num_mlb
956 MDrv_WriteByteMask( REG_FRC_BK233_FB , 0x08, 0x1f); // reg_v_pixel_num_mlb
957 MDrv_WriteByteMask( REG_FRC_BK233_3A , 0x00, 0xff); // reg_time_gen_sw_h_width
958 MDrv_WriteByteMask( REG_FRC_BK233_3B , 0x0f, 0x1f); // reg_time_gen_sw_h_width
959 MDrv_WriteByteMask( REG_FRC_BK233_3C , 0x1b, 0xff); // reg_time_gen_sw_v_width
960 MDrv_WriteByteMask( REG_FRC_BK233_3D , 0x02, 0x1f); // reg_time_gen_sw_v_width
961 MDrv_WriteByteMask( REG_FRC_BK233_42 , 0x80, 0xff); // reg_mlb_disp_pixel_latch
962 MDrv_WriteByteMask( REG_FRC_BK233_43 , 0x07, 0x1f); // reg_mlb_disp_pixel_latch
963 MDrv_WriteByteMask( REG_FRC_BK233_A8 , 0x00, 0xff); // reg_gmv_vertical_active_window_height
964 MDrv_WriteByteMask( REG_FRC_BK233_A9 , 0x01, 0x01); // reg_gmv_vertical_active_window_height
965 // MFC_VDUP
966 MDrv_WriteByteMask( REG_FRC_BK20A_04 , 0xC0, 0xFF); // reg_VDUP_width
967 MDrv_WriteByteMask( REG_FRC_BK20A_05 , 0x03, 0xFF); // reg_VDUP_width
968 MDrv_WriteByteMask( REG_FRC_BK20A_06 , 0x70, 0xFF); // reg_VDUP_height
969 MDrv_WriteByteMask( REG_FRC_BK20A_07 , 0x08, 0xFF); // reg_VDUP_height
970 // MFC
971 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x72, 0xff); // reg_MFC_enable
972 MDrv_WriteByteMask( REG_FRC_BK226_70 , 0x00, 0x20); //
973 MDrv_WriteByteMask( REG_FRC_BK226_73 , 0x0f, 0x1f); // reg_h_pix_num_3D
974 MDrv_WriteByteMask( REG_FRC_BK226_72 , 0x00, 0xff); // reg_h_pix_num_3D
975 MDrv_WriteByteMask( REG_FRC_BK226_75 , 0x04, 0x1f); // reg_v_lin_num_3D
976 MDrv_WriteByteMask( REG_FRC_BK226_74 , 0x38, 0xff); // reg_v_lin_num_3D
977 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x08, 0x08); //
978 MDrv_WriteByteMask( REG_FRC_BK229_05 , 0x0f, 0xFF); // reg_h_pix_num_ME
979 MDrv_WriteByteMask( REG_FRC_BK229_04 , 0x00, 0xFF); // reg_h_pix_num_ME
980 MDrv_WriteByteMask( REG_FRC_BK229_07 , 0x08, 0x0F); // reg_v_lin_num_ME
981 MDrv_WriteByteMask( REG_FRC_BK229_06 , 0x70, 0xFF); // reg_v_lin_num_ME
982 MDrv_WriteByteMask( REG_FRC_BK229_91 , 0x0f, 0xFF); // reg_h_pix_num_MI
983 MDrv_WriteByteMask( REG_FRC_BK229_90 , 0x00, 0xFF); // reg_h_pix_num_MI
984 MDrv_WriteByteMask( REG_FRC_BK229_93 , 0x08, 0xFF); // reg_v_lin_num_MI
985 MDrv_WriteByteMask( REG_FRC_BK229_92 , 0x70, 0xFF); // reg_v_lin_num_MI
986 MDrv_WriteByteMask( REG_FRC_BK226_67 , 0x00, 0x01); // reg_422to444_en
987 MDrv_WriteByteMask( REG_FRC_BK232_D0 , 0x02, 0x02); // reg_rgb_bypass
988 MDrv_WriteByteMask( REG_FRC_BK226_60 , 0x00, 0x80); // reg_c_drop
989 MDrv_WriteByteMask( REG_FRC_BK229_9C , 0x00, 0x80); // reg_422_avgmode
990 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x00, 0x01); // reg_pipectrl_bypass
991 // MFC_Halo
992 MDrv_WriteByteMask( REG_FRC_BK22C_93 , 0x80, 0x80); // reg_halo_buf_frame_end_en
993 MDrv_WriteByteMask( REG_FRC_BK22C_A7 , 0x00, 0x02); // reg_halo_buf23_force_ready
994 // MFC_GMV
995 MDrv_WriteByteMask( REG_FRC_BK232_2A , 0x01, 0x01); // reg_gmv_in_ud_mode
996 // SNR
997 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en
998 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en
999 MDrv_WriteByteMask( REG_FRC_BK2E_E2 , 0x00, 0xff); // reg_snr_pix_num_LSB
1000 MDrv_WriteByteMask( REG_FRC_BK2E_E3 , 0x0f, 0x1f); // reg_snr_pix_num_MSB
1001 MDrv_WriteByteMask( REG_FRC_BK2E_E8 , 0x70, 0xff); // reg_snr_line_num_LSB
1002 MDrv_WriteByteMask( REG_FRC_BK2E_E9 , 0x08, 0x0f); // reg_snr_line_num_MSB
1003 // SNR_3D
1004 MDrv_WriteByteMask( REG_FRC_BK2E_65 , 0x00, 0x20); // reg_line_switch
1005 // SNR_VSU2X
1006 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en
1007 // FO_HSU
1008 MDrv_WriteByteMask( REG_FRC_BK115_30 , 0x00, 0xff); // hfac_smd0
1009 MDrv_WriteByteMask( REG_FRC_BK115_31 , 0x00, 0xff); // hfac_smd1
1010 MDrv_WriteByteMask( REG_FRC_BK115_32 , 0x00, 0x3f); // hfac_smd2
1011 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en
1012 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en
1013 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0
1014 MDrv_WriteByteMask( REG_FRC_BK115_0D , 0x0f, 0x1f); // hsp_size_in1
1015 MDrv_WriteByteMask( REG_FRC_BK115_0E , 0x00, 0xff); // hsp_size_out0
1016 MDrv_WriteByteMask( REG_FRC_BK115_0F , 0x0f, 0x1f); // hsp_size_out1
1017 // SPTP
1018 MDrv_WriteByteMask( REG_FRC_BK3E_80 , 0xff, 0xff); // reg_sptp_mfc_dc_m1
1019 MDrv_WriteByteMask( REG_FRC_BK3E_81 , 0x0e, 0x0f); // reg_sptp_mfc_dc_m1
1020 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en
1021 MDrv_WriteByteMask( REG_FRC_BK3E_84 , 0x01, 0x01); // reg_sptp_usr_en
1022 MDrv_WriteByteMask( REG_FRC_BK3E_88 , 0x00, 0xff); // reg_sptp_f0_st
1023 MDrv_WriteByteMask( REG_FRC_BK3E_89 , 0x00, 0x01); // reg_sptp_f0_st
1024 MDrv_WriteByteMask( REG_FRC_BK3E_8A , 0xf1, 0xff); // reg_sptp_f0_end
1025 MDrv_WriteByteMask( REG_FRC_BK3E_8B , 0x00, 0x01); // reg_sptp_f0_end
1026 MDrv_WriteByteMask( REG_FRC_BK3E_8C , 0xee, 0xff); // reg_sptp_f1_st
1027 MDrv_WriteByteMask( REG_FRC_BK3E_8D , 0x00, 0x01); // reg_sptp_f1_st
1028 MDrv_WriteByteMask( REG_FRC_BK3E_8E , 0xdf, 0xff); // reg_sptp_f1_end
1029 MDrv_WriteByteMask( REG_FRC_BK3E_8F , 0x01, 0x01); // reg_sptp_f1_end
1030 MDrv_WriteByteMask( REG_FRC_BK3E_86 , 0x02, 0xff); // reg_sptp_gb_en
1031 // CSC
1032 }
1033
1034
1035
1036 /********************************************/
1037 // 2D_4K2K_YUV
MFC_3D_2D_4K2K_2D_4K2K_YUV(void)1038 void MFC_3D_2D_4K2K_2D_4K2K_YUV(void)
1039 {
1040 // FSC_TOP
1041 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x01); // reg_hvsp_bypass
1042 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x02, 0x02); // reg_hvsp_buffer_md
1043 MDrv_WriteByteMask( REG_SC_BK4F_C0, 0x00, 0x04); // reg_fsc_lb_bypass
1044 // VSU
1045 MDrv_WriteByteMask( REG_SC_BK4F_12, 0x00, 0xff); // vsp_scl_fac0
1046 MDrv_WriteByteMask( REG_SC_BK4F_13, 0x00, 0xff); // vsp_scl_fac1
1047 MDrv_WriteByteMask( REG_SC_BK4F_14, 0x10, 0xff); // vsp_scl_fac2
1048 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x01, 0x01); // vsp_scl_en
1049 MDrv_WriteByteMask( REG_SC_BK4F_15, 0x00, 0x02); // vsp_shift_mode_en
1050 MDrv_WriteByteMask( REG_SC_BK4F_06, 0x00, 0xff); // vsp_ini_scl_fac0
1051 MDrv_WriteByteMask( REG_SC_BK4F_07, 0x00, 0xff); // vsp_ini_scl_fac1
1052 MDrv_WriteByteMask( REG_SC_BK4F_08, 0x00, 0xff); // vsp_ini_scl_fac2
1053 MDrv_WriteByteMask( REG_SC_BK4F_52, 0x70, 0xff); // vsp_vsize_in0
1054 MDrv_WriteByteMask( REG_SC_BK4F_53, 0x08, 0xff); // vsp_vsize_in1
1055 MDrv_WriteByteMask( REG_SC_BK4F_56, 0x70, 0xff); // vsp_vsize_out0
1056 MDrv_WriteByteMask( REG_SC_BK4F_57, 0x08, 0xff); // vsp_vsize_out1
1057 // HSU
1058 MDrv_WriteByteMask( REG_SC_BK4F_0E, 0x00, 0xff); // hsp_scl_fac0
1059 MDrv_WriteByteMask( REG_SC_BK4F_0F, 0x00, 0xff); // hsp_scl_fac1
1060 MDrv_WriteByteMask( REG_SC_BK4F_10, 0x10, 0xff); // hsp_scl_fac2
1061 MDrv_WriteByteMask( REG_SC_BK4F_11, 0x01, 0x01); // hsp_scl_en
1062 MDrv_WriteByteMask( REG_SC_BK4F_11, 0x00, 0x02); // hsp_shift_mode_en
1063 MDrv_WriteByteMask( REG_SC_BK4F_02, 0x00, 0xff); // hsp_ini_scl_fac0
1064 MDrv_WriteByteMask( REG_SC_BK4F_03, 0x00, 0xff); // hsp_ini_scl_fac1
1065 MDrv_WriteByteMask( REG_SC_BK4F_04, 0x00, 0xff); // hsp_ini_scl_fac2
1066 MDrv_WriteByteMask( REG_SC_BK4F_50, 0x00, 0xff); // hsp_hsize_in0
1067 MDrv_WriteByteMask( REG_SC_BK4F_51, 0x0f, 0xff); // hsp_hsize_in1
1068 MDrv_WriteByteMask( REG_SC_BK4F_54, 0x00, 0xff); // hsp_hsize_out0
1069 MDrv_WriteByteMask( REG_SC_BK4F_55, 0x0f, 0xff); // hsp_hsize_out1
1070 // SPTF_D2LR
1071 MDrv_WriteByteMask( REG_FRC_BK33A_60 , 0x00, 0xff); // gb_cut_st_l
1072 MDrv_WriteByteMask( REG_FRC_BK33A_61 , 0x00, 0xff); // gb_cut_st_l
1073 MDrv_WriteByteMask( REG_FRC_BK33A_62 , 0x80, 0xff); // gb_cut_end_l
1074 MDrv_WriteByteMask( REG_FRC_BK33A_63 , 0x07, 0xff); // gb_cut_end_l
1075 MDrv_WriteByteMask( REG_FRC_BK33A_64 , 0x80, 0xff); // gb_cut_st_r
1076 MDrv_WriteByteMask( REG_FRC_BK33A_65 , 0x00, 0xff); // gb_cut_st_r
1077 MDrv_WriteByteMask( REG_FRC_BK33A_66 , 0xff, 0xff); // gb_cut_end_r
1078 MDrv_WriteByteMask( REG_FRC_BK33A_67 , 0x1f, 0xff); // gb_cut_end_r
1079 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x01); // d2lr_bypass
1080 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x02, 0x02); // d2lr_eo
1081 MDrv_WriteByteMask( REG_FRC_BK33A_50 , 0x00, 0x04); // d2lr_lr
1082 MDrv_WriteByteMask( REG_FRC_BK33A_52 , 0x80, 0xff); // d2lr_output_h
1083 MDrv_WriteByteMask( REG_FRC_BK33A_53 , 0x08, 0xff); // d2lr_output_h
1084 MDrv_WriteByteMask( REG_FRC_BK33A_40 , 0x00, 0xff); // d2lr_w0_st
1085 MDrv_WriteByteMask( REG_FRC_BK33A_41 , 0x00, 0xff); // d2lr_w0_st
1086 MDrv_WriteByteMask( REG_FRC_BK33A_42 , 0xff, 0xff); // d2lr_w0_end
1087 MDrv_WriteByteMask( REG_FRC_BK33A_43 , 0x0e, 0xff); // d2lr_w0_end
1088 MDrv_WriteByteMask( REG_FRC_BK33A_44 , 0x00, 0xff); // d2lr_w1_st
1089 MDrv_WriteByteMask( REG_FRC_BK33A_45 , 0x00, 0xff); // d2lr_w1_st
1090 MDrv_WriteByteMask( REG_FRC_BK33A_46 , 0xff, 0xff); // d2lr_w1_end
1091 MDrv_WriteByteMask( REG_FRC_BK33A_47 , 0x0e, 0xff); // d2lr_w1_end
1092 MDrv_WriteByteMask( REG_FRC_BK33A_48 , 0x00, 0xff); // d2lr_r0_st
1093 MDrv_WriteByteMask( REG_FRC_BK33A_49 , 0x00, 0xff); // d2lr_r0_st
1094 MDrv_WriteByteMask( REG_FRC_BK33A_4A , 0x7f, 0xff); // d2lr_r0_end
1095 MDrv_WriteByteMask( REG_FRC_BK33A_4B , 0x08, 0xff); // d2lr_r0_end
1096 MDrv_WriteByteMask( REG_FRC_BK33A_4C , 0x80, 0xff); // d2lr_r1_st
1097 MDrv_WriteByteMask( REG_FRC_BK33A_4D , 0x06, 0xff); // d2lr_r1_st
1098 MDrv_WriteByteMask( REG_FRC_BK33A_4E , 0xff, 0xff); // d2lr_r1_end
1099 MDrv_WriteByteMask( REG_FRC_BK33A_4F , 0x0e, 0xff); // d2lr_r1_end
1100 // FSC_3D
1101 MDrv_WriteByteMask( REG_SC_BK4F_21, 0x00, 0x40); // reg_3d_top_bot_en
1102 MDrv_WriteByteMask( REG_SC_BK4F_21, 0x00, 0x80); // reg_3d_sbs_en
1103 // IPM_OPM
1104 MDrv_WriteByteMask( REG_FRC_BK134_1C , 0x80, 0xff); // ipm_offset_f2
1105 MDrv_WriteByteMask( REG_FRC_BK134_1D , 0x07, 0xff); // ipm_offset_f2
1106 MDrv_WriteByteMask( REG_FRC_BK134_1E , 0x80, 0xff); // ipm_fetch_f2
1107 MDrv_WriteByteMask( REG_FRC_BK134_1F , 0x07, 0xff); // ipm_fetch_f2
1108 MDrv_WriteByteMask( REG_FRC_BK134_04 , 0x00, 0xff); // ipm_mem_config_f2
1109 MDrv_WriteByteMask( REG_FRC_BK134_05 , 0x01, 0xff); // ipm_mem_config_f2
1110 MDrv_WriteByteMask( REG_FRC_BK13A_04 , 0x03, 0xff); // ipm_mem_config_f2
1111 MDrv_WriteByteMask( REG_FRC_BK13A_05 , 0x31, 0xff); // ipm_mem_config_f2
1112 MDrv_WriteByteMask( REG_FRC_BK13A_84 , 0x03, 0xff); // ipm_mem_config_f2
1113 MDrv_WriteByteMask( REG_FRC_BK13A_85 , 0x31, 0xff); // ipm_mem_config_f2
1114 MDrv_WriteByteMask( REG_FRC_BK134_9C , 0x80, 0xff); // ipm_fetch_f1
1115 MDrv_WriteByteMask( REG_FRC_BK134_9D , 0x07, 0xff); // ipm_fetch_f1
1116 MDrv_WriteByteMask( REG_FRC_BK134_9E , 0x80, 0xff); // ipm_offset_f1
1117 MDrv_WriteByteMask( REG_FRC_BK134_9F , 0x07, 0xff); // ipm_offset_f1
1118 MDrv_WriteByteMask( REG_FRC_BK134_84 , 0x00, 0xff); // ipm_mem_config_f1
1119 MDrv_WriteByteMask( REG_FRC_BK134_85 , 0x01, 0xff); // ipm_mem_config_f1
1120 MDrv_WriteByteMask( REG_FRC_BK134_2C , 0x80, 0xff); // opm_offset_f2
1121 MDrv_WriteByteMask( REG_FRC_BK134_2D , 0x07, 0xff); // opm_offset_f2
1122 MDrv_WriteByteMask( REG_FRC_BK134_2E , 0x80, 0xff); // opm_fetch_f2
1123 MDrv_WriteByteMask( REG_FRC_BK134_2F , 0x07, 0xff); // opm_fetch_f2
1124 MDrv_WriteByteMask( REG_FRC_BK134_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
1125 MDrv_WriteByteMask( REG_FRC_BK134_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
1126 MDrv_WriteByteMask( REG_FRC_BK136_2C , 0x80, 0xff); // opm_offset_f1
1127 MDrv_WriteByteMask( REG_FRC_BK136_2D , 0x07, 0xff); // opm_offset_f1
1128 MDrv_WriteByteMask( REG_FRC_BK136_2E , 0x80, 0xff); // opm_fetch_f1
1129 MDrv_WriteByteMask( REG_FRC_BK136_2F , 0x07, 0xff); // opm_fetch_f1
1130 MDrv_WriteByteMask( REG_FRC_BK136_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
1131 MDrv_WriteByteMask( REG_FRC_BK136_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
1132 MDrv_WriteByteMask( REG_FRC_BK13A_2C , 0x80, 0xff); // opm_offset_f2
1133 MDrv_WriteByteMask( REG_FRC_BK13A_2D , 0x07, 0xff); // opm_offset_f2
1134 MDrv_WriteByteMask( REG_FRC_BK13A_2E , 0x80, 0xff); // opm_fetch_f2
1135 MDrv_WriteByteMask( REG_FRC_BK13A_2F , 0x07, 0xff); // opm_fetch_f2
1136 MDrv_WriteByteMask( REG_FRC_BK13A_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
1137 MDrv_WriteByteMask( REG_FRC_BK13A_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
1138 MDrv_WriteByteMask( REG_FRC_BK13B_2C , 0x80, 0xff); // opm_offset_f1
1139 MDrv_WriteByteMask( REG_FRC_BK13B_2D , 0x07, 0xff); // opm_offset_f1
1140 MDrv_WriteByteMask( REG_FRC_BK13B_2E , 0x80, 0xff); // opm_fetch_f1
1141 MDrv_WriteByteMask( REG_FRC_BK13B_2F , 0x07, 0xff); // opm_fetch_f1
1142 MDrv_WriteByteMask( REG_FRC_BK13B_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
1143 MDrv_WriteByteMask( REG_FRC_BK13B_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
1144 MDrv_WriteByteMask( REG_FRC_BK13C_2C , 0x80, 0xff); // opm_offset_f2
1145 MDrv_WriteByteMask( REG_FRC_BK13C_2D , 0x07, 0xff); // opm_offset_f2
1146 MDrv_WriteByteMask( REG_FRC_BK13C_2E , 0x80, 0xff); // opm_fetch_f2
1147 MDrv_WriteByteMask( REG_FRC_BK13C_2F , 0x07, 0xff); // opm_fetch_f2
1148 MDrv_WriteByteMask( REG_FRC_BK13C_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
1149 MDrv_WriteByteMask( REG_FRC_BK13C_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
1150 MDrv_WriteByteMask( REG_FRC_BK13D_2C , 0x80, 0xff); // opm_offset_f1
1151 MDrv_WriteByteMask( REG_FRC_BK13D_2D , 0x07, 0xff); // opm_offset_f1
1152 MDrv_WriteByteMask( REG_FRC_BK13D_2E , 0x80, 0xff); // opm_fetch_f1
1153 MDrv_WriteByteMask( REG_FRC_BK13D_2F , 0x07, 0xff); // opm_fetch_f1
1154 MDrv_WriteByteMask( REG_FRC_BK13D_30 , 0x70, 0xff); // reg_ipm_vcnt_limit_num_f2
1155 MDrv_WriteByteMask( REG_FRC_BK13D_31 , 0x08, 0xff); // reg_ipm_vcnt_limit_num_f2
1156 // IPM_OPM_vlen
1157 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x80, 0x80); // reg_opm_vlen_sel
1158 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x80, 0x80); // reg_opm_vlen_sel
1159 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x80, 0x80); // reg_opm_vlen_sel
1160 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x80, 0x80); // reg_opm_vlen_sel
1161 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x80, 0x80); // reg_opm_vlen_sel
1162 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x80, 0x80); // reg_opm_vlen_sel
1163 MDrv_WriteByteMask( REG_FRC_BK134_62 , 0x70, 0xff); // reg_opm_vlen
1164 MDrv_WriteByteMask( REG_FRC_BK134_63 , 0x08, 0x1f); // reg_opm_vlen
1165 MDrv_WriteByteMask( REG_FRC_BK136_62 , 0x70, 0xff); // reg_opm_vlen
1166 MDrv_WriteByteMask( REG_FRC_BK136_63 , 0x08, 0x1f); // reg_opm_vlen
1167 MDrv_WriteByteMask( REG_FRC_BK13A_62 , 0x70, 0xff); // reg_opm_vlen
1168 MDrv_WriteByteMask( REG_FRC_BK13A_63 , 0x08, 0x1f); // reg_opm_vlen
1169 MDrv_WriteByteMask( REG_FRC_BK13B_62 , 0x70, 0xff); // reg_opm_vlen
1170 MDrv_WriteByteMask( REG_FRC_BK13B_63 , 0x08, 0x1f); // reg_opm_vlen
1171 MDrv_WriteByteMask( REG_FRC_BK13C_62 , 0x70, 0xff); // reg_opm_vlen
1172 MDrv_WriteByteMask( REG_FRC_BK13C_63 , 0x08, 0x1f); // reg_opm_vlen
1173 MDrv_WriteByteMask( REG_FRC_BK13D_62 , 0x70, 0xff); // reg_opm_vlen
1174 MDrv_WriteByteMask( REG_FRC_BK13D_63 , 0x08, 0x1f); // reg_opm_vlen
1175 MDrv_WriteByteMask( REG_FRC_BK134_CC , 0x70, 0xff); // reg_opm_vlen_new
1176 MDrv_WriteByteMask( REG_FRC_BK134_CD , 0x08, 0x1f); // reg_opm_vlen_new
1177 MDrv_WriteByteMask( REG_FRC_BK136_CC , 0x70, 0xff); // reg_opm_vlen_new
1178 MDrv_WriteByteMask( REG_FRC_BK136_CD , 0x08, 0x1f); // reg_opm_vlen_new
1179 MDrv_WriteByteMask( REG_FRC_BK13A_CC , 0x70, 0xff); // reg_opm_vlen_new
1180 MDrv_WriteByteMask( REG_FRC_BK13A_CD , 0x08, 0x1f); // reg_opm_vlen_new
1181 MDrv_WriteByteMask( REG_FRC_BK13B_CC , 0x70, 0xff); // reg_opm_vlen_new
1182 MDrv_WriteByteMask( REG_FRC_BK13B_CD , 0x08, 0x1f); // reg_opm_vlen_new
1183 MDrv_WriteByteMask( REG_FRC_BK13C_CC , 0x70, 0xff); // reg_opm_vlen_new
1184 MDrv_WriteByteMask( REG_FRC_BK13C_CD , 0x08, 0x1f); // reg_opm_vlen_new
1185 MDrv_WriteByteMask( REG_FRC_BK13D_CC , 0x70, 0xff); // reg_opm_vlen_new
1186 MDrv_WriteByteMask( REG_FRC_BK13D_CD , 0x08, 0x1f); // reg_opm_vlen_new
1187 MDrv_WriteByteMask( REG_FRC_BK134_BA , 0x38, 0xff); // reg_opm_meds_vlen
1188 MDrv_WriteByteMask( REG_FRC_BK134_BB , 0x04, 0x1f); // reg_opm_meds_vlen
1189 MDrv_WriteByteMask( REG_FRC_BK136_BA , 0x38, 0xff); // reg_opm_meds_vlen
1190 MDrv_WriteByteMask( REG_FRC_BK136_BB , 0x04, 0x1f); // reg_opm_meds_vlen
1191 MDrv_WriteByteMask( REG_FRC_BK13A_BA , 0x38, 0xff); // reg_opm_meds_vlen
1192 MDrv_WriteByteMask( REG_FRC_BK13A_BB , 0x04, 0x1f); // reg_opm_meds_vlen
1193 MDrv_WriteByteMask( REG_FRC_BK13B_BA , 0x38, 0xff); // reg_opm_meds_vlen
1194 MDrv_WriteByteMask( REG_FRC_BK13B_BB , 0x04, 0x1f); // reg_opm_meds_vlen
1195 MDrv_WriteByteMask( REG_FRC_BK13C_BA , 0x38, 0xff); // reg_opm_meds_vlen
1196 MDrv_WriteByteMask( REG_FRC_BK13C_BB , 0x04, 0x1f); // reg_opm_meds_vlen
1197 MDrv_WriteByteMask( REG_FRC_BK13D_BA , 0x38, 0xff); // reg_opm_meds_vlen
1198 MDrv_WriteByteMask( REG_FRC_BK13D_BB , 0x04, 0x1f); // reg_opm_meds_vlen
1199 MDrv_WriteByteMask( REG_FRC_BK134_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
1200 MDrv_WriteByteMask( REG_FRC_BK134_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
1201 MDrv_WriteByteMask( REG_FRC_BK136_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
1202 MDrv_WriteByteMask( REG_FRC_BK136_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
1203 MDrv_WriteByteMask( REG_FRC_BK13A_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
1204 MDrv_WriteByteMask( REG_FRC_BK13A_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
1205 MDrv_WriteByteMask( REG_FRC_BK13B_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
1206 MDrv_WriteByteMask( REG_FRC_BK13B_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
1207 MDrv_WriteByteMask( REG_FRC_BK13C_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
1208 MDrv_WriteByteMask( REG_FRC_BK13C_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
1209 MDrv_WriteByteMask( REG_FRC_BK13D_C8 , 0x38, 0xff); // reg_opm_meds_vlen_new
1210 MDrv_WriteByteMask( REG_FRC_BK13D_C9 , 0x04, 0x1f); // reg_opm_meds_vlen_new
1211 // IPM_OPM_DSmode
1212 MDrv_WriteByteMask( REG_FRC_BK13A_1C , 0xc0, 0xff); // reg_ipm_offset_f2
1213 MDrv_WriteByteMask( REG_FRC_BK13A_1D , 0x03, 0xff); // reg_ipm_offset_f2
1214 MDrv_WriteByteMask( REG_FRC_BK13A_1E , 0xc0, 0xff); // reg_ipm_fetch_num_f2
1215 MDrv_WriteByteMask( REG_FRC_BK13A_1F , 0x03, 0xff); // reg_ipm_fetch_num_f2
1216 MDrv_WriteByteMask( REG_FRC_BK13A_9C , 0xc0, 0xff); // reg_ipm_offset_f1
1217 MDrv_WriteByteMask( REG_FRC_BK13A_9D , 0x03, 0xff); // reg_ipm_offset_f1
1218 MDrv_WriteByteMask( REG_FRC_BK13A_9E , 0xc0, 0xff); // reg_ipm_fetch_num_f1
1219 MDrv_WriteByteMask( REG_FRC_BK13A_9F , 0x03, 0xff); // reg_ipm_fetch_num_f1
1220 MDrv_WriteByteMask( REG_FRC_BK134_BC , 0xc0, 0xff); // reg_opm_meds_offset
1221 MDrv_WriteByteMask( REG_FRC_BK134_BD , 0x03, 0xff); // reg_opm_meds_offset
1222 MDrv_WriteByteMask( REG_FRC_BK134_BE , 0xc0, 0xff); // reg_opm_meds_fetch_num
1223 MDrv_WriteByteMask( REG_FRC_BK134_BF , 0x03, 0xff); // reg_opm_meds_fetch_num
1224 // IPM_3D
1225 MDrv_WriteByteMask( REG_FRC_BK135_1C , 0x00, 0xff); // reg_v_toggle_value
1226 MDrv_WriteByteMask( REG_FRC_BK135_1D , 0x00, 0x0f); // reg_v_toggle_value
1227 MDrv_WriteByteMask( REG_FRC_BK135_04 , 0x00, 0x30); // reg_v_toggle_en
1228 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x80, 0x80); // reg_ipm_ud_en
1229 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x80, 0x80); // reg_ipm_meds_ud_en
1230 MDrv_WriteByteMask( REG_FRC_BK134_26 , 0x38, 0xff); // reg_ipm_turn_back_line
1231 MDrv_WriteByteMask( REG_FRC_BK134_27 , 0x04, 0x1f); // reg_ipm_turn_back_line
1232 MDrv_WriteByteMask( REG_FRC_BK13A_26 , 0x1c, 0xff); // reg_ipm_turn_back_line_meds
1233 MDrv_WriteByteMask( REG_FRC_BK13A_27 , 0x02, 0x1f); // reg_ipm_turn_back_line_meds
1234 // OPM_3D
1235 MDrv_WriteByteMask( REG_FRC_BK134_60 , 0x00, 0x01); // reg_ipm_3d_en_f2
1236 MDrv_WriteByteMask( REG_FRC_BK134_E0 , 0x00, 0x01); // reg_ipm_3d_en_f1
1237 MDrv_WriteByteMask( REG_FRC_BK13A_60 , 0x00, 0x01); // reg_ipm_3d_en_mef3f4_f2
1238 MDrv_WriteByteMask( REG_FRC_BK13A_E0 , 0x00, 0x01); // reg_ipm_3d_en_mef3f4_f1
1239 MDrv_WriteByteMask( REG_FRC_BK134_66 , 0x00, 0x80); // reg_opm_3d_en_f2
1240 MDrv_WriteByteMask( REG_FRC_BK136_66 , 0x00, 0x80); // reg_opm_3d_en_f1
1241 MDrv_WriteByteMask( REG_FRC_BK13A_66 , 0x00, 0x80); // reg_opm_3d_en_mef3f4_f2
1242 MDrv_WriteByteMask( REG_FRC_BK13B_66 , 0x00, 0x80); // reg_opm_3d_en_mef3f4_f1
1243 MDrv_WriteByteMask( REG_FRC_BK13C_66 , 0x00, 0x80); // reg_opm_3d_en_mif3_f2
1244 MDrv_WriteByteMask( REG_FRC_BK13D_66 , 0x00, 0x80); // reg_opm_3d_en_mif3_f1
1245 MDrv_WriteByteMask( REG_FRC_BK134_67 , 0x00, 0x04); // reg_opm_passive_en_f2
1246 MDrv_WriteByteMask( REG_FRC_BK136_67 , 0x00, 0x04); // reg_opm_passive_en_f1
1247 MDrv_WriteByteMask( REG_FRC_BK13A_67 , 0x00, 0x04); // reg_opm_passive_en_f2
1248 MDrv_WriteByteMask( REG_FRC_BK13B_67 , 0x00, 0x04); // reg_opm_passive_en_f1
1249 MDrv_WriteByteMask( REG_FRC_BK13C_67 , 0x00, 0x04); // reg_opm_passive_en_f2
1250 MDrv_WriteByteMask( REG_FRC_BK13D_67 , 0x00, 0x04); // reg_opm_passive_en_f1
1251 MDrv_WriteByteMask( REG_FRC_BK134_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
1252 MDrv_WriteByteMask( REG_FRC_BK136_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
1253 MDrv_WriteByteMask( REG_FRC_BK13A_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
1254 MDrv_WriteByteMask( REG_FRC_BK13B_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
1255 MDrv_WriteByteMask( REG_FRC_BK13C_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f2
1256 MDrv_WriteByteMask( REG_FRC_BK13D_2B , 0x00, 0x20); // reg_opm_line_repeat_en_f1
1257 // OPMRM
1258 MDrv_WriteByteMask( REG_FRC_BK134_E8 , 0x00, 0x01); // reg_opm_ml_en
1259 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x00, 0x08); // reg_rbk_free
1260 MDrv_WriteByteMask( REG_FRC_BK134_E9 , 0x00, 0x70); // reg_rbk_free_diff
1261 MDrv_WriteByteMask( REG_FRC_BK134_32 , 0x00, 0x80); // reg_opm_2f_md
1262 MDrv_WriteByteMask( REG_FRC_BK136_32 , 0x00, 0x80); // reg_opm_2f_md
1263 MDrv_WriteByteMask( REG_FRC_BK134_33 , 0x01, 0x01); // reg_opm_3f_md
1264 MDrv_WriteByteMask( REG_FRC_BK136_33 , 0x01, 0x01); // reg_opm_3f_md
1265 MDrv_WriteByteMask( REG_FRC_BK134_CE , 0x05, 0x0f); // reg_opm_memc_md
1266 MDrv_WriteByteMask( REG_FRC_BK134_CF , 0x04, 0x07); // reg_opm_memc_md
1267 // HSD_MEDS
1268 MDrv_WriteByteMask( REG_FRC_BK320_C2 , 0x33, 0xff); // reg_frc_ipm_hvsd_la_mode
1269 MDrv_WriteByteMask( REG_FRC_BK320_C3 , 0x8e, 0xff); // reg_frc_ipm_hvsd_drop_mode
1270 // MEMC_FSC
1271 MDrv_WriteByteMask( REG_FRC_BK320_A4 , 0x00, 0xff); // reg_frc_xxxx
1272 MDrv_WriteByteMask( REG_FRC_BK320_A5 , 0x0F, 0xff); // reg_frc_xxxx
1273 MDrv_WriteByteMask( REG_FRC_BK320_A6 , 0x80, 0xff); // reg_frc_xxxx
1274 MDrv_WriteByteMask( REG_FRC_BK320_A7 , 0x07, 0xff); // reg_frc_xxxx
1275 // MLB
1276 MDrv_WriteByteMask( REG_FRC_BK226_F4 , 0x01, 0xff); // reg_sadmvRangeL
1277 MDrv_WriteByteMask( REG_FRC_BK226_F5 , 0x00, 0x03); // reg_sadmvRangeL
1278 MDrv_WriteByteMask( REG_FRC_BK226_F8 , 0x01, 0xff); // reg_sadmvRangeU
1279 MDrv_WriteByteMask( REG_FRC_BK226_F9 , 0x00, 0x01); // reg_sadmvRangeU
1280 MDrv_WriteByteMask( REG_FRC_BK226_F6 , 0xff, 0xff); // reg_sadmvRangeR
1281 MDrv_WriteByteMask( REG_FRC_BK226_F7 , 0x03, 0x03); // reg_sadmvRangeR
1282 MDrv_WriteByteMask( REG_FRC_BK226_F2 , 0xff, 0xff); // reg_sadmvRangeD
1283 MDrv_WriteByteMask( REG_FRC_BK226_F3 , 0x00, 0x01); // reg_sadmvRangeD
1284 MDrv_WriteByteMask( REG_FRC_BK232_02 , 0x00, 0x02); // reg_pass3d_la
1285 MDrv_WriteByteMask( REG_FRC_BK232_11 , 0x00, 0xc0); // reg_mask_en
1286 // MV_PREPROC
1287 MDrv_WriteByteMask( REG_FRC_BK22C_92 , 0x00, 0x03); // reg_mv_preprocess
1288 // MFC_pipectrl
1289 MDrv_WriteByteMask( REG_FRC_BK233_3E , 0x00, 0xff); // reg_ppctr_h_pixl_num_me
1290 MDrv_WriteByteMask( REG_FRC_BK233_3F , 0x0f, 0x1f); // reg_ppctr_h_pixl_num_me
1291 MDrv_WriteByteMask( REG_FRC_BK233_40 , 0x38, 0xff); // reg_ppctr_v_line_num_me
1292 MDrv_WriteByteMask( REG_FRC_BK233_41 , 0x04, 0x1f); // reg_ppctr_v_line_num_me
1293 MDrv_WriteByteMask( REG_FRC_BK233_46 , 0x00, 0xff); // reg_me_h_pixel_num_mi
1294 MDrv_WriteByteMask( REG_FRC_BK233_47 , 0x0f, 0x1f); // reg_me_h_pixel_num_mi
1295 MDrv_WriteByteMask( REG_FRC_BK233_48 , 0x70, 0xff); // reg_me_v_pixel_num_mi
1296 MDrv_WriteByteMask( REG_FRC_BK233_49 , 0x08, 0x1f); // reg_me_v_pixel_num_mi
1297 MDrv_WriteByteMask( REG_FRC_BK233_F8 , 0x00, 0xff); // reg_h_pixel_num_mlb
1298 MDrv_WriteByteMask( REG_FRC_BK233_F9 , 0x0f, 0x1f); // reg_h_pixel_num_mlb
1299 MDrv_WriteByteMask( REG_FRC_BK233_FA , 0x70, 0xff); // reg_v_pixel_num_mlb
1300 MDrv_WriteByteMask( REG_FRC_BK233_FB , 0x08, 0x1f); // reg_v_pixel_num_mlb
1301 MDrv_WriteByteMask( REG_FRC_BK233_3A , 0x00, 0xff); // reg_time_gen_sw_h_width
1302 MDrv_WriteByteMask( REG_FRC_BK233_3B , 0x0f, 0x1f); // reg_time_gen_sw_h_width
1303 MDrv_WriteByteMask( REG_FRC_BK233_3C , 0x1b, 0xff); // reg_time_gen_sw_v_width
1304 MDrv_WriteByteMask( REG_FRC_BK233_3D , 0x02, 0x1f); // reg_time_gen_sw_v_width
1305 MDrv_WriteByteMask( REG_FRC_BK233_42 , 0x80, 0xff); // reg_mlb_disp_pixel_latch
1306 MDrv_WriteByteMask( REG_FRC_BK233_43 , 0x07, 0x1f); // reg_mlb_disp_pixel_latch
1307 MDrv_WriteByteMask( REG_FRC_BK233_A8 , 0x00, 0xff); // reg_gmv_vertical_active_window_height
1308 MDrv_WriteByteMask( REG_FRC_BK233_A9 , 0x01, 0x01); // reg_gmv_vertical_active_window_height
1309 // MFC_VDUP
1310 MDrv_WriteByteMask( REG_FRC_BK20A_04 , 0xC0, 0xFF); // reg_VDUP_width
1311 MDrv_WriteByteMask( REG_FRC_BK20A_05 , 0x03, 0xFF); // reg_VDUP_width
1312 MDrv_WriteByteMask( REG_FRC_BK20A_06 , 0x70, 0xFF); // reg_VDUP_height
1313 MDrv_WriteByteMask( REG_FRC_BK20A_07 , 0x08, 0xFF); // reg_VDUP_height
1314 // MFC
1315 MDrv_WriteByteMask( REG_FRC_BK226_61 , 0x73, 0xff); // reg_MFC_enable
1316 MDrv_WriteByteMask( REG_FRC_BK226_70 , 0x20, 0x20); //
1317 MDrv_WriteByteMask( REG_FRC_BK226_73 , 0x0f, 0x1f); // reg_h_pix_num_3D
1318 MDrv_WriteByteMask( REG_FRC_BK226_72 , 0x00, 0xff); // reg_h_pix_num_3D
1319 MDrv_WriteByteMask( REG_FRC_BK226_75 , 0x04, 0x1f); // reg_v_lin_num_3D
1320 MDrv_WriteByteMask( REG_FRC_BK226_74 , 0x38, 0xff); // reg_v_lin_num_3D
1321 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x08, 0x08); //
1322 MDrv_WriteByteMask( REG_FRC_BK229_05 , 0x0f, 0xFF); // reg_h_pix_num_ME
1323 MDrv_WriteByteMask( REG_FRC_BK229_04 , 0x00, 0xFF); // reg_h_pix_num_ME
1324 MDrv_WriteByteMask( REG_FRC_BK229_07 , 0x08, 0x0F); // reg_v_lin_num_ME
1325 MDrv_WriteByteMask( REG_FRC_BK229_06 , 0x70, 0xFF); // reg_v_lin_num_ME
1326 MDrv_WriteByteMask( REG_FRC_BK229_91 , 0x0f, 0xFF); // reg_h_pix_num_MI
1327 MDrv_WriteByteMask( REG_FRC_BK229_90 , 0x00, 0xFF); // reg_h_pix_num_MI
1328 MDrv_WriteByteMask( REG_FRC_BK229_93 , 0x08, 0xFF); // reg_v_lin_num_MI
1329 MDrv_WriteByteMask( REG_FRC_BK229_92 , 0x70, 0xFF); // reg_v_lin_num_MI
1330 MDrv_WriteByteMask( REG_FRC_BK226_67 , 0x01, 0x01); // reg_422to444_en
1331 MDrv_WriteByteMask( REG_FRC_BK232_D0 , 0x00, 0x02); // reg_rgb_bypass
1332 MDrv_WriteByteMask( REG_FRC_BK226_60 , 0x80, 0x80); // reg_c_drop
1333 MDrv_WriteByteMask( REG_FRC_BK229_9C , 0x80, 0x80); // reg_422_avgmode
1334 MDrv_WriteByteMask( REG_FRC_BK22C_80 , 0x01, 0x01); // reg_pipectrl_bypass
1335 // MFC_Halo
1336 MDrv_WriteByteMask( REG_FRC_BK22C_93 , 0x80, 0x80); // reg_halo_buf_frame_end_en
1337 MDrv_WriteByteMask( REG_FRC_BK22C_A7 , 0x00, 0x02); // reg_halo_buf23_force_ready
1338 // MFC_GMV
1339 MDrv_WriteByteMask( REG_FRC_BK232_2A , 0x01, 0x01); // reg_gmv_in_ud_mode
1340 // SNR
1341 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x08); // reg_snr_bypass_en
1342 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x04); // reg_snr_la_en
1343 MDrv_WriteByteMask( REG_FRC_BK2E_E2 , 0x00, 0xff); // reg_snr_pix_num_LSB
1344 MDrv_WriteByteMask( REG_FRC_BK2E_E3 , 0x0f, 0x1f); // reg_snr_pix_num_MSB
1345 MDrv_WriteByteMask( REG_FRC_BK2E_E8 , 0x70, 0xff); // reg_snr_line_num_LSB
1346 MDrv_WriteByteMask( REG_FRC_BK2E_E9 , 0x08, 0x0f); // reg_snr_line_num_MSB
1347 // SNR_3D
1348 MDrv_WriteByteMask( REG_FRC_BK2E_65 , 0x00, 0x20); // reg_line_switch
1349 // SNR_VSU2X
1350 MDrv_WriteByteMask( REG_FRC_BK2E_E0 , 0x00, 0x10); // reg_lbi_vsu2x_en
1351 // FO_HSU
1352 MDrv_WriteByteMask( REG_FRC_BK115_30 , 0x00, 0xff); // hfac_smd0
1353 MDrv_WriteByteMask( REG_FRC_BK115_31 , 0x00, 0xff); // hfac_smd1
1354 MDrv_WriteByteMask( REG_FRC_BK115_32 , 0x00, 0x3f); // hfac_smd2
1355 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x01, 0x01); // hsp_bypass_en
1356 MDrv_WriteByteMask( REG_FRC_BK115_33 , 0x00, 0x02); // hsp_bypass2_en
1357 MDrv_WriteByteMask( REG_FRC_BK115_0C , 0x00, 0xff); // hsp_size_in0
1358 MDrv_WriteByteMask( REG_FRC_BK115_0D , 0x0f, 0x1f); // hsp_size_in1
1359 MDrv_WriteByteMask( REG_FRC_BK115_0E , 0x00, 0xff); // hsp_size_out0
1360 MDrv_WriteByteMask( REG_FRC_BK115_0F , 0x0f, 0x1f); // hsp_size_out1
1361 // SPTP
1362 MDrv_WriteByteMask( REG_FRC_BK3E_80 , 0xff, 0xff); // reg_sptp_mfc_dc_m1
1363 MDrv_WriteByteMask( REG_FRC_BK3E_81 , 0x0e, 0x0f); // reg_sptp_mfc_dc_m1
1364 MDrv_WriteByteMask( REG_FRC_BK3E_82 , 0x00, 0x80); // reg_sptp_fbl_en
1365 MDrv_WriteByteMask( REG_FRC_BK3E_84 , 0x01, 0x01); // reg_sptp_usr_en
1366 MDrv_WriteByteMask( REG_FRC_BK3E_88 , 0x00, 0xff); // reg_sptp_f0_st
1367 MDrv_WriteByteMask( REG_FRC_BK3E_89 , 0x00, 0x01); // reg_sptp_f0_st
1368 MDrv_WriteByteMask( REG_FRC_BK3E_8A , 0xf1, 0xff); // reg_sptp_f0_end
1369 MDrv_WriteByteMask( REG_FRC_BK3E_8B , 0x00, 0x01); // reg_sptp_f0_end
1370 MDrv_WriteByteMask( REG_FRC_BK3E_8C , 0xee, 0xff); // reg_sptp_f1_st
1371 MDrv_WriteByteMask( REG_FRC_BK3E_8D , 0x00, 0x01); // reg_sptp_f1_st
1372 MDrv_WriteByteMask( REG_FRC_BK3E_8E , 0xdf, 0xff); // reg_sptp_f1_end
1373 MDrv_WriteByteMask( REG_FRC_BK3E_8F , 0x01, 0x01); // reg_sptp_f1_end
1374 MDrv_WriteByteMask( REG_FRC_BK3E_86 , 0x02, 0xff); // reg_sptp_gb_en
1375 // CSC
1376 }
1377
1378
1379
1380 /********************************************/
1381