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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvPNL.c
98 /// @brief Panel Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101 #define _DRVPNL_C_
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #include "MsCommon.h"
108
109 #ifdef MSOS_TYPE_LINUX_KERNEL
110 #include <linux/string.h>
111 #include <linux/delay.h>
112 #include <asm/div64.h>
113 #else
114 #include "string.h"
115 #define do_div(x,y) ((x)/=(y))
116 #endif
117 // Internal Definition
118 #include "drvMMIO.h"
119
120 #ifndef _DRV_SYS_H_
121 #include "drvSYS.h"
122 #endif
123 #include "utopia.h"
124 #include "utopia_dapi.h"
125 #include "apiPNL.h"
126 #include "apiPNL_v2.h"
127 #include "drvPNL.h"
128 #include "halPNL.h"
129 #include "PNL_private.h"
130 #include "pnl_hwreg_utility2.h"
131 #include "halCHIP.h"
132
133 #ifdef MSOS_TYPE_LINUX_KERNEL
134 #if (KERNEL_DRIVER_PATCH ==1)
135 #if !defined(CONFIG_ARM64)
136 #include <linux/math64.h>
137 //__aeabi_uldivmod
__aeabi_uldivmod(unsigned long long n,unsigned long long d)138 unsigned long long __aeabi_uldivmod(unsigned long long n, unsigned long long d)
139 {
140 return div64_u64(n, d);
141 }
142
143 //__aeabi_ldivmod
__aeabi_ldivmod(long long n,long long d)144 long long __aeabi_ldivmod(long long n, long long d)
145 {
146 return div64_s64(n, d);
147 }
148 #endif
149 #endif
150 #endif
151 //-------------------------------------------------------------------------------------------------
152 // Driver Compiler Options
153 //-------------------------------------------------------------------------------------------------
154
155 //-------------------------------------------------------------------------------------------------
156 // Local Defines
157 //-------------------------------------------------------------------------------------------------
158 #define UNUSED(x) (x=x)
159 #define TCON_TAB_MAX_SIZE 2048
160
161 #define NONPM_BASE (0x100000)
162 #define OD_BYTE_PER_WORD 16
163 #define PANEL_VSTART_OFFSET 8 //8 // for PANEL_DE_VSTART add offset
164
165 //-------------------------------------------------------------------------------------------------
166 // Local Structurs
167 //-------------------------------------------------------------------------------------------------
168 static const MS_U8 _cPnlVer[] = PNL_LIB_VERSION;
169
170 // Internal Data
171
172 //-------------------------------------------------------------------------------------------------
173 // Global Variables
174 //-------------------------------------------------------------------------------------------------
175
176 //-------------------------------------------------------------------------------------------------
177 // Local Variables
178 //-------------------------------------------------------------------------------------------------
179 // Function in mdrv_xc_menuload.c
180 typedef enum
181 {
182 E_MLOAD_UNSUPPORTED = 0,
183 E_MLOAD_DISABLED = 1,
184 E_MLOAD_ENABLED = 2,
185 }MLOAD_TYPE;
186
187 typedef enum
188 {
189 E_MLG_UNSUPPORTED = 0,
190 E_MLG_DISABLED = 1,
191 E_MLG_ENABLED = 2,
192 }MLG_TYPE;
193
194 extern MS_BOOL MApi_XC_MLoad_WriteCmds_And_Fire(MS_U32 *pu32Addr, MS_U16 *pu16Data, MS_U16 *pu16Mask, MS_U16 u16CmdCnt);
195 extern MS_BOOL MApi_XC_MLoad_WriteCmd_And_Fire(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask);
196 extern MLOAD_TYPE MApi_XC_MLoad_GetStatus(void);
197 extern MLG_TYPE MApi_XC_MLG_GetStatus(void);
198 extern void MApi_XC_MLG_Fire(MS_U8 *pR, MS_U8 *pG, MS_U8 *pB, MS_U16 u16Count, MS_U16 *pMaxGammaValue);
199 extern MS_BOOL MDrv_XC_IsSupportPipPatchUsingSc1MainAsSc0Sub(void);
200
201 //-------------------------------------------------------------------------------------------------
202 // Debug Functions
203 //-------------------------------------------------------------------------------------------------
204
205 //-------------------------------------------------------------------------------------------------
206 // Local Functions
207 //-------------------------------------------------------------------------------------------------
_MDrv_PNL_Init_XC_T3D(void * pInstance,PNL_InitData * pstPanelInitData)208 static void _MDrv_PNL_Init_XC_T3D(void *pInstance, PNL_InitData *pstPanelInitData)
209 {
210 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
211 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
212
213 if (pstPanelInitData->u32PNL_MISC & E_DRVPNL_MISC_SKIP_T3D_CONTROL)
214 {
215 //printf("\033[0;31m [%s][%d] *** SKIP T3D control *** \033[0m\n", __FUNCTION__, __LINE__);
216 }
217 else
218 {
219 //Need move those setting to hal to avoid write Reg which is not T3D bank by any chip
220 #if 0
221 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_55_L, pstPanelInitData->u16Width, 0x1FFF);//pixel width
222 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_66_L, pstPanelInitData->u16Height, 0x1FFF);//reg_col_height
223 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_51_L, pstPanelInitData->u16Width, 0x1FFF);//reg_ln_width
224 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_52_L, pstPanelInitData->u16Height, 0x1FFF);//reg_col_height
225 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_61_L, pstPanelInitData->u16Width, 0x3FFF);//reg_ln_width
226 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_62_L, pstPanelInitData->u16Height, 0x1FFF);//reg_col_height
227
228 //per designer, should always enable t3d, since it will affect osd/video's pipeline
229 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_61_L, BIT(0), BIT(0));//Enable Depth Render, for osd pipe line adjustment
230 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK62_08_L, BIT(4), BIT(4));//mtv bypass mode
231 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK63_57_L,(BIT(0)|BIT(1)),(BIT(0)|BIT(1)));//T3D fix subde enable, fix for T3D/PIP conflict issue (bit 0) Bug Fix miu eco (bit 1)
232 #endif
233 MHal_PNL_Set_T3D_Setting(pInstance);
234 }
235 }
236
_MDrv_PNL_Init_XC_VOP(void * pInstance,PNL_InitData * pstPanelInitData)237 static void _MDrv_PNL_Init_XC_VOP(void *pInstance, PNL_InitData *pstPanelInitData)
238 {
239 //Note: H/V Total, H/V DE End, H/V Syncwidth all need minus 1 when set to register
240 MS_U16 u16DE_HEND = pstPanelInitData->u16HStart + pstPanelInitData->u16Width - 1;
241 MS_U16 u16DE_HStart = pstPanelInitData->u16HStart;
242 MS_U16 u16DE_VEND = pstPanelInitData->u16VStart + pstPanelInitData->u16Height - 1;
243 MS_U16 u16DE_VStart = pstPanelInitData->u16VStart;
244 MS_U16 u16VsyncStart = 0;
245 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
246 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
247
248 if (MDrv_XC_IsSupportPipPatchUsingSc1MainAsSc0Sub())
249 {
250 u16VsyncStart = pstPanelInitData->u16VTotal - pstPanelInitData->u16VSyncStart +PANEL_VSTART_OFFSET;// vsync start = Vtt - (VSyncWidth + BackPorch)
251 }
252 else
253 {
254 u16VsyncStart = pstPanelInitData->u16VTotal - pstPanelInitData->u16VSyncStart ;// vsync start = Vtt - (VSyncWidth + BackPorch)
255 }
256
257 // Htotal/Vtotal
258 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_0C_L, (pstPanelInitData->u16HTotal - 1), VOP_HTT_MASK); // output htotal
259 #if defined(CONFIG_MBOOT) || !defined(PATCH_HW_VTT_LIMITATION)
260 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_0D_L, (pstPanelInitData->u16VTotal - 1), VOP_VTT_MASK); // output vtotal
261 #endif
262 #if defined(PATCH_HW_VTT_LIMITATION)
263 if(R1BYTEMSK(REG_CHIP_REVISION,0xFF) < HW_VTT_LIMITATION_CHIPREV)
264 {
265 MOD_W2BYTEMSK(REG_MOD_BK00_65_L,pstPanelInitData->u16VTotal,0x1FFF);
266 MHal_PNL_SetVopVttByBK68(pPNLInstancePrivate->u32DeviceID, (pstPanelInitData->u16VTotal - 1)&VOP_VTT_MASK);
267 }
268 #endif
269 // DE H/V start/size
270 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_04_L, u16DE_HStart, VOP_DE_HSTART_MASK); // DE H start
271 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_05_L, u16DE_HEND , VOP_DE_HEND_MASK); // DE H end
272 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_06_L, u16DE_VStart, VOP_DE_VSTART_MASK); // DE V start
273 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_07_L, u16DE_VEND , VOP_DE_VEND_MASK); // DE V end
274 //If support sc1, init sub vop
275 if (MDrv_XC_IsSupportPipPatchUsingSc1MainAsSc0Sub())
276 {
277 //follow HW_DESIGN_4K2K_VER = 6 rule
278 SC_W2BYTEMSK(1, REG_SC_BK10_0C_L, (pstPanelInitData->u16HTotal/2 - 1), VOP_HTT_MASK);
279 SC_W2BYTEMSK(1, REG_SC_BK10_0D_L, VOP_VTT_MASK, VOP_VTT_MASK); // output vtotal
280
281 // DE H/V start/size
282 SC_W2BYTEMSK(1, REG_SC_BK10_04_L, u16DE_HStart/2, VOP_DE_HSTART_MASK); // DE H start
283 SC_W2BYTEMSK(1, REG_SC_BK10_05_L, u16DE_HStart + pstPanelInitData->u16Width/2 - 1 , VOP_DE_HEND_MASK); // DE H end
284 SC_W2BYTEMSK(1, REG_SC_BK10_06_L, u16DE_VStart, VOP_DE_VSTART_MASK); // DE V start
285 //FIX ME: need review
286 SC_W2BYTEMSK(1, REG_SC_BK10_07_L, u16DE_VStart+pstPanelInitData->u16Height-1, VOP_DE_VEND_MASK); // DE V end
287 }
288 // Display H/V start/size
289 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_08_L, u16DE_HStart , VOP_DISPLAY_HSTART_MASK); // Display H start
290 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_09_L, u16DE_HEND , VOP_DISPLAY_HEND_MASK); // Display H end
291 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_0A_L, u16DE_VStart , VOP_DISPLAY_VSTART_MASK); // Display V start
292 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_0B_L, u16DE_VEND , VOP_DISPLAY_VEND_MASK); // Display V end
293
294 // H/V sync start/width
295 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_01_L, (pstPanelInitData->u8HSyncWidth-1), LBMASK); // hsync width
296 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_02_L, ((u16VsyncStart & 0x7FF) | ((u16VsyncStart & 0x800) << 1)), 0x17FF); // vsync start = Vtt - (VSyncWidth + BackPorch)
297 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_03_L, (u16VsyncStart + pstPanelInitData->u8VSyncWidth - 1), VOP_VSYNC_END_MASK); // vsync end = Vsync start + Vsync Width
298 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_10_L, (pstPanelInitData->bManuelVSyncCtrl << 15), BIT(15)); // manual vsync control
299 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_10_L, BIT(14), BIT(14)); //default set to mode1 // disable auto_htotal
300 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_23_L, BIT(7), BIT(7));
301
302 // output control
303 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_21_L, pstPanelInitData->u16OCTRL);
304
305 if (pstPanelInitData->eLPLL_Type == E_PNL_TYPE_LVDS ||
306 pstPanelInitData->eLPLL_Type == E_PNL_TYPE_DAC_I ||
307 pstPanelInitData->eLPLL_Type == E_PNL_TYPE_DAC_P)
308 {
309 // LVDS
310 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_22_L, 0x11, LBMASK); // 0x2f44 : Enable clock of internal control - LVDS or TTL Output
311 }
312 else
313 {
314 // RSDS
315 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_22_L, 0x00, LBMASK);
316 }
317
318 SC_W2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_46_L, pstPanelInitData->u16OSTRL);
319
320 // output driving current
321 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_47_L, pstPanelInitData->u16ODRV, LBMASK);
322 }
323
MDrv_PNL_GetDefaultVfreq(void * pInstance,MS_U16 u16Vfreq)324 MS_U16 MDrv_PNL_GetDefaultVfreq(void *pInstance, MS_U16 u16Vfreq)
325 {
326 MS_U16 u16DefaultVFreq = 0;
327
328 UNUSED(pInstance);
329
330 if(u16Vfreq > 2100)
331 {
332 u16DefaultVFreq = 2400;
333 }
334 else if(u16Vfreq > 1900)
335 {
336 u16DefaultVFreq = 2000;
337 }
338 else if(u16Vfreq > 1100)
339 {
340 u16DefaultVFreq = 1200;
341 }
342 else if(u16Vfreq > 900)
343 {
344 u16DefaultVFreq = 1000;
345 }
346 else if(u16Vfreq > 550)
347 {
348 u16DefaultVFreq = 600;
349 }
350 else if(u16Vfreq > 350)
351 {
352 u16DefaultVFreq = 500;
353 }
354 else if(u16Vfreq > 250)
355 {
356 u16DefaultVFreq = 300;
357 }
358 else if(u16Vfreq > 245)
359 {
360 u16DefaultVFreq = 250;
361 }
362 else if(u16Vfreq > 235)
363 {
364 u16DefaultVFreq = 240;
365 }
366 else
367 {
368 u16DefaultVFreq = 150;
369 }
370
371 return u16DefaultVFreq;
372 }
373
_MDrv_PNL_Init_LPLL(void * pInstance,PNL_InitData * pstPanelInitData)374 static void _MDrv_PNL_Init_LPLL(void *pInstance, PNL_InitData *pstPanelInitData)
375 {
376 MS_U64 ldHz = 1;
377 MS_U16 u16DefaultVFreq = 0;
378
379 MS_U16 u16HTotal = pstPanelInitData->u16HTotal;
380 MS_U16 u16VTotal = pstPanelInitData->u16VTotal;
381
382 u16DefaultVFreq = MDrv_PNL_GetDefaultVfreq(pInstance, pstPanelInitData->u16DefaultVFreq);
383
384 if(((pstPanelInitData->u32PNL_MISC == E_DRVPNL_MISC_MFC_ENABLE) || (pstPanelInitData->u32PNL_MISC == E_DRVPNL_MISC_MFC_ENABLE_60HZ))
385 &&(pstPanelInitData->u16Width == 1280)
386 &&(pstPanelInitData->u16Height == 720))
387 {
388 u16HTotal = 2200;
389 u16VTotal = 1130;
390 }
391
392 printf("[%s][%d]pstPanelInitData->u16Width=%u, pstPanelInitData->u16Height=%u\n",
393 __FUNCTION__,__LINE__,pstPanelInitData->u16Width, pstPanelInitData->u16Height);
394 printf("[%s][%d]u16HTotal=%u,u16VTotal=%u,pstPanelInitData->u16HTotal=%u,pstPanelInitData->u16VTotal=%u, u16DefaultVFreq=%u\n",
395 __FUNCTION__,__LINE__,u16HTotal,u16VTotal,pstPanelInitData->u16HTotal,pstPanelInitData->u16VTotal,u16DefaultVFreq);
396
397 ldHz = (MS_U64) (((MS_U64)u16HTotal) * (MS_U64)u16VTotal * (MS_U64)u16DefaultVFreq);
398
399 MHal_PNL_Init_LPLL(pInstance, pstPanelInitData->eLPLL_Type,pstPanelInitData->eLPLL_Mode,ldHz);
400
401 if ((pstPanelInitData->u32PNL_MISC == E_DRVPNL_MISC_MFC_ENABLE) ||
402 (pstPanelInitData->u32PNL_MISC == E_DRVPNL_MISC_MFC_ENABLE_60HZ) ||
403 (E_PNL_LPLL_VBY1_10BIT_8LANE == pstPanelInitData->eLPLL_Type)) // Napoli VB1_8lane default use FRC, so need 2 LPLL
404 {
405 MHal_PNL_FRC_lpll_src_sel(pInstance, 0);
406 }
407 else
408 {
409 MHal_PNL_FRC_lpll_src_sel(pInstance, 1);
410 }
411
412 }
413
_MDrv_PNL_DClkFactor(void * pInstance,PNL_MODE eLPLL_Mode,PNL_TYPE eLPLL_Type,MS_U64 ldHz)414 static MS_U64 _MDrv_PNL_DClkFactor(void *pInstance, PNL_MODE eLPLL_Mode, PNL_TYPE eLPLL_Type, MS_U64 ldHz)
415 {
416 return (((MS_U64)LVDS_MPLL_CLOCK_MHZ * 524288 * MHal_PNL_Get_LPLL_LoopGain(pInstance, eLPLL_Mode, eLPLL_Type, ldHz))); //216*524288*8=0x36000000
417 }
418
_MDrv_PNL_Init_Output_Dclk(void * pInstance,PNL_InitData * pstPanelInitData)419 static void _MDrv_PNL_Init_Output_Dclk(void *pInstance, PNL_InitData *pstPanelInitData)
420 {
421 MS_U32 u32OutputDclk;
422 MS_U16 u16DefaultVFreq = 0;
423 MS_U64 ldHz = 1;
424
425 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
426 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
427
428 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
429 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
430
431 MS_U16 u16HTotal = pstPanelInitData->u16HTotal;
432 MS_U16 u16VTotal = pstPanelInitData->u16VTotal;
433
434 u16DefaultVFreq = MDrv_PNL_GetDefaultVfreq(pInstance, pstPanelInitData->u16DefaultVFreq);
435
436 /// for A5/Agate FRC Active FPP 720P
437 if(((pstPanelInitData->u32PNL_MISC == E_DRVPNL_MISC_MFC_ENABLE) || (pstPanelInitData->u32PNL_MISC == E_DRVPNL_MISC_MFC_ENABLE_60HZ))
438 &&(pstPanelInitData->u16Width == 1280)
439 &&(pstPanelInitData->u16Height== 720))
440 {
441 u16HTotal = 2200;
442 u16VTotal = 1130;
443 }
444 printf("[%s][%d]pstPanelInitData->u16Width=%u, pstPanelInitData->u16Height=%u\n",
445 __FUNCTION__,__LINE__,pstPanelInitData->u16Width, pstPanelInitData->u16Height);
446 printf("[%s][%d]u16HTotal=%u,u16VTotal=%u,pstPanelInitData->u16HTotal=%u,pstPanelInitData->u16VTotal=%u, u16DefaultVFreq=%u\n",
447 __FUNCTION__,__LINE__,u16HTotal,u16VTotal,pstPanelInitData->u16HTotal,pstPanelInitData->u16VTotal,u16DefaultVFreq);
448
449 ldHz = (MS_U64) (((MS_U64)u16HTotal) * u16VTotal * u16DefaultVFreq);
450
451 u32OutputDclk = MDrv_PNL_CalculateLPLLSETbyDClk(pInstance, (MS_U64)ldHz, FALSE);
452
453 //printf("_MDrv_PNL_Init_Output_Dclk u32div = %lu, u32LpllSet = %lx\n", (MS_U32)u32div, (MS_U32)ldPllSet);
454
455 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
456 W2BYTEMSK(L_BK_LPLL(0x0C), FALSE, BIT(3));
457 W4BYTE(L_BK_LPLL(0x0F), u32OutputDclk);
458
459 if((pPNLResourcePrivate->stapiPNL._stPnlStatus.bPanel_Initialized == 0)&&
460 (pPNLResourcePrivate->stapiPNL._bSkipTimingChange == FALSE))
461 {
462 MHal_PNL_ChannelFIFOPointerADjust(pInstance);
463 }
464 #if SUPPORT_FRC
465 ldHz = (MS_U64) (((MS_U64)pstPanelInitData->u16HTotal) * pstPanelInitData->u16VTotal * u16DefaultVFreq);
466
467 Mhal_PNL_Flock_LPLLSet(pInstance, ldHz);
468 #endif
469 }
470
471
472 /*static void _MDrv_PNL_TCON_GetTabSize(MS_U8 *pTconTab, MS_U16 u16tabtype, MS_U32 *pu32TconTabsize)
473 {
474 MS_U8 u8Colslen = 0;
475 MS_U16 u16timeout = 0x3FFF;
476 MS_U16 u16Addr;
477 if (pTconTab == NULL)
478 {
479 PNL_ASSERT(0, "[%s] TCONTable error \n.", __FUNCTION__);
480 return;
481 }
482 switch(u16tabtype )
483 {
484 case TCON_TABTYPE_GENERAL:
485 case TCON_TABTYPE_GPIO:
486 case TCON_TABTYPE_SCALER:
487 case TCON_TABTYPE_MOD:
488 case TCON_TABTYPE_GAMMA:
489 u8Colslen = 4;
490 break;
491 case TCON_TABTYPE_POWER_SEQUENCE_ON:
492 case TCON_TABTYPE_POWER_SEQUENCE_OFF:
493 u8Colslen = 7;
494 break;
495 default:
496 PNL_ASSERT(0, "[%s] GetTable Size :unknown Tab Size \n.", __FUNCTION__);
497 return ;
498 }
499 while (--u16timeout)
500 {
501 u16Addr = (pTconTab[*pu32TconTabsize]<<8) + pTconTab[(*pu32TconTabsize +1)];
502 if (u16Addr == REG_TABLE_END) // check end of table
503 {
504 *pu32TconTabsize = *pu32TconTabsize + 4;
505 break;
506 }
507 *pu32TconTabsize = *pu32TconTabsize + u8Colslen;
508 }
509 if (u16timeout==0)
510 {
511 PNL_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
512 }
513
514 PNL_DBG(PNL_DBGLEVEL_INIT, "<<*pu32TconTabsize= %ld>>\n", *pu32TconTabsize);
515
516 if(*pu32TconTabsize > TCON_TAB_MAX_SIZE)
517 {
518 PNL_ASSERT(0, "[%s] Tab size too large than TCON_TAB_MAX_SIZE = %d \n.", __FUNCTION__, TCON_TAB_MAX_SIZE);
519 }
520 }*/
521
522 //-------------------------------------------------------------------------------------------------
523 // Global Functions
524 //-------------------------------------------------------------------------------------------------
MDrv_PNL_GetLibVer(void)525 const MS_U8 * MDrv_PNL_GetLibVer(void) ///< Get version
526 {
527 return _cPnlVer;
528 }
529
MDrv_PNL_GetInfo(void * pInstance)530 ST_PNL_DRV_INFO MDrv_PNL_GetInfo(void *pInstance) ///< Get info from driver
531 {
532 ST_PNL_DRV_INFO stPNLInfo = {GAMMA_TYPE, GAMMA_MAPPING};
533
534 UNUSED(pInstance);
535
536 return stPNLInfo;
537 }
538
MDrv_PNL_Control_Out_Swing(void * pInstance,MS_U16 u16Swing_Level)539 MS_BOOL MDrv_PNL_Control_Out_Swing(void *pInstance, MS_U16 u16Swing_Level)
540 {
541 return (MS_BOOL)MHal_PNL_MOD_Control_Out_Swing(pInstance, u16Swing_Level);
542 }
543
MDrv_PNL_PreInit(void * pInstance,PNL_OUTPUT_MODE eParam)544 PNL_Result MDrv_PNL_PreInit(void *pInstance, PNL_OUTPUT_MODE eParam)
545 {
546 if ( eParam == E_PNL_OUTPUT_MAX )
547 return E_PNL_FAIL;
548
549 MHal_PNL_PreInit(pInstance, eParam);
550
551 return E_PNL_OK;
552 }
553
554 // Output Dclk
MDrv_PNL_CalculateLPLLSETbyDClk(void * pInstance,MS_U64 u64LdHz,MS_BOOL bHighAccurate)555 MS_U32 MDrv_PNL_CalculateLPLLSETbyDClk(void *pInstance, MS_U64 u64LdHz, MS_BOOL bHighAccurate)
556 {
557
558 MS_U64 u64LdPllSet = 0;
559 MS_U32 u32Div = 0;
560 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
561 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
562
563 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
564 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
565
566 // loop div and loop gain use default parameters to avoid dclk floating out of range and getting wrong value
567 MS_U64 u64DefaultLdHz = (MS_U64) (((MS_U64)pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16HTotal)
568 * pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16VTotal
569 * pPNLResourcePrivate->stdrvPNL._stPnlInitData.u16DefaultVFreq);
570 #if defined (__aarch64__)
571 PNL_DBG(PNL_DBGLEVEL_INIT, "CalculateLPLLSETbyDClk u32KHz = %lu, u64DefaultLdHz = %lu\n", u64LdHz, u64DefaultLdHz);
572 #else
573 PNL_DBG(PNL_DBGLEVEL_INIT, "CalculateLPLLSETbyDClk u32KHz = %llu, u64DefaultLdHz = %llu\n", u64LdHz, u64DefaultLdHz);
574 #endif
575
576 #if (HW_DESIGN_HDMITX_VER == 2)
577 if ((E_PNL_TYPE_DAC_P == pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) || (E_PNL_TYPE_DAC_I == pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type))
578 {
579 // For Maxim HDMITx different color depth, need to use u64LdHz to parse loop_div
580 if (bHighAccurate)
581 u64DefaultLdHz = u64LdHz/100;
582 else
583 u64DefaultLdHz = u64LdHz;
584 }
585 #endif
586
587 #if (PNL_SUPPORT_2P_MODE == TRUE)
588 /// Mini LVDS, EPI34/28, LVDS_1CH, Vx1_1P are 1P structure
589 if(!((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_TTL)||
590 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_LVDS)&&(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode==E_PNL_MODE_SINGLE))||
591 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_HS_LVDS)&&(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode==E_PNL_MODE_SINGLE))||
592 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_1LANE)||(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_8BIT_1LANE)||
593 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_MINILVDS_2CH_3P_8BIT)&&(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_MINILVDS_1CH_6P_6BIT))||
594 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_EPI34_2P)&&(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_EPI28_4P))))
595 {
596 u64LdHz = u64LdHz/2;
597 }
598 #endif
599
600 MS_U32 u32Factor = 10;
601
602 if (bHighAccurate)
603 {
604 u32Factor = 1000;
605 }
606
607 switch(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type)
608 {
609
610 case E_PNL_TYPE_MINILVDS:
611 case E_PNL_TYPE_ANALOG_MINILVDS:
612 case E_PNL_TYPE_DIGITAL_MINILVDS:
613 case E_PNL_LPLL_MINILVDS_5P_2L:
614 case E_PNL_LPLL_MINILVDS_4P_2L:
615 case E_PNL_LPLL_MINILVDS_3P_2L:
616 case E_PNL_LPLL_MINILVDS_6P_1L:
617 case E_PNL_LPLL_MINILVDS_5P_1L:
618 case E_PNL_LPLL_MINILVDS_4P_1L:
619 case E_PNL_LPLL_MINILVDS_3P_1L:
620
621 case E_PNL_LPLL_MINILVDS_1CH_3P_6BIT:
622 case E_PNL_LPLL_MINILVDS_1CH_4P_6BIT:
623 case E_PNL_LPLL_MINILVDS_1CH_5P_6BIT:
624 case E_PNL_LPLL_MINILVDS_1CH_6P_6BIT:
625
626 case E_PNL_LPLL_MINILVDS_2CH_3P_6BIT:
627 case E_PNL_LPLL_MINILVDS_2CH_4P_6BIT:
628 case E_PNL_LPLL_MINILVDS_2CH_5P_6BIT:
629 case E_PNL_LPLL_MINILVDS_2CH_6P_6BIT:
630
631 case E_PNL_LPLL_MINILVDS_1CH_3P_8BIT:
632 case E_PNL_LPLL_MINILVDS_1CH_4P_8BIT:
633 case E_PNL_LPLL_MINILVDS_1CH_5P_8BIT:
634 case E_PNL_LPLL_MINILVDS_1CH_6P_8BIT:
635
636 case E_PNL_LPLL_MINILVDS_2CH_3P_8BIT:
637 case E_PNL_LPLL_MINILVDS_2CH_4P_8BIT:
638 case E_PNL_LPLL_MINILVDS_2CH_5P_8BIT:
639 case E_PNL_LPLL_MINILVDS_2CH_6P_8BIT:
640
641 case E_PNL_LPLL_EPI34_8P:
642 case E_PNL_LPLL_EPI28_8P:
643 case E_PNL_LPLL_EPI34_6P:
644 case E_PNL_LPLL_EPI28_6P:
645
646 case E_PNL_TYPE_TTL_TCON:
647 case E_PNL_TYPE_TTL:
648 case E_PNL_TYPE_LVDS:
649 case E_PNL_TYPE_RSDS:
650 case E_PNL_TYPE_MFC:
651 case E_PNL_TYPE_DAC_I:
652 case E_PNL_TYPE_DAC_P:
653 case E_PNL_TYPE_PDPLVDS:
654 case E_PNL_TYPE_HF_LVDS:
655 case E_PNL_TYPE_HS_LVDS:
656 case E_PNL_LPLL_HDMI_BYPASS_MODE:
657 case E_PNL_LPLL_VBY1_8BIT_4LANE_BYPASS_MODE:
658 case E_PNL_LPLL_VBY1_10BIT_4LANE_BYPASS_MODE:
659 default:
660 //the first " *2 " is from the dual mode
661 u32Div=(MS_U32)(MHal_PNL_Get_Loop_DIV(pInstance, pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode, pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type, u64DefaultLdHz));
662 u64LdPllSet = (_MDrv_PNL_DClkFactor(pInstance, pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Mode, pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type, u64DefaultLdHz) * 1000000 * u32Factor *2) + ((u64LdHz * u32Div) >> 1);
663 if(u32Div != 0)
664 {
665 #if (KERNEL_DRIVER_PATCH ==1)
666 u64LdPllSet /= u64LdHz;
667 #else
668 do_div(u64LdPllSet, u64LdHz);
669 #endif
670 do_div(u64LdPllSet, u32Div);
671 }
672 break;
673 }
674
675 PNL_DBG(PNL_DBGLEVEL_INIT, "CalculateLPLLSETbyDClk u32LpllSet = %tx\n", (ptrdiff_t)u64LdPllSet);
676 return (MS_U32)u64LdPllSet;
677
678 }
679
MDrv_PNL_Init(void * pInstance)680 PNL_Result MDrv_PNL_Init(void *pInstance)
681 {
682 MS_PHY u32NonPMBankSize, u32PMBankSize;
683
684 // get MMIO base
685 if(MDrv_MMIO_GetBASE( &g_ptr_PnlRiuBaseAddr, &u32NonPMBankSize, MS_MODULE_PNL ) != TRUE)
686 {
687 PNL_ASSERT(0, "%s %lx %lx\n", "Get base address failed", g_ptr_PnlRiuBaseAddr, u32NonPMBankSize);
688 return E_PNL_GET_BASEADDR_FAIL;
689 }
690 else
691 {
692 #if defined (__aarch64__)
693 printf("MDrv_PNL_Init u32PnlRiuBaseAddr = %lx\n", g_ptr_PnlRiuBaseAddr);
694 #else
695 printf("MDrv_PNL_Init u32PnlRiuBaseAddr = %tx\n", (ptrdiff_t)g_ptr_PnlRiuBaseAddr);
696 #endif
697 }
698
699 if(MDrv_MMIO_GetBASE( &g_ptr_PMRiuBaseAddr, &u32PMBankSize, MS_MODULE_PM ) != TRUE)
700 {
701 PNL_ASSERT(0, "%s %lx %lx\n", "Get PM base address failed", g_ptr_PMRiuBaseAddr, u32PMBankSize);
702 return E_PNL_GET_BASEADDR_FAIL;
703 }
704 else
705 {
706 #if defined (__aarch64__)
707 printf("MDrv_PNL_Init u32PnlRiuBaseAddr = %lx\n", g_ptr_PnlRiuBaseAddr);
708 #else
709 printf("MDrv_PNL_Init u32PMRiuBaseAddr = %tx\n",(ptrdiff_t) g_ptr_PMRiuBaseAddr);
710 #endif
711 }
712
713 MHal_PNL_Set_Device_Bank_Offset(pInstance);
714 MHal_PQ_Clock_Gen_For_Gamma(pInstance);
715 MHal_PNL_Init(pInstance);
716
717 return E_PNL_OK;
718 }
719
MDrv_PNL_SetPanelType(void * pInstance,PNL_InitData * pstPanelInitData)720 PNL_Result MDrv_PNL_SetPanelType(void *pInstance, PNL_InitData *pstPanelInitData)
721 {
722 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
723 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
724
725 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
726 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
727 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
728
729 if(
730 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_TYPE_TTL_TCON)||
731 ((pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type >= E_PNL_LPLL_MINILVDS_5P_2L)&&
732 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type <= E_PNL_LPLL_MINILVDS_1CH_6P_6BIT))))
733 {
734 if(MDrv_SYS_Query(E_SYS_QUERY_TCON_SUPPORTED) == FALSE)
735 {
736 printf("[%s][%d] ATTENTION!!! TCON PNL but not support TCON\n\n", __FUNCTION__, __LINE__);
737 return E_PNL_FAIL;
738 }
739 }
740
741 if (pPNLResourcePrivate->stdrvPNL._stPnlInitData.u32PNL_MISC == E_DRVPNL_MISC_MFC_ENABLE)
742 {
743 // For FRC case, check efuse about 120Hz panel support or not
744 if (MHal_PNL_Is_Support120Hz() == FALSE)
745 {
746 printf("[%s][%d] Only support 60Hz panel\n\n", __FUNCTION__, __LINE__);
747 return E_PNL_FAIL;
748 }
749 }
750
751 if( ( IsVBY1(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) )||
752 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_8BIT_4LANE_BYPASS_MODE) ||
753 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE_BYPASS_MODE))
754 {
755 if(MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(pInstance)!= TRUE)
756 {
757 pPNLResourcePrivate->stdrvPNL._stPnlInitData.bVideo_HW_Training_En = FALSE;
758 printf("[%s][%d] ATTENTION!!! Not support HW Training Mode\n\n", __FUNCTION__, __LINE__);
759 }
760
761 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.bVideo_HW_Training_En)
762 {
763 if((pPNLResourcePrivate->stapiPNL._stPnlStatus.bPanel_Initialized == 0)&&
764 (pPNLResourcePrivate->stapiPNL._bSkipTimingChange == FALSE))
765 {
766 MOD_W2BYTE(REG_MOD_BK00_60_L, 0x0000);
767 }
768 }
769 else
770 {
771 //Close the RT51 handshack code flow
772 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, BIT(14), BIT(14));
773 }
774 }
775
776 if(pPNLResourcePrivate->stapiPNL._bSkipTimingChange == FALSE)
777 {
778 MHal_PNL_Init_XC_Clk(pInstance, &pPNLResourcePrivate->stdrvPNL._stPnlInitData);
779 }
780 _MDrv_PNL_Init_XC_VOP(pInstance, &pPNLResourcePrivate->stdrvPNL._stPnlInitData);
781 _MDrv_PNL_Init_XC_T3D(pInstance, &pPNLResourcePrivate->stdrvPNL._stPnlInitData);
782 MHal_PNL_Init_MOD(pInstance, &pPNLResourcePrivate->stdrvPNL._stPnlInitData);
783 _MDrv_PNL_Init_LPLL(pInstance, &pPNLResourcePrivate->stdrvPNL._stPnlInitData);
784 _MDrv_PNL_Init_Output_Dclk(pInstance, &pPNLResourcePrivate->stdrvPNL._stPnlInitData);
785
786
787
788 if( ( IsVBY1(pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type) )||
789 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_8BIT_4LANE_BYPASS_MODE) ||
790 (pPNLResourcePrivate->stdrvPNL._stPnlInitData.eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE_BYPASS_MODE))
791 {
792 if(pPNLResourcePrivate->stdrvPNL._stPnlInitData.bVideo_HW_Training_En)
793 {
794 // MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x8000, 0x8000);
795 //MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE ,DISABLE);
796 MsOS_DelayTaskUs(100);
797 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance, TRUE ,ENABLE);
798 // MsOS_DelayTaskUs(10);
799 // MOD_W2BYTEMSK(REG_MOD_BK00_63_L, 0x0000, 0x8000);
800 }
801 else
802 {
803 //Open the RT51 handshack code flow
804 MOD_W2BYTEMSK(REG_MOD_BK00_44_L, 0, BIT(14));
805 }
806 }
807
808 return E_PNL_OK;
809 }
810
MDrv_PNL_Close(void * pInstance)811 PNL_Result MDrv_PNL_Close(void *pInstance)
812 {
813 UNUSED(pInstance);
814 return E_PNL_OK;
815 }
816
_MDrv_VOP_SetGammaMappingMode(void * pInstance,MS_U8 u8Mapping)817 static void _MDrv_VOP_SetGammaMappingMode(void *pInstance, MS_U8 u8Mapping)
818 {
819 MHal_VOP_SetGammaMappingMode(pInstance, u8Mapping);
820 }
821
822 /// set gamma table
MDrv_PNL_SetGammaTbl(void * pInstance,DRVPNL_GAMMA_TYPE eGammaType,MS_U8 * pu8GammaTab[3],DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)823 PNL_Result MDrv_PNL_SetGammaTbl(void *pInstance, DRVPNL_GAMMA_TYPE eGammaType, MS_U8* pu8GammaTab[3],
824 DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)
825 {
826 MS_U8 u8TgtChannel = 0;
827 MS_U8* pcTab1;
828 MS_U8 u8BackupMainSubEnableFlag = 0;
829 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
830 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
831
832 UNUSED(eGammaType);
833
834 // delay 2ms to wait LPLL stable (if not stable, it will make gamma value incorrect)
835 #ifdef MSOS_TYPE_LINUX_KERNEL
836 mdelay(2);
837 #else
838 MsOS_DelayTask(2);
839 #endif
840
841
842 // If gamma is on, turn if off
843 //if(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_50_L, BIT(0)))
844 if((SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_50_L, BIT(0)))&&(MApi_XC_MLG_GetStatus() != E_MLG_ENABLED))
845 {
846 if(MApi_XC_MLoad_GetStatus() == E_MLOAD_ENABLED)
847 {
848 MS_U32 u32Addr[2];
849 MS_U16 u16Data[2], u16Mask[2];
850 printf("MApi_XC_MLoad_GetStatus()\n");
851 // Disable Gamma of MainWindow
852 u32Addr[0] = 0x10A0;
853 u16Data[0] = 0x0000;
854 u16Mask[0] = 0x0001;
855 // Disable Gamma of SubWindow
856 u32Addr[1] = 0x0F30;
857 u16Data[1] = 0x0000;
858 u16Mask[1] = 0x0001;
859 MApi_XC_MLoad_WriteCmds_And_Fire(u32Addr ,u16Data ,u16Mask , 2);
860 }
861 else
862 {
863
864 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_50_L, FALSE, BIT(0));
865 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK0F_18_L, FALSE, BIT(0));
866 }
867
868 u8BackupMainSubEnableFlag |= BIT(0);
869 }
870 #ifdef USE_PANEL_GAMMA
871 else if (SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_26_L, BIT(3)))
872 {
873 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_26_L, FALSE, BIT(3));
874 u8BackupMainSubEnableFlag |= BIT(3);
875 }
876 #endif
877
878
879 _MDrv_VOP_SetGammaMappingMode(pInstance, (GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING) ? GAMMA_8BIT_MAPPING : GAMMA_10BIT_MAPPING);
880
881 if (MApi_XC_MLG_GetStatus() == E_MLG_ENABLED)
882 {
883 MS_U8 u8Channel;
884 MS_U16 pMaxGammaValue[3] ;
885 MS_U16 u16NumOfLevel = ((GammaMapMode == E_DRVPNL_GAMMA_8BIT_MAPPING) ? 256 : 1024);
886 pMaxGammaValue[0] = pMaxGammaValue[1] = pMaxGammaValue[2] = 0;
887 MApi_XC_MLG_Fire(pu8GammaTab[0], pu8GammaTab[1], pu8GammaTab[2], u16NumOfLevel, pMaxGammaValue);
888 // write max. value of gamma
889 for(u8Channel = 0; u8Channel < 3; u8Channel ++)
890 {
891 hal_PNL_SetMaxGammaValue(pInstance, u8Channel, pMaxGammaValue[u8Channel]);
892 }
893 }
894 else
895 {
896
897 while( u8TgtChannel < 3 ) // 0 for R, 1 for G, 2 for B
898 {
899 pcTab1 = pu8GammaTab[u8TgtChannel];
900 #ifdef MONACO_SC2
901 if(pPNLInstancePrivate->u32DeviceID == 0)
902 #endif
903 Hal_PNL_Set12BitGammaPerChannel(pInstance, u8TgtChannel, pcTab1, GammaMapMode);
904 #ifdef MONACO_SC2
905 else
906 Hal_PNL_Set12BitGammaPerChannel_SC2(pInstance, u8TgtChannel, pcTab1, GammaMapMode);
907 #endif
908 u8TgtChannel++;
909 }
910 }
911
912 // Recovery gamma table
913 //if( u8BackupMainSubEnableFlag & BIT(0) )
914 if(( u8BackupMainSubEnableFlag & BIT(0) )&&(MApi_XC_MLG_GetStatus() != E_MLG_ENABLED))
915 {
916
917 if(MApi_XC_MLoad_GetStatus() == E_MLOAD_ENABLED)
918 {
919 MS_U32 u32Addr[2];
920 MS_U16 u16Data[2], u16Mask[2];
921
922 // Enable Gamma of MainWindow
923 u32Addr[0] = 0x10A0;
924 u16Data[0] = 0x0001;
925 u16Mask[0] = 0x0001;
926 // Enable Gamma of SubWindow
927 u32Addr[1] = 0x0F30;
928 u16Data[1] = 0x0001;
929 u16Mask[1] = 0x0001;
930 MApi_XC_MLoad_WriteCmds_And_Fire(u32Addr ,u16Data ,u16Mask , 2);
931 }
932 else
933 {
934 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_50_L, BIT(0), BIT(0));
935 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK0F_18_L, BIT(0), BIT(0));
936 }
937 }
938 else if ( u8BackupMainSubEnableFlag & BIT(3) )
939 {
940 #ifdef USE_PANEL_GAMMA
941 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK24_26_L, BIT(3), BIT(3));
942 #endif
943 }
944 return E_PNL_OK;
945 }
946
947
948
MDrv_PNL_GetGammaTbl(void * pInstance,DRVPNL_GAMMA_TYPE eGammaType,MS_U8 * pu8GammaTab[3],DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)949 PNL_Result MDrv_PNL_GetGammaTbl(void *pInstance, DRVPNL_GAMMA_TYPE eGammaType, MS_U8* pu8GammaTab[3],
950 DRVPNL_GAMMA_MAPPEING_MODE GammaMapMode)
951 {
952 MS_U8 u8TgtChannel = 0;
953 MS_U8* pcTab1;
954 while( u8TgtChannel < 3 ) // 0 for R, 1 for G, 2 for B
955 {
956 pcTab1 = pu8GammaTab[u8TgtChannel];
957 Hal_PNL_Get12BitGammaPerChannel(pInstance, u8TgtChannel, pcTab1, GammaMapMode);
958 u8TgtChannel++;
959 }
960 return E_PNL_OK;
961 }
962
963
MDrv_PNL_SetGammaValue(void * pInstance,MS_U8 u8Channel,MS_U16 u16Offset,MS_U16 u16GammaValue)964 PNL_Result MDrv_PNL_SetGammaValue(void *pInstance, MS_U8 u8Channel, MS_U16 u16Offset, MS_U16 u16GammaValue)
965 {
966 MS_U16 u16MaxGammaValue;
967 MS_U8 u8BackupMainSubEnableFlag = 0;
968 MS_U16 u16MaxOffset = 0;
969 MS_BOOL bUsingBurstWrite = FALSE;
970 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
971 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
972
973 // delay 2ms to wait LPLL stable (if not stable, it will make gamma value incorrect)
974 #ifdef MSOS_TYPE_LINUX_KERNEL
975 mdelay(2);
976 #else
977 MsOS_DelayTask(2);
978 #endif
979
980 if (u8Channel > 2)
981 {
982 return E_PNL_FAIL;
983 }
984
985 if (Hal_VOP_Is_GammaMappingMode_enable(pInstance))
986 {
987 u16MaxOffset = 1024;
988 // Check write mode
989 bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance, E_DRVPNL_GAMMA_10BIT_MAPPING);
990 }
991 else
992 {
993 u16MaxOffset = 256;
994 bUsingBurstWrite = !Hal_VOP_Is_GammaSupportSignalWrite(pInstance, E_DRVPNL_GAMMA_8BIT_MAPPING);
995 }
996
997 if (u16Offset >= u16MaxOffset)
998 {
999 return E_PNL_FAIL;
1000 }
1001
1002 // If gamma is on, turn if off
1003 if(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_50_L, BIT(0)))
1004 {
1005 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_50_L, FALSE, BIT(0));
1006 u8BackupMainSubEnableFlag |= BIT(0);
1007 }
1008
1009 hal_PNL_WriteGamma12Bit(pInstance, u8Channel,bUsingBurstWrite, u16Offset, u16GammaValue);
1010
1011 u16MaxGammaValue = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK10_7A_L + 2 * u8Channel), 0xFFF);
1012 if (u16GammaValue > u16MaxGammaValue)
1013 {
1014 u16MaxGammaValue = u16GammaValue;
1015 }
1016
1017 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK10_7A_L + 4 * u8Channel), u16MaxGammaValue, 0xFFF); // max. base 0
1018 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, (REG_SC_BK10_7B_L + 4 * u8Channel), u16MaxGammaValue, 0xFFF); // max. base 1
1019
1020 // Recovery gamma table
1021 if( u8BackupMainSubEnableFlag & BIT(0) )
1022 {
1023 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_50_L, BIT(0), BIT(0));
1024 }
1025
1026
1027 return E_PNL_OK;
1028 }
1029
MDrv_PNL_En(void * pInstance,MS_BOOL bPanelOn,MS_BOOL bCalEn)1030 PNL_Result MDrv_PNL_En(void *pInstance, MS_BOOL bPanelOn, MS_BOOL bCalEn)
1031 {
1032 return MHal_PNL_En(pInstance, bPanelOn, bCalEn);
1033 }
1034
1035 //-----------------------------------------------------------------------------
1036 // SSC
1037 //-----------------------------------------------------------------------------
1038 // SPAN value, recommend value is 20KHz ~ 40KHz
1039 // STEP percent value, recommend is under 3%
1040
1041 // recommend value.
1042 // u16Periodx100Hz == 350, u16Percentx100 == 200
MDrv_PNL_SetSSC(void * pInstance,MS_U16 u16Fmodulation,MS_U16 u16Rdeviation,MS_BOOL bEnable)1043 PNL_Result MDrv_PNL_SetSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable)
1044 {
1045 MS_U16 u16Span;
1046 MS_U16 u16Step;
1047 MS_U32 u32PLL_SET;/// = MDrv_Read3Byte(L_BK_LPLL(0x0F));
1048
1049
1050 PNL_DBG(PNL_DBGLEVEL_SSC, "[%s][%d]\n", __FUNCTION__, __LINE__);
1051 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
1052 u32PLL_SET = R4BYTE(L_BK_LPLL(0x0F));
1053 // Set SPAN
1054 if(u16Fmodulation < 200 || u16Fmodulation > 400)
1055 u16Fmodulation = 300;
1056 u16Span =(((((MS_U64)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR ) / (u16Fmodulation) ) * 10000) / ((MS_U32)u32PLL_SET) ) ;
1057
1058 // Set STEP
1059 if(u16Rdeviation > 300)
1060 u16Rdeviation = 300;
1061 u16Step = ((MS_U32)u32PLL_SET*u16Rdeviation) / ((MS_U32)u16Span*10000);
1062
1063 W2BYTE(L_BK_LPLL(0x17), u16Step & 0x03FF);// LPLL_STEP
1064 W2BYTE(L_BK_LPLL(0x18), u16Span & 0x3FFF);// LPLL_SPAN
1065 W2BYTEMSK((L_BK_LPLL(0x0D)), (bEnable << 11), BIT(11)); // Enable ssc
1066
1067
1068 return E_PNL_OK;
1069 }
1070
1071
1072 //-----------------------------------------------------------------------------
1073 // OSD SSC
1074 //-----------------------------------------------------------------------------
1075 // SPAN value, recommend value is 20KHz ~ 40KHz
1076 // STEP percent value, recommend is under 3%
1077 // recommend value.
1078 // u16Periodx100Hz == 350, u16Percentx100 == 200
MDrv_PNL_SetOSDSSC(void * pInstance,MS_U16 u16Fmodulation,MS_U16 u16Rdeviation,MS_BOOL bEnable)1079 PNL_Result MDrv_PNL_SetOSDSSC(void *pInstance, MS_U16 u16Fmodulation, MS_U16 u16Rdeviation, MS_BOOL bEnable)
1080 {
1081 MHal_PNL_SetOSDSSC(pInstance, u16Fmodulation, u16Rdeviation, bEnable);
1082 return E_PNL_OK;
1083 }
1084
MDrv_PNL_SetOutputPattern(void * pInstance,MS_BOOL bEnable,MS_U16 u16Red,MS_U16 u16Green,MS_U16 u16Blue)1085 void MDrv_PNL_SetOutputPattern(void *pInstance, MS_BOOL bEnable, MS_U16 u16Red , MS_U16 u16Green, MS_U16 u16Blue)
1086 {
1087
1088 //printf("MDrv_PNL_SetOutputPattern: bEnable = %u, R/G/B=0x%x, 0x%x, 0x%x\n", bEnable, u16Red , u16Green, u16Blue);
1089 MHal_PNL_SetOutputPattern(pInstance, bEnable, u16Red , u16Green, u16Blue);
1090 }
1091
MDrv_PNL_SetOutputType(void * pInstance,PNL_OUTPUT_MODE eOutputMode,PNL_TYPE eLPLL_Type)1092 void MDrv_PNL_SetOutputType(void *pInstance, PNL_OUTPUT_MODE eOutputMode, PNL_TYPE eLPLL_Type)
1093 {
1094 MHal_PNL_SetOutputType(pInstance, eOutputMode, eLPLL_Type);
1095 }
1096
1097 #define REG_TABLE_END 0xFFFFFFFF
MDrv_PNL_TCON_DumpSCRegTab(void * pInstance,MS_U8 * pu8TconTab)1098 void MDrv_PNL_TCON_DumpSCRegTab(void *pInstance, MS_U8* pu8TconTab)
1099 {
1100 MS_U32 u32tabIdx = 0;
1101 MS_U16 u16timeout = 0x3FFF;
1102 MS_U32 u32Addr;
1103 MS_U16 u16Mask;
1104 MS_U16 u16Value;
1105 // MS_BOOL bHiByte;
1106 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1107 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1108
1109 PNL_DBG(PNL_DBGLEVEL_INIT, "MDrv_PNL_TCON_DumpSCRegTab\n");
1110 PNL_DBG(PNL_DBGLEVEL_INIT, "tab: sc \n");
1111
1112 if (pu8TconTab == NULL)
1113 {
1114 PNL_ASSERT(0, "[%s] TCONTable error \n.", __FUNCTION__);
1115 return;
1116 }
1117
1118 while (--u16timeout)
1119 {
1120 u32Addr = ((pu8TconTab[u32tabIdx]<<24) + (pu8TconTab[(u32tabIdx +1)]<<16) + (pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0xFFFFFFFF;
1121 u16Mask = pu8TconTab[(u32tabIdx +4)] & 0xFF;
1122 u16Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;
1123
1124 if (u32Addr == REG_TABLE_END) // check end of table
1125 break;
1126
1127 #if 1
1128 W1BYTEMSK(u32Addr, u16Value, u16Mask);
1129 #else
1130 bHiByte = (u32Addr & 0x8000) ? TRUE : FALSE;
1131 u32Addr = ((u32Addr & 0x7F00) | ((u32Addr & 0xFF) << 1));
1132
1133 //PNL_DBG(PNL_DBGLEVEL_INIT, "[addr=%04lx, msk=%02x, val=%02x] \n", u32Addr, u16Mask, u16Value);
1134 //PNL_DBG(PNL_DBGLEVEL_INIT, "[addr=%04lx, msk=%02x, val=%02x] \n", BK_SC((u32Addr & 0x00FF))|bHiByte, u16Mask, u16Value);
1135
1136 if (bHiByte)
1137 {
1138 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, u32Addr, (u16Value << 8), (u16Mask << 8));
1139 }
1140 else
1141 {
1142 SC_W2BYTEMSK(pPNLInstancePrivate->u32DeviceID, u32Addr, u16Value, u16Mask);
1143 }
1144 #endif
1145 u32tabIdx = u32tabIdx + 6;
1146 }
1147 if (u16timeout==0)
1148 {
1149 PNL_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
1150 }
1151 PNL_DBG(PNL_DBGLEVEL_INIT, "MDrv_PNL_TCON_DumpSCRegTab end\n");
1152 }
1153
MDrv_PNL_TCON_DumpMODRegTab(void * pInstance,MS_U8 * pu8TconTab)1154 void MDrv_PNL_TCON_DumpMODRegTab(void *pInstance, MS_U8* pu8TconTab)
1155 {
1156 MS_U32 u32tabIdx = 0;
1157 MS_U16 u16timeout = 0x3FFF;
1158 MS_U32 u32Addr;
1159 MS_U16 u16Mask;
1160 MS_U16 u16Value;
1161 // MS_BOOL bHiByte;
1162 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1163 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1164
1165 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1166 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1167
1168 PNL_DBG(PNL_DBGLEVEL_INIT, "MDrv_PNL_TCON_DumpMODRegTab\n");
1169
1170 PNL_DBG(PNL_DBGLEVEL_INIT, "tab: mod \n");
1171
1172 if (pu8TconTab == NULL)
1173 {
1174 PNL_ASSERT(0, "[%s] TCONTable error \n.", __FUNCTION__);
1175 return;
1176 }
1177
1178 pPNLResourcePrivate->stdrvPNL.g_bDrvPnl_UseTConTable_Mod = TRUE;
1179
1180 while (--u16timeout)
1181 {
1182 u32Addr = ((pu8TconTab[u32tabIdx]<<24) + (pu8TconTab[(u32tabIdx +1)]<<16) + (pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0xFFFFFFFF;
1183 u16Mask = pu8TconTab[(u32tabIdx +4)] & 0xFF;
1184 u16Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;
1185
1186 if (u32Addr == REG_TABLE_END) // check end of table
1187 break;
1188
1189 //printf("[addr=%04lx, msk=%02x, val=%02x] \n", u32Addr, u16Mask, u16Value);
1190
1191 PNL_DBG(PNL_DBGLEVEL_INIT, "[addr=%04tx, msk=%02x, val=%02x] \n",(ptrdiff_t) u32Addr, u16Mask, u16Value);
1192
1193 W1BYTEMSK(u32Addr, u16Value, u16Mask);
1194
1195 u32tabIdx = u32tabIdx + 6;
1196 }
1197
1198 if (u16timeout==0)
1199 {
1200 PNL_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
1201 }
1202 /// Add the TCON patch at here for different chip
1203 MHal_PNL_TCON_Patch();
1204
1205 PNL_DBG(PNL_DBGLEVEL_INIT, "MDrv_PNL_TCON_DumpMODRegTab END: REG_MOD_BK00_6E_L=%X\n", MOD_R2BYTE(REG_MOD_BK00_6E_L));
1206 }
1207
MDrv_PNL_TCON_DumpGENRegTab(void * pInstance,MS_U8 * pu8TconTab)1208 void MDrv_PNL_TCON_DumpGENRegTab(void *pInstance, MS_U8* pu8TconTab)
1209 {
1210 MS_U32 u32tabIdx = 0;
1211 MS_U16 u16timeout = 0x3FFF;
1212 MS_U32 u32Addr;
1213 MS_U8 u8Mask;
1214 MS_U8 u8Value;
1215 MS_U16 u16TconSubBank;
1216
1217 PNL_DBG(PNL_DBGLEVEL_INIT, "MDrv_PNL_TCON_DumpGENRegTab\n");
1218
1219 PNL_DBG(PNL_DBGLEVEL_INIT, "tab: gen \n");
1220
1221 if (pu8TconTab == NULL)
1222 {
1223 PNL_ASSERT(0, "[%s] TCONTable error \n.", __FUNCTION__);
1224 return;
1225 }
1226
1227 u16TconSubBank = MHal_PNL_Read_TCON_SubBank(pInstance);
1228 PNL_DBG(PNL_DBGLEVEL_INIT, "u16TconSubBank=%x\n", u16TconSubBank);
1229
1230 while (--u16timeout)
1231 {
1232 u32Addr = ((pu8TconTab[u32tabIdx]<<24) + (pu8TconTab[(u32tabIdx +1)]<<16) + (pu8TconTab[(u32tabIdx +2)]<<8) + pu8TconTab[(u32tabIdx +3)]) & 0xFFFFFFFF;
1233 u8Mask = pu8TconTab[(u32tabIdx +4)] & 0xFF;
1234 u8Value = pu8TconTab[(u32tabIdx +5)] & 0xFF;
1235
1236 if (u32Addr == REG_TABLE_END) // check end of table
1237 break;
1238
1239 PNL_DBG(PNL_DBGLEVEL_INIT, "[addr=%04tx, msk=%02x, val=%02x] \n", (ptrdiff_t)u32Addr, u8Mask, u8Value);
1240
1241 W1BYTEMSK(u32Addr, u8Value, u8Mask);
1242
1243 u32tabIdx = u32tabIdx + 6;
1244 }
1245
1246 MHal_PNL_Switch_TCON_SubBank(pInstance, u16TconSubBank);
1247
1248 if (u16timeout==0)
1249 {
1250 PNL_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
1251 }
1252 PNL_DBG(PNL_DBGLEVEL_INIT, "MDrv_PNL_TCON_DumpGENRegTab end\n");
1253 }
1254
1255 #if 0 // mode to APP
1256 static void _MDrv_PNL_TCON_DumpPSRegTab(MS_U8 u8TconTab[TCON_TAB_MAX_SIZE], MS_U8 u8Tcontype, MS_U8 *pu8delay)
1257 {
1258 MS_U32 u32tabIdx = 0;
1259 MS_U16 u16timeout = 0x3FFF;
1260 MS_U32 u32Addr;
1261 MS_U16 u16Mask;
1262 MS_U16 u16Value;
1263 MS_U8 u8signal_type = 0;
1264
1265 PNL_DBG(PNL_DBGLEVEL_INIT, "tab: power sequence \n");
1266
1267 if (u8TconTab == NULL)
1268 {
1269 PNL_ASSERT(0, "[%s] TCONTable error \n.", __FUNCTION__);
1270 return;
1271 }
1272
1273 while (--u16timeout)
1274 {
1275 u32Addr = ((u8TconTab[u32tabIdx]<<8) + u8TconTab[(u32tabIdx +1)]) & 0xFFFF;
1276 u16Mask = u8TconTab[(u32tabIdx +2)] & 0xFF;
1277 u16Value = u8TconTab[(u32tabIdx +3)] & 0xFF;
1278 u8signal_type = u8TconTab[(u32tabIdx +6)];
1279
1280 if (u32Addr == REG_TABLE_END) // check end of table
1281 break;
1282
1283 u32Addr = (u32Addr | 0x100000);
1284
1285 if(u8Tcontype == u8signal_type)
1286 {
1287 PNL_DBG(PNL_DBGLEVEL_INIT, "[addr=%04lx, msk=%02x, val=%02x] \n", u32Addr, u16Mask, u16Value);
1288
1289 if (u32Addr & 0x1)
1290 {
1291 u32Addr --;
1292 W2BYTEMSK(u32Addr, (u16Value << 8), (u16Mask << 8));
1293 }
1294 else
1295 {
1296 W2BYTEMSK(u32Addr, u16Value, u16Mask);
1297 }
1298 *pu8delay = u8TconTab[(u32tabIdx +5)];
1299 }
1300 u32tabIdx = u32tabIdx + 7;
1301 }
1302
1303 if (u16timeout==0)
1304 {
1305 PNL_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
1306 }
1307 }
1308 #endif
1309
1310
MDrv_PNL_TCON_Count_Reset(void * pInstance,MS_BOOL bEnable)1311 void MDrv_PNL_TCON_Count_Reset(void *pInstance, MS_BOOL bEnable)
1312 {
1313 UNUSED(pInstance);
1314 W2BYTEMSK(L_BK_TCON(0x03), (bEnable << 14), BIT(14));
1315 }
1316
MDrv_PNL_TCON_Init(void * pInstance)1317 void MDrv_PNL_TCON_Init(void *pInstance)
1318 {
1319 MHal_PNL_TCON_Init(pInstance);
1320 }
1321
1322
MDrv_PNL_GetDataFromRegister(void * pInstance,PNL_TimingInfo * PNLTiming)1323 MS_BOOL MDrv_PNL_GetDataFromRegister(void *pInstance, PNL_TimingInfo *PNLTiming)
1324 {
1325 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1326 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1327
1328 if(NULL == PNLTiming)
1329 {
1330 return FALSE;
1331 }
1332
1333 #if defined(PATCH_HW_VTT_LIMITATION)
1334 if(R1BYTEMSK(REG_CHIP_REVISION,0xFF) < HW_VTT_LIMITATION_CHIPREV)
1335 {
1336 PNLTiming->u16VTotal = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK68_36_L, VOP_VTT_MASK); // output vtotal
1337 }
1338 else
1339 #endif
1340 {
1341 //Vtotal
1342 PNLTiming->u16VTotal = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_0D_L, VOP_VTT_MASK); // output vtotal
1343 }
1344 PNLTiming->u16DEVStart = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_06_L, VOP_DE_VSTART_MASK); // DE V start
1345 PNLTiming->u16DEVEnd = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_07_L, VOP_DE_VEND_MASK); // DE V end
1346 PNLTiming->u16VSyncStart= SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_02_L, 0xFFF); // DE V end
1347 PNLTiming->u16VSyncEnd = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_03_L, VOP_VSYNC_END_MASK); // DE V end
1348
1349
1350 // Htotal
1351 PNLTiming->u16HTotal = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_0C_L, VOP_HTT_MASK); // output htotal
1352 PNLTiming->u16DEHStart = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_04_L, VOP_DE_HSTART_MASK); // DE H start
1353 PNLTiming->u16DEHEnd = SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_05_L, VOP_DE_HEND_MASK); // DE H end
1354 PNLTiming->u16HSyncWidth= SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_01_L, LBMASK); // DE H end
1355 PNLTiming->bIsPanelManualVysncMode = (MS_BOOL)(SC_R2BYTEMSK(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_10_L, BIT(15)) >> 15);
1356
1357 PNLTiming->bInterlaceOutput = MHal_PNL_GetOutputInterlaceTiming(pInstance);
1358 //printf("----MDrv_PNL_GetDataFromRegister().DAC flag------------%x,%x,%x\n", PM_R1BYTE(L_BK_DAC(REG_DAC_HD_CTRL), 0:0),
1359 // PM_R1BYTE(L_BK_DAC(REG_DAC_SD_CTRL), 2:0),
1360 // PM_R1BYTE(H_BK_HDMITX(REG_VE_CONFIG_01), 0:0));
1361 return TRUE;
1362 }
1363
MDrv_PNL_SetSSC_En(void * pInstance,MS_BOOL bEnable)1364 void MDrv_PNL_SetSSC_En(void *pInstance, MS_BOOL bEnable)
1365 {
1366 //printf("bEnable = %d\n", bEnable);
1367 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
1368 W2BYTEMSK((L_BK_LPLL(0x0D)), (bEnable << 11), BIT(11)); // Enable ssc
1369 }
1370
MDrv_PNL_SetOSDSSC_En(void * pInstance,MS_BOOL bEnable)1371 void MDrv_PNL_SetOSDSSC_En(void *pInstance, MS_BOOL bEnable)
1372 {
1373 MHal_PNL_SetOSDSSC_En(pInstance, bEnable);
1374 }
1375
MDrv_PNL_SetSSC_Fmodulation(void * pInstance,MS_U16 u16Fmodulation)1376 void MDrv_PNL_SetSSC_Fmodulation(void *pInstance, MS_U16 u16Fmodulation)
1377 {
1378
1379 #if 1
1380 MS_U64 u64Span;
1381 //MS_U16 u16Step;
1382 MS_U32 u32PLL_SET;/// = MDrv_Read3Byte(L_BK_LPLL(0x0F));
1383
1384 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
1385 u32PLL_SET = R4BYTE(L_BK_LPLL(0x0F));
1386 //printf("u16Fmodulation = %d\n", u16Fmodulation );
1387 u64Span = (((MS_U64)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR)/(u16Fmodulation) ) * 10000;
1388 u64Span = (u64Span+(u32PLL_SET/2))/u32PLL_SET;
1389 //u16Span =( ( (((MS_U32)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR ) / (u16Fmodulation) ) * 10000) + ((MS_U32)u32PLL_SET/2)) / ((MS_U32)u32PLL_SET) ;
1390 //printf("u64Span = 0x%x\n", u64Span);
1391 W2BYTE(L_BK_LPLL(0x18), (MS_U16)u64Span & 0x3FFF);// LPLL_SPAN
1392
1393 #endif
1394
1395 }
1396
MDrv_PNL_SetOSDSSC_Fmodulation(void * pInstance,MS_U16 u16Fmodulation)1397 void MDrv_PNL_SetOSDSSC_Fmodulation(void *pInstance, MS_U16 u16Fmodulation)
1398 {
1399 #if 1
1400 MS_U64 u64Span;
1401 //MS_U16 u16Step;
1402 MS_U32 u32PLL_SET;/// = MDrv_Read3Byte(L_BK_LPLL(0x0F));
1403
1404 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
1405 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48));
1406 //printf("u16Fmodulation = %d\n", u16Fmodulation );
1407 u64Span = (((MS_U64)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR)/(u16Fmodulation) ) * 10000;
1408 u64Span = (u64Span+(u32PLL_SET/2))/u32PLL_SET;
1409 //u16Span =( ( (((MS_U32)LVDS_MPLL_CLOCK_MHZ*LVDS_SPAN_FACTOR ) / (u16Fmodulation) ) * 10000) + ((MS_U32)u32PLL_SET/2)) / ((MS_U32)u32PLL_SET) ;
1410 //printf("u64Span = 0x%x\n", u64Span);
1411 W2BYTE(L_BK_LPLL(0x4F),(MS_U16)u64Span& 0x3FFF);// LPLL_SPAN
1412 #endif
1413 }
1414
1415
MDrv_PNL_SetSSC_Rdeviation(void * pInstance,MS_U16 u16Rdeviation)1416 void MDrv_PNL_SetSSC_Rdeviation(void *pInstance, MS_U16 u16Rdeviation)
1417 {
1418 #if 1
1419 MS_U16 u16Span;
1420 MS_U16 u16Step;
1421 MS_U32 u32PLL_SET;
1422
1423 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
1424 u32PLL_SET = R4BYTE(L_BK_LPLL(0x0F));
1425 u16Span =R2BYTE(L_BK_LPLL(0x18)) ;
1426 //printf("u16Rdeviation = %d\n", u16Rdeviation);
1427 u16Step = (((MS_U32)u32PLL_SET*u16Rdeviation) + ((MS_U32)u16Span*5000)) / ((MS_U32)u16Span*10000);
1428 //printf("u16Step = 0x%x\n", u16Step);
1429 W2BYTE(L_BK_LPLL(0x17), u16Step & 0x0FFF);// LPLL_STEP
1430 #endif
1431 }
1432
MDrv_PNL_SetOSDSSC_Rdeviation(void * pInstance,MS_U16 u16Rdeviation)1433 void MDrv_PNL_SetOSDSSC_Rdeviation(void *pInstance, MS_U16 u16Rdeviation)
1434 {
1435 #if 1
1436 MS_U16 u16Span;
1437 MS_U16 u16Step;
1438 MS_U32 u32PLL_SET;
1439
1440 MHal_PNL_Switch_LPLL_SubBank(pInstance, 0x00);
1441 u32PLL_SET = R4BYTE(L_BK_LPLL(0x48));
1442 u16Span =R2BYTE(L_BK_LPLL(0x4F)) ;
1443 //printf("u16Rdeviation = %d\n", u16Rdeviation);
1444 u16Step = (((MS_U32)u32PLL_SET*u16Rdeviation) + ((MS_U32)u16Span*5000)) / ((MS_U32)u16Span*10000);
1445 //printf("u16Step = 0x%x\n", u16Step);
1446 W2BYTE(L_BK_LPLL(0x4E), u16Step & 0x0FFF);// LPLL_STEP
1447 #endif
1448 }
1449
MDrv_Mod_Calibration_Init(void * pInstance,PNL_ModCali_InitData * pstModCaliInitData)1450 void MDrv_Mod_Calibration_Init(void *pInstance, PNL_ModCali_InitData *pstModCaliInitData)
1451 {
1452 MHal_MOD_Calibration_Init(pInstance, pstModCaliInitData);
1453 }
1454
MDrv_BD_LVDS_Output_Type(void * pInstance,MS_U16 Type)1455 void MDrv_BD_LVDS_Output_Type(void *pInstance, MS_U16 Type)
1456 {
1457 MHal_BD_LVDS_Output_Type(pInstance, Type);
1458 }
1459
MDrv_PNL_SkipTimingChange_GetCaps(void * pInstance)1460 MS_BOOL MDrv_PNL_SkipTimingChange_GetCaps(void *pInstance)
1461 {
1462 return Hal_PNL_SkipTimingChange_GetCaps(pInstance);
1463 }
1464
MDrv_PNL_PreSetModeOn(void * pInstance,MS_BOOL bSetMode)1465 void MDrv_PNL_PreSetModeOn(void *pInstance, MS_BOOL bSetMode)
1466 {
1467 MHal_PNL_PreSetModeOn(pInstance, bSetMode);
1468 }
1469
MDrv_PNL_HWLVDSReservedtoLRFlag(void * pInstance,PNL_DrvHW_LVDSResInfo lvdsresinfo)1470 void MDrv_PNL_HWLVDSReservedtoLRFlag(void *pInstance, PNL_DrvHW_LVDSResInfo lvdsresinfo)
1471 {
1472 MHal_PNL_HWLVDSReservedtoLRFlag(pInstance, lvdsresinfo);
1473 }
1474
MDrv_PNL_OverDriver_Init(void * pInstance,MS_PHY u32OD_MSB_Addr,MS_PHY u32OD_LSB_Addr,MS_U8 u8ODTbl[1056])1475 void MDrv_PNL_OverDriver_Init(void *pInstance, MS_PHY u32OD_MSB_Addr, MS_PHY u32OD_LSB_Addr, MS_U8 u8ODTbl[1056])
1476 {
1477 MS_PHY u32OD_MSB_limit, u32OD_LSB_limit;
1478
1479 MS_U8 u8MIUSel = 0;
1480
1481 #if defined(__AEONR2__)
1482 if( u32OD_MSB_Addr > HAL_MIU1_BASE)
1483 {
1484 u32OD_MSB_Addr = u32OD_MSB_Addr - HAL_MIU1_BASE;
1485 u8MIUSel = 1;
1486 }
1487
1488 if( u32OD_LSB_Addr > HAL_MIU1_BASE)
1489 {
1490 u32OD_LSB_Addr = u32OD_LSB_Addr - HAL_MIU1_BASE;
1491 }
1492 #else
1493 if( u32OD_MSB_Addr > HAL_MIU2_BASE)
1494 {
1495 u32OD_MSB_Addr = u32OD_MSB_Addr - HAL_MIU2_BASE;
1496 u8MIUSel = 2;
1497 }
1498 else if( u32OD_MSB_Addr > HAL_MIU1_BASE)
1499 {
1500 u32OD_MSB_Addr = u32OD_MSB_Addr - HAL_MIU1_BASE;
1501 u8MIUSel = 1;
1502 }
1503
1504 if( u32OD_LSB_Addr > HAL_MIU2_BASE)
1505 {
1506 u32OD_LSB_Addr = u32OD_LSB_Addr - HAL_MIU2_BASE;
1507 }
1508 else if( u32OD_LSB_Addr > HAL_MIU1_BASE)
1509 {
1510 u32OD_LSB_Addr = u32OD_LSB_Addr - HAL_MIU1_BASE;
1511 }
1512 #endif
1513 u32OD_MSB_Addr = (u32OD_MSB_Addr / OD_BYTE_PER_WORD) & 0xFFFFFFFF;
1514 u32OD_MSB_limit = u32OD_MSB_Addr + (((1920 *1080 *15)/(8 * OD_BYTE_PER_WORD)) + (4096/OD_BYTE_PER_WORD) + 20 + 16024);
1515 u32OD_LSB_Addr = (u32OD_LSB_Addr / OD_BYTE_PER_WORD) & 0xFFFFFFFF;
1516 u32OD_LSB_limit = u32OD_LSB_Addr + (((1920 *1080 *6)/(8 * OD_BYTE_PER_WORD)) + 20 + 80);
1517 if (SUPPORT_OVERDRIVE)
1518 {
1519 MHal_PNL_OverDriver_Init(pInstance, u32OD_MSB_Addr, u32OD_MSB_limit, u32OD_LSB_Addr, u32OD_LSB_limit, u8MIUSel);
1520 MHal_PNL_OverDriver_TBL(pInstance, u8ODTbl);
1521 }
1522 }
1523
MDrv_PNL_OverDriver_Enable(void * pInstance,MS_BOOL bEnable)1524 void MDrv_PNL_OverDriver_Enable(void *pInstance, MS_BOOL bEnable)
1525 {
1526 if (SUPPORT_OVERDRIVE)
1527 {
1528 MHal_PNL_OverDriver_Enable(pInstance, bEnable);
1529 }
1530 }
1531
MDrv_PNL_Is_SupportFRC(void * pInstance)1532 MS_BOOL MDrv_PNL_Is_SupportFRC(void *pInstance)
1533 {
1534 UNUSED(pInstance);
1535 return SUPPORT_FRC;
1536 }
1537
MDrv_PNL_Is_SupportTCON(void * pInstance)1538 MS_BOOL MDrv_PNL_Is_SupportTCON(void *pInstance)
1539 {
1540 UNUSED(pInstance);
1541 return (MS_BOOL)SUPPORT_TCON;
1542 }
1543
MDrv_FRC_MOD_ForcePairSwap(void * pInstance,MS_U32 u32Polarity)1544 void MDrv_FRC_MOD_ForcePairSwap(void *pInstance, MS_U32 u32Polarity)
1545 {
1546 MHal_FRC_MOD_PairSwap_UserMode(pInstance, u32Polarity);
1547 }
1548
MDrv_PNL_Get_DEVstart(void * pInstance)1549 MS_U16 MDrv_PNL_Get_DEVstart(void *pInstance)
1550 {
1551 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1552 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1553 return SC_R2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_06_L) & 0x1FFF; //pnl de vstart, B[12:0]
1554 }
1555
MDrv_PNL_Get_DEHstart(void * pInstance)1556 MS_U16 MDrv_PNL_Get_DEHstart(void *pInstance)
1557 {
1558 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1559 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1560 return SC_R2BYTE(pPNLInstancePrivate->u32DeviceID, REG_SC_BK10_04_L) & 0x3FFF; //pnl de vstart, B[13:0]
1561 }
1562
MDrv_PNL_isYUVOutput(void * pInstance)1563 MS_BOOL MDrv_PNL_isYUVOutput(void *pInstance)
1564 {
1565 //Warning : this function is obsolete, please change to use MApi_XC_GetStatusEx
1566 //Because if all HW CSC engine is off, then pnl output color space is same with the input signal
1567 return MHal_PNL_IsYUVOutput(pInstance);
1568 }
1569
MDrv_PNL_GetDACOut(void * pInstance)1570 MS_BOOL MDrv_PNL_GetDACOut(void *pInstance)
1571 {
1572 UNUSED(pInstance);
1573 return IS_DAC_OUT;
1574 }
1575
MDrv_PNL_CalExtLPLLSETbyDClk(void * pInstance,MS_U8 u8LPLL_Mode,MS_U8 u8LPLL_Type,MS_U64 ldHz)1576 void MDrv_PNL_CalExtLPLLSETbyDClk(void *pInstance, MS_U8 u8LPLL_Mode, MS_U8 u8LPLL_Type, MS_U64 ldHz)
1577 {
1578 //printf("u8LPLL_Mode=%u,u8LPLL_Type=%u, ldHz=%u\n",u8LPLL_Mode, u8LPLL_Type, ldHz);
1579 MHal_PNL_CalExtLPLLSETbyDClk(pInstance, u8LPLL_Mode, u8LPLL_Type, ldHz);
1580 }
1581
MDrv_PNL_EnableInternalTermination(void * pInstance,MS_BOOL bEnable)1582 MS_BOOL MDrv_PNL_EnableInternalTermination(void *pInstance, MS_BOOL bEnable)
1583 {
1584 UNUSED(pInstance);
1585
1586 if(bEnable)
1587 {
1588 MOD_W2BYTE(REG_MOD_BK00_75_L, 0x3FFF); //GCR_EN_RINT (internal termination open)
1589 }
1590 else
1591 {
1592 MOD_W2BYTE(REG_MOD_BK00_75_L, 0x0000); //GCR_EN_RINT (internal termination close)
1593 }
1594
1595 return TRUE;
1596 }
1597
MDrv_PNL_VBY1_Handshake(void * pInstance)1598 MS_BOOL MDrv_PNL_VBY1_Handshake(void *pInstance)
1599 {
1600 return MHal_PNL_VBY1_Handshake(pInstance);
1601 }
1602
MDrv_PNL_VBY1_OC_Handshake(void * pInstance)1603 MS_BOOL MDrv_PNL_VBY1_OC_Handshake(void *pInstance)
1604 {
1605 return MHal_PNL_VBY1_OC_Handshake(pInstance);
1606 }
1607
MDrv_PNL_SetOutputInterlaceTiming(void * pInstance,MS_BOOL bEnable)1608 PNL_Result MDrv_PNL_SetOutputInterlaceTiming(void *pInstance, MS_BOOL bEnable)
1609 {
1610 return MHal_PNL_SetOutputInterlaceTiming(pInstance, bEnable);
1611 }
1612
MDrv_PNL_GetOutputInterlaceTiming(void * pInstance,MS_BOOL * bIsInterlaceOutput)1613 void MDrv_PNL_GetOutputInterlaceTiming(void *pInstance, MS_BOOL* bIsInterlaceOutput)
1614 {
1615 *bIsInterlaceOutput = MHal_PNL_GetOutputInterlaceTiming(pInstance);
1616 }
1617
MDrv_PNL_SetOSDCOutputType(void * pInstance,MS_U16 eLPLL_Type,MS_U8 eOC_OutputFormat)1618 void MDrv_PNL_SetOSDCOutputType(void *pInstance, MS_U16 eLPLL_Type, MS_U8 eOC_OutputFormat)
1619 {
1620 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1621 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1622
1623 UtopiaInstanceGetPrivate(pInstance, (void**)&pPNLInstancePrivate);
1624 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1625 PNL_DBG(PNL_DBGLEVEL_INIT, "[%s][%d]\n", __FUNCTION__, __LINE__);
1626
1627 if(((eLPLL_Type >= E_PNL_LPLL_VBY1_10BIT_4LANE)&&
1628 (eLPLL_Type <= E_PNL_LPLL_VBY1_8BIT_8LANE))||
1629 (eLPLL_Type == E_PNL_LPLL_VBY1_8BIT_4LANE_BYPASS_MODE) ||
1630 (eLPLL_Type == E_PNL_LPLL_VBY1_10BIT_4LANE_BYPASS_MODE))
1631 {
1632 if(MHal_PNL_VBY1_IsSupport_Hardware_TrainingMode(pInstance)!= TRUE)
1633 {
1634 pPNLResourcePrivate->stdrvPNL._stPnlInitData.bOSD_HW_Training_En = FALSE;
1635 printf("[%s][%d] ATTENTION!!! Not support HW Training Mode\n\n", __FUNCTION__, __LINE__);
1636 }
1637 }
1638
1639 MHal_PNL_SetOSDCOutputType(pInstance, (PNL_TYPE) eLPLL_Type, (E_PNL_OSDC_OUTPUT_FORMAT)eOC_OutputFormat);
1640 }
1641
MDrv_PNL_Get_Semaphore(void * pInstance,E_PNL_POOL_ID eID)1642 MS_U32 MDrv_PNL_Get_Semaphore(void *pInstance,E_PNL_POOL_ID eID)
1643 {
1644 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1645
1646 if (eID >= E_PNL_POOL_ID_MAX)
1647 {
1648 printf("[%s,%5d] Unknown PNL Pool ID\n",__func__, __LINE__);
1649 return u32Return;
1650 }
1651
1652 if (pInstance == NULL)
1653 {
1654 printf("[%s,%5d]No instance existed, please get an instance by calling MApi_PNL_Init() first\n",__FUNCTION__,__LINE__);
1655 return u32Return;
1656 }
1657
1658 #if 0 // for Debug. It is important to check the tid
1659 pid_t tid;
1660 tid = syscall(SYS_gettid);
1661 printf("tid = (%d)\n",tid);
1662 #endif
1663
1664 void* pModule = NULL;
1665 UtopiaInstanceGetModule(pInstance, &pModule);
1666 if(UtopiaResourceObtain(pModule, eID, &g_pPNLResource[eID]) != UTOPIA_STATUS_SUCCESS)
1667 {
1668 printf("UtopiaResourceObtain fail\n");
1669 return UTOPIA_STATUS_ERR_RESOURCE;
1670 }
1671 u32Return = UTOPIA_STATUS_SUCCESS;
1672 return u32Return;
1673 }
1674
MDrv_PNL_Release_Semaphore(void * pInstance,E_PNL_POOL_ID eID)1675 MS_U32 MDrv_PNL_Release_Semaphore(void *pInstance,E_PNL_POOL_ID eID)
1676 {
1677 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1678
1679 if (eID >= E_PNL_POOL_ID_MAX)
1680 {
1681 printf("[%s,%5d] Unknown PNL Pool ID\n",__func__, __LINE__);
1682 return u32Return;
1683 }
1684 #if 0 // for Debug. It is important to check the tid
1685 pid_t tid;
1686 tid = syscall(SYS_gettid);
1687 printf("tid = (%d)\n",tid);
1688 #endif
1689
1690 u32Return = UtopiaResourceRelease(g_pPNLResource[eID]);
1691 return u32Return;
1692 }
1693
MDrv_PNL_GetDeviceNum(void)1694 MS_U32 MDrv_PNL_GetDeviceNum(void)
1695 {
1696 return PNL_SUPPORT_DEVICE_NUM;
1697 }
1698
MDrv_PNL_GetPanelVStart(void)1699 MS_U16 MDrv_PNL_GetPanelVStart(void)
1700 {
1701 return MHal_PNL_GetPanelVStart();
1702 }
1703
MDrv_PNL_Check_VBY1_Handshake_Status(void * pInstance)1704 MS_BOOL MDrv_PNL_Check_VBY1_Handshake_Status(void *pInstance)
1705 {
1706 return MHal_PNL_Check_VBY1_Handshake_Status(pInstance);
1707 }
1708
MDrv_PNL_MOD_PECurrent_Setting(void * pInstance,MS_U16 u16Current_Level,MS_U16 u16Channel_Select)1709 void MDrv_PNL_MOD_PECurrent_Setting(void *pInstance, MS_U16 u16Current_Level, MS_U16 u16Channel_Select)
1710 {
1711 MHal_PNL_MOD_PECurrent_Setting(pInstance, u16Current_Level, u16Channel_Select);
1712 }
1713
MDrv_PNL_VBY1_Hardware_TrainingMode_En(void * pInstance,MS_BOOL bIsVideoMode,MS_BOOL bEnable)1714 void MDrv_PNL_VBY1_Hardware_TrainingMode_En(void *pInstance, MS_BOOL bIsVideoMode ,MS_BOOL bEnable)
1715 {
1716 MHal_PNL_VBY1_Hardware_TrainingMode_En(pInstance,bIsVideoMode,bEnable);
1717 }
1718
MDrv_PNL_GetName(void)1719 const char* MDrv_PNL_GetName(void)
1720 {
1721 const char* pPanelName="";
1722 if (pu32PNLInst == NULL)
1723 {
1724 return pPanelName;
1725 }
1726
1727 PNL_INSTANCE_PRIVATE *pPNLInstancePrivate = NULL;
1728 PNL_RESOURCE_PRIVATE* pPNLResourcePrivate = NULL;
1729 UtopiaInstanceGetPrivate(pu32PNLInst, (void**)&pPNLInstancePrivate);
1730 UtopiaResourceGetPrivate(g_pPNLResource[PNL_GET_INTERNAL_POOL_ID(pPNLInstancePrivate->u32DeviceID)],(void**)(&pPNLResourcePrivate));
1731 pPanelName = pPNLResourcePrivate->stdrvPNL._stPnlInitData.pPanelName;
1732 //printf("\033[1;31m ###***###[%s][%d]pPanelName = %s\033[0m\n",__func__,__LINE__,pPanelName);
1733 return pPanelName;
1734 }
1735
1736