1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #include "MsCommon.h" 96 97 98 #define _RV1(addr, value) (((addr) >> 16) & 0xFF), (((addr) >> 8) & 0xFF), (MS_U8)(addr), (MS_U8)(value) 99 #define _END_OF_TBL2_ 0xFF, 0xFF, 0xFF 100 101 102 MS_U8 tVE_ENCODER_NTSC_TBL[] = 103 { 104 //video encoder 105 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync start 106 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end 107 _RV1(L_BK_VE_ENC(0x01), 0x94),// burst start 108 _RV1(H_BK_VE_ENC(0x01), 0xD7),// burst end 109 _RV1(L_BK_VE_ENC(0x02), 0x00), 110 _RV1(H_BK_VE_ENC(0x02), 0x00), 111 _RV1(L_BK_VE_ENC(0x03), 0x00), 112 _RV1(H_BK_VE_ENC(0x03), 0x00), 113 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast 114 _RV1(H_BK_VE_ENC(0x04), 0x4C),// contrast 115 _RV1(L_BK_VE_ENC(0x06), 0x00), 116 _RV1(H_BK_VE_ENC(0x06), 0x00), 117 _RV1(L_BK_VE_ENC(0x09), 0xB4),// h total 118 _RV1(H_BK_VE_ENC(0x09), 0x06), 119 _RV1(L_BK_VE_ENC(0x0A), 0x00),// brightness 120 _RV1(H_BK_VE_ENC(0x0A), 0x80),// brightness 121 _RV1(L_BK_VE_ENC(0x0B), 0x1F),// burst phase step 122 _RV1(H_BK_VE_ENC(0x0B), 0x7C), 123 _RV1(L_BK_VE_ENC(0x0C), 0xF0), 124 _RV1(H_BK_VE_ENC(0x0C), 0x21), 125 _RV1(L_BK_VE_ENC(0x0D), 0xD0), 126 _RV1(H_BK_VE_ENC(0x0D), 0x00), 127 _RV1(L_BK_VE_ENC(0x0E), 0x00), 128 _RV1(H_BK_VE_ENC(0x0E), 0x00), 129 _RV1(L_BK_VE_ENC(0x25), 0x00),// av st 130 _RV1(H_BK_VE_ENC(0x25), 0x01), 131 _RV1(L_BK_VE_ENC(0x26), 0x8D),// av end 132 _RV1(H_BK_VE_ENC(0x26), 0x06), 133 _RV1(L_BK_VE_ENC(0x27), 0x2A),// sync tip level & pad level 134 _RV1(H_BK_VE_ENC(0x27), 0x10), 135 _RV1(L_BK_VE_ENC(0x28), 0xF0),// sync step & blank level 136 _RV1(H_BK_VE_ENC(0x28), 0x38), 137 _RV1(L_BK_VE_ENC(0x29), 0x13),// burst amp & step 138 _RV1(H_BK_VE_ENC(0x29), 0x70), 139 _RV1(L_BK_VE_ENC(0x2A), 0x41),//chroma gain 140 _RV1(H_BK_VE_ENC(0x2A), 0x5B), 141 _RV1(L_BK_VE_ENC(0x2D), 0x20),// Y clamp 142 _RV1(H_BK_VE_ENC(0x2D), 0x53), 143 _RV1(L_BK_VE_ENC(0x2E), 0x00), 144 _RV1(H_BK_VE_ENC(0x2E), 0x00), 145 146 _RV1(L_BK_VE_ENC(0x78), 0x00),// disable MV 147 148 //video source 149 _RV1(L_BK_VE_SRC(0x42), 0xE0),// Frame line num 150 _RV1(H_BK_VE_SRC(0x42), 0x01), 151 _RV1(L_BK_VE_SRC(0x45), 0x30),// Field Size 152 _RV1(H_BK_VE_SRC(0x45), 0x2A), 153 154 _END_OF_TBL2_, 155 }; 156 157 MS_U8 tVE_ENCODER_NTSC_443_TBL[] = 158 { 159 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync st 160 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end 161 _RV1(L_BK_VE_ENC(0x01), 0x8E),// burst st 162 _RV1(H_BK_VE_ENC(0x01), 0xD1),// burst end 163 _RV1(L_BK_VE_ENC(0x02), 0x00), 164 _RV1(H_BK_VE_ENC(0x02), 0x00), 165 _RV1(L_BK_VE_ENC(0x03), 0x00), 166 _RV1(H_BK_VE_ENC(0x03), 0x00), 167 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast 168 _RV1(H_BK_VE_ENC(0x04), 0x4C),// contrast 169 _RV1(L_BK_VE_ENC(0x09), 0xB4),// h total 170 _RV1(H_BK_VE_ENC(0x09), 0x06), 171 _RV1(L_BK_VE_ENC(0x0A), 0x00),// brightness 172 _RV1(H_BK_VE_ENC(0x0A), 0x80),// brightness 173 _RV1(L_BK_VE_ENC(0x0B), 0xCB),// burst phase step 174 _RV1(H_BK_VE_ENC(0x0B), 0x8A), 175 _RV1(L_BK_VE_ENC(0x0C), 0x09), 176 _RV1(H_BK_VE_ENC(0x0C), 0x2A), 177 _RV1(L_BK_VE_ENC(0x0D), 0x2E), 178 _RV1(H_BK_VE_ENC(0x0D), 0x05), 179 _RV1(L_BK_VE_ENC(0x0E), 0xB2), 180 _RV1(H_BK_VE_ENC(0x0E), 0x01), 181 _RV1(L_BK_VE_ENC(0x25), 0xFF),// av st 182 _RV1(H_BK_VE_ENC(0x25), 0x00), 183 _RV1(L_BK_VE_ENC(0x26), 0x8D),// av end 184 _RV1(H_BK_VE_ENC(0x26), 0x06), 185 _RV1(L_BK_VE_ENC(0x27), 0x2A),// sync tip level & pad level 186 _RV1(H_BK_VE_ENC(0x27), 0x10), 187 _RV1(L_BK_VE_ENC(0x28), 0xF0),// sync step & blank level 188 _RV1(H_BK_VE_ENC(0x28), 0x38), 189 _RV1(L_BK_VE_ENC(0x29), 0x13),// burst amp & step 190 _RV1(H_BK_VE_ENC(0x29), 0x70), 191 _RV1(L_BK_VE_ENC(0x2A), 0x41),//chroma gain 192 _RV1(H_BK_VE_ENC(0x2A), 0x5B), 193 _RV1(L_BK_VE_ENC(0x2D), 0x20),// Y clamp 194 _RV1(H_BK_VE_ENC(0x2D), 0x53), 195 196 _RV1(L_BK_VE_ENC(0x78), 0x00),// disable MV 197 198 _RV1(L_BK_VE_SRC(0x42), 0xE0),// Frame line num 199 _RV1(H_BK_VE_SRC(0x42), 0x01), 200 _RV1(L_BK_VE_SRC(0x45), 0x30),// Field Size 201 _RV1(H_BK_VE_SRC(0x45), 0x2A), 202 _END_OF_TBL2_ 203 }; 204 205 MS_U8 tVE_ENCODER_NTSC_J_TBL[] = 206 { 207 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync st 208 _RV1(H_BK_VE_ENC(0x00), 0x7F),// hsync end 209 _RV1(L_BK_VE_ENC(0x01), 0x8E),// burst st 210 _RV1(H_BK_VE_ENC(0x01), 0xD1),// burst end 211 _RV1(L_BK_VE_ENC(0x02), 0x00), 212 _RV1(H_BK_VE_ENC(0x02), 0x00), 213 _RV1(L_BK_VE_ENC(0x03), 0x00), 214 _RV1(H_BK_VE_ENC(0x03), 0x00), 215 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast 216 _RV1(H_BK_VE_ENC(0x04), 0x52),// brightness 217 _RV1(L_BK_VE_ENC(0x09), 0xB4),// H total 218 _RV1(H_BK_VE_ENC(0x09), 0x06), 219 _RV1(L_BK_VE_ENC(0x0A), 0x00),// brightness 220 _RV1(H_BK_VE_ENC(0x0A), 0x80),// brightness 221 _RV1(L_BK_VE_ENC(0x0B), 0x1F),// burst phase step 222 _RV1(H_BK_VE_ENC(0x0B), 0x7C), 223 _RV1(L_BK_VE_ENC(0x0C), 0xF0), 224 _RV1(H_BK_VE_ENC(0x0C), 0x21), 225 _RV1(L_BK_VE_ENC(0x0D), 0xD0),// lower stage fraction 226 _RV1(H_BK_VE_ENC(0x0D), 0x00), 227 _RV1(L_BK_VE_ENC(0x0E), 0x00),// 625 stage fraction 228 _RV1(H_BK_VE_ENC(0x0E), 0x00), 229 _RV1(L_BK_VE_ENC(0x25), 0xFF),// av st 230 _RV1(H_BK_VE_ENC(0x25), 0x00), 231 _RV1(L_BK_VE_ENC(0x26), 0x8D),// av end 232 _RV1(H_BK_VE_ENC(0x26), 0x06), 233 _RV1(L_BK_VE_ENC(0x27), 0x00),// sync tip level & pad level 234 _RV1(H_BK_VE_ENC(0x27), 0x10), 235 _RV1(L_BK_VE_ENC(0x28), 0xF0),// sync step & blank level 236 _RV1(H_BK_VE_ENC(0x28), 0x38), 237 _RV1(L_BK_VE_ENC(0x29), 0x13),// burst amp & burst step 238 _RV1(H_BK_VE_ENC(0x29), 0x70), 239 _RV1(L_BK_VE_ENC(0x2A), 0x46),//chroma gain 240 _RV1(H_BK_VE_ENC(0x2A), 0x62), 241 _RV1(L_BK_VE_ENC(0x2D), 0x20),// Y clamp 242 _RV1(H_BK_VE_ENC(0x2D), 0x53), 243 244 _RV1(L_BK_VE_ENC(0x78), 0x00),// disable MV 245 246 _RV1(L_BK_VE_SRC(0x42), 0xE0),// Frame line number 247 _RV1(H_BK_VE_SRC(0x42), 0x01), 248 _RV1(L_BK_VE_SRC(0x45), 0x30),// Field Size 249 _RV1(H_BK_VE_SRC(0x45), 0x2A), 250 _END_OF_TBL2_, 251 }; 252 253 MS_U8 tVE_ENCODER_PAL_M_TBL[] = 254 { 255 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync st 256 _RV1(H_BK_VE_ENC(0x00), 0x7E),// hsync end 257 _RV1(L_BK_VE_ENC(0x01), 0x9B),// burst st 258 _RV1(H_BK_VE_ENC(0x01), 0xDE),// burst end 259 _RV1(L_BK_VE_ENC(0x02), 0x00), 260 _RV1(H_BK_VE_ENC(0x02), 0x00), 261 _RV1(L_BK_VE_ENC(0x03), 0x0A), 262 _RV1(H_BK_VE_ENC(0x03), 0x00), 263 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast 264 _RV1(H_BK_VE_ENC(0x04), 0x50),// contrast 265 _RV1(L_BK_VE_ENC(0x06), 0x02), 266 _RV1(L_BK_VE_ENC(0x09), 0xB4),// H total 267 _RV1(H_BK_VE_ENC(0x09), 0x06), 268 269 _RV1(L_BK_VE_ENC(0x0A), 0x00),// brightness 270 _RV1(H_BK_VE_ENC(0x0A), 0x80),// brightness 271 _RV1(L_BK_VE_ENC(0x0B), 0xE3),// burst phase step 272 _RV1(H_BK_VE_ENC(0x0B), 0xEF), 273 _RV1(L_BK_VE_ENC(0x0C), 0xE6), 274 _RV1(H_BK_VE_ENC(0x0C), 0x21), 275 _RV1(L_BK_VE_ENC(0x0D), 0x90),// lower stage fraction 276 _RV1(H_BK_VE_ENC(0x0D), 0x09), 277 _RV1(L_BK_VE_ENC(0x0E), 0x00),// 625 stage fraction 278 _RV1(H_BK_VE_ENC(0x0E), 0x00), 279 _RV1(L_BK_VE_ENC(0x25), 0xFA),// av st 280 _RV1(H_BK_VE_ENC(0x25), 0x00), 281 _RV1(L_BK_VE_ENC(0x26), 0x8C),// av end 282 _RV1(H_BK_VE_ENC(0x26), 0x06), 283 _RV1(L_BK_VE_ENC(0x27), 0x2A),// sync tip level & pad level 284 _RV1(H_BK_VE_ENC(0x27), 0x10), 285 _RV1(L_BK_VE_ENC(0x28), 0xF0),// sync step & blank level 286 _RV1(H_BK_VE_ENC(0x28), 0x3F), 287 _RV1(L_BK_VE_ENC(0x29), 0x14),// burst amp & burst step 288 _RV1(H_BK_VE_ENC(0x29), 0x54), 289 _RV1(L_BK_VE_ENC(0x2A), 0x44),//chroma gain 290 _RV1(H_BK_VE_ENC(0x2A), 0x60), 291 _RV1(L_BK_VE_ENC(0x2D), 0x30),// Y clamp 292 _RV1(H_BK_VE_ENC(0x2D), 0x53), 293 _RV1(L_BK_VE_ENC(0x78), 0x00),// disable MV 294 295 _RV1(L_BK_VE_SRC(0x42), 0xE0),// Frame line number 296 _RV1(H_BK_VE_SRC(0x42), 0x01), 297 _RV1(L_BK_VE_SRC(0x45), 0xA0),// Field Size 298 _RV1(H_BK_VE_SRC(0x45), 0x32), 299 _END_OF_TBL2_, 300 }; 301 302 MS_U8 tVE_ENCODER_PAL_N_TBL[] = 303 { 304 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync st 305 _RV1(H_BK_VE_ENC(0x00), 0x7E),// hsync end 306 _RV1(L_BK_VE_ENC(0x01), 0x97),// burst st 307 _RV1(H_BK_VE_ENC(0x01), 0xE1),// burst end 308 _RV1(L_BK_VE_ENC(0x02), 0x00), 309 _RV1(H_BK_VE_ENC(0x02), 0x00), 310 _RV1(L_BK_VE_ENC(0x03), 0x0A), 311 _RV1(H_BK_VE_ENC(0x03), 0x00), 312 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast 313 _RV1(H_BK_VE_ENC(0x04), 0x50),// contrast 314 _RV1(L_BK_VE_ENC(0x06), 0x02), 315 _RV1(L_BK_VE_ENC(0x09), 0xC0),// H total 316 _RV1(H_BK_VE_ENC(0x09), 0x06), 317 _RV1(L_BK_VE_ENC(0x0A), 0x00),// brightness 318 _RV1(H_BK_VE_ENC(0x0A), 0x80),// brightness 319 _RV1(L_BK_VE_ENC(0x0B), 0xCB),// burst phase step 320 _RV1(H_BK_VE_ENC(0x0B), 0x8A), 321 _RV1(L_BK_VE_ENC(0x0C), 0x09), 322 _RV1(H_BK_VE_ENC(0x0C), 0x2A), 323 _RV1(L_BK_VE_ENC(0x0D), 0x2E),// lower stage fraction 324 _RV1(H_BK_VE_ENC(0x0D), 0x05), 325 _RV1(L_BK_VE_ENC(0x0E), 0xB2),// 625 stage fraction 326 _RV1(H_BK_VE_ENC(0x0E), 0x01), 327 _RV1(L_BK_VE_ENC(0x25), 0xFE),// av st 328 _RV1(H_BK_VE_ENC(0x25), 0x00), 329 _RV1(L_BK_VE_ENC(0x26), 0x96),// av end 330 _RV1(H_BK_VE_ENC(0x26), 0x06), 331 _RV1(L_BK_VE_ENC(0x27), 0x2A),// sync tip level & pad level 332 _RV1(H_BK_VE_ENC(0x27), 0x10), 333 _RV1(L_BK_VE_ENC(0x28), 0xF0),// sync step & blank level 334 _RV1(H_BK_VE_ENC(0x28), 0x3F), 335 _RV1(L_BK_VE_ENC(0x29), 0x14),// burst amp & burst step 336 _RV1(H_BK_VE_ENC(0x29), 0x54), 337 _RV1(L_BK_VE_ENC(0x2A), 0x46),//chroma gain 338 _RV1(H_BK_VE_ENC(0x2A), 0x62), 339 _RV1(L_BK_VE_ENC(0x2D), 0x30),// Y clamp 340 _RV1(H_BK_VE_ENC(0x2D), 0x53), 341 _RV1(L_BK_VE_ENC(0x78), 0x00),// disable MacroVision 342 343 _RV1(L_BK_VE_SRC(0x42), 0x40),// Frame line number 344 _RV1(H_BK_VE_SRC(0x42), 0x02), 345 _RV1(L_BK_VE_SRC(0x45), 0xA0),// Field Size 346 _RV1(H_BK_VE_SRC(0x45), 0x32), 347 _END_OF_TBL2_ 348 }; 349 350 MS_U8 tVE_ENCODER_PAL_NC_TBL[] = 351 { 352 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync st 353 _RV1(H_BK_VE_ENC(0x00), 0x7E),// hsync end 354 _RV1(L_BK_VE_ENC(0x01), 0x97),// burst st 355 _RV1(H_BK_VE_ENC(0x01), 0xD3),// burst end 356 _RV1(L_BK_VE_ENC(0x02), 0x00), 357 _RV1(H_BK_VE_ENC(0x02), 0x00), 358 _RV1(L_BK_VE_ENC(0x03), 0x0A), 359 _RV1(H_BK_VE_ENC(0x03), 0x00), 360 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast 361 _RV1(H_BK_VE_ENC(0x04), 0x50),// contrast 362 _RV1(L_BK_VE_ENC(0x06), 0x02), 363 _RV1(L_BK_VE_ENC(0x09), 0xC0),// H total 364 _RV1(H_BK_VE_ENC(0x09), 0x06), 365 _RV1(L_BK_VE_ENC(0x0A), 0x00),// brightness 366 _RV1(H_BK_VE_ENC(0x0A), 0x80),// brightness 367 _RV1(L_BK_VE_ENC(0x0B), 0x46),// burst phase step 368 _RV1(H_BK_VE_ENC(0x0B), 0x94), 369 _RV1(L_BK_VE_ENC(0x0C), 0xF6), 370 _RV1(H_BK_VE_ENC(0x0C), 0x21), 371 _RV1(L_BK_VE_ENC(0x0D), 0x2E),// lower stage fraction 372 _RV1(H_BK_VE_ENC(0x0D), 0x0C), 373 _RV1(L_BK_VE_ENC(0x0E), 0xB2),// 625 stage fraction 374 _RV1(H_BK_VE_ENC(0x0E), 0x01), 375 _RV1(L_BK_VE_ENC(0x25), 0x17),// av st 376 _RV1(H_BK_VE_ENC(0x25), 0x01), 377 _RV1(L_BK_VE_ENC(0x26), 0x96),// av end 378 _RV1(H_BK_VE_ENC(0x26), 0x06), 379 _RV1(L_BK_VE_ENC(0x27), 0x00),// sync tip level & pad level 380 _RV1(H_BK_VE_ENC(0x27), 0x10), 381 _RV1(L_BK_VE_ENC(0x28), 0xFC),// sync step & blank level 382 _RV1(H_BK_VE_ENC(0x28), 0x3F), 383 _RV1(L_BK_VE_ENC(0x29), 0x14),// burst amp & burst step 384 _RV1(H_BK_VE_ENC(0x29), 0x54), 385 _RV1(L_BK_VE_ENC(0x2A), 0x46),//chroma gain 386 _RV1(H_BK_VE_ENC(0x2A), 0x62), 387 _RV1(L_BK_VE_ENC(0x2D), 0x30),// Y clamp 388 _RV1(H_BK_VE_ENC(0x2D), 0x53), 389 _RV1(L_BK_VE_ENC(0x78), 0x00),// disable MV 390 391 _RV1(L_BK_VE_SRC(0x42), 0x40),// Frame line number 392 _RV1(H_BK_VE_SRC(0x42), 0x02), 393 _RV1(L_BK_VE_SRC(0x45), 0xA0),// Field Size 394 _RV1(H_BK_VE_SRC(0x45), 0x32), 395 _END_OF_TBL2_ 396 }; 397 398 MS_U8 tVE_ENCODER_PAL_TBL[] = //for DTV/ATV 399 { 400 _RV1(L_BK_VE_ENC(0x00), 0x01),// hsync st 401 _RV1(H_BK_VE_ENC(0x00), 0x7E),// hsync end 402 _RV1(L_BK_VE_ENC(0x01), 0x9d),// burst st 403 _RV1(H_BK_VE_ENC(0x01), 0xD9),// burst end 404 _RV1(L_BK_VE_ENC(0x02), 0x00), 405 _RV1(H_BK_VE_ENC(0x02), 0x00), 406 _RV1(L_BK_VE_ENC(0x03), 0x08), 407 _RV1(H_BK_VE_ENC(0x03), 0x00), 408 _RV1(L_BK_VE_ENC(0x04), 0x00),// contrast 409 _RV1(H_BK_VE_ENC(0x04), 0x50),// contrast 410 _RV1(L_BK_VE_ENC(0x06), 0x02),// H total 411 _RV1(H_BK_VE_ENC(0x06), 0x00), 412 _RV1(L_BK_VE_ENC(0x09), 0xC0), 413 _RV1(H_BK_VE_ENC(0x09), 0x06), 414 _RV1(L_BK_VE_ENC(0x0A), 0x00),// brightness 415 _RV1(H_BK_VE_ENC(0x0A), 0x80),// brightness 416 _RV1(L_BK_VE_ENC(0x0B), 0xCB),// burst phase step 417 _RV1(H_BK_VE_ENC(0x0B), 0x8A), 418 _RV1(L_BK_VE_ENC(0x0C), 0x09), 419 _RV1(H_BK_VE_ENC(0x0C), 0x2A), 420 _RV1(L_BK_VE_ENC(0x0D), 0x2E),// lower stage fraction 421 _RV1(H_BK_VE_ENC(0x0D), 0x05), 422 _RV1(L_BK_VE_ENC(0x0E), 0xB2),// 625 stage fraction 423 _RV1(H_BK_VE_ENC(0x0E), 0x01), 424 _RV1(L_BK_VE_ENC(0x25), 0x17),// av st 425 _RV1(H_BK_VE_ENC(0x25), 0x01), 426 _RV1(L_BK_VE_ENC(0x26), 0x96),// av end 427 _RV1(H_BK_VE_ENC(0x26), 0x06), 428 _RV1(L_BK_VE_ENC(0x27), 0x00),// sync tip level & pad level 429 _RV1(H_BK_VE_ENC(0x27), 0x10), 430 _RV1(L_BK_VE_ENC(0x28), 0xFC),// sync step & blank level 431 _RV1(H_BK_VE_ENC(0x28), 0x3F), 432 _RV1(L_BK_VE_ENC(0x29), 0x14),// burst amp & burst step 433 _RV1(H_BK_VE_ENC(0x29), 0x54), 434 _RV1(L_BK_VE_ENC(0x2A), 0x46),//chroma gain 435 _RV1(H_BK_VE_ENC(0x2A), 0x62), 436 _RV1(L_BK_VE_ENC(0x2D), 0x30),// Y clamp 437 _RV1(H_BK_VE_ENC(0x2D), 0x53), 438 //_RV1(L_BK_VE_ENC(0x2E), 0x88), //modify for digital TTX 439 //_RV1(H_BK_VE_ENC(0x2E), 0x00), 440 441 _RV1(L_BK_VE_ENC(0x78), 0x00),// disable MV 442 443 _RV1(L_BK_VE_SRC(0x42), 0x40),// Frame line number 444 _RV1(H_BK_VE_SRC(0x42), 0x02), 445 _RV1(L_BK_VE_SRC(0x45), 0xA0),// Field Size 446 _RV1(H_BK_VE_SRC(0x45), 0x32), 447 _END_OF_TBL2_ 448 }; 449 450 MS_U8 tVE_COEF_NTSC_TBL[] = 451 {// disable filter 452 /* _RV1(L_BK_VE_ENC(0x0F), 0x00),// lfir_coef1 453 _RV1(H_BK_VE_ENC(0x0F), 0x00), 454 _RV1(L_BK_VE_ENC(0x10), 0x00),// lfir_coef2 455 _RV1(H_BK_VE_ENC(0x10), 0x00), 456 _RV1(L_BK_VE_ENC(0x11), 0x00),// lfir_coef3 457 _RV1(H_BK_VE_ENC(0x11), 0x00), 458 _RV1(L_BK_VE_ENC(0x12), 0x00),// lfir_coef4 459 _RV1(H_BK_VE_ENC(0x12), 0x00), 460 _RV1(L_BK_VE_ENC(0x13), 0x00),// lfir_coef5 461 _RV1(H_BK_VE_ENC(0x13), 0x00), 462 _RV1(L_BK_VE_ENC(0x14), 0x00),// lfir_coef6 463 _RV1(H_BK_VE_ENC(0x14), 0x00), 464 _RV1(L_BK_VE_ENC(0x15), 0x00),// lfir_coef7 465 _RV1(H_BK_VE_ENC(0x15), 0x00), 466 _RV1(L_BK_VE_ENC(0x16), 0x00),// lfir_coef8 467 _RV1(H_BK_VE_ENC(0x16), 0x00), 468 _RV1(L_BK_VE_ENC(0x17), 0x00),// lfir_coef9 469 _RV1(H_BK_VE_ENC(0x17), 0x00), 470 _RV1(L_BK_VE_ENC(0x18), 0x00),// lfir_coef10 471 _RV1(H_BK_VE_ENC(0x18), 0x00), 472 _RV1(L_BK_VE_ENC(0x19), 0x00),// lfir_coef11 473 _RV1(H_BK_VE_ENC(0x19), 0x08), 474 _RV1(L_BK_VE_ENC(0x1A), 0x00),// cfir_coef1 475 _RV1(H_BK_VE_ENC(0x1A), 0x00), 476 _RV1(L_BK_VE_ENC(0x1B), 0x00),// cfir_coef2 477 _RV1(H_BK_VE_ENC(0x1B), 0x00), 478 _RV1(L_BK_VE_ENC(0x1C), 0x00),// cfir_coef3 479 _RV1(H_BK_VE_ENC(0x1C), 0x00), 480 _RV1(L_BK_VE_ENC(0x1D), 0x00),// cfir_coef4 481 _RV1(H_BK_VE_ENC(0x1D), 0x00), 482 _RV1(L_BK_VE_ENC(0x1E), 0x00),// cfir_coef5 483 _RV1(H_BK_VE_ENC(0x1E), 0x00), 484 _RV1(L_BK_VE_ENC(0x1F), 0x00),// cfir_coef6 485 _RV1(H_BK_VE_ENC(0x1F), 0x00), 486 _RV1(L_BK_VE_ENC(0x20), 0x00),// cfir_coef7 487 _RV1(H_BK_VE_ENC(0x20), 0x00), 488 _RV1(L_BK_VE_ENC(0x21), 0x00),// cfir_coef7 489 _RV1(H_BK_VE_ENC(0x21), 0x00), 490 _RV1(L_BK_VE_ENC(0x22), 0x00),// cfir_coef9 491 _RV1(H_BK_VE_ENC(0x22), 0x00), 492 _RV1(L_BK_VE_ENC(0x23), 0x00),// cfir_coef10 493 _RV1(H_BK_VE_ENC(0x23), 0x00), 494 _RV1(L_BK_VE_ENC(0x24), 0x00),// cfir_coef11 495 _RV1(H_BK_VE_ENC(0x24), 0x04),*/ 496 _END_OF_TBL2_ 497 }; 498 499 MS_U8 tVE_COEF_PAL_TBL[] = 500 { 501 /* _RV1(L_BK_VE_ENC(0x0F), 0x00),// lfir_coef1 502 _RV1(H_BK_VE_ENC(0x0F), 0x00), 503 _RV1(L_BK_VE_ENC(0x10), 0x00),// lfir_coef2 504 _RV1(H_BK_VE_ENC(0x10), 0x00), 505 _RV1(L_BK_VE_ENC(0x11), 0x00),// lfir_coef3 506 _RV1(H_BK_VE_ENC(0x11), 0x00), 507 _RV1(L_BK_VE_ENC(0x12), 0x00),// lfir_coef4 508 _RV1(H_BK_VE_ENC(0x12), 0x00), 509 _RV1(L_BK_VE_ENC(0x13), 0x00),// lfir_coef5 510 _RV1(H_BK_VE_ENC(0x13), 0x00), 511 _RV1(L_BK_VE_ENC(0x14), 0x00),// lfir_coef6 512 _RV1(H_BK_VE_ENC(0x14), 0x00), 513 _RV1(L_BK_VE_ENC(0x15), 0x00),// lfir_coef7 514 _RV1(H_BK_VE_ENC(0x15), 0x00), 515 _RV1(L_BK_VE_ENC(0x16), 0x00),// lfir_coef8 516 _RV1(H_BK_VE_ENC(0x16), 0x00), 517 _RV1(L_BK_VE_ENC(0x17), 0x00),// lfir_coef9 518 _RV1(H_BK_VE_ENC(0x17), 0x00), 519 _RV1(L_BK_VE_ENC(0x18), 0x00),// lfir_coef10 520 _RV1(H_BK_VE_ENC(0x18), 0x00), 521 _RV1(L_BK_VE_ENC(0x19), 0x00),// lfir_coef11 522 _RV1(H_BK_VE_ENC(0x19), 0x08), 523 _RV1(L_BK_VE_ENC(0x1A), 0x00),// cfir_coef1 524 _RV1(H_BK_VE_ENC(0x1A), 0x00), 525 _RV1(L_BK_VE_ENC(0x1B), 0x00),// cfir_coef2 526 _RV1(H_BK_VE_ENC(0x1B), 0x00), 527 _RV1(L_BK_VE_ENC(0x1C), 0x00),// cfir_coef3 528 _RV1(H_BK_VE_ENC(0x1C), 0x00), 529 _RV1(L_BK_VE_ENC(0x1D), 0x00),// cfir_coef4 530 _RV1(H_BK_VE_ENC(0x1D), 0x00), 531 _RV1(L_BK_VE_ENC(0x1E), 0x00),// cfir_coef5 532 _RV1(H_BK_VE_ENC(0x1E), 0x00), 533 _RV1(L_BK_VE_ENC(0x1F), 0x00),// cfir_coef6 534 _RV1(H_BK_VE_ENC(0x1F), 0x00), 535 _RV1(L_BK_VE_ENC(0x20), 0x00),// cfir_coef7 536 _RV1(H_BK_VE_ENC(0x20), 0x00), 537 _RV1(L_BK_VE_ENC(0x21), 0x00),// cfir_coef7 538 _RV1(H_BK_VE_ENC(0x21), 0x00), 539 _RV1(L_BK_VE_ENC(0x22), 0x00),// cfir_coef9 540 _RV1(H_BK_VE_ENC(0x22), 0x00), 541 _RV1(L_BK_VE_ENC(0x23), 0x00),// cfir_coef10 542 _RV1(H_BK_VE_ENC(0x23), 0x00), 543 _RV1(L_BK_VE_ENC(0x24), 0x00),// cfir_coef11 544 _RV1(H_BK_VE_ENC(0x24), 0x04),*/ 545 _END_OF_TBL2_ 546 }; 547 548 MS_U8 tVE_VBI_NTSC_TBL[] = 549 { 550 _RV1(L_BK_VE_ENC(0x2E), 0x00),// VBI mode 551 _RV1(H_BK_VE_ENC(0x2E), 0x00), 552 _RV1(L_BK_VE_ENC(0x4E), 0x15),// ccvbi_st1 553 _RV1(H_BK_VE_ENC(0x4E), 0x00), 554 _RV1(L_BK_VE_ENC(0x4F), 0x15),// ccvbi_end1 555 _RV1(H_BK_VE_ENC(0x4F), 0x00), 556 _RV1(L_BK_VE_ENC(0x50), 0x1C),// ccvbi_st2 557 _RV1(H_BK_VE_ENC(0x50), 0x01), 558 _RV1(L_BK_VE_ENC(0x51), 0x1C),// ccvbi_end2 559 _RV1(H_BK_VE_ENC(0x51), 0x01), 560 _RV1(L_BK_VE_ENC(0x56), 0x14),// wssvbi_st1 561 _RV1(H_BK_VE_ENC(0x56), 0x00), 562 _RV1(L_BK_VE_ENC(0x57), 0x14),// wssvbi_end1 563 _RV1(H_BK_VE_ENC(0x57), 0x00), 564 _RV1(L_BK_VE_ENC(0x6C), 0x1B),// wssvbi_st2 565 _RV1(H_BK_VE_ENC(0x6C), 0x01), 566 _RV1(L_BK_VE_ENC(0x6D), 0x1B),// wssvbi_end2 567 _RV1(H_BK_VE_ENC(0x6D), 0x01), 568 _RV1(L_BK_VE_ENC(0x5C), 0xD6),// cc_phs_step [15:0] 569 _RV1(H_BK_VE_ENC(0x5C), 0x1D), 570 _RV1(L_BK_VE_ENC(0x5D), 0xC6),// cc_phs_step [31:16] 571 _RV1(H_BK_VE_ENC(0x5D), 0x04), 572 _RV1(L_BK_VE_ENC(0x60), 0x84),// wws_phs_step [15:0] 573 _RV1(H_BK_VE_ENC(0x60), 0x0F), 574 _RV1(L_BK_VE_ENC(0x61), 0x3E),// wws_phs_step [31:16] 575 _RV1(H_BK_VE_ENC(0x61), 0x04), 576 _RV1(L_BK_VE_ENC(0x64), 0x10),// cc_st 577 _RV1(H_BK_VE_ENC(0x64), 0x01), 578 _RV1(L_BK_VE_ENC(0x66), 0x2E),// wws_st 579 _RV1(H_BK_VE_ENC(0x66), 0x01), 580 _RV1(L_BK_VE_ENC(0x68), 0x18),// cc_lvl 581 _RV1(H_BK_VE_ENC(0x68), 0x01), 582 _RV1(L_BK_VE_ENC(0x6A), 0x90),// wws_lvl 583 _RV1(H_BK_VE_ENC(0x6A), 0x01), 584 585 _END_OF_TBL2_ 586 }; 587 588 MS_U8 tVE_VBI_PAL_TBL[] = 589 { 590 // TELETEXT 591 _RV1(L_BK_VE_ENC(0x2E), 0x88),// vbi mode 592 593 _RV1(H_BK_VE_ENC(0x2E), 0x00), 594 _RV1(L_BK_VE_ENC(0x52), 0x10),// vpsvib_st1 595 _RV1(H_BK_VE_ENC(0x52), 0x00), 596 _RV1(L_BK_VE_ENC(0x53), 0x10),// vpsvib_end1 597 _RV1(H_BK_VE_ENC(0x53), 0x00), 598 _RV1(L_BK_VE_ENC(0x54), 0x1C),// vpsvib_st2 599 _RV1(H_BK_VE_ENC(0x54), 0x01), 600 _RV1(L_BK_VE_ENC(0x55), 0x1B),// vpsvib_end2 601 _RV1(H_BK_VE_ENC(0x55), 0x01), 602 _RV1(L_BK_VE_ENC(0x56), 0x17),// wssvbi_st1 603 _RV1(H_BK_VE_ENC(0x56), 0x00), 604 _RV1(L_BK_VE_ENC(0x57), 0x17),// wssvbi_end1 605 _RV1(H_BK_VE_ENC(0x57), 0x00), 606 _RV1(L_BK_VE_ENC(0x6C), 0x1C),// wssvbi_st2 607 _RV1(H_BK_VE_ENC(0x6C), 0x01), 608 _RV1(L_BK_VE_ENC(0x6D), 0x1B),// wssvbi_end2 609 _RV1(H_BK_VE_ENC(0x6D), 0x01), 610 _RV1(L_BK_VE_ENC(0x58), 0x07),// ttvbi_st1 611 _RV1(H_BK_VE_ENC(0x58), 0x00), 612 _RV1(L_BK_VE_ENC(0x59), 0x16),// ttvbi_end1 613 _RV1(H_BK_VE_ENC(0x59), 0x00), 614 _RV1(L_BK_VE_ENC(0x5A), 0x3F),// ttvbi_st2 615 _RV1(H_BK_VE_ENC(0x5A), 0x01), 616 _RV1(L_BK_VE_ENC(0x5B), 0x4F),// ttvbi_end2 617 _RV1(H_BK_VE_ENC(0x5B), 0x01), 618 _RV1(L_BK_VE_ENC(0x5E), 0xDA),// vps_phs_step[15:0] 619 _RV1(H_BK_VE_ENC(0x5E), 0x4B), 620 _RV1(L_BK_VE_ENC(0x5F), 0x68),// vps_phs_step[31:16] 621 _RV1(H_BK_VE_ENC(0x5F), 0x2F), 622 _RV1(L_BK_VE_ENC(0x60), 0xDA),// wws_phs_step[15:0] 623 _RV1(H_BK_VE_ENC(0x60), 0x4B), 624 _RV1(L_BK_VE_ENC(0x61), 0x68),// wws_phs_step[31:16] 625 _RV1(H_BK_VE_ENC(0x61), 0x2F), 626 _RV1(L_BK_VE_ENC(0x62), 0x71),// tt_phs_step[15:0] 627 _RV1(H_BK_VE_ENC(0x62), 0x1C), 628 _RV1(L_BK_VE_ENC(0x63), 0xC7),// tt_phs_step[31:16] 629 _RV1(H_BK_VE_ENC(0x63), 0x41), 630 _RV1(L_BK_VE_ENC(0x65), 0x53),// vps_st 631 _RV1(H_BK_VE_ENC(0x65), 0x01), 632 _RV1(L_BK_VE_ENC(0x66), 0x30),// wws_st 633 _RV1(H_BK_VE_ENC(0x66), 0x01), 634 _RV1(L_BK_VE_ENC(0x67), 0x15),// tt_st 635 _RV1(H_BK_VE_ENC(0x67), 0x01), 636 _RV1(L_BK_VE_ENC(0x69), 0x90),// vps_lvl 637 _RV1(H_BK_VE_ENC(0x69), 0x01), 638 _RV1(L_BK_VE_ENC(0x6A), 0x90),// wws_lvl 639 _RV1(H_BK_VE_ENC(0x6A), 0x01), 640 _RV1(L_BK_VE_ENC(0x6B), 0x90),// tt_lvl 641 _RV1(H_BK_VE_ENC(0x6B), 0x01), 642 _RV1(H_BK_VE_ENC(0x3D), 0x00), 643 _END_OF_TBL2_ 644 }; 645 646 MS_U8 tVE_CCIROUT_NTSC_TBL[] = 647 { 648 _RV1(L_BK_VE_SRC(0x47), 0x0D),// frame line number 649 _RV1(H_BK_VE_SRC(0x47), 0x02), 650 _RV1(L_BK_VE_SRC(0x48), 0x01),// F0 blank star 651 _RV1(H_BK_VE_SRC(0x48), 0x00), 652 _RV1(L_BK_VE_SRC(0x49), 0x17),// F0 blank end 653 _RV1(H_BK_VE_SRC(0x49), 0x00), 654 _RV1(L_BK_VE_SRC(0x4A), 0x07),// F1 blank start 655 _RV1(H_BK_VE_SRC(0x4A), 0x01), 656 _RV1(L_BK_VE_SRC(0x4B), 0x1E),// F1 blank end 657 _RV1(H_BK_VE_SRC(0x4B), 0x01), 658 _RV1(L_BK_VE_SRC(0x4C), 0x04),// F0 start 659 _RV1(H_BK_VE_SRC(0x4C), 0x00), 660 _RV1(L_BK_VE_SRC(0x4D), 0x0A),// F0 end 661 _RV1(H_BK_VE_SRC(0x4D), 0x01), 662 _RV1(L_BK_VE_SRC(0x4E), 0x01),// F0 V start 663 _RV1(H_BK_VE_SRC(0x4E), 0x00), 664 _RV1(L_BK_VE_SRC(0x4F), 0x14),// F0 V end 665 _RV1(H_BK_VE_SRC(0x4F), 0x00), 666 _RV1(L_BK_VE_SRC(0x50), 0x08),// F1 V start 667 _RV1(H_BK_VE_SRC(0x50), 0x01), 668 _RV1(L_BK_VE_SRC(0x51), 0x1B),// F1 V end 669 _RV1(H_BK_VE_SRC(0x51), 0x01), 670 _END_OF_TBL2_, 671 }; 672 673 MS_U8 tVE_CCIROUT_PAL_TBL[] = 674 { 675 _RV1(L_BK_VE_SRC(0x47), 0x71),// frame line number 676 _RV1(H_BK_VE_SRC(0x47), 0x02), 677 _RV1(L_BK_VE_SRC(0x48), 0x01),// F0 blank star 678 _RV1(H_BK_VE_SRC(0x48), 0x00), 679 _RV1(L_BK_VE_SRC(0x49), 0x19),// F0 blank end 680 _RV1(H_BK_VE_SRC(0x49), 0x00), 681 _RV1(L_BK_VE_SRC(0x4A), 0x39),// F1 blank start 682 _RV1(H_BK_VE_SRC(0x4A), 0x01), 683 _RV1(L_BK_VE_SRC(0x4B), 0x52),// F1 blank end 684 _RV1(H_BK_VE_SRC(0x4B), 0x01), 685 _RV1(L_BK_VE_SRC(0x4C), 0x02),// F0 start 686 _RV1(H_BK_VE_SRC(0x4C), 0x00), 687 _RV1(L_BK_VE_SRC(0x4D), 0x3A),// F0 end 688 _RV1(H_BK_VE_SRC(0x4D), 0x01), 689 _RV1(L_BK_VE_SRC(0x4E), 0x07),// F0 V start 690 _RV1(H_BK_VE_SRC(0x4E), 0x01), 691 _RV1(L_BK_VE_SRC(0x4F), 0x18),// F0 V end 692 _RV1(H_BK_VE_SRC(0x4F), 0x00), 693 _RV1(L_BK_VE_SRC(0x50), 0x38),// F1 V start 694 _RV1(H_BK_VE_SRC(0x50), 0x01), 695 _RV1(L_BK_VE_SRC(0x51), 0x51),// F1 V end 696 _RV1(H_BK_VE_SRC(0x51), 0x01), 697 _END_OF_TBL2_, 698 }; 699 700 701 MS_VE_Out_VideoSYS VE_OUT_VIDEOSTD_TBL[MS_VE_VIDEOSYS_NUM] = 702 { // Reg Tbl Coef_TBL VBI TBL vtotal_525, bPALSwitch, bPALOut 703 /*NSTC */ {tVE_ENCODER_NTSC_TBL, tVE_COEF_NTSC_TBL, tVE_VBI_NTSC_TBL, 0, 0, 0}, 704 /*NSTC_443*/ {tVE_ENCODER_NTSC_443_TBL, tVE_COEF_NTSC_TBL, tVE_VBI_NTSC_TBL, 0, 0, 0}, 705 /*NSTC_J*/ {tVE_ENCODER_NTSC_J_TBL, tVE_COEF_NTSC_TBL, tVE_VBI_NTSC_TBL, 0, 0, 0}, 706 /*PAL_M*/ {tVE_ENCODER_PAL_M_TBL, tVE_COEF_PAL_TBL, tVE_VBI_NTSC_TBL, 0, 1, 1}, 707 /*PAL_N*/ {tVE_ENCODER_PAL_N_TBL, tVE_COEF_PAL_TBL, tVE_VBI_PAL_TBL, 1, 1, 1}, 708 /*PAL_NC*/ {tVE_ENCODER_PAL_NC_TBL, tVE_COEF_PAL_TBL, tVE_VBI_PAL_TBL, 1, 1, 1}, 709 /*PAL_B*/ {tVE_ENCODER_PAL_TBL, tVE_COEF_PAL_TBL, tVE_VBI_PAL_TBL, 1, 1, 1}, 710 /*SECAM*/ {NULL, NULL, NULL, 1, 1, 1}, 711 }; 712 713 714 715