1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //**************************************************** 96 // MACROVISION Drive Chip : Uranus4_Macrovision_Driver 97 // MACROVISION Excel CodeGen Version: 1.04 98 // MACROVISION Excel SW Version: 1.1 99 // MACROVISION Excel update date : 2013/9/17 11:39 100 //**************************************************** 101 102 #ifndef _DRVMACROVISION_TBL_H_ 103 #define _DRVMACROVISION_TBL_H_ 104 105 #ifdef __cplusplus 106 extern "C" 107 { 108 #endif 109 110 #define DRV_MACROVISION_REG(reg) ((reg>>8)&0xFF), (reg&0xFF) 111 #define REG_ADDR_SIZE 2 112 #define REG_MASK_SIZE 1 113 #define REG_TABLE_END 0xFFFF 114 115 #define _PK_L_(bank, addr) ((MS_U16)(bank << 8) | (addr)) 116 #define _PK_H_(bank, addr) ((MS_U16)((bank|0x80) << 8) | (addr)) 117 118 #define REG_TC_VE_SRC_BASE 0x3B00 119 #define REG_TC_VE_ENC1_BASE 0x3E00 120 #define REG_TC_VE_ENC2_BASE 0x3F00 121 122 typedef enum 123 { 124 MACROVISION_TABTYPE_MACROVISION, 125 } E_MACROVISION_TAB_TYPE; 126 127 typedef struct 128 { 129 MS_U8 *pVeMACROVISIONTab; 130 E_MACROVISION_TAB_TYPE eMACROVISIONtype; 131 } MACROVISION_TAB_INFO; 132 133 typedef enum 134 { 135 MACROVISION_TYPE_MACROVISION_NTSC_TYPE1, 136 MACROVISION_TYPE_MACROVISION_NTSC_TYPE2, 137 MACROVISION_TYPE_MACROVISION_NTSC_TYPE3, 138 MACROVISION_TYPE_MACROVISION_NTSC_TEST_N01, 139 MACROVISION_TYPE_MACROVISION_NTSC_TEST_N02, 140 MACROVISION_TYPE_MACROVISION_NTSC_TYPE2_TTX, 141 MACROVISION_TYPE_MACROVISION_NTSC_TEST_N01_TTX, 142 MACROVISION_TYPE_MACROVISION_PAL_TYPE1_2_3, 143 MACROVISION_TYPE_MACROVISION_PAL_TEST_P01, 144 MACROVISION_TYPE_MACROVISION_PAL_TEST_P02, 145 MACROVISION_TYPE_MACROVISION_PAL_TYPE1_2_3_TTX, 146 MACROVISION_TYPE_MACROVISION_PAL_TEST_P01_TTX, 147 MACROVISION_TYPE_NUMS, 148 } E_MACROVISION_TYPE_INDEX; 149 150 extern MACROVISION_TAB_INFO MACROVISIONMAP_Main[MACROVISION_TYPE_NUMS]; 151 152 typedef enum 153 { 154 VE_TAB_MACROVISION_NTSC_TYPE1_MACROVISION_ALL, 155 VE_TAB_MACROVISION_NTSC_TYPE1_MACROVISION_NUMS 156 } E_VE_MACROVISION_NTSC_TYPE1_MACROVISION_TYPE; 157 158 typedef enum 159 { 160 VE_TAB_MACROVISION_NTSC_TYPE2_MACROVISION_ALL, 161 VE_TAB_MACROVISION_NTSC_TYPE2_MACROVISION_NUMS 162 } E_VE_MACROVISION_NTSC_TYPE2_MACROVISION_TYPE; 163 164 typedef enum 165 { 166 VE_TAB_MACROVISION_NTSC_TYPE3_MACROVISION_ALL, 167 VE_TAB_MACROVISION_NTSC_TYPE3_MACROVISION_NUMS 168 } E_VE_MACROVISION_NTSC_TYPE3_MACROVISION_TYPE; 169 170 typedef enum 171 { 172 VE_TAB_MACROVISION_NTSC_TEST_N01_MACROVISION_ALL, 173 VE_TAB_MACROVISION_NTSC_TEST_N01_MACROVISION_NUMS 174 } E_VE_MACROVISION_NTSC_TEST_N01_MACROVISION_TYPE; 175 176 typedef enum 177 { 178 VE_TAB_MACROVISION_NTSC_TEST_N02_MACROVISION_ALL, 179 VE_TAB_MACROVISION_NTSC_TEST_N02_MACROVISION_NUMS 180 } E_VE_MACROVISION_NTSC_TEST_N02_MACROVISION_TYPE; 181 182 typedef enum 183 { 184 VE_TAB_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_ALL, 185 VE_TAB_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_NUMS 186 } E_VE_MACROVISION_NTSC_TYPE2_TTX_MACROVISION_TYPE; 187 188 typedef enum 189 { 190 VE_TAB_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_ALL, 191 VE_TAB_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_NUMS 192 } E_VE_MACROVISION_NTSC_TEST_N01_TTX_MACROVISION_TYPE; 193 194 typedef enum 195 { 196 VE_TAB_MACROVISION_PAL_TYPE1_2_3_MACROVISION_ALL, 197 VE_TAB_MACROVISION_PAL_TYPE1_2_3_MACROVISION_NUMS 198 } E_VE_MACROVISION_PAL_TYPE1_2_3_MACROVISION_TYPE; 199 200 typedef enum 201 { 202 VE_TAB_MACROVISION_PAL_TEST_P01_MACROVISION_ALL, 203 VE_TAB_MACROVISION_PAL_TEST_P01_MACROVISION_NUMS 204 } E_VE_MACROVISION_PAL_TEST_P01_MACROVISION_TYPE; 205 206 typedef enum 207 { 208 VE_TAB_MACROVISION_PAL_TEST_P02_MACROVISION_ALL, 209 VE_TAB_MACROVISION_PAL_TEST_P02_MACROVISION_NUMS 210 } E_VE_MACROVISION_PAL_TEST_P02_MACROVISION_TYPE; 211 212 typedef enum 213 { 214 VE_TAB_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_ALL, 215 VE_TAB_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_NUMS 216 } E_VE_MACROVISION_PAL_TYPE1_2_3_TTX_MACROVISION_TYPE; 217 218 typedef enum 219 { 220 VE_TAB_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_ALL, 221 VE_TAB_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_NUMS 222 } E_VE_MACROVISION_PAL_TEST_P01_TTX_MACROVISION_TYPE; 223 224 //------------------------------------------------------------------------------------------------- 225 // register define used for TCON table 226 //------------------------------------------------------------------------------------------------- 227 228 #define REG_TC_VE_SRC_00_L (REG_TC_VE_SRC_BASE + 0x00) 229 #define REG_TC_VE_SRC_00_H (REG_TC_VE_SRC_BASE + 0x01) 230 #define REG_TC_VE_SRC_01_L (REG_TC_VE_SRC_BASE + 0x02) 231 #define REG_TC_VE_SRC_01_H (REG_TC_VE_SRC_BASE + 0x03) 232 #define REG_TC_VE_SRC_02_L (REG_TC_VE_SRC_BASE + 0x04) 233 #define REG_TC_VE_SRC_02_H (REG_TC_VE_SRC_BASE + 0x05) 234 #define REG_TC_VE_SRC_03_L (REG_TC_VE_SRC_BASE + 0x06) 235 #define REG_TC_VE_SRC_03_H (REG_TC_VE_SRC_BASE + 0x07) 236 #define REG_TC_VE_SRC_04_L (REG_TC_VE_SRC_BASE + 0x08) 237 #define REG_TC_VE_SRC_04_H (REG_TC_VE_SRC_BASE + 0x09) 238 #define REG_TC_VE_SRC_05_L (REG_TC_VE_SRC_BASE + 0x0A) 239 #define REG_TC_VE_SRC_05_H (REG_TC_VE_SRC_BASE + 0x0B) 240 #define REG_TC_VE_SRC_06_L (REG_TC_VE_SRC_BASE + 0x0C) 241 #define REG_TC_VE_SRC_06_H (REG_TC_VE_SRC_BASE + 0x0D) 242 #define REG_TC_VE_SRC_07_L (REG_TC_VE_SRC_BASE + 0x0E) 243 #define REG_TC_VE_SRC_07_H (REG_TC_VE_SRC_BASE + 0x0F) 244 #define REG_TC_VE_SRC_08_L (REG_TC_VE_SRC_BASE + 0x10) 245 #define REG_TC_VE_SRC_08_H (REG_TC_VE_SRC_BASE + 0x11) 246 #define REG_TC_VE_SRC_09_L (REG_TC_VE_SRC_BASE + 0x12) 247 #define REG_TC_VE_SRC_09_H (REG_TC_VE_SRC_BASE + 0x13) 248 #define REG_TC_VE_SRC_0A_L (REG_TC_VE_SRC_BASE + 0x14) 249 #define REG_TC_VE_SRC_0A_H (REG_TC_VE_SRC_BASE + 0x15) 250 #define REG_TC_VE_SRC_0B_L (REG_TC_VE_SRC_BASE + 0x16) 251 #define REG_TC_VE_SRC_0B_H (REG_TC_VE_SRC_BASE + 0x17) 252 #define REG_TC_VE_SRC_0C_L (REG_TC_VE_SRC_BASE + 0x18) 253 #define REG_TC_VE_SRC_0C_H (REG_TC_VE_SRC_BASE + 0x19) 254 #define REG_TC_VE_SRC_0D_L (REG_TC_VE_SRC_BASE + 0x1A) 255 #define REG_TC_VE_SRC_0D_H (REG_TC_VE_SRC_BASE + 0x1B) 256 #define REG_TC_VE_SRC_0E_L (REG_TC_VE_SRC_BASE + 0x1C) 257 #define REG_TC_VE_SRC_0E_H (REG_TC_VE_SRC_BASE + 0x1D) 258 #define REG_TC_VE_SRC_0F_L (REG_TC_VE_SRC_BASE + 0x1E) 259 #define REG_TC_VE_SRC_0F_H (REG_TC_VE_SRC_BASE + 0x1F) 260 #define REG_TC_VE_SRC_10_L (REG_TC_VE_SRC_BASE + 0x20) 261 #define REG_TC_VE_SRC_10_H (REG_TC_VE_SRC_BASE + 0x21) 262 #define REG_TC_VE_SRC_11_L (REG_TC_VE_SRC_BASE + 0x22) 263 #define REG_TC_VE_SRC_11_H (REG_TC_VE_SRC_BASE + 0x23) 264 #define REG_TC_VE_SRC_12_L (REG_TC_VE_SRC_BASE + 0x24) 265 #define REG_TC_VE_SRC_12_H (REG_TC_VE_SRC_BASE + 0x25) 266 #define REG_TC_VE_SRC_13_L (REG_TC_VE_SRC_BASE + 0x26) 267 #define REG_TC_VE_SRC_13_H (REG_TC_VE_SRC_BASE + 0x27) 268 #define REG_TC_VE_SRC_14_L (REG_TC_VE_SRC_BASE + 0x28) 269 #define REG_TC_VE_SRC_14_H (REG_TC_VE_SRC_BASE + 0x29) 270 #define REG_TC_VE_SRC_15_L (REG_TC_VE_SRC_BASE + 0x2A) 271 #define REG_TC_VE_SRC_15_H (REG_TC_VE_SRC_BASE + 0x2B) 272 #define REG_TC_VE_SRC_16_L (REG_TC_VE_SRC_BASE + 0x2C) 273 #define REG_TC_VE_SRC_16_H (REG_TC_VE_SRC_BASE + 0x2D) 274 #define REG_TC_VE_SRC_17_L (REG_TC_VE_SRC_BASE + 0x2E) 275 #define REG_TC_VE_SRC_17_H (REG_TC_VE_SRC_BASE + 0x2F) 276 #define REG_TC_VE_SRC_18_L (REG_TC_VE_SRC_BASE + 0x30) 277 #define REG_TC_VE_SRC_18_H (REG_TC_VE_SRC_BASE + 0x31) 278 #define REG_TC_VE_SRC_19_L (REG_TC_VE_SRC_BASE + 0x32) 279 #define REG_TC_VE_SRC_19_H (REG_TC_VE_SRC_BASE + 0x33) 280 #define REG_TC_VE_SRC_1A_L (REG_TC_VE_SRC_BASE + 0x34) 281 #define REG_TC_VE_SRC_1A_H (REG_TC_VE_SRC_BASE + 0x35) 282 #define REG_TC_VE_SRC_1B_L (REG_TC_VE_SRC_BASE + 0x36) 283 #define REG_TC_VE_SRC_1B_H (REG_TC_VE_SRC_BASE + 0x37) 284 #define REG_TC_VE_SRC_1C_L (REG_TC_VE_SRC_BASE + 0x38) 285 #define REG_TC_VE_SRC_1C_H (REG_TC_VE_SRC_BASE + 0x39) 286 #define REG_TC_VE_SRC_1D_L (REG_TC_VE_SRC_BASE + 0x3A) 287 #define REG_TC_VE_SRC_1D_H (REG_TC_VE_SRC_BASE + 0x3B) 288 #define REG_TC_VE_SRC_1E_L (REG_TC_VE_SRC_BASE + 0x3C) 289 #define REG_TC_VE_SRC_1E_H (REG_TC_VE_SRC_BASE + 0x3D) 290 #define REG_TC_VE_SRC_1F_L (REG_TC_VE_SRC_BASE + 0x3E) 291 #define REG_TC_VE_SRC_1F_H (REG_TC_VE_SRC_BASE + 0x3F) 292 #define REG_TC_VE_SRC_20_L (REG_TC_VE_SRC_BASE + 0x40) 293 #define REG_TC_VE_SRC_20_H (REG_TC_VE_SRC_BASE + 0x41) 294 #define REG_TC_VE_SRC_21_L (REG_TC_VE_SRC_BASE + 0x42) 295 #define REG_TC_VE_SRC_21_H (REG_TC_VE_SRC_BASE + 0x43) 296 #define REG_TC_VE_SRC_22_L (REG_TC_VE_SRC_BASE + 0x44) 297 #define REG_TC_VE_SRC_22_H (REG_TC_VE_SRC_BASE + 0x45) 298 #define REG_TC_VE_SRC_23_L (REG_TC_VE_SRC_BASE + 0x46) 299 #define REG_TC_VE_SRC_23_H (REG_TC_VE_SRC_BASE + 0x47) 300 #define REG_TC_VE_SRC_24_L (REG_TC_VE_SRC_BASE + 0x48) 301 #define REG_TC_VE_SRC_24_H (REG_TC_VE_SRC_BASE + 0x49) 302 #define REG_TC_VE_SRC_25_L (REG_TC_VE_SRC_BASE + 0x4A) 303 #define REG_TC_VE_SRC_25_H (REG_TC_VE_SRC_BASE + 0x4B) 304 #define REG_TC_VE_SRC_26_L (REG_TC_VE_SRC_BASE + 0x4C) 305 #define REG_TC_VE_SRC_26_H (REG_TC_VE_SRC_BASE + 0x4D) 306 #define REG_TC_VE_SRC_27_L (REG_TC_VE_SRC_BASE + 0x4E) 307 #define REG_TC_VE_SRC_27_H (REG_TC_VE_SRC_BASE + 0x4F) 308 #define REG_TC_VE_SRC_28_L (REG_TC_VE_SRC_BASE + 0x50) 309 #define REG_TC_VE_SRC_28_H (REG_TC_VE_SRC_BASE + 0x51) 310 #define REG_TC_VE_SRC_29_L (REG_TC_VE_SRC_BASE + 0x52) 311 #define REG_TC_VE_SRC_29_H (REG_TC_VE_SRC_BASE + 0x53) 312 #define REG_TC_VE_SRC_2A_L (REG_TC_VE_SRC_BASE + 0x54) 313 #define REG_TC_VE_SRC_2A_H (REG_TC_VE_SRC_BASE + 0x55) 314 #define REG_TC_VE_SRC_2B_L (REG_TC_VE_SRC_BASE + 0x56) 315 #define REG_TC_VE_SRC_2B_H (REG_TC_VE_SRC_BASE + 0x57) 316 #define REG_TC_VE_SRC_2C_L (REG_TC_VE_SRC_BASE + 0x58) 317 #define REG_TC_VE_SRC_2C_H (REG_TC_VE_SRC_BASE + 0x59) 318 #define REG_TC_VE_SRC_2D_L (REG_TC_VE_SRC_BASE + 0x5A) 319 #define REG_TC_VE_SRC_2D_H (REG_TC_VE_SRC_BASE + 0x5B) 320 #define REG_TC_VE_SRC_2E_L (REG_TC_VE_SRC_BASE + 0x5C) 321 #define REG_TC_VE_SRC_2E_H (REG_TC_VE_SRC_BASE + 0x5D) 322 #define REG_TC_VE_SRC_2F_L (REG_TC_VE_SRC_BASE + 0x5E) 323 #define REG_TC_VE_SRC_2F_H (REG_TC_VE_SRC_BASE + 0x5F) 324 #define REG_TC_VE_SRC_30_L (REG_TC_VE_SRC_BASE + 0x60) 325 #define REG_TC_VE_SRC_30_H (REG_TC_VE_SRC_BASE + 0x61) 326 #define REG_TC_VE_SRC_31_L (REG_TC_VE_SRC_BASE + 0x62) 327 #define REG_TC_VE_SRC_31_H (REG_TC_VE_SRC_BASE + 0x63) 328 #define REG_TC_VE_SRC_32_L (REG_TC_VE_SRC_BASE + 0x64) 329 #define REG_TC_VE_SRC_32_H (REG_TC_VE_SRC_BASE + 0x65) 330 #define REG_TC_VE_SRC_33_L (REG_TC_VE_SRC_BASE + 0x66) 331 #define REG_TC_VE_SRC_33_H (REG_TC_VE_SRC_BASE + 0x67) 332 #define REG_TC_VE_SRC_34_L (REG_TC_VE_SRC_BASE + 0x68) 333 #define REG_TC_VE_SRC_34_H (REG_TC_VE_SRC_BASE + 0x69) 334 #define REG_TC_VE_SRC_35_L (REG_TC_VE_SRC_BASE + 0x6A) 335 #define REG_TC_VE_SRC_35_H (REG_TC_VE_SRC_BASE + 0x6B) 336 #define REG_TC_VE_SRC_36_L (REG_TC_VE_SRC_BASE + 0x6C) 337 #define REG_TC_VE_SRC_36_H (REG_TC_VE_SRC_BASE + 0x6D) 338 #define REG_TC_VE_SRC_37_L (REG_TC_VE_SRC_BASE + 0x6E) 339 #define REG_TC_VE_SRC_37_H (REG_TC_VE_SRC_BASE + 0x6F) 340 #define REG_TC_VE_SRC_38_L (REG_TC_VE_SRC_BASE + 0x70) 341 #define REG_TC_VE_SRC_38_H (REG_TC_VE_SRC_BASE + 0x71) 342 #define REG_TC_VE_SRC_39_L (REG_TC_VE_SRC_BASE + 0x72) 343 #define REG_TC_VE_SRC_39_H (REG_TC_VE_SRC_BASE + 0x73) 344 #define REG_TC_VE_SRC_3A_L (REG_TC_VE_SRC_BASE + 0x74) 345 #define REG_TC_VE_SRC_3A_H (REG_TC_VE_SRC_BASE + 0x75) 346 #define REG_TC_VE_SRC_3B_L (REG_TC_VE_SRC_BASE + 0x76) 347 #define REG_TC_VE_SRC_3B_H (REG_TC_VE_SRC_BASE + 0x77) 348 #define REG_TC_VE_SRC_3C_L (REG_TC_VE_SRC_BASE + 0x78) 349 #define REG_TC_VE_SRC_3C_H (REG_TC_VE_SRC_BASE + 0x79) 350 #define REG_TC_VE_SRC_3D_L (REG_TC_VE_SRC_BASE + 0x7A) 351 #define REG_TC_VE_SRC_3D_H (REG_TC_VE_SRC_BASE + 0x7B) 352 #define REG_TC_VE_SRC_3E_L (REG_TC_VE_SRC_BASE + 0x7C) 353 #define REG_TC_VE_SRC_3E_H (REG_TC_VE_SRC_BASE + 0x7D) 354 #define REG_TC_VE_SRC_3F_L (REG_TC_VE_SRC_BASE + 0x7E) 355 #define REG_TC_VE_SRC_3F_H (REG_TC_VE_SRC_BASE + 0x7F) 356 #define REG_TC_VE_SRC_40_L (REG_TC_VE_SRC_BASE + 0x80) 357 #define REG_TC_VE_SRC_40_H (REG_TC_VE_SRC_BASE + 0x81) 358 #define REG_TC_VE_SRC_41_L (REG_TC_VE_SRC_BASE + 0x82) 359 #define REG_TC_VE_SRC_41_H (REG_TC_VE_SRC_BASE + 0x83) 360 #define REG_TC_VE_SRC_42_L (REG_TC_VE_SRC_BASE + 0x84) 361 #define REG_TC_VE_SRC_42_H (REG_TC_VE_SRC_BASE + 0x85) 362 #define REG_TC_VE_SRC_43_L (REG_TC_VE_SRC_BASE + 0x86) 363 #define REG_TC_VE_SRC_43_H (REG_TC_VE_SRC_BASE + 0x87) 364 #define REG_TC_VE_SRC_44_L (REG_TC_VE_SRC_BASE + 0x88) 365 #define REG_TC_VE_SRC_44_H (REG_TC_VE_SRC_BASE + 0x89) 366 #define REG_TC_VE_SRC_45_L (REG_TC_VE_SRC_BASE + 0x8A) 367 #define REG_TC_VE_SRC_45_H (REG_TC_VE_SRC_BASE + 0x8B) 368 #define REG_TC_VE_SRC_46_L (REG_TC_VE_SRC_BASE + 0x8C) 369 #define REG_TC_VE_SRC_46_H (REG_TC_VE_SRC_BASE + 0x8D) 370 #define REG_TC_VE_SRC_47_L (REG_TC_VE_SRC_BASE + 0x8E) 371 #define REG_TC_VE_SRC_47_H (REG_TC_VE_SRC_BASE + 0x8F) 372 #define REG_TC_VE_SRC_48_L (REG_TC_VE_SRC_BASE + 0x90) 373 #define REG_TC_VE_SRC_48_H (REG_TC_VE_SRC_BASE + 0x91) 374 #define REG_TC_VE_SRC_49_L (REG_TC_VE_SRC_BASE + 0x92) 375 #define REG_TC_VE_SRC_49_H (REG_TC_VE_SRC_BASE + 0x93) 376 #define REG_TC_VE_SRC_4A_L (REG_TC_VE_SRC_BASE + 0x94) 377 #define REG_TC_VE_SRC_4A_H (REG_TC_VE_SRC_BASE + 0x95) 378 #define REG_TC_VE_SRC_4B_L (REG_TC_VE_SRC_BASE + 0x96) 379 #define REG_TC_VE_SRC_4B_H (REG_TC_VE_SRC_BASE + 0x97) 380 #define REG_TC_VE_SRC_4C_L (REG_TC_VE_SRC_BASE + 0x98) 381 #define REG_TC_VE_SRC_4C_H (REG_TC_VE_SRC_BASE + 0x99) 382 #define REG_TC_VE_SRC_4D_L (REG_TC_VE_SRC_BASE + 0x9A) 383 #define REG_TC_VE_SRC_4D_H (REG_TC_VE_SRC_BASE + 0x9B) 384 #define REG_TC_VE_SRC_4E_L (REG_TC_VE_SRC_BASE + 0x9C) 385 #define REG_TC_VE_SRC_4E_H (REG_TC_VE_SRC_BASE + 0x9D) 386 #define REG_TC_VE_SRC_4F_L (REG_TC_VE_SRC_BASE + 0x9E) 387 #define REG_TC_VE_SRC_4F_H (REG_TC_VE_SRC_BASE + 0x9F) 388 #define REG_TC_VE_SRC_50_L (REG_TC_VE_SRC_BASE + 0xA0) 389 #define REG_TC_VE_SRC_50_H (REG_TC_VE_SRC_BASE + 0xA1) 390 #define REG_TC_VE_SRC_51_L (REG_TC_VE_SRC_BASE + 0xA2) 391 #define REG_TC_VE_SRC_51_H (REG_TC_VE_SRC_BASE + 0xA3) 392 #define REG_TC_VE_SRC_52_L (REG_TC_VE_SRC_BASE + 0xA4) 393 #define REG_TC_VE_SRC_52_H (REG_TC_VE_SRC_BASE + 0xA5) 394 #define REG_TC_VE_SRC_53_L (REG_TC_VE_SRC_BASE + 0xA6) 395 #define REG_TC_VE_SRC_53_H (REG_TC_VE_SRC_BASE + 0xA7) 396 #define REG_TC_VE_SRC_54_L (REG_TC_VE_SRC_BASE + 0xA8) 397 #define REG_TC_VE_SRC_54_H (REG_TC_VE_SRC_BASE + 0xA9) 398 #define REG_TC_VE_SRC_55_L (REG_TC_VE_SRC_BASE + 0xAA) 399 #define REG_TC_VE_SRC_55_H (REG_TC_VE_SRC_BASE + 0xAB) 400 #define REG_TC_VE_SRC_56_L (REG_TC_VE_SRC_BASE + 0xAC) 401 #define REG_TC_VE_SRC_56_H (REG_TC_VE_SRC_BASE + 0xAD) 402 #define REG_TC_VE_SRC_57_L (REG_TC_VE_SRC_BASE + 0xAE) 403 #define REG_TC_VE_SRC_57_H (REG_TC_VE_SRC_BASE + 0xAF) 404 #define REG_TC_VE_SRC_58_L (REG_TC_VE_SRC_BASE + 0xB0) 405 #define REG_TC_VE_SRC_58_H (REG_TC_VE_SRC_BASE + 0xB1) 406 #define REG_TC_VE_SRC_59_L (REG_TC_VE_SRC_BASE + 0xB2) 407 #define REG_TC_VE_SRC_59_H (REG_TC_VE_SRC_BASE + 0xB3) 408 #define REG_TC_VE_SRC_5A_L (REG_TC_VE_SRC_BASE + 0xB4) 409 #define REG_TC_VE_SRC_5A_H (REG_TC_VE_SRC_BASE + 0xB5) 410 #define REG_TC_VE_SRC_5B_L (REG_TC_VE_SRC_BASE + 0xB6) 411 #define REG_TC_VE_SRC_5B_H (REG_TC_VE_SRC_BASE + 0xB7) 412 #define REG_TC_VE_SRC_5C_L (REG_TC_VE_SRC_BASE + 0xB8) 413 #define REG_TC_VE_SRC_5C_H (REG_TC_VE_SRC_BASE + 0xB9) 414 #define REG_TC_VE_SRC_5D_L (REG_TC_VE_SRC_BASE + 0xBA) 415 #define REG_TC_VE_SRC_5D_H (REG_TC_VE_SRC_BASE + 0xBB) 416 #define REG_TC_VE_SRC_5E_L (REG_TC_VE_SRC_BASE + 0xBC) 417 #define REG_TC_VE_SRC_5E_H (REG_TC_VE_SRC_BASE + 0xBD) 418 #define REG_TC_VE_SRC_5F_L (REG_TC_VE_SRC_BASE + 0xBE) 419 #define REG_TC_VE_SRC_5F_H (REG_TC_VE_SRC_BASE + 0xBF) 420 #define REG_TC_VE_SRC_60_L (REG_TC_VE_SRC_BASE + 0xC0) 421 #define REG_TC_VE_SRC_60_H (REG_TC_VE_SRC_BASE + 0xC1) 422 #define REG_TC_VE_SRC_61_L (REG_TC_VE_SRC_BASE + 0xC2) 423 #define REG_TC_VE_SRC_61_H (REG_TC_VE_SRC_BASE + 0xC3) 424 #define REG_TC_VE_SRC_62_L (REG_TC_VE_SRC_BASE + 0xC4) 425 #define REG_TC_VE_SRC_62_H (REG_TC_VE_SRC_BASE + 0xC5) 426 #define REG_TC_VE_SRC_63_L (REG_TC_VE_SRC_BASE + 0xC6) 427 #define REG_TC_VE_SRC_63_H (REG_TC_VE_SRC_BASE + 0xC7) 428 #define REG_TC_VE_SRC_64_L (REG_TC_VE_SRC_BASE + 0xC8) 429 #define REG_TC_VE_SRC_64_H (REG_TC_VE_SRC_BASE + 0xC9) 430 #define REG_TC_VE_SRC_65_L (REG_TC_VE_SRC_BASE + 0xCA) 431 #define REG_TC_VE_SRC_65_H (REG_TC_VE_SRC_BASE + 0xCB) 432 #define REG_TC_VE_SRC_66_L (REG_TC_VE_SRC_BASE + 0xCC) 433 #define REG_TC_VE_SRC_66_H (REG_TC_VE_SRC_BASE + 0xCD) 434 #define REG_TC_VE_SRC_67_L (REG_TC_VE_SRC_BASE + 0xCE) 435 #define REG_TC_VE_SRC_67_H (REG_TC_VE_SRC_BASE + 0xCF) 436 #define REG_TC_VE_SRC_68_L (REG_TC_VE_SRC_BASE + 0xD0) 437 #define REG_TC_VE_SRC_68_H (REG_TC_VE_SRC_BASE + 0xD1) 438 #define REG_TC_VE_SRC_69_L (REG_TC_VE_SRC_BASE + 0xD2) 439 #define REG_TC_VE_SRC_69_H (REG_TC_VE_SRC_BASE + 0xD3) 440 #define REG_TC_VE_SRC_6A_L (REG_TC_VE_SRC_BASE + 0xD4) 441 #define REG_TC_VE_SRC_6A_H (REG_TC_VE_SRC_BASE + 0xD5) 442 #define REG_TC_VE_SRC_6B_L (REG_TC_VE_SRC_BASE + 0xD6) 443 #define REG_TC_VE_SRC_6B_H (REG_TC_VE_SRC_BASE + 0xD7) 444 #define REG_TC_VE_SRC_6C_L (REG_TC_VE_SRC_BASE + 0xD8) 445 #define REG_TC_VE_SRC_6C_H (REG_TC_VE_SRC_BASE + 0xD9) 446 #define REG_TC_VE_SRC_6D_L (REG_TC_VE_SRC_BASE + 0xDA) 447 #define REG_TC_VE_SRC_6D_H (REG_TC_VE_SRC_BASE + 0xDB) 448 #define REG_TC_VE_SRC_6E_L (REG_TC_VE_SRC_BASE + 0xDC) 449 #define REG_TC_VE_SRC_6E_H (REG_TC_VE_SRC_BASE + 0xDD) 450 #define REG_TC_VE_SRC_6F_L (REG_TC_VE_SRC_BASE + 0xDE) 451 #define REG_TC_VE_SRC_6F_H (REG_TC_VE_SRC_BASE + 0xDF) 452 #define REG_TC_VE_SRC_70_L (REG_TC_VE_SRC_BASE + 0xE0) 453 #define REG_TC_VE_SRC_70_H (REG_TC_VE_SRC_BASE + 0xE1) 454 #define REG_TC_VE_SRC_71_L (REG_TC_VE_SRC_BASE + 0xE2) 455 #define REG_TC_VE_SRC_71_H (REG_TC_VE_SRC_BASE + 0xE3) 456 #define REG_TC_VE_SRC_72_L (REG_TC_VE_SRC_BASE + 0xE4) 457 #define REG_TC_VE_SRC_72_H (REG_TC_VE_SRC_BASE + 0xE5) 458 #define REG_TC_VE_SRC_73_L (REG_TC_VE_SRC_BASE + 0xE6) 459 #define REG_TC_VE_SRC_73_H (REG_TC_VE_SRC_BASE + 0xE7) 460 #define REG_TC_VE_SRC_74_L (REG_TC_VE_SRC_BASE + 0xE8) 461 #define REG_TC_VE_SRC_74_H (REG_TC_VE_SRC_BASE + 0xE9) 462 #define REG_TC_VE_SRC_75_L (REG_TC_VE_SRC_BASE + 0xEA) 463 #define REG_TC_VE_SRC_75_H (REG_TC_VE_SRC_BASE + 0xEB) 464 #define REG_TC_VE_SRC_76_L (REG_TC_VE_SRC_BASE + 0xEC) 465 #define REG_TC_VE_SRC_76_H (REG_TC_VE_SRC_BASE + 0xED) 466 #define REG_TC_VE_SRC_77_L (REG_TC_VE_SRC_BASE + 0xEE) 467 #define REG_TC_VE_SRC_77_H (REG_TC_VE_SRC_BASE + 0xEF) 468 #define REG_TC_VE_SRC_78_L (REG_TC_VE_SRC_BASE + 0xF0) 469 #define REG_TC_VE_SRC_78_H (REG_TC_VE_SRC_BASE + 0xF1) 470 #define REG_TC_VE_SRC_79_L (REG_TC_VE_SRC_BASE + 0xF2) 471 #define REG_TC_VE_SRC_79_H (REG_TC_VE_SRC_BASE + 0xF3) 472 #define REG_TC_VE_SRC_7A_L (REG_TC_VE_SRC_BASE + 0xF4) 473 #define REG_TC_VE_SRC_7A_H (REG_TC_VE_SRC_BASE + 0xF5) 474 #define REG_TC_VE_SRC_7B_L (REG_TC_VE_SRC_BASE + 0xF6) 475 #define REG_TC_VE_SRC_7B_H (REG_TC_VE_SRC_BASE + 0xF7) 476 #define REG_TC_VE_SRC_7C_L (REG_TC_VE_SRC_BASE + 0xF8) 477 #define REG_TC_VE_SRC_7C_H (REG_TC_VE_SRC_BASE + 0xF9) 478 #define REG_TC_VE_SRC_7D_L (REG_TC_VE_SRC_BASE + 0xFA) 479 #define REG_TC_VE_SRC_7D_H (REG_TC_VE_SRC_BASE + 0xFB) 480 #define REG_TC_VE_SRC_7E_L (REG_TC_VE_SRC_BASE + 0xFC) 481 #define REG_TC_VE_SRC_7E_H (REG_TC_VE_SRC_BASE + 0xFD) 482 #define REG_TC_VE_SRC_7F_L (REG_TC_VE_SRC_BASE + 0xFE) 483 #define REG_TC_VE_SRC_7F_H (REG_TC_VE_SRC_BASE + 0xFF) 484 485 #define REG_TC_VE_ENC1_00_L (REG_TC_VE_ENC1_BASE + 0x00) 486 #define REG_TC_VE_ENC1_00_H (REG_TC_VE_ENC1_BASE + 0x01) 487 #define REG_TC_VE_ENC1_01_L (REG_TC_VE_ENC1_BASE + 0x02) 488 #define REG_TC_VE_ENC1_01_H (REG_TC_VE_ENC1_BASE + 0x03) 489 #define REG_TC_VE_ENC1_02_L (REG_TC_VE_ENC1_BASE + 0x04) 490 #define REG_TC_VE_ENC1_02_H (REG_TC_VE_ENC1_BASE + 0x05) 491 #define REG_TC_VE_ENC1_03_L (REG_TC_VE_ENC1_BASE + 0x06) 492 #define REG_TC_VE_ENC1_03_H (REG_TC_VE_ENC1_BASE + 0x07) 493 #define REG_TC_VE_ENC1_04_L (REG_TC_VE_ENC1_BASE + 0x08) 494 #define REG_TC_VE_ENC1_04_H (REG_TC_VE_ENC1_BASE + 0x09) 495 #define REG_TC_VE_ENC1_05_L (REG_TC_VE_ENC1_BASE + 0x0A) 496 #define REG_TC_VE_ENC1_05_H (REG_TC_VE_ENC1_BASE + 0x0B) 497 #define REG_TC_VE_ENC1_06_L (REG_TC_VE_ENC1_BASE + 0x0C) 498 #define REG_TC_VE_ENC1_06_H (REG_TC_VE_ENC1_BASE + 0x0D) 499 #define REG_TC_VE_ENC1_07_L (REG_TC_VE_ENC1_BASE + 0x0E) 500 #define REG_TC_VE_ENC1_07_H (REG_TC_VE_ENC1_BASE + 0x0F) 501 #define REG_TC_VE_ENC1_08_L (REG_TC_VE_ENC1_BASE + 0x10) 502 #define REG_TC_VE_ENC1_08_H (REG_TC_VE_ENC1_BASE + 0x11) 503 #define REG_TC_VE_ENC1_09_L (REG_TC_VE_ENC1_BASE + 0x12) 504 #define REG_TC_VE_ENC1_09_H (REG_TC_VE_ENC1_BASE + 0x13) 505 #define REG_TC_VE_ENC1_0A_L (REG_TC_VE_ENC1_BASE + 0x14) 506 #define REG_TC_VE_ENC1_0A_H (REG_TC_VE_ENC1_BASE + 0x15) 507 #define REG_TC_VE_ENC1_0B_L (REG_TC_VE_ENC1_BASE + 0x16) 508 #define REG_TC_VE_ENC1_0B_H (REG_TC_VE_ENC1_BASE + 0x17) 509 #define REG_TC_VE_ENC1_0C_L (REG_TC_VE_ENC1_BASE + 0x18) 510 #define REG_TC_VE_ENC1_0C_H (REG_TC_VE_ENC1_BASE + 0x19) 511 #define REG_TC_VE_ENC1_0D_L (REG_TC_VE_ENC1_BASE + 0x1A) 512 #define REG_TC_VE_ENC1_0D_H (REG_TC_VE_ENC1_BASE + 0x1B) 513 #define REG_TC_VE_ENC1_0E_L (REG_TC_VE_ENC1_BASE + 0x1C) 514 #define REG_TC_VE_ENC1_0E_H (REG_TC_VE_ENC1_BASE + 0x1D) 515 #define REG_TC_VE_ENC1_0F_L (REG_TC_VE_ENC1_BASE + 0x1E) 516 #define REG_TC_VE_ENC1_0F_H (REG_TC_VE_ENC1_BASE + 0x1F) 517 #define REG_TC_VE_ENC1_10_L (REG_TC_VE_ENC1_BASE + 0x20) 518 #define REG_TC_VE_ENC1_10_H (REG_TC_VE_ENC1_BASE + 0x21) 519 #define REG_TC_VE_ENC1_11_L (REG_TC_VE_ENC1_BASE + 0x22) 520 #define REG_TC_VE_ENC1_11_H (REG_TC_VE_ENC1_BASE + 0x23) 521 #define REG_TC_VE_ENC1_12_L (REG_TC_VE_ENC1_BASE + 0x24) 522 #define REG_TC_VE_ENC1_12_H (REG_TC_VE_ENC1_BASE + 0x25) 523 #define REG_TC_VE_ENC1_13_L (REG_TC_VE_ENC1_BASE + 0x26) 524 #define REG_TC_VE_ENC1_13_H (REG_TC_VE_ENC1_BASE + 0x27) 525 #define REG_TC_VE_ENC1_14_L (REG_TC_VE_ENC1_BASE + 0x28) 526 #define REG_TC_VE_ENC1_14_H (REG_TC_VE_ENC1_BASE + 0x29) 527 #define REG_TC_VE_ENC1_15_L (REG_TC_VE_ENC1_BASE + 0x2A) 528 #define REG_TC_VE_ENC1_15_H (REG_TC_VE_ENC1_BASE + 0x2B) 529 #define REG_TC_VE_ENC1_16_L (REG_TC_VE_ENC1_BASE + 0x2C) 530 #define REG_TC_VE_ENC1_16_H (REG_TC_VE_ENC1_BASE + 0x2D) 531 #define REG_TC_VE_ENC1_17_L (REG_TC_VE_ENC1_BASE + 0x2E) 532 #define REG_TC_VE_ENC1_17_H (REG_TC_VE_ENC1_BASE + 0x2F) 533 #define REG_TC_VE_ENC1_18_L (REG_TC_VE_ENC1_BASE + 0x30) 534 #define REG_TC_VE_ENC1_18_H (REG_TC_VE_ENC1_BASE + 0x31) 535 #define REG_TC_VE_ENC1_19_L (REG_TC_VE_ENC1_BASE + 0x32) 536 #define REG_TC_VE_ENC1_19_H (REG_TC_VE_ENC1_BASE + 0x33) 537 #define REG_TC_VE_ENC1_1A_L (REG_TC_VE_ENC1_BASE + 0x34) 538 #define REG_TC_VE_ENC1_1A_H (REG_TC_VE_ENC1_BASE + 0x35) 539 #define REG_TC_VE_ENC1_1B_L (REG_TC_VE_ENC1_BASE + 0x36) 540 #define REG_TC_VE_ENC1_1B_H (REG_TC_VE_ENC1_BASE + 0x37) 541 #define REG_TC_VE_ENC1_1C_L (REG_TC_VE_ENC1_BASE + 0x38) 542 #define REG_TC_VE_ENC1_1C_H (REG_TC_VE_ENC1_BASE + 0x39) 543 #define REG_TC_VE_ENC1_1D_L (REG_TC_VE_ENC1_BASE + 0x3A) 544 #define REG_TC_VE_ENC1_1D_H (REG_TC_VE_ENC1_BASE + 0x3B) 545 #define REG_TC_VE_ENC1_1E_L (REG_TC_VE_ENC1_BASE + 0x3C) 546 #define REG_TC_VE_ENC1_1E_H (REG_TC_VE_ENC1_BASE + 0x3D) 547 #define REG_TC_VE_ENC1_1F_L (REG_TC_VE_ENC1_BASE + 0x3E) 548 #define REG_TC_VE_ENC1_1F_H (REG_TC_VE_ENC1_BASE + 0x3F) 549 #define REG_TC_VE_ENC1_20_L (REG_TC_VE_ENC1_BASE + 0x40) 550 #define REG_TC_VE_ENC1_20_H (REG_TC_VE_ENC1_BASE + 0x41) 551 #define REG_TC_VE_ENC1_21_L (REG_TC_VE_ENC1_BASE + 0x42) 552 #define REG_TC_VE_ENC1_21_H (REG_TC_VE_ENC1_BASE + 0x43) 553 #define REG_TC_VE_ENC1_22_L (REG_TC_VE_ENC1_BASE + 0x44) 554 #define REG_TC_VE_ENC1_22_H (REG_TC_VE_ENC1_BASE + 0x45) 555 #define REG_TC_VE_ENC1_23_L (REG_TC_VE_ENC1_BASE + 0x46) 556 #define REG_TC_VE_ENC1_23_H (REG_TC_VE_ENC1_BASE + 0x47) 557 #define REG_TC_VE_ENC1_24_L (REG_TC_VE_ENC1_BASE + 0x48) 558 #define REG_TC_VE_ENC1_24_H (REG_TC_VE_ENC1_BASE + 0x49) 559 #define REG_TC_VE_ENC1_25_L (REG_TC_VE_ENC1_BASE + 0x4A) 560 #define REG_TC_VE_ENC1_25_H (REG_TC_VE_ENC1_BASE + 0x4B) 561 #define REG_TC_VE_ENC1_26_L (REG_TC_VE_ENC1_BASE + 0x4C) 562 #define REG_TC_VE_ENC1_26_H (REG_TC_VE_ENC1_BASE + 0x4D) 563 #define REG_TC_VE_ENC1_27_L (REG_TC_VE_ENC1_BASE + 0x4E) 564 #define REG_TC_VE_ENC1_27_H (REG_TC_VE_ENC1_BASE + 0x4F) 565 #define REG_TC_VE_ENC1_28_L (REG_TC_VE_ENC1_BASE + 0x50) 566 #define REG_TC_VE_ENC1_28_H (REG_TC_VE_ENC1_BASE + 0x51) 567 #define REG_TC_VE_ENC1_29_L (REG_TC_VE_ENC1_BASE + 0x52) 568 #define REG_TC_VE_ENC1_29_H (REG_TC_VE_ENC1_BASE + 0x53) 569 #define REG_TC_VE_ENC1_2A_L (REG_TC_VE_ENC1_BASE + 0x54) 570 #define REG_TC_VE_ENC1_2A_H (REG_TC_VE_ENC1_BASE + 0x55) 571 #define REG_TC_VE_ENC1_2B_L (REG_TC_VE_ENC1_BASE + 0x56) 572 #define REG_TC_VE_ENC1_2B_H (REG_TC_VE_ENC1_BASE + 0x57) 573 #define REG_TC_VE_ENC1_2C_L (REG_TC_VE_ENC1_BASE + 0x58) 574 #define REG_TC_VE_ENC1_2C_H (REG_TC_VE_ENC1_BASE + 0x59) 575 #define REG_TC_VE_ENC1_2D_L (REG_TC_VE_ENC1_BASE + 0x5A) 576 #define REG_TC_VE_ENC1_2D_H (REG_TC_VE_ENC1_BASE + 0x5B) 577 #define REG_TC_VE_ENC1_2E_L (REG_TC_VE_ENC1_BASE + 0x5C) 578 #define REG_TC_VE_ENC1_2E_H (REG_TC_VE_ENC1_BASE + 0x5D) 579 #define REG_TC_VE_ENC1_2F_L (REG_TC_VE_ENC1_BASE + 0x5E) 580 #define REG_TC_VE_ENC1_2F_H (REG_TC_VE_ENC1_BASE + 0x5F) 581 #define REG_TC_VE_ENC1_30_L (REG_TC_VE_ENC1_BASE + 0x60) 582 #define REG_TC_VE_ENC1_30_H (REG_TC_VE_ENC1_BASE + 0x61) 583 #define REG_TC_VE_ENC1_31_L (REG_TC_VE_ENC1_BASE + 0x62) 584 #define REG_TC_VE_ENC1_31_H (REG_TC_VE_ENC1_BASE + 0x63) 585 #define REG_TC_VE_ENC1_32_L (REG_TC_VE_ENC1_BASE + 0x64) 586 #define REG_TC_VE_ENC1_32_H (REG_TC_VE_ENC1_BASE + 0x65) 587 #define REG_TC_VE_ENC1_33_L (REG_TC_VE_ENC1_BASE + 0x66) 588 #define REG_TC_VE_ENC1_33_H (REG_TC_VE_ENC1_BASE + 0x67) 589 #define REG_TC_VE_ENC1_34_L (REG_TC_VE_ENC1_BASE + 0x68) 590 #define REG_TC_VE_ENC1_34_H (REG_TC_VE_ENC1_BASE + 0x69) 591 #define REG_TC_VE_ENC1_35_L (REG_TC_VE_ENC1_BASE + 0x6A) 592 #define REG_TC_VE_ENC1_35_H (REG_TC_VE_ENC1_BASE + 0x6B) 593 #define REG_TC_VE_ENC1_36_L (REG_TC_VE_ENC1_BASE + 0x6C) 594 #define REG_TC_VE_ENC1_36_H (REG_TC_VE_ENC1_BASE + 0x6D) 595 #define REG_TC_VE_ENC1_37_L (REG_TC_VE_ENC1_BASE + 0x6E) 596 #define REG_TC_VE_ENC1_37_H (REG_TC_VE_ENC1_BASE + 0x6F) 597 #define REG_TC_VE_ENC1_38_L (REG_TC_VE_ENC1_BASE + 0x70) 598 #define REG_TC_VE_ENC1_38_H (REG_TC_VE_ENC1_BASE + 0x71) 599 #define REG_TC_VE_ENC1_39_L (REG_TC_VE_ENC1_BASE + 0x72) 600 #define REG_TC_VE_ENC1_39_H (REG_TC_VE_ENC1_BASE + 0x73) 601 #define REG_TC_VE_ENC1_3A_L (REG_TC_VE_ENC1_BASE + 0x74) 602 #define REG_TC_VE_ENC1_3A_H (REG_TC_VE_ENC1_BASE + 0x75) 603 #define REG_TC_VE_ENC1_3B_L (REG_TC_VE_ENC1_BASE + 0x76) 604 #define REG_TC_VE_ENC1_3B_H (REG_TC_VE_ENC1_BASE + 0x77) 605 #define REG_TC_VE_ENC1_3C_L (REG_TC_VE_ENC1_BASE + 0x78) 606 #define REG_TC_VE_ENC1_3C_H (REG_TC_VE_ENC1_BASE + 0x79) 607 #define REG_TC_VE_ENC1_3D_L (REG_TC_VE_ENC1_BASE + 0x7A) 608 #define REG_TC_VE_ENC1_3D_H (REG_TC_VE_ENC1_BASE + 0x7B) 609 #define REG_TC_VE_ENC1_3E_L (REG_TC_VE_ENC1_BASE + 0x7C) 610 #define REG_TC_VE_ENC1_3E_H (REG_TC_VE_ENC1_BASE + 0x7D) 611 #define REG_TC_VE_ENC1_3F_L (REG_TC_VE_ENC1_BASE + 0x7E) 612 #define REG_TC_VE_ENC1_3F_H (REG_TC_VE_ENC1_BASE + 0x7F) 613 #define REG_TC_VE_ENC1_40_L (REG_TC_VE_ENC1_BASE + 0x80) 614 #define REG_TC_VE_ENC1_40_H (REG_TC_VE_ENC1_BASE + 0x81) 615 #define REG_TC_VE_ENC1_41_L (REG_TC_VE_ENC1_BASE + 0x82) 616 #define REG_TC_VE_ENC1_41_H (REG_TC_VE_ENC1_BASE + 0x83) 617 #define REG_TC_VE_ENC1_42_L (REG_TC_VE_ENC1_BASE + 0x84) 618 #define REG_TC_VE_ENC1_42_H (REG_TC_VE_ENC1_BASE + 0x85) 619 #define REG_TC_VE_ENC1_43_L (REG_TC_VE_ENC1_BASE + 0x86) 620 #define REG_TC_VE_ENC1_43_H (REG_TC_VE_ENC1_BASE + 0x87) 621 #define REG_TC_VE_ENC1_44_L (REG_TC_VE_ENC1_BASE + 0x88) 622 #define REG_TC_VE_ENC1_44_H (REG_TC_VE_ENC1_BASE + 0x89) 623 #define REG_TC_VE_ENC1_45_L (REG_TC_VE_ENC1_BASE + 0x8A) 624 #define REG_TC_VE_ENC1_45_H (REG_TC_VE_ENC1_BASE + 0x8B) 625 #define REG_TC_VE_ENC1_46_L (REG_TC_VE_ENC1_BASE + 0x8C) 626 #define REG_TC_VE_ENC1_46_H (REG_TC_VE_ENC1_BASE + 0x8D) 627 #define REG_TC_VE_ENC1_47_L (REG_TC_VE_ENC1_BASE + 0x8E) 628 #define REG_TC_VE_ENC1_47_H (REG_TC_VE_ENC1_BASE + 0x8F) 629 #define REG_TC_VE_ENC1_48_L (REG_TC_VE_ENC1_BASE + 0x90) 630 #define REG_TC_VE_ENC1_48_H (REG_TC_VE_ENC1_BASE + 0x91) 631 #define REG_TC_VE_ENC1_49_L (REG_TC_VE_ENC1_BASE + 0x92) 632 #define REG_TC_VE_ENC1_49_H (REG_TC_VE_ENC1_BASE + 0x93) 633 #define REG_TC_VE_ENC1_4A_L (REG_TC_VE_ENC1_BASE + 0x94) 634 #define REG_TC_VE_ENC1_4A_H (REG_TC_VE_ENC1_BASE + 0x95) 635 #define REG_TC_VE_ENC1_4B_L (REG_TC_VE_ENC1_BASE + 0x96) 636 #define REG_TC_VE_ENC1_4B_H (REG_TC_VE_ENC1_BASE + 0x97) 637 #define REG_TC_VE_ENC1_4C_L (REG_TC_VE_ENC1_BASE + 0x98) 638 #define REG_TC_VE_ENC1_4C_H (REG_TC_VE_ENC1_BASE + 0x99) 639 #define REG_TC_VE_ENC1_4D_L (REG_TC_VE_ENC1_BASE + 0x9A) 640 #define REG_TC_VE_ENC1_4D_H (REG_TC_VE_ENC1_BASE + 0x9B) 641 #define REG_TC_VE_ENC1_4E_L (REG_TC_VE_ENC1_BASE + 0x9C) 642 #define REG_TC_VE_ENC1_4E_H (REG_TC_VE_ENC1_BASE + 0x9D) 643 #define REG_TC_VE_ENC1_4F_L (REG_TC_VE_ENC1_BASE + 0x9E) 644 #define REG_TC_VE_ENC1_4F_H (REG_TC_VE_ENC1_BASE + 0x9F) 645 #define REG_TC_VE_ENC1_50_L (REG_TC_VE_ENC1_BASE + 0xA0) 646 #define REG_TC_VE_ENC1_50_H (REG_TC_VE_ENC1_BASE + 0xA1) 647 #define REG_TC_VE_ENC1_51_L (REG_TC_VE_ENC1_BASE + 0xA2) 648 #define REG_TC_VE_ENC1_51_H (REG_TC_VE_ENC1_BASE + 0xA3) 649 #define REG_TC_VE_ENC1_52_L (REG_TC_VE_ENC1_BASE + 0xA4) 650 #define REG_TC_VE_ENC1_52_H (REG_TC_VE_ENC1_BASE + 0xA5) 651 #define REG_TC_VE_ENC1_53_L (REG_TC_VE_ENC1_BASE + 0xA6) 652 #define REG_TC_VE_ENC1_53_H (REG_TC_VE_ENC1_BASE + 0xA7) 653 #define REG_TC_VE_ENC1_54_L (REG_TC_VE_ENC1_BASE + 0xA8) 654 #define REG_TC_VE_ENC1_54_H (REG_TC_VE_ENC1_BASE + 0xA9) 655 #define REG_TC_VE_ENC1_55_L (REG_TC_VE_ENC1_BASE + 0xAA) 656 #define REG_TC_VE_ENC1_55_H (REG_TC_VE_ENC1_BASE + 0xAB) 657 #define REG_TC_VE_ENC1_56_L (REG_TC_VE_ENC1_BASE + 0xAC) 658 #define REG_TC_VE_ENC1_56_H (REG_TC_VE_ENC1_BASE + 0xAD) 659 #define REG_TC_VE_ENC1_57_L (REG_TC_VE_ENC1_BASE + 0xAE) 660 #define REG_TC_VE_ENC1_57_H (REG_TC_VE_ENC1_BASE + 0xAF) 661 #define REG_TC_VE_ENC1_58_L (REG_TC_VE_ENC1_BASE + 0xB0) 662 #define REG_TC_VE_ENC1_58_H (REG_TC_VE_ENC1_BASE + 0xB1) 663 #define REG_TC_VE_ENC1_59_L (REG_TC_VE_ENC1_BASE + 0xB2) 664 #define REG_TC_VE_ENC1_59_H (REG_TC_VE_ENC1_BASE + 0xB3) 665 #define REG_TC_VE_ENC1_5A_L (REG_TC_VE_ENC1_BASE + 0xB4) 666 #define REG_TC_VE_ENC1_5A_H (REG_TC_VE_ENC1_BASE + 0xB5) 667 #define REG_TC_VE_ENC1_5B_L (REG_TC_VE_ENC1_BASE + 0xB6) 668 #define REG_TC_VE_ENC1_5B_H (REG_TC_VE_ENC1_BASE + 0xB7) 669 #define REG_TC_VE_ENC1_5C_L (REG_TC_VE_ENC1_BASE + 0xB8) 670 #define REG_TC_VE_ENC1_5C_H (REG_TC_VE_ENC1_BASE + 0xB9) 671 #define REG_TC_VE_ENC1_5D_L (REG_TC_VE_ENC1_BASE + 0xBA) 672 #define REG_TC_VE_ENC1_5D_H (REG_TC_VE_ENC1_BASE + 0xBB) 673 #define REG_TC_VE_ENC1_5E_L (REG_TC_VE_ENC1_BASE + 0xBC) 674 #define REG_TC_VE_ENC1_5E_H (REG_TC_VE_ENC1_BASE + 0xBD) 675 #define REG_TC_VE_ENC1_5F_L (REG_TC_VE_ENC1_BASE + 0xBE) 676 #define REG_TC_VE_ENC1_5F_H (REG_TC_VE_ENC1_BASE + 0xBF) 677 #define REG_TC_VE_ENC1_60_L (REG_TC_VE_ENC1_BASE + 0xC0) 678 #define REG_TC_VE_ENC1_60_H (REG_TC_VE_ENC1_BASE + 0xC1) 679 #define REG_TC_VE_ENC1_61_L (REG_TC_VE_ENC1_BASE + 0xC2) 680 #define REG_TC_VE_ENC1_61_H (REG_TC_VE_ENC1_BASE + 0xC3) 681 #define REG_TC_VE_ENC1_62_L (REG_TC_VE_ENC1_BASE + 0xC4) 682 #define REG_TC_VE_ENC1_62_H (REG_TC_VE_ENC1_BASE + 0xC5) 683 #define REG_TC_VE_ENC1_63_L (REG_TC_VE_ENC1_BASE + 0xC6) 684 #define REG_TC_VE_ENC1_63_H (REG_TC_VE_ENC1_BASE + 0xC7) 685 #define REG_TC_VE_ENC1_64_L (REG_TC_VE_ENC1_BASE + 0xC8) 686 #define REG_TC_VE_ENC1_64_H (REG_TC_VE_ENC1_BASE + 0xC9) 687 #define REG_TC_VE_ENC1_65_L (REG_TC_VE_ENC1_BASE + 0xCA) 688 #define REG_TC_VE_ENC1_65_H (REG_TC_VE_ENC1_BASE + 0xCB) 689 #define REG_TC_VE_ENC1_66_L (REG_TC_VE_ENC1_BASE + 0xCC) 690 #define REG_TC_VE_ENC1_66_H (REG_TC_VE_ENC1_BASE + 0xCD) 691 #define REG_TC_VE_ENC1_67_L (REG_TC_VE_ENC1_BASE + 0xCE) 692 #define REG_TC_VE_ENC1_67_H (REG_TC_VE_ENC1_BASE + 0xCF) 693 #define REG_TC_VE_ENC1_68_L (REG_TC_VE_ENC1_BASE + 0xD0) 694 #define REG_TC_VE_ENC1_68_H (REG_TC_VE_ENC1_BASE + 0xD1) 695 #define REG_TC_VE_ENC1_69_L (REG_TC_VE_ENC1_BASE + 0xD2) 696 #define REG_TC_VE_ENC1_69_H (REG_TC_VE_ENC1_BASE + 0xD3) 697 #define REG_TC_VE_ENC1_6A_L (REG_TC_VE_ENC1_BASE + 0xD4) 698 #define REG_TC_VE_ENC1_6A_H (REG_TC_VE_ENC1_BASE + 0xD5) 699 #define REG_TC_VE_ENC1_6B_L (REG_TC_VE_ENC1_BASE + 0xD6) 700 #define REG_TC_VE_ENC1_6B_H (REG_TC_VE_ENC1_BASE + 0xD7) 701 #define REG_TC_VE_ENC1_6C_L (REG_TC_VE_ENC1_BASE + 0xD8) 702 #define REG_TC_VE_ENC1_6C_H (REG_TC_VE_ENC1_BASE + 0xD9) 703 #define REG_TC_VE_ENC1_6D_L (REG_TC_VE_ENC1_BASE + 0xDA) 704 #define REG_TC_VE_ENC1_6D_H (REG_TC_VE_ENC1_BASE + 0xDB) 705 #define REG_TC_VE_ENC1_6E_L (REG_TC_VE_ENC1_BASE + 0xDC) 706 #define REG_TC_VE_ENC1_6E_H (REG_TC_VE_ENC1_BASE + 0xDD) 707 #define REG_TC_VE_ENC1_6F_L (REG_TC_VE_ENC1_BASE + 0xDE) 708 #define REG_TC_VE_ENC1_6F_H (REG_TC_VE_ENC1_BASE + 0xDF) 709 #define REG_TC_VE_ENC1_70_L (REG_TC_VE_ENC1_BASE + 0xE0) 710 #define REG_TC_VE_ENC1_70_H (REG_TC_VE_ENC1_BASE + 0xE1) 711 #define REG_TC_VE_ENC1_71_L (REG_TC_VE_ENC1_BASE + 0xE2) 712 #define REG_TC_VE_ENC1_71_H (REG_TC_VE_ENC1_BASE + 0xE3) 713 #define REG_TC_VE_ENC1_72_L (REG_TC_VE_ENC1_BASE + 0xE4) 714 #define REG_TC_VE_ENC1_72_H (REG_TC_VE_ENC1_BASE + 0xE5) 715 #define REG_TC_VE_ENC1_73_L (REG_TC_VE_ENC1_BASE + 0xE6) 716 #define REG_TC_VE_ENC1_73_H (REG_TC_VE_ENC1_BASE + 0xE7) 717 #define REG_TC_VE_ENC1_74_L (REG_TC_VE_ENC1_BASE + 0xE8) 718 #define REG_TC_VE_ENC1_74_H (REG_TC_VE_ENC1_BASE + 0xE9) 719 #define REG_TC_VE_ENC1_75_L (REG_TC_VE_ENC1_BASE + 0xEA) 720 #define REG_TC_VE_ENC1_75_H (REG_TC_VE_ENC1_BASE + 0xEB) 721 #define REG_TC_VE_ENC1_76_L (REG_TC_VE_ENC1_BASE + 0xEC) 722 #define REG_TC_VE_ENC1_76_H (REG_TC_VE_ENC1_BASE + 0xED) 723 #define REG_TC_VE_ENC1_77_L (REG_TC_VE_ENC1_BASE + 0xEE) 724 #define REG_TC_VE_ENC1_77_H (REG_TC_VE_ENC1_BASE + 0xEF) 725 #define REG_TC_VE_ENC1_78_L (REG_TC_VE_ENC1_BASE + 0xF0) 726 #define REG_TC_VE_ENC1_78_H (REG_TC_VE_ENC1_BASE + 0xF1) 727 #define REG_TC_VE_ENC1_79_L (REG_TC_VE_ENC1_BASE + 0xF2) 728 #define REG_TC_VE_ENC1_79_H (REG_TC_VE_ENC1_BASE + 0xF3) 729 #define REG_TC_VE_ENC1_7A_L (REG_TC_VE_ENC1_BASE + 0xF4) 730 #define REG_TC_VE_ENC1_7A_H (REG_TC_VE_ENC1_BASE + 0xF5) 731 #define REG_TC_VE_ENC1_7B_L (REG_TC_VE_ENC1_BASE + 0xF6) 732 #define REG_TC_VE_ENC1_7B_H (REG_TC_VE_ENC1_BASE + 0xF7) 733 #define REG_TC_VE_ENC1_7C_L (REG_TC_VE_ENC1_BASE + 0xF8) 734 #define REG_TC_VE_ENC1_7C_H (REG_TC_VE_ENC1_BASE + 0xF9) 735 #define REG_TC_VE_ENC1_7D_L (REG_TC_VE_ENC1_BASE + 0xFA) 736 #define REG_TC_VE_ENC1_7D_H (REG_TC_VE_ENC1_BASE + 0xFB) 737 #define REG_TC_VE_ENC1_7E_L (REG_TC_VE_ENC1_BASE + 0xFC) 738 #define REG_TC_VE_ENC1_7E_H (REG_TC_VE_ENC1_BASE + 0xFD) 739 #define REG_TC_VE_ENC1_7F_L (REG_TC_VE_ENC1_BASE + 0xFE) 740 #define REG_TC_VE_ENC1_7F_H (REG_TC_VE_ENC1_BASE + 0xFF) 741 742 #define REG_TC_VE_ENC2_00_L (REG_TC_VE_ENC2_BASE + 0x00) 743 #define REG_TC_VE_ENC2_00_H (REG_TC_VE_ENC2_BASE + 0x01) 744 #define REG_TC_VE_ENC2_01_L (REG_TC_VE_ENC2_BASE + 0x02) 745 #define REG_TC_VE_ENC2_01_H (REG_TC_VE_ENC2_BASE + 0x03) 746 #define REG_TC_VE_ENC2_02_L (REG_TC_VE_ENC2_BASE + 0x04) 747 #define REG_TC_VE_ENC2_02_H (REG_TC_VE_ENC2_BASE + 0x05) 748 #define REG_TC_VE_ENC2_03_L (REG_TC_VE_ENC2_BASE + 0x06) 749 #define REG_TC_VE_ENC2_03_H (REG_TC_VE_ENC2_BASE + 0x07) 750 #define REG_TC_VE_ENC2_04_L (REG_TC_VE_ENC2_BASE + 0x08) 751 #define REG_TC_VE_ENC2_04_H (REG_TC_VE_ENC2_BASE + 0x09) 752 #define REG_TC_VE_ENC2_05_L (REG_TC_VE_ENC2_BASE + 0x0A) 753 #define REG_TC_VE_ENC2_05_H (REG_TC_VE_ENC2_BASE + 0x0B) 754 #define REG_TC_VE_ENC2_06_L (REG_TC_VE_ENC2_BASE + 0x0C) 755 #define REG_TC_VE_ENC2_06_H (REG_TC_VE_ENC2_BASE + 0x0D) 756 #define REG_TC_VE_ENC2_07_L (REG_TC_VE_ENC2_BASE + 0x0E) 757 #define REG_TC_VE_ENC2_07_H (REG_TC_VE_ENC2_BASE + 0x0F) 758 #define REG_TC_VE_ENC2_08_L (REG_TC_VE_ENC2_BASE + 0x10) 759 #define REG_TC_VE_ENC2_08_H (REG_TC_VE_ENC2_BASE + 0x11) 760 #define REG_TC_VE_ENC2_09_L (REG_TC_VE_ENC2_BASE + 0x12) 761 #define REG_TC_VE_ENC2_09_H (REG_TC_VE_ENC2_BASE + 0x13) 762 #define REG_TC_VE_ENC2_0A_L (REG_TC_VE_ENC2_BASE + 0x14) 763 #define REG_TC_VE_ENC2_0A_H (REG_TC_VE_ENC2_BASE + 0x15) 764 #define REG_TC_VE_ENC2_0B_L (REG_TC_VE_ENC2_BASE + 0x16) 765 #define REG_TC_VE_ENC2_0B_H (REG_TC_VE_ENC2_BASE + 0x17) 766 #define REG_TC_VE_ENC2_0C_L (REG_TC_VE_ENC2_BASE + 0x18) 767 #define REG_TC_VE_ENC2_0C_H (REG_TC_VE_ENC2_BASE + 0x19) 768 #define REG_TC_VE_ENC2_0D_L (REG_TC_VE_ENC2_BASE + 0x1A) 769 #define REG_TC_VE_ENC2_0D_H (REG_TC_VE_ENC2_BASE + 0x1B) 770 #define REG_TC_VE_ENC2_0E_L (REG_TC_VE_ENC2_BASE + 0x1C) 771 #define REG_TC_VE_ENC2_0E_H (REG_TC_VE_ENC2_BASE + 0x1D) 772 #define REG_TC_VE_ENC2_0F_L (REG_TC_VE_ENC2_BASE + 0x1E) 773 #define REG_TC_VE_ENC2_0F_H (REG_TC_VE_ENC2_BASE + 0x1F) 774 #define REG_TC_VE_ENC2_10_L (REG_TC_VE_ENC2_BASE + 0x20) 775 #define REG_TC_VE_ENC2_10_H (REG_TC_VE_ENC2_BASE + 0x21) 776 #define REG_TC_VE_ENC2_11_L (REG_TC_VE_ENC2_BASE + 0x22) 777 #define REG_TC_VE_ENC2_11_H (REG_TC_VE_ENC2_BASE + 0x23) 778 #define REG_TC_VE_ENC2_12_L (REG_TC_VE_ENC2_BASE + 0x24) 779 #define REG_TC_VE_ENC2_12_H (REG_TC_VE_ENC2_BASE + 0x25) 780 #define REG_TC_VE_ENC2_13_L (REG_TC_VE_ENC2_BASE + 0x26) 781 #define REG_TC_VE_ENC2_13_H (REG_TC_VE_ENC2_BASE + 0x27) 782 #define REG_TC_VE_ENC2_14_L (REG_TC_VE_ENC2_BASE + 0x28) 783 #define REG_TC_VE_ENC2_14_H (REG_TC_VE_ENC2_BASE + 0x29) 784 #define REG_TC_VE_ENC2_15_L (REG_TC_VE_ENC2_BASE + 0x2A) 785 #define REG_TC_VE_ENC2_15_H (REG_TC_VE_ENC2_BASE + 0x2B) 786 #define REG_TC_VE_ENC2_16_L (REG_TC_VE_ENC2_BASE + 0x2C) 787 #define REG_TC_VE_ENC2_16_H (REG_TC_VE_ENC2_BASE + 0x2D) 788 #define REG_TC_VE_ENC2_17_L (REG_TC_VE_ENC2_BASE + 0x2E) 789 #define REG_TC_VE_ENC2_17_H (REG_TC_VE_ENC2_BASE + 0x2F) 790 #define REG_TC_VE_ENC2_18_L (REG_TC_VE_ENC2_BASE + 0x30) 791 #define REG_TC_VE_ENC2_18_H (REG_TC_VE_ENC2_BASE + 0x31) 792 #define REG_TC_VE_ENC2_19_L (REG_TC_VE_ENC2_BASE + 0x32) 793 #define REG_TC_VE_ENC2_19_H (REG_TC_VE_ENC2_BASE + 0x33) 794 #define REG_TC_VE_ENC2_1A_L (REG_TC_VE_ENC2_BASE + 0x34) 795 #define REG_TC_VE_ENC2_1A_H (REG_TC_VE_ENC2_BASE + 0x35) 796 #define REG_TC_VE_ENC2_1B_L (REG_TC_VE_ENC2_BASE + 0x36) 797 #define REG_TC_VE_ENC2_1B_H (REG_TC_VE_ENC2_BASE + 0x37) 798 #define REG_TC_VE_ENC2_1C_L (REG_TC_VE_ENC2_BASE + 0x38) 799 #define REG_TC_VE_ENC2_1C_H (REG_TC_VE_ENC2_BASE + 0x39) 800 #define REG_TC_VE_ENC2_1D_L (REG_TC_VE_ENC2_BASE + 0x3A) 801 #define REG_TC_VE_ENC2_1D_H (REG_TC_VE_ENC2_BASE + 0x3B) 802 #define REG_TC_VE_ENC2_1E_L (REG_TC_VE_ENC2_BASE + 0x3C) 803 #define REG_TC_VE_ENC2_1E_H (REG_TC_VE_ENC2_BASE + 0x3D) 804 #define REG_TC_VE_ENC2_1F_L (REG_TC_VE_ENC2_BASE + 0x3E) 805 #define REG_TC_VE_ENC2_1F_H (REG_TC_VE_ENC2_BASE + 0x3F) 806 #define REG_TC_VE_ENC2_20_L (REG_TC_VE_ENC2_BASE + 0x40) 807 #define REG_TC_VE_ENC2_20_H (REG_TC_VE_ENC2_BASE + 0x41) 808 #define REG_TC_VE_ENC2_21_L (REG_TC_VE_ENC2_BASE + 0x42) 809 #define REG_TC_VE_ENC2_21_H (REG_TC_VE_ENC2_BASE + 0x43) 810 #define REG_TC_VE_ENC2_22_L (REG_TC_VE_ENC2_BASE + 0x44) 811 #define REG_TC_VE_ENC2_22_H (REG_TC_VE_ENC2_BASE + 0x45) 812 #define REG_TC_VE_ENC2_23_L (REG_TC_VE_ENC2_BASE + 0x46) 813 #define REG_TC_VE_ENC2_23_H (REG_TC_VE_ENC2_BASE + 0x47) 814 #define REG_TC_VE_ENC2_24_L (REG_TC_VE_ENC2_BASE + 0x48) 815 #define REG_TC_VE_ENC2_24_H (REG_TC_VE_ENC2_BASE + 0x49) 816 #define REG_TC_VE_ENC2_25_L (REG_TC_VE_ENC2_BASE + 0x4A) 817 #define REG_TC_VE_ENC2_25_H (REG_TC_VE_ENC2_BASE + 0x4B) 818 #define REG_TC_VE_ENC2_26_L (REG_TC_VE_ENC2_BASE + 0x4C) 819 #define REG_TC_VE_ENC2_26_H (REG_TC_VE_ENC2_BASE + 0x4D) 820 #define REG_TC_VE_ENC2_27_L (REG_TC_VE_ENC2_BASE + 0x4E) 821 #define REG_TC_VE_ENC2_27_H (REG_TC_VE_ENC2_BASE + 0x4F) 822 #define REG_TC_VE_ENC2_28_L (REG_TC_VE_ENC2_BASE + 0x50) 823 #define REG_TC_VE_ENC2_28_H (REG_TC_VE_ENC2_BASE + 0x51) 824 #define REG_TC_VE_ENC2_29_L (REG_TC_VE_ENC2_BASE + 0x52) 825 #define REG_TC_VE_ENC2_29_H (REG_TC_VE_ENC2_BASE + 0x53) 826 #define REG_TC_VE_ENC2_2A_L (REG_TC_VE_ENC2_BASE + 0x54) 827 #define REG_TC_VE_ENC2_2A_H (REG_TC_VE_ENC2_BASE + 0x55) 828 #define REG_TC_VE_ENC2_2B_L (REG_TC_VE_ENC2_BASE + 0x56) 829 #define REG_TC_VE_ENC2_2B_H (REG_TC_VE_ENC2_BASE + 0x57) 830 #define REG_TC_VE_ENC2_2C_L (REG_TC_VE_ENC2_BASE + 0x58) 831 #define REG_TC_VE_ENC2_2C_H (REG_TC_VE_ENC2_BASE + 0x59) 832 #define REG_TC_VE_ENC2_2D_L (REG_TC_VE_ENC2_BASE + 0x5A) 833 #define REG_TC_VE_ENC2_2D_H (REG_TC_VE_ENC2_BASE + 0x5B) 834 #define REG_TC_VE_ENC2_2E_L (REG_TC_VE_ENC2_BASE + 0x5C) 835 #define REG_TC_VE_ENC2_2E_H (REG_TC_VE_ENC2_BASE + 0x5D) 836 #define REG_TC_VE_ENC2_2F_L (REG_TC_VE_ENC2_BASE + 0x5E) 837 #define REG_TC_VE_ENC2_2F_H (REG_TC_VE_ENC2_BASE + 0x5F) 838 #define REG_TC_VE_ENC2_30_L (REG_TC_VE_ENC2_BASE + 0x60) 839 #define REG_TC_VE_ENC2_30_H (REG_TC_VE_ENC2_BASE + 0x61) 840 #define REG_TC_VE_ENC2_31_L (REG_TC_VE_ENC2_BASE + 0x62) 841 #define REG_TC_VE_ENC2_31_H (REG_TC_VE_ENC2_BASE + 0x63) 842 #define REG_TC_VE_ENC2_32_L (REG_TC_VE_ENC2_BASE + 0x64) 843 #define REG_TC_VE_ENC2_32_H (REG_TC_VE_ENC2_BASE + 0x65) 844 #define REG_TC_VE_ENC2_33_L (REG_TC_VE_ENC2_BASE + 0x66) 845 #define REG_TC_VE_ENC2_33_H (REG_TC_VE_ENC2_BASE + 0x67) 846 #define REG_TC_VE_ENC2_34_L (REG_TC_VE_ENC2_BASE + 0x68) 847 #define REG_TC_VE_ENC2_34_H (REG_TC_VE_ENC2_BASE + 0x69) 848 #define REG_TC_VE_ENC2_35_L (REG_TC_VE_ENC2_BASE + 0x6A) 849 #define REG_TC_VE_ENC2_35_H (REG_TC_VE_ENC2_BASE + 0x6B) 850 #define REG_TC_VE_ENC2_36_L (REG_TC_VE_ENC2_BASE + 0x6C) 851 #define REG_TC_VE_ENC2_36_H (REG_TC_VE_ENC2_BASE + 0x6D) 852 #define REG_TC_VE_ENC2_37_L (REG_TC_VE_ENC2_BASE + 0x6E) 853 #define REG_TC_VE_ENC2_37_H (REG_TC_VE_ENC2_BASE + 0x6F) 854 #define REG_TC_VE_ENC2_38_L (REG_TC_VE_ENC2_BASE + 0x70) 855 #define REG_TC_VE_ENC2_38_H (REG_TC_VE_ENC2_BASE + 0x71) 856 #define REG_TC_VE_ENC2_39_L (REG_TC_VE_ENC2_BASE + 0x72) 857 #define REG_TC_VE_ENC2_39_H (REG_TC_VE_ENC2_BASE + 0x73) 858 #define REG_TC_VE_ENC2_3A_L (REG_TC_VE_ENC2_BASE + 0x74) 859 #define REG_TC_VE_ENC2_3A_H (REG_TC_VE_ENC2_BASE + 0x75) 860 #define REG_TC_VE_ENC2_3B_L (REG_TC_VE_ENC2_BASE + 0x76) 861 #define REG_TC_VE_ENC2_3B_H (REG_TC_VE_ENC2_BASE + 0x77) 862 #define REG_TC_VE_ENC2_3C_L (REG_TC_VE_ENC2_BASE + 0x78) 863 #define REG_TC_VE_ENC2_3C_H (REG_TC_VE_ENC2_BASE + 0x79) 864 #define REG_TC_VE_ENC2_3D_L (REG_TC_VE_ENC2_BASE + 0x7A) 865 #define REG_TC_VE_ENC2_3D_H (REG_TC_VE_ENC2_BASE + 0x7B) 866 #define REG_TC_VE_ENC2_3E_L (REG_TC_VE_ENC2_BASE + 0x7C) 867 #define REG_TC_VE_ENC2_3E_H (REG_TC_VE_ENC2_BASE + 0x7D) 868 #define REG_TC_VE_ENC2_3F_L (REG_TC_VE_ENC2_BASE + 0x7E) 869 #define REG_TC_VE_ENC2_3F_H (REG_TC_VE_ENC2_BASE + 0x7F) 870 #define REG_TC_VE_ENC2_40_L (REG_TC_VE_ENC2_BASE + 0x80) 871 #define REG_TC_VE_ENC2_40_H (REG_TC_VE_ENC2_BASE + 0x81) 872 #define REG_TC_VE_ENC2_41_L (REG_TC_VE_ENC2_BASE + 0x82) 873 #define REG_TC_VE_ENC2_41_H (REG_TC_VE_ENC2_BASE + 0x83) 874 #define REG_TC_VE_ENC2_42_L (REG_TC_VE_ENC2_BASE + 0x84) 875 #define REG_TC_VE_ENC2_42_H (REG_TC_VE_ENC2_BASE + 0x85) 876 #define REG_TC_VE_ENC2_43_L (REG_TC_VE_ENC2_BASE + 0x86) 877 #define REG_TC_VE_ENC2_43_H (REG_TC_VE_ENC2_BASE + 0x87) 878 #define REG_TC_VE_ENC2_44_L (REG_TC_VE_ENC2_BASE + 0x88) 879 #define REG_TC_VE_ENC2_44_H (REG_TC_VE_ENC2_BASE + 0x89) 880 #define REG_TC_VE_ENC2_45_L (REG_TC_VE_ENC2_BASE + 0x8A) 881 #define REG_TC_VE_ENC2_45_H (REG_TC_VE_ENC2_BASE + 0x8B) 882 #define REG_TC_VE_ENC2_46_L (REG_TC_VE_ENC2_BASE + 0x8C) 883 #define REG_TC_VE_ENC2_46_H (REG_TC_VE_ENC2_BASE + 0x8D) 884 #define REG_TC_VE_ENC2_47_L (REG_TC_VE_ENC2_BASE + 0x8E) 885 #define REG_TC_VE_ENC2_47_H (REG_TC_VE_ENC2_BASE + 0x8F) 886 #define REG_TC_VE_ENC2_48_L (REG_TC_VE_ENC2_BASE + 0x90) 887 #define REG_TC_VE_ENC2_48_H (REG_TC_VE_ENC2_BASE + 0x91) 888 #define REG_TC_VE_ENC2_49_L (REG_TC_VE_ENC2_BASE + 0x92) 889 #define REG_TC_VE_ENC2_49_H (REG_TC_VE_ENC2_BASE + 0x93) 890 #define REG_TC_VE_ENC2_4A_L (REG_TC_VE_ENC2_BASE + 0x94) 891 #define REG_TC_VE_ENC2_4A_H (REG_TC_VE_ENC2_BASE + 0x95) 892 #define REG_TC_VE_ENC2_4B_L (REG_TC_VE_ENC2_BASE + 0x96) 893 #define REG_TC_VE_ENC2_4B_H (REG_TC_VE_ENC2_BASE + 0x97) 894 #define REG_TC_VE_ENC2_4C_L (REG_TC_VE_ENC2_BASE + 0x98) 895 #define REG_TC_VE_ENC2_4C_H (REG_TC_VE_ENC2_BASE + 0x99) 896 #define REG_TC_VE_ENC2_4D_L (REG_TC_VE_ENC2_BASE + 0x9A) 897 #define REG_TC_VE_ENC2_4D_H (REG_TC_VE_ENC2_BASE + 0x9B) 898 #define REG_TC_VE_ENC2_4E_L (REG_TC_VE_ENC2_BASE + 0x9C) 899 #define REG_TC_VE_ENC2_4E_H (REG_TC_VE_ENC2_BASE + 0x9D) 900 #define REG_TC_VE_ENC2_4F_L (REG_TC_VE_ENC2_BASE + 0x9E) 901 #define REG_TC_VE_ENC2_4F_H (REG_TC_VE_ENC2_BASE + 0x9F) 902 #define REG_TC_VE_ENC2_50_L (REG_TC_VE_ENC2_BASE + 0xA0) 903 #define REG_TC_VE_ENC2_50_H (REG_TC_VE_ENC2_BASE + 0xA1) 904 #define REG_TC_VE_ENC2_51_L (REG_TC_VE_ENC2_BASE + 0xA2) 905 #define REG_TC_VE_ENC2_51_H (REG_TC_VE_ENC2_BASE + 0xA3) 906 #define REG_TC_VE_ENC2_52_L (REG_TC_VE_ENC2_BASE + 0xA4) 907 #define REG_TC_VE_ENC2_52_H (REG_TC_VE_ENC2_BASE + 0xA5) 908 #define REG_TC_VE_ENC2_53_L (REG_TC_VE_ENC2_BASE + 0xA6) 909 #define REG_TC_VE_ENC2_53_H (REG_TC_VE_ENC2_BASE + 0xA7) 910 #define REG_TC_VE_ENC2_54_L (REG_TC_VE_ENC2_BASE + 0xA8) 911 #define REG_TC_VE_ENC2_54_H (REG_TC_VE_ENC2_BASE + 0xA9) 912 #define REG_TC_VE_ENC2_55_L (REG_TC_VE_ENC2_BASE + 0xAA) 913 #define REG_TC_VE_ENC2_55_H (REG_TC_VE_ENC2_BASE + 0xAB) 914 #define REG_TC_VE_ENC2_56_L (REG_TC_VE_ENC2_BASE + 0xAC) 915 #define REG_TC_VE_ENC2_56_H (REG_TC_VE_ENC2_BASE + 0xAD) 916 #define REG_TC_VE_ENC2_57_L (REG_TC_VE_ENC2_BASE + 0xAE) 917 #define REG_TC_VE_ENC2_57_H (REG_TC_VE_ENC2_BASE + 0xAF) 918 #define REG_TC_VE_ENC2_58_L (REG_TC_VE_ENC2_BASE + 0xB0) 919 #define REG_TC_VE_ENC2_58_H (REG_TC_VE_ENC2_BASE + 0xB1) 920 #define REG_TC_VE_ENC2_59_L (REG_TC_VE_ENC2_BASE + 0xB2) 921 #define REG_TC_VE_ENC2_59_H (REG_TC_VE_ENC2_BASE + 0xB3) 922 #define REG_TC_VE_ENC2_5A_L (REG_TC_VE_ENC2_BASE + 0xB4) 923 #define REG_TC_VE_ENC2_5A_H (REG_TC_VE_ENC2_BASE + 0xB5) 924 #define REG_TC_VE_ENC2_5B_L (REG_TC_VE_ENC2_BASE + 0xB6) 925 #define REG_TC_VE_ENC2_5B_H (REG_TC_VE_ENC2_BASE + 0xB7) 926 #define REG_TC_VE_ENC2_5C_L (REG_TC_VE_ENC2_BASE + 0xB8) 927 #define REG_TC_VE_ENC2_5C_H (REG_TC_VE_ENC2_BASE + 0xB9) 928 #define REG_TC_VE_ENC2_5D_L (REG_TC_VE_ENC2_BASE + 0xBA) 929 #define REG_TC_VE_ENC2_5D_H (REG_TC_VE_ENC2_BASE + 0xBB) 930 #define REG_TC_VE_ENC2_5E_L (REG_TC_VE_ENC2_BASE + 0xBC) 931 #define REG_TC_VE_ENC2_5E_H (REG_TC_VE_ENC2_BASE + 0xBD) 932 #define REG_TC_VE_ENC2_5F_L (REG_TC_VE_ENC2_BASE + 0xBE) 933 #define REG_TC_VE_ENC2_5F_H (REG_TC_VE_ENC2_BASE + 0xBF) 934 #define REG_TC_VE_ENC2_60_L (REG_TC_VE_ENC2_BASE + 0xC0) 935 #define REG_TC_VE_ENC2_60_H (REG_TC_VE_ENC2_BASE + 0xC1) 936 #define REG_TC_VE_ENC2_61_L (REG_TC_VE_ENC2_BASE + 0xC2) 937 #define REG_TC_VE_ENC2_61_H (REG_TC_VE_ENC2_BASE + 0xC3) 938 #define REG_TC_VE_ENC2_62_L (REG_TC_VE_ENC2_BASE + 0xC4) 939 #define REG_TC_VE_ENC2_62_H (REG_TC_VE_ENC2_BASE + 0xC5) 940 #define REG_TC_VE_ENC2_63_L (REG_TC_VE_ENC2_BASE + 0xC6) 941 #define REG_TC_VE_ENC2_63_H (REG_TC_VE_ENC2_BASE + 0xC7) 942 #define REG_TC_VE_ENC2_64_L (REG_TC_VE_ENC2_BASE + 0xC8) 943 #define REG_TC_VE_ENC2_64_H (REG_TC_VE_ENC2_BASE + 0xC9) 944 #define REG_TC_VE_ENC2_65_L (REG_TC_VE_ENC2_BASE + 0xCA) 945 #define REG_TC_VE_ENC2_65_H (REG_TC_VE_ENC2_BASE + 0xCB) 946 #define REG_TC_VE_ENC2_66_L (REG_TC_VE_ENC2_BASE + 0xCC) 947 #define REG_TC_VE_ENC2_66_H (REG_TC_VE_ENC2_BASE + 0xCD) 948 #define REG_TC_VE_ENC2_67_L (REG_TC_VE_ENC2_BASE + 0xCE) 949 #define REG_TC_VE_ENC2_67_H (REG_TC_VE_ENC2_BASE + 0xCF) 950 #define REG_TC_VE_ENC2_68_L (REG_TC_VE_ENC2_BASE + 0xD0) 951 #define REG_TC_VE_ENC2_68_H (REG_TC_VE_ENC2_BASE + 0xD1) 952 #define REG_TC_VE_ENC2_69_L (REG_TC_VE_ENC2_BASE + 0xD2) 953 #define REG_TC_VE_ENC2_69_H (REG_TC_VE_ENC2_BASE + 0xD3) 954 #define REG_TC_VE_ENC2_6A_L (REG_TC_VE_ENC2_BASE + 0xD4) 955 #define REG_TC_VE_ENC2_6A_H (REG_TC_VE_ENC2_BASE + 0xD5) 956 #define REG_TC_VE_ENC2_6B_L (REG_TC_VE_ENC2_BASE + 0xD6) 957 #define REG_TC_VE_ENC2_6B_H (REG_TC_VE_ENC2_BASE + 0xD7) 958 #define REG_TC_VE_ENC2_6C_L (REG_TC_VE_ENC2_BASE + 0xD8) 959 #define REG_TC_VE_ENC2_6C_H (REG_TC_VE_ENC2_BASE + 0xD9) 960 #define REG_TC_VE_ENC2_6D_L (REG_TC_VE_ENC2_BASE + 0xDA) 961 #define REG_TC_VE_ENC2_6D_H (REG_TC_VE_ENC2_BASE + 0xDB) 962 #define REG_TC_VE_ENC2_6E_L (REG_TC_VE_ENC2_BASE + 0xDC) 963 #define REG_TC_VE_ENC2_6E_H (REG_TC_VE_ENC2_BASE + 0xDD) 964 #define REG_TC_VE_ENC2_6F_L (REG_TC_VE_ENC2_BASE + 0xDE) 965 #define REG_TC_VE_ENC2_6F_H (REG_TC_VE_ENC2_BASE + 0xDF) 966 #define REG_TC_VE_ENC2_70_L (REG_TC_VE_ENC2_BASE + 0xE0) 967 #define REG_TC_VE_ENC2_70_H (REG_TC_VE_ENC2_BASE + 0xE1) 968 #define REG_TC_VE_ENC2_71_L (REG_TC_VE_ENC2_BASE + 0xE2) 969 #define REG_TC_VE_ENC2_71_H (REG_TC_VE_ENC2_BASE + 0xE3) 970 #define REG_TC_VE_ENC2_72_L (REG_TC_VE_ENC2_BASE + 0xE4) 971 #define REG_TC_VE_ENC2_72_H (REG_TC_VE_ENC2_BASE + 0xE5) 972 #define REG_TC_VE_ENC2_73_L (REG_TC_VE_ENC2_BASE + 0xE6) 973 #define REG_TC_VE_ENC2_73_H (REG_TC_VE_ENC2_BASE + 0xE7) 974 #define REG_TC_VE_ENC2_74_L (REG_TC_VE_ENC2_BASE + 0xE8) 975 #define REG_TC_VE_ENC2_74_H (REG_TC_VE_ENC2_BASE + 0xE9) 976 #define REG_TC_VE_ENC2_75_L (REG_TC_VE_ENC2_BASE + 0xEA) 977 #define REG_TC_VE_ENC2_75_H (REG_TC_VE_ENC2_BASE + 0xEB) 978 #define REG_TC_VE_ENC2_76_L (REG_TC_VE_ENC2_BASE + 0xEC) 979 #define REG_TC_VE_ENC2_76_H (REG_TC_VE_ENC2_BASE + 0xED) 980 #define REG_TC_VE_ENC2_77_L (REG_TC_VE_ENC2_BASE + 0xEE) 981 #define REG_TC_VE_ENC2_77_H (REG_TC_VE_ENC2_BASE + 0xEF) 982 #define REG_TC_VE_ENC2_78_L (REG_TC_VE_ENC2_BASE + 0xF0) 983 #define REG_TC_VE_ENC2_78_H (REG_TC_VE_ENC2_BASE + 0xF1) 984 #define REG_TC_VE_ENC2_79_L (REG_TC_VE_ENC2_BASE + 0xF2) 985 #define REG_TC_VE_ENC2_79_H (REG_TC_VE_ENC2_BASE + 0xF3) 986 #define REG_TC_VE_ENC2_7A_L (REG_TC_VE_ENC2_BASE + 0xF4) 987 #define REG_TC_VE_ENC2_7A_H (REG_TC_VE_ENC2_BASE + 0xF5) 988 #define REG_TC_VE_ENC2_7B_L (REG_TC_VE_ENC2_BASE + 0xF6) 989 #define REG_TC_VE_ENC2_7B_H (REG_TC_VE_ENC2_BASE + 0xF7) 990 #define REG_TC_VE_ENC2_7C_L (REG_TC_VE_ENC2_BASE + 0xF8) 991 #define REG_TC_VE_ENC2_7C_H (REG_TC_VE_ENC2_BASE + 0xF9) 992 #define REG_TC_VE_ENC2_7D_L (REG_TC_VE_ENC2_BASE + 0xFA) 993 #define REG_TC_VE_ENC2_7D_H (REG_TC_VE_ENC2_BASE + 0xFB) 994 #define REG_TC_VE_ENC2_7E_L (REG_TC_VE_ENC2_BASE + 0xFC) 995 #define REG_TC_VE_ENC2_7E_H (REG_TC_VE_ENC2_BASE + 0xFD) 996 #define REG_TC_VE_ENC2_7F_L (REG_TC_VE_ENC2_BASE + 0xFE) 997 #define REG_TC_VE_ENC2_7F_H (REG_TC_VE_ENC2_BASE + 0xFF) 998 999 #ifdef __cplusplus 1000 } 1001 #endif 1002 1003 #undef _DRVADCTBL_H_ 1004 #endif 1005