1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE) 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 #define VPU_FORCE_MIU_MODE 1 121 #define HVD_ENABLE_IQMEM 0 122 #define VPU_IQMEM_BASE 0xe0000000 123 #define ENABLE_DECOMPRESS_FUNCTION TRUE 124 125 #define VPU_CLOCK_240MHZ BITS(4:2,0) 126 #define VPU_CLOCK_216MHZ BITS(4:2,1) 127 #define VPU_CLOCK_192MHZ BITS(4:2,2) 128 #define VPU_CLOCK_XTAL BITS(4:2,3) 129 #define VPU_CLOCK_320MHZ BITS(4:2,4) 130 #define VPU_CLOCK_288MHZ BITS(4:2,5) 131 132 133 #define VPU_IQMEM_BASE 0xe0000000 134 135 #define VPU_ENABLE_MOBF_TEST 0 136 137 138 139 #define VPU_HI_MBOX0 0 140 #define VPU_HI_MBOX1 1 141 #define VPU_RISC_MBOX0 2 142 #define VPU_RISC_MBOX1 3 143 144 145 #define VPU_EX_TimerDelayMS(x) \ 146 do \ 147 { \ 148 volatile MS_U32 ticks = 0; \ 149 while (ticks < (((MS_U32) (x)) << 13)) \ 150 { \ 151 ticks++; \ 152 } \ 153 } while(0) 154 155 #ifdef VDEC3 156 #define VPU_BBU_NAL_TBL BIT(0) 157 #define VPU_BBU_ES_BUFFER BIT(1) 158 #define HAL_VPU_INVALID_BBU_ID 0xFFFFFFFF 159 #define VPU_MAX_DEC_NUM 16 160 #else 161 #define VPU_MAX_DEC_NUM 2 162 #endif 163 #define CHECK_NULL_PTR(vbbu_addr) (((void *)(vbbu_addr)) == NULL) 164 165 //------------------------------------------------------------------------------------------------- 166 // Type and Structure 167 //------------------------------------------------------------------------------------------------- 168 typedef enum 169 { 170 E_HAL_HVD_STREAM_NONE = 0x0, 171 172 //Support TSP/TS/File mode 173 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 174 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 175 E_HAL_HVD_MAIN_STREAM_MAX, 176 177 //Only support file mode 178 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 179 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 180 E_HAL_HVD_SUB_STREAM1, 181 E_HAL_HVD_SUB_STREAM_MAX, 182 183 #ifdef VDEC3 184 E_HAL_HVD_N_STREAM_BASE = 0x40, 185 E_HAL_HVD_N_STREAM0 = E_HAL_HVD_N_STREAM_BASE, 186 E_HAL_HVD_N_STREAM_MAX = E_HAL_HVD_N_STREAM0 + VPU_MAX_DEC_NUM, 187 #endif 188 189 //Only support MVC stream 190 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 191 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 192 E_HAL_HVD_MVC_Sub_View, 193 E_HAL_HVD_MVC_STREAM_MAX, 194 } HAL_HVD_StreamId; 195 196 typedef enum 197 { 198 E_VPU_EX_DECODER_NONE = 0, 199 E_VPU_EX_DECODER_GET, 200 E_VPU_EX_DECODER_GET_MVC, 201 E_VPU_EX_DECODER_MVD, 202 E_VPU_EX_DECODER_HVD, 203 E_VPU_EX_DECODER_MJPEG, 204 E_VPU_EX_DECODER_RVD, 205 E_VPU_EX_DECODER_MVC, 206 E_VPU_EX_DECODER_VP8, 207 #ifdef VDEC3 208 E_VPU_EX_DECODER_EVD, 209 #if SUPPORT_G2VP9 210 E_VPU_EX_DECODER_G2VP9, 211 #endif 212 #endif 213 } VPU_EX_DecoderType; 214 215 typedef enum 216 { 217 E_VPU_EX_CLOCK_240MHZ = VPU_CLOCK_240MHZ, 218 E_VPU_EX_CLOCK_216MHZ = VPU_CLOCK_216MHZ, 219 E_VPU_EX_CLOCK_192MHZ = VPU_CLOCK_192MHZ, 220 E_VPU_EX_CLOCK_XTAL = VPU_CLOCK_XTAL, 221 E_VPU_EX_CLOCK_320MHZ = VPU_CLOCK_320MHZ, 222 E_VPU_EX_CLOCK_288MHZ = VPU_CLOCK_288MHZ, 223 } VPU_EX_ClockSpeed; 224 225 typedef enum 226 { 227 E_HAL_VPU_STREAM_NONE = 0x0, 228 229 //Support TSP/TS File/File mode 230 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 231 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 232 E_HAL_VPU_MAIN_STREAM_MAX, 233 234 //Only support file mode 235 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 236 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 237 E_HAL_VPU_SUB_STREAM_MAX, 238 239 #ifdef VDEC3 240 E_HAL_VPU_N_STREAM_BASE = 0x40, 241 E_HAL_VPU_N_STREAM0 = E_HAL_VPU_N_STREAM_BASE, 242 E_HAL_VPU_N_STREAM_MAX = E_HAL_VPU_N_STREAM0 + VPU_MAX_DEC_NUM, 243 #endif 244 245 //Only support MVC stream 246 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 247 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 248 E_HAL_VPU_MVC_SUB_VIEW, 249 E_HAL_VPU_MVC_STREAM_MAX, 250 } HAL_VPU_StreamId; 251 252 typedef enum 253 { 254 //Support TSP/TS/File mode 255 E_HAL_VPU_MAIN_STREAM, 256 257 //Only support file mode 258 E_HAL_VPU_SUB_STREAM, 259 260 //Only support MVC mode 261 E_HAL_VPU_MVC_STREAM, 262 263 #ifdef VDEC3 264 E_HAL_VPU_N_STREAM, 265 #endif 266 } HAL_VPU_StreamType; 267 268 typedef enum 269 { 270 //Support TSP/TS/File mode 271 E_VPU_EX_INPUT_TSP, 272 //Only support file mode 273 E_VPU_EX_INPUT_FILE, 274 E_VPU_EX_INPUT_NONE, 275 } VPU_EX_SourceType; 276 277 typedef enum 278 { 279 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 280 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 281 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 282 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 283 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 284 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 285 } VPU_EX_UartLevel; 286 287 typedef enum 288 { 289 E_VPU_EX_FW_VER_CTRLR = 0, 290 E_VPU_EX_FW_VER_MVD_FW, 291 E_VPU_EX_FW_VER_HVD_FW, 292 E_VPU_EX_FW_VER_MVD_IF, 293 E_VPU_EX_FW_VER_HVD_IF, 294 } VPU_EX_FWVerType; 295 296 /// DecodeMode for f/w tasks 297 typedef enum 298 { 299 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 300 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 301 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 302 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 303 } VPU_EX_DecMode; 304 305 /// CmdMode for KOREA3D or PIP mode 306 typedef enum 307 { 308 //Group1:Set Korea3DTV mode 309 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 310 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 311 E_VPU_CMD_MODE_KR3D_FORCE_P, 312 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 313 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 314 315 //Group2:Set PIP mode 316 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 317 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 318 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 319 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 320 } VPU_EX_CmdMode; 321 322 #define CMA_DRV_DIRECT_INIT 323 #ifdef CMA_DRV_DIRECT_INIT 324 /// input source select enumerator 325 typedef enum 326 { 327 ///DTV mode 328 E_VPU_EX_SRC_MODE_DTV = 0, 329 ///TS file mode 330 E_VPU_EX_SRC_MODE_TS_FILE, 331 ///generic file mode 332 E_VPU_EX_SRC_MODE_FILE, 333 /// TS file and dual ES buffer mode 334 E_VPU_EX_SRC_MODE_TS_FILE_DUAL_ES, 335 ///generic file and dual ES buffer mode 336 E_VPU_EX_SRC_MODE_FILE_DUAL_ES, 337 } VPU_EX_SrcMode; 338 #endif 339 340 /// codec type enumerator 341 typedef enum 342 { 343 ///unsupported codec type 344 E_VPU_EX_CODEC_TYPE_NONE = 0, 345 ///MPEG 1/2 346 E_VPU_EX_CODEC_TYPE_MPEG2, 347 ///H263 (short video header) 348 E_VPU_EX_CODEC_TYPE_H263, 349 ///MPEG4 (default) 350 E_VPU_EX_CODEC_TYPE_MPEG4, 351 ///MPEG4 (Divx311) 352 E_VPU_EX_CODEC_TYPE_DIVX311, 353 ///MPEG4 (Divx412) 354 E_VPU_EX_CODEC_TYPE_DIVX412, 355 ///FLV 356 E_VPU_EX_CODEC_TYPE_FLV, 357 ///VC1 advanced profile (VC1) 358 E_VPU_EX_CODEC_TYPE_VC1_ADV, 359 ///VC1 main profile (RCV) 360 E_VPU_EX_CODEC_TYPE_VC1_MAIN, 361 ///Real Video version 8 362 E_VPU_EX_CODEC_TYPE_RV8, 363 ///Real Video version 9 and 10 364 E_VPU_EX_CODEC_TYPE_RV9, 365 ///H264 366 E_VPU_EX_CODEC_TYPE_H264, 367 ///AVS 368 E_VPU_EX_CODEC_TYPE_AVS, 369 ///MJPEG 370 E_VPU_EX_CODEC_TYPE_MJPEG, 371 ///MVC 372 E_VPU_EX_CODEC_TYPE_MVC, 373 ///VP8 374 E_VPU_EX_CODEC_TYPE_VP8, 375 ///HEVC 376 E_VPU_EX_CODEC_TYPE_HEVC, 377 ///VP9 378 E_VPU_EX_CODEC_TYPE_VP9, 379 E_VPU_EX_CODEC_TYPE_NUM 380 } VPU_EX_CodecType; 381 382 /// record origin stream type for VPU hal 383 typedef enum 384 { 385 E_VPU_ORIGINAL_MAIN_STREAM = 0, 386 E_VPU_ORIGINAL_SUB_STREAM, 387 E_VPU_ORIGINAL_N_STREAM, 388 } VPU_EX_Original_Stream; 389 390 typedef struct 391 { 392 VPU_EX_ClockSpeed eClockSpeed; 393 MS_BOOL bClockInv; 394 MS_S32 s32VPUMutexID; 395 MS_U32 u32VPUMutexTimeout; 396 MS_U8 u8MiuSel; 397 } VPU_EX_InitParam; 398 399 typedef struct 400 { 401 MS_U32 u32Id; 402 HAL_VPU_StreamId eVpuId; 403 VPU_EX_SourceType eSrcType; 404 VPU_EX_DecoderType eDecType; 405 MS_U8 u8HalId; // hal MVD/HVD id 406 MS_U32 u32HeapSize; 407 } VPU_EX_TaskInfo; 408 409 typedef struct 410 { 411 MS_VIRT u32DstAddr; 412 MS_VIRT u32DstSize; 413 MS_VIRT u32BinSize; 414 MS_VIRT u32BinAddr; 415 MS_U8 u8SrcType; 416 } VPU_EX_FWCodeCfg; 417 418 typedef struct 419 { 420 MS_VIRT u32DstAddr; 421 MS_VIRT u32BinAddr; 422 MS_VIRT u32BinSize; 423 MS_VIRT u32FrameBufAddr; 424 MS_VIRT u32VLCTableOffset; 425 } VPU_EX_VLCTblCfg; 426 427 #ifdef VDEC3 428 typedef struct 429 { 430 MS_VIRT u32FrameBufAddr; 431 MS_VIRT u32FrameBufSize; 432 } VPU_EX_FBCfg; 433 #endif 434 435 /// VPU init parameters for dual decoder 436 typedef struct 437 { 438 VPU_EX_FWCodeCfg *pFWCodeCfg; 439 VPU_EX_TaskInfo *pTaskInfo; 440 VPU_EX_VLCTblCfg *pVLCCfg; 441 #ifdef VDEC3 442 VPU_EX_FBCfg *pFBCfg; 443 #endif 444 } VPU_EX_NDecInitPara; 445 446 typedef struct 447 { 448 MS_U8 u8DecMod; 449 MS_U8 u8CodecCnt; 450 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 451 MS_U8 u8ArgSize; 452 MS_U32 u32Arg; 453 } VPU_EX_DecModCfg; 454 455 456 typedef enum 457 { 458 E_VDEC_EX_CODEC_PROFILE_NONE, 459 460 E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, 461 462 E_VDEC_EX_CODEC_PROFILE_MP4_ASP, 463 464 E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, 465 466 E_VDEC_EX_CODEC_PROFILE_VC1_AP, 467 468 E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, 469 470 E_VDEC_EX_CODEC_PROFILE_VP9_0, 471 E_VDEC_EX_CODEC_PROFILE_VP9_2, 472 473 E_VDEC_EX_CODEC_PROFILE_H264_CBP, 474 E_VDEC_EX_CODEC_PROFILE_H264_BP, 475 E_VDEC_EX_CODEC_PROFILE_H264_XP, 476 E_VDEC_EX_CODEC_PROFILE_H264_MP, 477 E_VDEC_EX_CODEC_PROFILE_H264_HIP, 478 E_VDEC_EX_CODEC_PROFILE_H264_PHIP, 479 E_VDEC_EX_CODEC_PROFILE_H264_CHIP, 480 E_VDEC_EX_CODEC_PROFILE_H264_HI10P, 481 E_VDEC_EX_CODEC_PROFILE_H264_HI422P, 482 E_VDEC_EX_CODEC_PROFILE_H264_HI444PP, 483 484 E_VDEC_EX_CODEC_PROFILE_H265_MAIN, 485 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, 486 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_12, 487 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_10, 488 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_12, 489 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444, 490 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_10, 491 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_12, 492 493 E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, 494 495 496 } VDEC_EX_CODEC_CAP_PROFILE_INFO; 497 498 typedef enum 499 { 500 E_VDEC_EX_CODEC_LEVEL_NONE, 501 502 E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, 503 504 E_VDEC_EX_CODEC_LEVEL_MP4_L5, 505 506 E_VDEC_EX_CODEC_LEVEL_VC1_L3, 507 508 E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, 509 510 511 E_VDEC_EX_CODEC_LEVEL_H264_1, 512 E_VDEC_EX_CODEC_LEVEL_H264_1B, 513 E_VDEC_EX_CODEC_LEVEL_H264_1_1, 514 E_VDEC_EX_CODEC_LEVEL_H264_1_2, 515 E_VDEC_EX_CODEC_LEVEL_H264_1_3, 516 E_VDEC_EX_CODEC_LEVEL_H264_2, 517 E_VDEC_EX_CODEC_LEVEL_H264_2_1, 518 E_VDEC_EX_CODEC_LEVEL_H264_2_2, 519 E_VDEC_EX_CODEC_LEVEL_H264_3, 520 E_VDEC_EX_CODEC_LEVEL_H264_3_1, 521 E_VDEC_EX_CODEC_LEVEL_H264_3_2, 522 E_VDEC_EX_CODEC_LEVEL_H264_4, 523 E_VDEC_EX_CODEC_LEVEL_H264_4_1, 524 E_VDEC_EX_CODEC_LEVEL_H264_4_2, 525 E_VDEC_EX_CODEC_LEVEL_H264_5, 526 E_VDEC_EX_CODEC_LEVEL_H264_5_1, 527 E_VDEC_EX_CODEC_LEVEL_H264_5_2, 528 529 E_VDEC_EX_CODEC_LEVEL_H265_1, 530 E_VDEC_EX_CODEC_LEVEL_H265_2, 531 E_VDEC_EX_CODEC_LEVEL_H265_2_1, 532 E_VDEC_EX_CODEC_LEVEL_H265_3, 533 E_VDEC_EX_CODEC_LEVEL_H265_3_1, 534 E_VDEC_EX_CODEC_LEVEL_H265_4_MT, 535 E_VDEC_EX_CODEC_LEVEL_H265_4_HT, 536 E_VDEC_EX_CODEC_LEVEL_H265_4_1_MT, 537 E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, 538 E_VDEC_EX_CODEC_LEVEL_H265_5_MT, 539 E_VDEC_EX_CODEC_LEVEL_H265_5_HT, 540 E_VDEC_EX_CODEC_LEVEL_H265_5_1_MT, 541 E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, 542 E_VDEC_EX_CODEC_LEVEL_H265_5_2_MT, 543 E_VDEC_EX_CODEC_LEVEL_H265_5_2_HT, 544 E_VDEC_EX_CODEC_LEVEL_H265_6_MT, 545 E_VDEC_EX_CODEC_LEVEL_H265_6_HT, 546 E_VDEC_EX_CODEC_LEVEL_H265_6_1_MT, 547 E_VDEC_EX_CODEC_LEVEL_H265_6_1_HT, 548 E_VDEC_EX_CODEC_LEVEL_H265_6_2_MT, 549 E_VDEC_EX_CODEC_LEVEL_H265_6_2_HT, 550 551 E_VDEC_EX_CODEC_LEVEL_AVS_6010860, 552 553 } VDEC_EX_CODEC_CAP_LEVEL_INFO; 554 555 556 typedef enum 557 { 558 E_VDEC_EX_CODEC_VERSION_NONE, 559 560 E_VDEC_EX_CODEC_VERSION_DIVX_311, 561 E_VDEC_EX_CODEC_VERSION_DIVX_4, 562 E_VDEC_EX_CODEC_VERSION_DIVX_5, 563 E_VDEC_EX_CODEC_VERSION_DIVX_6, 564 565 E_VDEC_EX_CODEC_VERSION_FLV_1, 566 567 E_VDEC_EX_CODEC_VERSION_H263_1, 568 569 } VDEC_EX_CODEC_CAP_VERSION_INFO; 570 571 typedef struct DLL_PACKED 572 { 573 MS_U16 u16CodecCapWidth; 574 MS_U16 u16CodecCapHeight; 575 MS_U8 u8CodecCapFrameRate; 576 VDEC_EX_CODEC_CAP_PROFILE_INFO u8CodecCapProfile; 577 VDEC_EX_CODEC_CAP_VERSION_INFO u8CodecCapVersion; 578 VDEC_EX_CODEC_CAP_LEVEL_INFO u8CodecCapLevel; 579 MS_U32 u32CodecType; 580 MS_U32 u32BitRate; //20170110 581 MS_U32 u32Reserved1; 582 }VDEC_EX_CODEC_CAP_INFO; 583 584 //------------------------------------------------------------------------------------------------- 585 // Function and Variable 586 //------------------------------------------------------------------------------------------------- 587 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex); 588 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 589 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 590 #ifdef VDEC3 591 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId); 592 #else 593 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 594 #endif 595 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 596 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 597 598 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 599 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase); 600 601 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 602 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 603 MS_BOOL HAL_VPU_EX_DeInit(void); 604 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 605 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 606 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr); 607 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 608 void HAL_VPU_EX_SwRstRelse(void); 609 void HAL_VPU_EX_SwRelseMAU(void); 610 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Address); 611 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Address, MS_U32 u32Value); 612 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 613 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 614 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 615 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 616 MS_U32 HAL_VPU_EX_GetProgCnt(void); 617 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 618 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr); 619 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 620 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id); 621 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id); 622 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id); 623 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id); 624 MS_BOOL HAL_VPU_EX_IsPowered(void); 625 MS_BOOL HAL_VPU_EX_IsRsted(void); 626 MS_BOOL HAL_VPU_EX_IsEVDR2(void); 627 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 628 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 629 #ifdef VDEC3 630 MS_BOOL HAL_VPU_EX_EVDInUsed(void); 631 #if SUPPORT_G2VP9 632 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void); 633 #endif 634 #endif 635 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable); 636 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 637 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 638 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 639 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 640 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo); 641 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id); 642 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id); 643 void HAL_VPU_EX_Mutex_Lock(void); 644 void HAL_VPU_EX_Mutex_UnLock(void); 645 646 MS_VIRT HAL_VPU_EX_MIU1BASE(void); 647 MS_VIRT HAL_VPU_EX_GetSHMAddr(void); 648 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 649 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr); 650 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 651 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass); 652 653 void HAL_VPU_EX_ForceSwRst(void); 654 655 #ifdef VDEC3 656 typedef enum 657 { 658 E_HVD_CMDQ_CMD, 659 E_HVD_CMDQ_ARG, 660 } HVD_COMMAND_QUEUE_TYPE; 661 662 typedef enum 663 { 664 E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL, 665 E_HVD_COMMAND_QUEUE_NOT_INITIALED, 666 E_HVD_COMMAND_QUEUE_FULL, 667 E_HVD_COMMAND_QUEUE_SEND_FAIL, 668 } HVD_DRAM_COMMAND_QUEUE_SEND_STATUS; 669 670 671 typedef struct 672 { 673 MS_VIRT u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 674 MS_U32 u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 675 MS_U64 u64TimeStamp; ///< Packet time stamp. unit: ms. 676 MS_U32 u32ID_L; ///< Packet ID low part. 677 MS_U32 u32ID_H; ///< Packet ID high part. 678 } HAL_VPU_EX_PacketInfo; 679 // *****************Virtual BBU function***************** 680 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr); 681 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr); 682 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 683 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 684 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr); 685 // *****************General dram command queue function***************** 686 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd); 687 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd); 688 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg); 689 // *****************Dram command queue function***************** 690 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue); 691 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue); 692 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 693 // *****************Display dram command queue function***************** 694 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue); 695 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue); 696 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 697 // *****************General purpose function***************** 698 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr); 699 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit); 700 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit); 701 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType); 702 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU); 703 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo); 704 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType); 705 // *****************CMA function***************** 706 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode, 707 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize); 708 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut); 709 #endif 710 #ifdef VDEC3_FB 711 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType); 712 #endif 713 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size); 714 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx); 715 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream); 716 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType); 717 718 #else 719 typedef struct 720 { 721 MS_PHY Bitstream_Addr_Main; 722 MS_U32 Bitstream_Len_Main; 723 MS_PHY Bitstream_Addr_Sub; 724 MS_U32 Bitstream_Len_Sub; 725 MS_PHY MIU1_BaseAddr; 726 } VPU_EX_LOCK_DOWN_REGISTER; 727 728 729 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr); 730 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 731 732 #endif 733 #endif // _HAL_VPU_EX_H_ 734 735