1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117 #include "drvSYS.h" //20170110
118
119 //-------------------------------------------------------------------------------------------------
120 // Driver Compiler Options
121 //-------------------------------------------------------------------------------------------------
122 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
123
124 //-------------------------------------------------------------------------------------------------
125 // Local Defines
126 //-------------------------------------------------------------------------------------------------
127 #define RV_VLC_TABLE_SIZE 0x20000
128 /* Add for Mobile Platform by Ted Sun */
129 //#define HVD_DISPQ_PREFETCH_COUNT 2
130 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
131 #define VPU_QMEM_BASE 0x20000000UL
132
133 //max support pixel(by chip capacity)
134 #define HVD_HW_MAX_PIXEL (1920*1088*61000ULL) // FHD@60p
135 #define HEVC_HW_MAX_PIXEL (1920*1088*61000ULL) // FHD@60p
136 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
137
138 #define EVD_HW_BUFFER 0x200000 //0x800000: support MFcodec, 0x200000: not support MFcodec
139
140 #if 0
141 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
142 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
143 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
144 static MS_U16 _u16DispQPtr = 0;
145 #endif
146
147 #define IS_TASK_ALIVE(id) ((id) != -1)
148 #ifndef UNUSED
149 #define UNUSED(x) (void)(x)
150 #endif
151
152
153 //---------------------------------- Mutex settings -----------------------------------------
154 #if HAL_HVD_ENABLE_MUTEX_PROTECT
155 #define _HAL_HVD_MutexCreate() \
156 do \
157 { \
158 if (s32HVDMutexID < 0) \
159 { \
160 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
161 } \
162 } while (0)
163
164 #define _HAL_HVD_MutexDelete() \
165 do \
166 { \
167 if (s32HVDMutexID >= 0) \
168 { \
169 OSAL_HVD_MutexDelete(s32HVDMutexID); \
170 s32HVDMutexID = -1; \
171 } \
172 } while (0)
173
174 #define _HAL_HVD_Entry() \
175 do \
176 { \
177 if (s32HVDMutexID >= 0) \
178 { \
179 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
180 { \
181 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
182 } \
183 } \
184 } while (0)
185
186 #define _HAL_HVD_Return(_ret_) \
187 do \
188 { \
189 if (s32HVDMutexID >= 0) \
190 { \
191 OSAL_HVD_MutexRelease(s32HVDMutexID); \
192 } \
193 return _ret_; \
194 } while(0)
195
196 #define _HAL_HVD_Release() \
197 do \
198 { \
199 if (s32HVDMutexID >= 0) \
200 { \
201 OSAL_HVD_MutexRelease(s32HVDMutexID); \
202 } \
203 } while (0)
204 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
205
206 #define _HAL_HVD_MutexCreate()
207 #define _HAL_HVD_MutexDelete()
208 #define _HAL_HVD_Entry()
209 #define _HAL_HVD_Return(_ret) {return _ret;}
210 #define _HAL_HVD_Release()
211
212 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
213
214 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
215 #define IS_TASK_ALIVE(id) ((id) != -1)
216 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
217
218 //------------------------------ MIU SETTINGS ----------------------------------
219 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ1_MASK, m, BIT(2))
220 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
221 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
222 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
223
224 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ1_MASK, m, BIT(2))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
226 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(1))
227 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
228
229 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL1) & BIT(2)) == BIT(2))
230 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
231 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == BIT(1))
232 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0))
233
234 #if SUPPORT_EVD
235 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
236 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
237 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
238
239 #define _MaskMiu1Req_EVD_RW1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
240 #define _MaskMiu1Req_EVD_RW2( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
241 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(3))
242
243 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0))
244 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0))
245 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0))
246
247 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)))
248 #define HVD_EVD_RW2_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)))
249 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)))
250 #endif
251
252 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
253 do \
254 { \
255 if (HVD_##miu_clients##_ON_MIU1 == 0) \
256 { \
257 _MaskMiuReq_##miu_clients(mask); \
258 } \
259 else \
260 { \
261 _MaskMiu1Req_##miu_clients(mask); \
262 } \
263 } while (0)
264
265 // check RM is supported or not
266 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
267 #ifdef VDEC3
268 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
269 #else
270 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
271 #endif
272
273 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
274
275 //-------------------------------------------------------------------------------------------------
276 // Local Structures
277 //-------------------------------------------------------------------------------------------------
278
279 //-------------------------------------------------------------------------------------------------
280 // Local Functions Prototype
281 //-------------------------------------------------------------------------------------------------
282 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
283 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
284 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
285 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
286 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
287 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
288 static MS_U32 _HVD_EX_GetPC(void);
289 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
290 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
291 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
292 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
293 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
294 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
295 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
296 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
297 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
298 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
299 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
300 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
301 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
302 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
303 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
304 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
305 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
306 #if SUPPORT_EVD
307 static void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable);
308 static MS_BOOL HAL_EVD_EX_DeinitHW(void);
309 #endif
310 #if SUPPORT_G2VP9 && defined(VDEC3)
311 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
312 #endif
313 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
314 #if SUPPORT_G2VP9 && defined(VDEC3)
315 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
316 #endif
317 //-------------------------------------------------------------------------------------------------
318 // Global Variables
319 //-------------------------------------------------------------------------------------------------
320 #if defined (__aeon__)
321 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
322 #else
323 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
324 #endif
325 #if HAL_HVD_ENABLE_MUTEX_PROTECT
326 MS_S32 s32HVDMutexID = -1;
327 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
328 #endif
329
330
331 #define HVD_EX_STACK_SIZE 4096
332 //-------------------------------------------------------------------------------------------------
333 // Local Variables
334 //-------------------------------------------------------------------------------------------------
335 typedef struct
336 {
337
338 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
339 MS_U8 g_hvd_nal_fill_pair[2][8];
340 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
341 MS_U16 _u16DispQPtr;
342 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
343
344 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
345 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
346 MS_U32 u32VPUClockType;
347 MS_U32 u32HVDClockType;//160
348 #if SUPPORT_EVD
349 MS_U32 u32EVDClockType;
350 #endif
351 #if SUPPORT_G2VP9 && defined(VDEC3)
352 MS_U32 u32VP9ClockType;
353 #endif
354 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
355
356 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
357 MS_BOOL g_RstFlag;
358 MS_U64 u64pts_real;
359 MS_PHY u32VP8BBUWptr;
360 MS_PHY u32EVDBBUWptr;
361 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
362 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
363 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
364 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
365 //pre_set
366 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
367 } HVD_Hal_CTX;
368
369 HVD_Hal_CTX* pHVDHalContext = NULL;
370 HVD_Hal_CTX gHVDHalContext;
371 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
372
373 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
374 {
375 {FALSE},
376 {FALSE},
377 {FALSE},
378 #ifdef VDEC3
379 {FALSE},
380 #endif
381 };
382
383 //-------------------------------------------------------------------------------------------------
384 // Debug Functions
385 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)386 void HVD_EX_SetRstFlag(MS_BOOL bRst)
387 {
388 pHVDHalContext->g_RstFlag = bRst;
389 }
HVD_EX_GetRstFlag(void)390 MS_BOOL HVD_EX_GetRstFlag(void)
391 {
392 return pHVDHalContext->g_RstFlag;
393 }
394
395 //-------------------------------------------------------------------------------------------------
396 // Local Functions
397 //-------------------------------------------------------------------------------------------------
398 #ifdef VDEC3 //20170110
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)399 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
400 {
401 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
402
403 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
404 #if SUPPORT_MSVP9
405 || u32CodecType == E_HVD_INIT_HW_VP9
406 #endif
407 )
408 return TRUE;
409
410 return FALSE;
411 }
412
_HAL_EX_BBU_VP8_InUsed(void)413 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
414 {
415 if (!pHVDHalContext)
416 return FALSE;
417
418 MS_U32 i;
419 MS_BOOL bRet = FALSE;
420
421 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
422 {
423 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
424 {
425 bRet = TRUE;
426 break;
427 }
428 }
429
430 return bRet;
431 }
432
433 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
434 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)435 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
436 {
437
438 MS_U32 ret = TRUE;
439 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
440
441 if(pCtrl == NULL || pstTaskInfo == NULL)
442 return FALSE;
443
444 pstTaskInfo->u32Id = u32Id;
445
446 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
447 {
448 case E_HVD_INIT_HW_RM:
449 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
450 break;
451 case E_HVD_INIT_HW_VP8:
452 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
453 break;
454 case E_HVD_INIT_HW_MVC:
455 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
456 break;
457 case E_HVD_INIT_HW_HEVC:
458 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
459 break;
460 #if SUPPORT_MSVP9
461 case E_HVD_INIT_HW_VP9:
462 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
463 break;
464 #endif
465 #if SUPPORT_G2VP9
466 case E_HVD_INIT_HW_VP9:
467 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
468 break;
469 #endif
470 default:
471 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
472 break;
473 }
474
475 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
476
477 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
478 {
479 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
480 }
481 else
482 {
483 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
484 }
485
486 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
487
488 #ifdef SUPPORT_EVD
489 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
490 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
491 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
492 #endif
493 return ret;
494
495 }
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)496 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
497 {
498 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
499 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
500 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
501 _HAL_HVD_Entry();
502
503 if(pCtrl == NULL)
504 _HAL_HVD_Return(ret);
505
506 VPU_EX_TaskInfo taskInfo;
507 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
508
509 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
510
511 taskInfo.u8HalId = u8Idx;
512 ret = HAL_VPU_EX_GetBBUId(u32Id,&taskInfo, pCtrl->bShareBBU);
513
514 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
515 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
516
517 _HAL_HVD_Return(ret);
518 }
519
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)520 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
521 {
522 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
523 MS_BOOL ret = FALSE;
524 _HAL_HVD_Entry();
525
526 if(pCtrl == NULL)
527 _HAL_HVD_Return(ret);
528 VPU_EX_TaskInfo taskInfo;
529 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
530
531 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
532
533 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
534
535 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
536 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
537
538 _HAL_HVD_Return(ret);
539 }
540
HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId)541 MS_BOOL HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId)
542 {
543 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
544 MS_BOOL ret = FALSE;
545 _HAL_HVD_Entry();
546
547 if(pCtrl == NULL)
548 _HAL_HVD_Return(ret);
549 VPU_EX_TaskInfo taskInfo;
550 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
551
552 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
553
554 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, taskInfo.eDecType);
555
556 _HAL_HVD_Return(TRUE);
557 }
558 #endif
559
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)560 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
561 {
562 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
563 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
564 pstHVDStream->s32HvdPpTaskId = -1;
565 }
566
_HVD_EX_Context_Init_HAL(void)567 static void _HVD_EX_Context_Init_HAL(void)
568 {
569 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
570 pHVDHalContext->u32VPUClockType = 320; ///Note : Max VD_R2 clock in Monaco is only 320MHz
571 ///Note : Max EVD_R2 clock in Monaco is only 384MHz
572
573 const SYS_Info* sysInfo;
574 sysInfo = MDrv_SYS_GetInfo();
575
576 pHVDHalContext->u32HVDClockType = 240;//160;
577
578 #if SUPPORT_EVD
579 pHVDHalContext->u32EVDClockType = 240;
580 #endif
581 #if SUPPORT_G2VP9 && defined(VDEC3)
582 pHVDHalContext->u32VP9ClockType = 384;
583 #endif
584 #ifdef VDEC3
585 MS_U8 i;
586
587 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
588 {
589 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
590 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
591 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
592 }
593 #else
594 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
595 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
596 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
597 #endif
598 }
599
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)600 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
601 {
602 MS_U16 u16Ret = 0;
603 #if (HVD_ENABLE_MVC || (!VDEC3))
604 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
605 #endif
606 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
607 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
608 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
609 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
610
611 #if HVD_ENABLE_MVC
612 if(HAL_HVD_EX_CheckMVCID(u32Id))
613 {
614 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
615 }
616 #endif /// HVD_ENABLE_MVC
617
618 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
619 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
620
621 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
622 {
623 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
624 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
625 }
626 else
627 #ifdef VDEC3
628 if (0 == pCtrl->u32BBUId)
629 #else
630 if (0 == u8TaskId)
631 #endif
632 {
633 //if(pCtrl->InitParams.bColocateBBUMode)
634 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
635 u16Ret = pShm->u32ColocateBBUReadPtr;
636 else
637 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
638 }
639 else
640 {
641 //if(pCtrl->InitParams.bColocateBBUMode)
642 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
643 u16Ret = pShm->u32ColocateBBUReadPtr;
644 else
645 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
646 }
647
648 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
649 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
650
651 return u16Ret;
652 }
653
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)654 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
655 {
656 MS_U16 u16Ret = 0;
657 #if (HVD_ENABLE_MVC || (!VDEC3))
658 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
659 #endif
660 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
661 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
662 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
663 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
664
665 #if HVD_ENABLE_MVC
666 if (HAL_HVD_EX_CheckMVCID(u32Id))
667 {
668 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
669 }
670 #endif /// HVD_ENABLE_MVC
671 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
672 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
673
674 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
675 {
676 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
677 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
678 }
679 else
680 #ifdef VDEC3
681 if (0 == pDrvCtrl->u32BBUId)
682 #else
683 if (0 == u8TaskId)
684 #endif
685 {
686 //if(pDrvCtrl->InitParams.bColocateBBUMode)
687 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
688 u16Ret = pShm->u32ColocateBBUWritePtr;
689 else
690 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
691 }
692 else
693 {
694 //if(pDrvCtrl->InitParams.bColocateBBUMode)
695 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
696 u16Ret = pShm->u32ColocateBBUWritePtr;
697 else
698 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
699 }
700
701 return u16Ret;
702 }
703
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)704 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
705 {
706 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
707 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
708
709 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
710 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
711 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
712 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
713 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
714 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
715 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
716 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
717 }
718
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)719 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
720 {
721 #if (HVD_ENABLE_MVC || (!VDEC3))
722 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
723 #endif
724 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
725 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
726 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
727 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
728
729 #if HVD_ENABLE_MVC
730 if (HAL_HVD_EX_CheckMVCID(u32Id))
731 {
732 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
733 }
734 #endif /// HVD_ENABLE_MVC
735
736 //HVD_EX_MSG_COVERITY("[%s] u8TaskId = %d\n",__FUNCTION__,u8TaskId);//coverity - set_but_not_used: variable "u8TaskId" was set but never used
737
738 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
739 {
740 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
741 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
742 }
743 else
744 #ifdef VDEC3
745 if (0 == pCtrl->u32BBUId)
746 #else
747 if (0 == u8TaskId)
748 #endif
749 {
750 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
751 //if(pCtrl->InitParams.bColocateBBUMode)
752 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
753 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
754 }
755 else
756 {
757 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
758 //if(pCtrl->InitParams.bColocateBBUMode)
759 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
760 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
761 }
762
763 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
764 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
765
766 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
767 }
768
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)769 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
770 {
771 MS_BOOL bResult = TRUE;
772 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
773 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
774
775 switch (u8MBox)
776 {
777 case E_HVD_HI_0:
778 {
779 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
780 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
781 break;
782 }
783 case E_HVD_HI_1:
784 {
785 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
786 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
787 break;
788 }
789 case E_HVD_VPU_HI_0:
790 {
791 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
792 break;
793 }
794 case E_HVD_VPU_HI_1:
795 {
796 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
797 break;
798 }
799 default:
800 {
801 bResult = FALSE;
802 break;
803 }
804 }
805
806 return bResult;
807 }
808
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)809 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
810 {
811 MS_BOOL bResult = TRUE;
812 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
813 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
814
815 switch (u8MBox)
816 {
817 case E_HVD_HI_0:
818 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
819 break;
820 case E_HVD_HI_1:
821 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
822 break;
823 case E_HVD_RISC_0:
824 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
825 break;
826 case E_HVD_RISC_1:
827 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
828 break;
829 case E_HVD_VPU_HI_0:
830 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
831 break;
832 case E_HVD_VPU_HI_1:
833 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
834 break;
835 case E_HVD_VPU_RISC_0:
836 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
837 break;
838 case E_HVD_VPU_RISC_1:
839 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
840 break;
841 default:
842 break;
843 }
844
845 return bResult;
846 }
847
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)848 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
849 {
850 MS_BOOL bResult = TRUE;
851 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
852 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
853
854 switch (u8MBox)
855 {
856 case E_HVD_HI_0:
857 {
858 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
859 break;
860 }
861 case E_HVD_HI_1:
862 {
863 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
864 break;
865 }
866 case E_HVD_RISC_0:
867 {
868 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
869 break;
870 }
871 case E_HVD_RISC_1:
872 {
873 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
874 break;
875 }
876 case E_HVD_VPU_RISC_0:
877 {
878 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
879 break;
880 }
881 case E_HVD_VPU_RISC_1:
882 {
883 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
884 break;
885 }
886 default:
887 {
888 bResult = FALSE;
889 break;
890 }
891 }
892
893 return bResult;
894 }
895
896 #if 0
897 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
898 {
899 switch (u8MBox)
900 {
901 case E_HVD_RISC_0:
902 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
903 break;
904 case E_HVD_RISC_1:
905 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
906 break;
907 case E_HVD_VPU_RISC_0:
908 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
909 break;
910 case E_HVD_VPU_RISC_1:
911 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
912 break;
913 default:
914 break;
915 }
916 }
917 #endif
918
_HVD_EX_GetPC(void)919 static MS_U32 _HVD_EX_GetPC(void)
920 {
921 MS_U32 u32PC = 0;
922 u32PC = HAL_VPU_EX_GetProgCnt();
923 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
924 return u32PC;
925 }
926
_HVD_EX_GetESWritePtr(MS_U32 u32Id)927 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
928 {
929 MS_U32 u32Data = 0;
930 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
931 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
932
933 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
934 {
935 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
936
937 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
938 {
939 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
940
941 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
942 }
943 }
944 else
945 {
946 #if HVD_ENABLE_MVC
947 MS_U8 u8ViewIdx = 0;
948 if(HAL_HVD_EX_CheckMVCID(u32Id))
949 {
950 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
951 }
952 if(u8ViewIdx != 0) /// 2nd ES ptr.
953 {
954 u32Data = pShm->u32ES2WritePtr;
955 }
956 else
957 {
958 u32Data = pShm->u32ESWritePtr;
959 }
960 #else
961 u32Data = pShm->u32ESWritePtr;
962 #endif
963 }
964
965 return u32Data;
966 }
967
968 #define NAL_UNIT_LEN_BITS 21
969 #define NAL_UNIT_OFT_BITS 30
970 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
971 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
972 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
973
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)974 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
975 {
976 MS_U32 u32Data = 0;
977 MS_U8 u8TaskId = 0;
978 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
979 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
980 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
981 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
982 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
983
984 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
985 #if HVD_ENABLE_MVC
986 if(HAL_HVD_EX_CheckMVCID(u32Id))
987 {
988 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
989 }
990 #endif /// HVD_ENABLE_MVC
991
992 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
993 {
994 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
995 {
996 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
997 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
998 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
999 MS_U32 *u32Adr;
1000 MS_U32 u32Tmp;
1001
1002 if (u16ReadPtr == u16WritePtr)
1003 {
1004 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1005 }
1006 else
1007 {
1008 if (u16ReadPtr)
1009 u16ReadPtr--;
1010 else
1011 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1012
1013 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1014
1015 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1016 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1017 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1018 u32Data = u32Data | u32Tmp;
1019
1020 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1021 //while(1);
1022 }
1023 goto EXIT;
1024 }
1025 // set reg_poll_nal_rptr 0
1026 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1027 // set reg_poll_nal_rptr 1
1028 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1029
1030 // read reg_nal_rptr_hi
1031 #ifdef VDEC3
1032 if (0 == pCtrl->u32BBUId)
1033 #else
1034 if (0 == u8TaskId)
1035 #endif
1036 {
1037 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
1038 u32Data >>= 6;
1039 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
1040 }
1041 else
1042 {
1043 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
1044 u32Data >>= 6;
1045 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
1046 }
1047
1048 u32Data <<= 3; // unit
1049
1050 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1051 {
1052 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1053
1054 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1055 {
1056 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1057 u32Data = u32ESWptr;
1058 }
1059 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1060 {
1061 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1062 u32Data = u32ESWptr;
1063 }
1064 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1065 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1066 {
1067 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1068 u32Data = u32ESWptr;
1069 }
1070 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1071 && ((u32Data - u32ESWptr) < 32)
1072 && (pCtrl->u32FlushRstPtr == 1))
1073 {
1074 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1075 u32Data = u32ESWptr;
1076 }
1077 }
1078
1079 // remove illegal pointer
1080 #if 1
1081 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1082 {
1083 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1084
1085 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1086 (u32PacketStaddr <
1087 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1088 {
1089 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1090 u32Data = pCtrl->u32LastESRptr;
1091 }
1092 }
1093 #endif
1094 }
1095 else
1096 {
1097 #if HVD_ENABLE_MVC
1098 MS_U8 u8ViewIdx = 0;
1099 if(HAL_HVD_EX_CheckMVCID(u32Id))
1100 {
1101 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1102 }
1103 if(u8ViewIdx != 0) /// 2nd ES ptr.
1104 {
1105 u32Data = pShm->u32ES2ReadPtr;
1106 }
1107 else
1108 {
1109 u32Data = pShm->u32ESReadPtr;
1110 }
1111 #else
1112 u32Data = pShm->u32ESReadPtr;
1113 #endif
1114 }
1115
1116 EXIT:
1117
1118 pCtrl->u32LastESRptr = u32Data;
1119
1120 return u32Data;
1121 }
1122
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1123 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1124 {
1125 MS_U16 u16TimeOut = 0xFFFF;
1126 MS_BOOL bResult = FALSE;
1127
1128 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1129
1130 while (--u16TimeOut)
1131 {
1132 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1133 {
1134 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1135 break;
1136 }
1137 }
1138
1139 return bResult;
1140 }
1141
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1142 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1143 {
1144 MS_U16 u16TimeOut = 0xFFFF;
1145 MS_BOOL bResult = FALSE;
1146 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1147
1148 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1149
1150 #if HVD_ENABLE_MVC
1151 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1152 {
1153 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1154 }
1155 #endif /// HVD_ENABLE_MVC
1156
1157 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1158
1159 while (--u16TimeOut)
1160 {
1161 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1162 {
1163 u32Cmd |= (u8TaskId << 24);
1164 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1165 break;
1166 }
1167 }
1168 return bResult;
1169 }
1170
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1171 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1172 {
1173 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1174 #ifdef VDEC3
1175 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1176 MS_BOOL IsSent = FALSE;
1177 MS_BOOL IsMailBox = FALSE;
1178 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1179
1180 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1181 {
1182 do {
1183 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1184 if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL)
1185 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1186 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1187 break;
1188 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1189 IsSent = TRUE;
1190 break;
1191 }
1192 else if (HVD_GetSysTime_ms() > u32timeout)
1193 {
1194 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1195 break;
1196 }
1197 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1198 }
1199 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1200 {
1201 do {
1202 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1203 if (!SentRet)
1204 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1205 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1206 break;
1207 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1208 IsSent = TRUE;
1209 break;
1210 }
1211 else if (HVD_GetSysTime_ms() > u32timeout)
1212 {
1213 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1214 break;
1215 }
1216 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1217 }
1218 if (!IsSent) {
1219 IsMailBox = TRUE;
1220 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1221 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1222 #else
1223 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1224 #endif
1225 {
1226 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1227 if (HVD_GetSysTime_ms() > u32timeout)
1228 {
1229 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1230 return E_HVD_RETURN_TIMEOUT;
1231 }
1232 //#endif
1233
1234 #if 0
1235 if (u32Cmd == E_HVD_CMD_STOP)
1236 {
1237 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1238 #if HVD_ENABLE_MVC
1239 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1240 {
1241 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1242 }
1243 #endif /// HVD_ENABLE_MVC
1244 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1245
1246 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1247 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1248
1249 return E_HVD_RETURN_SUCCESS;
1250 }
1251 #endif
1252
1253 if(u32Cmd < E_DUAL_CMD_BASE)
1254 {
1255 //_HVD_EX_GetPC();
1256 HAL_HVD_EX_Dump_FW_Status(u32Id);
1257 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1258 }
1259 }
1260
1261 #ifdef VDEC3
1262 }
1263 IsSent = FALSE;
1264 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1265 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1266 {
1267 do {
1268 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1269 if (!SentRet)
1270 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1271 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1272 break;
1273 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1274 IsSent = TRUE;
1275 break;
1276 }
1277 else if (HVD_GetSysTime_ms() > u32timeout)
1278 {
1279 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1280 break;
1281 }
1282 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1283 }
1284 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1285 {
1286 do {
1287 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1288 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1289 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1290 }
1291 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1292 break;
1293 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1294 IsSent = TRUE;
1295 break;
1296 }
1297 else if (HVD_GetSysTime_ms() > u32timeout)
1298 {
1299 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1300 break;
1301 }
1302 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1303 }
1304 if (!IsSent)
1305 {
1306 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1307 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1308 #else
1309 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1310
1311 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1312 #endif
1313 {
1314 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1315 if (HVD_GetSysTime_ms() > u32timeout)
1316 {
1317 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1318 return E_HVD_RETURN_TIMEOUT;
1319 }
1320 //#endif
1321 if(u32Cmd < E_DUAL_CMD_BASE)
1322 {
1323 //_HVD_EX_GetPC();
1324 HAL_HVD_EX_Dump_FW_Status(u32Id);
1325 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1326 }
1327 }
1328 #ifdef VDEC3
1329 }
1330 else
1331 {
1332 HAL_HVD_EX_FlushMemory();
1333 }
1334 #endif
1335 return E_HVD_RETURN_SUCCESS;
1336 }
1337
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1338 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1339 {
1340 #if HAL_HVD_ENABLE_MIU_PROTECT
1341 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
1342 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1343 #if SUPPORT_EVD
1344 _HVD_MIU_SetReqMask(EVD_RW1, bEnable);
1345 _HVD_MIU_SetReqMask(EVD_RW2, bEnable);
1346 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1347 #endif
1348 _HVD_MIU_SetReqMask(HVD_RW, bEnable);
1349 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1350 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1351 //HVD_Delay_ms(1);
1352 #endif
1353 return;
1354 }
1355
1356 #ifdef VDEC3
1357
1358 #if 0
1359 static MS_BOOL _HAL_EX_IS_HVD(MS_U32 u32ModeFlag) // VP8 isn't included
1360 {
1361 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1362
1363 if ((u32CodecType == E_HVD_INIT_HW_MVC) ||
1364 (u32CodecType == E_HVD_INIT_HW_AVC) ||
1365 (u32CodecType == E_HVD_INIT_HW_AVS) ||
1366 (u32CodecType == E_HVD_INIT_HW_RM))
1367 return TRUE;
1368
1369 return FALSE;
1370 }
1371 #endif //20170110
1372
1373 #if 0
1374 static MS_BOOL _HAL_EX_BBU_EVD_InUsed(void)
1375 {
1376 if (!pHVDHalContext)
1377 return FALSE;
1378
1379 MS_U32 i;
1380 MS_BOOL bRet = FALSE;
1381
1382 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1383 {
1384 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1385 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC)
1386 #if SUPPORT_MSVP9
1387 ||(pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP9)
1388 #endif
1389 ))
1390 {
1391 bRet = TRUE;
1392 break;
1393 }
1394 }
1395
1396 return bRet;
1397 }
1398
1399 static MS_BOOL _HAL_EX_BBU_HVD_InUsed(void) // VP8 isn't included
1400 {
1401 if (!pHVDHalContext)
1402 return FALSE;
1403
1404 MS_U32 i;
1405 MS_BOOL bRet = FALSE;
1406
1407 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1408 {
1409 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1410 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVC) ||
1411 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVS) ||
1412 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_RM)))
1413 {
1414 bRet = TRUE;
1415 break;
1416 }
1417 }
1418
1419 return bRet;
1420 }
1421
1422 #endif //20170110
1423 #endif
1424
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1425 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1426 {
1427 MS_U16 u16Reg = 0;
1428 MS_VIRT u32StAddr = 0;
1429 #ifdef VDEC3
1430 MS_U32 u32Length = 0;
1431 #endif
1432 //MS_BOOL bBitMIU1 = FALSE;
1433 //MS_BOOL bCodeMIU1 = FALSE;
1434 MS_U8 u8BitMiuSel = 0;
1435 MS_U8 u8CodeMiuSel = 0;
1436 MS_U8 u8FBMiuSel = 0;
1437 MS_U8 u8TmpMiuSel = 0;
1438
1439 MS_U32 u32BitStartOffset;
1440 MS_U32 u32CodeStartOffset;
1441 MS_U32 u32FBStartOffset;
1442
1443 #ifndef VDEC3
1444 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1445 #endif
1446 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1447 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1448 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1449 //HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1450
1451 _HAL_HVD_Entry();
1452 if(pCtrl == NULL) return;
1453
1454 MS_BOOL bESBufferAlreadySet = FALSE;
1455 VPU_EX_TaskInfo taskInfo;
1456 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1457
1458 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
1459
1460 bESBufferAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1461
1462
1463
1464 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1465 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1466 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1467
1468 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1469 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1470 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1471 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1472 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1473 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1474 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1475 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1476 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1477 (u8FBMiuSel << VDEC_PPIN_MIUSEL));
1478 #if 0
1479 if (u8BitMiuSel != u8CodeMiuSel)
1480 {
1481 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
1482 }
1483 else
1484 {
1485 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
1486 }
1487 #endif //20170110
1488
1489 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1490 {
1491 #if 0
1492 #ifdef VDEC3
1493 if (!_HAL_EX_BBU_VP8_InUsed())
1494 #endif
1495 {
1496 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1497
1498 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1499 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1500 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1501
1502 u32StAddr += VP8_BBU_TBL_SIZE;
1503
1504 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1505 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1506 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1507 }
1508 #endif //20170110
1509 // ES buffer
1510 #ifdef VDEC3
1511 if(pCtrl->bShareBBU )
1512 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1513 else
1514 #endif
1515 u32StAddr = u32BitStartOffset;
1516
1517 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1518
1519 #ifdef VDEC3
1520 if (!_HAL_EX_BBU_VP8_InUsed())
1521 #endif
1522 {
1523 HVD_EX_MSG_DBG("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1524
1525 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1526 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1527
1528 #ifdef VDEC3
1529 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1530 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1531 #else
1532 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1533 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1534 #endif
1535
1536 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1537 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1538 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1539 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1540 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1541 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1542 }
1543
1544 _HAL_HVD_Return();
1545 }
1546
1547 #if 0
1548 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1549
1550 HVD_EX_MSG_COVERITY("[%d]NAL start addr=%lx\n",u8TaskId, u32StAddr);
1551
1552 #ifdef VDEC3
1553 if (!pCtrl->bShareBBU || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1554 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1555 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1556 {
1557 if (pCtrl->u32BBUId == 0)
1558 {
1559 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1560 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1561 // -1 is for NAL_TAB_LEN counts from zero.
1562 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1563 }
1564 else
1565 {
1566 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1567 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1568 // -1 is for NAL_TAB_LEN counts from zero.
1569 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1570 }
1571 }
1572 #else
1573 if (0 == u8TaskId)
1574 {
1575 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1576 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1577 // -1 is for NAL_TAB_LEN counts from zero.
1578 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1579 }
1580 else
1581 {
1582 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1583 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1584 // -1 is for NAL_TAB_LEN counts from zero.
1585 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1586 }
1587 #endif
1588
1589 #endif //20170110
1590 // ES buffer
1591 #ifdef VDEC3
1592 if(!pCtrl->bShareBBU || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1593 {
1594 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1595 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1596 }
1597 else
1598 {
1599 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1600 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1601 }
1602 #else
1603 u32StAddr = u32BitStartOffset;
1604 #endif
1605
1606 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1607
1608 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1609
1610 #ifdef VDEC3
1611 #if 0
1612 if (!pCtrl->bShareBBU || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1613 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1614 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1615 #endif //20170110
1616 if (!bESBufferAlreadySet)
1617 {
1618 if (pCtrl->u32BBUId == 0)
1619 {
1620 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1621 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1622
1623 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1624 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1625 }
1626 else
1627 {
1628 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1629 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1630
1631 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1632 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1633 }
1634 }
1635 #else
1636 if (0 == u8TaskId)
1637 {
1638 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1639 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1640
1641 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1642 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1643 }
1644 else
1645 {
1646 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1647 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1648
1649 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1650 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1651 }
1652 #endif
1653
1654 // others
1655 #ifdef VDEC3
1656 #if 0
1657 if (!pCtrl->bShareBBU || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1658 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1659 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1660 #endif //20170110
1661 if (!bESBufferAlreadySet)
1662 {
1663 if (pCtrl->u32BBUId == 0)
1664 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1665 else
1666 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1667
1668 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1669 {
1670 if (pCtrl->u32BBUId == 0)
1671 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1672 else
1673 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1674 }
1675 else
1676 {
1677 if (pCtrl->u32BBUId == 0)
1678 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1679 else
1680 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1681 }
1682 #if 0
1683 if (_HVD_EX_IS_BBU_TSP_MODE(u32Id))
1684 {
1685 HVD_PRINT("\033[1;32m[%s] %d u16Reg &= ~HVD_REG_BBU_TSP_INPUT\033[m\n",__FUNCTION__,__LINE__);
1686 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1687 }
1688 #endif //20170110
1689
1690 if (pCtrl->u32BBUId == 0)
1691 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1692 else
1693 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1694
1695 #if 0
1696 if (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // RM
1697 {
1698 if (pCtrl->u32BBUId == 0) // force BBU to remove nothing, RM only
1699 u16Reg |= HVD_REG_BBU_PASER_DISABLE;
1700 else
1701 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2;
1702 }
1703 #if SUPPORT_MSVP9
1704 else if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1705 {
1706 if (pCtrl->u32BBUId == 0)
1707 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03;
1708 else
1709 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03_BS2;
1710 }
1711 #endif
1712 else // AVS or AVC or HEVC
1713 {
1714 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1715 {
1716 if (pCtrl->u32BBUId == 0)
1717 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1718 else
1719 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1720 }
1721 else // start code remained
1722 {
1723 if (pCtrl->u32BBUId == 0)
1724 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1725 else
1726 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1727 }
1728 }
1729 #endif //20170110
1730
1731 if (pCtrl->u32BBUId == 0)
1732 {
1733 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1734 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1735 }
1736 else
1737 {
1738 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1739 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1740 }
1741 }
1742 #else
1743 if (0 == u8TaskId)
1744 {
1745 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1746
1747 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1748 {
1749 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1750 }
1751 else
1752 {
1753 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1754 }
1755 #if 0
1756 if (_HVD_EX_IS_BBU_TSP_MODE(u32Id))
1757 {
1758 HVD_PRINT("\033[1;31m][%s][%s] %d u16Reg &= ~HVD_REG_BBU_TSP_INPUT\033[m\n",__FILE__,__FUNCTION__,__LINE__);
1759 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1760 }
1761 #endif //20170110
1762 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1763
1764 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1765 {
1766 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1767 }
1768 else // AVS or AVC
1769 {
1770 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1771 {
1772 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1773 }
1774 else // start code remained
1775 {
1776 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1777 }
1778 }
1779
1780 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1781
1782 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1783 }
1784 else
1785 {
1786 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1787
1788 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1789 {
1790 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1791 }
1792 else
1793 {
1794 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1795 }
1796
1797 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1798
1799 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1800 {
1801 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1802 }
1803 else // AVS or AVC
1804 {
1805 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1806 {
1807 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1808 }
1809 else // start code remained
1810 {
1811 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1812 }
1813 }
1814
1815 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1816
1817 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1818 }
1819 #endif
1820
1821 #if (HVD_ENABLE_MVC)
1822 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1823 {
1824 /// Used sub stream to record sub view data.
1825 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1826 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1827
1828 #if 0
1829 if (u8BitMiuSel != u8CodeMiuSel)
1830 {
1831 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
1832 }
1833 else
1834 {
1835 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
1836 }
1837
1838
1839 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", u32StAddr);
1840 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
1841 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
1842 // -1 is for NAL_TAB_LEN counts from zero.
1843 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1844
1845 #endif //20170110
1846 // ES buffer
1847 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1848
1849 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1850 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1851 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1852
1853 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1854 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1855
1856 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1857 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1858 {
1859 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1860 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1861 }
1862 else
1863 {
1864 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1865 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1866 }
1867 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1868 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1869 {
1870 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1871 }
1872 else // AVS or AVC
1873 {
1874 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1875 {
1876 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1877 }
1878 else // start code remained
1879 {
1880 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1881 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1882 }
1883 }
1884 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1885 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1886 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1887 }
1888 #endif
1889
1890 // MIF offset
1891 #if 0
1892 {
1893 MS_U16 offaddr = 0;
1894 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1895 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1896 {
1897 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1898 }
1899 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1900 offaddr = (MS_U16) ((u32StAddr) >> 20);
1901 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1902 //0x1FF; // 9 bits(L + H)
1903 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1904 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1905 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1906 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1907 {
1908 u16Reg |= HVD_REG_MIF_OFFSET_H;
1909 }
1910 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1911 }
1912 #endif
1913
1914 if (!bESBufferAlreadySet)
1915 {
1916 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1917 }
1918
1919 _HAL_HVD_Return();
1920 }
1921
1922 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1923 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1924 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1925 {
1926 MS_U16 u16Reg = 0;
1927 MS_U32 u32StAddr = 0;
1928 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1929 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1930 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1931
1932 if(pCtrl == NULL) return;
1933
1934 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1935 {
1936 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1937
1938 // ES buffer
1939 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1940
1941 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1942 {
1943 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1944 }
1945
1946 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1947 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1948
1949 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1950 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1951
1952 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1953 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1954 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1955 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1956 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1957 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1958
1959 return;
1960 }
1961
1962 // ES buffer
1963 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1964
1965 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1966 {
1967 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1968 }
1969
1970 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1971
1972 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1973 {
1974 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1975 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1976
1977 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1978 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1979 }
1980 else
1981 {
1982 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1983 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1984
1985 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1986 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1987 }
1988 }
1989 #endif
1990
_HVD_EX_GetESLevel(MS_U32 u32Id)1991 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1992 {
1993 MS_U32 u32Wptr = 0;
1994 MS_U32 u32Rptr = 0;
1995 MS_U32 u32CurMBX = 0;
1996 MS_U32 u32ESsize = 0;
1997 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1998 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1999
2000 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2001 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2002 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2003
2004 if (u32Rptr >= u32Wptr)
2005 {
2006 u32CurMBX = u32Rptr - u32Wptr;
2007 }
2008 else
2009 {
2010 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
2011 }
2012
2013 if (u32CurMBX == 0)
2014 {
2015 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2016 }
2017 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
2018 {
2019 u32Ret = E_HVD_ESB_LEVEL_OVER;
2020 }
2021 else
2022 {
2023 u32CurMBX = u32ESsize - u32CurMBX;
2024 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
2025 {
2026 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2027 }
2028 }
2029
2030 return u32Ret;
2031 }
2032
_HVD_EX_GetESQuantity(MS_U32 u32Id)2033 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
2034 {
2035 MS_U32 u32Wptr = 0;
2036 MS_U32 u32Rptr = 0;
2037 MS_U32 u32ESsize = 0;
2038 MS_U32 u32Ret = 0;
2039 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2040
2041 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2042 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2043 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2044
2045
2046 if(u32Wptr >= u32Rptr)
2047 {
2048 u32Ret = u32Wptr - u32Rptr;
2049 }
2050 else
2051 {
2052 u32Ret = u32ESsize - u32Rptr + u32Wptr;
2053 }
2054 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
2055 return u32Ret;
2056 }
2057
2058 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)2059 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
2060 {
2061
2062 MS_U32 u32Timeout = 20000;
2063
2064 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
2065 {
2066
2067 HAL_VPU_EX_IQMemSetDAMode(TRUE);
2068
2069 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
2070
2071
2072 while (u32Timeout)
2073 {
2074
2075 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
2076 {
2077 break;
2078 }
2079 u32Timeout--;
2080 HVD_Delay_ms(1);
2081 }
2082
2083 HAL_VPU_EX_IQMemSetDAMode(FALSE);
2084
2085 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
2086
2087 if (u32Timeout==0)
2088 {
2089 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
2090 return FALSE;
2091 }
2092
2093
2094 }
2095 return TRUE;
2096 }
2097
2098 #endif
2099
2100 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2101 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2102 #else
2103 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2104 #endif
2105 {
2106 MS_U32 u32FirmVer = 0;
2107 MS_U32 u32Timeout = 20000;
2108 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2109
2110 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2111
2112 #if HVD_ENABLE_TIME_MEASURE
2113 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2114 #endif
2115
2116 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2117
2118 VPU_EX_FWCodeCfg fwCfg;
2119 VPU_EX_TaskInfo taskInfo;
2120 VPU_EX_VLCTblCfg vlcCfg;
2121 #ifdef VDEC3
2122 VPU_EX_FBCfg fbCfg;
2123 #endif
2124 VPU_EX_NDecInitPara nDecInitPara;
2125
2126 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2127 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2128 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2129 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2130 #ifdef VDEC3_FB
2131 nDecInitPara.pVLCCfg = NULL;
2132 #else
2133 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2134 {
2135 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2136 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2137 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2138 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2139 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2140 nDecInitPara.pVLCCfg = &vlcCfg;
2141 }
2142 #endif
2143 nDecInitPara.pFWCodeCfg = &fwCfg;
2144 nDecInitPara.pTaskInfo = &taskInfo;
2145 #ifdef VDEC3
2146 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2147 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2148
2149 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2150 {
2151 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2152 }
2153
2154 nDecInitPara.pFBCfg = &fbCfg;
2155 #endif
2156
2157 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2158 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2159 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2160 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2161 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2162
2163 taskInfo.u32Id = u32Id;
2164
2165 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2166 {
2167 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2168 }
2169 #ifdef VDEC3
2170 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
2171 {
2172 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2173 }
2174 #if SUPPORT_MSVP9
2175 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2176 {
2177 HVD_PRINT("SUPPORT_MSVP9\n");
2178 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2179 }
2180 #endif
2181 #if SUPPORT_G2VP9
2182 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2183 {
2184 HVD_PRINT("SUPPORT_G2VP9\n");
2185 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2186 }
2187 #endif
2188 #endif
2189 else
2190 {
2191 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2192 }
2193
2194 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2195
2196 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2197 {
2198 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2199 }
2200 else
2201 {
2202 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2203 }
2204 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2205
2206 #ifdef SUPPORT_EVD
2207 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2208 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2209 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2210 #endif
2211
2212 if(TRUE == HVD_EX_GetRstFlag())
2213 {
2214 //Delete task for Rst
2215 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2216 {
2217 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2218 }
2219 HVD_EX_SetRstFlag(FALSE);
2220 }
2221
2222 #if (HVD_ENABLE_IQMEM)
2223 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2224 #endif
2225
2226 #ifdef VDEC3
2227 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2228 #else
2229 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2230 #endif
2231 {
2232 HVD_EX_MSG_ERR("Task create fail!\n");
2233
2234 return FALSE;
2235 }
2236
2237 while (u32Timeout)
2238 {
2239 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2240
2241 if (u32FirmVer != 0)
2242 {
2243 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2244 break;
2245 }
2246 u32Timeout--;
2247 HVD_Delay_ms(1);
2248 }
2249
2250 #ifdef VDEC3_FB
2251 #if HVD_ENABLE_RV_FEATURE
2252 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2253
2254 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2255 {
2256 if(pShm->u32RM_VLCTableAddr == 0) {
2257 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2258 }
2259 else
2260 {
2261 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr+pShm->u32RM_VLCTableAddr));
2262 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2263 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2264 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2265 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2266 nDecInitPara.pVLCCfg = &vlcCfg;
2267 }
2268 }
2269
2270 if (nDecInitPara.pVLCCfg)
2271 {
2272 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2273 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2274 {
2275 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2276 return FALSE;
2277 }
2278 }
2279 #endif
2280 #endif
2281 if (u32Timeout > 0)
2282 {
2283 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2284
2285 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2286
2287 #ifdef VDEC3
2288 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2289 {
2290 case E_HVD_INIT_HW_AVC:
2291 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2292 break;
2293 case E_HVD_INIT_HW_AVS:
2294 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2295 break;
2296 case E_HVD_INIT_HW_RM:
2297 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2298 break;
2299 case E_HVD_INIT_HW_MVC:
2300 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2301 break;
2302 case E_HVD_INIT_HW_VP8:
2303 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2304 break;
2305 case E_HVD_INIT_HW_MJPEG:
2306 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2307 break;
2308 case E_HVD_INIT_HW_VP6:
2309 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2310 break;
2311 case E_HVD_INIT_HW_HEVC:
2312 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2313 break;
2314 case E_HVD_INIT_HW_VP9:
2315 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2316 break;
2317 default:
2318 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2319 break;
2320 }
2321 #endif
2322
2323 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2324 }
2325 else
2326 {
2327 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2328 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2329
2330 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2331 {
2332 HVD_EX_MSG_ERR("Task delete fail!\n");
2333 }
2334
2335 return FALSE;
2336 }
2337
2338
2339
2340 #if (HVD_ENABLE_IQMEM)
2341
2342 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2343 {
2344
2345 HAL_HVD_EX_IQMem_Init(u32Id);
2346 }
2347 else{
2348 HVD_EX_MSG_DBG("not support IQMEM\n");
2349 }
2350 #endif
2351
2352
2353
2354
2355
2356
2357 #if HVD_ENABLE_TIME_MEASURE
2358 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2359 #endif
2360
2361 return TRUE;
2362 }
2363
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2364 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2365 {
2366 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2367 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2368 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2369 {
2370 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2371 }
2372 else
2373 {
2374 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2375 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2376 }
2377 }
2378
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2379 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2380 {
2381 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2382 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2383
2384 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2385 {
2386 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2387 }
2388 else
2389 {
2390 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2391 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2392 }
2393 }
2394
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2395 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2396 {
2397 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2398 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2399
2400 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2401 {
2402 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2403 {
2404 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2405 }
2406 }
2407 else
2408 {
2409 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2410 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2411 }
2412 }
2413
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2414 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2415 {
2416 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2417 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2418 MS_VIRT u32DestAddr = 0;
2419 HVD_PTS_Entry PTSEntry;
2420 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2421 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2422 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2423
2424 // update R & W ptr
2425 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2426
2427 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2428
2429 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2430 {
2431 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2432 (MS_U32) MAX_PTS_TABLE_SIZE);
2433 return E_HVD_RETURN_FAIL;
2434 }
2435
2436 // check queue is full or not
2437 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2438 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2439
2440 if (u32PTSWptr == u32PTSRptr)
2441 {
2442 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2443 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2444 return E_HVD_RETURN_FAIL;
2445 }
2446
2447 // add one PTS entry
2448 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2449 PTSEntry.u32ID_L = pInfo->u32ID_L;
2450 PTSEntry.u32ID_H = pInfo->u32ID_H;
2451 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2452
2453 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2454
2455 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2456
2457 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2458
2459 HAL_HVD_EX_FlushMemory();
2460
2461 // update Write ptr
2462 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2463
2464 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2465
2466 return E_HVD_RETURN_SUCCESS;
2467 }
2468
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2469 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2470 {
2471 //---------------------------------------------------
2472 // item format in nal table:
2473 // reserved |borken| u32NalOffset | u32NalLen
2474 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2475 //---------------------------------------------------
2476 MS_VIRT u32Adr = 0;
2477 MS_U32 u32BBUNewWptr = 0;
2478 MS_U8 item[8];
2479 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2480 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2481 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2482 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2483
2484 #if HVD_ENABLE_MVC
2485 if(HAL_HVD_EX_CheckMVCID(u32Id))
2486 {
2487 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2488 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2489 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2490 {
2491 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2492 }
2493 }
2494 #endif /// HVD_ENABLE_MVC
2495
2496 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2497 {
2498 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2499 }
2500 else
2501 {
2502 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2503 }
2504 u32BBUNewWptr++;
2505 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2506
2507 // prepare nal entry
2508
2509 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2510 {
2511 // NAL len 22 bits , HEVC level5 constrain
2512 item[0] = u32NalLen & 0xff;
2513 item[1] = (u32NalLen >> 8) & 0xff;
2514 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2515 item[3] = (u32NalOffset >> 2) & 0xff;
2516 item[4] = (u32NalOffset >> 10) & 0xff;
2517 item[5] = (u32NalOffset >> 18) & 0xff;
2518 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2519 item[7] = 0;
2520 }
2521 else
2522 {
2523 item[0] = u32NalLen & 0xff;
2524 item[1] = (u32NalLen >> 8) & 0xff;
2525 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2526 item[3] = (u32NalOffset >> 3) & 0xff;
2527 item[4] = (u32NalOffset >> 11) & 0xff;
2528 item[5] = (u32NalOffset >> 19) & 0xff;
2529 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2530 item[7] = 0;
2531 }
2532
2533 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2534 {
2535 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2536 }
2537 else
2538 {
2539 // add nal entry
2540 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2541 }
2542
2543 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2544
2545 HAL_HVD_EX_FlushMemory();
2546
2547 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2548
2549 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2550 {
2551 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2552 }
2553 else
2554 {
2555 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2556 }
2557
2558 return E_HVD_RETURN_SUCCESS;
2559 }
2560
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2561 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2562 {
2563 MS_U8 item[8];
2564 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2565 MS_VIRT u32Adr = 0;
2566 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2567 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2568 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2569
2570 /*
2571 printf("nal2 offset=0x%x, len=0x%x\n",
2572 u32NalOffset2, u32NalLen2);
2573 */
2574
2575 item[0] = u32NalLen2 & 0xff;
2576 item[1] = (u32NalLen2 >> 8) & 0xff;
2577 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2578 item[3] = (u32NalOffset2 >> 3) & 0xff;
2579 item[4] = (u32NalOffset2 >> 11) & 0xff;
2580 item[5] = (u32NalOffset2 >> 19) & 0xff;
2581 item[6] = (u32NalOffset2 >> 27) & 0x07;
2582 item[7] = 0;
2583
2584 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2585 {
2586 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2587 }
2588 else
2589 {
2590 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2591 }
2592
2593 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2594
2595 HAL_HVD_EX_FlushMemory();
2596
2597 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2598 }
2599
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2600 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2601 {
2602 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2603 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2604
2605 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2606 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2607 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2608 {
2609 MS_U16 i;
2610 MS_PHY u32VUIAddr;
2611 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2612
2613 HAL_HVD_EX_ReadMemory();
2614 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2615
2616 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2617 {
2618 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2619 {
2620 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2621 }
2622 else
2623 {
2624 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2625 }
2626 pData++;
2627 }
2628 }
2629 else
2630 {
2631 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2632 }
2633
2634 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2635 }
2636
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2637 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2638 {
2639 MS_U32 u32ReadPtr = 0;
2640 MS_U32 eRet = 0;
2641 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2642 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2643
2644 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2645 MS_U32 u32WritePtr = 0;
2646
2647 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2648 {
2649 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2650 }
2651 else
2652 {
2653 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2654 }
2655
2656 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2657
2658 if (u32WritePtr >= u32ReadPtr)
2659 {
2660 eRet = u32WritePtr - u32ReadPtr;
2661 }
2662 else
2663 {
2664 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2665 }
2666
2667 #if 0
2668 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2669 {
2670 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2671 }
2672 else
2673 {
2674 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2675 }
2676
2677 #endif
2678 return eRet;
2679 }
2680
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2681 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2682 {
2683 MS_U32 u32ReadPtr = 0;
2684 MS_U32 eRet = 0;
2685 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2686
2687 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2688
2689 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2690 {
2691 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2692 (MS_U32) MAX_PTS_TABLE_SIZE);
2693 return 0;
2694 }
2695
2696 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2697
2698 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2699 {
2700 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2701 }
2702 else
2703 {
2704 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2705 }
2706
2707 return eRet;
2708 }
2709
2710 #if 0
2711 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2712 {
2713 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2714
2715 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2716 }
2717 #endif //20170110
2718
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2719 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2720 {
2721 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2722 MS_U16 u16QNum = pShm->u16DispQNumb;
2723 MS_U16 u16QPtr = pShm->u16DispQPtr;
2724 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2725
2726 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
2727 HVD_Frm_Information *pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2728 #if (HVD_ENABLE_MVC)
2729 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2730
2731 if(bMVC)
2732 {
2733 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2734 {
2735 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2736 MS_U16 u16UsedFrm = 0;
2737 MS_U16 u16ResvFrmNum = ((u16RealQPtr % 2) == 0) ? 1 : 0; // need to check the next frame num is exist when get first frame.
2738 if (u16RealQPtr != u16QPtr)
2739 {
2740 if (u16RealQPtr > u16QPtr)
2741 {
2742 u16UsedFrm = u16RealQPtr - u16QPtr;
2743 }
2744 else
2745 {
2746 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2747 }
2748 }
2749
2750 if (u16QNum > (u16UsedFrm + u16ResvFrmNum))
2751 {
2752 u16QNum -= u16UsedFrm;
2753 u16QPtr = u16RealQPtr;
2754 pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2755
2756 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2757 {
2758 if ((u16QPtr % 2) == 0)
2759 {
2760 HVD_Frm_Information *pHvdFrmNext = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr + 1];
2761
2762 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2763 {
2764 return NULL;
2765 }
2766
2767 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2768 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2769 }
2770 else
2771 {
2772 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2773 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2774 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2775
2776 HVD_Frm_Information *pHvdFrmPrv = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1]; // must be odd
2777 pHvdFrmPrv->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2778 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2779 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2780 }
2781 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2782 u16QPtr++;
2783 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2784 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2785
2786 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2787 }
2788 }
2789
2790 return NULL;
2791 }
2792
2793 /* Add for Mobile Platform by Ted Sun */
2794 #if 0
2795 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
2796 {
2797 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
2798 }
2799 #endif
2800
2801 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2802 //search the next frame to display
2803 while (u16QNum > 0)
2804 {
2805 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2806 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2807 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2808
2809 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2810 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2811 {
2812 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2813 /// Check the depned view was initial when Output the base view.
2814 if((u16QPtr%2) == 0)
2815 {
2816 HVD_Frm_Information *pHvdFrm_sub = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2817 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2818 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2819 {
2820 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2821 ///printf("Return NULL.\n");
2822 return NULL;
2823 }
2824 }
2825
2826 //printf("V:%d.\n",u16QPtr);
2827 pHVDHalContext->_u16DispQPtr = u16QPtr;
2828 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2829 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2830 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2831 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2832 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2833 }
2834
2835 u16QNum--;
2836 //go to next frame in the dispQ
2837 u16QPtr++;
2838
2839 if (u16QPtr >= pShm->u16DispQSize)
2840 {
2841 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2842 }
2843 }
2844 }
2845 else
2846 #endif ///HVD_ENABLE_MVC
2847 {
2848 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2849 {
2850
2851 while (u16QNum != 0)
2852 {
2853 pHvdFrm = (HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2854
2855 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2856 {
2857 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2858 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2859 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2860 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2861 }
2862 u16QNum--;
2863 //go to next frame in the dispQ
2864 u16QPtr++;
2865
2866 if (u16QPtr >= pShm->u16DispQSize)
2867 {
2868 u16QPtr = 0; //wrap to the begin
2869 }
2870
2871 }
2872
2873
2874
2875 return NULL;
2876 }
2877 /* Add for Mobile Platform by Ted Sun */
2878 #if 0
2879 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
2880 {
2881 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
2882 }
2883 #endif
2884 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2885 //search the next frame to display
2886 while (u16QNum != 0)
2887 {
2888 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2889
2890 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2891 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2892 {
2893 pHVDHalContext->_u16DispQPtr = u16QPtr;
2894 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2895 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2896 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2897 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2898 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2899 }
2900
2901 u16QNum--;
2902 //go to next frame in the dispQ
2903 u16QPtr++;
2904
2905 if (u16QPtr == pShm->u16DispQSize)
2906 {
2907 u16QPtr = 0; //wrap to the begin
2908 }
2909 }
2910 }
2911
2912 return NULL;
2913 }
2914
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2915 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2916 {
2917 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2918 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2919 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2920 {
2921 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2922 if(pVsyncBridgeExt != NULL)
2923 {
2924 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2925 }
2926 }
2927 return pFrmInfoExt;
2928 }
2929
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2930 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2931 {
2932 #if (SUPPORT_EVD || SUPPORT_MSVP9)
2933 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2934 #endif
2935 MS_U64 u64Ret = 0;
2936
2937 #if SUPPORT_EVD
2938 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
2939 if (isEVD)
2940 {
2941 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2942 }
2943 else
2944 #endif
2945 #if SUPPORT_G2VP9
2946 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2947 {
2948 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2949 }
2950 else
2951 #endif
2952 {
2953 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2954 }
2955
2956 return u64Ret;
2957 }
2958
2959 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2960 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2961 {
2962 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2963 MS_U16 u16QNum = pShm->u16DispQNumb;
2964 MS_U16 u16QPtr = pShm->u16DispQPtr;
2965 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2966
2967 #if (HVD_ENABLE_MVC)
2968 if (HAL_HVD_EX_CheckMVCID(u32Id))
2969 {
2970 if (u16QNum == 1) return TRUE;
2971 }
2972 #endif
2973
2974 while (u16QNum != 0)
2975 {
2976 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2977 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2978 {
2979 return FALSE;
2980 }
2981 u16QNum--;
2982 u16QPtr++;
2983
2984 if (u16QPtr >= pShm->u16DispQSize)
2985 {
2986 u16QPtr = 0; //wrap to the begin
2987 }
2988 }
2989
2990 return TRUE;
2991 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2992 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2993 {
2994 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2995
2996 return &(_pHVDCtrls[u8DrvId]);
2997 }
2998
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2999 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
3000 {
3001 MS_U8 u8OffsetIdx = 0;
3002 MS_U8 u8SidBaseMask = 0xF0;
3003 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
3004
3005 switch (eSidBase)
3006 {
3007 case E_HAL_HVD_MAIN_STREAM_BASE:
3008 {
3009 u8OffsetIdx = 0;
3010 break;
3011 }
3012 case E_HAL_VPU_SUB_STREAM_BASE:
3013 {
3014 u8OffsetIdx = 1;
3015 break;
3016 }
3017 case E_HAL_VPU_MVC_STREAM_BASE:
3018 {
3019 u8OffsetIdx = 0;
3020 break;
3021 }
3022 #ifdef VDEC3
3023 case E_HAL_VPU_N_STREAM_BASE:
3024 {
3025 u8OffsetIdx = (u32Id>>8) & 0xF;
3026 break;
3027 }
3028 #endif
3029 default:
3030 {
3031 u8OffsetIdx = 0;
3032 break;
3033 }
3034 }
3035
3036 return u8OffsetIdx;
3037 }
3038 /*
3039 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3040 {
3041 MS_U32 i = 0;
3042 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3043 {
3044 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
3045 {
3046 return TRUE;
3047 }
3048 }
3049 return FALSE;
3050 }
3051 */
3052
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3053 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3054 {
3055 MS_PHY u32PhyAddr = 0x0;
3056 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3057
3058 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3059 {
3060 return 0;
3061 }
3062
3063 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3064
3065 if (u32PhyAddr == 0xFFFFFFFFUL)
3066 {
3067 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3068 }
3069 else
3070 {
3071 // TEE, common + share_info
3072 u32PhyAddr += COMMON_AREA_SIZE;
3073 }
3074
3075 return MsOS_PA2KSEG1(u32PhyAddr);
3076 }
3077 /*
3078 void HAL_HVD_MVDMiuClientSel(MS_U8 u8MiuSel)
3079 {
3080 if (u8MiuSel == 0)
3081 {
3082 _HVD_WriteWordMask(MIU_CLIENT_SELECT_GP2, 0, MIU_CLIENT_SELECT_GP2_MVD);
3083 }
3084 else
3085 {
3086 _HVD_WriteWordMask(MIU_CLIENT_SELECT_GP2, MIU_CLIENT_SELECT_GP2_MVD, MIU_CLIENT_SELECT_GP2_MVD);
3087 }
3088 }
3089 */
3090
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3091 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3092 {
3093 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3094 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3095
3096 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3097 {
3098 return 0;
3099 }
3100
3101 MS_PHY u32PhyAddr = 0x0;
3102 #if 0
3103 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3104
3105 if (u32PhyAddr == 0xFFFFFFFF)
3106 {
3107 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3108 }
3109 #endif
3110 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3111 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3112
3113 return MsOS_PA2KSEG1(u32PhyAddr);
3114 }
3115
3116
3117 #if SUPPORT_G2VP9 && defined(VDEC3)
3118
3119
3120 #ifdef __ARM_NEON__
3121 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3122 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3123 {
3124 uint32x4x4_t data, data2;
3125 MS_U8* raster2 = raster + tile_w * 4;
3126
3127 data = vld4q_u32((const uint32_t *)tile);
3128 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3129
3130 vst1q_u32((uint32_t *)raster, data.val[0]);
3131 raster += stride;
3132 vst1q_u32((uint32_t *)raster, data.val[1]);
3133 raster += stride;
3134 vst1q_u32((uint32_t *)raster, data.val[2]);
3135 raster += stride;
3136 vst1q_u32((uint32_t *)raster, data.val[3]);
3137
3138
3139 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3140 raster2 += stride;
3141 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3142 raster2 += stride;
3143 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3144 raster2 += stride;
3145 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3146 }
3147 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3148 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3149 {
3150 MS_U8* tile0 = tile;
3151 MS_U8* tile1 = tile+16;
3152 MS_U8* tile2 = tile+32;
3153 MS_U8* tile3 = tile+48;
3154 int i;
3155
3156 for (i=0; i<4; i++) {
3157 raster[i] = tile0[i];
3158 raster[4+i] = tile1[i];
3159 raster[8+i] = tile2[i];
3160 raster[12+i] = tile3[i];
3161 }
3162
3163 for (i=0; i<4; i++) {
3164 raster[stride+i] = tile0[4+i];
3165 raster[stride+4+i] = tile1[4+i];
3166 raster[stride+8+i] = tile2[4+i];
3167 raster[stride+12+i] = tile3[4+i];
3168 }
3169
3170 for (i=0; i<4; i++) {
3171 raster[2*stride+i] = tile0[8+i];
3172 raster[2*stride+4+i] = tile1[8+i];
3173 raster[2*stride+8+i] = tile2[8+i];
3174 raster[2*stride+12+i] = tile3[8+i];
3175 }
3176
3177 for (i=0; i<4; i++) {
3178 raster[3*stride+i] = tile0[12+i];
3179 raster[3*stride+4+i] = tile1[12+i];
3180 raster[3*stride+8+i] = tile2[12+i];
3181 raster[3*stride+12+i] = tile3[12+i];
3182 }
3183 }
3184 #endif
3185
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3186 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3187 {
3188 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3189 u32Id,
3190 E_TASK_PRI_MEDIUM,
3191 TRUE,
3192 NULL,
3193 32, // stack size..
3194 "HVD_PostProcess_task");
3195
3196 if (s32HvdPpTaskId < 0)
3197 {
3198 HVD_EX_MSG_ERR("Pp Task create failed\n");
3199
3200 return FALSE;
3201 }
3202
3203 HVD_EX_MSG_DBG("Pp Task create success\n");
3204 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3205
3206 return TRUE;
3207 }
3208
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3209 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3210 {
3211 return y * stride * h + x * w * h;
3212 }
3213
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3214 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3215 {
3216 return y * stride * h + x * w;
3217 }
3218
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3219 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3220 {
3221 raster[0] = tile[0];
3222 raster[1] = tile[1];
3223 raster[2] = tile[2];
3224 raster[3] = tile[3];
3225 raster[stride] = tile[4];
3226 raster[stride + 1] = tile[5];
3227 raster[stride + 2] = tile[6];
3228 raster[stride + 3] = tile[7];
3229 raster[2 * stride] = tile[8];
3230 raster[2 * stride + 1] = tile[9];
3231 raster[2 * stride + 2] = tile[10];
3232 raster[2 * stride + 3] = tile[11];
3233 raster[3 * stride] = tile[12];
3234 raster[3 * stride + 1] = tile[13];
3235 raster[3 * stride + 2] = tile[14];
3236 raster[3 * stride + 3] = tile[15];
3237 }
3238
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3239 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3240 {
3241 const MS_U32 tile_w = 4;
3242 const MS_U32 tile_h = 4;
3243 MS_U32 tile_stride = w;
3244 MS_U32 x, y;
3245 MS_U8 *dst1, *dst2;
3246 MS_U8 *src1, *src2;
3247
3248 #ifdef __ARM_NEON__
3249 // To overlap load and store, handle two blocks at the same time.
3250 dst1 = dst;
3251 src1 = src;
3252 for (y = 0; y < h / tile_h; y++)
3253 {
3254 dst2 = dst1;
3255 src2 = src1;
3256 for (x = 0; x <= (w/tile_w - 8); x+=8)
3257 {
3258 tile4x4_to_raster_8(
3259 dst2,
3260 src2,
3261 raster_stride, tile_w, tile_h);
3262 dst2 += tile_w * 8;
3263 src2 += tile_w * tile_h * 8;
3264 }
3265 dst1 += raster_stride * tile_h;
3266 src1 += tile_stride * tile_h;
3267 for (; x < w / tile_w; x++)
3268 {
3269 tile4x4_to_raster(
3270 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3271 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3272 raster_stride);
3273 }
3274 }
3275 #else
3276 dst1 = NULL;
3277 src1 = NULL;
3278 dst2 = NULL;
3279 src2 = NULL;
3280
3281 for (y = 0; y < h / tile_h; y++)
3282 {
3283 for (x = 0; x <= (w/tile_w - 4); x+=4)
3284 {
3285 tile4x4_to_raster_4(
3286 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3287 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3288 raster_stride);
3289 }
3290 for (; x < w / tile_w; x++)
3291 {
3292 tile4x4_to_raster(
3293 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3294 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3295 raster_stride);
3296 }
3297 }
3298 #endif
3299 }
3300
3301 #define FLUSH_CACHE_SIZE (256 * 1024)
3302
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3303 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3304 {
3305 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3306 if (u32Size > FLUSH_CACHE_SIZE)
3307 u32Size = FLUSH_CACHE_SIZE;
3308
3309 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);//20170110
3310 }
3311
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3312 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3313 {
3314 MS_U32 u32SkipSize = 0;
3315
3316 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3317 if (u32Size > FLUSH_CACHE_SIZE)
3318 {
3319 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3320 u32Size = FLUSH_CACHE_SIZE;
3321 }
3322
3323 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3324 }
3325
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3326 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3327 {
3328 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3329 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3330 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3331 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3332
3333 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3334
3335 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3336
3337 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3338 {
3339 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3340 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3341
3342 HVD_Delay_ms(1); // FIXME
3343
3344 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3345 continue;
3346
3347 HAL_HVD_EX_ReadMemory();
3348
3349 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3350 {
3351 MS_U8 *pSrcVA, *pDstVA;
3352 MS_U32 u32SrcPA, u32DstPA;
3353 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3354 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3355
3356 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3357 {
3358 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3359
3360 u16Width = pFrmInfo->u16Width;
3361 u16Height = pFrmInfo->u16Height;
3362 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3363 }
3364
3365 // Luma
3366 u32SrcMiuSel = pFrmInfo->u2Luma1Miu;
3367 u32DstMiuSel = pFrmInfo->u2Luma0Miu;
3368
3369 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3370 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3371
3372 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3373 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3374
3375 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3376
3377 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3378
3379 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3380
3381 // Chroma
3382 u32SrcMiuSel = pFrmInfo->u2Chroma1Miu;
3383 u32DstMiuSel = pFrmInfo->u2Chroma0Miu;
3384
3385 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3386 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3387
3388 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3389 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3390
3391 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3392
3393 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3394
3395 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3396
3397 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3398 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3399 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3400
3401 HAL_HVD_EX_FlushMemory();
3402
3403 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3404 break;
3405
3406 HAL_HVD_EX_ReadMemory();
3407 }
3408 }
3409
3410 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3411
3412 return TRUE;
3413 }
3414 #endif
3415
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3416 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3417 {
3418 #ifndef VDEC3
3419 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3420 #endif
3421 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3422 MS_BOOL isEVD = FALSE;
3423 //MS_U8 u8MiuSel;
3424 //MS_U32 u32StartOffset;
3425
3426 if(pCtrl == NULL)
3427 {
3428 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3429 //return FALSE;
3430 goto RESET;
3431 }
3432
3433 #if SUPPORT_EVD
3434 isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
3435 #endif
3436
3437 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3438 // re-setup clock.
3439 #if SUPPORT_G2VP9 && defined(VDEC3)
3440 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3441 #endif
3442 if (!HAL_VPU_EX_HVDInUsed())
3443 {
3444 printf("HVD power on\n");
3445 HAL_HVD_EX_PowerCtrl(TRUE);
3446 }
3447
3448 #if SUPPORT_EVD
3449 if (isEVD)
3450 {
3451 #ifdef VDEC3
3452 if (!HAL_VPU_EX_EVDInUsed())
3453 #endif
3454 {
3455 printf("EVD power on\n");
3456 HAL_EVD_EX_PowerCtrl(TRUE);
3457 }
3458 }
3459 #endif
3460
3461 #if SUPPORT_G2VP9 && defined(VDEC3)
3462 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3463 {
3464 if (!HAL_VPU_EX_G2VP9InUsed())
3465 {
3466 printf("G2 VP9 power on\n");
3467 HAL_VP9_EX_PowerCtrl(TRUE);
3468 }
3469 }
3470 #endif
3471
3472 if ((!HAL_VPU_EX_HVDInUsed()) && (DecoderType != E_VPU_EX_DECODER_MVD))
3473 {
3474 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3475 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3476 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3477 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3478
3479 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3480
3481 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
3482 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3483 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256);
3484 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256);
3485 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128);
3486 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128);
3487
3488 /*
3489 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3490 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3491 {
3492 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr >= HAL_MIU1_BASE)
3493 {
3494 _HAL_HVD_Entry();
3495 HAL_HVD_MVDMiuClientSel(1);
3496 _HAL_HVD_Release();
3497 }
3498 else
3499 {
3500 _HAL_HVD_Entry();
3501 HAL_HVD_MVDMiuClientSel(0);
3502 _HAL_HVD_Release();
3503 }
3504 }*/
3505 }
3506
3507 #if SUPPORT_EVD
3508 if (isEVD)
3509 {
3510 #ifdef VDEC3
3511 if (!HAL_VPU_EX_EVDInUsed())
3512 #endif
3513 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3514 }
3515 #endif
3516
3517 #if SUPPORT_G2VP9 && defined(VDEC3)
3518 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3519 {
3520 if (!HAL_VPU_EX_G2VP9InUsed())
3521 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3522 }
3523 #endif
3524
3525 #if SUPPORT_EVD
3526 if (isEVD)
3527 {
3528 #ifdef VDEC3
3529 if (!HAL_VPU_EX_EVDInUsed())
3530 #endif
3531 {
3532 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3533 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3534 }
3535
3536 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3537 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3538 {
3539 #ifdef VDEC3
3540 if (0 == pCtrl->u32BBUId)
3541 #else
3542 if (0 == u8TaskId)
3543 #endif
3544 {
3545 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3546 }
3547 else
3548 {
3549 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3550 }
3551 }
3552 goto RESET;
3553 }
3554 #endif
3555
3556 // HVD4, from JANUS and later chip
3557 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3558 {
3559 case E_HVD_INIT_HW_AVS:
3560 {
3561 #ifdef VDEC3
3562 if (0 == pCtrl->u32BBUId)
3563 #else
3564 if (0 == u8TaskId)
3565 #endif
3566 {
3567 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3568 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3569 }
3570 else
3571 {
3572 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3573 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3574 }
3575
3576 break;
3577 }
3578 case E_HVD_INIT_HW_RM:
3579 {
3580 #ifdef VDEC3
3581 if (0 == pCtrl->u32BBUId)
3582 #else
3583 if (0 == u8TaskId)
3584 #endif
3585 {
3586 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3587 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3588
3589 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3590 {
3591 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3592 }
3593 else // RV 8
3594 {
3595 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3596 }
3597 }
3598 else
3599 {
3600 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3601 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3602
3603 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3604 {
3605 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3606 }
3607 else // RV 8
3608 {
3609 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3610 }
3611
3612 }
3613
3614 break;
3615 }
3616 default:
3617 {
3618 #ifdef VDEC3
3619 if (0 == pCtrl->u32BBUId)
3620 #else
3621 if (0 == u8TaskId)
3622 #endif
3623 {
3624 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3625 }
3626 else
3627 {
3628 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3629 }
3630 break;
3631 }
3632 }
3633
3634 RESET:
3635 //T9: use miu128bit
3636 #if 0
3637 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3638
3639 if (!HAL_VPU_EX_HVDInUsed())
3640 {
3641 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3642 }
3643
3644 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3645 #endif
3646
3647 #if SUPPORT_EVD
3648 if (isEVD)
3649 {
3650 #ifdef VDEC3
3651 if (!HAL_VPU_EX_EVDInUsed())
3652 #endif
3653 {
3654 printf("EVD miu 256 bits\n");
3655 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3656 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3657 }
3658 }
3659
3660 // This is for Clippers, Miami and Munich using 128 bits bbu
3661 if (isEVD)
3662 {
3663 printf("EVD BBU 256 bits\n");
3664 _HVD_Write2Byte(EVD_REG_BBU_MIU_WIDTH, EVD_REG_BBU_MIU_256);
3665 }
3666 #endif
3667
3668 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3669 // Only ES buffer addrress needs to be set for VP8
3670 _HVD_EX_SetESBufferAddr(u32Id);
3671 #else
3672 if(DecoderType != E_VPU_EX_DECODER_MVD)
3673 {
3674 _HVD_EX_SetBufferAddr(u32Id);
3675 }
3676 #endif
3677 if (!HAL_VPU_EX_HVDInUsed())
3678 {
3679 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3680 }
3681
3682 #if SUPPORT_EVD
3683 if (isEVD)
3684 {
3685 #ifdef VDEC3
3686 if (!HAL_VPU_EX_EVDInUsed())
3687 #endif
3688 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3689 }
3690 #endif
3691 #if SUPPORT_G2VP9 && defined(VDEC3)
3692 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3693 {
3694 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3695
3696 if (!HAL_VPU_EX_G2VP9InUsed())
3697 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3698
3699 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3700 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3701 }
3702 #endif
3703
3704 return TRUE;
3705 }
3706
HAL_HVD_EX_DeinitHW(void)3707 MS_BOOL HAL_HVD_EX_DeinitHW(void)
3708 {
3709 MS_U16 u16Timeout = 1000;
3710
3711 _HVD_EX_SetMIUProtectMask(TRUE);
3712
3713 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
3714 HAL_EVD_EX_DeinitHW();
3715 #endif
3716
3717 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3718
3719 while (u16Timeout)
3720 {
3721 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3722 {
3723 break;
3724 }
3725 u16Timeout--;
3726 }
3727
3728 HAL_HVD_EX_PowerCtrl(FALSE);
3729
3730 _HVD_EX_SetMIUProtectMask(FALSE);
3731
3732 return TRUE;
3733 }
3734
HAL_HVD_EX_FlushMemory(void)3735 void HAL_HVD_EX_FlushMemory(void)
3736 {
3737 MsOS_FlushMemory();
3738 }
3739
HAL_HVD_EX_ReadMemory(void)3740 void HAL_HVD_EX_ReadMemory(void)
3741 {
3742 MsOS_ReadMemory();
3743 }
3744
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3745 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3746 {
3747 _pHVDCtrls = pHVDCtrlsBase;
3748 }
3749
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3750 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3751 {
3752 return;
3753 }
3754
HAL_HVD_EX_GetHWVersionID(void)3755 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3756 {
3757 return _HVD_Read2Byte(HVD_REG_REV_ID);
3758 }
3759
3760
HAL_HVD_EX_Init_Share_Mem(void)3761 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3762 {
3763 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3764 #if !defined(SUPPORT_X_MODEL_FEATURE)
3765 MS_U32 u32ShmId;
3766 MS_VIRT u32Addr;
3767 MS_U32 u32BufSize;
3768
3769
3770 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3771 sizeof(HVD_Hal_CTX),
3772 &u32ShmId,
3773 &u32Addr,
3774 &u32BufSize,
3775 MSOS_SHM_QUERY))
3776 {
3777 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3778 sizeof(HVD_Hal_CTX),
3779 &u32ShmId,
3780 &u32Addr,
3781 &u32BufSize,
3782 MSOS_SHM_CREATE))
3783 {
3784 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3785 if(pHVDHalContext == NULL)
3786 {
3787 pHVDHalContext = &gHVDHalContext;
3788 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3789 _HVD_EX_Context_Init_HAL();
3790 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3791 }
3792 else
3793 {
3794 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3795 }
3796 //return FALSE;
3797 }
3798 else
3799 {
3800 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3801 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3802 _HVD_EX_Context_Init_HAL();
3803 }
3804 }
3805 else
3806 {
3807 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3808 }
3809 #else
3810 if(pHVDHalContext == NULL)
3811 {
3812 pHVDHalContext = &gHVDHalContext;
3813 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3814 _HVD_EX_Context_Init_HAL();
3815 }
3816 #endif
3817 _HAL_HVD_MutexCreate();
3818 #else
3819 if(pHVDHalContext == NULL)
3820 {
3821 pHVDHalContext = &gHVDHalContext;
3822 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3823 _HVD_EX_Context_Init_HAL();
3824 }
3825 #endif
3826
3827 return TRUE;
3828 }
3829
3830
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3831 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3832 {
3833 MS_U32 i = 0;
3834
3835 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3836 {
3837 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3838 return pHVDHalContext->_stHVDStream[0].eStreamId;
3839 }
3840 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3841 {
3842 for (i = 0;
3843 i <
3844 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3845 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3846 {
3847 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3848 {
3849 return pHVDHalContext->_stHVDStream[i].eStreamId;
3850 }
3851 }
3852 }
3853 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3854 {
3855 for (i = 0;
3856 i <
3857 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3858 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3859 {
3860 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3861 {
3862 return pHVDHalContext->_stHVDStream[i].eStreamId;
3863 }
3864 }
3865 }
3866 #ifdef VDEC3
3867 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3868 {
3869 i = eStreamType - E_HAL_HVD_N_STREAM;
3870 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3871 return pHVDHalContext->_stHVDStream[i].eStreamId;
3872 }
3873 #endif
3874
3875 return E_HAL_HVD_STREAM_NONE;
3876 }
3877
HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)3878 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)
3879 {
3880
3881
3882 // _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
3883 const SYS_Info* sysInfo;
3884 sysInfo = MDrv_SYS_GetInfo();
3885
3886
3887 if (bEnable)
3888 {
3889 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3890 }
3891 else
3892 {
3893 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3894 }
3895
3896 // fix to not inverse
3897 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
3898
3899 switch (pHVDHalContext->u32HVDClockType)
3900 {
3901
3902 case 288: // for maldives only
3903 {
3904 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
3905 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_172MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3906 break;
3907
3908 }
3909 case 240:
3910 {
3911 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
3912 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3913 break;
3914 }
3915 case 216:
3916 {
3917 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
3918 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3919 break;
3920 }
3921 case 172:
3922 {
3923 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
3924 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3925 break;
3926 }
3927 default:
3928 {
3929 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
3930 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
3931 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3932 break;
3933 }
3934 }
3935
3936 return;
3937 }
3938
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)3939 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
3940 {
3941 u32HVDRegOSBase = u32RegBase;
3942 HAL_VPU_EX_InitRegBase(u32RegBase);
3943 }
3944
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)3945 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
3946 {
3947 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
3948 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3949 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
3950 }
3951
HAL_HVD_EX_InitVariables(MS_U32 u32Id)3952 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
3953 {
3954 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3955 HVD_ShareMem *pShm = NULL;
3956 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3957 #if HVD_ENABLE_MVC
3958 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3959 #endif ///HVD_ENABLE_MVC
3960
3961 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
3962 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
3963 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
3964 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
3965 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
3966 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = TRUE;
3967 int i;
3968 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
3969 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
3970 #if HVD_ENABLE_MVC
3971 if(bMVC)
3972 {
3973 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
3974 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
3975 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
3976 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
3977 }
3978 #endif ///HVD_ENABLE_MVC
3979
3980 // set a local copy of FW code address; assuming there is only one copy of FW,
3981 // no matter how many task will be created.
3982
3983 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3984
3985 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
3986
3987 // global variables
3988 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
3989
3990
3991 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
3992 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
3993 // Create mutex
3994 //_HAL_HVD_MutexCreate();
3995
3996 // fill HVD init variables
3997 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3998 {
3999 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4000 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4001 }
4002 else
4003 #if HVD_ENABLE_RV_FEATURE
4004 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4005 {
4006 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4007 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4008 #ifdef VDEC3_FB
4009 pHVDHalContext->u32RV_VLCTableAddr = 0;
4010 #else
4011 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4012 {
4013 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4014 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4015 }
4016 else
4017 {
4018 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4019 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4020 return E_HVD_RETURN_INVALID_PARAMETER;
4021 }
4022 #endif
4023 }
4024 else
4025 #endif
4026 {
4027 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4028 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4029 #if HVD_ENABLE_MVC
4030 if(bMVC)
4031 {
4032 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4033 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4034 }
4035 #endif /// HVD_ENABLE_MVC
4036 pHVDHalContext->u32RV_VLCTableAddr = 0;
4037 }
4038
4039 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4040 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4041 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4042 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4043 {
4044 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4045 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4046 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4047 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4048 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4049 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4050 #if HVD_ENABLE_MVC
4051 if(bMVC)
4052 {
4053 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4054 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4055 {
4056 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4057 }
4058 }
4059 #endif /// HVD_ENABLE_MVC
4060
4061 return E_HVD_RETURN_SUCCESS;
4062 }
4063 else
4064 {
4065 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4066 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
4067 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4068 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4069 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4070 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4071 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4072 return E_HVD_RETURN_INVALID_PARAMETER;
4073 }
4074 }
4075
4076 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4077 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4078 #else
4079 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4080 #endif
4081 {
4082 MS_U32 u32Addr = 0;
4083 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4084 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4085 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4086
4087 MS_U32 u32TmpStartOffset;
4088 MS_U8 u8TmpMiuSel;
4089
4090
4091 memset(pShm, 0, sizeof(HVD_ShareMem));
4092
4093 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4094
4095 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4096 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4097 #ifdef VDEC3
4098 if (bFWdecideFB || bCMAUsed)
4099 {
4100 pShm->u32FrameBufAddr = 0;
4101 pShm->u32FrameBufSize = 0;
4102 }
4103 else
4104 #endif
4105 {
4106 pShm->u32FrameBufAddr = u32Addr;
4107 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4108 }
4109
4110 pShm->u8ExternalHeapIdx = 0xFF; //20170110
4111 pShm->DispInfo.u16DispWidth = 1;
4112 pShm->DispInfo.u16DispHeight = 1;
4113 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4114 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4115 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4116 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4117 //Chip info
4118 pShm->u16ChipID = E_MSTAR_CHIP_MUSTANG;
4119 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4120 // PreSetControl
4121 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
4122 {
4123 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4124 }
4125
4126 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
4127 {
4128 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
4129 }//20170110
4130
4131 if (_HVD_EX_IS_BBU_TSP_MODE(u32Id))
4132 {
4133 pShm->bUseTSPInBBUMode = TRUE;
4134 HVD_PRINT("\033[1;36m[%s] %d set PRESET_TSP_IN_BBU_MODE pShm->u32PreSetControl = %x\033[m\n",__FUNCTION__,__LINE__,(unsigned int)(pShm->u32PreSetControl));
4135 }
4136 else
4137 pShm->bUseTSPInBBUMode = FALSE;
4138
4139
4140 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
4141 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4142 {
4143 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4144
4145 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
4146
4147 pShm->u32IapGnBufAddr = u32Addr;
4148 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
4149
4150 }
4151
4152 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4153 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4154 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4155 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4156 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4157 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4158
4159 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.bEnable))
4160 {
4161 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4162
4163 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.bConnect;
4164 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
4165 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4166
4167 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, pShm->stDynmcDispPath.u8DispPath);
4168 }
4169 else
4170 {
4171 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4172
4173 MS_U8 u8Connect = FALSE;
4174 MS_U8 u8Path = E_CTL_DISPLAY_PATH_NONE;
4175 switch (pCtrl->eStream)
4176 {
4177 case E_HVD_ORIGINAL_MAIN_STREAM:
4178 u8Connect = TRUE;
4179 u8Path = E_CTL_DISPLAY_PATH_MVOP_0;
4180 break;
4181 case E_HVD_ORIGINAL_SUB_STREAM:
4182 u8Connect = TRUE;
4183 u8Path = E_CTL_DISPLAY_PATH_MVOP_1;
4184 break;
4185 case E_HVD_ORIGINAL_N_STREAM:
4186 default:
4187 u8Connect = FALSE;
4188 u8Path = E_CTL_DISPLAY_PATH_NONE;
4189 break;
4190 }
4191
4192 pShm->stDynmcDispPath.u8Connect = u8Connect;
4193 pShm->stDynmcDispPath.u8DispPath = u8Path;
4194 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4195
4196 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, u8Path);
4197 }
4198
4199 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
4200 {
4201 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.bEnable))
4202 {
4203 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4204 pShm->u8InputTSP = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.u8InputTsp;
4205
4206 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4207 }
4208 else
4209 {
4210 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4211
4212 MS_U8 u8Input = E_CTL_INPUT_TSP_NONE;
4213 switch (pCtrl->eStream)
4214 {
4215 case E_HVD_ORIGINAL_MAIN_STREAM:
4216 u8Input = E_CTL_INPUT_TSP_0;
4217 break;
4218 case E_HVD_ORIGINAL_SUB_STREAM:
4219 u8Input = E_CTL_INPUT_TSP_1;
4220 break;
4221 case E_HVD_ORIGINAL_N_STREAM:
4222 default:
4223 u8Input = E_CTL_INPUT_TSP_NONE;
4224 break;
4225 }
4226
4227 pShm->u8InputTSP = u8Input;
4228
4229 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4230 }
4231 }
4232 else
4233 {
4234 HVD_EX_MSG_DBG("[NDec][0x%x][%d] not TSP input, ignore PRESET_CONNECT_INPUT_TSP \n", u32Id, u8Idx);
4235 }
4236
4237 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4238 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4239 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4240 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4241 else
4242 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4243 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4244 {
4245 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4246 {
4247 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4248 }
4249 else
4250 {
4251 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4252 }
4253 }
4254 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4255 {
4256 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4257 {
4258 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4259 }
4260 else
4261 {
4262 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4263 }
4264 }
4265 else
4266 {
4267 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4268 }
4269
4270 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4271 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4272 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4273 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4274 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4275 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4276 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4277 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4278 {
4279 pShm->bUseWbMvop = 1;
4280 }
4281
4282 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4283
4284 #if (VPU_FORCE_MIU_MODE)
4285 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4286
4287 pShm->u32FWBaseAddr = u32TmpStartOffset;
4288
4289 #else
4290 ///TODO:
4291 /*
4292 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4293
4294 if(u8TmpMiuSel == E_CHIP_MIU_0)
4295 {
4296 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4297 }
4298 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4299 {
4300 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4301 }
4302 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4303 {
4304 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4305 }
4306 */
4307 #endif
4308 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4309 #else
4310 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4311 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4312 {
4313 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4314 }
4315 pShm->u32FWBaseAddr = u32Addr;
4316 #endif
4317
4318 // RM only
4319 #if HVD_ENABLE_RV_FEATURE
4320 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4321 && (pCtrl->InitParams.pRVFileInfo != NULL))
4322 {
4323 MS_U32 i = 0;
4324
4325 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4326 {
4327 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4328 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4329 }
4330
4331 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4332 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4333 #ifdef VDEC3_FB
4334 pShm->u32RM_VLCTableAddr = 0;
4335 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4336 #else
4337 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4338
4339 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4340 u32Addr = u32TmpStartOffset;
4341
4342 pShm->u32RM_VLCTableAddr = u32Addr;
4343 #endif
4344 }
4345 #endif
4346
4347 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4348 && (pCtrl->InitParams.pRVFileInfo != NULL))
4349 {
4350 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4351 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4352 }
4353
4354 //if(pCtrl->InitParams.bColocateBBUMode)
4355 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4356 {
4357 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4358 }
4359
4360 #if SUPPORT_G2VP9
4361 // Enable SW detile support for G2 VP9
4362 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4363 {
4364 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4365 }
4366 #endif
4367
4368 HAL_HVD_EX_FlushMemory();
4369
4370 return E_HVD_RETURN_SUCCESS;
4371 }
4372 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4373 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4374 #else
4375 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4376 #endif
4377 {
4378 MS_BOOL bInitRet = FALSE;
4379
4380 #if 0
4381 // check MVD power on
4382 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4383 {
4384 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4385 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4386 HVD_Delay_ms(1);
4387 }
4388 // Check VPU power on
4389 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4390 {
4391 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4392 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4393 HVD_Delay_ms(1);
4394 }
4395 // check HVD power on
4396 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4397 {
4398 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4399 HAL_HVD_EX_PowerCtrl(TRUE);
4400 HVD_Delay_ms(1);
4401 }
4402 #endif
4403 #ifdef VDEC3
4404 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4405 #else
4406 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4407 #endif
4408 if (!bInitRet)
4409 {
4410 return E_HVD_RETURN_FAIL;
4411 }
4412
4413 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4414
4415 if (!bInitRet)
4416 {
4417 return E_HVD_RETURN_FAIL;
4418 }
4419
4420 return E_HVD_RETURN_SUCCESS;
4421 }
4422
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4423 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4424 {
4425 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4426
4427 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4428
4429 return E_HVD_RETURN_SUCCESS;
4430 }
4431
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4432 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4433 {
4434 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4435 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4436 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4437 MS_BOOL bMVC = FALSE;
4438 #if HVD_ENABLE_MVC
4439 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4440 #endif
4441
4442 switch (u32type)
4443 {
4444 // share memory
4445 // switch
4446 case E_HVD_SDATA_FRAMEBUF_ADDR:
4447 {
4448 pShm->u32FrameBufAddr = u32Data;
4449 break;
4450 }
4451 case E_HVD_SDATA_FRAMEBUF_SIZE:
4452 {
4453 pShm->u32FrameBufSize = u32Data;
4454 break;
4455 }
4456 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4457 {
4458 pShm->u32FrameBuf2Addr = u32Data;
4459 break;
4460 }
4461 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4462 {
4463 pShm->u32FrameBuf2Size = u32Data;
4464 break;
4465 }
4466 case E_HVD_SDATA_MAX_CMA_SIZE:
4467 {
4468 pShm->u32MaxCMAFrameBufSize = u32Data;
4469 break;
4470 }
4471 case E_HVD_SDATA_MAX_CMA_SIZE2:
4472 {
4473 pShm->u32MaxCMAFrameBuf2Size = u32Data;
4474 break;
4475 }
4476 case E_HVD_SDATA_CMA_USED:
4477 {
4478 pShm->bCMA_Use = u32Data;
4479 break;
4480 }
4481 case E_HVD_SDATA_CMA_ALLOC_DONE:
4482 {
4483 pShm->bCMA_AllocDone = u32Data;
4484 break;
4485 }
4486 case E_HVD_SDATA_CMA_TWO_MIU:
4487 {
4488 pShm->bCMA_TwoMIU = u32Data;
4489 break;
4490 }
4491 case E_HVD_SDATA_RM_PICTURE_SIZES:
4492 {
4493 if(u32Data != NULL)
4494 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4495 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4496 break;
4497 }
4498 case E_HVD_SDATA_ERROR_CODE:
4499 {
4500 pShm->u16ErrCode = (MS_U16) u32Data;
4501 break;
4502 }
4503 case E_HVD_SDATA_DISP_INFO_TH:
4504 {
4505 if(u32Data != NULL)
4506 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4507 sizeof(HVD_DISP_THRESHOLD));
4508 break;
4509 }
4510 case E_HVD_SDATA_FW_FLUSH_STATUS:
4511 {
4512 pShm->u8FlushStatus = (MS_U8)u32Data;
4513 break;
4514 }
4515 case E_HVD_SDATA_DMX_FRAMERATE:
4516 {
4517 pShm->u32DmxFrameRate = u32Data;
4518 break;
4519 }
4520 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4521 {
4522 pShm->u32DmxFrameRateBase = u32Data;
4523 break;
4524 }
4525 case E_HVD_SDATA_MIU_SEL:
4526 {
4527 pShm->u32VDEC_MIU_SEL = u32Data;
4528 break;
4529 }
4530 // SRAM
4531
4532 // Mailbox
4533 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4534 {
4535 if (u32Data != 0)
4536 {
4537 pShm->bEnableDispCtrl = TRUE;
4538 pShm->bIsTrigDisp = TRUE;
4539 }
4540 else
4541 {
4542 pShm->bEnableDispCtrl = FALSE;
4543 }
4544
4545 break;
4546 }
4547 case E_HVD_SDATA_GET_DISP_INFO_START:
4548 {
4549 pShm->bSpsChange = FALSE;
4550 break;
4551 }
4552 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4553 {
4554 pShm->u32VirtualBoxWidth = u32Data;
4555 break;
4556 }
4557 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4558 {
4559 pShm->u32VirtualBoxHeight = u32Data;
4560 break;
4561 }
4562 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4563 {
4564 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4565 {
4566 //printf("DispFrame DqPtr: %d\n", u32Data);
4567 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4568 }
4569 break;
4570 }
4571 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4572 {
4573 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4574 {
4575 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4576 {
4577 //printf("DispFrame DqPtr: %ld\n", u32Data);
4578 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4579 }
4580 }
4581 break;
4582 }
4583 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4584 {
4585 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4586 {
4587 if (bMVC)
4588 {
4589 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4590 {
4591 //ALOGE("R1: %x", u32Data);
4592 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4593 }
4594 else
4595 {
4596 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4597 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4598 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4599 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4600 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4601 }
4602 }
4603 else
4604 {
4605 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4606 }
4607 }
4608 else
4609 {
4610 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4611 {
4612 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4613 }
4614 }
4615 break;
4616 }
4617 case E_HVD_SDATA_HDR_PERFRAME:
4618 {
4619 if (u32Data != 0)
4620 {
4621 pShm->u8IsDoblyHDR10 = TRUE;
4622 }
4623 else
4624 {
4625 pShm->u8IsDoblyHDR10 = FALSE;
4626 }
4627 break;
4628 }
4629 #if (HVD_ENABLE_IQMEM)
4630 case E_HVD_SDATA_FW_IQMEM_CTRL:
4631 {
4632 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4633 break;
4634
4635 }
4636 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4637 {
4638 if (u32Data != 0)
4639 {
4640 pShm->bIQmemEnableIfSupport= TRUE;
4641 }
4642 else
4643 {
4644 pShm->bIQmemEnableIfSupport= FALSE;
4645 }
4646
4647
4648 break;
4649
4650 }
4651 #endif
4652 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
4653 {
4654 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
4655 break;
4656 }
4657 case E_HVD_SDATA_VP9HDR10INFO:
4658 {
4659 int i,j;
4660 HVD_Config_VP9HDR10* stVP9HDR10Info = (HVD_Config_VP9HDR10*) u32Data;
4661
4662 pShm->VP9HDR10Info.u32Version = stVP9HDR10Info->u32Version;
4663 pShm->VP9HDR10Info.u8MatrixCoefficients = stVP9HDR10Info->u8MatrixCoefficients;
4664 pShm->VP9HDR10Info.u8BitsPerChannel = stVP9HDR10Info->u8BitsPerChannel;
4665 pShm->VP9HDR10Info.u8ChromaSubsamplingHorz = stVP9HDR10Info->u8ChromaSubsamplingHorz;
4666 pShm->VP9HDR10Info.u8ChromaSubsamplingVert = stVP9HDR10Info->u8ChromaSubsamplingVert;
4667 pShm->VP9HDR10Info.u8CbSubsamplingHorz = stVP9HDR10Info->u8CbSubsamplingHorz;
4668 pShm->VP9HDR10Info.u8CbSubsamplingVert = stVP9HDR10Info->u8CbSubsamplingVert;
4669 pShm->VP9HDR10Info.u8ChromaSitingHorz = stVP9HDR10Info->u8ChromaSitingHorz;
4670 pShm->VP9HDR10Info.u8ChromaSitingVert = stVP9HDR10Info->u8ChromaSitingVert;
4671 pShm->VP9HDR10Info.u8ColorRange = stVP9HDR10Info->u8ColorRange;
4672 pShm->VP9HDR10Info.u8TransferCharacteristics = stVP9HDR10Info->u8TransferCharacteristics;
4673 pShm->VP9HDR10Info.u8ColourPrimaries = stVP9HDR10Info->u8ColourPrimaries;
4674 pShm->VP9HDR10Info.u16MaxCLL = stVP9HDR10Info->u16MaxCLL;
4675 pShm->VP9HDR10Info.u16MaxFALL = stVP9HDR10Info->u16MaxFALL;
4676 pShm->VP9HDR10Info.u32MaxLuminance = stVP9HDR10Info->u32MaxLuminance;
4677 pShm->VP9HDR10Info.u32MinLuminance = stVP9HDR10Info->u32MinLuminance;
4678
4679 for(i=0;i<2;i++)
4680 {
4681 pShm->VP9HDR10Info.u16WhitePoint[i] = stVP9HDR10Info->u16WhitePoint[i];
4682 }
4683
4684 for(i=0;i<3;i++)
4685 {
4686 for(j=0;j<2;j++)
4687 {
4688 pShm->VP9HDR10Info.u16Primaries[i][j] = stVP9HDR10Info->u16Primaries[i][j];
4689 }
4690 }
4691 pShm->u8VP9HDR10InfoVaild = TRUE;
4692 break;
4693 }
4694 default:
4695 break;
4696 }
4697
4698 HAL_HVD_EX_FlushMemory();
4699
4700 return eRet;
4701 }
4702
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4703 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4704 {
4705 MS_S64 s64Ret = 0;
4706 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4707
4708 HAL_HVD_EX_ReadMemory();
4709
4710 switch (eType)
4711 {
4712 case E_HVD_GDATA_PTS_STC_DIFF:
4713 s64Ret = pShm->s64PtsStcDiff;
4714 break;
4715 default:
4716 break;
4717 }
4718
4719 return s64Ret;
4720 }
4721
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4722 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4723 {
4724 MS_VIRT u32Ret = 0;
4725 //static MS_U64 u64pts_real = 0;
4726 MS_U64 u64pts_low = 0;
4727 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4728 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4729
4730 HAL_HVD_EX_ReadMemory();
4731
4732 if(pShm == NULL)
4733 {
4734 printf("########## VDEC patch for Debug ###########\n");
4735 return 0x0;
4736 }
4737
4738 switch (eType)
4739 {
4740 // share memory
4741 // switch
4742 case E_HVD_GDATA_DISP_INFO_ADDR:
4743 {
4744 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4745 break;
4746 }
4747 case E_HVD_GDATA_MIU_SEL:
4748 u32Ret = pShm->u32VDEC_MIU_SEL;
4749 break;
4750 case E_HVD_GDATA_FRAMEBUF_ADDR:
4751 u32Ret = pShm->u32FrameBufAddr;
4752 break;
4753 case E_HVD_GDATA_FRAMEBUF_SIZE:
4754 u32Ret = pShm->u32FrameBufSize;
4755 break;
4756 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4757 u32Ret = pShm->u32FrameBuf2Addr;
4758 break;
4759 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4760 u32Ret = pShm->u32FrameBuf2Size;
4761 break;
4762 case E_HVD_GDATA_CMA_ALLOC_DONE:
4763 u32Ret = pShm->bCMA_AllocDone;
4764 break;
4765 case E_HVD_GDATA_CMA_USED:
4766 u32Ret = pShm->bCMA_Use;
4767 break;
4768 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
4769 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
4770 break;
4771 // report
4772 case E_HVD_GDATA_PTS:
4773 {
4774 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
4775 break;
4776 }
4777 case E_HVD_GDATA_U64PTS:
4778 {
4779 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
4780 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
4781 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4782 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4783 break;
4784 }
4785 case E_HVD_GDATA_U64PTS_PRE_PARSE:
4786 {
4787 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
4788 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
4789 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4790 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4791 break;
4792 }
4793 case E_HVD_GDATA_DECODE_CNT:
4794 {
4795 u32Ret = pShm->u32DecodeCnt;
4796 break;
4797 }
4798 case E_HVD_GDATA_DATA_ERROR_CNT:
4799 {
4800 u32Ret = pShm->u32DataErrCnt;
4801 break;
4802 }
4803 case E_HVD_GDATA_DEC_ERROR_CNT:
4804 {
4805 u32Ret = pShm->u32DecErrCnt;
4806 break;
4807 }
4808 case E_HVD_GDATA_ERROR_CODE:
4809 {
4810 u32Ret = (MS_U32) (pShm->u16ErrCode);
4811 break;
4812 }
4813 case E_HVD_GDATA_VPU_IDLE_CNT:
4814 {
4815 u32Ret = pShm->u32VPUIdleCnt;
4816 break;
4817 }
4818 case E_HVD_GDATA_DISP_FRM_INFO:
4819 {
4820 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
4821 break;
4822 }
4823 case E_HVD_GDATA_DEC_FRM_INFO:
4824 {
4825 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
4826 break;
4827 }
4828 case E_HVD_GDATA_ES_LEVEL:
4829 {
4830 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
4831 break;
4832 }
4833 #if HVD_ENABLE_MVC
4834 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
4835 {
4836 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
4837 break;
4838 }
4839 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
4840 {
4841 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
4842 break;
4843 }
4844 #endif
4845
4846 // user data
4847 case E_HVD_GDATA_USERDATA_WPTR:
4848 {
4849 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
4850 break;
4851 }
4852 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
4853 {
4854 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
4855 break;
4856 }
4857 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
4858 {
4859 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
4860 break;
4861 }
4862 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
4863 {
4864 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
4865 break;
4866 }
4867 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
4868 {
4869 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
4870 break;
4871 }
4872 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
4873 {
4874 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
4875 break;
4876 }
4877 // report - modes
4878 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
4879 {
4880 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
4881 break;
4882 }
4883 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
4884 {
4885 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
4886 break;
4887 }
4888 case E_HVD_GDATA_IS_ERR_CONCEAL:
4889 {
4890 u32Ret = pShm->ModeStatus.bIsErrConceal;
4891 break;
4892 }
4893 case E_HVD_GDATA_IS_SYNC_ON:
4894 {
4895 u32Ret = pShm->ModeStatus.bIsSyncOn;
4896 break;
4897 }
4898 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
4899 {
4900 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
4901 break;
4902 }
4903 case E_HVD_GDATA_SYNC_MODE:
4904 {
4905 u32Ret = pShm->ModeStatus.u8SyncType;
4906 break;
4907 }
4908 case E_HVD_GDATA_SKIP_MODE:
4909 {
4910 u32Ret = pShm->ModeStatus.u8SkipMode;
4911 break;
4912 }
4913 case E_HVD_GDATA_DROP_MODE:
4914 {
4915 u32Ret = pShm->ModeStatus.u8DropMode;
4916 break;
4917 }
4918 case E_HVD_GDATA_DISPLAY_DURATION:
4919 {
4920 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
4921 break;
4922 }
4923 case E_HVD_GDATA_FRC_MODE:
4924 {
4925 u32Ret = pShm->ModeStatus.u8FrcMode;
4926 break;
4927 }
4928 case E_HVD_GDATA_NEXT_PTS:
4929 {
4930 u32Ret = pShm->u32NextPTS;
4931 break;
4932 }
4933 case E_HVD_GDATA_DISP_Q_SIZE:
4934 {
4935 u32Ret = pShm->u16DispQSize;
4936 break;
4937 }
4938 case E_HVD_GDATA_DISP_Q_PTR:
4939 {
4940 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
4941 break;
4942 }
4943 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
4944 {
4945 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
4946 break;
4947 }
4948 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
4949 {
4950 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
4951 break;
4952 }
4953 case E_HVD_GDATA_REAL_FRAMERATE:
4954 {
4955 // return VPS/VUI timing info framerate, and 0 if timing info not exist
4956 u32Ret = pShm->u32RealFrameRate;
4957 break;
4958 }
4959 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
4960 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
4961 break;
4962 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
4963 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
4964 break;
4965 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
4966 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
4967 break;
4968 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
4969 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
4970 break;
4971 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
4972 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
4973 break;
4974 case E_HVD_GDATA_FW_STATUS_FLAG:
4975 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
4976 break;
4977
4978 // internal control
4979 case E_HVD_GDATA_IS_1ST_FRM_RDY:
4980 {
4981 u32Ret = pShm->bIs1stFrameRdy;
4982 break;
4983 }
4984 case E_HVD_GDATA_IS_I_FRM_FOUND:
4985 {
4986 u32Ret = pShm->bIsIFrmFound;
4987 break;
4988 }
4989 case E_HVD_GDATA_IS_SYNC_START:
4990 {
4991 u32Ret = pShm->bIsSyncStart;
4992 break;
4993 }
4994 case E_HVD_GDATA_IS_SYNC_REACH:
4995 {
4996 u32Ret = pShm->bIsSyncReach;
4997 break;
4998 }
4999 case E_HVD_GDATA_FW_VERSION_ID:
5000 {
5001 u32Ret = pShm->u32FWVersionID;
5002 break;
5003 }
5004 case E_HVD_GDATA_FW_IF_VERSION_ID:
5005 {
5006 u32Ret = pShm->u32FWIfVersionID;
5007 break;
5008 }
5009 case E_HVD_GDATA_BBU_Q_NUMB:
5010 {
5011 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
5012 break;
5013 }
5014 case E_HVD_GDATA_DEC_Q_NUMB:
5015 {
5016 u32Ret = pShm->u16DecQNumb;
5017 break;
5018 }
5019 case E_HVD_GDATA_DISP_Q_NUMB:
5020 {
5021 u32Ret = pShm->u16DispQNumb;
5022 break;
5023 }
5024 case E_HVD_GDATA_PTS_Q_NUMB:
5025 {
5026 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
5027 break;
5028 }
5029 case E_HVD_GDATA_FW_INIT_DONE:
5030 {
5031 u32Ret = pShm->bInitDone;
5032 break;
5033 }
5034 // debug
5035 case E_HVD_GDATA_SKIP_CNT:
5036 {
5037 u32Ret = pShm->u32SkipCnt;
5038 break;
5039 }
5040 case E_HVD_GDATA_GOP_CNT:
5041 {
5042 u32Ret = pShm->u32DropCnt;
5043 break;
5044 }
5045 case E_HVD_GDATA_DISP_CNT:
5046 {
5047 u32Ret = pShm->u32DispCnt;
5048 break;
5049 }
5050 case E_HVD_GDATA_DROP_CNT:
5051 {
5052 u32Ret = pShm->u32DropCnt;
5053 break;
5054 }
5055 case E_HVD_GDATA_DISP_STC:
5056 {
5057 u32Ret = pShm->u32DispSTC;
5058 break;
5059 }
5060 case E_HVD_GDATA_VSYNC_CNT:
5061 {
5062 u32Ret = pShm->u32VsyncCnt;
5063 break;
5064 }
5065 case E_HVD_GDATA_MAIN_LOOP_CNT:
5066 {
5067 u32Ret = pShm->u32MainLoopCnt;
5068 break;
5069 }
5070
5071 // AVC
5072 case E_HVD_GDATA_AVC_LEVEL_IDC:
5073 {
5074 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5075 break;
5076 }
5077 case E_HVD_GDATA_AVC_LOW_DELAY:
5078 {
5079 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5080 break;
5081 }
5082 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5083 {
5084 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5085 break;
5086 }
5087 case E_HVD_GDATA_FW_FLUSH_STATUS:
5088 {
5089 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5090 break;
5091 }
5092 case E_HVD_GDATA_FW_CODEC_TYPE:
5093 {
5094 u32Ret = pShm->u32CodecType;
5095 break;
5096 }
5097 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5098 {
5099 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5100 break;
5101 }
5102 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5103 {
5104 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5105 {
5106 u32Ret = 1;
5107 }
5108 else
5109 {
5110 u32Ret = 0;
5111 }
5112 break;
5113 }
5114
5115 // SRAM
5116
5117 // Mailbox
5118 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5119 {
5120 u32Ret = pShm->u32FwState;
5121 break;
5122 }
5123 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5124 {
5125 u32Ret = pShm->bSpsChange;
5126 break;
5127 }
5128 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5129 {
5130 u32Ret = pShm->bSpsChange;
5131
5132 if (pShm->bSpsChange &&
5133 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5134 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5135 {
5136 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5137 }
5138
5139 break;
5140 }
5141 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5142 {
5143 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5144
5145 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5146 {
5147 u32Ret = pShm->u32FwInfo;
5148 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5149 }
5150 break;
5151 }
5152 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5153 {
5154 if (pShm->bIsTrigDisp) // not clear yet
5155 {
5156 u32Ret = FALSE;
5157 }
5158 else
5159 {
5160 u32Ret = TRUE;
5161 }
5162 break;
5163 }
5164 case E_HVD_GDATA_ES_READ_PTR:
5165 {
5166 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5167 break;
5168 }
5169 case E_HVD_GDATA_ES_WRITE_PTR:
5170 {
5171 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5172 break;
5173 }
5174 case E_HVD_GDATA_BBU_READ_PTR:
5175 {
5176 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5177 break;
5178 }
5179 case E_HVD_GDATA_BBU_WRITE_PTR:
5180 {
5181 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5182 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5183 {
5184 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5185 }
5186 else
5187 {
5188 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5189 }
5190 break;
5191 }
5192 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5193 {
5194 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5195
5196 u32Ret = pCtrl->u32BBUWptr_Fired;
5197
5198 break;
5199 }
5200 case E_HVD_GDATA_VPU_PC_CNT:
5201 {
5202 u32Ret = _HVD_EX_GetPC();
5203 break;
5204 }
5205 case E_HVD_GDATA_ES_QUANTITY:
5206 {
5207 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5208 break;
5209 }
5210
5211
5212 // FW def
5213 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5214 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5215 break;
5216
5217 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5218 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5219 break;
5220 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5221 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5222 break;
5223 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5224 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5225 break;
5226 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5227 u32Ret = MAX_PTS_TABLE_SIZE;
5228 break;
5229 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5230 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5231 break;
5232 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5233 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5234 break;
5235 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5236 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5237 break;
5238 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5239 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5240 break;
5241 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5242 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5243 break;
5244 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5245 {
5246 if (pShm->bDSIsRunning)
5247 {
5248 u32Ret = TRUE;
5249 }
5250 else
5251 {
5252 u32Ret = FALSE;
5253 }
5254 break;
5255 }
5256 #if (HVD_ENABLE_IQMEM)
5257 case E_HVD_GDATA_FW_IQMEM_CTRL:
5258 {
5259
5260 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5261
5262 break;
5263 }
5264 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5265 {
5266 if(pShm->bIsIQMEMSupport){
5267 u32Ret = TRUE;
5268 }
5269 else{
5270
5271 u32Ret = FALSE;
5272 }
5273
5274 break;
5275 }
5276 #endif
5277 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5278 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5279 break;
5280 case E_HVD_GDATA_FIELD_PIC_FLAG:
5281 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5282 break;
5283 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5284 u32Ret = pShm->u32SeamlessTSStatus;
5285 break;
5286 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5287 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5288 break;
5289 #ifdef VDEC3
5290 case E_HVD_GDATA_FW_VBBU_ADDR:
5291 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5292 break;
5293 #endif
5294 case E_HVD_GDATA_SEQ_CHANGE_INFO:
5295 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
5296 break;
5297 default:
5298 break;
5299 }
5300 return u32Ret;
5301 }
5302
HAL_HVD_EX_GetDVSupportProfiles(void)5303 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
5304 {
5305 #if 0 // wait avc finish DV dual job
5306 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5307 #else
5308 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5309 #endif
5310 }
5311
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)5312 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
5313 {
5314 switch (u32DV_Stream_Profile)
5315 {
5316 #if 0 // wait avc finish DV dual job
5317 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
5318 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
5319 #endif
5320
5321 #if 0 // unsupported profile
5322 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
5323 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5324 #endif
5325
5326 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
5327 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5328
5329 #if 0 // unsupported profile
5330 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
5331 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5332 #endif
5333
5334 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
5335 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5336
5337 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
5338 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5339
5340 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
5341 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5342
5343 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
5344 default:
5345 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5346 }
5347 }
5348
5349
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5350 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5351 {
5352 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5353 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5354 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5355
5356 _HAL_HVD_Entry();
5357
5358 // check if old SVD cmds
5359 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5360 {
5361 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5362
5363 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5364 }
5365
5366 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5367 {
5368 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5369 }
5370
5371 #if HVD_ENABLE_MVC
5372 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5373 {
5374 if (HAL_HVD_EX_CheckMVCID(u32Id) && u32Cmd == E_HVD_CMD_FLUSH)
5375 {
5376 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5377 }
5378 }
5379 #endif
5380
5381 if (u32Cmd == E_HVD_CMD_FLUSH &&
5382 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5383 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5384 {
5385 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5386 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5387 {
5388 _HAL_HVD_Release();
5389 HVD_Delay_ms(1);
5390 _HAL_HVD_Entry();
5391 }
5392
5393 }
5394
5395 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5396
5397 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5398
5399 _HAL_HVD_Return(eRet);
5400 }
5401
HAL_HVD_EX_DeInit(MS_U32 u32Id)5402 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5403 {
5404 HVD_Return eRet = E_HVD_RETURN_FAIL;
5405 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5406 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5407 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5408 // MS_U8 u8MiuSel;
5409 // MS_U32 u32StartOffset;
5410
5411
5412 #if HVD_ENABLE_TIME_MEASURE
5413 MS_U32 ExitTimeCnt = 0;
5414 ExitTimeCnt = HVD_GetSysTime_ms();
5415 #endif
5416
5417 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5418
5419 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5420
5421 if (E_HVD_RETURN_SUCCESS != eRet)
5422 {
5423 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5424 }
5425
5426 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5427
5428 if (E_HVD_RETURN_SUCCESS != eRet)
5429 {
5430 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5431 }
5432
5433 // check FW state to make sure it's STOP DONE
5434 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5435 {
5436 if (HVD_GetSysTime_ms() > u32Timeout)
5437 {
5438 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5439
5440 //return E_HVD_RETURN_TIMEOUT;
5441 eRet = E_HVD_RETURN_TIMEOUT;
5442 break;
5443 }
5444 }
5445
5446 VPU_EX_FWCodeCfg fwCfg;
5447 VPU_EX_TaskInfo taskInfo;
5448 VPU_EX_NDecInitPara nDecInitPara;
5449
5450 nDecInitPara.pFWCodeCfg = &fwCfg;
5451 nDecInitPara.pTaskInfo = &taskInfo;
5452
5453 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5454 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5455
5456 taskInfo.u32Id = u32Id;
5457 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5458 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5459
5460 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5461 {
5462 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5463 }
5464 else
5465 {
5466 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5467 }
5468
5469 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5470 {
5471 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5472 }
5473
5474 /* clear es buffer */
5475 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5476 {
5477 //printf("Clear ES buffer\n");
5478
5479 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5480 }
5481
5482 //_HAL_HVD_MutexDelete();
5483
5484 #if HVD_ENABLE_TIME_MEASURE
5485 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5486 #endif
5487
5488 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5489 #ifndef VDEC3
5490 // reset bbu wptr
5491 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5492 {
5493 if(TRUE == HAL_VPU_EX_HVDInUsed())
5494 {
5495 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5496 {
5497 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5498 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5499 }
5500 else
5501 {
5502 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5503 {
5504 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5505 }
5506 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5507 }
5508 }
5509 else
5510 {
5511 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5512 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5513 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5514 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5515 {
5516 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5517 {
5518 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5519 }
5520 }
5521 else
5522 {
5523 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5524 }
5525 }
5526 }
5527 #endif
5528 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5529
5530 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5531 {
5532 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5533 }
5534 /*
5535 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5536 {
5537 if(pCtrl->MemMap.u32FrameBufAddr >= HAL_MIU1_BASE)
5538 {
5539 _HAL_HVD_Entry();
5540 HAL_HVD_MVDMiuClientSel(1);
5541 _HAL_HVD_Release();
5542 }
5543 else
5544 {
5545 _HAL_HVD_Entry();
5546 HAL_HVD_MVDMiuClientSel(0);
5547 _HAL_HVD_Release();
5548 }
5549 }
5550 */
5551 HVD_EX_MSG_DBG("success\n");
5552
5553 return eRet;
5554 }
5555
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5556 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5557 {
5558 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5559 MS_U32 u32Addr = 0;
5560 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5561 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5562
5563 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5564
5565 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5566 {
5567 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5568
5569 if (E_HVD_RETURN_SUCCESS != eRet)
5570 {
5571 return eRet;
5572 }
5573 }
5574
5575 HVD_EX_MSG_ERR(">>> halHVD pts,idH = %u, %u\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5576 printf(">>> halHVD pts,idH = %u, %u\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5577
5578 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5579 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5580 {
5581 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5582
5583 if (E_HVD_RETURN_SUCCESS != eRet)
5584 {
5585 return eRet;
5586 }
5587 }
5588
5589 u32Addr = pInfo->u32Staddr;
5590
5591 if (pInfo->bRVBrokenPacket)
5592 {
5593 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5594 }
5595
5596 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5597 {
5598 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5599 }
5600 else
5601 {
5602 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5603 }
5604
5605 if (E_HVD_RETURN_SUCCESS != eRet)
5606 {
5607 return eRet;
5608 }
5609
5610 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5611 {
5612 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5613 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5614
5615 if (E_HVD_RETURN_SUCCESS != eRet)
5616 {
5617 return eRet;
5618 }
5619 }
5620
5621 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5622
5623 // do not add local pointer
5624 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5625 {
5626 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5627
5628 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5629 (u32PacketStAddr <
5630 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5631 {
5632 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5633 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5634 }
5635 else
5636 {
5637 //null packet
5638 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5639 pCtrl->LastNal.u32NalSize = 0;
5640 }
5641 }
5642 else
5643 {
5644 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5645 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5646 }
5647
5648 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5649 pCtrl->u32BBUPacketCnt++;
5650
5651 return eRet;
5652 }
5653
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5654 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5655 {
5656 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5657 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5658 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5659 if(bCurrentStatus == bEnable)
5660 return;
5661
5662 if (bEnable)
5663 {
5664 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5665 }
5666 else
5667 {
5668 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5669 }
5670 }
5671
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5672 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5673 {
5674 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5675 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5676
5677 if (bEnable)
5678 {
5679 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5680 }
5681 else
5682 {
5683 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5684 }
5685 }
5686
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5687 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5688 {
5689 MS_U32 u32RB = 0;
5690 switch(eISRType)
5691 {
5692 case E_HWDEC_ISR_HVD:
5693 u32RB = REG_HVD_BASE;
5694 break;
5695 #if SUPPORT_EVD
5696 case E_HWDEC_ISR_EVD:
5697 u32RB = REG_EVD_BASE;
5698 break;
5699 #endif
5700 #if SUPPORT_G2VP9
5701 case E_HWDEC_ISR_G2VP9:
5702 break;
5703 #endif
5704 default:
5705 break;
5706 }
5707 if(u32RB)
5708 {
5709 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5710 }
5711 }
5712
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5713 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5714 {
5715 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5716 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5717
5718 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5719 }
5720
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5721 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5722 {
5723 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5724 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5725
5726 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5727 {
5728 return FALSE;
5729 }
5730 else
5731 {
5732 return TRUE;
5733 }
5734 }
5735
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5736 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5737 {
5738 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5739
5740 if (pCtrl)
5741 {
5742 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5743 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5744 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5745 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5746 {
5747 return FALSE;
5748 }
5749 else
5750 {
5751 return TRUE;
5752 }
5753 }
5754 else
5755 {
5756 return FALSE;
5757 }
5758 }
5759
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5760 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5761 {
5762 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5763 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5764 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5765
5766 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5767 {
5768 HAL_HVD_EX_ReadMemory();
5769
5770 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5771 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5772
5773 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
5774 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
5775 }
5776
5777 return TRUE;
5778 }
5779
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)5780 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
5781 {
5782 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5783 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5784 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5785 MS_U32 u32Data;
5786 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5787
5788 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
5789
5790 HAL_HVD_EX_FlushMemory();
5791 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5792 {
5793 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5794 pCtrl->LastNal.u32NalAddr = u32Data;
5795 pCtrl->LastNal.u32NalSize = 0;
5796 }
5797
5798 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5799 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
5800
5801 return TRUE;
5802 }
5803
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)5804 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
5805 {
5806 if (bEnable)
5807 {
5808 if (HAL_VPU_EX_IsEVDR2())
5809 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5810 else
5811 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
5812 }
5813 else
5814 {
5815 #if defined (__aeon__)
5816 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5817 #else // defined (__mips__)
5818 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
5819 #endif
5820 }
5821 }
5822
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)5823 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
5824 {
5825 return 0;
5826 }
5827
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)5828 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
5829 {
5830 return;
5831 }
5832
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)5833 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
5834 {
5835 //if( u16Clock == 0 )
5836 return 216; //140;
5837 //if( )
5838 }
5839
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)5840 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
5841 {
5842 //MS_BOOL bBitMIU1 = FALSE;
5843 //MS_BOOL bCodeMIU1 = FALSE;
5844 MS_U8 u8BitMiuSel = 0;
5845 MS_U8 u8CodeMiuSel = 0;
5846 MS_U32 u32BitStartOffset;
5847 MS_U32 u32CodeStartOffset;
5848 //MS_U8 u8MiuSel;
5849 //MS_U32 u32StartOffset;
5850 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5851 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5852 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5853 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
5854
5855 #if HVD_ENABLE_MVC
5856 if(HAL_HVD_EX_CheckMVCID(u32Id))
5857 {
5858 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
5859 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
5860 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
5861 {
5862 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
5863 }
5864 }
5865 #endif /// HVD_ENABLE_MVC
5866
5867 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
5868 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5869 //HVD_EX_MSG_COVERITY("u32BitStartOffset = 0x%lx u32CodeStartOffset = 0x%lx \n", u32BitStartOffset,u32CodeStartOffset);
5870
5871 if (u8BitMiuSel != u8CodeMiuSel)
5872 {
5873 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
5874 BDMA_Result bdmaRlt;
5875 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5876
5877 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5878 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
5879 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5880
5881 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
5882
5883 if (E_BDMA_OK != bdmaRlt)
5884 {
5885 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
5886 }
5887 #else
5888 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5889
5890 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5891 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
5892 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5893
5894 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
5895 #endif
5896 }
5897
5898 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
5899
5900 HAL_HVD_EX_FlushMemory();
5901
5902 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5903 {
5904 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
5905 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
5906 }
5907 else
5908 {
5909 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
5910
5911 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5912 }
5913 }
5914
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)5915 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
5916 {
5917 if (bEnable)
5918 {
5919 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5920 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
5921 }
5922 else
5923 {
5924 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
5925 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
5926 }
5927 }
5928
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)5929 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
5930 {
5931 MS_U32 tmp1 = 0;
5932 MS_U32 tmp2 = 0;
5933 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5934
5935 HAL_HVD_EX_ReadMemory();
5936
5937 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
5938 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
5939
5940 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
5941 {
5942 MS_U32 u32Tmp = u32UartCtrl;
5943
5944 HVD_EX_MSG_DBG("\n");
5945 u32UartCtrl = 0; // turn off debug message to prevent other function prints
5946 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
5947 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
5948
5949 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
5950 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
5951 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
5952 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
5953
5954 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
5955 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
5956 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
5957
5958 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
5959 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
5960 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
5961 _HVD_EX_GetESLevel(u32Id));
5962
5963 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
5964 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
5965 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
5966 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
5967 printf
5968 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
5969 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
5970 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
5971 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
5972 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
5973 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
5974 pShm->ModeStatus.bShowOneField);
5975
5976 u32UartCtrl = u32Tmp; // recover debug level
5977 }
5978 }
5979
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)5980 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
5981 {
5982 MS_U8 *u32Addr = NULL;
5983 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5984 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5985
5986 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
5987 {
5988 return;
5989 }
5990
5991 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
5992
5993 *u32NalSize = *(u32Addr + 2) & 0x1f;
5994 *u32NalSize <<= 8;
5995 *u32NalSize |= *(u32Addr + 1) & 0xff;
5996 *u32NalSize <<= 8;
5997 *u32NalSize |= *(u32Addr) & 0xff;
5998
5999 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
6000 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
6001 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
6002 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
6003 }
6004
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)6005 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
6006 {
6007 MS_U32 u32CurIdx = 0;
6008 MS_BOOL bFinished = FALSE;
6009 MS_U32 u32NalOffset = 0;
6010 MS_U32 u32NalSize = 0;
6011 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6012
6013 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
6014 {
6015 return;
6016 }
6017
6018 u32CurIdx = u32StartIdx;
6019
6020 do
6021 {
6022 if (u32CurIdx == u32EndIdx)
6023 {
6024 bFinished = TRUE;
6025 }
6026
6027 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
6028
6029 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
6030 {
6031 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
6032 }
6033
6034 u32CurIdx++;
6035
6036 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6037 {
6038 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6039 }
6040 } while (bFinished == TRUE);
6041 }
6042
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)6043 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
6044 {
6045 MS_U32 i = 0;
6046 MS_U32 value = 0;
6047
6048 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6049 {
6050 HVD_EX_MSG_DBG("\n");
6051
6052 for (i = 0; i <= u32Num; i++)
6053 {
6054 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
6055 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
6056 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
6057
6058 if (value == 0)
6059 {
6060 break;
6061 }
6062
6063 printf(" %08x", value);
6064
6065 if (((i % 8) + 1) == 8)
6066 {
6067 printf(" |%u\n", i + 1);
6068 }
6069 }
6070
6071 printf("\nHVD Dump HW status End: total number:%u\n", i);
6072 }
6073 }
6074
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)6075 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
6076 {
6077 if (pDrvCtrl)
6078 {
6079 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
6080 }
6081 }
6082
6083 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)6084 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
6085 {
6086 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
6087 }
6088
HAL_HVD_EX_GetView(MS_U32 u32Id)6089 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
6090 {
6091 #ifdef VDEC3
6092 if( (0xFF & (u32Id >> 16)) == 0x1)
6093 return E_VDEC_EX_SUB_VIEW;
6094 else
6095 return E_VDEC_EX_MAIN_VIEW;
6096 #else
6097 if( (0xFF & (u32Id >> 8)) == 0x10)
6098 return E_VDEC_EX_MAIN_VIEW;
6099 else
6100 return E_VDEC_EX_SUB_VIEW;
6101 #endif
6102 }
6103 #endif ///HVD_ENABLE_MVC
6104
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)6105 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
6106 {
6107 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
6108 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
6109 return;
6110 }
6111
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)6112 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id)
6113 {
6114 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
6115 return;
6116 }
6117
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)6118 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
6119 {
6120 MS_U64 _hw_max_pixel = 0;
6121 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6122
6123 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6124 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6125 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6126 }
6127
6128
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6129 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6130 {
6131 #if 1
6132 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6133 MS_U16 u16QNum = pShm->u16DispQNumb;
6134 MS_U16 u16QPtr = pShm->u16DispQPtr;
6135 // MS_U16 u16QSize = pShm->u16DispQSize;
6136 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6137 MS_U32 u32DispQNum = 0;
6138 #if HVD_ENABLE_MVC
6139 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6140
6141 if(bMVC)
6142 {
6143 #if 0
6144 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6145 {
6146 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6147 }
6148 #endif
6149
6150 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6151 //search the next frame to display
6152 while (u16QNum > 0)
6153 {
6154 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6155 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6156 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6157
6158 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6159 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6160 {
6161 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6162 /// Check the depned view was initial when Output the base view.
6163 if((u16QPtr%2) == 0)
6164 {
6165 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6166 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6167 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6168 {
6169 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6170 ///printf("Return NULL.\n");
6171 break;
6172 }
6173 }
6174 u32DispQNum++;
6175 }
6176
6177 u16QNum--;
6178 //go to next frame in the dispQ
6179 u16QPtr++;
6180
6181 if (u16QPtr >= pShm->u16DispQSize)
6182 {
6183 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6184 }
6185 }
6186 }
6187 else
6188 #endif ///HVD_ENABLE_MVC
6189 {
6190 #if 0
6191 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6192 {
6193 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6194 }
6195 #endif
6196 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6197 //search the next frame to display
6198 while (u16QNum != 0)
6199 {
6200 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6201
6202 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6203 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6204 {
6205 u32DispQNum++;
6206 }
6207
6208 u16QNum--;
6209 //go to next frame in the dispQ
6210 u16QPtr++;
6211
6212 if (u16QPtr == pShm->u16DispQSize)
6213 {
6214 u16QPtr = 0; //wrap to the begin
6215 }
6216 }
6217 }
6218
6219 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6220 return u32DispQNum;
6221 #else
6222 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6223 return pShm->u16DispQNumb;
6224 #endif
6225 }
6226
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6227 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6228 {
6229 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6230 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
6231 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6232 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6233 #if SUPPORT_G2VP9 && defined(VDEC3)
6234 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6235 #else // Not using G2 VP9 implies using Mstar EVD VP9
6236 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6237 #endif
6238 else
6239 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6240 }
6241
6242 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)6243 void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)
6244 {
6245 if (bEnable)
6246 {
6247 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6248 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6249 }
6250 else
6251 {
6252 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6253 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6254 }
6255
6256 switch (pHVDHalContext->u32EVDClockType)
6257 {
6258 case 240:
6259 {
6260 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_288MHZ, TOP_CKG_EVD_PPU_MASK);
6261 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6262 break;
6263 }
6264 case 216:
6265 {
6266 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6267 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_216MHZ, TOP_CKG_EVD_MASK);
6268 break;
6269 }
6270 case 172:
6271 {
6272 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_216MHZ, TOP_CKG_EVD_PPU_MASK);
6273 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_172MHZ, TOP_CKG_EVD_MASK);
6274 break;
6275 }
6276 case 160:
6277 {
6278 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_172MHZ, TOP_CKG_EVD_PPU_MASK);
6279 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_160MHZ, TOP_CKG_EVD_MASK);
6280 break;
6281 }
6282 default:
6283 {
6284 _HVD_WriteByteMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_288MHZ, TOP_CKG_EVD_PPU_MASK);
6285 _HVD_WriteByteMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6286 break;
6287 }
6288 }
6289
6290 return;
6291 }
6292
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6293 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6294 {
6295 #ifndef VDEC3
6296 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6297 #endif
6298 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6299 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6300 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6301
6302 #ifdef VDEC3
6303 if (0 == pCtrl->u32BBUId)
6304 #else
6305 if (0 == u8TaskId)
6306 #endif
6307 {
6308 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6309 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6310 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)) & (~HVD_REG_BBU_TSP_INPUT));
6311 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)));
6312 }
6313 else
6314 {
6315 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6316 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6317 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)) & (~HVD_REG_BBU_TSP_INPUT_BS2));
6318 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)));
6319 }
6320
6321 return;
6322 }
6323
HAL_EVD_EX_DeinitHW(void)6324 static MS_BOOL HAL_EVD_EX_DeinitHW(void)
6325 {
6326 MS_U16 u16Timeout = 1000;
6327
6328 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6329
6330 while (u16Timeout)
6331 {
6332 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6333 {
6334 break;
6335 }
6336 u16Timeout--;
6337 }
6338
6339 HAL_EVD_EX_PowerCtrl(FALSE);
6340
6341 return TRUE;
6342 }
6343 #endif
6344
6345 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6346 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6347 {
6348 if (bEnable)
6349 {
6350 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6351 }
6352 else
6353 {
6354 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6355 }
6356
6357 switch (pHVDHalContext->u32VP9ClockType)
6358 {
6359 case 432:
6360 {
6361 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6362 break;
6363 }
6364 case 384:
6365 {
6366 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6367 break;
6368 }
6369 case 345:
6370 {
6371 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6372 break;
6373 }
6374 case 320:
6375 {
6376 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6377 break;
6378 }
6379 case 288:
6380 {
6381 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6382 break;
6383 }
6384 case 240:
6385 {
6386 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6387 break;
6388 }
6389 case 216:
6390 {
6391 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6392 break;
6393 }
6394 case 456:
6395 {
6396 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_EVDPLL, TOP_CKG_VP9_CLK_MASK);
6397 break;
6398 }
6399 case 480:
6400 {
6401 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_EVDPLL, TOP_CKG_VP9_CLK_MASK);
6402 break;
6403 }
6404 default:
6405 {
6406 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6407 break;
6408 }
6409 }
6410
6411 return;
6412 }
6413
HAL_VP9_EX_DeinitHW(void)6414 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6415 {
6416 MS_U16 u16Timeout = 1000;
6417
6418 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6419
6420 while (u16Timeout)
6421 {
6422 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6423 {
6424 break;
6425 }
6426 u16Timeout--;
6427 }
6428
6429 HAL_VP9_EX_PowerCtrl(FALSE);
6430
6431 return TRUE;
6432 }
6433 #endif
6434
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6435 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6436 {
6437 return TRUE;
6438 }
6439
6440 #if 0
6441 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
6442 {
6443 _HVD_EX_SetBufferAddr(u32Id);
6444 }
6445 #endif //20170110
6446
HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)6447 void HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)
6448 {
6449 MS_VIRT u32StAddr = 0;
6450 MS_U8 u8BitMiuSel = 0;
6451 MS_U8 u8CodeMiuSel = 0;
6452 MS_U8 u8TmpMiuSel = 0;
6453 MS_U32 u32BitStartOffset;
6454 MS_U32 u32CodeStartOffset;
6455
6456 #ifndef VDEC3
6457 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6458 #endif
6459 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6460 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6461 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6462 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6463
6464 _HAL_HVD_Entry();
6465
6466 if (pCtrl == NULL)
6467 {
6468 _HAL_HVD_Return();
6469 }
6470
6471 MS_BOOL bNalTblAlreadySet = FALSE;
6472 VPU_EX_TaskInfo taskInfo;
6473 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
6474 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
6475
6476 bNalTblAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6477
6478
6479
6480 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6481 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6482
6483 if (u8BitMiuSel != u8CodeMiuSel)
6484 {
6485 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
6486 }
6487 else
6488 {
6489 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
6490 }
6491
6492 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6493 {
6494 #ifdef VDEC3
6495 if (!_HAL_EX_BBU_VP8_InUsed())
6496 #endif
6497 {
6498 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
6499
6500 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
6501 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
6502 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6503
6504 u32StAddr += VP8_BBU_TBL_SIZE;
6505
6506 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
6507 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
6508 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6509 }
6510
6511 _HAL_HVD_Return();
6512 }
6513
6514 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
6515
6516 #ifdef VDEC3
6517 if (!bNalTblAlreadySet)
6518 {
6519 if (pCtrl->u32BBUId == 0)
6520 {
6521 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6522 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6523 // -1 is for NAL_TAB_LEN counts from zero.
6524 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6525 }
6526 else
6527 {
6528 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6529 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6530 // -1 is for NAL_TAB_LEN counts from zero.
6531 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6532 }
6533 }
6534 #else
6535 if (0 == u8TaskId)
6536 {
6537 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6538 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6539 // -1 is for NAL_TAB_LEN counts from zero.
6540 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6541 }
6542 else
6543 {
6544 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6545 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6546 // -1 is for NAL_TAB_LEN counts from zero.
6547 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6548 }
6549 #endif
6550
6551
6552 #if (HVD_ENABLE_MVC)
6553 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
6554 {
6555 /// Used sub stream to record sub view data.
6556 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
6557 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
6558
6559 if (u8BitMiuSel != u8CodeMiuSel)
6560 {
6561 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
6562 }
6563 else
6564 {
6565 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
6566 }
6567
6568 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
6569 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
6570 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
6571 // -1 is for NAL_TAB_LEN counts from zero.
6572 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
6573 }
6574 #endif
6575
6576 if (!bNalTblAlreadySet)
6577 {
6578 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6579 }
6580
6581 _HAL_HVD_Return();
6582 }
6583
6584 /*
6585 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6586 {
6587 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6588
6589 if(pCtrl->InitParams.u16ChipECONum == 0)
6590 return FALSE;
6591 else
6592 return TRUE;
6593
6594 }
6595 */
6596
_HVD_EX_IS_BBU_TSP_MODE(MS_U32 u32Id)6597 MS_BOOL _HVD_EX_IS_BBU_TSP_MODE(MS_U32 u32Id)
6598 {
6599 return FALSE;
6600 }
_HVD_EX_BBU_Get_TaskRunning(MS_U32 u32Id)6601 MS_BOOL _HVD_EX_BBU_Get_TaskRunning(MS_U32 u32Id)
6602 {
6603 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6604 return pHVDHalContext->bBBU_running[u8Idx];
6605 }
6606
_HVD_EX_BBU_Set_TaskRunning(MS_U32 u32Id,MS_BOOL val)6607 void _HVD_EX_BBU_Set_TaskRunning(MS_U32 u32Id,MS_BOOL val)
6608 {
6609 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6610 pHVDHalContext->bBBU_running[u8Idx] = val;
6611 }
6612
_HVD_EX_GetESOffsetIncrease(MS_U32 u32Id,MS_U32 inc,MS_U32 offset)6613 MS_U32 _HVD_EX_GetESOffsetIncrease(MS_U32 u32Id, MS_U32 inc, MS_U32 offset)
6614 {
6615 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6616 return (offset + inc < pCtrl->MemMap.u32BitstreamBufSize)?(offset + inc):(offset + inc - pCtrl->MemMap.u32BitstreamBufSize);
6617 }
6618
_HVD_EX_GetESOffsetMinus(MS_U32 u32Id,MS_U32 mis,MS_U32 offset)6619 MS_U32 _HVD_EX_GetESOffsetMinus(MS_U32 u32Id, MS_U32 mis, MS_U32 offset)
6620 {
6621 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6622 return (offset >= mis)?(offset - mis):(offset + pCtrl->MemMap.u32BitstreamBufSize - mis);
6623 }
6624
_HVD_EX_ES_DBG_PRINT(MS_U32 u32Id,MS_U32 offset,MS_U32 length)6625 void _HVD_EX_ES_DBG_PRINT(MS_U32 u32Id, MS_U32 offset, MS_U32 length)
6626 {
6627 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6628 int idx = 0;
6629 MS_U32 newOffset = 0;
6630 HVD_PRINT("\033[1;33m [%s][%s] %d offset = %x \n\033[1;36m",__FILE__,__FUNCTION__,__LINE__,(unsigned int)offset);
6631 for(idx = 0;idx<length;idx++)
6632 {
6633 newOffset = _HVD_EX_GetESOffsetIncrease(u32Id, idx, offset);
6634 char* tempPtr = (char*)(pCtrl->MemMap.u32BitstreamBufVAddr + newOffset);
6635 HVD_PRINT("%02x ",(unsigned int)(*tempPtr));
6636
6637 if(idx % 4 ==3 || idx % 8 == 7)
6638 HVD_PRINT(" ");
6639 if(idx % 32 ==31)
6640 HVD_PRINT("\n");
6641 }
6642 }
6643
_HVD_EX_BBU_FindStartCode(MS_U32 u32Id,MS_U32 * u32Offset,MS_U32 u32ESRptr,MS_U32 u32ESWptr)6644 MS_BOOL _HVD_EX_BBU_FindStartCode(MS_U32 u32Id,MS_U32* u32Offset, MS_U32 u32ESRptr, MS_U32 u32ESWptr)
6645 {
6646
6647 return false;
6648 }
6649
6650
6651
HAL_HVD_EX_BBU_Task(MS_U32 u32Id)6652 void HAL_HVD_EX_BBU_Task(MS_U32 u32Id)
6653 {
6654
6655 }
6656
6657
6658
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6659 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6660 {
6661
6662
6663 }
6664
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6665 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6666 {
6667
6668 }
HAL_HVD_EX_GetEVDHWBuffer(void)6669 MS_U32 HAL_HVD_EX_GetEVDHWBuffer(void)
6670 {
6671 return EVD_HW_BUFFER;
6672 }
6673 #endif
6674