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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE) 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 121 #define VPU_FORCE_MIU_MODE 1 122 #define HVD_ENABLE_IQMEM 0 123 #define VPU_IQMEM_BASE 0xe0000000 124 125 126 #define ENABLE_DECOMPRESS_FUNCTION TRUE 127 128 #define VPU_CLOCK_240MHZ BITS(4:2,0) 129 #define VPU_CLOCK_216MHZ BITS(4:2,1) 130 #define VPU_CLOCK_192MHZ BITS(4:2,2) 131 #define VPU_CLOCK_12MHZ BITS(4:2,3) 132 #define VPU_CLOCK_320MHZ BITS(4:2,4) 133 #define VPU_CLOCK_288MHZ BITS(4:2,5) 134 #define VPU_CLOCK_432MHZ BITS(4:2,6) 135 #define VPU_CLOCK_384MHZ BITS(4:2,7) 136 137 138 #define VPU_HI_MBOX0 0 139 #define VPU_HI_MBOX1 1 140 #define VPU_RISC_MBOX0 2 141 #define VPU_RISC_MBOX1 3 142 143 144 #define VPU_EX_TimerDelayMS(x) \ 145 do \ 146 { \ 147 volatile MS_U32 ticks = 0; \ 148 while (ticks < (((MS_U32) (x)) << 13)) \ 149 { \ 150 ticks++; \ 151 } \ 152 } while(0) 153 154 #ifdef VDEC3 155 #define HAL_VPU_INVALID_BBU_ID 0xFFFFFFFF 156 #define VPU_MAX_DEC_NUM 16 157 #else 158 #define VPU_MAX_DEC_NUM 2 159 #endif 160 #define CHECK_NULL_PTR(vbbu_addr) (((void *)(vbbu_addr)) == NULL) 161 162 //------------------------------------------------------------------------------------------------- 163 // Type and Structure 164 //------------------------------------------------------------------------------------------------- 165 typedef enum 166 { 167 E_HAL_HVD_STREAM_NONE = 0x0, 168 169 //Support TSP/TS/File mode 170 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 171 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 172 E_HAL_HVD_MAIN_STREAM_MAX, 173 174 //Only support file mode 175 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 176 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 177 E_HAL_HVD_SUB_STREAM1, 178 E_HAL_HVD_SUB_STREAM_MAX, 179 180 #ifdef VDEC3 181 E_HAL_HVD_N_STREAM_BASE = 0x40, 182 E_HAL_HVD_N_STREAM0 = E_HAL_HVD_N_STREAM_BASE, 183 E_HAL_HVD_N_STREAM_MAX = E_HAL_HVD_N_STREAM0 + VPU_MAX_DEC_NUM, 184 #endif 185 186 //Only support MVC stream 187 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 188 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 189 E_HAL_HVD_MVC_Sub_View, 190 E_HAL_HVD_MVC_STREAM_MAX, 191 } HAL_HVD_StreamId; 192 193 typedef enum 194 { 195 E_VPU_EX_DECODER_NONE = 0, 196 E_VPU_EX_DECODER_GET, 197 E_VPU_EX_DECODER_GET_MVC, 198 E_VPU_EX_DECODER_MVD, 199 E_VPU_EX_DECODER_HVD, 200 E_VPU_EX_DECODER_MJPEG, 201 E_VPU_EX_DECODER_RVD, 202 E_VPU_EX_DECODER_MVC, 203 E_VPU_EX_DECODER_VP8, 204 #ifdef VDEC3 205 E_VPU_EX_DECODER_EVD, 206 #if SUPPORT_G2VP9 207 E_VPU_EX_DECODER_G2VP9, 208 #endif 209 #endif 210 } VPU_EX_DecoderType; 211 212 #ifdef CONFIG_MSTAR_CLKM 213 typedef enum 214 { 215 E_VPU_EX_CLKPORT_MVD = 0, 216 E_VPU_EX_CLKPORT_MVD_CORE, 217 E_VPU_EX_CLKPORT_MVD_PAS, 218 E_VPU_EX_CLKPORT_HVD, 219 E_VPU_EX_CLKPORT_HVD_IDB, 220 E_VPU_EX_CLKPORT_HVD_AEC, 221 E_VPU_EX_CLKPORT_HVD_AEC_LITE, 222 E_VPU_EX_CLKPORT_VP8, 223 E_VPU_EX_CLKPORT_EVD, 224 E_VPU_EX_CLKPORT_EVD_PPU, 225 E_VPU_EX_CLKPORT_EVD_LITE, 226 E_VPU_EX_CLKPORT_EVD_PPU_LITE, 227 E_VPU_EX_CLKPORT_VD_MHEG5, 228 E_VPU_EX_CLKPORT_VD_MHEG5_LITE, 229 } VPU_EX_ClkPortType; 230 #endif 231 232 typedef enum 233 { 234 E_VPU_EX_CLOCK_240MHZ = VPU_CLOCK_240MHZ, 235 E_VPU_EX_CLOCK_216MHZ = VPU_CLOCK_216MHZ, 236 E_VPU_EX_CLOCK_192MHZ = VPU_CLOCK_192MHZ, 237 E_VPU_EX_CLOCK_12MHZ = VPU_CLOCK_12MHZ, 238 E_VPU_EX_CLOCK_320MHZ = VPU_CLOCK_320MHZ, 239 E_VPU_EX_CLOCK_288MHZ = VPU_CLOCK_288MHZ, 240 E_VPU_EX_CLOCK_432MHZ = VPU_CLOCK_432MHZ, 241 E_VPU_EX_CLOCK_384MHZ = VPU_CLOCK_384MHZ, 242 243 } VPU_EX_ClockSpeed; 244 245 246 typedef enum 247 { 248 E_HAL_VPU_STREAM_NONE = 0x0, 249 250 //Support TSP/TS File/File mode 251 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 252 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 253 E_HAL_VPU_MAIN_STREAM_MAX, 254 255 //Only support file mode 256 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 257 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 258 E_HAL_VPU_SUB_STREAM_MAX, 259 260 #ifdef VDEC3 261 E_HAL_VPU_N_STREAM_BASE = 0x40, 262 E_HAL_VPU_N_STREAM0 = E_HAL_VPU_N_STREAM_BASE, 263 E_HAL_VPU_N_STREAM_MAX = E_HAL_VPU_N_STREAM0 + VPU_MAX_DEC_NUM, 264 #endif 265 266 //Only support MVC stream 267 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 268 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 269 E_HAL_VPU_MVC_SUB_VIEW, 270 E_HAL_VPU_MVC_STREAM_MAX, 271 } HAL_VPU_StreamId; 272 273 typedef enum 274 { 275 //Support TSP/TS/File mode 276 E_HAL_VPU_MAIN_STREAM, 277 278 //Only support file mode 279 E_HAL_VPU_SUB_STREAM, 280 281 //Only support MVC mode 282 E_HAL_VPU_MVC_STREAM, 283 284 #ifdef VDEC3 285 E_HAL_VPU_N_STREAM, 286 #endif 287 } HAL_VPU_StreamType; 288 289 typedef enum 290 { 291 //Support TSP/TS/File mode 292 E_VPU_EX_INPUT_TSP, 293 //Only support file mode 294 E_VPU_EX_INPUT_FILE, 295 E_VPU_EX_INPUT_NONE, 296 } VPU_EX_SourceType; 297 298 typedef enum 299 { 300 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 301 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 302 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 303 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 304 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 305 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 306 } VPU_EX_UartLevel; 307 308 typedef enum 309 { 310 E_VPU_EX_FW_VER_CTRLR = 0, 311 E_VPU_EX_FW_VER_MVD_FW, 312 E_VPU_EX_FW_VER_HVD_FW, 313 E_VPU_EX_FW_VER_MVD_IF, 314 E_VPU_EX_FW_VER_HVD_IF, 315 } VPU_EX_FWVerType; 316 317 /// DecodeMode for f/w tasks 318 typedef enum 319 { 320 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 321 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 322 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 323 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 324 } VPU_EX_DecMode; 325 326 /// CmdMode for KOREA3D or PIP mode 327 typedef enum 328 { 329 //Group1:Set Korea3DTV mode 330 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 331 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 332 E_VPU_CMD_MODE_KR3D_FORCE_P, 333 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 334 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 335 336 //Group2:Set PIP mode 337 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 338 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 339 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 340 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 341 } VPU_EX_CmdMode; 342 343 #define CMA_DRV_DIRECT_INIT 344 #ifdef CMA_DRV_DIRECT_INIT 345 /// input source select enumerator 346 typedef enum 347 { 348 ///DTV mode 349 E_VPU_EX_SRC_MODE_DTV = 0, 350 ///TS file mode 351 E_VPU_EX_SRC_MODE_TS_FILE, 352 ///generic file mode 353 E_VPU_EX_SRC_MODE_FILE, 354 /// TS file and dual ES buffer mode 355 E_VPU_EX_SRC_MODE_TS_FILE_DUAL_ES, 356 ///generic file and dual ES buffer mode 357 E_VPU_EX_SRC_MODE_FILE_DUAL_ES, 358 } VPU_EX_SrcMode; 359 #endif 360 361 /// codec type enumerator 362 typedef enum 363 { 364 ///unsupported codec type 365 E_VPU_EX_CODEC_TYPE_NONE = 0, 366 ///MPEG 1/2 367 E_VPU_EX_CODEC_TYPE_MPEG2, 368 ///H263 (short video header) 369 E_VPU_EX_CODEC_TYPE_H263, 370 ///MPEG4 (default) 371 E_VPU_EX_CODEC_TYPE_MPEG4, 372 ///MPEG4 (Divx311) 373 E_VPU_EX_CODEC_TYPE_DIVX311, 374 ///MPEG4 (Divx412) 375 E_VPU_EX_CODEC_TYPE_DIVX412, 376 ///FLV 377 E_VPU_EX_CODEC_TYPE_FLV, 378 ///VC1 advanced profile (VC1) 379 E_VPU_EX_CODEC_TYPE_VC1_ADV, 380 ///VC1 main profile (RCV) 381 E_VPU_EX_CODEC_TYPE_VC1_MAIN, 382 ///Real Video version 8 383 E_VPU_EX_CODEC_TYPE_RV8, 384 ///Real Video version 9 and 10 385 E_VPU_EX_CODEC_TYPE_RV9, 386 ///H264 387 E_VPU_EX_CODEC_TYPE_H264, 388 ///AVS 389 E_VPU_EX_CODEC_TYPE_AVS, 390 ///MJPEG 391 E_VPU_EX_CODEC_TYPE_MJPEG, 392 ///MVC 393 E_VPU_EX_CODEC_TYPE_MVC, 394 ///VP8 395 E_VPU_EX_CODEC_TYPE_VP8, 396 ///HEVC 397 E_VPU_EX_CODEC_TYPE_HEVC, 398 ///VP9 399 E_VPU_EX_CODEC_TYPE_VP9, 400 // HEVC Dolby vision 401 E_VPU_EX_CODEC_TYPE_HEVC_DV, 402 E_VPU_EX_CODEC_TYPE_NUM 403 } VPU_EX_CodecType; 404 405 typedef struct 406 { 407 VPU_EX_ClockSpeed eClockSpeed; 408 MS_BOOL bClockInv; 409 MS_S32 s32VPUMutexID; 410 MS_U32 u32VPUMutexTimeout; 411 MS_U8 u8MiuSel; 412 } VPU_EX_InitParam; 413 414 typedef struct 415 { 416 MS_U32 u32Id; 417 HAL_VPU_StreamId eVpuId; 418 VPU_EX_SourceType eSrcType; 419 VPU_EX_DecoderType eDecType; 420 MS_U8 u8HalId; // hal MVD/HVD id 421 MS_U32 u32HeapSize; 422 } VPU_EX_TaskInfo; 423 424 typedef struct 425 { 426 MS_VIRT u32DstAddr; 427 MS_VIRT u32DstSize; 428 MS_VIRT u32BinSize; 429 MS_VIRT u32BinAddr; 430 MS_U8 u8SrcType; 431 } VPU_EX_FWCodeCfg; 432 433 typedef struct 434 { 435 MS_VIRT u32DstAddr; 436 MS_VIRT u32BinAddr; 437 MS_VIRT u32BinSize; 438 MS_VIRT u32FrameBufAddr; 439 MS_VIRT u32VLCTableOffset; 440 } VPU_EX_VLCTblCfg; 441 442 #ifdef VDEC3 443 typedef struct 444 { 445 MS_VIRT u32FrameBufAddr; 446 MS_VIRT u32FrameBufSize; 447 } VPU_EX_FBCfg; 448 #endif 449 450 /// VPU init parameters for dual decoder 451 typedef struct 452 { 453 VPU_EX_FWCodeCfg *pFWCodeCfg; 454 VPU_EX_TaskInfo *pTaskInfo; 455 VPU_EX_VLCTblCfg *pVLCCfg; 456 #ifdef VDEC3 457 VPU_EX_FBCfg *pFBCfg; 458 #endif 459 } VPU_EX_NDecInitPara; 460 461 typedef struct 462 { 463 MS_U8 u8DecMod; 464 MS_U8 u8CodecCnt; 465 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 466 MS_U8 u8ArgSize; 467 MS_U32 u32Arg; 468 } VPU_EX_DecModCfg; 469 470 471 typedef enum 472 { 473 E_VDEC_EX_CODEC_PROFILE_NONE, 474 475 E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, 476 477 E_VDEC_EX_CODEC_PROFILE_MP4_ASP, 478 479 E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, 480 481 E_VDEC_EX_CODEC_PROFILE_VC1_AP, 482 483 E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, 484 485 E_VDEC_EX_CODEC_PROFILE_VP9_0, 486 E_VDEC_EX_CODEC_PROFILE_VP9_2, 487 488 E_VDEC_EX_CODEC_PROFILE_H264_CBP, 489 E_VDEC_EX_CODEC_PROFILE_H264_BP, 490 E_VDEC_EX_CODEC_PROFILE_H264_XP, 491 E_VDEC_EX_CODEC_PROFILE_H264_MP, 492 E_VDEC_EX_CODEC_PROFILE_H264_HIP, 493 E_VDEC_EX_CODEC_PROFILE_H264_PHIP, 494 E_VDEC_EX_CODEC_PROFILE_H264_CHIP, 495 E_VDEC_EX_CODEC_PROFILE_H264_HI10P, 496 E_VDEC_EX_CODEC_PROFILE_H264_HI422P, 497 E_VDEC_EX_CODEC_PROFILE_H264_HI444PP, 498 499 E_VDEC_EX_CODEC_PROFILE_H265_MAIN, 500 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, 501 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_12, 502 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_10, 503 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_12, 504 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444, 505 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_10, 506 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_12, 507 508 E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, 509 510 511 } VDEC_EX_CODEC_CAP_PROFILE_INFO; 512 513 typedef enum 514 { 515 E_VDEC_EX_CODEC_LEVEL_NONE, 516 517 E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, 518 519 E_VDEC_EX_CODEC_LEVEL_MP4_L5, 520 521 E_VDEC_EX_CODEC_LEVEL_VC1_L3, 522 523 E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, 524 525 526 E_VDEC_EX_CODEC_LEVEL_H264_1, 527 E_VDEC_EX_CODEC_LEVEL_H264_1B, 528 E_VDEC_EX_CODEC_LEVEL_H264_1_1, 529 E_VDEC_EX_CODEC_LEVEL_H264_1_2, 530 E_VDEC_EX_CODEC_LEVEL_H264_1_3, 531 E_VDEC_EX_CODEC_LEVEL_H264_2, 532 E_VDEC_EX_CODEC_LEVEL_H264_2_1, 533 E_VDEC_EX_CODEC_LEVEL_H264_2_2, 534 E_VDEC_EX_CODEC_LEVEL_H264_3, 535 E_VDEC_EX_CODEC_LEVEL_H264_3_1, 536 E_VDEC_EX_CODEC_LEVEL_H264_3_2, 537 E_VDEC_EX_CODEC_LEVEL_H264_4, 538 E_VDEC_EX_CODEC_LEVEL_H264_4_1, 539 E_VDEC_EX_CODEC_LEVEL_H264_4_2, 540 E_VDEC_EX_CODEC_LEVEL_H264_5, 541 E_VDEC_EX_CODEC_LEVEL_H264_5_1, 542 E_VDEC_EX_CODEC_LEVEL_H264_5_2, 543 544 E_VDEC_EX_CODEC_LEVEL_H265_1, 545 E_VDEC_EX_CODEC_LEVEL_H265_2, 546 E_VDEC_EX_CODEC_LEVEL_H265_2_1, 547 E_VDEC_EX_CODEC_LEVEL_H265_3, 548 E_VDEC_EX_CODEC_LEVEL_H265_3_1, 549 E_VDEC_EX_CODEC_LEVEL_H265_4_MT, 550 E_VDEC_EX_CODEC_LEVEL_H265_4_HT, 551 E_VDEC_EX_CODEC_LEVEL_H265_4_1_MT, 552 E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, 553 E_VDEC_EX_CODEC_LEVEL_H265_5_MT, 554 E_VDEC_EX_CODEC_LEVEL_H265_5_HT, 555 E_VDEC_EX_CODEC_LEVEL_H265_5_1_MT, 556 E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, 557 E_VDEC_EX_CODEC_LEVEL_H265_5_2_MT, 558 E_VDEC_EX_CODEC_LEVEL_H265_5_2_HT, 559 E_VDEC_EX_CODEC_LEVEL_H265_6_MT, 560 E_VDEC_EX_CODEC_LEVEL_H265_6_HT, 561 E_VDEC_EX_CODEC_LEVEL_H265_6_1_MT, 562 E_VDEC_EX_CODEC_LEVEL_H265_6_1_HT, 563 E_VDEC_EX_CODEC_LEVEL_H265_6_2_MT, 564 E_VDEC_EX_CODEC_LEVEL_H265_6_2_HT, 565 566 E_VDEC_EX_CODEC_LEVEL_AVS_6010860, 567 568 } VDEC_EX_CODEC_CAP_LEVEL_INFO; 569 570 571 typedef enum 572 { 573 E_VDEC_EX_CODEC_VERSION_NONE, 574 575 E_VDEC_EX_CODEC_VERSION_DIVX_311, 576 E_VDEC_EX_CODEC_VERSION_DIVX_4, 577 E_VDEC_EX_CODEC_VERSION_DIVX_5, 578 E_VDEC_EX_CODEC_VERSION_DIVX_6, 579 580 E_VDEC_EX_CODEC_VERSION_FLV_1, 581 582 E_VDEC_EX_CODEC_VERSION_H263_1, 583 584 } VDEC_EX_CODEC_CAP_VERSION_INFO; 585 586 typedef struct 587 { 588 MS_U16 u16CodecCapWidth; 589 MS_U16 u16CodecCapHeight; 590 MS_U8 u8CodecCapFrameRate; 591 VDEC_EX_CODEC_CAP_PROFILE_INFO u8CodecCapProfile; 592 VDEC_EX_CODEC_CAP_VERSION_INFO u8CodecCapVersion; 593 VDEC_EX_CODEC_CAP_LEVEL_INFO u8CodecCapLevel; 594 MS_U32 u32CodecType; 595 MS_U32 u32Reserved1; 596 }VDEC_EX_CODEC_CAP_INFO; 597 598 //------------------------------------------------------------------------------------------------- 599 // Function and Variable 600 //------------------------------------------------------------------------------------------------- 601 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 602 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 603 #ifdef VDEC3 604 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId); 605 #else 606 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 607 #endif 608 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 609 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 610 611 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 612 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase); 613 614 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 615 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 616 MS_BOOL HAL_VPU_EX_DeInit(void); 617 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 618 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 619 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr); 620 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 621 void HAL_VPU_EX_SwRstRelse(void); 622 void HAL_VPU_EX_SwRelseMAU(void); 623 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Address); 624 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Address, MS_U32 u32Value); 625 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 626 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 627 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 628 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 629 MS_U32 HAL_VPU_EX_GetProgCnt(void); 630 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 631 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr); 632 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 633 MS_BOOL HAL_VPU_EX_IsPowered(void); 634 MS_BOOL HAL_VPU_EX_IsRsted(void); 635 MS_BOOL HAL_VPU_EX_IsEVDR2(void); 636 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 637 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 638 #ifdef VDEC3 639 MS_BOOL HAL_VPU_EX_EVDInUsed(void); 640 #if SUPPORT_G2VP9 641 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void); 642 #endif 643 #endif 644 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable); 645 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 646 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 647 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 648 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 649 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo); 650 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id); 651 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id); 652 void HAL_VPU_EX_Mutex_Lock(void); 653 void HAL_VPU_EX_Mutex_UnLock(void); 654 655 MS_VIRT HAL_VPU_EX_MIU1BASE(void); 656 MS_VIRT HAL_VPU_EX_GetSHMAddr(void); 657 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 658 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr); 659 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 660 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass); 661 662 void HAL_VPU_EX_ForceSwRst(void); 663 664 #ifdef VDEC3 665 typedef enum 666 { 667 E_HVD_CMDQ_CMD, 668 E_HVD_CMDQ_ARG, 669 } HVD_COMMAND_QUEUE_TYPE; 670 671 typedef enum 672 { 673 E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL, 674 E_HVD_COMMAND_QUEUE_NOT_INITIALED, 675 E_HVD_COMMAND_QUEUE_FULL, 676 E_HVD_COMMAND_QUEUE_SEND_FAIL, 677 } HVD_DRAM_COMMAND_QUEUE_SEND_STATUS; 678 679 680 typedef struct 681 { 682 MS_VIRT u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 683 MS_U32 u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 684 MS_U64 u64TimeStamp; ///< Packet time stamp. unit: ms. 685 MS_U32 u32ID_L; ///< Packet ID low part. 686 MS_U32 u32ID_H; ///< Packet ID high part. 687 } HAL_VPU_EX_PacketInfo; 688 // *****************Virtual BBU function***************** 689 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr); 690 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr); 691 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 692 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 693 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr); 694 // *****************General dram command queue function***************** 695 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd); 696 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd); 697 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg); 698 // *****************Dram command queue function***************** 699 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue); 700 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue); 701 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 702 // *****************Display dram command queue function***************** 703 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue); 704 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue); 705 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 706 // *****************General purpose function***************** 707 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr); 708 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bIsNstreamMode); 709 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo); 710 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType, MS_U8 u8CMAHeapIdx); 711 #ifdef CMA_DRV_DIRECT_INIT 712 // *****************CMA function***************** 713 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode, 714 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize, MS_U8 u8CMAHeapIdx); 715 #endif 716 #endif 717 #ifdef VDEC3_FB 718 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType); 719 #endif 720 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size); 721 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx); 722 MS_U8 HAL_VPU_EX_CheckFreeStream(void); 723 #ifdef CONFIG_MSTAR_CLKM 724 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable); 725 #endif 726 727 #else 728 typedef struct 729 { 730 MS_PHY Bitstream_Addr_Main; 731 MS_U32 Bitstream_Len_Main; 732 MS_PHY Bitstream_Addr_Sub; 733 MS_U32 Bitstream_Len_Sub; 734 MS_PHY MIU1_BaseAddr; 735 } VPU_EX_LOCK_DOWN_REGISTER; 736 737 738 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr); 739 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 740 741 #endif 742 #endif // _HAL_VPU_EX_H_ 743 744