1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
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11 //
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15 //
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
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90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114 #include "drvSYS.h"
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #else
150 #ifndef ANDROID
151 #define VPRINTF printf
152 #else
153 #include <sys/mman.h>
154 #include <cutils/ashmem.h>
155 #include <cutils/log.h>
156 #define VPRINTF ALOGD
157 #endif
158 #endif
159
160 #ifdef CONFIG_MSTAR_CLKM
161 #include "drvCLKM.h"
162 #endif
163 //-------------------------------------------------------------------------------------------------
164 // Driver Compiler Options
165 //-------------------------------------------------------------------------------------------------
166
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Defines
170 //-------------------------------------------------------------------------------------------------
171 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
172
173 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
174 #ifdef VDEC3
175 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
176 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
177 #define MAX_MVD_SLQ_COUNT 2
178 #define MAX_SUPPORT_DECODER_NUM 16
179 #else
180 #define MAX_SUPPORT_DECODER_NUM 2
181 #endif
182 typedef enum
183 {
184 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
185 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
186 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
187 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
188
189
190 typedef enum
191 {
192 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
193 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
194 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
195 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
196 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
197 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
198
199 typedef enum
200 {
201 E_VPU_UART_CTRL_DISABLE = BIT(4),
202 E_VPU_UART_CTRL_ERR = BIT(0),
203 E_VPU_UART_CTRL_INFO = BIT(1),
204 E_VPU_UART_CTRL_DBG = BIT(2),
205 E_VPU_UART_CTRL_FW = BIT(3),
206 E_VPU_UART_CTRL_MUST = BIT(4),
207 E_VPU_UART_CTRL_TRACE = BIT(5),
208 } VPU_EX_UartCtrl;
209
210 typedef struct
211 {
212 HAL_VPU_StreamId eStreamId;
213 VPU_EX_DecoderType eDecodertype;
214 } VPU_EX_Stream;
215
216
217 #define VPU_MSG_ERR(format, args...) \
218 do \
219 { \
220 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
221 { \
222 printf("[VPU][ERR]%s:", __FUNCTION__); \
223 printf(format, ##args); \
224 } \
225 } while (0)
226
227 #define VPU_MSG_DBG(format, args...) \
228 do \
229 { \
230 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
231 { \
232 printf("[VPU][DBG]%s:", __FUNCTION__); \
233 printf(format, ##args); \
234 } \
235 } while (0)
236
237 #define VPU_MSG_INFO(format, args...) \
238 do \
239 { \
240 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
241 { \
242 printf("[VPU][INF]%s:", __FUNCTION__); \
243 printf(format, ##args); \
244 } \
245 } while (0)
246
247 //------------------------------ MIU SETTINGS ----------------------------------
248 #ifdef EVDR2
249 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1)) // G31
250 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1)) // G31
251 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2)) // G32
252
253 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1)) // G31
254 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1)) // G31
255 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2)) // G32
256
257 #define VPU_D_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
258 #define VPU_Q_RW_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == 0)
259 #define VPU_I_R_ON_MIU0 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == 0)
260
261 #define VPU_D_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
262 #define VPU_Q_RW_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
263 #define VPU_I_R_ON_MIU1 ((_VPU_ReadByte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
264 #endif
265
266
267
268 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
269 do \
270 { \
271 if (miu_clients##_ON_MIU0 == 1) \
272 { \
273 _MaskMiuReq_##miu_clients(mask); \
274 } \
275 else \
276 { \
277 if (miu_clients##_ON_MIU1 == 1) \
278 { \
279 _MaskMiu1Req_##miu_clients(mask); \
280 } \
281 } \
282 } while(0)
283
284
285
286
287 #if ENABLE_VPU_MUTEX_PROTECTION
288 MS_S32 s32VPUMutexID = -1;
289 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
290
291 #define _HAL_VPU_MutexCreate() \
292 if (s32VPUMutexID < 0) \
293 { \
294 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
295 }
296
297 #define _HAL_VPU_MutexDelete() \
298 if (s32VPUMutexID >= 0) \
299 { \
300 MsOS_DeleteMutex(s32VPUMutexID); \
301 s32VPUMutexID = -1; \
302 }
303
304 #define _HAL_VPU_Entry() \
305 if (s32VPUMutexID >= 0) \
306 { \
307 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
308 { \
309 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
310 } \
311 }
312
313 #define _HAL_VPU_Return(_ret) \
314 { \
315 if (s32VPUMutexID >= 0) \
316 { \
317 MsOS_ReleaseMutex(s32VPUMutexID); \
318 } \
319 return _ret; \
320 }
321
322 #define _HAL_VPU_Release() \
323 { \
324 if (s32VPUMutexID >= 0) \
325 { \
326 MsOS_ReleaseMutex(s32VPUMutexID); \
327 } \
328 }
329 #else
330 #define _HAL_VPU_MutexCreate()
331 #define _HAL_VPU_MutexDelete()
332 #define _HAL_VPU_Entry()
333 #define _HAL_VPU_Return(_ret) {return _ret;}
334 #define _HAL_VPU_Release()
335 #endif
336
337 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
338 #define VPU_CMD_TIMEOUT 1000 // 1 sec
339
340 //-------------------------------------------------------------------------------------------------
341 // Local Structures
342 //-------------------------------------------------------------------------------------------------
343 typedef struct _VPU_HWInitFunc
344 {
345 MS_BOOL (*pfMVDHW_Init)(void);
346 MS_BOOL (*pfMVDHW_Deinit)(void);
347 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
348 MS_BOOL (*pfHVDHW_Deinit)(void);
349 } VPU_HWInitFunc;
350
351 typedef struct
352 {
353 MS_U32 u32ApiHW_Version; //<Version of current structure>
354 MS_U16 u16ApiHW_Length; //<Length of this structure>
355
356 MS_U8 u8Cap_Support_Decoder_Num;
357
358 MS_BOOL bCap_Support_MPEG2;
359 MS_BOOL bCap_Support_H263;
360 MS_BOOL bCap_Support_MPEG4;
361 MS_BOOL bCap_Support_DIVX311;
362 MS_BOOL bCap_Support_DIVX412;
363 MS_BOOL bCap_Support_FLV;
364 MS_BOOL bCap_Support_VC1ADV;
365 MS_BOOL bCap_Support_VC1MAIN;
366
367 MS_BOOL bCap_Support_RV8;
368 MS_BOOL bCap_Support_RV9;
369 MS_BOOL bCap_Support_H264;
370 MS_BOOL bCap_Support_AVS;
371 MS_BOOL bCap_Support_AVS_PLUS;
372 MS_BOOL bCap_Support_MJPEG;
373 MS_BOOL bCap_Support_MVC;
374 MS_BOOL bCap_Support_VP8;
375 MS_BOOL bCap_Support_VP9;
376 MS_BOOL bCap_Support_HEVC;
377
378 /*New HW Cap and Feature add in struct at the end*/
379 }VDEC_HwCap;
380
381 //-------------------------------------------------------------------------------------------------
382 // Local Functions Prototype
383 //-------------------------------------------------------------------------------------------------
384 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
385 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
386 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
387
388 //-------------------------------------------------------------------------------------------------
389 // Global Variables
390 //-------------------------------------------------------------------------------------------------
391 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
392 extern MS_BOOL HAL_MVD_InitHW(VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
393 extern MS_BOOL HAL_MVD_DeinitHW(VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
394 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
395 extern MS_BOOL HAL_HVD_EX_DeinitHW(void);
396 extern void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id);
397 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
398 #if SUPPORT_G2VP9 && defined(VDEC3)
399 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
400 #endif
401 #if defined (__aeon__)
402 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
403 #else
404 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
405 #endif
406
407 //-------------------------------------------------------------------------------------------------
408 // Local Variables
409 //-------------------------------------------------------------------------------------------------
410 #if 0
411
412 static MS_BOOL _bVPUPowered = FALSE;
413 static MS_BOOL _bVPURsted = FALSE;
414 static MS_BOOL _bVPUSingleMode = FALSE;
415 static VPU_EX_DecModCfg _stVPUDecMode;
416
417 static MS_U8 u8TaskCnt = 0;
418
419 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
420
421 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
422 static VPU_EX_Stream _stVPUStream[] =
423 {
424 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
425 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
426 };
427 static VPU_HWInitFunc stHWInitFunc =
428 {
429 &HAL_MVD_InitHW,
430 &HAL_MVD_DeinitHW,
431 &HAL_HVD_EX_InitHW,
432 &HAL_HVD_EX_DeinitHW,
433 };
434
435 #endif
436
437 #if VPU_ENABLE_EMBEDDED_FW_BINARY
438 static const MS_U8 u8HVD_FW_Binary[] = {
439 #include "fwVPU.dat"
440 };
441
442 #if HVD_ENABLE_RV_FEATURE
443 static const MS_U8 u8HVD_VLC_Binary[] = {
444 #include "fwVPU_VLC.dat"
445 };
446 #endif
447 #endif
448
449
450 #ifdef VDEC3
451 typedef struct
452 {
453 MS_BOOL bTSP;
454 MS_U32 u32Used;
455 } BBU_STATE;
456
457 typedef struct
458 {
459 MS_BOOL bTSP;
460 MS_BOOL bUsedbyMVD;
461 MS_U32 u32Used;
462 } SLQ_STATE;
463 #endif
464
465 typedef struct
466 {
467 MS_BOOL _bVPUPowered;
468 MS_BOOL _bVPURsted;
469 MS_BOOL _bVPUSingleMode;
470 VPU_EX_DecModCfg _stVPUDecMode;
471 MS_U8 u8TaskCnt;
472 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
473 #ifdef VDEC3
474 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
475 #else
476 VPU_EX_Stream _stVPUStream[2];
477 #endif
478
479 VPU_HWInitFunc stHWInitFunc;
480
481 MS_BOOL bVpuExReloadFW;
482 MS_BOOL bVpuExLoadFWRlt;
483 MS_VIRT u32VPUSHMAddr; //PA
484 MS_BOOL bEnableVPUSecureMode;
485
486 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
487 MS_BOOL bEnableDymanicFBMode;
488 MS_PHY u32DynamicFBAddress;
489 MS_U32 u32DynamicFBSize;
490 #ifdef VDEC3
491 MS_VIRT u32FWCodeAddr;
492 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
493
494 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
495 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
496 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
497
498 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
499 #endif
500 MS_U8 u8ForceRst;
501 } VPU_Hal_CTX;
502
503 //global variables
504 VPU_Hal_CTX* pVPUHalContext = NULL;
505 VPU_Hal_CTX gVPUHalContext;
506 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
507 MS_BOOL bVPUMbxInitFlag = 0;
508 MS_U8 u8VPUMbxMsgClass = 0;
509 MBX_Msg VPUReeToTeeMbxMsg;
510 MBX_Msg VPUTeeToReeMbxMsg;
511
512 //-------------------------------------------------------------------------------------------------
513 // Debug Functions
514 //-------------------------------------------------------------------------------------------------
515
516
517 //-------------------------------------------------------------------------------------------------
518 // Local Functions
519 //-------------------------------------------------------------------------------------------------
520
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)521 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
522 {
523 #if HVD_ENABLE_RV_FEATURE
524 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
525 {
526 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
527 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
528 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
529
530 if (pVlcCfg->u32BinSize)
531 {
532 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
533
534 MS_U32 u32Start;
535 MS_U32 u32StartOffset;
536 MS_U8 u8MiuSel;
537
538 // Get MIU selection and offset from physical address = 0x30000000
539 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
540
541
542 if(u8MiuSel == E_CHIP_MIU_0)
543 cpyflag = E_SPIDMA_DEV_MIU0;
544 else if(u8MiuSel == E_CHIP_MIU_1)
545 cpyflag = E_SPIDMA_DEV_MIU1;
546 else if(u8MiuSel == E_CHIP_MIU_2)
547 cpyflag = E_SPIDMA_DEV_MIU2;
548
549 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
550 {
551 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
552 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
553
554 return FALSE;
555 }
556 }
557 else
558 {
559 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
560 return FALSE;
561 }
562 #else
563 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
564 return FALSE;
565 #endif
566 }
567 else
568 {
569 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
570 {
571 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
572 {
573 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
574 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
575
576 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
577 BDMA_Result bdmaRlt;
578 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
579
580 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
581 u32SrcAdd = pVlcCfg->u32BinAddr;
582 u32tabsize = pVlcCfg->u32BinSize;
583 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
584 MsOS_FlushMemory();
585 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
586
587 if (E_BDMA_OK != bdmaRlt)
588 {
589 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
590 }
591 #else
592 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
593 #endif
594 }
595 else
596 {
597 VPU_MSG_ERR
598 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
599 return FALSE;
600 }
601 }
602 else
603 {
604 #if VPU_ENABLE_EMBEDDED_FW_BINARY
605 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
606 MS_U8 *pu8HVD_VLC_Binary;
607
608 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
609
610 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
611 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
612 (MS_U32) sizeof(u8HVD_VLC_Binary));
613
614 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
615 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
616 #else
617 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
618 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
619 (MS_U32) sizeof(u8HVD_VLC_Binary));
620
621 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
622 #endif
623 #else
624 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
625 return FALSE;
626 #endif
627 }
628 }
629 #endif
630
631 return TRUE;
632 }
633
634 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)635 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
636 {
637 MS_U8 u8OffsetIdx = 0;
638 MS_U8 u8VSidBaseMask = 0xF0;
639 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
640
641 switch (eVSidBase)
642 {
643 case E_HAL_VPU_MAIN_STREAM_BASE:
644 {
645 u8OffsetIdx = 0;
646 break;
647 }
648 case E_HAL_VPU_SUB_STREAM_BASE:
649 {
650 u8OffsetIdx = 1;
651 break;
652 }
653 case E_HAL_VPU_MVC_STREAM_BASE:
654 {
655 u8OffsetIdx = 0;
656 break;
657 }
658 #ifdef VDEC3
659 case E_HAL_VPU_N_STREAM_BASE:
660 {
661 u8OffsetIdx = u32Id & 0x0F;
662 break;
663 }
664 #endif
665 default:
666 {
667 u8OffsetIdx = 0;
668 break;
669 }
670 }
671
672 /*
673 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
674 u32Id, eVSidBase, u8OffsetIdx);
675 */
676 return u8OffsetIdx;
677 }
678
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)679 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
680 {
681 return _VPU_EX_GetOffsetIdx(u32Id);
682 }
683
_VPU_EX_Context_Init(void)684 static void _VPU_EX_Context_Init(void)
685 {
686 #ifdef VDEC3
687 MS_U8 i;
688
689 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
690 {
691 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
692 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
693 }
694
695 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
696 {
697 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
698 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
699 }
700
701 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
702 {
703 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
704 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
705 }
706
707 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
708 {
709 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
710 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
711 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
712 }
713 #else
714 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
715 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
716 #endif
717 pVPUHalContext->bVpuExReloadFW = TRUE;
718 pVPUHalContext->u8ForceRst = 0;
719
720 }
721
HAL_VPU_EX_ForceSwRst(void)722 void HAL_VPU_EX_ForceSwRst(void)
723 {
724 pVPUHalContext->u8ForceRst = 1;
725 }
726
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)727 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
728 {
729 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
730 MS_U8 u8OffsetIdx = 0;
731
732 if (NULL == pTaskInfo)
733 {
734 return eCmd;
735 }
736
737 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
738
739 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
740 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
741
742 #ifdef VDEC3
743 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
744 {
745 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
746 {
747 eCmd = E_NST_CMD_TASK_MVD_TSP;
748 }
749 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
750 {
751 eCmd = E_NST_CMD_TASK_MVD_SLQ;
752 }
753 }
754 #else
755 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
756 {
757 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
758 {
759 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
760 }
761 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
762 {
763 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
764 }
765 }
766 #endif
767 #ifdef VDEC3
768 #if SUPPORT_G2VP9
769 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
770 #else
771 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
772 #endif
773 {
774 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
775 {
776 eCmd = E_NST_CMD_TASK_HVD_TSP;
777 }
778 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
779 {
780 eCmd = E_NST_CMD_TASK_HVD_BBU;
781 }
782 }
783 #else
784 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
785 {
786 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
787 {
788 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
789 }
790 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
791 {
792 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
793 }
794 }
795 #endif
796
797 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
798 return eCmd;
799 }
800
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)801 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
802 {
803 if (!pTaskInfo)
804 {
805 VPU_MSG_ERR("null input\n");
806 return FALSE;
807 }
808
809 //Check if we need to init MVD HW
810 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
811 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
812 {
813 //Init HW
814 if (FALSE == HAL_VPU_EX_MVDInUsed())
815 {
816 if (TRUE != HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
817 {
818 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
819 return FALSE;
820 }
821 }
822 else
823 {
824 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
825 }
826 }
827
828 //MVD use sub mvop
829 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
830 #ifdef VDEC3
831 (pTaskInfo->u8HalId == 1) )
832 #else
833 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
834 #endif
835 {
836 VPU_MSG_ERR("Force turn on HVD\n");
837 if(!HAL_VPU_EX_HVDInUsed())
838 {
839 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
840 {
841 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
842 {
843 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
844 return FALSE;
845 }
846 }
847 else
848 {
849 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
850 #ifdef CONFIG_MSTAR_CLKM
851 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
852 #else
853 HAL_HVD_EX_PowerCtrl(TRUE);
854 #endif
855 }
856 }
857 else
858 {
859 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
860 }
861 }
862
863 //Check if we need to init HVD HW
864 #ifdef VDEC3
865 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
866 #else
867 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
868 #endif
869 {
870 if (!HAL_VPU_EX_MVDInUsed())
871 {
872 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
873 {
874 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
875 return FALSE;
876 }
877 }
878
879 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
880 {
881 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
882 return FALSE;
883 }
884 #if SUPPORT_MSVP9
885 if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
886 {
887 _VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); //for VP9 dqmem
888 }
889 #endif
890 }
891
892 #if SUPPORT_G2VP9 && defined(VDEC3)
893 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
894 {
895 if (!HAL_VPU_EX_MVDInUsed())
896 {
897 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
898 {
899 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
900 return FALSE;
901 }
902 }
903 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
904 {
905 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
906 return FALSE;
907 }
908 }
909 #endif
910
911 return TRUE;
912 }
913
_VPU_EX_InClock(MS_U32 u32type)914 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
915 {
916 switch (u32type)
917 {
918 case VPU_CLOCK_240MHZ:
919 return 240000000UL;
920 case VPU_CLOCK_216MHZ:
921 return 216000000UL;
922 case VPU_CLOCK_192MHZ:
923 return 192000000UL;
924 case VPU_CLOCK_12MHZ:
925 return 12000000UL;
926 case VPU_CLOCK_320MHZ:
927 return 320000000UL;
928 case VPU_CLOCK_288MHZ:
929 return 288000000UL;
930 case VPU_CLOCK_432MHZ:
931 return 432000000UL;
932 default:
933 return 384000000UL;
934 }
935 }
936
937
938 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
939 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)940 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
941 {
942 //#ifndef MSOS_TYPE_LINUX_KERNEL
943 #if 1
944 MS_U8 ClassNum = 0;
945 MBX_Result result;
946
947 #if 0
948 if (bVPUMbxInitFlag == TRUE)
949 {
950 return TRUE;
951 }
952 #endif
953
954 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
955 {
956 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
957 return FALSE;
958 }
959 else
960 {
961 MApi_MBX_Enable(TRUE);
962 }
963
964 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
965
966 if (E_MBX_SUCCESS != result)
967 {
968 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
969 return FALSE;
970 }
971
972 result = MApi_MBX_RegisterMSG(ClassNum, 10);
973
974 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
975 {
976 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
977 return FALSE;
978 }
979 else
980 {
981 bVPUMbxInitFlag = TRUE;
982 u8VPUMbxMsgClass = ClassNum;
983 return TRUE;
984 }
985 #else
986 return FALSE;
987 #endif
988 }
989
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)990 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
991 {
992 MBX_Result result;
993 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
994
995 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
996 {
997 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
998 }
999
1000 if (bVPUMbxInitFlag == FALSE)
1001 {
1002 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1003 }
1004
1005 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1006 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1007 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1008 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1009 VPUReeToTeeMbxMsg.u8Index = msg_type;
1010
1011 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1012 if (E_MBX_SUCCESS != result)
1013 {
1014 printf("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1015 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1016 }
1017
1018 // Receive Reply ACK from TEE side.
1019 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1020
1021 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1022
1023 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1024 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1025 {
1026 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1027 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1028 }
1029 else
1030 #else
1031 do
1032 {
1033 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1034 } while(E_MBX_SUCCESS != result);
1035 #endif
1036 {
1037 u8Index = VPUTeeToReeMbxMsg.u8Index;
1038 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1039
1040 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1041 {
1042 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1043 }
1044 }
1045
1046 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1047 }
1048
1049
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1050 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1051 {
1052 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1053 {
1054 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1055 {
1056 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1057 return FALSE;
1058 }
1059 else
1060 {
1061 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1062 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1063 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1064 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1065 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1066 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1067 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1068 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1069
1070 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1071
1072
1073 MS_U32 u32Start;
1074
1075 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1076 {
1077 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1078 pVPUHalContext->u32VPUSHMAddr = u32Start;
1079 }
1080 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1081 {
1082 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1083 pVPUHalContext->u32VPUSHMAddr = u32Start;
1084
1085 }
1086 else // == 0
1087 {
1088 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1089 }
1090 }
1091 }
1092 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1093 {
1094 MS_U32 u32Offset;
1095 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1096 {
1097 u32Offset = u32SHMAddr-u32MIU1Addr;
1098 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1099 }
1100 else
1101 {
1102 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1103 }
1104 }
1105 return TRUE;
1106 }
1107
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1108 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1109 {
1110 bVPUMbxInitFlag = TRUE;
1111 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1112 return TRUE;
1113 }
1114
1115 #endif
1116
HAL_VPU_EX_GetFWReload(void)1117 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1118 {
1119 return pVPUHalContext->bVpuExReloadFW;
1120 }
1121
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1122 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1123 {
1124 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1125 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1126 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1127 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1128 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1129 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1130 )
1131 {
1132 return FALSE;
1133 }
1134 else
1135 {
1136 return TRUE;
1137 }
1138 }
1139
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1140 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1141 {
1142 MS_PHY u32fwPA = NULL; //physical address
1143 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_384MHZ;//20160818 E_VPU_EX_CLOCK_320MHZ patch for mooney clock hw bug
1144
1145 if (TRUE == HAL_VPU_EX_IsPowered())
1146 {
1147 VPU_MSG_DBG("IsPowered\n");
1148 return TRUE;
1149 }
1150 else
1151 {
1152 //VPU hold
1153 HAL_VPU_EX_SwRst(FALSE);
1154
1155 //VPU clock on
1156 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1157
1158 if (VPU_I_R_ON_MIU0)
1159 VPUInitParams.u8MiuSel = 0;
1160 else if (VPU_I_R_ON_MIU1)
1161 VPUInitParams.u8MiuSel = 1;
1162
1163 HAL_VPU_EX_Init(&VPUInitParams);
1164 }
1165
1166 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1167 VPU_EX_TaskInfo *pTaskInfo = NULL;
1168 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1169
1170 if (pInitPara)
1171 {
1172 pFWCodeCfg = pInitPara->pFWCodeCfg;
1173 pTaskInfo = pInitPara->pTaskInfo;
1174 pVlcCfg = pInitPara->pVLCCfg;
1175 }
1176 else
1177 {
1178 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1179 return FALSE;
1180 }
1181
1182 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1183
1184 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1185 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1186 {
1187 SYS_TEEINFO teemode;
1188 MDrv_SYS_ReadKernelCmdLine();
1189 MDrv_SYS_GetTEEInfo(&teemode);
1190 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1191 {
1192 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1193
1194 if (FALSE == HAL_VPU_EX_GetFWReload())
1195 {
1196 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1197 {
1198 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1199 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1200 {
1201 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1202 return FALSE;
1203 }
1204 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1205 }
1206 else
1207 {
1208 //Check f/w prefix "VDEC30"
1209 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1210 {
1211 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1212 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1213 {
1214 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1215 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1216 return FALSE;
1217 }
1218 }
1219 else
1220 {
1221 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1222 }
1223 }
1224 }
1225 else
1226 {
1227 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1228 {
1229 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1230 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1231 return FALSE;
1232 }
1233 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1234 }
1235 }
1236 }
1237 else
1238 #endif
1239 {
1240 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1241
1242 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1243 {
1244 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1245 return FALSE;
1246 }
1247 }
1248
1249 if (pVlcCfg)
1250 {
1251 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1252 {
1253 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1254 return FALSE;
1255 }
1256 }
1257
1258 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1259 {
1260 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1261 return FALSE;
1262 }
1263
1264 //Init HW
1265 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1266 {
1267 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1268 //_MVD_INIT_FAIL_RET();
1269 return FALSE;
1270 }
1271 else
1272 {
1273 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1274 }
1275
1276 //set vpu clock to FW
1277 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1278 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1279
1280 ctl_ptr->statue = CTL_STU_NONE;
1281 //notify controller the interface version of VPU driver.
1282 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1283 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1284 MsOS_FlushMemory();
1285 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1286
1287 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1288 if (TRUE == HAL_VPU_EX_IsRsted())
1289 {
1290 VPU_MSG_DBG("VPU_IsRsted\n");
1291 return TRUE;
1292 }
1293 else
1294 {
1295 HAL_VPU_EX_SwRstRelse();
1296 }
1297
1298 return TRUE;
1299 }
1300
_VPU_EX_DeinitHW(VPU_EX_TaskInfo * pTaskInfo)1301 static MS_BOOL _VPU_EX_DeinitHW(VPU_EX_TaskInfo *pTaskInfo)
1302 {
1303 MS_BOOL bRet = FALSE;
1304
1305 if (FALSE == HAL_VPU_EX_MVDInUsed())
1306 {
1307 bRet = HAL_MVD_DeinitHW(pTaskInfo->eSrcType, pTaskInfo->eDecType);
1308 }
1309
1310 if (FALSE == HAL_VPU_EX_HVDInUsed())
1311 {
1312 bRet = HAL_HVD_EX_DeinitHW();
1313 }
1314 #if SUPPORT_G2VP9 && defined(VDEC3)
1315 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1316 {
1317 bRet = HAL_VP9_EX_DeinitHW();
1318 }
1319 #endif
1320 return bRet;
1321 }
1322
_VPU_EX_DeinitAll(VPU_EX_NDecInitPara * pInitPara)1323 static MS_BOOL _VPU_EX_DeinitAll(VPU_EX_NDecInitPara *pInitPara)
1324 {
1325 HAL_VPU_EX_SwRst(TRUE);
1326 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
1327 HAL_VPU_EX_DeInit();
1328
1329 return TRUE;
1330 }
1331
_VPU_EX_GetActiveCodecCnt(void)1332 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1333 {
1334 MS_U32 i;
1335 MS_U8 u8ActiveCnt = 0;
1336 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1337 {
1338 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1339 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1340 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1341 {
1342 u8ActiveCnt++;
1343 }
1344 }
1345 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1346 {
1347 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1348 }
1349 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1350 return u8ActiveCnt;
1351 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1352 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1353 {
1354 if (TRUE)
1355 {
1356 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1357 }
1358 else
1359 {
1360 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1361 }
1362 }
1363
_VPU_EX_ClockSpeed(MS_U32 u32type)1364 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1365 {
1366 switch (u32type)
1367 {
1368 case VPU_CLOCK_240MHZ:
1369 case VPU_CLOCK_216MHZ:
1370 case VPU_CLOCK_192MHZ:
1371 case VPU_CLOCK_12MHZ:
1372 case VPU_CLOCK_320MHZ:
1373 case VPU_CLOCK_288MHZ:
1374 case VPU_CLOCK_384MHZ:
1375 case VPU_CLOCK_432MHZ:
1376 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1377 break;
1378 default:
1379 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK);
1380 break;
1381 }
1382 _VPU_WriteWordMask((CLKGEN0_REG_BASE+(0x006a<<1)), 0x0, BMASK(2:1));//20160817 patch for mooney clock hw bug, wb clk not div 2
1383 }
1384 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1385 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1386 {
1387 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1388 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1389 {
1390 return TRUE;
1391 }
1392 return FALSE;
1393 }
1394 #endif
1395
1396
1397 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1398 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1399 {
1400 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1401 {
1402 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1403 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1404 ms_VDECDecompressDeInit();
1405 return TRUE;
1406 }
1407 else
1408 {
1409 return FALSE;
1410 }
1411 }
1412 #endif
1413
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1414 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1415 {
1416 MS_BOOL bRet = TRUE;
1417 pVPUHalContext->_bVPUSingleMode = bEnable;
1418 return bRet;
1419 }
1420
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1421 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1422 {
1423 MS_BOOL bRet = TRUE;
1424 MS_U8 i=0;
1425 if (pstCfg != NULL)
1426 {
1427 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1428 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1429 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1430 {
1431 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1432 }
1433 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1434 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1435 }
1436 else
1437 {
1438 bRet = FALSE;
1439 }
1440 return bRet;
1441 }
1442
1443 //static MS_BOOL bVpuExReloadFW = TRUE;
1444 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1445 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1446 {
1447 pVPUHalContext->bVpuExReloadFW = bReload;
1448 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1449 return TRUE;
1450 }
1451
1452
1453 //-------------------------------------------------------------------------------------------------
1454 // Global Functions
1455 //-------------------------------------------------------------------------------------------------
1456 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1457 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1458 {
1459 #if HVD_ENABLE_RV_FEATURE
1460 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1461 {
1462 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1463 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1464 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1465
1466 if (pVlcCfg->u32BinSize)
1467 {
1468 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1469
1470 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1471 {
1472 cpyflag = E_SPIDMA_DEV_MIU1;
1473 }
1474 else
1475 {
1476 cpyflag = E_SPIDMA_DEV_MIU0;
1477 }
1478
1479 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1480 {
1481 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1482 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1483
1484 return FALSE;
1485 }
1486 }
1487 else
1488 {
1489 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1490 return FALSE;
1491 }
1492 #else
1493 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1494 return FALSE;
1495 #endif
1496 }
1497 else
1498 {
1499 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1500 {
1501 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1502 {
1503 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1504 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1505
1506 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1507 BDMA_Result bdmaRlt;
1508
1509 MsOS_FlushMemory();
1510 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1511
1512 if (E_BDMA_OK != bdmaRlt)
1513 {
1514 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1515 }
1516 #else
1517 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1518 #endif
1519 }
1520 else
1521 {
1522 VPU_MSG_ERR
1523 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1524 return FALSE;
1525 }
1526 }
1527 else
1528 {
1529 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1530 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1531 MS_U8 *pu8HVD_VLC_Binary;
1532
1533 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1534
1535 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1536 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1537 (MS_U32) sizeof(u8HVD_VLC_Binary));
1538
1539 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1540 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1541 #else
1542 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1543 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1544 (MS_U32) sizeof(u8HVD_VLC_Binary));
1545
1546 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1547 #endif
1548 #else
1549 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1550 return FALSE;
1551 #endif
1552 }
1553 }
1554 #endif
1555
1556 return TRUE;
1557 }
1558 #endif
1559 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1560 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1561 #else
1562 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1563 #endif
1564 {
1565 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1566 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1567 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1568 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1569 MS_U32 u32Arg = 0xFFFFFFFF;
1570 MS_U32 u32Timeout = 0;
1571 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1572 MS_U32 u32CmdArg = 0;
1573 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1574 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1575
1576 _HAL_VPU_Entry();
1577 //Check FW buffer size
1578 if (1 == u8Offset)
1579 {
1580 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1581 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1582
1583 if (u32CurFWBuffSize < u32MinFWBuffSize)
1584 {
1585 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1586 _HAL_VPU_Release();
1587 return FALSE;
1588 }
1589 }
1590
1591 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1592 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1593 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1594 {
1595 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1596 }
1597 #ifdef VDEC3
1598 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1599 #endif
1600
1601 if (0 == pVPUHalContext->u8TaskCnt)
1602 {
1603 //No task is created, need to load f/w, etc.
1604 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1605
1606 if (!_VPU_EX_InitAll(pInitPara))
1607 {
1608 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1609 _HAL_VPU_Release();
1610 return FALSE;
1611 }
1612
1613 //Check if controller finish initialization: clear mailbox, etc.
1614 //Need to check it before sending any controller commands!
1615 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1616 while (CTL_STU_NONE == ctl_ptr->statue)
1617 {
1618 if (HVD_GetSysTime_ms() > u32Timeout)
1619 {
1620 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1621 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1622 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1623 MS_U32 t=0;
1624 for (t=0; t<30; t++)
1625 {
1626 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1627 }
1628 _HAL_VPU_Release();
1629 return FALSE;
1630 }
1631
1632 MsOS_ReadMemory();
1633 }
1634
1635 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1636 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1637
1638 }
1639 else
1640 {
1641 if (pVPUHalContext->_bVPUSingleMode)
1642 {
1643 //Show error message
1644 printf("This task will use dram instead of sram!!!\n");
1645 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1646 }
1647
1648 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1649 {
1650 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1651 _HAL_VPU_Release();
1652 return FALSE;
1653 }
1654 if (pInitPara->pVLCCfg)
1655 {
1656 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1657 {
1658 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1659 _HAL_VPU_Release();
1660 return FALSE;
1661 }
1662 }
1663 }
1664
1665
1666 #ifdef VDEC3
1667 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1668 {
1669 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1670
1671 memset(pTemp4,0,sizeof(VDEC_VBBU));
1672
1673 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1674
1675 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1676
1677 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1678
1679 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1680
1681 memset(pTemp2,0,sizeof(CMD_QUEUE));
1682
1683 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1684
1685 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1686
1687 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1688
1689 memset(pTemp3,0,0x2000);
1690
1691 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1692
1693 memset((void*)pVersion,0,0x8);
1694
1695 *pVersion = 1; //0:diu, 1:wb
1696 }
1697
1698 #endif
1699
1700 #if 1 // For TEE
1701 #ifdef VDEC3
1702 #if SUPPORT_G2VP9
1703 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1704 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1705 #else
1706 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1707 #endif
1708 #else
1709 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1710 #endif
1711 {
1712 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1713
1714 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1715 {
1716 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1717 }
1718 else
1719 {
1720 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1721 }
1722
1723 MsOS_FlushMemory();
1724 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1725
1726 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1727 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1728 }
1729 #endif
1730
1731 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1732 {
1733 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1734 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1735
1736 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1737
1738 MsOS_FlushMemory();
1739 }
1740
1741 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1742 {
1743 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1744 //arg=1 to get better performance for single task
1745 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1746 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1747 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1748 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1749 {
1750 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1751 }
1752 }
1753 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1754 {
1755 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1756 {
1757 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1758 {
1759 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1760 u32CmdArg = CTL_MODE_3DTV;
1761 break;
1762 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1763 u32CmdArg = CTL_MODE_3DTV_PROG;
1764 break;
1765 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1766 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1767 break;
1768 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1769 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1770 break;
1771 default:
1772 u32CmdArg = CTL_MODE_3DTV;
1773 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1774 break;
1775 }
1776 }
1777 else
1778 {
1779 u32CmdArg = CTL_MODE_3DWMV;
1780 }
1781 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1782 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1783 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1784 {
1785 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1786 }
1787 }
1788 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1789 {
1790 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1791 {
1792 u32CmdArg = CTL_MODE_ONE_STC;
1793 }
1794 else
1795 {
1796 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1797 }
1798 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1799 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1800 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1801 {
1802 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1803 }
1804 }
1805
1806 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
1807 #if defined(SUPPORT_NEW_MEM_LAYOUT)
1808 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1809 #ifdef VDEC3
1810 {
1811 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1812 }
1813 #else
1814 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1815 #endif
1816
1817 #ifdef VDEC3
1818 #if SUPPORT_G2VP9
1819 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1820 #else
1821 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1822 #endif
1823 {
1824 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
1825 }
1826 #else
1827 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1828 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
1829 #endif
1830 else
1831 {
1832 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1833 _HAL_VPU_Release();
1834 return FALSE;
1835 }
1836 #else
1837 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
1838 #endif
1839
1840 VPRINTF("[%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
1841 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
1842
1843 MsOS_ReadMemory();
1844 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1845 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1846
1847 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1848 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
1849 {
1850 if (HVD_GetSysTime_ms() > u32Timeout)
1851 {
1852 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
1853 MS_U32 t=0;
1854 for (t=0; t<30; t++)
1855 {
1856 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1857 }
1858 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1859 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1860 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
1861 _HAL_VPU_Release();
1862 return FALSE;
1863 //#endif
1864 }
1865
1866 MsOS_ReadMemory();
1867 }
1868
1869 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1870 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1871
1872 #ifdef VDEC3
1873 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1874 #else
1875 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1876 #endif
1877 {
1878 HAL_HVD_EX_SetBufferAddr(u32Id);
1879 }
1880
1881 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1882 {
1883 eDecType = E_VPU_EX_DECODER_MVD;
1884 }
1885 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1886 {
1887 eDecType = E_VPU_EX_DECODER_HVD;
1888 }
1889 #ifdef VDEC3
1890 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1891 {
1892 eDecType = E_VPU_EX_DECODER_EVD;
1893 }
1894 #if SUPPORT_G2VP9
1895 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1896 {
1897 eDecType = E_VPU_EX_DECODER_G2VP9;
1898 }
1899 #endif
1900 #endif
1901 else
1902 {
1903 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1904 _HAL_VPU_Release();
1905 return FALSE;
1906 }
1907
1908 #ifdef VDEC3
1909 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1910 {
1911 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
1912 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
1913 }
1914 #endif
1915
1916 if (pTaskInfo->eDecType != eDecType)
1917 {
1918 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
1919 pTaskInfo->eDecType, eDecType);
1920 }
1921 goto _SAVE_DEC_TYPE;
1922
1923 _SAVE_DEC_TYPE:
1924 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
1925 {
1926 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
1927 }
1928 else
1929 {
1930 VPU_MSG_ERR("Cannot save eDecType!!\n");
1931 }
1932
1933 (pVPUHalContext->u8TaskCnt)++;
1934 _HAL_VPU_Release();
1935 return TRUE;
1936 }
1937
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)1938 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1939 {
1940 HVD_Return eRet;
1941 #ifdef VDEC3
1942 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
1943 #else
1944 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
1945 #endif
1946 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1947 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
1948
1949 _HAL_VPU_Entry();
1950 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
1951
1952 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
1953 if(eRet != E_HVD_RETURN_SUCCESS)
1954 {
1955 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
1956 }
1957
1958 {
1959 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1960 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1961 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1962
1963 MsOS_ReadMemory();
1964
1965 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1966 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1967
1968 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
1969 {
1970 if (HVD_GetSysTime_ms() > u32Timeout)
1971 {
1972 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
1973 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1974 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
1975
1976 if(pVPUHalContext->u8TaskCnt == 1)
1977 {
1978 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
1979 break;
1980 }
1981 else if(pVPUHalContext->u8TaskCnt == 2)
1982 {
1983 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
1984 break;
1985 }
1986 else
1987 {
1988 VPU_MSG_ERR("Task number is not correct\n");
1989 _HAL_VPU_Release();
1990 return FALSE;
1991 }
1992 }
1993
1994 MsOS_ReadMemory();
1995 }
1996
1997 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1998 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1999 }
2000 #if SUPPORT_EVD
2001 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2002 {
2003 HAL_EVD_EX_ClearTSPInput(u32Id);
2004 }
2005 #endif
2006
2007 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2008 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2009 {
2010 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2011 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2012 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2013 }
2014
2015 if (pVPUHalContext->u8TaskCnt)
2016 {
2017 (pVPUHalContext->u8TaskCnt)--;
2018 }
2019 else
2020 {
2021 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2022 }
2023
2024 if (0 == pVPUHalContext->u8TaskCnt)
2025 {
2026 int i;
2027 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2028 _VPU_EX_DeinitAll(pInitPara);
2029 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2030 pVPUHalContext->u32VPUSHMAddr = 0;
2031
2032 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2033 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2034 }
2035 else
2036 {
2037 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2038 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
2039 }
2040
2041 _HAL_VPU_Release();
2042 return TRUE;
2043 }
2044
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2045 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2046 {
2047 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2048 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2049 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2050 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2051 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2052 #endif
2053
2054 if (FALSE == HAL_VPU_EX_GetFWReload())
2055 {
2056 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2057 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2058 {
2059 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2060 }
2061 else
2062 {
2063 //Check f/w prefix "VDEC30"
2064 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2065 {
2066 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2067 }
2068 else
2069 {
2070 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2071 return TRUE;
2072 }
2073 }
2074 }
2075
2076 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2077 {
2078 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2079 if (u32Size != 0)
2080 {
2081 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2082
2083
2084 MS_U32 u32Start;
2085 MS_U32 u32StartOffset;
2086 MS_U8 u8MiuSel;
2087
2088 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2089
2090
2091 if(u8MiuSel == E_CHIP_MIU_0)
2092 cpyflag = E_SPIDMA_DEV_MIU0;
2093 else if(u8MiuSel == E_CHIP_MIU_1)
2094 cpyflag = E_SPIDMA_DEV_MIU1;
2095 else if(u8MiuSel == E_CHIP_MIU_2)
2096 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2097
2098 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2099 {
2100 goto _load_code_fail;
2101 }
2102 }
2103 else
2104 {
2105 goto _load_code_fail;
2106 }
2107 #else
2108 goto _load_code_fail;
2109 #endif
2110 }
2111 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2112 {
2113 if (u32BinAddr != 0 && u32Size != 0)
2114 {
2115 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2116 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2117 {
2118 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2119 {
2120 VPU_MSG_INFO("Decompress ok!!!\n");
2121 }
2122 else
2123 {
2124 VPU_MSG_INFO("Decompress fail!!!\n");
2125 }
2126 }
2127 else
2128 #endif
2129 {
2130 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2131 }
2132 }
2133 else
2134 {
2135 goto _load_code_fail;
2136 }
2137 }
2138 else
2139 {
2140 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2141 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2142 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2143 (MS_U32) sizeof(u8HVD_FW_Binary));
2144
2145 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2146 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2147 {
2148 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2149 {
2150 VPU_MSG_INFO("Decompress ok!!!\n");
2151 }
2152 else
2153 {
2154 VPU_MSG_INFO("Decompress fail!!!\n");
2155 }
2156 }
2157 else
2158 #endif
2159 {
2160 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2161 }
2162 #else
2163 goto _load_code_fail;
2164 #endif
2165 }
2166
2167 MAsm_CPU_Sync();
2168 MsOS_FlushMemory();
2169
2170 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2171 {
2172 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2173 goto _load_code_fail;
2174 }
2175
2176 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2177 return TRUE;
2178
2179 _load_code_fail:
2180 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2181 return FALSE;
2182 }
2183
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2184 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2185 {
2186 u32VPURegOSBase = u32RegBase;
2187 }
2188
HAL_VPU_EX_Init_Share_Mem(void)2189 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2190 {
2191 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2192
2193 MS_U32 u32ShmId;
2194 MS_VIRT u32Addr;
2195 MS_U32 u32BufSize;
2196
2197
2198 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2199 sizeof(VPU_Hal_CTX),
2200 &u32ShmId,
2201 &u32Addr,
2202 &u32BufSize,
2203 MSOS_SHM_QUERY))
2204 {
2205 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2206 sizeof(VPU_Hal_CTX),
2207 &u32ShmId,
2208 &u32Addr,
2209 &u32BufSize,
2210 MSOS_SHM_CREATE))
2211 {
2212 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2213 if(pVPUHalContext == NULL)
2214 {
2215 pVPUHalContext = &gVPUHalContext;
2216 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2217 _VPU_EX_Context_Init();
2218 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2219 }
2220 else
2221 {
2222 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2223 }
2224 //return FALSE;
2225 }
2226 else
2227 {
2228 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2229 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2230 _VPU_EX_Context_Init();
2231 }
2232 }
2233 else
2234 {
2235 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2236 }
2237 #else
2238 if(pVPUHalContext == NULL)
2239 {
2240 pVPUHalContext = &gVPUHalContext;
2241 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2242 _VPU_EX_Context_Init();
2243 }
2244 #endif
2245
2246 return TRUE;
2247
2248 }
2249
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2250 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2251 {
2252 MS_U32 i = 0;
2253
2254 _HAL_VPU_MutexCreate();
2255
2256 _HAL_VPU_Entry();
2257
2258 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2259 {
2260 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2261 {
2262 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2263 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2264 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2265 _HAL_VPU_Release();
2266 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2267 }
2268 }
2269 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2270 {
2271 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2272 {
2273 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2274 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2275 {
2276 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2277 _HAL_VPU_Release();
2278 return pVPUHalContext->_stVPUStream[i].eStreamId;
2279 }
2280 }
2281 }
2282 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2283 {
2284 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2285 {
2286 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2287 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2288 {
2289 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2290 _HAL_VPU_Release();
2291 return pVPUHalContext->_stVPUStream[i].eStreamId;
2292 }
2293 }
2294 }
2295 #ifdef VDEC3
2296 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2297 {
2298 #if 1 // bound FW task to main/sub stream
2299 i = eStreamType - E_HAL_VPU_N_STREAM;
2300 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2301 {
2302 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2303 _HAL_VPU_Release();
2304 return pVPUHalContext->_stVPUStream[i].eStreamId;
2305 }
2306 #else // dynamic select FW task id
2307 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2308 {
2309 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2310 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2311 {
2312 return pVPUHalContext->_stVPUStream[i].eStreamId;
2313 }
2314 }
2315 #endif
2316 }
2317 #endif
2318
2319 _HAL_VPU_Release();
2320
2321 return E_HAL_VPU_STREAM_NONE;
2322 }
2323
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2324 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2325 {
2326 if(u8Idx > 2)
2327 {
2328 return FALSE;
2329 }
2330
2331 _HAL_VPU_Entry();
2332
2333 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2334 {
2335 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2336 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2337 }
2338 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2339 {
2340 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2341 }
2342
2343 _HAL_VPU_Release();
2344
2345 return TRUE;
2346 }
2347
HAL_VPU_EX_CheckFreeStream(void)2348 MS_U8 HAL_VPU_EX_CheckFreeStream(void)
2349 {
2350 MS_U8 u8Idx = 0;
2351
2352 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2353 {
2354 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2355 break;
2356 }
2357
2358 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2359 {
2360 VPU_MSG_ERR("all vpu free streams are occupied \n");
2361 return -1;
2362 }
2363
2364 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2365 return u8Idx;
2366 }
2367
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2368 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2369 {
2370 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2371
2372 // enable module
2373 _VPU_EX_ClockInv(InitParams->bClockInv);
2374 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2375 HAL_VPU_EX_PowerCtrl(TRUE);
2376
2377 #ifdef CONFIG_MSTAR_CLKM
2378 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2379 #endif
2380
2381 #ifdef CONFIG_MSTAR_SRAMPD
2382 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2383 HVD_Delay_ms(1);
2384 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2385 HVD_Delay_ms(1);
2386 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2387 HVD_Delay_ms(1);
2388 #endif
2389 #if 1 //Create VPU's own mutex
2390 //_HAL_VPU_MutexCreate();
2391 #else
2392 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2393 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2394 #endif
2395
2396 return TRUE;
2397 }
2398
HAL_VPU_EX_DeInit(void)2399 MS_BOOL HAL_VPU_EX_DeInit(void)
2400 {
2401 if (0 != _VPU_EX_GetActiveCodecCnt())
2402 {
2403 VPU_MSG_DBG("do nothing since codec is active.\n");
2404 return TRUE;
2405 }
2406
2407 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2408
2409 #ifdef CONFIG_MSTAR_CLKM
2410 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2411 #else
2412 HAL_VPU_EX_PowerCtrl(FALSE);
2413 #endif
2414
2415 #ifdef CONFIG_MSTAR_SRAMPD
2416 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2417 HVD_Delay_ms(1);
2418 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2419 HVD_Delay_ms(1);
2420 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2421 HVD_Delay_ms(1);
2422 #endif
2423
2424 HAL_VPU_EX_SwRelseMAU();
2425 //_HAL_VPU_MutexDelete();
2426
2427 return TRUE;
2428 }
2429
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2430 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2431 {
2432 if (bEnable)
2433 {
2434 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2435 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2436 pVPUHalContext->_bVPUPowered = TRUE;
2437 }
2438 else
2439 {
2440 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2441 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2442 pVPUHalContext->_bVPUPowered = FALSE;
2443 }
2444 }
2445
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2446 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2447 {
2448 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2449 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2450 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2451 VPU_EX_TimerDelayMS(1);
2452 }
2453
2454 ///-----------------------------------------------------------------------------
2455 /// config AVCH264 CPU
2456 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2457 /// @param u8dlend_en \b IN: endian
2458 /// - 1, little endian
2459 /// - 0, big endian
2460 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2461 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2462 {
2463 MS_BOOL bRet = TRUE;
2464 MS_U32 u32Offset = 0;
2465 MS_U16 tempreg = 0;
2466 MS_U8 u8MiuSel;
2467 //MS_U32 u32TmpStartOffset;
2468
2469 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2470
2471 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2472 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2473 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2474 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2475 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2476 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2477 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2478 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2479 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2480 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2481
2482 #if (HVD_ENABLE_IQMEM)
2483 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2484 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2485 #endif
2486
2487 #if (VPU_FORCE_MIU_MODE)
2488 // Data sram base Unit: byte address
2489 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2490 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2491 // Instruction sram base Unit: byte address
2492 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2493 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2494
2495 #ifndef HAL_FEATURE_MAU
2496 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2497 #endif
2498 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2499
2500 //use force miu mode
2501 if(u8MiuSel == E_CHIP_MIU_0)
2502 {
2503 #ifdef HAL_FEATURE_MAU
2504 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2505 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2506 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2507 #else
2508 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2509 #endif
2510 }
2511 else if(u8MiuSel == E_CHIP_MIU_1)
2512 {
2513 #ifdef HAL_FEATURE_MAU
2514 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2515 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2516 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2517 #else
2518 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2519 #endif
2520 }
2521 else //miu 2
2522 {
2523 #ifdef HAL_FEATURE_MAU
2524 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2525 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2526 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2527 #else
2528 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2529 #endif
2530 }
2531 #else
2532 ///TODO:
2533 #endif
2534
2535
2536 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2537 tempreg |= VPU_REG_IO2_EN;
2538 tempreg |= VPU_REG_QMEM_SPACE_EN;
2539 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2540
2541 return bRet;
2542 }
2543
2544 ///-----------------------------------------------------------------------------
2545 /// Set IQMem data access mode or instruction fetch mode
2546 /// @param u8dlend_en \b IN: endian
2547 /// - 1, switch to data access mode
2548 /// - 0, switch to instruction fetch mode
2549 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2550 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2551 {
2552
2553 if(bEnable){
2554
2555 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2556 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);
2557
2558 }
2559 else{
2560
2561 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);
2562
2563 }
2564 }
2565
2566 ///-----------------------------------------------------------------------------
2567 /// H.264 SW reset
2568 /// @return TRUE or FALSE
2569 /// - TRUE, Success
2570 /// - FALSE, Failed
2571 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2572 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2573 {
2574 MS_U16 tempreg = 0, tempreg1 = 0;
2575 MS_U16 idle_cnt;
2576 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2577 tempreg |= VPU_REG_CPU_STALL_EN;
2578 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2579
2580 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2581 // 0xf means VPU is not stalled
2582 if (tempreg & 0xf || pVPUHalContext->u8ForceRst == 1) {
2583 pVPUHalContext->u8ForceRst = 0;
2584 // write R2 RIU registers to select DCU/ICU debug data
2585 // Writing these registers here provides enough time for them to
2586 // take effect.
2587 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2588 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2589 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2590 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2591
2592 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2593 // This step is important because in the next step we want to make
2594 // sure "DCU is not replaying when R2 is stalled".
2595 idle_cnt = 100;
2596 do
2597 {
2598 if (--idle_cnt == 0)
2599 {
2600 printf("VPU_REG_CPU_STALL_EN is not set\n");
2601 break;
2602 }
2603 MsOS_DelayTask(1);
2604 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2605 // check CPU status: DCU should NOT be replaying
2606 // If R2 has been stalled, we can guarantee that if we found DCU is
2607 // NOT replaying, it will NOT replay later even CPU is going to issue
2608 // a load/store instruction.
2609 idle_cnt = 100;
2610 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2611 {
2612 if (--idle_cnt == 0)
2613 {
2614 printf("DCU is replaying\n");
2615 break;
2616 }
2617 MsOS_DelayTask(1);
2618 }
2619 // wait 1ms to prevent race condition between (1) DCU is not
2620 // replaying, and (2) BIU start to doing new job or ICU start to
2621 // fetch new instruction
2622 MsOS_DelayTask(1);
2623
2624 // check BIU should be empty
2625 idle_cnt = 100;
2626 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2627 {
2628 if (--idle_cnt == 0)
2629 {
2630 printf("BIU DCU idle time out~~~~~\n");
2631 break;
2632 }
2633 MsOS_DelayTask(1);
2634 }
2635
2636 // check CPU is not requesting ICU
2637 idle_cnt = 100;
2638 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2639 {
2640 if (--idle_cnt == 0)
2641 {
2642 printf("CPU keeps requesting ICU\n");
2643 break;
2644 }
2645 MsOS_DelayTask(1);
2646 }
2647
2648 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2649 // (2) ISB start to fetch
2650 MsOS_DelayTask(1);
2651
2652 // check ISB should be idle
2653 idle_cnt = 100;
2654 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2655 {
2656 if (--idle_cnt == 0)
2657 {
2658 printf("ISB is busy\n");
2659 break;
2660 }
2661 MsOS_DelayTask(1);
2662 }
2663 }
2664 #ifdef HAL_FEATURE_MAU
2665 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2666 if (bCheckMauIdle)
2667 {
2668 MS_U32 mau_idle_cnt = 100;// ms
2669 while (mau_idle_cnt)
2670 {
2671 if (TRUE == _VPU_EX_MAU_IDLE())
2672 {
2673 break;
2674 }
2675 mau_idle_cnt--;
2676 MsOS_DelayTask(1);
2677 }
2678
2679 if (mau_idle_cnt == 0)
2680 {
2681 printf("MAU idle time out~~~~~\n");
2682 }
2683 }
2684 #endif
2685
2686 // this command set MIU to block R2 (does not ack R2's request)
2687 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2688
2689 #ifdef HAL_FEATURE_MAU
2690 // reset MAU
2691 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2692 tempreg1 |= MAU1_REG_SW_RESET;
2693 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2694 #if defined(UDMA_FPGA_ENVI)
2695 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2696 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2697 #endif
2698 #endif
2699
2700 // reset R2
2701 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2702 // by the same RIU write, the R2 reset signal may reach afifo eralier
2703 // than MIU reset and afifo write pointer will be reset to position 0.
2704 // In this case, afifo consider it is not empty because read/write
2705 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2706 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2707 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2708 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2709 VPU_EX_TimerDelayMS(1);
2710 tempreg &= ~VPU_REG_CPU_R2_EN;
2711 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2712 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2713
2714 VPU_EX_TimerDelayMS(1);
2715
2716 // this command set MIU to accept R2 (can ack R2's request)
2717 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2718
2719 pVPUHalContext->_bVPURsted = FALSE;
2720 return TRUE;
2721 }
2722 /*
2723 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2724 {
2725 MS_U16 tempreg = 0, tempreg1 = 0;
2726 #ifndef HAL_FEATURE_MAU
2727 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2728 tempreg |= VPU_REG_CPU_STALL_EN;
2729 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2730
2731 MS_U32 idle_cnt = 100;// ms
2732 while (idle_cnt)
2733 {
2734 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2735 {
2736 break;
2737 }
2738 idle_cnt--;
2739 MsOS_DelayTask(1);
2740 }
2741
2742 if (idle_cnt == 0)
2743 {
2744 printf("ISB ICU idle time out~~~~~\n");
2745 }
2746
2747 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2748 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2749 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2750 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2751
2752 MS_U32 idle_cnt_1 = 100;// ms
2753 while (idle_cnt_1)
2754 {
2755 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2756 {
2757 break;
2758 }
2759 idle_cnt_1--;
2760 MsOS_DelayTask(1);
2761 }
2762
2763 if (idle_cnt_1 == 0)
2764 {
2765 printf("BIU DCU idle time out~~~~~\n");
2766 }
2767
2768 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2769 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2770 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2771 VPU_EX_TimerDelayMS(1);
2772 tempreg &= ~VPU_REG_CPU_R2_EN;
2773 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2774 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2775
2776 #else
2777 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2778
2779 if (bCheckMauIdle)
2780 {
2781 MS_U32 mau_idle_cnt = 100;// ms
2782 while (mau_idle_cnt)
2783 {
2784 if (TRUE == _VPU_EX_MAU_IDLE())
2785 {
2786 break;
2787 }
2788 mau_idle_cnt--;
2789 MsOS_DelayTask(1);
2790 }
2791
2792 if (mau_idle_cnt == 0)
2793 {
2794 printf("MAU idle time out~~~~~\n");
2795 }
2796 }
2797
2798
2799 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2800
2801 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2802 tempreg1 |= MAU1_REG_SW_RESET;
2803 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2804
2805 #if defined(UDMA_FPGA_ENVI)
2806 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2807 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2808 #endif
2809
2810 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2811 tempreg &= ~VPU_REG_CPU_R2_EN;
2812 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2813 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2814 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2815 #endif
2816 VPU_EX_TimerDelayMS(1);
2817 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2818
2819 pVPUHalContext->_bVPURsted = FALSE;
2820 return TRUE;
2821 }
2822 */
2823 ///-----------------------------------------------------------------------------
2824 /// CPU reset release
2825 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)2826 void HAL_VPU_EX_SwRstRelse(void)
2827 {
2828 MS_U16 tempreg = 0;
2829
2830 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2831 tempreg &= ~VPU_REG_CPU_STALL_EN;
2832 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2833
2834 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2835 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
2836 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2837 VPU_EX_TimerDelayMS(1);
2838 tempreg |= VPU_REG_CPU_SW_RSTZ;
2839 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2840 VPU_EX_TimerDelayMS(1);
2841 tempreg |= VPU_REG_CPU_R2_EN;
2842 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2843 #ifdef HAL_FEATURE_MAU
2844 MS_U16 tempreg1 = 0;
2845 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2846 tempreg1 &= ~MAU1_REG_SW_RESET;
2847 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2848 #endif
2849 pVPUHalContext->_bVPURsted = TRUE;
2850 }
2851
HAL_VPU_EX_SwRelseMAU(void)2852 void HAL_VPU_EX_SwRelseMAU(void)
2853 {
2854
2855 #ifdef HAL_FEATURE_MAU
2856 MS_U16 tempreg = 0;
2857 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
2858 tempreg &= ~MAU1_REG_SW_RESET;
2859 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
2860 #endif
2861 }
2862
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)2863 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
2864 {
2865 MS_U32 u32value = 0;
2866
2867 return u32value;
2868 }
2869
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)2870 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
2871 {
2872 MS_BOOL bRet = TRUE;
2873
2874 return bRet;
2875 }
2876
2877 ///-----------------------------------------------------------------------------
2878 /// Check AVCH264 Ready or not
2879 /// @return TRUE or FALSE
2880 /// - TRUE, MailBox is free
2881 /// - FALSE, MailBox is busy
2882 /// @param u8MBox \b IN: MailBox to check
2883 /// - AVCH264_HI_MBOX0,
2884 /// - AVCH264_HI_MBOX1,
2885 /// - AVCH264_RISC_MBOX0,
2886 /// - AVCH264_RISC_MBOX1,
2887 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)2888 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
2889 {
2890 MS_BOOL bResult = FALSE;
2891
2892 switch (u32type)
2893 {
2894 case VPU_HI_MBOX0:
2895 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
2896 break;
2897 case VPU_HI_MBOX1:
2898 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
2899 break;
2900 case VPU_RISC_MBOX0:
2901 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
2902 break;
2903 case VPU_RISC_MBOX1:
2904 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
2905 break;
2906 default:
2907 break;
2908 }
2909 return bResult;
2910 }
2911
2912
2913 ///-----------------------------------------------------------------------------
2914 /// Read message from AVCH264
2915 /// @return TRUE or FALSE
2916 /// - TRUE, success
2917 /// - FALSE, failed
2918 /// @param u8MBox \b IN: MailBox to read
2919 /// - AVCH264_RISC_MBOX0
2920 /// - AVCH264_RISC_MBOX1
2921 /// @param u32Msg \b OUT: message read
2922 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)2923 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
2924 {
2925 MS_BOOL bResult = TRUE;
2926
2927 switch (u32type)
2928 {
2929 case VPU_HI_MBOX0:
2930 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
2931 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
2932 break;
2933 case VPU_HI_MBOX1:
2934 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
2935 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
2936 break;
2937 case VPU_RISC_MBOX0:
2938 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
2939 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
2940 break;
2941 case VPU_RISC_MBOX1:
2942 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
2943 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
2944 break;
2945 default:
2946 *u32Msg = 0;
2947 bResult = FALSE;
2948 break;
2949 }
2950 return bResult;
2951 }
2952
2953 ///-----------------------------------------------------------------------------
2954 /// Mailbox from AVCH264 clear bit resest
2955 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)2956 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
2957 {
2958 switch (u32type)
2959 {
2960 case VPU_RISC_MBOX0:
2961 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
2962 break;
2963 case VPU_RISC_MBOX1:
2964 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
2965 break;
2966 default:
2967 break;
2968 }
2969 }
2970
2971 ///-----------------------------------------------------------------------------
2972 /// Send message to AVCH264
2973 /// @return TRUE or FALSE
2974 /// - TRUE, Success
2975 /// - FALSE, Failed
2976 /// @param u8MBox \b IN: MailBox
2977 /// - AVCH264_HI_MBOX0,
2978 /// - AVCH264_HI_MBOX1,
2979 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)2980 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
2981 {
2982 MS_BOOL bResult = TRUE;
2983
2984 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
2985
2986 switch (u32type)
2987 {
2988 case VPU_HI_MBOX0:
2989 {
2990 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
2991 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
2992 break;
2993 }
2994 case VPU_HI_MBOX1:
2995 {
2996 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
2997 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
2998 break;
2999 }
3000 default:
3001 {
3002 bResult = FALSE;
3003 break;
3004 }
3005 }
3006
3007 return bResult;
3008 }
3009
HAL_VPU_EX_GetProgCnt(void)3010 MS_U32 HAL_VPU_EX_GetProgCnt(void)
3011 {
3012
3013 MS_U16 expc_l=0;
3014 MS_U16 expc_h=0;
3015 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
3016 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
3017 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3018 }
3019
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3020 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3021 {
3022 return _VPU_EX_GetOffsetIdx(u32Id);
3023 }
3024
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3025 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3026 {
3027 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3028
3029 if (u32ShmAddr == 0)
3030 {
3031 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
3032 }
3033 else
3034 {
3035 if (u8Offset == 0)
3036 {
3037 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
3038 }
3039 else if (u8Offset == 1)
3040 {
3041 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3042 }
3043 }
3044
3045 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3046 return;
3047 }
3048
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3049 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3050 {
3051 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3052
3053 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3054 }
3055
3056
HAL_VPU_EX_IsPowered(void)3057 MS_BOOL HAL_VPU_EX_IsPowered(void)
3058 {
3059 return pVPUHalContext->_bVPUPowered;
3060 }
3061
HAL_VPU_EX_IsRsted(void)3062 MS_BOOL HAL_VPU_EX_IsRsted(void)
3063 {
3064 return pVPUHalContext->_bVPURsted;
3065 }
3066
HAL_VPU_EX_IsEVDR2(void)3067 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3068 {
3069 #ifdef EVDR2
3070 return TRUE;
3071 #else
3072 return FALSE;
3073 #endif
3074 }
3075
HAL_VPU_EX_MVDInUsed(void)3076 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3077 {
3078 //MVD is in used for MVD or HVD_TSP mode.
3079 MS_U8 i;
3080 MS_U8 u8UseCnt = 0;
3081
3082 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3083 {
3084 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3085 #ifdef VDEC3
3086 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3087 #endif
3088 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3089 {
3090 u8UseCnt++;
3091 }
3092 }
3093
3094 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3095
3096 if (u8UseCnt != 0)
3097 {
3098 return TRUE;
3099 }
3100 else
3101 {
3102 return FALSE;
3103 }
3104 }
3105
HAL_VPU_EX_HVDInUsed(void)3106 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3107 {
3108 //HVD is in used for HVD or MVD in sub stream.
3109 MS_U8 i;
3110 MS_U8 u8UseCnt = 0;
3111 MS_BOOL bMVDTriggerHVD = FALSE;
3112 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3113 {
3114 #ifdef VDEC3
3115 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) &&
3116 (pVPUHalContext->u8HALId[i] == 1) &&
3117 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod);
3118 #else
3119 bMVDTriggerHVD = (E_VPU_EX_DECODER_MVD == pVPUHalContext->_stVPUStream[i].eDecodertype) &&
3120 (E_HAL_VPU_SUB_STREAM0 == pVPUHalContext->_stVPUStream[i].eStreamId) &&
3121 (E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod);
3122 #endif
3123
3124 if(bMVDTriggerHVD)
3125 {
3126 VPU_MSG_DBG("%s i:%d eDecodertype:%d u8DecMod:%d\n",__FUNCTION__,i,pVPUHalContext->_stVPUStream[i].eDecodertype,pVPUHalContext->_stVPUDecMode.u8DecMod);
3127 }
3128
3129 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3130 #ifdef VDEC3
3131 ||(E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3132 #endif
3133 ||(TRUE == bMVDTriggerHVD)
3134 )
3135 {
3136 u8UseCnt++;
3137 }
3138 }
3139
3140 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3141
3142 if (u8UseCnt != 0)
3143 {
3144 return TRUE;
3145 }
3146 else
3147 {
3148 return FALSE;
3149 }
3150 }
3151
HAL_VPU_EX_Mutex_Lock(void)3152 void HAL_VPU_EX_Mutex_Lock(void)
3153 {
3154 _HAL_VPU_Entry();
3155 }
3156
HAL_VPU_EX_Mutex_UnLock(void)3157 void HAL_VPU_EX_Mutex_UnLock(void)
3158 {
3159 _HAL_VPU_Release();
3160 }
3161
3162 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3163 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3164 {
3165 MS_U8 i;
3166 MS_U8 u8UseCnt = 0;
3167
3168 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3169 {
3170 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3171 {
3172 u8UseCnt++;
3173 }
3174 }
3175
3176 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3177
3178 if (u8UseCnt != 0)
3179 {
3180 return TRUE;
3181 }
3182 else
3183 {
3184 return FALSE;
3185 }
3186 }
3187
3188 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3189 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3190 {
3191 MS_U8 i;
3192 MS_U8 u8UseCnt = 0;
3193
3194 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3195 {
3196 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3197 {
3198 u8UseCnt++;
3199 }
3200 }
3201
3202 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3203
3204 if (u8UseCnt != 0)
3205 {
3206 return TRUE;
3207 }
3208 else
3209 {
3210 return FALSE;
3211 }
3212 }
3213 #endif
3214 #endif
3215
3216 //-----------------------------------------------------------------------------
3217 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3218 /// @brief \b Function \b Description: Set debug level
3219 /// @param -elevel \b IN : debug level
3220 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3221 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3222 {
3223 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3224
3225 switch (eLevel)
3226 {
3227 case E_VPU_EX_UART_LEVEL_ERR:
3228 {
3229 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3230 break;
3231 }
3232 case E_VPU_EX_UART_LEVEL_INFO:
3233 {
3234 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3235 break;
3236 }
3237 case E_VPU_EX_UART_LEVEL_DBG:
3238 {
3239 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3240 break;
3241 }
3242 case E_VPU_EX_UART_LEVEL_TRACE:
3243 {
3244 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3245 break;
3246 }
3247 case E_VPU_EX_UART_LEVEL_FW:
3248 {
3249 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3250 break;
3251 }
3252 default:
3253 {
3254 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3255 break;
3256 }
3257 }
3258 }
3259
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3260 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3261 {
3262 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3263 MS_U32 u32CmdArg = (MS_U32)eVerType;
3264 MS_U32 u32Version = 0xFFFFFFFF;
3265 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3266 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3267 {
3268 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3269 return u32Version;
3270 }
3271
3272 MS_BOOL bRet = false;
3273 MS_U32 u32TimeOut = 0xFFFFFFFF;
3274
3275 while(--u32TimeOut)
3276 {
3277 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3278 {
3279 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3280 if (false == bRet)
3281 {
3282 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3283 return u32Version;
3284 }
3285
3286 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3287 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3288 return u32Version;
3289 }
3290 }
3291
3292 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3293
3294 return u32Version;
3295 }
3296
HAL_VPU_EX_NotSupportDS(void)3297 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3298 {
3299 return FALSE;
3300 }
3301
3302 //-----------------------------------------------------------------------------
3303 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3304 /// @brief \b Function \b Description: Get VPU MIU base address
3305 /// @return - vpu MIU1 base
3306 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3307 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3308 {
3309 return VPU_MIU1BASE_ADDR;
3310 }
3311
3312
HAL_VPU_EX_GetSHMAddr(void)3313 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3314 {
3315 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3316 {
3317 return 0;
3318 }
3319 return pVPUHalContext->u32VPUSHMAddr;
3320 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3321 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3322 {
3323 pVPUHalContext->bEnableVPUSecureMode = enable;
3324 return TRUE;
3325 }
3326
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3327 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3328 {
3329 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3330
3331 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3332 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3333 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3334 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3335 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3336 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3337 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3338 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3339
3340 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3341 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3342 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3343 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3344 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3345 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3346 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3347 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3348 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3349 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3350
3351 return TRUE;
3352 }
3353
3354 //-----------------------------------------------------------------------------
3355 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3356 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3357 /// @return - success/fail
3358 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3359 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3360 {
3361 #define MAX_CAPABILITY_INFO_NUM 8
3362 #define MAX_CODEC_TYPE_NUM 18
3363
3364 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3365 {
3366 //width, height , frmrate, profile, level, version bit rate reserved2
3367 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3368 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3369 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3370 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3371 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3372 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3373 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3374 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3375 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3376 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3377 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3378 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_4_2, E_VDEC_EX_CODEC_VERSION_NONE, 62, 0},//E_HVD_EX_CODEC_TYPE_H264
3379 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 60, 0},//E_HVD_EX_CODEC_TYPE_AVS
3380 { 1280, 720, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3381 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_4_2, E_VDEC_EX_CODEC_VERSION_NONE, 62, 0},//E_HVD_EX_CODEC_TYPE_MVC
3382 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3383 { 4096, 2160, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3384 { 4096, 2160, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 100, 0},//E_HVD_EX_CODEC_TYPE_VP9
3385 };
3386
3387 if(eCodecType < MAX_CODEC_TYPE_NUM)
3388 {
3389 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3390 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3391 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3392 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3393 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3394 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3395 return TRUE;
3396 }
3397 else
3398 {
3399 return FALSE;
3400 }
3401 }
3402
3403 #ifdef VDEC3
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bIsNstreamMode)3404 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bIsNstreamMode)
3405 {
3406 MS_U32 i, max_bbu_cnt;
3407 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3408
3409 if(pTaskInfo == NULL)
3410 return retBBUId;
3411
3412 BBU_STATE *bbu_state;
3413 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3414 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3415
3416 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3417
3418 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3419
3420 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3421 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3422 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3423
3424 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3425 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3426
3427 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3428 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3429 */
3430 #if 1
3431 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3432 {
3433 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3434 if (bTSP)
3435 {
3436 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3437 {
3438 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3439 slq_state[u8TaskId].bTSP = TRUE;
3440 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3441 return u8TaskId;
3442 }
3443 }
3444 else
3445 {
3446 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3447 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3448 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3449 {
3450 if (slq_state[i].u32Used != 0)
3451 {
3452 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3453 {
3454 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3455 }
3456 }
3457 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3458 {
3459 avaliable_bbu_idx = i; // recored the first empty bbu
3460 }
3461 }
3462
3463 if (bIsNstreamMode && shared_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // In Nstream mode, first priority is sharing bbu
3464 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3465 slq_state[shared_bbu_idx].bTSP = FALSE;
3466 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3467 return shared_bbu_idx;
3468 }
3469 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3470 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3471 slq_state[u8TaskId].bTSP = FALSE;
3472 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3473 return u8TaskId;
3474 }
3475 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // 3rd priority is avaliable bbu id
3476 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3477 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3478 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3479 return avaliable_bbu_idx;
3480 }
3481 else {
3482 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3483 }
3484 }
3485 }
3486 #if SUPPORT_G2VP9
3487 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3488 {
3489 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3490 // Don't care the return value, G2_VP9 will not use it.
3491 return 0;
3492 }
3493 #endif
3494 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3495 {
3496 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3497 // Don't care the return value, VP8 will not use it.
3498 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3499 return u8Offset;
3500 //return 0;
3501 }
3502 else
3503 {
3504 switch (pTaskInfo->eDecType)
3505 {
3506 case E_VPU_EX_DECODER_EVD:
3507 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3508 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3509 break;
3510 case E_VPU_EX_DECODER_HVD:
3511 case E_VPU_EX_DECODER_RVD:
3512 case E_VPU_EX_DECODER_MVC:
3513 default:
3514 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3515 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3516 break;
3517 }
3518
3519 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3520 if (bTSP)
3521 {
3522 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3523 {
3524 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3525 bbu_state[u8TaskId].bTSP = TRUE;
3526 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3527 slq_state[u8TaskId].bTSP = TRUE;
3528 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3529 return u8TaskId;
3530 }
3531 }
3532 else
3533 {
3534 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3535 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3536 for (i = 0; i < max_bbu_cnt; i++)
3537 {
3538 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3539 {
3540 if (bbu_state[i].bTSP == FALSE)
3541 {
3542 shared_bbu_idx = i;
3543 }
3544 }
3545 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3546 {
3547 avaliable_bbu_idx = i;
3548 }
3549 }
3550 if (bIsNstreamMode && shared_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // // In Nstream mode, first priority is sharing bbu
3551 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3552 return shared_bbu_idx;
3553 }
3554 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3555 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3556 return u8TaskId;
3557 }
3558 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID) { // 3rd priority is avaliable bbu id
3559 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3560 return avaliable_bbu_idx;
3561 }
3562 else {
3563 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3564 }
3565 }
3566 }
3567 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3568 MS_U32 j;
3569 MS_BOOL Got = FALSE;
3570 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3571 {
3572 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3573 {
3574 if(slq_state[i].u32Used != 0)
3575 {
3576 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3577 {
3578 retBBUId = i;
3579 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3580 slq_state[retBBUId].bTSP = bTSP;
3581 slq_state[retBBUId].bUsedbyMVD = TRUE;
3582 return retBBUId;
3583 }
3584 }
3585 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3586 {
3587 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3588 {
3589 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3590 {
3591 Got = TRUE;
3592 retBBUId = i;
3593 }
3594 }
3595
3596 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
3597 {
3598 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
3599 {
3600 Got = TRUE;
3601 retBBUId = i;
3602 }
3603 }
3604
3605 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
3606 retBBUId = i;
3607 }
3608 }
3609 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3610 {
3611 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3612 slq_state[retBBUId].bTSP = bTSP;
3613 slq_state[retBBUId].bUsedbyMVD = TRUE;
3614 }
3615 }
3616 #if SUPPORT_G2VP9
3617 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3618 {
3619 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3620 // Don't care the return value, G2_VP9 will not use it.
3621 return 0;
3622 }
3623 #endif
3624 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3625 {
3626 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3627 // Don't care the return value, VP8 will not use it.
3628 return 0;
3629 }
3630 else // HVD/EVD case
3631 {
3632 switch (pTaskInfo->eDecType)
3633 {
3634 case E_VPU_EX_DECODER_EVD:
3635 case E_VPU_EX_DECODER_G2VP9:
3636 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3637 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3638 break;
3639 case E_VPU_EX_DECODER_HVD:
3640 case E_VPU_EX_DECODER_RVD:
3641 case E_VPU_EX_DECODER_MVC:
3642 default:
3643 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3644 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3645 break;
3646 }
3647
3648 for (i = 0; i < max_bbu_cnt; i++)
3649 {
3650 if(bbu_state[i].u32Used != 0)
3651 {
3652 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
3653 {
3654 retBBUId = i;
3655 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3656 bbu_state[retBBUId].bTSP = bTSP;
3657 return retBBUId;
3658 }
3659 }
3660 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
3661 {
3662 if(i < MAX_MVD_SLQ_COUNT)
3663 {
3664 if(!bTSP) //HVD/EVD first MM case
3665 {
3666 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
3667 {
3668 retBBUId = i;
3669 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3670 bbu_state[retBBUId].bTSP = bTSP;
3671 return retBBUId;
3672 }
3673
3674 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
3675 retBBUId = i;
3676 }
3677 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
3678 {
3679 retBBUId = i;
3680 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3681 bbu_state[retBBUId].bTSP = bTSP;
3682 slq_state[retBBUId].bUsedbyMVD = FALSE;
3683 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3684 slq_state[retBBUId].bTSP = bTSP;
3685 return retBBUId;
3686 }
3687 }
3688 }
3689 }
3690 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3691 {
3692 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3693 bbu_state[retBBUId].bTSP = bTSP;
3694 if(bTSP)
3695 {
3696 slq_state[retBBUId].bUsedbyMVD = FALSE;
3697 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3698 slq_state[retBBUId].bTSP = bTSP;
3699 }
3700 }
3701 }
3702 #endif
3703 return retBBUId;
3704 }
3705
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)3706 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
3707 {
3708 MS_U32 max_bbu_cnt;
3709 BBU_STATE *bbu_state;
3710 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3711
3712 if(pTaskInfo == NULL)
3713 return FALSE;
3714 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3715 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3716
3717 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
3718 /* MS_U32 i;
3719 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3720 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3721
3722 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3723 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3724
3725 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3726 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3727 */
3728 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3729 {
3730 // TO DO
3731 if(u32BBUId < MAX_MVD_SLQ_COUNT)
3732 {
3733 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3734 slq_state[u32BBUId].bTSP = FALSE;
3735 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3736 return TRUE;
3737 }
3738 }
3739 #if SUPPORT_G2VP9
3740 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3741 {
3742 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3743 return TRUE;
3744 }
3745 #endif
3746 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3747 {
3748 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3749 return TRUE;
3750 }
3751 else
3752 {
3753 switch (pTaskInfo->eDecType)
3754 {
3755 case E_VPU_EX_DECODER_EVD:
3756 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3757 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3758 break;
3759 case E_VPU_EX_DECODER_HVD:
3760 case E_VPU_EX_DECODER_RVD:
3761 case E_VPU_EX_DECODER_MVC:
3762 default:
3763 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3764 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3765 break;
3766 }
3767
3768 if (u32BBUId < max_bbu_cnt)
3769 {
3770 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
3771 bbu_state[u32BBUId].bTSP = FALSE;
3772 if (bTSP)
3773 {
3774 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3775 slq_state[u32BBUId].bTSP = FALSE;
3776 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3777 }
3778 return TRUE;
3779 }
3780 }
3781 return FALSE;
3782 }
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)3783 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
3784 {
3785 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3786
3787 if (CHECK_NULL_PTR(pstVBBU))
3788 return 0;
3789 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
3790 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
3791 MS_U32 u32Vacancy = 0;
3792
3793 if (u32WrPtr == u32RdPtr)
3794 {
3795 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
3796 }
3797 else if (u32WrPtr > u32RdPtr)
3798 {
3799 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
3800 }
3801 else
3802 {
3803 u32Vacancy = u32RdPtr - u32WrPtr - 1;
3804 }
3805
3806 return u32Vacancy;
3807 }
3808
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)3809 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
3810 {
3811 return MAX_VDEC_VBBU_ENTRY_COUNT;
3812 }
3813
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)3814 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
3815 {
3816 return pVPUHalContext->u32FWCodeAddr;
3817 }
3818
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)3819 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
3820 {
3821 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3822 #if SUPPORT_G2VP9
3823 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3824 #endif
3825
3826 if (CHECK_NULL_PTR(pstVBBU))
3827 return FALSE;
3828 MsOS_ReadMemory();
3829 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
3830
3831 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
3832 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
3833 {
3834 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
3835 }
3836 else
3837 {
3838 #if SUPPORT_G2VP9
3839 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3840 {
3841 if (stEntry->u32Offset == 0)
3842 return 0;
3843 else
3844 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3845 }
3846 else
3847 #endif
3848 {
3849 return stEntry->u32Offset;
3850 }
3851 }
3852 }
3853
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)3854 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
3855 {
3856 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3857 VDEC_VBBU_Entry *stEntry;
3858 #if SUPPORT_G2VP9
3859 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3860 #endif
3861
3862 MsOS_ReadMemory();
3863 if (CHECK_NULL_PTR(pstVBBU))
3864 return 0;
3865 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
3866
3867 if (u32WrPtr == 0)
3868 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
3869 else
3870 u32WrPtr--;
3871
3872 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
3873
3874 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
3875 #if SUPPORT_G2VP9
3876 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3877 {
3878 if (stEntry->u32Offset == 0)
3879 return 0;
3880 else
3881 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3882 }
3883 else
3884 #endif
3885 {
3886 return stEntry->u32Offset + stEntry->u32Length;
3887 }
3888 }
3889
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)3890 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
3891 {
3892 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3893 #if SUPPORT_G2VP9
3894 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
3895 #endif
3896
3897 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
3898 return FALSE;
3899 MsOS_ReadMemory();
3900 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
3901 MS_U32 u32NewWrPtr;
3902
3903 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
3904 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
3905 {
3906 u32NewWrPtr = 0;
3907 }
3908
3909 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
3910
3911 stEntry->u32Offset = stVpuPkt->u32Offset;
3912
3913 #if SUPPORT_G2VP9
3914 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
3915 {
3916 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
3917 }
3918 #endif
3919
3920 stEntry->u32Length = stVpuPkt->u32Length;
3921 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
3922 stEntry->u32ID_H = stVpuPkt->u32ID_H;
3923 stEntry->u32ID_L = stVpuPkt->u32ID_L;
3924
3925 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
3926
3927 pstVBBU->u32WrPtr = u32NewWrPtr;
3928
3929 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
3930
3931 MsOS_FlushMemory();
3932
3933 return TRUE;
3934 }
3935
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)3936 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
3937 {
3938 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
3939
3940 if (CHECK_NULL_PTR(pstVBBU))
3941 return FALSE;
3942 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
3943 }
3944
3945 ///-----------------------------------------------------------------------------
3946 /// specify the command send to Mail box or DRAM
3947 /// @return TRUE or FALSE
3948 /// - TRUE, Mail box
3949 /// - FALSE, Dram
3950 /// @param u32Cmd \b IN: Command is going to be sned
3951 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)3952 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
3953 {
3954 MS_BOOL bResult = TRUE;
3955
3956 switch (u32Cmd)
3957 {
3958 // *********** Runtime action Command
3959 /* case E_HVD_CMD_RELEASE_DISPQ:
3960 case E_HVD_CMD_UPDATE_DISPQ:
3961 case E_HVD_CMD_FLUSH_DEC_Q:
3962 case E_HVD_CMD_FLUSH:
3963 case E_HVD_CMD_PLAY:
3964 case E_HVD_CMD_PAUSE:
3965 case E_HVD_CMD_STOP:
3966 case E_HVD_CMD_STEP_DECODE:
3967 case E_HVD_CMD_SKIP_DEC:
3968 case E_HVD_CMD_DISP_I_DIRECT:*/
3969 // *********** Dual-Stream Create Task Command
3970 case E_DUAL_CMD_TASK0_HVD_BBU:
3971 case E_DUAL_CMD_TASK0_HVD_TSP:
3972 case E_DUAL_CMD_TASK0_MVD_SLQ:
3973 case E_DUAL_CMD_TASK0_MVD_TSP:
3974 case E_DUAL_CMD_TASK1_HVD_BBU:
3975 case E_DUAL_CMD_TASK1_HVD_TSP:
3976 case E_DUAL_CMD_MODE:
3977 #ifndef _WIN32
3978 case E_DUAL_CMD_TASK1_MVD_SLQ:
3979 case E_DUAL_CMD_TASK1_MVD_TSP:
3980 #endif
3981 case E_DUAL_CMD_DEL_TASK:
3982 case E_DUAL_CMD_SINGLE_TASK:
3983 case E_DUAL_VERSION:
3984 case E_DUAL_R2_CMD_EXIT:
3985 #ifdef VDEC3
3986 case E_DUAL_R2_CMD_FBADDR:
3987 case E_DUAL_R2_CMD_FBSIZE:
3988 // *********** N-Streams
3989 case E_NST_CMD_TASK_HVD_TSP:
3990 case E_NST_CMD_TASK_HVD_BBU:
3991 case E_NST_CMD_TASK_MVD_TSP:
3992 case E_NST_CMD_TASK_MVD_SLQ:
3993 case E_NST_CMD_DEL_TASK:
3994 case E_NST_CMD_COMMON_MASK:
3995 case E_NST_CMD_COMMON_CMD1:
3996 #endif
3997 case E_DUAL_CMD_COMMON:
3998 {
3999 bResult = TRUE;
4000 }
4001 break;
4002 default:
4003 {
4004 bResult = FALSE;
4005 }
4006 break;
4007 }
4008
4009 return bResult;
4010 }
4011
4012 ///-----------------------------------------------------------------------------
4013 /// specify the command send to Mail box or DRAM
4014 /// @return TRUE or FALSE
4015 /// - TRUE, Mail box
4016 /// - FALSE, Dram
4017 /// @param u32Cmd \b IN: Command is going to be sned
4018 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4019 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4020 {
4021 MS_BOOL bResult = TRUE;
4022
4023 switch (u32Cmd)
4024 {
4025 // *********** Runtime action Command
4026 case E_HVD_CMD_RELEASE_DISPQ:
4027 case E_HVD_CMD_UPDATE_DISPQ:
4028 case E_HVD_CMD_FLUSH_DEC_Q:
4029 case E_HVD_CMD_PAUSE:
4030 case E_HVD_CMD_FLUSH:
4031 case E_HVD_CMD_PLAY:
4032 case E_HVD_CMD_STOP:
4033 case E_HVD_CMD_SKIP_DEC:
4034 case E_HVD_CMD_DISP_I_DIRECT:
4035 case E_HVD_CMD_STEP_DECODE:
4036 case E_HVD_CMD_INC_DISPQ_NUM:
4037 {
4038 bResult = TRUE;
4039 }
4040 break;
4041 default:
4042 {
4043 bResult = FALSE;
4044 }
4045 break;
4046 }
4047
4048 return bResult;
4049 }
4050
4051 ///-----------------------------------------------------------------------------
4052 /// Send message to HVD stream command queue
4053 /// @return TRUE or FALSE
4054 /// - TRUE, Success
4055 /// - FALSE, Failed
4056 /// @param u32DramAddr \b IN: address to be writen
4057 /// @param u32Msg \b IN: data to be writen
4058 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4059 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4060 {
4061 MS_BOOL bResult = TRUE;
4062
4063 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4064
4065 WRITE_LONG(u32DramAddr,u32Msg);
4066
4067 return bResult;
4068 }
4069
4070 ///-----------------------------------------------------------------------------
4071 /// Read task share memory to specify that task command queue is empty or not
4072 /// @return TRUE or FALSE
4073 /// - TRUE, Empty
4074 /// - FALSE, Non empty
4075 /// @param u32Id \b IN: Task information
4076 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4077 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4078 {
4079 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4080 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4081 if (!cmd_q)
4082 {
4083 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4084 return FALSE;
4085 }
4086
4087 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4088 }
4089
4090 ///-----------------------------------------------------------------------------
4091 /// Read task share memory to specify that task command queue is full or not
4092 /// @return TRUE or FALSE
4093 /// - TRUE, Full
4094 /// - FALSE, Non full
4095 /// @param u32Id \b IN: Task information
4096 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4097 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4098 {
4099 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4100 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4101 if (!cmd_q)
4102 {
4103 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4104 return TRUE;
4105 }
4106 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4107
4108 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4109 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4110
4111 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4112 }
4113
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4114 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4115 {
4116 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4117 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4118 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4119
4120 #if HVD_ENABLE_MVC
4121 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4122 {
4123 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4124 }
4125 #endif
4126
4127 if (CHECK_NULL_PTR(cmd_q))
4128 {
4129 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4130 return bResult;
4131 }
4132 MS_VIRT u32CmdQWdPtr;
4133
4134 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4135 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4136
4137 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4138 return E_HVD_COMMAND_QUEUE_FULL;
4139 else
4140 {
4141 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4142 }
4143
4144 switch (u8CmdType)
4145 {
4146 case E_HVD_CMDQ_CMD:
4147 {
4148 u32Msg |= (u8TaskID << 24);
4149 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4150
4151 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4152
4153 if (bResult)
4154 {
4155 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4156
4157 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4158 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4159
4160 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4161 }
4162 break;
4163 }
4164 case E_HVD_CMDQ_ARG:
4165 {
4166 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4167 if (bResult)
4168 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4169 break;
4170 }
4171 default:
4172 {
4173 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4174 break;
4175 }
4176 }
4177
4178 MsOS_FlushMemory();
4179
4180 return bResult;
4181 }
4182
4183 ///-----------------------------------------------------------------------------
4184 /// Read task share memory to specify that task display command queue is empty or not
4185 /// @return TRUE or FALSE
4186 /// - TRUE, Empty
4187 /// - FALSE, Non empty
4188 /// @param u32Id \b IN: Task information
4189 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4190 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4191 {
4192 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4193 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4194 if (!cmd_q)
4195 {
4196 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4197 return FALSE;
4198 }
4199
4200 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4201 }
4202
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4203 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4204 {
4205 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4206 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4207 if (!cmd_q)
4208 {
4209 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4210 return TRUE;
4211 }
4212
4213 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4214
4215 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4216 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4217
4218 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4219 }
4220
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4221 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4222 {
4223 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4224 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4225 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4226
4227 #if HVD_ENABLE_MVC
4228 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4229 {
4230 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4231 }
4232 #endif
4233
4234 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4235 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4236
4237 if (CHECK_NULL_PTR(cmd_q))
4238 {
4239 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4240 return bResult;
4241 }
4242
4243 MS_VIRT u32DISPCMDQWdPtr;
4244
4245 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4246 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4247
4248 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4249 return E_HVD_COMMAND_QUEUE_FULL;
4250 else
4251 {
4252 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4253 }
4254
4255 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4256
4257 switch (u8CmdType)
4258 {
4259 case E_HVD_CMDQ_CMD:
4260 {
4261 u32Msg |= (u8TaskID << 24);
4262 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4263
4264 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4265
4266 if (bResult)
4267 {
4268 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4269
4270 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4271 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4272
4273 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4274 }
4275 break;
4276 }
4277 case E_HVD_CMDQ_ARG:
4278 {
4279 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4280 if (bResult)
4281 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4282 break;
4283 }
4284 default:
4285 {
4286 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4287 break;
4288 }
4289 }
4290
4291 MsOS_FlushMemory();
4292
4293 return bResult;
4294 }
4295
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4296 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4297 {
4298 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4299 MS_U32 u32StAddr;
4300 MS_U8 u8TmpMiuSel;
4301
4302 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4303
4304 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4305
4306 return TRUE;
4307 }
4308 #endif
4309
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4310 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4311 {
4312 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4313
4314 if(u32address >= HAL_MIU1_BASE)
4315 {
4316 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4317 }
4318 else
4319 {
4320 pVPUHalContext->u32DynamicFBAddress = u32address;
4321 }
4322
4323 pVPUHalContext->u32DynamicFBSize = u32Size;
4324 }
4325
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType,MS_U8 u8CMAHeapIdx)4326 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType, MS_U8 u8CMAHeapIdx)
4327 {
4328 MS_SIZE FrameBufferSize = 0;
4329
4330 switch(eCodecType)
4331 {
4332 case E_VPU_EX_CODEC_TYPE_MPEG2:
4333 case E_VPU_EX_CODEC_TYPE_H263:
4334 case E_VPU_EX_CODEC_TYPE_MPEG4:
4335 case E_VPU_EX_CODEC_TYPE_DIVX311:
4336 case E_VPU_EX_CODEC_TYPE_DIVX412:
4337 case E_VPU_EX_CODEC_TYPE_FLV:
4338 FrameBufferSize = 0x1E00000;
4339 break;
4340 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4341 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4342 FrameBufferSize = 0x6C00000;
4343 break;
4344 case E_VPU_EX_CODEC_TYPE_RV8:
4345 case E_VPU_EX_CODEC_TYPE_RV9:
4346 FrameBufferSize = 0x1B00000;
4347 break;
4348 case E_VPU_EX_CODEC_TYPE_VP8:
4349 FrameBufferSize = 0x1500000;
4350 break;
4351 case E_VPU_EX_CODEC_TYPE_H264:
4352 FrameBufferSize = 0x8200000;
4353 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4354 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4355 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4356 break;
4357 case E_VPU_EX_CODEC_TYPE_AVS:
4358 FrameBufferSize = 0x1B00000;
4359 break;
4360 case E_VPU_EX_CODEC_TYPE_MJPEG:
4361 FrameBufferSize = 0x2800000;
4362 break;
4363 case E_VPU_EX_CODEC_TYPE_MVC:
4364 FrameBufferSize = 0x4200000;
4365 break;
4366 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
4367 FrameBufferSize = 0xB000000;
4368 break;
4369 case E_VPU_EX_CODEC_TYPE_HEVC:
4370 #if SUPPORT_MSVP9
4371 case E_VPU_EX_CODEC_TYPE_VP9:
4372 #endif
4373 //FrameBufferSize = 0xA000000;
4374 FrameBufferSize = (u8CMAHeapIdx == 0)?0xA000000:0x3000000;
4375 break;
4376 #if !SUPPORT_MSVP9
4377 case E_VPU_EX_CODEC_TYPE_VP9:
4378 FrameBufferSize = 0x7800000;
4379 break;
4380 #endif
4381 default:
4382 FrameBufferSize = 0;
4383 break;
4384 }
4385
4386 return FrameBufferSize;
4387 }
4388
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType,MS_U8 u8CMAHeapIdx)4389 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType, MS_U8 u8CMAHeapIdx)
4390 {
4391 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType, u8CMAHeapIdx);
4392 }
4393
4394 #ifdef CMA_DRV_DIRECT_INIT
4395 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize,MS_U8 u8CMAHeapIdx)4396 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
4397 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize, MS_U8 u8CMAHeapIdx)
4398 {
4399 MS_SIZE FrameBufferSize = 0;
4400
4401 if (!offset || !length)
4402 return FALSE;
4403
4404 total_length -= unUseSize;
4405 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
4406 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
4407
4408 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType, u8CMAHeapIdx);
4409
4410 if(FrameBufferSize == 0)
4411 {
4412 return FALSE;
4413 }
4414 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu\n", __FUNCTION__, __LINE__,
4415 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
4416 if (total_length < FrameBufferSize)
4417 {
4418 *offset = unUseSize;
4419 *length = total_length;
4420 }
4421 else // todo, dual decode case
4422 {
4423 *offset = unUseSize;
4424 *length = FrameBufferSize;
4425 }
4426 return TRUE;
4427 }
4428 #endif
4429
4430 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4431 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4432 {
4433 MS_S32 handle;
4434 switch(eClkPortType)
4435 {
4436 case E_VPU_EX_CLKPORT_MVD:
4437 {
4438 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4439 if(bEnable)
4440 {
4441 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4442 }
4443 else
4444 {
4445 Drv_Clkm_Clk_Gate_Disable(handle);
4446 }
4447 break;
4448 }
4449 case E_VPU_EX_CLKPORT_MVD_CORE:
4450 {
4451 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4452 if(bEnable)
4453 {
4454 Drv_Clkm_Set_Clk_Source(handle, "");
4455 }
4456 else
4457 {
4458 Drv_Clkm_Clk_Gate_Disable(handle);
4459 }
4460 break;
4461 }
4462 case E_VPU_EX_CLKPORT_MVD_PAS:
4463 {
4464 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4465 if(bEnable)
4466 {
4467 Drv_Clkm_Set_Clk_Source(handle, "");
4468 }
4469 else
4470 {
4471 Drv_Clkm_Clk_Gate_Disable(handle);
4472 }
4473 break;
4474 }
4475 case E_VPU_EX_CLKPORT_HVD:
4476 {
4477 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4478 if(bEnable)
4479 {
4480 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4481 }
4482 else
4483 {
4484 Drv_Clkm_Clk_Gate_Disable(handle);
4485 }
4486 break;
4487 }
4488 case E_VPU_EX_CLKPORT_HVD_IDB:
4489 {
4490 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4491 if(bEnable)
4492 {
4493 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4494 }
4495 else
4496 {
4497 Drv_Clkm_Clk_Gate_Disable(handle);
4498 }
4499 break;
4500 }
4501 case E_VPU_EX_CLKPORT_HVD_AEC:
4502 {
4503 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4504 if(bEnable)
4505 {
4506 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4507 }
4508 else
4509 {
4510 Drv_Clkm_Clk_Gate_Disable(handle);
4511 }
4512 break;
4513 }
4514 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4515 {
4516 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4517 if(bEnable)
4518 {
4519 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4520 }
4521 else
4522 {
4523 Drv_Clkm_Clk_Gate_Disable(handle);
4524 }
4525 break;
4526 }
4527 case E_VPU_EX_CLKPORT_VP8:
4528 {
4529 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4530 if(bEnable)
4531 {
4532 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4533 }
4534 else
4535 {
4536 Drv_Clkm_Clk_Gate_Disable(handle);
4537 }
4538 break;
4539 }
4540 case E_VPU_EX_CLKPORT_EVD:
4541 {
4542 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4543 if(bEnable)
4544 {
4545 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4546 }
4547 else
4548 {
4549 Drv_Clkm_Clk_Gate_Disable(handle);
4550 }
4551 break;
4552 }
4553 case E_VPU_EX_CLKPORT_EVD_PPU:
4554 {
4555 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4556 if(bEnable)
4557 {
4558 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4559 }
4560 else
4561 {
4562 Drv_Clkm_Clk_Gate_Disable(handle);
4563 }
4564 break;
4565 }
4566 case E_VPU_EX_CLKPORT_EVD_LITE:
4567 {
4568 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
4569 if(bEnable)
4570 {
4571 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4572 }
4573 else
4574 {
4575 Drv_Clkm_Clk_Gate_Disable(handle);
4576 }
4577 break;
4578 }
4579 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
4580 {
4581 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
4582 if(bEnable)
4583 {
4584 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4585 }
4586 else
4587 {
4588 Drv_Clkm_Clk_Gate_Disable(handle);
4589 }
4590 break;
4591 }
4592 case E_VPU_EX_CLKPORT_VD_MHEG5:
4593 {
4594 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
4595 if(bEnable)
4596 {
4597 Drv_Clkm_Set_Clk_Source(handle, "");
4598 }
4599 else
4600 {
4601 Drv_Clkm_Clk_Gate_Disable(handle);
4602 }
4603 break;
4604 }
4605 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
4606 {
4607 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
4608 if(bEnable)
4609 {
4610 Drv_Clkm_Set_Clk_Source(handle, "");
4611 }
4612 else
4613 {
4614 Drv_Clkm_Clk_Gate_Disable(handle);
4615 }
4616 break;
4617 }
4618 }
4619 }
4620 #endif //#ifdef CONFIG_MSTAR_CLKM
4621
4622 #else
4623 #include "halVPU_EX.h"
4624 #include "drvMMIO.h"
4625 #include "../hvd_v3/regHVD_EX.h"
4626 #include "halCHIP.h"
4627
4628 #if defined(MSOS_TYPE_NUTTX)
4629 extern int lib_lowprintf(const char *fmt, ...);
4630 #define PRINTF lib_lowprintf
4631 #elif defined(MSOS_TYPE_OPTEE)
4632 #define PRINTF printf
4633 #endif
4634
4635 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
4636 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
4637
4638 MS_U8 u8FW_Binary[] = {
4639 #include "fwVPU.dat"
4640 };
4641
4642 MS_U32 u32HVDRegOSBase;
4643
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)4644 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
4645 {
4646 //PRINTF("do load code,u32DestAddr %x\n",addr);
4647 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
4648 MAsm_CPU_Sync();
4649 MsOS_FlushMemory();
4650
4651 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
4652 {
4653 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
4654 return FALSE;
4655 }
4656 return TRUE;
4657 }
4658
HAL_VPU_EX_SetLockDownRegister(void * param)4659 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
4660 {
4661 #if 1
4662 MS_PHY u32StAddr_main;
4663 MS_PHY u32StAddr_sub;
4664 MS_U32 u32NonPMBankSize = 0;
4665 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
4666
4667 if(param == NULL)
4668 {
4669 return FALSE;
4670 }
4671
4672 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
4673
4674 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
4675
4676 // ES buffer
4677 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
4678 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
4679
4680
4681 MS_PHY u32StartOffset;
4682 MS_U8 u8MiuSel;
4683
4684 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
4685 u32StAddr_main = u32StartOffset;
4686
4687 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
4688 u32StAddr_sub = u32StartOffset;
4689
4690 //Lock down register
4691 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
4692 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
4693
4694 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(REG_HVD_BASE), HVD_LWORD(u32StAddr_sub >> 3));
4695 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(REG_HVD_BASE), HVD_HWORD(u32StAddr_sub >> 3));
4696 //~
4697
4698 // Lock Down
4699 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
4700 //~
4701 #endif
4702 return TRUE;
4703 }
4704 #endif
4705