1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (1920*1088*61000ULL) // FHD@60p
134 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #if 0
138 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
139 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
140 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
141 static MS_U16 _u16DispQPtr = 0;
142 #endif
143
144 #define IS_TASK_ALIVE(id) ((id) != -1)
145 #ifndef UNUSED
146 #define UNUSED(x) (void)(x)
147 #endif
148
149
150 //---------------------------------- Mutex settings -----------------------------------------
151 #if HAL_HVD_ENABLE_MUTEX_PROTECT
152 #define _HAL_HVD_MutexCreate() \
153 do \
154 { \
155 if (s32HVDMutexID < 0) \
156 { \
157 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
158 } \
159 } while (0)
160
161 #define _HAL_HVD_MutexDelete() \
162 do \
163 { \
164 if (s32HVDMutexID >= 0) \
165 { \
166 OSAL_HVD_MutexDelete(s32HVDMutexID); \
167 s32HVDMutexID = -1; \
168 } \
169 } while (0)
170
171 #define _HAL_HVD_Entry() \
172 do \
173 { \
174 if (s32HVDMutexID >= 0) \
175 { \
176 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
177 { \
178 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
179 } \
180 } \
181 } while (0)
182
183 #define _HAL_HVD_Return(_ret_) \
184 do \
185 { \
186 if (s32HVDMutexID >= 0) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 return _ret_; \
191 } while(0)
192
193 #define _HAL_HVD_Release() \
194 do \
195 { \
196 if (s32HVDMutexID >= 0) \
197 { \
198 OSAL_HVD_MutexRelease(s32HVDMutexID); \
199 } \
200 } while (0)
201 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define _HAL_HVD_MutexCreate()
204 #define _HAL_HVD_MutexDelete()
205 #define _HAL_HVD_Entry()
206 #define _HAL_HVD_Return(_ret) {return _ret;}
207 #define _HAL_HVD_Release()
208
209 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
210
211 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
212 #define IS_TASK_ALIVE(id) ((id) != -1)
213 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
214
215 //------------------------------ MIU SETTINGS ----------------------------------
216 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
217 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
218 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
219 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
220
221 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
222 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
223 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
224 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
225
226 #define HVD_MVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0)
227 #define HVD_MVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0)
228 #define HVD_HVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(2)) == 0)
229 #define HVD_HVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(1)) == 0)
230
231 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4))
232 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
233 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(2)) == BIT(2))
234 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(1)) == BIT(1))
235
236 #if SUPPORT_EVD
237 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
238 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
239 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
240 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
241
242 #define HVD_EVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0)
243 #define HVD_EVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0)
244 #define HVD_EVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0))
245 #define HVD_EVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0))
246 #endif
247
248 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
249 do \
250 { \
251 if (HVD_##miu_clients##_ON_MIU0 == 1) \
252 { \
253 _MaskMiuReq_##miu_clients(mask); \
254 } \
255 else \
256 { \
257 _MaskMiu1Req_##miu_clients(mask); \
258 } \
259 } while (0)
260
261
262 // check RM is supported or not
263 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
264 #ifdef VDEC3
265 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
266 #else
267 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
268 #endif
269
270 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
271
272 //-------------------------------------------------------------------------------------------------
273 // Local Structures
274 //-------------------------------------------------------------------------------------------------
275
276 //-------------------------------------------------------------------------------------------------
277 // Local Functions Prototype
278 //-------------------------------------------------------------------------------------------------
279 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
280 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
281 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
282 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
283 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
284 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
285 static MS_U32 _HVD_EX_GetPC(void);
286 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
287 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
288 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
289 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
290 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
291 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
292 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
293 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
294 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
295 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
296 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
297 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
298 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
299 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
300 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
301 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
302 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
303 #if SUPPORT_EVD
304 static void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable);
305 static MS_BOOL HAL_EVD_EX_DeinitHW(void);
306 #endif
307 #if SUPPORT_G2VP9 && defined(VDEC3)
308 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
309 #endif
310 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
311 #if SUPPORT_G2VP9 && defined(VDEC3)
312 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
313 #endif
314 //-------------------------------------------------------------------------------------------------
315 // Global Variables
316 //-------------------------------------------------------------------------------------------------
317 #if defined (__aeon__)
318 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
319 #else
320 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
321 #endif
322 #if HAL_HVD_ENABLE_MUTEX_PROTECT
323 MS_S32 s32HVDMutexID = -1;
324 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
325 #endif
326
327
328 #define HVD_EX_STACK_SIZE 4096
329 //-------------------------------------------------------------------------------------------------
330 // Local Variables
331 //-------------------------------------------------------------------------------------------------
332 typedef struct
333 {
334
335 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
336 MS_U8 g_hvd_nal_fill_pair[2][8];
337 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
338 MS_U16 _u16DispQPtr;
339 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
340
341 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
342 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
343 MS_U32 u32VPUClockType;
344 MS_U32 u32HVDClockType;//160
345 #if SUPPORT_EVD
346 MS_U32 u32EVDClockType;
347 #endif
348 #if SUPPORT_G2VP9 && defined(VDEC3)
349 MS_U32 u32VP9ClockType;
350 #endif
351 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
352
353 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
354 MS_BOOL g_RstFlag;
355 MS_U64 u64pts_real;
356 MS_PHY u32VP8BBUWptr;
357 MS_PHY u32EVDBBUWptr;
358 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
359 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
360 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
361 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
362 //pre_set
363 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
364 } HVD_Hal_CTX;
365
366 HVD_Hal_CTX* pHVDHalContext = NULL;
367 HVD_Hal_CTX gHVDHalContext;
368 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
369
370 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
371 {
372 {FALSE},
373 {FALSE},
374 {FALSE},
375 #ifdef VDEC3
376 {FALSE},
377 #endif
378 };
379
380 //-------------------------------------------------------------------------------------------------
381 // Debug Functions
382 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)383 void HVD_EX_SetRstFlag(MS_BOOL bRst)
384 {
385 pHVDHalContext->g_RstFlag = bRst;
386 }
HVD_EX_GetRstFlag(void)387 MS_BOOL HVD_EX_GetRstFlag(void)
388 {
389 return pHVDHalContext->g_RstFlag;
390 }
391
392 //-------------------------------------------------------------------------------------------------
393 // Local Functions
394 //-------------------------------------------------------------------------------------------------
395
396 #ifdef VDEC3
397 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
398 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)399 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
400 {
401
402 MS_U32 ret = TRUE;
403 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
404
405 if(pCtrl == NULL || pstTaskInfo == NULL)
406 return FALSE;
407
408 pstTaskInfo->u32Id = u32Id;
409
410 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
411 {
412 case E_HVD_INIT_HW_RM:
413 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
414 break;
415 case E_HVD_INIT_HW_VP8:
416 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
417 break;
418 case E_HVD_INIT_HW_MVC:
419 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
420 break;
421 case E_HVD_INIT_HW_HEVC:
422 case E_HVD_INIT_HW_HEVC_DV:
423 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
424 break;
425 #if SUPPORT_MSVP9
426 case E_HVD_INIT_HW_VP9:
427 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
428 break;
429 #endif
430 #if SUPPORT_G2VP9
431 case E_HVD_INIT_HW_VP9:
432 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
433 break;
434 #endif
435 default:
436 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
437 break;
438 }
439
440 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
441
442 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
443 {
444 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
445 }
446 else
447 {
448 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
449 }
450
451 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
452
453 #ifdef SUPPORT_EVD
454 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
455 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
456 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
457 #endif
458 return ret;
459
460 }
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)461 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
462 {
463 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
464 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
465 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
466 _HAL_HVD_Entry();
467
468 if(pCtrl == NULL)
469 _HAL_HVD_Return(ret);
470
471 VPU_EX_TaskInfo taskInfo;
472 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
473
474 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
475
476 taskInfo.u8HalId = u8Idx;
477 ret = HAL_VPU_EX_GetBBUId(u32Id,&taskInfo, pCtrl->bNStreamMode);
478
479 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
480 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
481
482 _HAL_HVD_Return(ret);
483 }
484
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)485 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
486 {
487 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
488 MS_BOOL ret = FALSE;
489 _HAL_HVD_Entry();
490
491 if(pCtrl == NULL)
492 _HAL_HVD_Return(ret);
493 VPU_EX_TaskInfo taskInfo;
494 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
495
496 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
497
498 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
499
500 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
501 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
502
503 _HAL_HVD_Return(ret);
504 }
505 #endif
506
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)507 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
508 {
509 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
510 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
511 pstHVDStream->s32HvdPpTaskId = -1;
512 }
513
_HVD_EX_Context_Init_HAL(void)514 static void _HVD_EX_Context_Init_HAL(void)
515 {
516 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
517 pHVDHalContext->u32VPUClockType = 384;
518 pHVDHalContext->u32HVDClockType = 240;
519 #if SUPPORT_EVD
520 pHVDHalContext->u32EVDClockType = 576;
521 #endif
522 #if SUPPORT_G2VP9 && defined(VDEC3)
523 pHVDHalContext->u32VP9ClockType = 384;
524 #endif
525 #ifdef VDEC3
526 MS_U8 i;
527
528 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
529 {
530 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
531 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
532 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
533 }
534 #else
535 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
536 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
537 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
538 #endif
539 }
540
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)541 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
542 {
543 MS_U16 u16Ret = 0;
544 #if (HVD_ENABLE_MVC || (!VDEC3))
545 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
546 #endif
547 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
548 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
549 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
550 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
551
552 #if HVD_ENABLE_MVC
553 if(HAL_HVD_EX_CheckMVCID(u32Id))
554 {
555 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
556 }
557 #endif /// HVD_ENABLE_MVC
558
559 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
560 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
561
562 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
563 {
564 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
565 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
566 }
567 else
568 #ifdef VDEC3
569 if (0 == pCtrl->u32BBUId)
570 #else
571 if (0 == u8TaskId)
572 #endif
573 {
574 //if(pCtrl->InitParams.bColocateBBUMode)
575 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
576 u16Ret = pShm->u32ColocateBBUReadPtr;
577 else
578 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
579 }
580 else
581 {
582 //if(pCtrl->InitParams.bColocateBBUMode)
583 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
584 u16Ret = pShm->u32ColocateBBUReadPtr;
585 else
586 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
587 }
588
589 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
590 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
591
592 return u16Ret;
593 }
594
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)595 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
596 {
597 MS_U16 u16Ret = 0;
598 #if (HVD_ENABLE_MVC || (!VDEC3))
599 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
600 #endif
601 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
602 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
603 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
604 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
605
606 #if HVD_ENABLE_MVC
607 if (HAL_HVD_EX_CheckMVCID(u32Id))
608 {
609 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
610 }
611 #endif /// HVD_ENABLE_MVC
612 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
613 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
614
615 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
616 {
617 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
618 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
619 }
620 else
621 #ifdef VDEC3
622 if (0 == pDrvCtrl->u32BBUId)
623 #else
624 if (0 == u8TaskId)
625 #endif
626 {
627 //if(pDrvCtrl->InitParams.bColocateBBUMode)
628 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
629 u16Ret = pShm->u32ColocateBBUWritePtr;
630 else
631 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
632 }
633 else
634 {
635 //if(pDrvCtrl->InitParams.bColocateBBUMode)
636 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
637 u16Ret = pShm->u32ColocateBBUWritePtr;
638 else
639 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
640 }
641
642 return u16Ret;
643 }
644
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)645 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
646 {
647 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
648 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
649
650 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
651 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
652 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
653 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
654 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
655 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
656 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
657 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
658 }
659
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)660 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
661 {
662 #if (HVD_ENABLE_MVC || (!VDEC3))
663 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
664 #endif
665 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
666 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
667 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
668 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
669
670 #if HVD_ENABLE_MVC
671 if (HAL_HVD_EX_CheckMVCID(u32Id))
672 {
673 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
674 }
675 #endif /// HVD_ENABLE_MVC
676
677 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
678 {
679 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
680 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
681 }
682 else
683 #ifdef VDEC3
684 if (0 == pCtrl->u32BBUId)
685 #else
686 if (0 == u8TaskId)
687 #endif
688 {
689 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
690 //if(pCtrl->InitParams.bColocateBBUMode)
691 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
692 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
693 }
694 else
695 {
696 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
697 //if(pCtrl->InitParams.bColocateBBUMode)
698 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
699 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
700 }
701
702 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
703 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
704
705 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
706 }
707
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)708 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
709 {
710 MS_BOOL bResult = TRUE;
711 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
712 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
713
714 switch (u8MBox)
715 {
716 case E_HVD_HI_0:
717 {
718 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
719 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
720 break;
721 }
722 case E_HVD_HI_1:
723 {
724 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
725 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
726 break;
727 }
728 case E_HVD_VPU_HI_0:
729 {
730 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
731 break;
732 }
733 case E_HVD_VPU_HI_1:
734 {
735 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
736 break;
737 }
738 default:
739 {
740 bResult = FALSE;
741 break;
742 }
743 }
744
745 return bResult;
746 }
747
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)748 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
749 {
750 MS_BOOL bResult = TRUE;
751 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
752 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
753
754 switch (u8MBox)
755 {
756 case E_HVD_HI_0:
757 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
758 break;
759 case E_HVD_HI_1:
760 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
761 break;
762 case E_HVD_RISC_0:
763 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
764 break;
765 case E_HVD_RISC_1:
766 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
767 break;
768 case E_HVD_VPU_HI_0:
769 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
770 break;
771 case E_HVD_VPU_HI_1:
772 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
773 break;
774 case E_HVD_VPU_RISC_0:
775 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
776 break;
777 case E_HVD_VPU_RISC_1:
778 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
779 break;
780 default:
781 break;
782 }
783
784 return bResult;
785 }
786
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)787 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
788 {
789 MS_BOOL bResult = TRUE;
790 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
791 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
792
793 switch (u8MBox)
794 {
795 case E_HVD_HI_0:
796 {
797 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
798 break;
799 }
800 case E_HVD_HI_1:
801 {
802 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
803 break;
804 }
805 case E_HVD_RISC_0:
806 {
807 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
808 break;
809 }
810 case E_HVD_RISC_1:
811 {
812 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
813 break;
814 }
815 case E_HVD_VPU_RISC_0:
816 {
817 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
818 break;
819 }
820 case E_HVD_VPU_RISC_1:
821 {
822 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
823 break;
824 }
825 default:
826 {
827 bResult = FALSE;
828 break;
829 }
830 }
831
832 return bResult;
833 }
834
835 #if 0
836 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
837 {
838 switch (u8MBox)
839 {
840 case E_HVD_RISC_0:
841 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
842 break;
843 case E_HVD_RISC_1:
844 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
845 break;
846 case E_HVD_VPU_RISC_0:
847 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
848 break;
849 case E_HVD_VPU_RISC_1:
850 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
851 break;
852 default:
853 break;
854 }
855 }
856 #endif
857
_HVD_EX_GetPC(void)858 static MS_U32 _HVD_EX_GetPC(void)
859 {
860 MS_U32 u32PC = 0;
861 u32PC = HAL_VPU_EX_GetProgCnt();
862 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
863 return u32PC;
864 }
865
_HVD_EX_GetESWritePtr(MS_U32 u32Id)866 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
867 {
868 MS_U32 u32Data = 0;
869 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
870 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
871
872 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
873 {
874 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
875
876 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
877 {
878 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
879
880 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
881 }
882 }
883 else
884 {
885 #if HVD_ENABLE_MVC
886 MS_U8 u8ViewIdx = 0;
887 if(HAL_HVD_EX_CheckMVCID(u32Id))
888 {
889 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
890 }
891 if(u8ViewIdx != 0) /// 2nd ES ptr.
892 {
893 u32Data = pShm->u32ES2WritePtr;
894 }
895 else
896 {
897 u32Data = pShm->u32ESWritePtr;
898 }
899 #else
900 u32Data = pShm->u32ESWritePtr;
901 #endif
902 }
903
904 return u32Data;
905 }
906
907 #define NAL_UNIT_LEN_BITS 21
908 #define NAL_UNIT_OFT_BITS 30
909 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
910 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
911 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
912
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)913 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
914 {
915 MS_U32 u32Data = 0;
916 MS_U8 u8TaskId = 0;
917 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
918 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
919 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
920 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
921 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
922
923 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
924 #if HVD_ENABLE_MVC
925 if(HAL_HVD_EX_CheckMVCID(u32Id))
926 {
927 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
928 }
929 #endif /// HVD_ENABLE_MVC
930
931 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
932 {
933 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
934 {
935 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
936 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
937 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
938 MS_U32 *u32Adr;
939 MS_U32 u32Tmp;
940
941 if (u16ReadPtr == u16WritePtr)
942 {
943 u32Data = _HVD_EX_GetESWritePtr(u32Id);
944 }
945 else
946 {
947 if (u16ReadPtr)
948 u16ReadPtr--;
949 else
950 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
951
952 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
953
954 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
955 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
956 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
957 u32Data = u32Data | u32Tmp;
958
959 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
960 //while(1);
961 }
962 goto EXIT;
963 }
964 // set reg_poll_nal_rptr 0
965 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
966 // set reg_poll_nal_rptr 1
967 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
968
969 // read reg_nal_rptr_hi
970 #ifdef VDEC3
971 if (0 == pCtrl->u32BBUId)
972 #else
973 if (0 == u8TaskId)
974 #endif
975 {
976 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
977 u32Data >>= 6;
978 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
979 }
980 else
981 {
982 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
983 u32Data >>= 6;
984 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
985 }
986
987 u32Data <<= 3; // unit
988
989 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
990 {
991 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
992
993 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
994 {
995 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
996 u32Data = u32ESWptr;
997 }
998 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
999 {
1000 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1001 u32Data = u32ESWptr;
1002 }
1003 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1004 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1005 {
1006 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1007 u32Data = u32ESWptr;
1008 }
1009 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1010 && ((u32Data - u32ESWptr) < 32)
1011 && (pCtrl->u32FlushRstPtr == 1))
1012 {
1013 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1014 u32Data = u32ESWptr;
1015 }
1016 }
1017
1018 // remove illegal pointer
1019 #if 1
1020 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1021 {
1022 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1023
1024 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1025 (u32PacketStaddr <
1026 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1027 {
1028 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1029 u32Data = pCtrl->u32LastESRptr;
1030 }
1031 }
1032 #endif
1033 }
1034 else
1035 {
1036 #if HVD_ENABLE_MVC
1037 MS_U8 u8ViewIdx = 0;
1038 if(HAL_HVD_EX_CheckMVCID(u32Id))
1039 {
1040 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1041 }
1042 if(u8ViewIdx != 0) /// 2nd ES ptr.
1043 {
1044 u32Data = pShm->u32ES2ReadPtr;
1045 }
1046 else
1047 {
1048 u32Data = pShm->u32ESReadPtr;
1049 }
1050 #else
1051 u32Data = pShm->u32ESReadPtr;
1052 #endif
1053 }
1054
1055 EXIT:
1056
1057 pCtrl->u32LastESRptr = u32Data;
1058
1059 return u32Data;
1060 }
1061
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1062 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1063 {
1064 MS_U16 u16TimeOut = 0xFFFF;
1065 MS_BOOL bResult = FALSE;
1066
1067 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1068
1069 while (--u16TimeOut)
1070 {
1071 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1072 {
1073 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1074 break;
1075 }
1076 }
1077
1078 return bResult;
1079 }
1080
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1081 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1082 {
1083 MS_U16 u16TimeOut = 0xFFFF;
1084 MS_BOOL bResult = FALSE;
1085 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1086
1087 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1088
1089 #if HVD_ENABLE_MVC
1090 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1091 {
1092 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1093 }
1094 #endif /// HVD_ENABLE_MVC
1095
1096 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1097
1098 while (--u16TimeOut)
1099 {
1100 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1101 {
1102 u32Cmd |= (u8TaskId << 24);
1103 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1104 break;
1105 }
1106 }
1107 return bResult;
1108 }
1109
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1110 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1111 {
1112 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1113 #ifdef VDEC3
1114 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1115 MS_BOOL IsSent = FALSE;
1116 MS_BOOL IsMailBox = FALSE;
1117 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1118
1119 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1120 {
1121 do {
1122 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1123 if (!SentRet)
1124 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1125 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1126 break;
1127 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1128 IsSent = TRUE;
1129 break;
1130 }
1131 else if (HVD_GetSysTime_ms() > u32timeout)
1132 {
1133 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1134 break;
1135 }
1136 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1137 }
1138 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1139 {
1140 do {
1141 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1142 if (!SentRet)
1143 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1144 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1145 break;
1146 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1147 IsSent = TRUE;
1148 break;
1149 }
1150 else if (HVD_GetSysTime_ms() > u32timeout)
1151 {
1152 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1153 break;
1154 }
1155 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1156 }
1157 if (!IsSent) {
1158 IsMailBox = TRUE;
1159 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1160 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1161 #else
1162 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1163 #endif
1164 {
1165 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1166 if (HVD_GetSysTime_ms() > u32timeout)
1167 {
1168 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1169 return E_HVD_RETURN_TIMEOUT;
1170 }
1171 #endif
1172
1173 #if 0
1174 if (u32Cmd == E_HVD_CMD_STOP)
1175 {
1176 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1177 #if HVD_ENABLE_MVC
1178 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1179 {
1180 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1181 }
1182 #endif /// HVD_ENABLE_MVC
1183 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1184
1185 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1186 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1187
1188 return E_HVD_RETURN_SUCCESS;
1189 }
1190 #endif
1191
1192 if(u32Cmd < E_DUAL_CMD_BASE)
1193 {
1194 //_HVD_EX_GetPC();
1195 HAL_HVD_EX_Dump_FW_Status(u32Id);
1196 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1197 }
1198 }
1199
1200 #ifdef VDEC3
1201 }
1202 IsSent = FALSE;
1203 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1204 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1205 {
1206 do {
1207 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1208 if (!SentRet)
1209 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1210 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1211 break;
1212 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1213 IsSent = TRUE;
1214 break;
1215 }
1216 else if (HVD_GetSysTime_ms() > u32timeout)
1217 {
1218 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1219 break;
1220 }
1221 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1222 }
1223 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1224 {
1225 do {
1226 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1227 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1228 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1229 }
1230 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1231 break;
1232 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1233 IsSent = TRUE;
1234 break;
1235 }
1236 else if (HVD_GetSysTime_ms() > u32timeout)
1237 {
1238 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1239 break;
1240 }
1241 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1242 }
1243 if (!IsSent)
1244 {
1245 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1246 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1247 #else
1248 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1249
1250 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1251 #endif
1252 {
1253 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1254 if (HVD_GetSysTime_ms() > u32timeout)
1255 {
1256 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1257 return E_HVD_RETURN_TIMEOUT;
1258 }
1259 #endif
1260 if(u32Cmd < E_DUAL_CMD_BASE)
1261 {
1262 //_HVD_EX_GetPC();
1263 HAL_HVD_EX_Dump_FW_Status(u32Id);
1264 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1265 }
1266 }
1267 #ifdef VDEC3
1268 }
1269 else
1270 {
1271 HAL_HVD_EX_FlushMemory();
1272 }
1273 #endif
1274 return E_HVD_RETURN_SUCCESS;
1275 }
1276
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1277 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1278 {
1279 #if HAL_HVD_ENABLE_MIU_PROTECT
1280 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
1281 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1282 #if SUPPORT_EVD
1283 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1284 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1285 #endif
1286 _HVD_MIU_SetReqMask(HVD_RW, bEnable);
1287 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1288 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1289 //HVD_Delay_ms(1);
1290 #endif
1291 return;
1292 }
1293
1294 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)1295 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
1296 {
1297 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1298
1299 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
1300 #if SUPPORT_MSVP9
1301 || u32CodecType == E_HVD_INIT_HW_VP9
1302 #endif
1303 )
1304 return TRUE;
1305
1306 return FALSE;
1307 }
1308
_HAL_EX_IS_HVD(MS_U32 u32ModeFlag)1309 static MS_BOOL _HAL_EX_IS_HVD(MS_U32 u32ModeFlag) // VP8 isn't included
1310 {
1311 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1312
1313 if ((u32CodecType == E_HVD_INIT_HW_MVC) ||
1314 (u32CodecType == E_HVD_INIT_HW_AVC) ||
1315 (u32CodecType == E_HVD_INIT_HW_AVS) ||
1316 (u32CodecType == E_HVD_INIT_HW_RM))
1317 return TRUE;
1318
1319 return FALSE;
1320 }
1321
_HAL_EX_BBU_EVD_InUsed(void)1322 static MS_BOOL _HAL_EX_BBU_EVD_InUsed(void)
1323 {
1324 if (!pHVDHalContext)
1325 return FALSE;
1326
1327 MS_U32 i;
1328 MS_BOOL bRet = FALSE;
1329
1330 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1331 {
1332 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1333 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC)
1334 || (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC_DV)
1335 #if SUPPORT_MSVP9
1336 ||(pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP9)
1337 #endif
1338 ))
1339 {
1340 bRet = TRUE;
1341 break;
1342 }
1343 }
1344
1345 return bRet;
1346 }
1347
_HAL_EX_BBU_HVD_InUsed(void)1348 static MS_BOOL _HAL_EX_BBU_HVD_InUsed(void) // VP8 isn't included
1349 {
1350 if (!pHVDHalContext)
1351 return FALSE;
1352
1353 MS_U32 i;
1354 MS_BOOL bRet = FALSE;
1355
1356 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1357 {
1358 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1359 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVC) ||
1360 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVS) ||
1361 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_RM)))
1362 {
1363 bRet = TRUE;
1364 break;
1365 }
1366 }
1367
1368 return bRet;
1369 }
1370
_HAL_EX_BBU_VP8_InUsed(void)1371 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
1372 {
1373 if (!pHVDHalContext)
1374 return FALSE;
1375
1376 MS_U32 i;
1377 MS_BOOL bRet = FALSE;
1378
1379 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1380 {
1381 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
1382 {
1383 bRet = TRUE;
1384 break;
1385 }
1386 }
1387
1388 return bRet;
1389 }
1390
1391 #endif
1392
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1393 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1394 {
1395 MS_U16 u16Reg = 0;
1396 MS_VIRT u32StAddr = 0;
1397 #ifdef VDEC3
1398 MS_U32 u32Length = 0;
1399 #endif
1400 //MS_BOOL bBitMIU1 = FALSE;
1401 //MS_BOOL bCodeMIU1 = FALSE;
1402 MS_U8 u8BitMiuSel = 0;
1403 MS_U8 u8CodeMiuSel = 0;
1404 MS_U8 u8FBMiuSel = 0;
1405 MS_U32 u32BitStartOffset;
1406 MS_U32 u32CodeStartOffset;
1407 MS_U32 u32FBStartOffset;
1408
1409 MS_U8 u8TaskId = 0;
1410 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1411 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1412 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1413 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1414
1415 // MS_U32 u32TmpStartOffset;
1416 MS_U8 u8TmpMiuSel;
1417
1418
1419
1420 if(pCtrl == NULL) return;
1421
1422 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1423 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1424 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1425
1426 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1427 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1428 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1429 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1430 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1431 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1432 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1433 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1434 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1435 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
1436 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
1437
1438 if (u8BitMiuSel != u8CodeMiuSel)
1439 {
1440 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
1441 }
1442 else
1443 {
1444 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
1445 }
1446
1447 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1448 {
1449 #ifdef VDEC3
1450 if (!_HAL_EX_BBU_VP8_InUsed())
1451 #endif
1452 {
1453 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1454
1455 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1456 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1457 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1458
1459 u32StAddr += VP8_BBU_TBL_SIZE;
1460
1461 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1462 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1463 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1464 }
1465
1466 // ES buffer
1467 #ifdef VDEC3
1468 if(pCtrl->bNStreamMode)
1469 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1470 else
1471 #endif
1472 u32StAddr = u32BitStartOffset;
1473
1474 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1475
1476 #ifdef VDEC3
1477 if (!_HAL_EX_BBU_VP8_InUsed())
1478 #endif
1479 {
1480 HVD_EX_MSG_DBG("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1481
1482 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1483 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1484
1485 #ifdef VDEC3
1486 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1487 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1488 #else
1489 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1490 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1491 #endif
1492
1493 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1494 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1495 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1496 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1497 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1498 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1499 }
1500
1501 return;
1502 }
1503
1504 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1505
1506 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
1507
1508 #ifdef VDEC3
1509 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1510 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1511 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1512 {
1513 if (pCtrl->u32BBUId == 0)
1514 {
1515 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1516 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1517 // -1 is for NAL_TAB_LEN counts from zero.
1518 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1519 }
1520 else
1521 {
1522 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1523 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1524 // -1 is for NAL_TAB_LEN counts from zero.
1525 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1526 }
1527 }
1528 #else
1529 if (0 == u8TaskId)
1530 {
1531 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1532 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1533 // -1 is for NAL_TAB_LEN counts from zero.
1534 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1535 }
1536 else
1537 {
1538 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1539 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1540 // -1 is for NAL_TAB_LEN counts from zero.
1541 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1542 }
1543 #endif
1544
1545 // ES buffer
1546 #ifdef VDEC3
1547 if(!pCtrl->bNStreamMode || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1548 {
1549 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1550 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1551 }
1552 else
1553 {
1554 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1555 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1556 }
1557 #else
1558 u32StAddr = u32BitStartOffset;
1559 #endif
1560
1561 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1562
1563 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1564
1565 #ifdef VDEC3
1566 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1567 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1568 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1569 {
1570 if (pCtrl->u32BBUId == 0)
1571 {
1572 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1573 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1574
1575 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1576 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1577 }
1578 else
1579 {
1580 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1581 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1582
1583 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1584 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1585 }
1586 }
1587 #else
1588 if (0 == u8TaskId)
1589 {
1590 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1591 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1592
1593 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1594 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1595 }
1596 else
1597 {
1598 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1599 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1600
1601 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1602 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1603 }
1604 #endif
1605
1606 // others
1607 #ifdef VDEC3
1608 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1609 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1610 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1611 {
1612 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1613
1614 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1615 {
1616 if (pCtrl->u32BBUId == 0)
1617 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1618 else
1619 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1620 }
1621 else
1622 {
1623 if (pCtrl->u32BBUId == 0)
1624 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1625 else
1626 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1627 }
1628
1629 if (pCtrl->u32BBUId == 0)
1630 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1631 else
1632 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1633
1634 if (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // RM
1635 {
1636 if (pCtrl->u32BBUId == 0) // force BBU to remove nothing, RM only
1637 u16Reg |= HVD_REG_BBU_PASER_DISABLE;
1638 else
1639 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2;
1640 }
1641 #if SUPPORT_MSVP9
1642 else if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1643 {
1644 if (pCtrl->u32BBUId == 0)
1645 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03;
1646 else
1647 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03_BS2;
1648 }
1649 #endif
1650 else // AVS or AVC or HEVC or HEVC_DV
1651 {
1652 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1653 {
1654 if (pCtrl->u32BBUId == 0)
1655 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1656 else
1657 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1658 }
1659 else // start code remained
1660 {
1661 if (pCtrl->u32BBUId == 0)
1662 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1663 else
1664 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1665 }
1666 }
1667
1668 if (pCtrl->u32BBUId == 0)
1669 {
1670 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1671 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1672 }
1673 else
1674 {
1675 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1676 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1677 }
1678 }
1679 #else
1680 if (0 == u8TaskId)
1681 {
1682 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1683
1684 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1685 {
1686 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1687 }
1688 else
1689 {
1690 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1691 }
1692
1693 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1694
1695 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1696 {
1697 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1698 }
1699 else // AVS or AVC
1700 {
1701 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1702 {
1703 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1704 }
1705 else // start code remained
1706 {
1707 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1708 }
1709 }
1710
1711 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1712
1713 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1714 }
1715 else
1716 {
1717 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1718
1719 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1720 {
1721 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1722 }
1723 else
1724 {
1725 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1726 }
1727
1728 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1729
1730 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1731 {
1732 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1733 }
1734 else // AVS or AVC
1735 {
1736 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1737 {
1738 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1739 }
1740 else // start code remained
1741 {
1742 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1743 }
1744 }
1745
1746 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1747
1748 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1749 }
1750 #endif
1751
1752 #if (HVD_ENABLE_MVC)
1753 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1754 {
1755 /// Used sub stream to record sub view data.
1756 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1757 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1758
1759 if (u8BitMiuSel != u8CodeMiuSel)
1760 {
1761 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
1762 }
1763 else
1764 {
1765 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
1766 }
1767
1768
1769 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
1770 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
1771 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
1772 // -1 is for NAL_TAB_LEN counts from zero.
1773 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1774
1775 // ES buffer
1776 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1777
1778 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1779 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1780 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1781
1782 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1783 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1784
1785 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1786 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1787 {
1788 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1789 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1790 }
1791 else
1792 {
1793 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1794 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1795 }
1796 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1797 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1798 {
1799 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1800 }
1801 else // AVS or AVC
1802 {
1803 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1804 {
1805 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1806 }
1807 else // start code remained
1808 {
1809 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1810 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1811 }
1812 }
1813 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1814 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1815 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1816 }
1817 #endif
1818
1819 // MIF offset
1820 #if 0
1821 {
1822 MS_U16 offaddr = 0;
1823 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1824 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1825 {
1826 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1827 }
1828 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1829 offaddr = (MS_U16) ((u32StAddr) >> 20);
1830 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1831 //0x1FF; // 9 bits(L + H)
1832 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1833 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1834 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1835 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1836 {
1837 u16Reg |= HVD_REG_MIF_OFFSET_H;
1838 }
1839 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1840 }
1841 #endif
1842 }
1843
1844 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1845 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1846 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1847 {
1848 MS_U16 u16Reg = 0;
1849 MS_U32 u32StAddr = 0;
1850 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1851 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1852 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1853
1854 if(pCtrl == NULL) return;
1855
1856 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1857 {
1858 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1859
1860 // ES buffer
1861 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1862
1863 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1864 {
1865 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1866 }
1867
1868 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1869 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1870
1871 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1872 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1873
1874 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1875 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1876 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1877 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1878 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1879 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1880
1881 return;
1882 }
1883
1884 // ES buffer
1885 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1886
1887 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1888 {
1889 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1890 }
1891
1892 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1893
1894 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1895 {
1896 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1897 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1898
1899 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1900 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1901 }
1902 else
1903 {
1904 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1905 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1906
1907 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1908 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1909 }
1910 }
1911 #endif
1912
_HVD_EX_GetESLevel(MS_U32 u32Id)1913 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1914 {
1915 MS_U32 u32Wptr = 0;
1916 MS_U32 u32Rptr = 0;
1917 MS_U32 u32CurMBX = 0;
1918 MS_U32 u32ESsize = 0;
1919 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1920 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1921
1922 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1923 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1924 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1925
1926 if (u32Rptr >= u32Wptr)
1927 {
1928 u32CurMBX = u32Rptr - u32Wptr;
1929 }
1930 else
1931 {
1932 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1933 }
1934
1935 if (u32CurMBX == 0)
1936 {
1937 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1938 }
1939 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1940 {
1941 u32Ret = E_HVD_ESB_LEVEL_OVER;
1942 }
1943 else
1944 {
1945 u32CurMBX = u32ESsize - u32CurMBX;
1946 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1947 {
1948 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1949 }
1950 }
1951
1952 return u32Ret;
1953 }
1954
_HVD_EX_GetESQuantity(MS_U32 u32Id)1955 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1956 {
1957 MS_U32 u32Wptr = 0;
1958 MS_U32 u32Rptr = 0;
1959 MS_U32 u32ESsize = 0;
1960 MS_U32 u32Ret = 0;
1961 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1962
1963 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1964 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1965 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1966
1967
1968 if(u32Wptr >= u32Rptr)
1969 {
1970 u32Ret = u32Wptr - u32Rptr;
1971 }
1972 else
1973 {
1974 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1975 }
1976 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1977 return u32Ret;
1978 }
1979
1980 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)1981 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
1982 {
1983
1984 MS_U32 u32Timeout = 20000;
1985
1986 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
1987 {
1988
1989 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1990
1991 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
1992
1993
1994 while (u32Timeout)
1995 {
1996
1997 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
1998 {
1999 break;
2000 }
2001 u32Timeout--;
2002 HVD_Delay_ms(1);
2003 }
2004
2005 HAL_VPU_EX_IQMemSetDAMode(FALSE);
2006
2007 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
2008
2009 if (u32Timeout==0)
2010 {
2011 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
2012 return FALSE;
2013 }
2014
2015
2016 }
2017 return TRUE;
2018 }
2019
2020 #endif
2021
2022 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2023 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2024 #else
2025 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2026 #endif
2027 {
2028 MS_U32 u32FirmVer = 0;
2029 MS_U32 u32Timeout = 20000;
2030 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2031
2032 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2033
2034 #if HVD_ENABLE_TIME_MEASURE
2035 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2036 #endif
2037
2038 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2039
2040 VPU_EX_FWCodeCfg fwCfg;
2041 VPU_EX_TaskInfo taskInfo;
2042 VPU_EX_VLCTblCfg vlcCfg;
2043 #ifdef VDEC3
2044 VPU_EX_FBCfg fbCfg;
2045 #endif
2046 VPU_EX_NDecInitPara nDecInitPara;
2047
2048 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2049 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2050 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2051 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2052 #ifdef VDEC3_FB
2053 nDecInitPara.pVLCCfg = NULL;
2054 #else
2055 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2056 {
2057 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2058 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2059 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2060 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2061 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2062 nDecInitPara.pVLCCfg = &vlcCfg;
2063 }
2064 #endif
2065 nDecInitPara.pFWCodeCfg = &fwCfg;
2066 nDecInitPara.pTaskInfo = &taskInfo;
2067 #ifdef VDEC3
2068 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2069 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2070
2071 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2072 {
2073 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2074 }
2075
2076 nDecInitPara.pFBCfg = &fbCfg;
2077 #endif
2078
2079 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2080 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2081 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2082 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2083 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2084
2085 taskInfo.u32Id = u32Id;
2086
2087 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2088 {
2089 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2090 }
2091 #ifdef VDEC3
2092 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2093 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
2094 {
2095 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2096 }
2097 #if SUPPORT_MSVP9
2098 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2099 {
2100 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2101 }
2102 #endif
2103 #if SUPPORT_G2VP9
2104 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2105 {
2106 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2107 }
2108 #endif
2109 #endif
2110 else
2111 {
2112 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2113 }
2114
2115 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2116
2117 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2118 {
2119 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2120 }
2121 else
2122 {
2123 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2124 }
2125 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2126
2127 #ifdef SUPPORT_EVD
2128 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2129 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2130 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2131 #endif
2132
2133 if(TRUE == HVD_EX_GetRstFlag())
2134 {
2135 //Delete task for Rst
2136 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2137 {
2138 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2139 }
2140 HVD_EX_SetRstFlag(FALSE);
2141 }
2142
2143 #if (HVD_ENABLE_IQMEM)
2144 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2145 #endif
2146
2147 #ifdef VDEC3
2148 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2149 #else
2150 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2151 #endif
2152 {
2153 HVD_EX_MSG_ERR("Task create fail!\n");
2154
2155 return FALSE;
2156 }
2157
2158 while (u32Timeout)
2159 {
2160 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2161
2162 if (u32FirmVer != 0)
2163 {
2164 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2165 break;
2166 }
2167 u32Timeout--;
2168 HVD_Delay_ms(1);
2169 }
2170
2171 #ifdef VDEC3_FB
2172 #if HVD_ENABLE_RV_FEATURE
2173 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2174
2175 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2176 {
2177 if(pShm->u32RM_VLCTableAddr == 0) {
2178 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2179 }
2180 else
2181 {
2182 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2183 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2184 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2185 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2186 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2187 nDecInitPara.pVLCCfg = &vlcCfg;
2188 }
2189 }
2190
2191 if (nDecInitPara.pVLCCfg)
2192 {
2193 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2194 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2195 {
2196 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2197 return FALSE;
2198 }
2199 }
2200 #endif
2201 #endif
2202 if (u32Timeout > 0)
2203 {
2204 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2205
2206 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2207
2208 #ifdef VDEC3
2209 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2210 {
2211 case E_HVD_INIT_HW_AVC:
2212 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2213 break;
2214 case E_HVD_INIT_HW_AVS:
2215 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2216 break;
2217 case E_HVD_INIT_HW_RM:
2218 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2219 break;
2220 case E_HVD_INIT_HW_MVC:
2221 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2222 break;
2223 case E_HVD_INIT_HW_VP8:
2224 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2225 break;
2226 case E_HVD_INIT_HW_MJPEG:
2227 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2228 break;
2229 case E_HVD_INIT_HW_VP6:
2230 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2231 break;
2232 case E_HVD_INIT_HW_HEVC:
2233 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2234 break;
2235 case E_HVD_INIT_HW_VP9:
2236 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2237 break;
2238 case E_HVD_INIT_HW_HEVC_DV:
2239 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
2240 break;
2241 default:
2242 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2243 break;
2244 }
2245 #endif
2246
2247 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2248 }
2249 else
2250 {
2251 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2252 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2253
2254 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2255 {
2256 HVD_EX_MSG_ERR("Task delete fail!\n");
2257 }
2258
2259 return FALSE;
2260 }
2261
2262
2263
2264 #if (HVD_ENABLE_IQMEM)
2265
2266 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2267 {
2268
2269 HAL_HVD_EX_IQMem_Init(u32Id);
2270 }
2271 else{
2272 HVD_EX_MSG_DBG("not support IQMEM\n");
2273 }
2274 #endif
2275
2276
2277
2278
2279
2280
2281 #if HVD_ENABLE_TIME_MEASURE
2282 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2283 #endif
2284
2285 return TRUE;
2286 }
2287
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2288 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2289 {
2290 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2291 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2292 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2293 {
2294 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2295 }
2296 else
2297 {
2298 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2299 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2300 }
2301 }
2302
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2303 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2304 {
2305 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2306 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2307
2308 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2309 {
2310 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2311 }
2312 else
2313 {
2314 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2315 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2316 }
2317 }
2318
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2319 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2320 {
2321 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2322 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2323
2324 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2325 {
2326 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2327 {
2328 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2329 }
2330 }
2331 else
2332 {
2333 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2334 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2335 }
2336 }
2337
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2338 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2339 {
2340 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2341 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2342 MS_VIRT u32DestAddr = 0;
2343 HVD_PTS_Entry PTSEntry;
2344 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2345 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2346 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2347
2348 // update R & W ptr
2349 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2350
2351 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2352
2353 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2354 {
2355 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2356 (MS_U32) MAX_PTS_TABLE_SIZE);
2357 return E_HVD_RETURN_FAIL;
2358 }
2359
2360 // check queue is full or not
2361 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2362 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2363
2364 if (u32PTSWptr == u32PTSRptr)
2365 {
2366 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2367 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2368 return E_HVD_RETURN_FAIL;
2369 }
2370
2371 // add one PTS entry
2372 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2373 PTSEntry.u32ID_L = pInfo->u32ID_L;
2374 PTSEntry.u32ID_H = pInfo->u32ID_H;
2375 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2376
2377 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2378
2379 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2380
2381 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2382
2383 HAL_HVD_EX_FlushMemory();
2384
2385 // update Write ptr
2386 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2387
2388 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2389
2390 return E_HVD_RETURN_SUCCESS;
2391 }
2392
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2393 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2394 {
2395 //---------------------------------------------------
2396 // item format in nal table:
2397 // reserved |borken| u32NalOffset | u32NalLen
2398 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2399 //---------------------------------------------------
2400 MS_VIRT u32Adr = 0;
2401 MS_U32 u32BBUNewWptr = 0;
2402 MS_U8 item[8];
2403 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2404 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2405 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2406 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2407
2408 #if HVD_ENABLE_MVC
2409 if(HAL_HVD_EX_CheckMVCID(u32Id))
2410 {
2411 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2412 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2413 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2414 {
2415 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2416 }
2417 }
2418 #endif /// HVD_ENABLE_MVC
2419
2420 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2421 {
2422 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2423 }
2424 else
2425 {
2426 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2427 }
2428 u32BBUNewWptr++;
2429 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2430
2431 // prepare nal entry
2432
2433 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
2434 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2435 {
2436 // NAL len 22 bits , HEVC level5 constrain
2437 item[0] = u32NalLen & 0xff;
2438 item[1] = (u32NalLen >> 8) & 0xff;
2439 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2440 item[3] = (u32NalOffset >> 2) & 0xff;
2441 item[4] = (u32NalOffset >> 10) & 0xff;
2442 item[5] = (u32NalOffset >> 18) & 0xff;
2443 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2444 item[7] = 0;
2445 }
2446 else
2447 {
2448 item[0] = u32NalLen & 0xff;
2449 item[1] = (u32NalLen >> 8) & 0xff;
2450 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2451 item[3] = (u32NalOffset >> 3) & 0xff;
2452 item[4] = (u32NalOffset >> 11) & 0xff;
2453 item[5] = (u32NalOffset >> 19) & 0xff;
2454 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2455 item[7] = 0;
2456 }
2457
2458 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2459 {
2460 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2461 }
2462 else
2463 {
2464 // add nal entry
2465 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2466 }
2467
2468 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2469
2470 HAL_HVD_EX_FlushMemory();
2471
2472 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2473
2474 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2475 {
2476 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2477 }
2478 else
2479 {
2480 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2481 }
2482
2483 return E_HVD_RETURN_SUCCESS;
2484 }
2485
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2486 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2487 {
2488 MS_U8 item[8];
2489 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2490 MS_VIRT u32Adr = 0;
2491 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2492 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2493 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2494
2495 /*
2496 printf("nal2 offset=0x%x, len=0x%x\n",
2497 u32NalOffset2, u32NalLen2);
2498 */
2499
2500 item[0] = u32NalLen2 & 0xff;
2501 item[1] = (u32NalLen2 >> 8) & 0xff;
2502 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2503 item[3] = (u32NalOffset2 >> 3) & 0xff;
2504 item[4] = (u32NalOffset2 >> 11) & 0xff;
2505 item[5] = (u32NalOffset2 >> 19) & 0xff;
2506 item[6] = (u32NalOffset2 >> 27) & 0x07;
2507 item[7] = 0;
2508
2509 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2510 {
2511 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2512 }
2513 else
2514 {
2515 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2516 }
2517
2518 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2519
2520 HAL_HVD_EX_FlushMemory();
2521
2522 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2523 }
2524
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2525 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2526 {
2527 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2528 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2529
2530 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2531 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2532 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2533 {
2534 MS_U16 i;
2535 MS_PHY u32VUIAddr;
2536 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2537
2538 HAL_HVD_EX_ReadMemory();
2539 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2540
2541 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2542 {
2543 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2544 {
2545 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2546 }
2547 else
2548 {
2549 *pData = *((MS_VIRT *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2550 }
2551 pData++;
2552 }
2553 }
2554 else
2555 {
2556 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2557 }
2558
2559 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2560 }
2561
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2562 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2563 {
2564 MS_U32 u32ReadPtr = 0;
2565 MS_U32 eRet = 0;
2566 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2567 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2568
2569 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2570 MS_U32 u32WritePtr = 0;
2571
2572 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2573 {
2574 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2575 }
2576 else
2577 {
2578 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2579 }
2580
2581 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2582
2583 if (u32WritePtr >= u32ReadPtr)
2584 {
2585 eRet = u32WritePtr - u32ReadPtr;
2586 }
2587 else
2588 {
2589 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2590 }
2591
2592 #if 0
2593 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2594 {
2595 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2596 }
2597 else
2598 {
2599 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2600 }
2601
2602 #endif
2603 return eRet;
2604 }
2605
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2606 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2607 {
2608 MS_U32 u32ReadPtr = 0;
2609 MS_U32 eRet = 0;
2610 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2611
2612 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2613
2614 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2615 {
2616 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2617 (MS_U32) MAX_PTS_TABLE_SIZE);
2618 return 0;
2619 }
2620
2621 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2622
2623 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2624 {
2625 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2626 }
2627 else
2628 {
2629 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2630 }
2631
2632 return eRet;
2633 }
2634
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)2635 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2636 {
2637 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2638
2639 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2640 }
2641
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2642 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2643 {
2644 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2645 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2646 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2647 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2648 HAL_HVD_EX_ReadMemory();
2649 MS_U16 u16QNum = pShm->u16DispQNumb;
2650 MS_U16 u16QPtr = pShm->u16DispQPtr;
2651
2652 HVD_Frm_Information *pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2653 if (bDolbyVision)
2654 {
2655 if (pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
2656 {
2657 return NULL;
2658 }
2659 else
2660 {
2661 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = FALSE;
2662 }
2663 }
2664
2665 #if (HVD_ENABLE_MVC)
2666 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2667 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
2668 {
2669 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2670 {
2671 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2672 MS_U16 u16UsedFrm = 0;
2673 MS_U16 u16ResvFrmNum = ((u16RealQPtr % 2) == 0) ? 1 : 0; // need to check the next frame num is exist when get first frame.
2674 if (u16RealQPtr != u16QPtr)
2675 {
2676 if (u16RealQPtr > u16QPtr)
2677 {
2678 u16UsedFrm = u16RealQPtr - u16QPtr;
2679 }
2680 else
2681 {
2682 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2683 }
2684 }
2685
2686 if (u16QNum > (u16UsedFrm + u16ResvFrmNum))
2687 {
2688 u16QNum -= u16UsedFrm;
2689 u16QPtr = u16RealQPtr;
2690 pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2691
2692 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2693 {
2694 if ((u16QPtr % 2) == 0)
2695 {
2696 HVD_Frm_Information *pHvdFrmNext = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr + 1];
2697
2698 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2699 {
2700 return NULL;
2701 }
2702
2703 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2704 if(bDolbyVision)
2705 HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2706 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2707 }
2708 else
2709 {
2710 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2711 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2712 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2713 HVD_Frm_Information *pHvdFrmPrv = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1]; // must be odd
2714
2715 if(bDolbyVision)
2716 {
2717 HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData);
2718
2719 HVD_Frm_Information *pPrevHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1];//BL
2720 if(DIFF(pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
2721 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp);
2722 }
2723 pHvdFrmPrv->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2724 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2725 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2726 }
2727 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2728 u16QPtr++;
2729 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2730 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2731
2732 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2733 }
2734 }
2735
2736 return NULL;
2737 }
2738
2739 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2740 //search the next frame to display
2741 while (u16QNum > 0)
2742 {
2743 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2744 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2745 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2746
2747 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2748 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2749 {
2750 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2751 /// Check the depned view was initial when Output the base view.
2752 if((u16QPtr%2) == 0)
2753 {
2754 HVD_Frm_Information *pHvdFrm_sub = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2755 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2756 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2757 {
2758 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2759 ///printf("Return NULL.\n");
2760 return NULL;
2761 }
2762 }
2763
2764 //printf("V:%d.\n",u16QPtr);
2765 pHVDHalContext->_u16DispQPtr = u16QPtr;
2766 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2767 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2768 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2769 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2770 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2771 }
2772
2773 u16QNum--;
2774 //go to next frame in the dispQ
2775 u16QPtr++;
2776
2777 if (u16QPtr >= pShm->u16DispQSize)
2778 {
2779 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2780 }
2781 }
2782 }
2783 else
2784 #endif ///HVD_ENABLE_MVC
2785 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
2786 if (_HVD_EX_IsHevcInterlaceField(u32Id))
2787 {
2788 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
2789 HVD_Frm_Information *pHvdFrm_first = NULL;
2790
2791 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
2792 return NULL;
2793 }
2794
2795 while (u16QNum != 0)
2796 {
2797 pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2798 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2799 {
2800 if (!first_field) // second get frame, we will check at least one paired in disp queue.
2801 {
2802 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2803 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2804 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2805
2806 if(pHvdFrm->u8FieldType == 1 || pHvdFrm->u8FieldType == 9 || pHvdFrm->u8FieldType == 11)
2807 pHvdFrm->u8FieldType = 0;
2808 else
2809 pHvdFrm->u8FieldType = 1;
2810 return pHvdFrm;
2811 }
2812 else // first get frame, we will check at least one paired in disp queue.
2813 {
2814 if (pHvdFrm_first == NULL)
2815 {
2816 pHvdFrm_first = pHvdFrm;
2817 }
2818 else
2819 {
2820 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2821 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
2822
2823 //After flush, we cannot get the correct field type of first field from sei, so we use second field type to decide first field type.
2824 if (pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 0xff)
2825 {
2826 if (pHvdFrm->u8FieldType == 9)
2827 pHvdFrm_first->u8FieldType = 12;
2828 else if (pHvdFrm->u8FieldType == 10)
2829 pHvdFrm_first->u8FieldType = 11;
2830 else if (pHvdFrm->u8FieldType == 10)
2831 pHvdFrm_first->u8FieldType = 11;
2832 else if (pHvdFrm->u8FieldType == 1)
2833 pHvdFrm_first->u8FieldType = 2;
2834 else if (pHvdFrm->u8FieldType == 2)
2835 pHvdFrm_first->u8FieldType = 1;
2836 else
2837 {
2838 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2839 return NULL;
2840 }
2841 if ((pHvdFrm_first->u32ID_L >> 16) & 0x1)
2842 pHvdFrm_first->u32ID_L |= (1 << 16);
2843 else
2844 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2845 }
2846 else if (pHvdFrm_first->u8FieldType == 9 || pHvdFrm_first->u8FieldType == 10)
2847 {
2848 if (pHvdFrm_first->u8FieldType == 9 && pHvdFrm->u8FieldType == 12)
2849 {
2850 pHvdFrm_first->u32ID_L |= (1 << 16);
2851 pHvdFrm->u32ID_L |= (1 << 16);
2852 }
2853 else if (pHvdFrm_first->u8FieldType == 10 && pHvdFrm->u8FieldType == 11)
2854 {
2855 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2856 pHvdFrm->u32ID_L &= (~(1 << 16));
2857 }
2858 else
2859 {
2860 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2861 return NULL;
2862 }
2863 }
2864 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
2865 if (pHvdFrm_first->u8FieldType == 1 || pHvdFrm_first->u8FieldType == 9 || pHvdFrm_first->u8FieldType == 11)
2866 pHvdFrm_first->u8FieldType = 0;
2867 else
2868 pHvdFrm_first->u8FieldType = 1;
2869 return pHvdFrm_first;
2870 }
2871 }
2872 }
2873 u16QNum--;
2874 //go to next frame in the dispQ
2875 u16QPtr++;
2876
2877 if (u16QPtr == pShm->u16DispQSize)
2878 {
2879 u16QPtr = 0; //wrap to the begin
2880 }
2881
2882 }
2883 return NULL;
2884 }
2885 else
2886 {
2887 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2888 {
2889
2890 while (u16QNum != 0)
2891 {
2892 pHvdFrm = (HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2893
2894 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2895 {
2896 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2897 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2898 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2899 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2900 }
2901 u16QNum--;
2902 //go to next frame in the dispQ
2903 if (bDolbyVision)
2904 u16QPtr += 2; // single layer must in even ptr
2905 else
2906 u16QPtr++;
2907
2908 if (u16QPtr >= pShm->u16DispQSize)
2909 {
2910 u16QPtr = 0; //wrap to the begin
2911 }
2912 }
2913
2914 return NULL;
2915 }
2916
2917 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2918 //search the next frame to display
2919 while (u16QNum != 0)
2920 {
2921 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2922
2923 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2924 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2925 {
2926 pHVDHalContext->_u16DispQPtr = u16QPtr;
2927 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2928 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2929 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2930 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2931 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2932 }
2933
2934 u16QNum--;
2935 //go to next frame in the dispQ
2936 u16QPtr++;
2937
2938 if (u16QPtr == pShm->u16DispQSize)
2939 {
2940 u16QPtr = 0; //wrap to the begin
2941 }
2942 }
2943 }
2944
2945 return NULL;
2946 }
2947
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2948 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2949 {
2950 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2951 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2952 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2953 {
2954 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2955 if(pVsyncBridgeExt != NULL)
2956 {
2957 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2958 }
2959 }
2960 return pFrmInfoExt;
2961 }
2962
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2963 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2964 {
2965 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2966 MS_U64 u64Ret = 0;
2967 #if SUPPORT_EVD
2968 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
2969 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2970 #if SUPPORT_MSVP9
2971 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2972 #endif
2973 #endif
2974
2975 #if SUPPORT_EVD
2976 if (isEVD)
2977 {
2978 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2979 }
2980 else
2981 #endif
2982 #if SUPPORT_G2VP9
2983 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2984 {
2985 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2986 }
2987 else
2988 #endif
2989 {
2990 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2991 }
2992
2993 return u64Ret;
2994 }
2995
2996 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2997 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2998 {
2999 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3000 MS_U16 u16QNum = pShm->u16DispQNumb;
3001 MS_U16 u16QPtr = pShm->u16DispQPtr;
3002 static volatile HVD_Frm_Information *pHvdFrm = NULL;
3003 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3004 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3005 MS_BOOL bMVC = FALSE;
3006 #if HVD_ENABLE_MVC
3007 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3008 #endif
3009
3010
3011 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
3012 {
3013 if (u16QNum == 1) return TRUE;
3014 }
3015
3016 while (u16QNum != 0)
3017 {
3018 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3019 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3020 {
3021 return FALSE;
3022 }
3023 u16QNum--;
3024
3025 if (bDolbyVision)
3026 u16QPtr += 2; // single layer must in even ptr
3027 else
3028 u16QPtr++;
3029
3030 if (u16QPtr >= pShm->u16DispQSize)
3031 {
3032 u16QPtr = 0; //wrap to the begin
3033 }
3034 }
3035
3036 return TRUE;
3037 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)3038 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
3039 {
3040 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3041
3042 return &(_pHVDCtrls[u8DrvId]);
3043 }
3044
_HVD_EX_GetStreamIdx(MS_U32 u32Id)3045 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
3046 {
3047 MS_U8 u8OffsetIdx = 0;
3048 MS_U8 u8SidBaseMask = 0xF0;
3049 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
3050
3051 switch (eSidBase)
3052 {
3053 case E_HAL_HVD_MAIN_STREAM_BASE:
3054 {
3055 u8OffsetIdx = 0;
3056 break;
3057 }
3058 case E_HAL_VPU_SUB_STREAM_BASE:
3059 {
3060 u8OffsetIdx = 1;
3061 break;
3062 }
3063 case E_HAL_VPU_MVC_STREAM_BASE:
3064 {
3065 u8OffsetIdx = 0;
3066 break;
3067 }
3068 #ifdef VDEC3
3069 case E_HAL_VPU_N_STREAM_BASE:
3070 {
3071 u8OffsetIdx = (u32Id>>8) & 0xF;
3072 break;
3073 }
3074 #endif
3075 default:
3076 {
3077 u8OffsetIdx = 0;
3078 break;
3079 }
3080 }
3081
3082 return u8OffsetIdx;
3083 }
3084 /*
3085 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3086 {
3087 MS_U32 i = 0;
3088 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3089 {
3090 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
3091 {
3092 return TRUE;
3093 }
3094 }
3095 return FALSE;
3096 }
3097 */
3098
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3099 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3100 {
3101 MS_PHY u32PhyAddr = 0x0;
3102 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3103
3104 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3105 {
3106 return 0;
3107 }
3108
3109 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3110
3111 if (u32PhyAddr == 0xFFFFFFFF) //boris
3112 {
3113 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3114 }
3115 else
3116 {
3117 // TEE, common + share_info
3118 u32PhyAddr += COMMON_AREA_SIZE;
3119 }
3120
3121 return MsOS_PA2KSEG1(u32PhyAddr);
3122 }
3123
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3124 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3125 {
3126 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3127 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3128
3129 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3130 {
3131 return 0;
3132 }
3133
3134 MS_PHY u32PhyAddr = 0x0;
3135 #if 0
3136 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3137
3138 if (u32PhyAddr == 0xFFFFFFFF)
3139 {
3140 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3141 }
3142 #endif
3143 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3144 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3145
3146 return MsOS_PA2KSEG1(u32PhyAddr);
3147 }
3148
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3149 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3150 {
3151
3152 if (u8MiuSel == E_CHIP_MIU_0)
3153 {
3154 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3155 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3156 }
3157 else if (u8MiuSel == E_CHIP_MIU_1)
3158 {
3159 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3160 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3161 }
3162 else // 2
3163 {
3164 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3165 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3166 }
3167
3168 }
3169
3170 #if SUPPORT_G2VP9 && defined(VDEC3)
3171 #ifdef __ARM_NEON__
3172 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3173 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3174 {
3175 uint32x4x4_t data, data2;
3176 MS_U8* raster2 = raster + tile_w * 4;
3177
3178 data = vld4q_u32((const uint32_t *)tile);
3179 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3180
3181 vst1q_u32((uint32_t *)raster, data.val[0]);
3182 raster += stride;
3183 vst1q_u32((uint32_t *)raster, data.val[1]);
3184 raster += stride;
3185 vst1q_u32((uint32_t *)raster, data.val[2]);
3186 raster += stride;
3187 vst1q_u32((uint32_t *)raster, data.val[3]);
3188
3189
3190 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3191 raster2 += stride;
3192 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3193 raster2 += stride;
3194 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3195 raster2 += stride;
3196 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3197 }
3198 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3199 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3200 {
3201 MS_U8* tile0 = tile;
3202 MS_U8* tile1 = tile+16;
3203 MS_U8* tile2 = tile+32;
3204 MS_U8* tile3 = tile+48;
3205 int i;
3206
3207 for (i=0; i<4; i++) {
3208 raster[i] = tile0[i];
3209 raster[4+i] = tile1[i];
3210 raster[8+i] = tile2[i];
3211 raster[12+i] = tile3[i];
3212 }
3213
3214 for (i=0; i<4; i++) {
3215 raster[stride+i] = tile0[4+i];
3216 raster[stride+4+i] = tile1[4+i];
3217 raster[stride+8+i] = tile2[4+i];
3218 raster[stride+12+i] = tile3[4+i];
3219 }
3220
3221 for (i=0; i<4; i++) {
3222 raster[2*stride+i] = tile0[8+i];
3223 raster[2*stride+4+i] = tile1[8+i];
3224 raster[2*stride+8+i] = tile2[8+i];
3225 raster[2*stride+12+i] = tile3[8+i];
3226 }
3227
3228 for (i=0; i<4; i++) {
3229 raster[3*stride+i] = tile0[12+i];
3230 raster[3*stride+4+i] = tile1[12+i];
3231 raster[3*stride+8+i] = tile2[12+i];
3232 raster[3*stride+12+i] = tile3[12+i];
3233 }
3234 }
3235 #endif // #ifdef __ARM_NEON__
3236
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3237 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3238 {
3239 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3240 u32Id,
3241 E_TASK_PRI_MEDIUM,
3242 TRUE,
3243 NULL,
3244 32, // stack size..
3245 "HVD_PostProcess_task");
3246
3247 if (s32HvdPpTaskId < 0)
3248 {
3249 HVD_EX_MSG_ERR("Pp Task create failed\n");
3250
3251 return FALSE;
3252 }
3253
3254 HVD_EX_MSG_DBG("Pp Task create success\n");
3255 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3256
3257 return TRUE;
3258 }
3259
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3260 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3261 {
3262 return y * stride * h + x * w * h;
3263 }
3264
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3265 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3266 {
3267 return y * stride * h + x * w;
3268 }
3269
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3270 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3271 {
3272 raster[0] = tile[0];
3273 raster[1] = tile[1];
3274 raster[2] = tile[2];
3275 raster[3] = tile[3];
3276 raster[stride] = tile[4];
3277 raster[stride + 1] = tile[5];
3278 raster[stride + 2] = tile[6];
3279 raster[stride + 3] = tile[7];
3280 raster[2 * stride] = tile[8];
3281 raster[2 * stride + 1] = tile[9];
3282 raster[2 * stride + 2] = tile[10];
3283 raster[2 * stride + 3] = tile[11];
3284 raster[3 * stride] = tile[12];
3285 raster[3 * stride + 1] = tile[13];
3286 raster[3 * stride + 2] = tile[14];
3287 raster[3 * stride + 3] = tile[15];
3288 }
3289
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3290 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3291 {
3292 const MS_U32 tile_w = 4;
3293 const MS_U32 tile_h = 4;
3294 MS_U32 tile_stride = w;
3295 MS_U32 x, y;
3296 MS_U8 *dst1, *dst2;
3297 MS_U8 *src1, *src2;
3298
3299 #ifdef __ARM_NEON__
3300 // To overlap load and store, handle two blocks at the same time.
3301 dst1 = dst;
3302 src1 = src;
3303 for (y = 0; y < h / tile_h; y++)
3304 {
3305 dst2 = dst1;
3306 src2 = src1;
3307 for (x = 0; x <= (w/tile_w - 8); x+=8)
3308 {
3309 tile4x4_to_raster_8(
3310 dst2,
3311 src2,
3312 raster_stride, tile_w, tile_h);
3313 dst2 += tile_w * 8;
3314 src2 += tile_w * tile_h * 8;
3315 }
3316 dst1 += raster_stride * tile_h;
3317 src1 += tile_stride * tile_h;
3318 for (; x < w / tile_w; x++)
3319 {
3320 tile4x4_to_raster(
3321 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3322 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3323 raster_stride);
3324 }
3325 }
3326 #else
3327 dst1 = NULL;
3328 src1 = NULL;
3329 dst2 = NULL;
3330 src2 = NULL;
3331
3332 for (y = 0; y < h / tile_h; y++)
3333 {
3334 for (x = 0; x <= (w/tile_w - 4); x+=4)
3335 {
3336 tile4x4_to_raster_4(
3337 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3338 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3339 raster_stride);
3340 }
3341 for (; x < w / tile_w; x++)
3342 {
3343 tile4x4_to_raster(
3344 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3345 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3346 raster_stride);
3347 }
3348 }
3349 #endif
3350 }
3351
3352 #define FLUSH_CACHE_SIZE (256 * 1024)
3353
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3354 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3355 {
3356 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3357 if (u32Size > FLUSH_CACHE_SIZE)
3358 u32Size = FLUSH_CACHE_SIZE;
3359
3360 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3361 }
3362
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3363 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3364 {
3365 MS_U32 u32SkipSize = 0;
3366
3367 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3368 if (u32Size > FLUSH_CACHE_SIZE)
3369 {
3370 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3371 u32Size = FLUSH_CACHE_SIZE;
3372 }
3373
3374 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3375 }
3376
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3377 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3378 {
3379 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3380 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3381 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3382 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3383
3384 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3385
3386 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3387
3388 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3389 {
3390 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3391 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3392
3393 HVD_Delay_ms(1); // FIXME
3394
3395 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3396 continue;
3397
3398 HAL_HVD_EX_ReadMemory();
3399
3400 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3401 {
3402 MS_U8 *pSrcVA, *pDstVA;
3403 MS_U32 u32SrcPA, u32DstPA;
3404 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3405 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3406
3407 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3408 {
3409 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3410
3411 u16Width = pFrmInfo->u16Width;
3412 u16Height = pFrmInfo->u16Height;
3413 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3414 }
3415
3416 // Luma
3417 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3418 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3419
3420 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3421 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3422
3423 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3424 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3425
3426 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3427
3428 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3429
3430 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3431
3432 // Chroma
3433 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3434 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3435
3436 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3437 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3438
3439 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3440 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3441
3442 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3443
3444 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3445
3446 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3447
3448 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3449 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3450 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3451
3452 HAL_HVD_EX_FlushMemory();
3453
3454 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3455 break;
3456
3457 HAL_HVD_EX_ReadMemory();
3458 }
3459 }
3460
3461 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3462
3463 return TRUE;
3464 }
3465 #endif
3466
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3467 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3468 {
3469 #ifndef VDEC3
3470 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3471 #endif
3472 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3473 // MS_U8 u8MiuSel;
3474 // MS_U32 u32StartOffset;
3475
3476 #if SUPPORT_EVD
3477 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
3478 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3479 #if SUPPORT_MSVP9
3480 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3481 #endif
3482 #endif
3483 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
3484 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3485
3486 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3487 // re-setup clock.
3488 #if SUPPORT_G2VP9 && defined(VDEC3)
3489 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3490 #endif
3491
3492
3493 if (!HAL_VPU_EX_HVDInUsed())
3494 {
3495 printf("HVD power on\n");
3496 #ifdef CONFIG_MSTAR_CLKM
3497 MS_BOOL isHVD = (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) \
3498 || (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) \
3499 || (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) \
3500 || (E_HVD_INIT_HW_MVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) \
3501 || (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3502
3503 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
3504
3505 if(isHVD)
3506 {
3507 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_IDB, TRUE);
3508 }
3509
3510 if(E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3511 {
3512 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VP8, TRUE);
3513 }
3514 else if((E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
3515 (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) )
3516 {
3517 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_AEC, TRUE);
3518 }
3519 #else
3520 HAL_HVD_EX_PowerCtrl(TRUE);
3521 #endif
3522
3523 #ifdef CONFIG_MSTAR_SRAMPD
3524 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3525 HVD_Delay_ms(1);
3526 #endif
3527 }
3528
3529 #if SUPPORT_EVD
3530 if (isEVD) /// Disable it for disable H264 IMI
3531 {
3532 #ifdef VDEC3
3533 if (!HAL_VPU_EX_EVDInUsed())
3534 #endif
3535 {
3536 printf("EVD power on\n");
3537 HAL_EVD_EX_PowerCtrl(TRUE);
3538 }
3539 }
3540 #endif
3541
3542 #if SUPPORT_G2VP9 && defined(VDEC3)
3543 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3544 {
3545 if (!HAL_VPU_EX_G2VP9InUsed())
3546 {
3547 printf("G2 VP9 power on\n");
3548 HAL_VP9_EX_PowerCtrl(TRUE);
3549 }
3550 }
3551 #endif
3552
3553 if ((!HAL_VPU_EX_HVDInUsed()) )
3554 {
3555 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3556 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3557 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3558 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3559
3560 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3561
3562 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_128 , HVD_REG_RESET_MIU_128);
3563
3564 //BWA
3565 //_HVD_Write2Byte(HVD_REG_BWA_CLK, ((_HVD_Read2Byte(HVD_REG_BWA_CLK))&((~HVD_REG_CLK_HVD_SW_OV_EN & ~HVD_REG_CLK_HVD_IDB_SW_OV_EN))));
3566
3567 #if 0
3568 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3569 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3570 {
3571 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
3572
3573 _HAL_HVD_Entry();
3574 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3575 _HAL_HVD_Release();
3576
3577 }
3578 #endif
3579 }
3580
3581 #if SUPPORT_EVD
3582 if (isEVD)
3583 {
3584 #ifdef VDEC3
3585 if (!HAL_VPU_EX_EVDInUsed())
3586 #endif
3587 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3588 }
3589 #endif
3590
3591 #if SUPPORT_G2VP9 && defined(VDEC3)
3592 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3593 {
3594 if (!HAL_VPU_EX_G2VP9InUsed())
3595 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3596 }
3597 #endif
3598
3599
3600 if(pCtrl == NULL)
3601 {
3602 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3603 //return FALSE;
3604 goto RESET;
3605 }
3606
3607 #if SUPPORT_EVD
3608 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
3609 {
3610 #ifdef VDEC3
3611 if (!HAL_VPU_EX_EVDInUsed())
3612 #endif
3613 {
3614 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3615 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3616 }
3617
3618 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3619 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3620 {
3621 #ifdef VDEC3
3622 if (0 == pCtrl->u32BBUId)
3623 #else
3624 if (0 == u8TaskId)
3625 #endif
3626 {
3627 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3628 }
3629 else
3630 {
3631 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3632 }
3633
3634 }
3635 goto RESET;
3636 }
3637 #endif
3638
3639 // HVD4, from JANUS and later chip
3640 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3641 {
3642 case E_HVD_INIT_HW_AVS:
3643 {
3644 #ifdef VDEC3
3645 if (0 == pCtrl->u32BBUId)
3646 #else
3647 if (0 == u8TaskId)
3648 #endif
3649 {
3650 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3651 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3652 }
3653 else
3654 {
3655 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3656 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3657 }
3658
3659 break;
3660 }
3661 case E_HVD_INIT_HW_RM:
3662 {
3663 #ifdef VDEC3
3664 if (0 == pCtrl->u32BBUId)
3665 #else
3666 if (0 == u8TaskId)
3667 #endif
3668 {
3669 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3670 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3671
3672 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3673 {
3674 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3675 }
3676 else // RV 8
3677 {
3678 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3679 }
3680 }
3681 else
3682 {
3683 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3684 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3685
3686 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3687 {
3688 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3689 }
3690 else // RV 8
3691 {
3692 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3693 }
3694
3695 }
3696
3697 break;
3698 }
3699 default:
3700 {
3701 #ifdef VDEC3
3702 if (0 == pCtrl->u32BBUId)
3703 #else
3704 if (0 == u8TaskId)
3705 #endif
3706 {
3707 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3708 }
3709 else
3710 {
3711 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3712 }
3713 break;
3714 }
3715 }
3716
3717 RESET:
3718
3719 //T9: use miu128bit
3720 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3721
3722 if (!HAL_VPU_EX_HVDInUsed())
3723 {
3724 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3725 }
3726
3727 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3728
3729 #if SUPPORT_EVD
3730 if (isEVD)
3731 {
3732 #ifdef VDEC3
3733 if (!HAL_VPU_EX_EVDInUsed())
3734 #endif
3735 {
3736 printf("EVD miu 256 bits\n");
3737 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3738 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3739 _HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) & ~REG_CLK_EVD_SW_OV_EN & ~REG_CLK_EVD_PPU_SW_OV_EN));//set 0 firmware
3740 //_HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) | REG_CLK_EVD_SW_OV_EN | REG_CLK_EVD_PPU_SW_OV_EN));//set 1 driver
3741 printf("EVD BBU 256 bits\n");
3742 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) & ~REG_BBU_MIU_128));
3743 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) | REG_BBU_MIU_256));
3744 }
3745 }
3746 #endif
3747 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3748 // Only ES buffer addrress needs to be set for VP8
3749 _HVD_EX_SetESBufferAddr(u32Id);
3750 #else
3751 if(DecoderType != E_VPU_EX_DECODER_MVD)
3752 {
3753 _HVD_EX_SetBufferAddr(u32Id);
3754 }
3755 #endif
3756 if (!HAL_VPU_EX_HVDInUsed())
3757 {
3758 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3759 }
3760
3761 #if SUPPORT_EVD
3762 if (isEVD)
3763 {
3764 #ifdef VDEC3
3765 if (!HAL_VPU_EX_EVDInUsed())
3766 #endif
3767 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3768 }
3769 #endif
3770
3771 #if SUPPORT_G2VP9 && defined(VDEC3)
3772 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3773 {
3774 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3775
3776 if (!HAL_VPU_EX_G2VP9InUsed())
3777 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3778
3779 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3780 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3781 }
3782 #endif
3783
3784 return TRUE;
3785 }
3786
HAL_HVD_EX_DeinitHW(void)3787 MS_BOOL HAL_HVD_EX_DeinitHW(void)
3788 {
3789 MS_U16 u16Timeout = 1000;
3790
3791 _HVD_EX_SetMIUProtectMask(TRUE);
3792
3793 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
3794 HAL_EVD_EX_DeinitHW();
3795 #endif
3796
3797 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3798
3799 while (u16Timeout)
3800 {
3801 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3802 {
3803 break;
3804 }
3805 u16Timeout--;
3806 }
3807
3808 #ifdef CONFIG_MSTAR_CLKM
3809 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, FALSE);
3810 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_IDB, FALSE);
3811 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_AEC, FALSE);
3812 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VP8, FALSE);
3813 #else
3814 HAL_HVD_EX_PowerCtrl(FALSE);
3815 #endif
3816
3817 #ifdef CONFIG_MSTAR_SRAMPD
3818 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3819 HVD_Delay_ms(1);
3820 #endif
3821
3822 _HVD_EX_SetMIUProtectMask(FALSE);
3823
3824 return TRUE;
3825 }
3826
HAL_HVD_EX_FlushMemory(void)3827 void HAL_HVD_EX_FlushMemory(void)
3828 {
3829 MsOS_FlushMemory();
3830 }
3831
HAL_HVD_EX_ReadMemory(void)3832 void HAL_HVD_EX_ReadMemory(void)
3833 {
3834 MsOS_ReadMemory();
3835 }
3836
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3837 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3838 {
3839 _pHVDCtrls = pHVDCtrlsBase;
3840 }
3841
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3842 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3843 {
3844 return;
3845 }
3846
HAL_HVD_EX_GetHWVersionID(void)3847 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3848 {
3849 return _HVD_Read2Byte(HVD_REG_REV_ID);
3850 }
3851
3852
HAL_HVD_EX_Init_Share_Mem(void)3853 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3854 {
3855 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3856 #if !defined(SUPPORT_X_MODEL_FEATURE)
3857 MS_U32 u32ShmId;
3858 MS_VIRT u32Addr;
3859 MS_U32 u32BufSize;
3860
3861
3862 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3863 sizeof(HVD_Hal_CTX),
3864 &u32ShmId,
3865 &u32Addr,
3866 &u32BufSize,
3867 MSOS_SHM_QUERY))
3868 {
3869 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3870 sizeof(HVD_Hal_CTX),
3871 &u32ShmId,
3872 &u32Addr,
3873 &u32BufSize,
3874 MSOS_SHM_CREATE))
3875 {
3876 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3877 if(pHVDHalContext == NULL)
3878 {
3879 pHVDHalContext = &gHVDHalContext;
3880 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3881 _HVD_EX_Context_Init_HAL();
3882 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3883 }
3884 else
3885 {
3886 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3887 }
3888 //return FALSE;
3889 }
3890 else
3891 {
3892 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3893 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3894 _HVD_EX_Context_Init_HAL();
3895 }
3896 }
3897 else
3898 {
3899 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3900 }
3901 #else
3902 if(pHVDHalContext == NULL)
3903 {
3904 pHVDHalContext = &gHVDHalContext;
3905 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3906 _HVD_EX_Context_Init_HAL();
3907 }
3908 #endif
3909 _HAL_HVD_MutexCreate();
3910 #else
3911 if(pHVDHalContext == NULL)
3912 {
3913 pHVDHalContext = &gHVDHalContext;
3914 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3915 _HVD_EX_Context_Init_HAL();
3916 }
3917 #endif
3918
3919 return TRUE;
3920 }
3921
3922
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3923 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3924 {
3925 MS_U32 i = 0;
3926
3927 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3928 {
3929 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3930 return pHVDHalContext->_stHVDStream[0].eStreamId;
3931 }
3932 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3933 {
3934 for (i = 0;
3935 i <
3936 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3937 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3938 {
3939 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3940 {
3941 return pHVDHalContext->_stHVDStream[i].eStreamId;
3942 }
3943 }
3944 }
3945 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3946 {
3947 for (i = 0;
3948 i <
3949 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3950 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3951 {
3952 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3953 {
3954 return pHVDHalContext->_stHVDStream[i].eStreamId;
3955 }
3956 }
3957 }
3958 #ifdef VDEC3
3959 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3960 {
3961 i = eStreamType - E_HAL_HVD_N_STREAM;
3962 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3963 return pHVDHalContext->_stHVDStream[i].eStreamId;
3964 }
3965 #endif
3966
3967 return E_HAL_HVD_STREAM_NONE;
3968 }
3969
HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)3970 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)
3971 {
3972 if (bEnable)
3973 {
3974 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3975 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3976 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3977 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
3978 }
3979 else
3980 {
3981 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3982 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3983 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3984 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
3985 }
3986
3987 // fix to not inverse
3988 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
3989
3990 switch (pHVDHalContext->u32HVDClockType)
3991 {
3992 #if 0 //for overclocking
3993 case 432:
3994 {
3995 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
3996 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3997 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3998 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
3999 break;
4000 }
4001 #endif
4002 case 384:
4003 {
4004 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4005 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4006 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4007 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4008 break;
4009 }
4010 case 345:
4011 {
4012 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
4013 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4014 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4015 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4016 break;
4017 }
4018 case 320:
4019 {
4020 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
4021 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_345MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4022 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4023 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4024 break;
4025 }
4026 case 288:
4027 {
4028 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4029 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4030 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4031 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4032 break;
4033 }
4034 case 240:
4035 {
4036 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
4037 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4038 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4039 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4040 break;
4041 }
4042 case 216:
4043 {
4044 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
4045 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4046 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4047 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
4048 break;
4049 }
4050 case 172:
4051 {
4052 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
4053 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4054 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4055 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
4056 break;
4057 }
4058
4059 default:
4060 {
4061 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4062 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4063 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4064 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4065 break;
4066 }
4067 }
4068
4069 return;
4070 }
4071
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4072 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4073 {
4074 u32HVDRegOSBase = u32RegBase;
4075 HAL_VPU_EX_InitRegBase(u32RegBase);
4076 }
4077
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4078 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4079 {
4080 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4081 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4082 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4083 }
4084
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4085 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4086 {
4087 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4088 HVD_ShareMem *pShm = NULL;
4089 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4090 #if HVD_ENABLE_MVC
4091 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4092 #endif ///HVD_ENABLE_MVC
4093
4094 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4095 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4096 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4097 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4098 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4099 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = TRUE;
4100 int i;
4101 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4102 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4103 #if HVD_ENABLE_MVC
4104 if(bMVC)
4105 {
4106 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4107 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4108 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4109 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4110 }
4111 #endif ///HVD_ENABLE_MVC
4112
4113 // set a local copy of FW code address; assuming there is only one copy of FW,
4114 // no matter how many task will be created.
4115
4116 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4117
4118 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4119
4120 // global variables
4121 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4122
4123
4124 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4125 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4126 // Create mutex
4127 //_HAL_HVD_MutexCreate();
4128
4129 // fill HVD init variables
4130 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4131 {
4132 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4133 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4134 }
4135 else
4136 #if HVD_ENABLE_RV_FEATURE
4137 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4138 {
4139 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4140 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4141 #ifdef VDEC3_FB
4142 pHVDHalContext->u32RV_VLCTableAddr = 0;
4143 #else
4144 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4145 {
4146 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4147 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4148 }
4149 else
4150 {
4151 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4152 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4153 return E_HVD_RETURN_INVALID_PARAMETER;
4154 }
4155 #endif
4156 }
4157 else
4158 #endif
4159 {
4160 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4161 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4162 #if HVD_ENABLE_MVC
4163 if(bMVC)
4164 {
4165 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4166 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4167 }
4168 #endif /// HVD_ENABLE_MVC
4169 pHVDHalContext->u32RV_VLCTableAddr = 0;
4170 }
4171
4172 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4173 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4174 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4175 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4176 {
4177 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4178 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4179 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4180 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4181 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4182 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4183 #if HVD_ENABLE_MVC
4184 if(bMVC)
4185 {
4186 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4187 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4188 {
4189 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4190 }
4191 }
4192 #endif /// HVD_ENABLE_MVC
4193
4194 return E_HVD_RETURN_SUCCESS;
4195 }
4196 else
4197 {
4198 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4199 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
4200 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4201 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4202 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4203 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4204 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4205 return E_HVD_RETURN_INVALID_PARAMETER;
4206 }
4207 }
4208
4209 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4210 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4211 #else
4212 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4213 #endif
4214 {
4215 MS_U32 u32Addr = 0;
4216 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4217 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4218 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4219
4220 MS_U32 u32TmpStartOffset;
4221 MS_U8 u8TmpMiuSel;
4222
4223
4224 memset(pShm, 0, sizeof(HVD_ShareMem));
4225
4226 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4227
4228 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4229 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4230 #ifdef VDEC3
4231 if (bFWdecideFB || bCMAUsed)
4232 {
4233 pShm->u32FrameBufAddr = 0;
4234 pShm->u32FrameBufSize = 0;
4235 }
4236 else
4237 #endif
4238 {
4239 pShm->u32FrameBufAddr = u32Addr;
4240 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4241 }
4242
4243 // FIXME: need to use the avaliable task resource instead of using next task resource
4244 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
4245 pShm->u8ExternalHeapIdx = u8Idx + 1;
4246 else
4247 pShm->u8ExternalHeapIdx = 0xFF;
4248 pShm->DispInfo.u16DispWidth = 1;
4249 pShm->DispInfo.u16DispHeight = 1;
4250 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4251 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4252 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4253 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4254 //Chip info
4255 pShm->u16ChipID = E_MSTAR_CHIP_MOONEY;
4256 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4257 // PreSetControl
4258 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bOnePendingBuffer)
4259 {
4260 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4261 }
4262 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bVP94k2kCheck)
4263 {
4264 pShm->u32PreSetControl |= PRESET_VP9_4K2K_CHECK;
4265 }
4266 pShm->bUseTSPInBBUMode = FALSE;
4267
4268
4269 if ((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
4270 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4271 {
4272 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4273
4274 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
4275
4276 pShm->u32IapGnBufAddr = u32Addr;
4277 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufSize;
4278
4279 }
4280
4281 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4282 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4283 {
4284 case E_HVD_DEF_MFCODEC_DEFAULT:
4285 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4286 break;
4287 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4288 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4289 break;
4290 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4291 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4292 break;
4293 default:
4294 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4295 }
4296
4297 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4298 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
4299 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4300
4301 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4302 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4303 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4304 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4305 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4306 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4307
4308 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4309 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4310 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4311 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4312 else
4313 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4314 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4315 {
4316 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4317 {
4318 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4319 }
4320 else
4321 {
4322 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4323 }
4324 }
4325 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4326 {
4327 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4328 {
4329 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4330 }
4331 else
4332 {
4333 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4334 }
4335 }
4336 else
4337 {
4338 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4339 }
4340
4341 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4342 {
4343 pShm->bHVDIMIEnable = TRUE; //AVC FW enable IMI only for 4k2k
4344 }
4345
4346 #if 0
4347 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
4348 {
4349 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
4350 }
4351 #endif
4352
4353 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4354 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4355 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4356 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4357 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4358 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4359 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4360 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4361 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4362 {
4363 pShm->bUseWbMvop = 1;
4364 }
4365
4366 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
4367 /*|| E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)*/)
4368 {
4369 if(!(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & E_HVD_DEF_FEATURE_DISABLE_TEMPORAL_SCALABILITY))
4370 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
4371 }
4372
4373 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4374
4375 #if (VPU_FORCE_MIU_MODE)
4376 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4377
4378 pShm->u32FWBaseAddr = u32TmpStartOffset;
4379
4380 #else
4381 ///TODO:
4382 /*
4383 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4384
4385 if(u8TmpMiuSel == E_CHIP_MIU_0)
4386 {
4387 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4388 }
4389 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4390 {
4391 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4392 }
4393 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4394 {
4395 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4396 }
4397 */
4398 #endif
4399 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4400 #else
4401 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4402 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4403 {
4404 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4405 }
4406 pShm->u32FWBaseAddr = u32Addr;
4407 #endif
4408
4409 // RM only
4410 #if HVD_ENABLE_RV_FEATURE
4411 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4412 && (pCtrl->InitParams.pRVFileInfo != NULL))
4413 {
4414 MS_U32 i = 0;
4415
4416 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4417 {
4418 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4419 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4420 }
4421
4422 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4423 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4424 #ifdef VDEC3_FB
4425 pShm->u32RM_VLCTableAddr = 0;
4426 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4427 #else
4428 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4429
4430 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4431 u32Addr = u32TmpStartOffset;
4432
4433 pShm->u32RM_VLCTableAddr = u32Addr;
4434 #endif
4435 }
4436 #endif
4437
4438 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4439 && (pCtrl->InitParams.pRVFileInfo != NULL))
4440 {
4441 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4442 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4443 }
4444
4445 //if(pCtrl->InitParams.bColocateBBUMode)
4446 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4447 {
4448 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4449 }
4450
4451 #if SUPPORT_G2VP9
4452 // Enable SW detile support for G2 VP9
4453 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4454 {
4455 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4456 }
4457 #endif
4458
4459 HAL_HVD_EX_FlushMemory();
4460
4461 return E_HVD_RETURN_SUCCESS;
4462 }
4463 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4464 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4465 #else
4466 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4467 #endif
4468 {
4469 MS_BOOL bInitRet = FALSE;
4470
4471 #if 0
4472 // check MVD power on
4473 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4474 {
4475 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4476 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4477 HVD_Delay_ms(1);
4478 }
4479 // Check VPU power on
4480 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4481 {
4482 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4483 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4484 HVD_Delay_ms(1);
4485 }
4486 // check HVD power on
4487 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4488 {
4489 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4490 HAL_HVD_EX_PowerCtrl(TRUE);
4491 HVD_Delay_ms(1);
4492 }
4493 #endif
4494 #ifdef VDEC3
4495 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4496 #else
4497 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4498 #endif
4499 if (!bInitRet)
4500 {
4501 return E_HVD_RETURN_FAIL;
4502 }
4503
4504 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4505
4506 if (!bInitRet)
4507 {
4508 return E_HVD_RETURN_FAIL;
4509 }
4510
4511 return E_HVD_RETURN_SUCCESS;
4512 }
4513
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4514 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4515 {
4516 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4517
4518 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4519
4520 return E_HVD_RETURN_SUCCESS;
4521 }
4522
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4523 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4524 {
4525 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4526 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4527 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4528 MS_BOOL bMVC = FALSE;
4529 #if HVD_ENABLE_MVC
4530 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4531 #endif
4532
4533 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4534 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4535
4536 switch (u32type)
4537 {
4538 // share memory
4539 // switch
4540 case E_HVD_SDATA_FRAMEBUF_ADDR:
4541 {
4542 pShm->u32FrameBufAddr = u32Data;
4543 break;
4544 }
4545 case E_HVD_SDATA_FRAMEBUF_SIZE:
4546 {
4547 pShm->u32FrameBufSize = u32Data;
4548 break;
4549 }
4550 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4551 {
4552 pShm->u32FrameBuf2Addr = u32Data;
4553 break;
4554 }
4555 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4556 {
4557 pShm->u32FrameBuf2Size = u32Data;
4558 break;
4559 }
4560 case E_HVD_SDATA_MAX_CMA_SIZE:
4561 {
4562 pShm->u32MaxCMAFrameBufSize = u32Data;
4563 break;
4564 }
4565 case E_HVD_SDATA_MAX_CMA_SIZE2:
4566 {
4567 pShm->u32MaxCMAFrameBuf2Size = u32Data;
4568 break;
4569 }
4570 case E_HVD_SDATA_CMA_USED:
4571 {
4572 pShm->bCMA_Use = u32Data;
4573 break;
4574 }
4575 case E_HVD_SDATA_CMA_ALLOC_DONE:
4576 {
4577 pShm->bCMA_AllocDone = u32Data;
4578 break;
4579 }
4580 case E_HVD_SDATA_CMA_TWO_MIU:
4581 {
4582 pShm->bCMA_TwoMIU = u32Data;
4583 break;
4584 }
4585 case E_HVD_SDATA_RM_PICTURE_SIZES:
4586 {
4587 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4588 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4589 break;
4590 }
4591 case E_HVD_SDATA_ERROR_CODE:
4592 {
4593 pShm->u16ErrCode = (MS_U16) u32Data;
4594 break;
4595 }
4596 case E_HVD_SDATA_DISP_INFO_TH:
4597 {
4598 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4599 sizeof(HVD_DISP_THRESHOLD));
4600 break;
4601 }
4602 case E_HVD_SDATA_FW_FLUSH_STATUS:
4603 {
4604 pShm->u8FlushStatus = (MS_U8)u32Data;
4605 break;
4606 }
4607 case E_HVD_SDATA_DMX_FRAMERATE:
4608 {
4609 pShm->u32DmxFrameRate = u32Data;
4610 break;
4611 }
4612 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4613 {
4614 pShm->u32DmxFrameRateBase = u32Data;
4615 break;
4616 }
4617 case E_HVD_SDATA_MIU_SEL:
4618 {
4619 pShm->u32VDEC_MIU_SEL = u32Data;
4620 break;
4621 }
4622 case E_HVD_SDATA_DV_XC_SHM_SIZE:
4623 {
4624 pShm->u32DolbyVisionXCShmSize = u32Data;
4625 break;
4626 }
4627 // SRAM
4628
4629 // Mailbox
4630 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4631 {
4632 if (u32Data != 0)
4633 {
4634 pShm->bEnableDispCtrl = TRUE;
4635 pShm->bIsTrigDisp = TRUE;
4636 }
4637 else
4638 {
4639 pShm->bEnableDispCtrl = FALSE;
4640 }
4641
4642 break;
4643 }
4644 case E_HVD_SDATA_GET_DISP_INFO_START:
4645 {
4646 pShm->bSpsChange = FALSE;
4647 break;
4648 }
4649 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4650 {
4651 pShm->u32VirtualBoxWidth = u32Data;
4652 break;
4653 }
4654 case E_HVD_SDATA_DV_INFO:
4655 {
4656 MS_U8 u8DVLevel = u32Data & 0x00ff;
4657 MS_U8 u8DVProfile = (u32Data >> 8) & 0x00ff;
4658
4659 pShm->u8DVLevelFromDriverAPI = u8DVLevel;
4660 pShm->u8DVProfileFromDriverAPI = u8DVProfile;
4661 break;
4662 }
4663 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4664 {
4665 pShm->u32VirtualBoxHeight = u32Data;
4666 break;
4667 }
4668 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4669 {
4670 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4671 {
4672 //printf("DispFrame DqPtr: %d\n", u32Data);
4673 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4674 }
4675 break;
4676 }
4677 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4678 {
4679 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4680 {
4681 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4682 {
4683 //printf("DispFrame DqPtr: %ld\n", u32Data);
4684 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4685 }
4686 }
4687 break;
4688 }
4689 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4690 {
4691 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4692 {
4693 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
4694 {
4695 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4696 {
4697 //ALOGE("R1: %x", u32Data);
4698 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4699 }
4700 else
4701 {
4702 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4703 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4704 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4705 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4706 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4707 }
4708 }
4709 else
4710 {
4711 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4712 }
4713 }
4714 else
4715 {
4716 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4717 {
4718 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4719 }
4720 }
4721 break;
4722 }
4723 #if (HVD_ENABLE_IQMEM)
4724 case E_HVD_SDATA_FW_IQMEM_CTRL:
4725 {
4726 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4727 break;
4728
4729 }
4730 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4731 {
4732 if (u32Data != 0)
4733 {
4734 pShm->bIQmemEnableIfSupport= TRUE;
4735 }
4736 else
4737 {
4738 pShm->bIQmemEnableIfSupport= FALSE;
4739 }
4740
4741
4742 break;
4743
4744 }
4745 #endif
4746
4747 default:
4748 break;
4749 }
4750
4751 HAL_HVD_EX_FlushMemory();
4752
4753 return eRet;
4754 }
4755
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4756 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4757 {
4758 MS_S64 s64Ret = 0;
4759 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4760
4761 HAL_HVD_EX_ReadMemory();
4762
4763 switch (eType)
4764 {
4765 case E_HVD_GDATA_PTS_STC_DIFF:
4766 s64Ret = pShm->s64PtsStcDiff;
4767 break;
4768 default:
4769 break;
4770 }
4771
4772 return s64Ret;
4773 }
4774
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4775 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4776 {
4777 MS_VIRT u32Ret = 0;
4778 //static MS_U64 u64pts_real = 0;
4779 MS_U64 u64pts_low = 0;
4780 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4781 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4782
4783 HAL_HVD_EX_ReadMemory();
4784
4785 if(pShm == NULL)
4786 {
4787 printf("########## VDEC patch for Debug ###########\n");
4788 return 0x0;
4789 }
4790
4791 switch (eType)
4792 {
4793 // share memory
4794 // switch
4795 case E_HVD_GDATA_DISP_INFO_ADDR:
4796 {
4797 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4798 break;
4799 }
4800 case E_HVD_GDATA_MIU_SEL:
4801 u32Ret = pShm->u32VDEC_MIU_SEL;
4802 break;
4803 case E_HVD_GDATA_FRAMEBUF_ADDR:
4804 u32Ret = pShm->u32FrameBufAddr;
4805 break;
4806 case E_HVD_GDATA_FRAMEBUF_SIZE:
4807 u32Ret = pShm->u32FrameBufSize;
4808 break;
4809 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4810 u32Ret = pShm->u32FrameBuf2Addr;
4811 break;
4812 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4813 u32Ret = pShm->u32FrameBuf2Size;
4814 break;
4815 case E_HVD_GDATA_CMA_ALLOC_DONE:
4816 u32Ret = pShm->bCMA_AllocDone;
4817 break;
4818 case E_HVD_GDATA_CMA_USED:
4819 u32Ret = pShm->bCMA_Use;
4820 break;
4821 // report
4822 case E_HVD_GDATA_PTS:
4823 {
4824 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
4825 break;
4826 }
4827 case E_HVD_GDATA_U64PTS:
4828 {
4829 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
4830 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
4831 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4832 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4833 break;
4834 }
4835 case E_HVD_GDATA_U64PTS_PRE_PARSE:
4836 {
4837 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
4838 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
4839 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4840 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4841 break;
4842 }
4843 case E_HVD_GDATA_DECODE_CNT:
4844 {
4845 u32Ret = pShm->u32DecodeCnt;
4846 break;
4847 }
4848 case E_HVD_GDATA_DATA_ERROR_CNT:
4849 {
4850 u32Ret = pShm->u32DataErrCnt;
4851 break;
4852 }
4853 case E_HVD_GDATA_DEC_ERROR_CNT:
4854 {
4855 u32Ret = pShm->u32DecErrCnt;
4856 break;
4857 }
4858 case E_HVD_GDATA_ERROR_CODE:
4859 {
4860 u32Ret = (MS_U32) (pShm->u16ErrCode);
4861 break;
4862 }
4863 case E_HVD_GDATA_VPU_IDLE_CNT:
4864 {
4865 u32Ret = pShm->u32VPUIdleCnt;
4866 break;
4867 }
4868 case E_HVD_GDATA_DISP_FRM_INFO:
4869 {
4870 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
4871 break;
4872 }
4873 case E_HVD_GDATA_DEC_FRM_INFO:
4874 {
4875 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
4876 break;
4877 }
4878 case E_HVD_GDATA_ES_LEVEL:
4879 {
4880 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
4881 break;
4882 }
4883 #if HVD_ENABLE_MVC
4884 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
4885 {
4886 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
4887 break;
4888 }
4889 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
4890 {
4891 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
4892 break;
4893 }
4894 #endif
4895
4896 // user data
4897 case E_HVD_GDATA_USERDATA_WPTR:
4898 {
4899 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
4900 break;
4901 }
4902 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
4903 {
4904 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
4905 break;
4906 }
4907 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
4908 {
4909 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
4910 break;
4911 }
4912 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
4913 {
4914 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
4915 break;
4916 }
4917 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
4918 {
4919 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
4920 break;
4921 }
4922 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
4923 {
4924 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
4925 break;
4926 }
4927 // report - modes
4928 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
4929 {
4930 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
4931 break;
4932 }
4933 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
4934 {
4935 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
4936 break;
4937 }
4938 case E_HVD_GDATA_IS_ERR_CONCEAL:
4939 {
4940 u32Ret = pShm->ModeStatus.bIsErrConceal;
4941 break;
4942 }
4943 case E_HVD_GDATA_IS_SYNC_ON:
4944 {
4945 u32Ret = pShm->ModeStatus.bIsSyncOn;
4946 break;
4947 }
4948 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
4949 {
4950 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
4951 break;
4952 }
4953 case E_HVD_GDATA_SYNC_MODE:
4954 {
4955 u32Ret = pShm->ModeStatus.u8SyncType;
4956 break;
4957 }
4958 case E_HVD_GDATA_SKIP_MODE:
4959 {
4960 u32Ret = pShm->ModeStatus.u8SkipMode;
4961 break;
4962 }
4963 case E_HVD_GDATA_DROP_MODE:
4964 {
4965 u32Ret = pShm->ModeStatus.u8DropMode;
4966 break;
4967 }
4968 case E_HVD_GDATA_DISPLAY_DURATION:
4969 {
4970 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
4971 break;
4972 }
4973 case E_HVD_GDATA_FRC_MODE:
4974 {
4975 u32Ret = pShm->ModeStatus.u8FrcMode;
4976 break;
4977 }
4978 case E_HVD_GDATA_NEXT_PTS:
4979 {
4980 u32Ret = pShm->u32NextPTS;
4981 break;
4982 }
4983 case E_HVD_GDATA_DISP_Q_SIZE:
4984 {
4985 u32Ret = pShm->u16DispQSize;
4986 break;
4987 }
4988 case E_HVD_GDATA_DISP_Q_PTR:
4989 {
4990 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
4991 break;
4992 }
4993 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
4994 {
4995 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
4996 break;
4997 }
4998 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
4999 {
5000 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
5001 break;
5002 }
5003 case E_HVD_GDATA_REAL_FRAMERATE:
5004 {
5005 // return VPS/VUI timing info framerate, and 0 if timing info not exist
5006 u32Ret = pShm->u32RealFrameRate;
5007 break;
5008 }
5009 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
5010 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
5011 break;
5012 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
5013 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
5014 break;
5015 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
5016 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
5017 break;
5018 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
5019 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
5020 break;
5021 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
5022 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
5023 break;
5024 case E_HVD_GDATA_FW_STATUS_FLAG:
5025 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
5026 break;
5027
5028 // internal control
5029 case E_HVD_GDATA_IS_1ST_FRM_RDY:
5030 {
5031 u32Ret = pShm->bIs1stFrameRdy;
5032 break;
5033 }
5034 case E_HVD_GDATA_IS_I_FRM_FOUND:
5035 {
5036 u32Ret = pShm->bIsIFrmFound;
5037 break;
5038 }
5039 case E_HVD_GDATA_IS_SYNC_START:
5040 {
5041 u32Ret = pShm->bIsSyncStart;
5042 break;
5043 }
5044 case E_HVD_GDATA_IS_SYNC_REACH:
5045 {
5046 u32Ret = pShm->bIsSyncReach;
5047 break;
5048 }
5049 case E_HVD_GDATA_FW_VERSION_ID:
5050 {
5051 u32Ret = pShm->u32FWVersionID;
5052 break;
5053 }
5054 case E_HVD_GDATA_FW_IF_VERSION_ID:
5055 {
5056 u32Ret = pShm->u32FWIfVersionID;
5057 break;
5058 }
5059 case E_HVD_GDATA_BBU_Q_NUMB:
5060 {
5061 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
5062 break;
5063 }
5064 case E_HVD_GDATA_DEC_Q_NUMB:
5065 {
5066 u32Ret = pShm->u16DecQNumb;
5067 break;
5068 }
5069 case E_HVD_GDATA_DISP_Q_NUMB:
5070 {
5071 u32Ret = pShm->u16DispQNumb;
5072 break;
5073 }
5074 case E_HVD_GDATA_PTS_Q_NUMB:
5075 {
5076 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
5077 break;
5078 }
5079 case E_HVD_GDATA_FW_INIT_DONE:
5080 {
5081 u32Ret = pShm->bInitDone;
5082 break;
5083 }
5084 // debug
5085 case E_HVD_GDATA_SKIP_CNT:
5086 {
5087 u32Ret = pShm->u32SkipCnt;
5088 break;
5089 }
5090 case E_HVD_GDATA_GOP_CNT:
5091 {
5092 u32Ret = pShm->u32DropCnt;
5093 break;
5094 }
5095 case E_HVD_GDATA_DISP_CNT:
5096 {
5097 u32Ret = pShm->u32DispCnt;
5098 break;
5099 }
5100 case E_HVD_GDATA_DROP_CNT:
5101 {
5102 u32Ret = pShm->u32DropCnt;
5103 break;
5104 }
5105 case E_HVD_GDATA_DISP_STC:
5106 {
5107 u32Ret = pShm->u32DispSTC;
5108 break;
5109 }
5110 case E_HVD_GDATA_VSYNC_CNT:
5111 {
5112 u32Ret = pShm->u32VsyncCnt;
5113 break;
5114 }
5115 case E_HVD_GDATA_MAIN_LOOP_CNT:
5116 {
5117 u32Ret = pShm->u32MainLoopCnt;
5118 break;
5119 }
5120
5121 // AVC
5122 case E_HVD_GDATA_AVC_LEVEL_IDC:
5123 {
5124 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5125 break;
5126 }
5127 case E_HVD_GDATA_AVC_LOW_DELAY:
5128 {
5129 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5130 break;
5131 }
5132 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5133 {
5134 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5135 break;
5136 }
5137 case E_HVD_GDATA_FW_FLUSH_STATUS:
5138 {
5139 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5140 break;
5141 }
5142 case E_HVD_GDATA_FW_CODEC_TYPE:
5143 {
5144 u32Ret = pShm->u32CodecType;
5145 break;
5146 }
5147 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5148 {
5149 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5150 break;
5151 }
5152 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5153 {
5154 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5155 {
5156 u32Ret = 1;
5157 }
5158 else
5159 {
5160 u32Ret = 0;
5161 }
5162 break;
5163 }
5164
5165 // SRAM
5166
5167 // Mailbox
5168 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5169 {
5170 u32Ret = pShm->u32FwState;
5171 break;
5172 }
5173 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5174 {
5175 u32Ret = pShm->bSpsChange;
5176 break;
5177 }
5178 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5179 {
5180 u32Ret = pShm->bSpsChange;
5181
5182 if (pShm->bSpsChange &&
5183 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5184 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5185 {
5186 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5187 }
5188
5189 break;
5190 }
5191 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5192 {
5193 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5194
5195 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5196 {
5197 u32Ret = pShm->u32FwInfo;
5198 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5199 }
5200 break;
5201 }
5202 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5203 {
5204 if (pShm->bIsTrigDisp) // not clear yet
5205 {
5206 u32Ret = FALSE;
5207 }
5208 else
5209 {
5210 u32Ret = TRUE;
5211 }
5212 break;
5213 }
5214 case E_HVD_GDATA_ES_READ_PTR:
5215 {
5216 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5217 break;
5218 }
5219 case E_HVD_GDATA_ES_WRITE_PTR:
5220 {
5221 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5222 break;
5223 }
5224 case E_HVD_GDATA_BBU_READ_PTR:
5225 {
5226 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5227 break;
5228 }
5229 case E_HVD_GDATA_BBU_WRITE_PTR:
5230 {
5231 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5232 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5233 {
5234 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5235 }
5236 else
5237 {
5238 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5239 }
5240 break;
5241 }
5242 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5243 {
5244 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5245
5246 u32Ret = pCtrl->u32BBUWptr_Fired;
5247
5248 break;
5249 }
5250 case E_HVD_GDATA_VPU_PC_CNT:
5251 {
5252 u32Ret = _HVD_EX_GetPC();
5253 break;
5254 }
5255 case E_HVD_GDATA_ES_QUANTITY:
5256 {
5257 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5258 break;
5259 }
5260
5261
5262 // FW def
5263 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5264 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5265 break;
5266
5267 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5268 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5269 break;
5270 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5271 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5272 break;
5273 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5274 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5275 break;
5276 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5277 u32Ret = MAX_PTS_TABLE_SIZE;
5278 break;
5279 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5280 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5281 break;
5282 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5283 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5284 break;
5285 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5286 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5287 break;
5288 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5289 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5290 break;
5291 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5292 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5293 break;
5294 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5295 {
5296 if (pShm->bDSIsRunning)
5297 {
5298 u32Ret = TRUE;
5299 }
5300 else
5301 {
5302 u32Ret = FALSE;
5303 }
5304 break;
5305 }
5306 #if (HVD_ENABLE_IQMEM)
5307 case E_HVD_GDATA_FW_IQMEM_CTRL:
5308 {
5309
5310 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5311
5312 break;
5313 }
5314 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5315 {
5316 if(pShm->bIsIQMEMSupport){
5317 u32Ret = TRUE;
5318 }
5319 else{
5320
5321 u32Ret = FALSE;
5322 }
5323
5324 break;
5325 }
5326 #endif
5327 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5328 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5329 break;
5330 case E_HVD_GDATA_FIELD_PIC_FLAG:
5331 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5332 break;
5333 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5334 u32Ret = pShm->u32SeamlessTSStatus;
5335 break;
5336 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5337 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5338 break;
5339 #ifdef VDEC3
5340 case E_HVD_GDATA_FW_VBBU_ADDR:
5341 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5342 break;
5343 #endif
5344 case E_HVD_GDATA_SEQ_CHANGE_INFO:
5345 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
5346 break;
5347 default:
5348 break;
5349 }
5350 return u32Ret;
5351 }
5352
HAL_HVD_EX_GetDVSupportProfiles(void)5353 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
5354 {
5355 //chip dependent, mooney doesn't support any DV profile
5356 #if 0 // wait avc finish DV dual job
5357 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5358 #else
5359 return E_DV_STREAM_PROFILE_ID_UNSUPPORTED;
5360 #endif
5361 }
5362
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)5363 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
5364 {
5365 //mooney doesn't support any DV profile
5366 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5367 /*
5368 switch (u32DV_Stream_Profile)
5369 {
5370 #if 0 // wait avc finish DV dual job
5371 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
5372 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
5373 #endif
5374
5375 #if 0 // unsupported profile
5376 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
5377 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5378 #endif
5379
5380 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
5381 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5382
5383 #if 0 // unsupported profile
5384 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
5385 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5386 #endif
5387
5388 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
5389 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5390
5391 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
5392 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5393
5394 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
5395 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5396
5397 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
5398 default:
5399 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5400 }
5401 */
5402 }
5403
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5404 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5405 {
5406 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5407 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5408 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5409
5410 _HAL_HVD_Entry();
5411
5412 // check if old SVD cmds
5413 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5414 {
5415 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5416
5417 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5418 }
5419
5420 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5421 {
5422 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5423 }
5424
5425 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5426 {
5427 if (u32Cmd == E_HVD_CMD_FLUSH)
5428 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5429 }
5430
5431 if (u32Cmd == E_HVD_CMD_FLUSH &&
5432 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5433 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5434 {
5435 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5436 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5437 {
5438 _HAL_HVD_Release();
5439 HVD_Delay_ms(1);
5440 _HAL_HVD_Entry();
5441 }
5442 }
5443
5444 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5445
5446 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5447
5448 _HAL_HVD_Return(eRet);
5449 }
5450
HAL_HVD_EX_DeInit(MS_U32 u32Id)5451 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5452 {
5453 HVD_Return eRet = E_HVD_RETURN_FAIL;
5454 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5455 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5456 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5457 MS_U8 u8MiuSel;
5458 MS_U32 u32StartOffset;
5459 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5460
5461 #if HVD_ENABLE_TIME_MEASURE
5462 MS_U32 ExitTimeCnt = 0;
5463 ExitTimeCnt = HVD_GetSysTime_ms();
5464 #endif
5465
5466 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5467
5468 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5469
5470 if (E_HVD_RETURN_SUCCESS != eRet)
5471 {
5472 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5473 }
5474
5475 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5476
5477 if (E_HVD_RETURN_SUCCESS != eRet)
5478 {
5479 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5480 }
5481
5482 // check FW state to make sure it's STOP DONE
5483 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5484 {
5485 if (HVD_GetSysTime_ms() > u32Timeout)
5486 {
5487 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5488
5489 //return E_HVD_RETURN_TIMEOUT;
5490 eRet = E_HVD_RETURN_TIMEOUT;
5491 break;
5492 }
5493 }
5494
5495 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
5496 {
5497 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
5498 pShm->u8VdecPlusDropRatio,
5499 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5500 pShm->u32VdecPlusDropCnt,
5501 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5502 pShm->u32VdecPlusDecCnt,
5503 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
5504 }
5505 else
5506 {
5507 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
5508 pShm->u8VdecPlusDropRatio,
5509 pShm->u32VdecPlusDropCnt,
5510 pShm->u32VdecPlusDecCnt,
5511 pShm->u32VdecPlusDispPicCnt);
5512 }
5513
5514 VPU_EX_FWCodeCfg fwCfg;
5515 VPU_EX_TaskInfo taskInfo;
5516 VPU_EX_NDecInitPara nDecInitPara;
5517
5518 nDecInitPara.pFWCodeCfg = &fwCfg;
5519 nDecInitPara.pTaskInfo = &taskInfo;
5520
5521 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5522 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5523
5524 taskInfo.u32Id = u32Id;
5525 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5526 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5527
5528 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5529 {
5530 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5531 }
5532 else
5533 {
5534 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5535 }
5536
5537 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5538 {
5539 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5540 }
5541
5542 /* clear es buffer */
5543 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5544 {
5545 //printf("Clear ES buffer\n");
5546
5547 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5548 }
5549
5550 //_HAL_HVD_MutexDelete();
5551
5552 #if HVD_ENABLE_TIME_MEASURE
5553 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5554 #endif
5555
5556 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5557 #ifndef VDEC3
5558 // reset bbu wptr
5559 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5560 {
5561 if(TRUE == HAL_VPU_EX_HVDInUsed())
5562 {
5563 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5564 {
5565 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5566 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5567 }
5568 else
5569 {
5570 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5571 {
5572 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5573 }
5574 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5575 }
5576 }
5577 else
5578 {
5579 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5580 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5581 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5582 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5583 {
5584 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5585 {
5586 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5587 }
5588 }
5589 else
5590 {
5591 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5592 }
5593 }
5594 }
5595 #endif
5596 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5597
5598 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5599 {
5600 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5601 }
5602
5603 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5604 {
5605
5606 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5607
5608 _HAL_HVD_Entry();
5609 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5610 _HAL_HVD_Release();
5611
5612 }
5613
5614 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
5615 HVD_EX_MSG_DBG("success\n");
5616
5617 return eRet;
5618 }
5619
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5620 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5621 {
5622 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5623 MS_U32 u32Addr = 0;
5624 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5625 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5626
5627 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5628
5629 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5630 {
5631 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5632
5633 if (E_HVD_RETURN_SUCCESS != eRet)
5634 {
5635 return eRet;
5636 }
5637 }
5638
5639 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5640
5641 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5642 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5643 {
5644 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5645
5646 if (E_HVD_RETURN_SUCCESS != eRet)
5647 {
5648 return eRet;
5649 }
5650 }
5651
5652 u32Addr = pInfo->u32Staddr;
5653
5654 if (pInfo->bRVBrokenPacket)
5655 {
5656 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5657 }
5658
5659 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5660 {
5661 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5662 }
5663 else
5664 {
5665 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5666 }
5667
5668 if (E_HVD_RETURN_SUCCESS != eRet)
5669 {
5670 return eRet;
5671 }
5672
5673 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5674 {
5675 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5676 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5677
5678 if (E_HVD_RETURN_SUCCESS != eRet)
5679 {
5680 return eRet;
5681 }
5682 }
5683
5684 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5685
5686 // do not add local pointer
5687 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5688 {
5689 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5690
5691 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5692 (u32PacketStAddr <
5693 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5694 {
5695 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5696 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5697 }
5698 else
5699 {
5700 //null packet
5701 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5702 pCtrl->LastNal.u32NalSize = 0;
5703 }
5704 }
5705 else
5706 {
5707 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5708 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5709 }
5710
5711 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5712 pCtrl->u32BBUPacketCnt++;
5713
5714 return eRet;
5715 }
5716
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5717 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5718 {
5719 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5720 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5721 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5722 if(bCurrentStatus == bEnable)
5723 return;
5724
5725 if (bEnable)
5726 {
5727 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5728 }
5729 else
5730 {
5731 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5732 }
5733 }
5734
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5735 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5736 {
5737 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5738 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5739
5740 if (bEnable)
5741 {
5742 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5743 }
5744 else
5745 {
5746 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5747 }
5748 }
5749
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5750 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5751 {
5752 MS_U32 u32RB = 0;
5753 switch(eISRType)
5754 {
5755 case E_HWDEC_ISR_HVD:
5756 u32RB = REG_HVD_BASE;
5757 break;
5758 #if SUPPORT_EVD
5759 case E_HWDEC_ISR_EVD:
5760 u32RB = REG_EVD_BASE;
5761 break;
5762 #endif
5763 #if SUPPORT_G2VP9
5764 case E_HWDEC_ISR_G2VP9:
5765 break;
5766 #endif
5767 default:
5768 break;
5769 }
5770 if(u32RB)
5771 {
5772 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5773 }
5774 }
5775
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5776 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5777 {
5778 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5779 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5780
5781 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5782 }
5783
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5784 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5785 {
5786 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5787 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5788
5789 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5790 {
5791 return FALSE;
5792 }
5793 else
5794 {
5795 return TRUE;
5796 }
5797 }
5798
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5799 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5800 {
5801 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5802
5803 if (pCtrl)
5804 {
5805 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5806 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5807 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5808 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5809 {
5810 return FALSE;
5811 }
5812 else
5813 {
5814 return TRUE;
5815 }
5816 }
5817 else
5818 {
5819 return FALSE;
5820 }
5821 }
5822
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5823 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5824 {
5825 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5826 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5827 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5828
5829 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5830 {
5831 HAL_HVD_EX_ReadMemory();
5832
5833 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5834 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5835
5836 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
5837 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
5838 }
5839
5840 return TRUE;
5841 }
5842
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)5843 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
5844 {
5845 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5846 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5847 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5848 MS_U32 u32Data;
5849 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5850
5851 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
5852
5853 HAL_HVD_EX_FlushMemory();
5854 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5855 {
5856 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5857 pCtrl->LastNal.u32NalAddr = u32Data;
5858 pCtrl->LastNal.u32NalSize = 0;
5859 }
5860
5861 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5862 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
5863
5864 return TRUE;
5865 }
5866
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)5867 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
5868 {
5869 if (bEnable)
5870 {
5871 if (HAL_VPU_EX_IsEVDR2())
5872 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5873 else
5874 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
5875 }
5876 else
5877 {
5878 #if defined (__aeon__)
5879 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5880 #else // defined (__mips__)
5881 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
5882 #endif
5883 }
5884 }
5885
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)5886 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
5887 {
5888 return 0;
5889 }
5890
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)5891 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
5892 {
5893 return;
5894 }
5895
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)5896 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
5897 {
5898 //if( u16Clock == 0 )
5899 return 216; //140;
5900 //if( )
5901 }
5902
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)5903 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
5904 {
5905 //MS_BOOL bBitMIU1 = FALSE;
5906 //MS_BOOL bCodeMIU1 = FALSE;
5907 MS_U8 u8BitMiuSel = 0;
5908 MS_U8 u8CodeMiuSel = 0;
5909 MS_U32 u32BitStartOffset;
5910 MS_U32 u32CodeStartOffset;
5911 //MS_U8 u8MiuSel;
5912 //MS_U32 u32StartOffset;
5913 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5914 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5915 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5916 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
5917
5918 #if HVD_ENABLE_MVC
5919 if(HAL_HVD_EX_CheckMVCID(u32Id))
5920 {
5921 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
5922 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
5923 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
5924 {
5925 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
5926 }
5927 }
5928 #endif /// HVD_ENABLE_MVC
5929
5930 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
5931 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5932
5933
5934
5935
5936 if (u8BitMiuSel != u8CodeMiuSel)
5937 {
5938 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
5939 BDMA_Result bdmaRlt;
5940 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5941
5942 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5943 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
5944 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5945
5946 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
5947
5948 if (E_BDMA_OK != bdmaRlt)
5949 {
5950 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
5951 }
5952 #else
5953 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5954
5955 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5956 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
5957 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5958
5959 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
5960 #endif
5961 }
5962
5963 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
5964
5965 HAL_HVD_EX_FlushMemory();
5966
5967 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5968 {
5969 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
5970 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
5971 }
5972 else
5973 {
5974 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
5975
5976 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5977 }
5978 }
5979
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)5980 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
5981 {
5982 if (bEnable)
5983 {
5984 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5985 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
5986 }
5987 else
5988 {
5989 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
5990 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
5991 }
5992 }
5993
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)5994 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
5995 {
5996 MS_U32 tmp1 = 0;
5997 MS_U32 tmp2 = 0;
5998 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5999
6000 HAL_HVD_EX_ReadMemory();
6001
6002 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
6003 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
6004
6005 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6006 {
6007 MS_U32 u32Tmp = u32UartCtrl;
6008
6009 HVD_EX_MSG_DBG("\n");
6010 u32UartCtrl = 0; // turn off debug message to prevent other function prints
6011 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
6012 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
6013
6014 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
6015 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
6016 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
6017 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
6018
6019 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
6020 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
6021 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
6022
6023 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
6024 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
6025 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
6026 _HVD_EX_GetESLevel(u32Id));
6027
6028 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
6029 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
6030 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
6031 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
6032 printf
6033 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
6034 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
6035 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
6036 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
6037 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
6038 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
6039 pShm->ModeStatus.bShowOneField);
6040
6041 u32UartCtrl = u32Tmp; // recover debug level
6042 }
6043 }
6044
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)6045 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
6046 {
6047 MS_U8 *u32Addr = NULL;
6048 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6049 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6050
6051 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6052 {
6053 return;
6054 }
6055
6056 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
6057
6058 *u32NalSize = *(u32Addr + 2) & 0x1f;
6059 *u32NalSize <<= 8;
6060 *u32NalSize |= *(u32Addr + 1) & 0xff;
6061 *u32NalSize <<= 8;
6062 *u32NalSize |= *(u32Addr) & 0xff;
6063
6064 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
6065 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
6066 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
6067 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
6068 }
6069
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)6070 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
6071 {
6072 MS_U32 u32CurIdx = 0;
6073 MS_BOOL bFinished = FALSE;
6074 MS_U32 u32NalOffset = 0;
6075 MS_U32 u32NalSize = 0;
6076 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6077
6078 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
6079 {
6080 return;
6081 }
6082
6083 u32CurIdx = u32StartIdx;
6084
6085 do
6086 {
6087 if (u32CurIdx == u32EndIdx)
6088 {
6089 bFinished = TRUE;
6090 }
6091
6092 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
6093
6094 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
6095 {
6096 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
6097 }
6098
6099 u32CurIdx++;
6100
6101 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6102 {
6103 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6104 }
6105 } while (bFinished == TRUE);
6106 }
6107
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)6108 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
6109 {
6110 MS_U32 i = 0;
6111 MS_U32 value = 0;
6112
6113 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6114 {
6115 HVD_EX_MSG_DBG("\n");
6116
6117 for (i = 0; i <= u32Num; i++)
6118 {
6119 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
6120 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
6121 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
6122
6123 if (value == 0)
6124 {
6125 break;
6126 }
6127
6128 printf(" %08x", value);
6129
6130 if (((i % 8) + 1) == 8)
6131 {
6132 printf(" |%u\n", i + 1);
6133 }
6134 }
6135
6136 printf("\nHVD Dump HW status End: total number:%u\n", i);
6137 }
6138 }
6139
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)6140 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
6141 {
6142 if (pDrvCtrl)
6143 {
6144 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
6145 }
6146 }
6147
6148 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)6149 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
6150 {
6151 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
6152 }
6153
HAL_HVD_EX_GetView(MS_U32 u32Id)6154 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
6155 {
6156 if( (0xFF & (u32Id >> 8)) == 0x10)
6157 return E_VDEC_EX_MAIN_VIEW;
6158 else
6159 return E_VDEC_EX_SUB_VIEW;
6160 }
6161 #endif ///HVD_ENABLE_MVC
6162
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)6163 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
6164 {
6165 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
6166 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
6167 return;
6168 }
6169
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)6170 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
6171 {
6172 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
6173 return;
6174 }
6175
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)6176 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
6177 {
6178 MS_U64 _hw_max_pixel = 0;
6179 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6180
6181 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6182 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6183 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6184 }
6185
6186
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6187 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6188 {
6189 #if 1
6190 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6191 MS_U16 u16QNum = pShm->u16DispQNumb;
6192 MS_U16 u16QPtr = pShm->u16DispQPtr;
6193 // MS_U16 u16QSize = pShm->u16DispQSize;
6194 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6195 MS_U32 u32DispQNum = 0;
6196 #if HVD_ENABLE_MVC
6197 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6198
6199 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6200 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
6201
6202 if(bMVC || bDolbyVision)
6203 {
6204 #if 0
6205 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6206 {
6207 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6208 }
6209 #endif
6210
6211 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6212 //search the next frame to display
6213 while (u16QNum > 0)
6214 {
6215 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6216 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6217 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6218
6219 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6220 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6221 {
6222 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6223 /// Check the depned view was initial when Output the base view.
6224 if((u16QPtr%2) == 0)
6225 {
6226 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6227 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6228 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6229 {
6230 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6231 ///printf("Return NULL.\n");
6232 continue;
6233 }
6234 }
6235 u32DispQNum++;
6236 }
6237
6238 u16QNum--;
6239 //go to next frame in the dispQ
6240 u16QPtr++;
6241
6242 if (u16QPtr >= pShm->u16DispQSize)
6243 {
6244 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6245 }
6246 }
6247 }
6248 else
6249 #endif ///HVD_ENABLE_MVC
6250 {
6251 #if 0
6252 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6253 {
6254 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6255 }
6256 #endif
6257 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6258 //search the next frame to display
6259 while (u16QNum != 0)
6260 {
6261 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6262
6263 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6264 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6265 {
6266 u32DispQNum++;
6267 }
6268
6269 u16QNum--;
6270 //go to next frame in the dispQ
6271 u16QPtr++;
6272
6273 if (u16QPtr == pShm->u16DispQSize)
6274 {
6275 u16QPtr = 0; //wrap to the begin
6276 }
6277 }
6278 }
6279
6280 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6281 return u32DispQNum;
6282 #else
6283 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6284 return pShm->u16DispQNumb;
6285 #endif
6286 }
6287
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6288 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6289 {
6290 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6291 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
6292 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
6293 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6294 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6295 #if SUPPORT_G2VP9 && defined(VDEC3)
6296 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6297 #else // Not using G2 VP9 implies using Mstar EVD VP9
6298 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6299 #endif
6300 else
6301 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6302 }
6303
6304 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)6305 void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)
6306 {
6307 #ifdef CONFIG_MSTAR_CLKM
6308 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
6309 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
6310 #else
6311 if (bEnable)
6312 {
6313 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6314 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6315 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6316 }
6317 else
6318 {
6319 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6320 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6321 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6322 }
6323
6324 switch (pHVDHalContext->u32EVDClockType)
6325 {
6326 case 576:
6327 {
6328 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6329 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6330 break;
6331 }
6332 case 532:
6333 {
6334 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
6335 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
6336 break;
6337 }
6338 case 456:
6339 {
6340 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6341 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6342 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
6343 }
6344 case 466:
6345 {
6346 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6347 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
6348 break;
6349 }
6350 case 480:
6351 {
6352 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6353 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6354 break;
6355 }
6356 case 384:
6357 {
6358 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6359 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6360 break;
6361 }
6362 case 320:
6363 {
6364 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6365 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6366 break;
6367 }
6368 case 240:
6369 {
6370 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6371 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6372 break;
6373 }
6374 case 192:
6375 {
6376 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6377 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6378 break;
6379 }
6380 default:
6381 {
6382 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6383 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6384 break;
6385 }
6386 }
6387 #endif
6388 #ifdef CONFIG_MSTAR_SRAMPD
6389 if (bEnable)
6390 {
6391 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6392 HVD_Delay_ms(1);
6393 }
6394 else
6395 {
6396 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6397 HVD_Delay_ms(1);
6398 }
6399 #endif
6400 return;
6401 }
6402
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6403 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6404 {
6405 #ifndef VDEC3
6406 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6407 #endif
6408 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6409 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6410 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6411
6412 #ifdef VDEC3
6413 if (0 == pCtrl->u32BBUId)
6414 #else
6415 if (0 == u8TaskId)
6416 #endif
6417 {
6418 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6419 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6420 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)) & (~HVD_REG_BBU_TSP_INPUT));
6421 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)));
6422 }
6423 else
6424 {
6425 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6426 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6427 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)) & (~HVD_REG_BBU_TSP_INPUT_BS2));
6428 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)));
6429 }
6430
6431 return;
6432 }
6433
HAL_EVD_EX_DeinitHW(void)6434 static MS_BOOL HAL_EVD_EX_DeinitHW(void)
6435 {
6436 MS_U16 u16Timeout = 1000;
6437
6438 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6439
6440 while (u16Timeout)
6441 {
6442 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6443 {
6444 break;
6445 }
6446 u16Timeout--;
6447 }
6448
6449 HAL_EVD_EX_PowerCtrl(FALSE);
6450
6451 return TRUE;
6452 }
6453 #endif
6454
6455 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6456 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6457 {
6458 if (bEnable)
6459 {
6460 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6461 }
6462 else
6463 {
6464 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6465 }
6466
6467 switch (pHVDHalContext->u32VP9ClockType)
6468 {
6469 case 432:
6470 {
6471 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6472 break;
6473 }
6474 case 384:
6475 {
6476 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6477 break;
6478 }
6479 case 345:
6480 {
6481 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6482 break;
6483 }
6484 case 320:
6485 {
6486 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6487 break;
6488 }
6489 case 288:
6490 {
6491 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6492 break;
6493 }
6494 case 240:
6495 {
6496 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6497 break;
6498 }
6499 case 216:
6500 {
6501 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6502 break;
6503 }
6504 case 172:
6505 {
6506 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6507 break;
6508 }
6509 default:
6510 {
6511 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6512 break;
6513 }
6514 }
6515
6516 return;
6517 }
6518
HAL_VP9_EX_DeinitHW(void)6519 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6520 {
6521 MS_U16 u16Timeout = 1000;
6522
6523 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6524
6525 while (u16Timeout)
6526 {
6527 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6528 {
6529 break;
6530 }
6531 u16Timeout--;
6532 }
6533
6534 HAL_VP9_EX_PowerCtrl(FALSE);
6535
6536 return TRUE;
6537 }
6538 #endif
6539
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6540 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6541 {
6542 return TRUE;
6543 }
HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)6544 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
6545 {
6546 _HVD_EX_SetBufferAddr(u32Id);
6547 }
6548
6549
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6550 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6551 {
6552 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6553
6554 if(pCtrl->InitParams.u16ChipECONum == 0)
6555 return FALSE;
6556 else
6557 return TRUE;
6558
6559 }
6560
6561
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6562 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6563 {
6564
6565 }
6566
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6567 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6568 {
6569
6570 }
6571 #endif
6572