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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regVPU.h 98 /// @brief VPU Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_VPU_H_ 103 #define _REG_VPU_H_ 104 105 //#include "MsCommon.h" 106 107 #ifndef BMASK 108 #define BIT(_bit_) (1 << (_bit_)) 109 #define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) 110 #define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) 111 #endif 112 113 #ifndef READ_BYTE 114 #define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) 115 #define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) 116 #define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) 117 #define WRITE_BYTE(_reg, _val) { (*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } 118 #define WRITE_WORD(_reg, _val) { (*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } 119 #define WRITE_LONG(_reg, _val) { (*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } 120 #endif 121 122 //------------------------------------------------------------------------------------------------- 123 // Hardware Capability 124 //------------------------------------------------------------------------------------------------- 125 126 127 //------------------------------------------------------------------------------------------------- 128 // Macro and Define 129 //------------------------------------------------------------------------------------------------- 130 131 //***************************************************************************** 132 // RIU macro 133 #define VPU_MACRO_START do { 134 #define VPU_MACRO_END } while (0) 135 #define VPU_RIU_BASE u32VPURegOSBase 136 137 #define VPU_HIGHBYTE(u16) ((MS_U8)((u16) >> 8)) 138 #define VPU_LOWBYTE(u16) ((MS_U8)(u16)) 139 #define VPU_RIU_READ_BYTE(addr) ( READ_BYTE( VPU_RIU_BASE + (addr) ) ) 140 #define VPU_RIU_READ_WORD(addr) ( READ_WORD( VPU_RIU_BASE + (addr) ) ) 141 #define VPU_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( VPU_RIU_BASE+(addr), val); } 142 #define VPU_RIU_WRITE_WORD(addr, val) { WRITE_WORD( VPU_RIU_BASE+(addr), val); } 143 144 145 #define _VPU_ReadByte( u32Reg ) VPU_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 146 147 #define _VPU_Read2Byte( u32Reg ) (VPU_RIU_READ_WORD((u32Reg)<<1)) 148 149 #define _VPU_Read4Byte( u32Reg ) ( (MS_U32)VPU_RIU_READ_WORD((u32Reg)<<1) | ((MS_U32)VPU_RIU_READ_WORD(((u32Reg)+2)<<1)<<16 ) ) 150 151 #define _VPU_ReadRegBit( u32Reg, u8Mask ) (VPU_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 152 153 #define _VPU_ReadWordBit( u32Reg, u16Mask ) (_VPU_Read2Byte( u32Reg ) & (u16Mask)) 154 155 #define _VPU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 156 VPU_MACRO_START \ 157 VPU_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (VPU_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 158 (VPU_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 159 VPU_MACRO_END 160 161 #define _VPU_WriteByte( u32Reg, u8Val ) \ 162 VPU_MACRO_START \ 163 VPU_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 164 VPU_MACRO_END 165 166 #define _VPU_Write2Byte( u32Reg, u16Val ) \ 167 VPU_MACRO_START \ 168 if ( ((u32Reg) & 0x01) ) \ 169 { \ 170 VPU_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 171 VPU_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 172 } \ 173 else \ 174 { \ 175 VPU_RIU_WRITE_WORD( ((u32Reg)<<1) , u16Val); \ 176 } \ 177 VPU_MACRO_END 178 179 #define _VPU_Write3Byte( u32Reg, u32Val ) \ 180 if ((u32Reg) & 0x01) \ 181 { \ 182 VPU_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 183 VPU_RIU_WRITE_WORD( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 184 } \ 185 else \ 186 { \ 187 VPU_RIU_WRITE_WORD( (u32Reg) << 1, u32Val); \ 188 VPU_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 189 } 190 191 #define _VPU_Write4Byte( u32Reg, u32Val ) \ 192 VPU_MACRO_START \ 193 if ((u32Reg) & 0x01) \ 194 { \ 195 VPU_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 196 VPU_RIU_WRITE_WORD( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 197 VPU_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 198 } \ 199 else \ 200 { \ 201 VPU_RIU_WRITE_WORD( (u32Reg) <<1 , u32Val); \ 202 VPU_RIU_WRITE_WORD( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 203 } \ 204 VPU_MACRO_END 205 206 #define _VPU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 207 VPU_MACRO_START \ 208 VPU_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (VPU_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 209 VPU_MACRO_END 210 211 #define _VPU_WriteWordMask( u32Reg, u16Val , u16Msk) \ 212 VPU_MACRO_START \ 213 if ( ((u32Reg) & 0x01) ) \ 214 { \ 215 if ((u16Msk)&0xff00) _VPU_WriteByteMask( ((u32Reg)+1) , (((u16Val) & 0xff00)>>8) , (((u16Msk)&0xff00)>>8) ); \ 216 _VPU_WriteByteMask( (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk)&0x00ff) ); \ 217 } \ 218 else \ 219 { \ 220 VPU_RIU_WRITE_WORD( ((u32Reg)<<1) , (((u16Val) & (u16Msk)) | (_VPU_Read2Byte( u32Reg ) & (~( u16Msk )))) ); \ 221 } \ 222 VPU_MACRO_END 223 224 225 226 //------------------------------------------------------------------------------ 227 // VPU Reg 228 //------------------------------------------------------------------------------ 229 #define EVDR2 230 #ifdef EVDR2 231 #define REG_VPU_BASE (0x63300) 232 #define REG_MBX_BASE (0x63400) 233 #define REG_MAU1_BASE (0x63400) 234 #define REG_MAU1_LV2_0_BASE (0x63700) 235 #define REG_MAU1_LV2_1_BASE (0x63800) 236 #else 237 #define REG_VPU_BASE (0x0300) 238 #define REG_MBX_BASE (0x0400) 239 #define REG_MAU1_BASE (0x0400) 240 #define REG_MAU1_LV2_0_BASE (0x63500) 241 #define REG_MAU1_LV2_1_BASE (0x63600) 242 #endif 243 244 //write back stage PC 245 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1)) 246 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1)) 247 248 #define VPU_REG_CPU_STATUS (REG_VPU_BASE+( 0x000f<<1)) 249 #define VPU_REG_CPU_D_REPLAY BIT(8) 250 #define VPU_REG_CPU_I_EMPTY BIT(6) 251 252 #define VPU_REG_MIU_LAST (REG_VPU_BASE+( 0x0020<<1)) 253 #define VPU_REG_MIU_LAST_EN BIT(5) 254 255 #define VPU_REG_ICU_STATUS (REG_VPU_BASE+( 0x001f<<1)) 256 #define VPU_REG_ICU_IDLE BIT(1) 257 #define VPU_REG_ISB_IDLE BIT(8) 258 259 #define VPU_REG_ICU_DBG_SEL (REG_VPU_BASE+( 0x0010<<1)) 260 #define VPU_REG_ICU_DBG_DAT0 (REG_VPU_BASE+( 0x0014<<1)) 261 #define VPU_REG_ICPU_REQ BIT(14) 262 263 #define VPU_REG_DCU_DBG_SEL (REG_VPU_BASE+( 0x0028<<1)) 264 #define VPU_REG_DCU_DBG_SEL_0 BIT(2) 265 #define VPU_REG_DCU_DBG_SEL_1 BIT(3) 266 #define VPU_REG_DCU_STATUS (REG_VPU_BASE+( 0x0029<<1)) 267 #define VPU_REG_BIU_EMPTY BIT(11) 268 269 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1)) 270 #define VPU_REG_CPU_R2_EN BIT(0) 271 #define VPU_REG_CPU_SW_RSTZ BIT(1) 272 #define VPU_REG_CPU_MIU_SW_RSTZ BIT(2) 273 #define VPU_REG_CPU_RIU_SW_RSTZ BIT(3) 274 #define VPU_REG_CPU_SPI_BOOT BIT(4) 275 #define VPU_REG_CPU_SDRAM_BOOT BIT(5) 276 #define VPU_REG_CPU_R2_INTO BIT(6) 277 #define VPU_REG_CPU_DBG_ON_DCU BIT(8) 278 #define VPU_REG_CPU_DBG_ON_ICU BIT(9) 279 #define VPU_REG_CPU_DBG_CLK_SEL BIT(10) 280 #define VPU_REG_CPU_DBG_CLK_TOGGLE BIT(11) 281 282 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address 283 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1)) 284 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address 285 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1)) 286 287 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32 288 289 290 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1)) 291 #define VPU_REG_IQMEM_BASE_H (REG_VPU_BASE+(0x004a<<1)) 292 #define VPU_REG_IQMEM_MASK_L (REG_VPU_BASE+(0x004b<<1)) 293 #define VPU_REG_IQMEM_MASK_H (REG_VPU_BASE+(0x004c<<1)) 294 295 #define VPU_REG_DQMEM_BASE_L (REG_VPU_BASE+(0x004d<<1)) 296 #define VPU_REG_DQMEM_BASE_H (REG_VPU_BASE+(0x004e<<1)) 297 #define VPU_REG_DQMEM_MASK_L (REG_VPU_BASE+(0x004f<<1)) 298 #define VPU_REG_DQMEM_MASK_H (REG_VPU_BASE+(0x0050<<1)) 299 300 #define VPU_REG_PQMEM_BASE_L (REG_VPU_BASE+(0x0051<<1)) 301 #define VPU_REG_PQMEM_BASE_H (REG_VPU_BASE+(0x0052<<1)) 302 #define VPU_REG_PQMEM_MASK_L (REG_VPU_BASE+(0x0053<<1)) 303 #define VPU_REG_PQMEM_MASK_H (REG_VPU_BASE+(0x0054<<1)) 304 #define VPU_REG_IQMEM_SETTING (REG_VPU_BASE+(0x0064<<1)) 305 #define VPU_REG_VQMEM_BASE_L (REG_VPU_BASE+(0x0067<<1)) 306 #define VPU_REG_VQMEM_BASE_H (REG_VPU_BASE+(0x0068<<1)) 307 #define VPU_REG_VQMEM_MASK_L (REG_VPU_BASE+(0x0069<<1)) 308 #define VPU_REG_VQMEM_MASK_H (REG_VPU_BASE+(0x006a<<1)) 309 #define VPU_REG_CPU_CONFIG (REG_VPU_BASE+(0x006b<<1)) 310 #define VPU_REG_CPU_STALL_EN BIT(15) 311 312 #define VPU_REG_QMEM_OWNER (REG_VPU_BASE+(0x006c<<1)) 313 314 #define VPU_REG_IO0_BASE (REG_VPU_BASE+(0x0045<<1)) //RIU 315 #define VPU_REG_IO1_BASE (REG_VPU_BASE+(0x0055<<1)) //R2 internal UART 316 #define VPU_REG_IO2_BASE (REG_VPU_BASE+(0x0056<<1)) //R2 read SPI 317 #define VPU_REG_IO3_BASE (REG_VPU_BASE+(0x0057<<1)) //IP use 318 #define VPU_REG_CONTROL_SET (REG_VPU_BASE+(0x0058<<1)) 319 320 #define VPU_REG_R2_MI_SEL_BASE (REG_VPU_BASE+(0x0072<<1)) 321 322 #define VPU_REG_IO0_EN BIT(0) //default Enable 323 #define VPU_REG_IO1_EN BIT(1) //default Enable 324 #define VPU_REG_IO2_EN BIT(2) 325 #define VPU_REG_IO3_EN BIT(3) 326 #define VPU_REG_QMEM_SPACE_EN BIT(4) 327 #define VPU_REG_MMU_IO_EN BIT(5) 328 #define VPU_REG_WMB_FORCE_OFF BIT(6) 329 #define VPU_REG_WMB_AUTO_OFF BIT(7) 330 #define VPU_REG_PQMEM_SPACE_EN BIT(13) 331 #define VPU_REG_VQMEM_SPACE_EN BIT(14) 332 333 334 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1)) 335 336 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1)) 337 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1)) 338 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1)) 339 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1)) 340 341 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) 342 #define VPU_REG_HI_MBOX0_SET BIT(0) 343 #define VPU_REG_HI_MBOX1_SET BIT(1) 344 345 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1)) 346 #define VPU_REG_RISC_MBOX0_CLR BIT(0) 347 #define VPU_REG_RISC_MBOX1_CLR BIT(1) 348 #define VPU_REG_RISC_ISR_CLR BIT(2) 349 #define VPU_REG_RISC_ISR_MSK BIT(6) 350 #define VPU_REG_RISC_ISR_FORCE BIT(10) 351 352 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1)) 353 #define VPU_REG_RISC_MBOX0_RDY BIT(0) 354 #define VPU_REG_RISC_MBOX1_RDY BIT(1) 355 #define VPU_REG_RISC_ISR_VALID BIT(2) 356 357 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1)) 358 #define VPU_REG_HI_MBOX0_RDY BIT(0) 359 #define VPU_REG_HI_MBOX1_RDY BIT(1) 360 361 #define VPU_REG_RISC_MBOX0_L (REG_MBX_BASE+(0x006b<<1)) 362 #define VPU_REG_RISC_MBOX0_H (REG_MBX_BASE+(0x006c<<1)) 363 #define VPU_REG_RISC_MBOX1_L (REG_MBX_BASE+(0x006d<<1)) 364 #define VPU_REG_RISC_MBOX1_H (REG_MBX_BASE+(0x006e<<1)) 365 366 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1)) 367 #define MAU1_REG_SW_RESET BIT(0) 368 369 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1)) 370 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1)) 371 #define MAU1_FSM_CS_MASK BMASK(13:9) 372 #define MAU1_FSM_CS_IDLE BITS(13:9, 1) 373 374 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1)) 375 #define MAU1_LV2_0_MIU_SEL (REG_MAU1_LV2_0_BASE+(0x0001<<1)) 376 #define MAU1_LV2_1_MIU_SEL (REG_MAU1_LV2_1_BASE+(0x0001<<1)) 377 378 379 //------------------------------------------------------------------------------ 380 // ChipTop Reg 381 //------------------------------------------------------------------------------ 382 383 #define CHIPTOP_REG_BASE (0x1E00 ) 384 #define CLKGEN0_REG_BASE (0x0B00 ) 385 386 #define REG_TOP_VPU (CLKGEN0_REG_BASE+(0x0030<<1)) 387 #define TOP_CKG_VPU_MASK BMASK(4:0) 388 #define TOP_CKG_VPU_DIS BIT(0) 389 #define TOP_CKG_VPU_INV BIT(1) 390 #define TOP_CKG_VPU_CLK_MASK BMASK(4:2) 391 392 #define REG_CHIPTOP_DUMMY_CODEC (CHIPTOP_REG_BASE+(0x0015<<1)) 393 #define REG_CHIPTOP_DUMMY_CODEC_MASK BMASK(15:0) 394 #define REG_CHIPTOP_DUMMY_CODEC_ENABLE BITS(15:14,3) 395 396 //------------------------------------------------------------------------------ 397 // MIU Reg 398 //------------------------------------------------------------------------------ 399 //------------------------------------------------------------------------------ 400 // MIU Reg 401 //------------------------------------------------------------------------------ 402 #define MIU0_REG_HVD_BASE (0x1200) 403 #define MIU0_REG_HVD_BASE2 (0x61500) 404 405 #define MIU1_REG_HVD_BASE (0x0600) 406 #define MIU1_REG_HVD_BASE2 (0x62200) 407 408 #define MIU2_REG_HVD_BASE (0x62000) 409 #define MIU2_REG_HVD_BASE2 (0x62300) 410 411 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1)) 412 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1)) 413 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1)) 414 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1)) 415 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) 416 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1)) 417 418 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) 419 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1)) 420 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1)) 421 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1)) 422 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1)) 423 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1)) 424 425 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) 426 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1)) 427 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) 428 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1)) 429 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) 430 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1)) 431 432 433 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1)) 434 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1)) 435 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1)) 436 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) 437 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) 438 #define MIU0_REG_SEL5 (MIU0_REG_HVD_BASE+(( 0x007D)<<1)) 439 440 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1)) 441 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1)) 442 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1)) 443 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1)) 444 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1)) 445 #define MIU2_REG_SEL5 (MIU2_REG_HVD_BASE+(( 0x007D)<<1)) 446 447 448 //------------------------------------------------------------------------------------------------- 449 // Type and Structure 450 //------------------------------------------------------------------------------------------------- 451 452 453 454 455 #endif // _REG_VPU_H_ 456 457