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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #ifndef MSOS_TYPE_NUTTX 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 #define VPU_FORCE_MIU_MODE 1 121 #define HVD_ENABLE_IQMEM 0 122 #define VPU_IQMEM_BASE 0xe0000000 123 #define ENABLE_DECOMPRESS_FUNCTION TRUE 124 125 #define VPU_CLOCK_240MHZ BITS(4:2,0) 126 #define VPU_CLOCK_216MHZ BITS(4:2,1) 127 #define VPU_CLOCK_192MHZ BITS(4:2,2) 128 #define VPU_CLOCK_XTAL BITS(4:2,3) 129 #define VPU_CLOCK_320MHZ BITS(4:2,4) 130 #define VPU_CLOCK_288MHZ BITS(4:2,5) 131 132 133 #define VPU_IQMEM_BASE 0xe0000000 134 135 #define VPU_ENABLE_MOBF_TEST 0 136 137 138 139 #define VPU_HI_MBOX0 0 140 #define VPU_HI_MBOX1 1 141 #define VPU_RISC_MBOX0 2 142 #define VPU_RISC_MBOX1 3 143 144 145 #define VPU_EX_TimerDelayMS(x) \ 146 do \ 147 { \ 148 volatile MS_U32 ticks = 0; \ 149 while (ticks < (((MS_U32) (x)) << 13)) \ 150 { \ 151 ticks++; \ 152 } \ 153 } while(0) 154 155 #ifdef VDEC3 156 #define HAL_VPU_INVALID_BBU_ID 0xFFFFFFFF 157 #define VPU_MAX_DEC_NUM 16 158 #else 159 #define VPU_MAX_DEC_NUM 2 160 #endif 161 #define CHECK_NULL_PTR(vbbu_addr) (((void *)(vbbu_addr)) == NULL) 162 163 //------------------------------------------------------------------------------------------------- 164 // Type and Structure 165 //------------------------------------------------------------------------------------------------- 166 typedef enum 167 { 168 E_HAL_HVD_STREAM_NONE = 0x0, 169 170 //Support TSP/TS/File mode 171 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 172 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 173 E_HAL_HVD_MAIN_STREAM_MAX, 174 175 //Only support file mode 176 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 177 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 178 E_HAL_HVD_SUB_STREAM1, 179 E_HAL_HVD_SUB_STREAM_MAX, 180 181 #ifdef VDEC3 182 E_HAL_HVD_N_STREAM_BASE = 0x40, 183 E_HAL_HVD_N_STREAM0 = E_HAL_HVD_N_STREAM_BASE, 184 E_HAL_HVD_N_STREAM_MAX = E_HAL_HVD_N_STREAM0 + VPU_MAX_DEC_NUM, 185 #endif 186 187 //Only support MVC stream 188 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 189 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 190 E_HAL_HVD_MVC_Sub_View, 191 E_HAL_HVD_MVC_STREAM_MAX, 192 } HAL_HVD_StreamId; 193 194 typedef enum 195 { 196 E_VPU_EX_DECODER_NONE = 0, 197 E_VPU_EX_DECODER_MVD, 198 E_VPU_EX_DECODER_HVD, 199 E_VPU_EX_DECODER_MJPEG, 200 E_VPU_EX_DECODER_RVD, 201 E_VPU_EX_DECODER_MVC, 202 E_VPU_EX_DECODER_VP8, 203 #ifdef VDEC3 204 E_VPU_EX_DECODER_EVD, 205 #if SUPPORT_G2VP9 206 E_VPU_EX_DECODER_G2VP9, 207 #endif 208 #endif 209 } VPU_EX_DecoderType; 210 211 typedef enum 212 { 213 E_VPU_EX_CLOCK_240MHZ = VPU_CLOCK_240MHZ, 214 E_VPU_EX_CLOCK_216MHZ = VPU_CLOCK_216MHZ, 215 E_VPU_EX_CLOCK_192MHZ = VPU_CLOCK_192MHZ, 216 E_VPU_EX_CLOCK_XTAL = VPU_CLOCK_XTAL, 217 E_VPU_EX_CLOCK_320MHZ = VPU_CLOCK_320MHZ, 218 E_VPU_EX_CLOCK_288MHZ = VPU_CLOCK_288MHZ, 219 } VPU_EX_ClockSpeed; 220 221 typedef enum 222 { 223 E_HAL_VPU_STREAM_NONE = 0x0, 224 225 //Support TSP/TS File/File mode 226 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 227 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 228 E_HAL_VPU_MAIN_STREAM_MAX, 229 230 //Only support file mode 231 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 232 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 233 E_HAL_VPU_SUB_STREAM_MAX, 234 235 #ifdef VDEC3 236 E_HAL_VPU_N_STREAM_BASE = 0x40, 237 E_HAL_VPU_N_STREAM0 = E_HAL_VPU_N_STREAM_BASE, 238 E_HAL_VPU_N_STREAM_MAX = E_HAL_VPU_N_STREAM0 + VPU_MAX_DEC_NUM, 239 #endif 240 241 //Only support MVC stream 242 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 243 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 244 E_HAL_VPU_MVC_SUB_VIEW, 245 E_HAL_VPU_MVC_STREAM_MAX, 246 } HAL_VPU_StreamId; 247 248 typedef enum 249 { 250 //Support TSP/TS/File mode 251 E_HAL_VPU_MAIN_STREAM, 252 253 //Only support file mode 254 E_HAL_VPU_SUB_STREAM, 255 256 //Only support MVC mode 257 E_HAL_VPU_MVC_STREAM, 258 259 #ifdef VDEC3 260 E_HAL_VPU_N_STREAM, 261 #endif 262 } HAL_VPU_StreamType; 263 264 typedef enum 265 { 266 //Support TSP/TS/File mode 267 E_VPU_EX_INPUT_TSP, 268 //Only support file mode 269 E_VPU_EX_INPUT_FILE, 270 E_VPU_EX_INPUT_NONE, 271 } VPU_EX_SourceType; 272 273 typedef enum 274 { 275 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 276 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 277 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 278 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 279 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 280 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 281 } VPU_EX_UartLevel; 282 283 typedef enum 284 { 285 E_VPU_EX_FW_VER_CTRLR = 0, 286 E_VPU_EX_FW_VER_MVD_FW, 287 E_VPU_EX_FW_VER_HVD_FW, 288 E_VPU_EX_FW_VER_MVD_IF, 289 E_VPU_EX_FW_VER_HVD_IF, 290 } VPU_EX_FWVerType; 291 292 /// DecodeMode for f/w tasks 293 typedef enum 294 { 295 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 296 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 297 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 298 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 299 } VPU_EX_DecMode; 300 301 /// CmdMode for KOREA3D or PIP mode 302 typedef enum 303 { 304 //Group1:Set Korea3DTV mode 305 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 306 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 307 E_VPU_CMD_MODE_KR3D_FORCE_P, 308 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 309 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 310 311 //Group2:Set PIP mode 312 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 313 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 314 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 315 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 316 } VPU_EX_CmdMode; 317 318 typedef struct 319 { 320 VPU_EX_ClockSpeed eClockSpeed; 321 MS_BOOL bClockInv; 322 MS_S32 s32VPUMutexID; 323 MS_U32 u32VPUMutexTimeout; 324 MS_U8 u8MiuSel; 325 } VPU_EX_InitParam; 326 327 #define CMA_DRV_DIRECT_INIT 328 #ifdef CMA_DRV_DIRECT_INIT 329 /// input source select enumerator 330 typedef enum 331 { 332 ///DTV mode 333 E_VPU_EX_SRC_MODE_DTV = 0, 334 ///TS file mode 335 E_VPU_EX_SRC_MODE_TS_FILE, 336 ///generic file mode 337 E_VPU_EX_SRC_MODE_FILE, 338 /// TS file and dual ES buffer mode 339 E_VPU_EX_SRC_MODE_TS_FILE_DUAL_ES, 340 ///generic file and dual ES buffer mode 341 E_VPU_EX_SRC_MODE_FILE_DUAL_ES, 342 } VPU_EX_SrcMode; 343 #endif 344 345 /// codec type enumerator 346 typedef enum 347 { 348 ///unsupported codec type 349 E_VPU_EX_CODEC_TYPE_NONE = 0, 350 ///MPEG 1/2 351 E_VPU_EX_CODEC_TYPE_MPEG2, 352 ///H263 (short video header) 353 E_VPU_EX_CODEC_TYPE_H263, 354 ///MPEG4 (default) 355 E_VPU_EX_CODEC_TYPE_MPEG4, 356 ///MPEG4 (Divx311) 357 E_VPU_EX_CODEC_TYPE_DIVX311, 358 ///MPEG4 (Divx412) 359 E_VPU_EX_CODEC_TYPE_DIVX412, 360 ///FLV 361 E_VPU_EX_CODEC_TYPE_FLV, 362 ///VC1 advanced profile (VC1) 363 E_VPU_EX_CODEC_TYPE_VC1_ADV, 364 ///VC1 main profile (RCV) 365 E_VPU_EX_CODEC_TYPE_VC1_MAIN, 366 ///Real Video version 8 367 E_VPU_EX_CODEC_TYPE_RV8, 368 ///Real Video version 9 and 10 369 E_VPU_EX_CODEC_TYPE_RV9, 370 ///H264 371 E_VPU_EX_CODEC_TYPE_H264, 372 ///AVS 373 E_VPU_EX_CODEC_TYPE_AVS, 374 ///MJPEG 375 E_VPU_EX_CODEC_TYPE_MJPEG, 376 ///MVC 377 E_VPU_EX_CODEC_TYPE_MVC, 378 ///VP8 379 E_VPU_EX_CODEC_TYPE_VP8, 380 ///HEVC 381 E_VPU_EX_CODEC_TYPE_HEVC, 382 ///VP9 383 E_VPU_EX_CODEC_TYPE_VP9, 384 E_VPU_EX_CODEC_TYPE_NUM 385 } VPU_EX_CodecType; 386 387 typedef struct 388 { 389 MS_U32 u32Id; 390 HAL_VPU_StreamId eVpuId; 391 VPU_EX_SourceType eSrcType; 392 VPU_EX_DecoderType eDecType; 393 MS_U8 u8HalId; // hal MVD/HVD id 394 MS_U32 u32HeapSize; 395 } VPU_EX_TaskInfo; 396 397 typedef struct 398 { 399 MS_U32 u32DstAddr; 400 MS_U32 u32DstSize; 401 MS_U32 u32BinSize; 402 MS_U32 u32BinAddr; 403 MS_U8 u8SrcType; 404 } VPU_EX_FWCodeCfg; 405 406 typedef struct 407 { 408 MS_U32 u32DstAddr; 409 MS_U32 u32BinAddr; 410 MS_U32 u32BinSize; 411 MS_U32 u32FrameBufAddr; 412 MS_U32 u32VLCTableOffset; 413 } VPU_EX_VLCTblCfg; 414 415 #ifdef VDEC3 416 typedef struct 417 { 418 MS_U32 u32FrameBufAddr; 419 MS_U32 u32FrameBufSize; 420 } VPU_EX_FBCfg; 421 #endif 422 423 /// VPU init parameters for dual decoder 424 typedef struct 425 { 426 VPU_EX_FWCodeCfg *pFWCodeCfg; 427 VPU_EX_TaskInfo *pTaskInfo; 428 VPU_EX_VLCTblCfg *pVLCCfg; 429 #ifdef VDEC3 430 VPU_EX_FBCfg *pFBCfg; 431 #endif 432 } VPU_EX_NDecInitPara; 433 434 typedef struct 435 { 436 MS_U8 u8DecMod; 437 MS_U8 u8CodecCnt; 438 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 439 MS_U8 u8ArgSize; 440 MS_U32 u32Arg; 441 } VPU_EX_DecModCfg; 442 443 typedef enum 444 { 445 E_VDEC_EX_CODEC_PROFILE_NONE, 446 447 E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, 448 449 E_VDEC_EX_CODEC_PROFILE_MP4_ASP, 450 451 E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, 452 453 E_VDEC_EX_CODEC_PROFILE_VC1_AP, 454 455 E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, 456 457 E_VDEC_EX_CODEC_PROFILE_VP9_0, 458 E_VDEC_EX_CODEC_PROFILE_VP9_2, 459 460 E_VDEC_EX_CODEC_PROFILE_H264_CBP, 461 E_VDEC_EX_CODEC_PROFILE_H264_BP, 462 E_VDEC_EX_CODEC_PROFILE_H264_XP, 463 E_VDEC_EX_CODEC_PROFILE_H264_MP, 464 E_VDEC_EX_CODEC_PROFILE_H264_HIP, 465 E_VDEC_EX_CODEC_PROFILE_H264_PHIP, 466 E_VDEC_EX_CODEC_PROFILE_H264_CHIP, 467 E_VDEC_EX_CODEC_PROFILE_H264_HI10P, 468 E_VDEC_EX_CODEC_PROFILE_H264_HI422P, 469 E_VDEC_EX_CODEC_PROFILE_H264_HI444PP, 470 471 E_VDEC_EX_CODEC_PROFILE_H265_MAIN, 472 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, 473 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_12, 474 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_10, 475 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_12, 476 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444, 477 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_10, 478 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_12, 479 480 E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, 481 482 } VDEC_EX_CODEC_CAP_PROFILE_INFO; 483 484 typedef enum 485 { 486 E_VDEC_EX_CODEC_LEVEL_NONE, 487 488 E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, 489 490 E_VDEC_EX_CODEC_LEVEL_MP4_L5, 491 492 E_VDEC_EX_CODEC_LEVEL_VC1_L3, 493 494 E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, 495 496 497 E_VDEC_EX_CODEC_LEVEL_H264_1, 498 E_VDEC_EX_CODEC_LEVEL_H264_1B, 499 E_VDEC_EX_CODEC_LEVEL_H264_1_1, 500 E_VDEC_EX_CODEC_LEVEL_H264_1_2, 501 E_VDEC_EX_CODEC_LEVEL_H264_1_3, 502 E_VDEC_EX_CODEC_LEVEL_H264_2, 503 E_VDEC_EX_CODEC_LEVEL_H264_2_1, 504 E_VDEC_EX_CODEC_LEVEL_H264_2_2, 505 E_VDEC_EX_CODEC_LEVEL_H264_3, 506 E_VDEC_EX_CODEC_LEVEL_H264_3_1, 507 E_VDEC_EX_CODEC_LEVEL_H264_3_2, 508 E_VDEC_EX_CODEC_LEVEL_H264_4, 509 E_VDEC_EX_CODEC_LEVEL_H264_4_1, 510 E_VDEC_EX_CODEC_LEVEL_H264_4_2, 511 E_VDEC_EX_CODEC_LEVEL_H264_5, 512 E_VDEC_EX_CODEC_LEVEL_H264_5_1, 513 E_VDEC_EX_CODEC_LEVEL_H264_5_2, 514 515 E_VDEC_EX_CODEC_LEVEL_H265_1, 516 E_VDEC_EX_CODEC_LEVEL_H265_2, 517 E_VDEC_EX_CODEC_LEVEL_H265_2_1, 518 E_VDEC_EX_CODEC_LEVEL_H265_3, 519 E_VDEC_EX_CODEC_LEVEL_H265_3_1, 520 E_VDEC_EX_CODEC_LEVEL_H265_4_MT, 521 E_VDEC_EX_CODEC_LEVEL_H265_4_HT, 522 E_VDEC_EX_CODEC_LEVEL_H265_4_1_MT, 523 E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, 524 E_VDEC_EX_CODEC_LEVEL_H265_5_MT, 525 E_VDEC_EX_CODEC_LEVEL_H265_5_HT, 526 E_VDEC_EX_CODEC_LEVEL_H265_5_1_MT, 527 E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, 528 E_VDEC_EX_CODEC_LEVEL_H265_5_2_MT, 529 E_VDEC_EX_CODEC_LEVEL_H265_5_2_HT, 530 E_VDEC_EX_CODEC_LEVEL_H265_6_MT, 531 E_VDEC_EX_CODEC_LEVEL_H265_6_HT, 532 E_VDEC_EX_CODEC_LEVEL_H265_6_1_MT, 533 E_VDEC_EX_CODEC_LEVEL_H265_6_1_HT, 534 E_VDEC_EX_CODEC_LEVEL_H265_6_2_MT, 535 E_VDEC_EX_CODEC_LEVEL_H265_6_2_HT, 536 537 E_VDEC_EX_CODEC_LEVEL_AVS_6010860, 538 539 } VDEC_EX_CODEC_CAP_LEVEL_INFO; 540 541 542 typedef enum 543 { 544 E_VDEC_EX_CODEC_VERSION_NONE, 545 546 E_VDEC_EX_CODEC_VERSION_DIVX_311, 547 E_VDEC_EX_CODEC_VERSION_DIVX_4, 548 E_VDEC_EX_CODEC_VERSION_DIVX_5, 549 E_VDEC_EX_CODEC_VERSION_DIVX_6, 550 551 E_VDEC_EX_CODEC_VERSION_FLV_1, 552 553 E_VDEC_EX_CODEC_VERSION_H263_1, 554 555 } VDEC_EX_CODEC_CAP_VERSION_INFO; 556 557 typedef struct 558 { 559 MS_U16 u16CodecCapWidth; 560 MS_U16 u16CodecCapHeight; 561 MS_U8 u8CodecCapFrameRate; 562 VDEC_EX_CODEC_CAP_PROFILE_INFO u8CodecCapProfile; 563 VDEC_EX_CODEC_CAP_VERSION_INFO u8CodecCapVersion; 564 VDEC_EX_CODEC_CAP_LEVEL_INFO u8CodecCapLevel; 565 MS_U32 u32CodecType; 566 MS_U32 u32BitRate; 567 }VDEC_EX_CODEC_CAP_INFO; 568 569 //------------------------------------------------------------------------------------------------- 570 // Function and Variable 571 //------------------------------------------------------------------------------------------------- 572 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 573 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 574 #ifdef VDEC3 575 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId); 576 #else 577 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 578 #endif 579 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 580 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 581 582 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 583 void HAL_VPU_EX_InitRegBase(MS_U32 u32RegBase); 584 585 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 586 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 587 MS_BOOL HAL_VPU_EX_DeInit(void); 588 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 589 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 590 MS_BOOL HAL_VPU_EX_CPUSetting(MS_U32 u32StAddr); 591 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 592 void HAL_VPU_EX_SwRstRelse(void); 593 void HAL_VPU_EX_SwRelseMAU(void); 594 MS_U32 HAL_VPU_EX_MemRead(MS_U32 u32Address); 595 MS_BOOL HAL_VPU_EX_MemWrite(MS_U32 u32Address, MS_U32 u32Value); 596 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 597 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 598 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 599 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 600 MS_U32 HAL_VPU_EX_GetProgCnt(void); 601 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 602 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_U32 u32ShmAddr); 603 MS_U32 HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 604 MS_U32 HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id); 605 MS_U32 HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id); 606 MS_BOOL HAL_VPU_EX_IsPowered(void); 607 MS_BOOL HAL_VPU_EX_IsRsted(void); 608 MS_BOOL HAL_VPU_EX_IsEVDR2(void); 609 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 610 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 611 #ifdef VDEC3 612 MS_BOOL HAL_VPU_EX_EVDInUsed(void); 613 #if SUPPORT_G2VP9 614 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void); 615 #endif 616 #endif 617 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable); 618 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 619 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 620 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 621 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 622 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo); 623 624 MS_U32 HAL_VPU_EX_MIU1BASE(void); 625 MS_U32 HAL_VPU_EX_GetSHMAddr(void); 626 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 627 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(void); 628 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 629 #ifdef VDEC3 630 typedef enum 631 { 632 E_HVD_CMDQ_CMD, 633 E_HVD_CMDQ_ARG, 634 } HVD_COMMAND_QUEUE_TYPE; 635 636 typedef enum 637 { 638 E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL, 639 E_HVD_COMMAND_QUEUE_NOT_INITIALED, 640 E_HVD_COMMAND_QUEUE_FULL, 641 E_HVD_COMMAND_QUEUE_SEND_FAIL, 642 } HVD_DRAM_COMMAND_QUEUE_SEND_STATUS; 643 644 645 typedef struct 646 { 647 MS_U32 u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 648 MS_U32 u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 649 MS_U64 u64TimeStamp; ///< Packet time stamp. unit: ms. 650 MS_U32 u32ID_L; ///< Packet ID low part. 651 MS_U32 u32ID_H; ///< Packet ID high part. 652 } HAL_VPU_EX_PacketInfo; 653 // *****************Virtual BBU function***************** 654 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_U32 u32VBBUAddr); 655 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_U32 u32VBBUAddr); 656 MS_U32 HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_U32 u32VBBUAddr); 657 MS_U32 HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_U32 u32VBBUAddr); 658 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_U32 u32VBBUAddr); 659 // *****************General dram command queue function***************** 660 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd); 661 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd); 662 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_U32 u32DramAddr, MS_U32 u32Msg); 663 // *****************Dram command queue function***************** 664 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue); 665 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue); 666 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, HVD_COMMAND_QUEUE_TYPE u8CmdType, MS_U32 u32Msg); 667 // *****************Display dram command queue function***************** 668 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue); 669 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue); 670 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, HVD_COMMAND_QUEUE_TYPE u8CmdType, MS_U32 u32Msg); 671 // *****************General purpose function***************** 672 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32BsAddr); 673 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bIsNstreamMode); 674 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo); 675 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType); 676 #ifdef CMA_DRV_DIRECT_INIT 677 // *****************CMA function***************** 678 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode, 679 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize); 680 #endif 681 682 #endif 683 684 #ifdef VDEC3_FB 685 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType); 686 #endif 687 MS_U8 HAL_VPU_EX_CheckFreeStream(void); 688 689 690 #else 691 typedef struct 692 { 693 MS_U32 Bitstream_Addr_Main; 694 MS_U32 Bitstream_Len_Main; 695 MS_U32 Bitstream_Addr_Sub; 696 MS_U32 Bitstream_Len_Sub; 697 MS_U32 MIU1_BaseAddr; 698 } VPU_EX_LOCK_DOWN_REGISTER; 699 700 701 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_U32 addr); 702 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 703 704 #endif 705 #endif // _HAL_VPU_EX_H_ 706 707