1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
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84 // herein regardless in any format shall remain the sole proprietary of
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include <string.h>
101 #include "drvHVD_Common.h"
102
103 // Internal Definition
104 #include "drvHVD_def.h"
105 #include "fwHVD_if.h"
106 #include "halVPU_EX.h"
107 #include "halHVD_EX.h"
108 #include "regHVD_EX.h"
109 #include "drvSYS.h"
110
111 //-------------------------------------------------------------------------------------------------
112 // Driver Compiler Options
113 //-------------------------------------------------------------------------------------------------
114 #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE)
115
116 //-------------------------------------------------------------------------------------------------
117 // Local Defines
118 //-------------------------------------------------------------------------------------------------
119 #define RV_VLC_TABLE_SIZE 0x20000
120 /* Add for Mobile Platform by Ted Sun */
121 //#define HVD_DISPQ_PREFETCH_COUNT 2
122 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
123 #define VPU_QMEM_BASE 0x20000000UL
124
125 //max support pixel(by chip capacity)
126 #define HVD_HW_MAX_PIXEL (1920*1088*61000ULL) // 4kx2k@30p
127 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
128 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
129
130 #define EVD_HW_BUFFER 0x200000 //0x800000: support MFcodec, 0x200000: not support MFcodec
131
132 #define VER_MUNICH 0
133 #define VER_MALDIVES 1
134
135 #if 0
136 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
137 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
138 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
139 static MS_U16 _u16DispQPtr = 0;
140 #endif
141
142 //---------------------------------- Mutex settings -----------------------------------------
143 #if HAL_HVD_ENABLE_MUTEX_PROTECT
144 #define _HAL_HVD_MutexCreate() \
145 do \
146 { \
147 if (s32HVDMutexID < 0) \
148 { \
149 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
150 } \
151 } while (0)
152
153 #define _HAL_HVD_MutexDelete() \
154 do \
155 { \
156 if (s32HVDMutexID >= 0) \
157 { \
158 OSAL_HVD_MutexDelete(s32HVDMutexID); \
159 s32HVDMutexID = -1; \
160 } \
161 } while (0)
162
163 #define _HAL_HVD_Entry() \
164 do \
165 { \
166 if (s32HVDMutexID >= 0) \
167 { \
168 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
169 { \
170 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
171 } \
172 } \
173 } while (0)
174
175 #define _HAL_HVD_Return(_ret_) \
176 do \
177 { \
178 if (s32HVDMutexID >= 0) \
179 { \
180 OSAL_HVD_MutexRelease(s32HVDMutexID); \
181 } \
182 return _ret_; \
183 } while(0)
184
185 #define _HAL_HVD_Release() \
186 do \
187 { \
188 if (s32HVDMutexID >= 0) \
189 { \
190 OSAL_HVD_MutexRelease(s32HVDMutexID); \
191 } \
192 } while (0)
193 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
194
195 #define _HAL_HVD_MutexCreate()
196 #define _HAL_HVD_MutexDelete()
197 #define _HAL_HVD_Entry()
198 #define _HAL_HVD_Return(_ret) {return _ret;}
199 #define _HAL_HVD_Release()
200
201 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
204 #define IS_TASK_ALIVE(id) ((id) != -1)
205 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
206
207 //------------------------------ MIU SETTINGS ----------------------------------
208 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(4))
209 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
210 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(2))
211 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ3_MASK, m, BIT(1))
212
213 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(4))
214 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
215 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(2))
216 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ3_MASK, m, BIT(1))
217
218 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(4)) == BIT(4))
219 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
220 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(2)) == BIT(2))
221 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL3) & BIT(1)) == BIT(1))
222
223 #if SUPPORT_EVD
224 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
225 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(3))
226 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
227 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(3))
228 #define HVD_EVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(2)) == BIT(2))
229 #define HVD_EVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(3)) == BIT(3))
230 #endif
231
232 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
233 do \
234 { \
235 if (HVD_##miu_clients##_ON_MIU1 == 0) \
236 { \
237 _MaskMiuReq_##miu_clients(mask); \
238 } \
239 else \
240 { \
241 _MaskMiu1Req_##miu_clients(mask); \
242 } \
243 } while (0)
244
245 // check RM is supported or not
246 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
247 #ifdef VDEC3
248 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
249 #else
250 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
251 #endif
252 //-------------------------------------------------------------------------------------------------
253 // Local Structures
254 //-------------------------------------------------------------------------------------------------
255
256 //-------------------------------------------------------------------------------------------------
257 // Local Functions Prototype
258 //-------------------------------------------------------------------------------------------------
259 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
260 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
261 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
262 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
263 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
264 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
265 static MS_U32 _HVD_EX_GetPC(void);
266 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
267 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
268 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
269 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
270 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
271 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
272 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
273 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
274 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
275 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
276 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
277 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
278 static MS_U32 _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
279 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
280 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
281 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
282 static MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id);
283 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
284 #if SUPPORT_EVD
285 static void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable);
286 static MS_BOOL HAL_EVD_EX_DeinitHW(void);
287 #endif
288 #if SUPPORT_G2VP9 && defined(VDEC3)
289 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
290 #endif
291 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
292 #if SUPPORT_G2VP9 && defined(VDEC3)
293 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
294 #endif
295 //-------------------------------------------------------------------------------------------------
296 // Global Variables
297 //-------------------------------------------------------------------------------------------------
298 #if defined (__aeon__)
299 static MS_U32 u32HVDRegOSBase = 0xA0200000;
300 #else
301 static MS_U32 u32HVDRegOSBase = 0xBF200000;
302 #endif
303 #if HAL_HVD_ENABLE_MUTEX_PROTECT
304 MS_S32 s32HVDMutexID = -1;
305 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
306 #endif
307
308
309 #define HVD_EX_STACK_SIZE 4096
310 //-------------------------------------------------------------------------------------------------
311 // Local Variables
312 //-------------------------------------------------------------------------------------------------
313 typedef struct
314 {
315
316 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
317 MS_U8 g_hvd_nal_fill_pair[2][8];
318 MS_U32 u32RV_VLCTableAddr; // offset from Frame buffer start address
319 MS_U16 _u16DispQPtr;
320 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
321
322 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
323 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
324 MS_U32 u32VPUClockType;
325 MS_U32 u32HVDClockType;//160
326 #if SUPPORT_EVD
327 MS_U32 u32EVDClockType;
328 #endif
329 #if SUPPORT_G2VP9 && defined(VDEC3)
330 MS_U32 u32VP9ClockType;
331 #endif
332 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
333
334 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
335 MS_BOOL g_RstFlag;
336 MS_U64 u64pts_real;
337 MS_U32 u32VP8BBUWptr;
338 MS_U32 u32EVDBBUWptr;
339 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
340 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
341 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
342 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
343 //pre_set
344 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
345 } HVD_Hal_CTX;
346
347 HVD_Hal_CTX* pHVDHalContext = NULL;
348 HVD_Hal_CTX gHVDHalContext;
349 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
350
351 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
352 {
353 {FALSE},
354 {FALSE},
355 {FALSE},
356 #ifdef VDEC3
357 {FALSE},
358 #endif
359 };
360
361 //-------------------------------------------------------------------------------------------------
362 // Debug Functions
363 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)364 void HVD_EX_SetRstFlag(MS_BOOL bRst)
365 {
366 pHVDHalContext->g_RstFlag = bRst;
367 }
HVD_EX_GetRstFlag(void)368 MS_BOOL HVD_EX_GetRstFlag(void)
369 {
370 return pHVDHalContext->g_RstFlag;
371 }
372
373 //-------------------------------------------------------------------------------------------------
374 // Local Functions
375 //-------------------------------------------------------------------------------------------------
376
377 #ifdef VDEC3
378 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
379 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)380 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
381 {
382
383 MS_U32 ret = TRUE;
384 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
385
386 if(pCtrl == NULL || pstTaskInfo == NULL)
387 return FALSE;
388
389 pstTaskInfo->u32Id = u32Id;
390
391 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
392 {
393 case E_HVD_INIT_HW_RM:
394 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
395 break;
396 case E_HVD_INIT_HW_VP8:
397 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
398 break;
399 case E_HVD_INIT_HW_MVC:
400 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
401 break;
402 case E_HVD_INIT_HW_HEVC:
403 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
404 break;
405 #if SUPPORT_MSVP9
406 case E_HVD_INIT_HW_VP9:
407 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
408 break;
409 #endif
410 #if SUPPORT_G2VP9
411 case E_HVD_INIT_HW_VP9:
412 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
413 break;
414 #endif
415 default:
416 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
417 break;
418 }
419
420 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
421
422 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
423 {
424 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
425 }
426 else
427 {
428 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
429 }
430
431 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
432
433 #ifdef SUPPORT_EVD
434 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
435 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
436 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
437 #endif
438 return ret;
439
440 }
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)441 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
442 {
443 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
444 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
445 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
446 _HAL_HVD_Entry();
447
448 if(pCtrl == NULL)
449 _HAL_HVD_Return(ret);
450
451 VPU_EX_TaskInfo taskInfo;
452 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
453
454 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
455
456 taskInfo.u8HalId = u8Idx;
457 ret = HAL_VPU_EX_GetBBUId(u32Id,&taskInfo, pCtrl->bNStreamMode);
458
459 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
460 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
461
462 _HAL_HVD_Return(ret);
463 }
464
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)465 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
466 {
467 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
468 MS_BOOL ret = FALSE;
469 _HAL_HVD_Entry();
470
471 if(pCtrl == NULL)
472 _HAL_HVD_Return(ret);
473 VPU_EX_TaskInfo taskInfo;
474 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
475
476 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
477
478 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
479
480 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
481 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
482
483 _HAL_HVD_Return(ret);
484 }
485 #endif
486
487 #if SUPPORT_G2VP9 && defined(VDEC3)
488
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)489 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
490 {
491 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
492 u32Id,
493 E_TASK_PRI_MEDIUM,
494 TRUE,
495 NULL,
496 32, // stack size..
497 "HVD_PostProcess_task");
498
499 if (s32HvdPpTaskId < 0)
500 {
501 HVD_EX_MSG_ERR("Pp Task create failed\n");
502
503 return FALSE;
504 }
505
506 HVD_EX_MSG_DBG("Pp Task create success\n");
507 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
508
509 return TRUE;
510 }
511 #endif
512
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)513 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
514 {
515 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
516 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
517 pstHVDStream->s32HvdPpTaskId = -1;
518 }
519
_HVD_EX_Context_Init_HAL(void)520 static void _HVD_EX_Context_Init_HAL(void)
521 {
522 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
523 pHVDHalContext->u32VPUClockType = 320; ///Note : Max VD_R2 clock in Monaco is only 320MHz
524 ///Note : Max EVD_R2 clock in Monaco is only 384MHz
525
526 const SYS_Info* sysInfo;
527 sysInfo = MDrv_SYS_GetInfo();
528
529 if(sysInfo->Chip.Version == VER_MALDIVES)
530 pHVDHalContext->u32HVDClockType = 288;//160;
531 else
532 pHVDHalContext->u32HVDClockType = 240;//160;
533
534
535 #if SUPPORT_EVD
536 pHVDHalContext->u32EVDClockType = 240;
537 #endif
538 #if SUPPORT_G2VP9 && defined(VDEC3)
539 pHVDHalContext->u32VP9ClockType = 384;
540 #endif
541 #ifdef VDEC3
542 MS_U8 i;
543
544 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
545 {
546 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
547 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
548 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
549 }
550 #else
551 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
552 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
553 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
554 #endif
555 }
556
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)557 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
558 {
559 MS_U16 u16Ret = 0;
560 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
561 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
562 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
563 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
564 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
565
566 #if HVD_ENABLE_MVC
567 if(HAL_HVD_EX_CheckMVCID(u32Id))
568 {
569 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
570 }
571 #endif /// HVD_ENABLE_MVC
572
573 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
574 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
575
576 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
577 {
578 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
579 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
580 }
581 else
582 #ifdef VDEC3
583 if (0 == pCtrl->u32BBUId)
584 #else
585 if (0 == u8TaskId)
586 #endif
587 {
588 //if(pCtrl->InitParams.bColocateBBUMode)
589 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
590 u16Ret = pShm->u32ColocateBBUReadPtr;
591 else
592 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
593 }
594 else
595 {
596 //if(pCtrl->InitParams.bColocateBBUMode)
597 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
598 u16Ret = pShm->u32ColocateBBUReadPtr;
599 else
600 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
601 }
602
603 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
604 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
605
606 return u16Ret;
607 }
608
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)609 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
610 {
611 MS_U16 u16Ret = 0;
612 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
613 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
614 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
615 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
616 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
617
618 #if HVD_ENABLE_MVC
619 if (HAL_HVD_EX_CheckMVCID(u32Id))
620 {
621 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
622 }
623 #endif /// HVD_ENABLE_MVC
624 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
625 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
626
627 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
628 {
629 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
630 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
631 }
632 else
633 #ifdef VDEC3
634 if (0 == pDrvCtrl->u32BBUId)
635 #else
636 if (0 == u8TaskId)
637 #endif
638 {
639 //if(pDrvCtrl->InitParams.bColocateBBUMode)
640 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
641 u16Ret = pShm->u32ColocateBBUWritePtr;
642 else
643 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
644 }
645 else
646 {
647 //if(pDrvCtrl->InitParams.bColocateBBUMode)
648 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
649 u16Ret = pShm->u32ColocateBBUWritePtr;
650 else
651 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
652 }
653
654 return u16Ret;
655 }
656
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)657 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
658 {
659 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
660 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
661
662 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
663 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
664 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
665 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
666 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
667 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
668 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
669 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
670 }
671
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)672 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
673 {
674 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
675 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
676 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
677 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
678 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
679
680 #if HVD_ENABLE_MVC
681 if (HAL_HVD_EX_CheckMVCID(u32Id))
682 {
683 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
684 }
685 #endif /// HVD_ENABLE_MVC
686
687 HVD_EX_MSG_COVERITY("[%s] u8TaskId = %d\n",__FUNCTION__,u8TaskId);//coverity - set_but_not_used: variable "u8TaskId" was set but never used
688
689 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
690 {
691 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
692 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
693 }
694 else
695 #ifdef VDEC3
696 if (0 == pCtrl->u32BBUId)
697 #else
698 if (0 == u8TaskId)
699 #endif
700 {
701 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
702 //if(pCtrl->InitParams.bColocateBBUMode)
703 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
704 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
705 }
706 else
707 {
708 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
709 //if(pCtrl->InitParams.bColocateBBUMode)
710 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
711 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
712 }
713
714 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
715 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
716
717 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
718 }
719
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)720 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
721 {
722 MS_BOOL bResult = TRUE;
723 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
724 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
725
726 switch (u8MBox)
727 {
728 case E_HVD_HI_0:
729 {
730 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
731 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
732 break;
733 }
734 case E_HVD_HI_1:
735 {
736 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
737 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
738 break;
739 }
740 case E_HVD_VPU_HI_0:
741 {
742 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
743 break;
744 }
745 case E_HVD_VPU_HI_1:
746 {
747 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
748 break;
749 }
750 default:
751 {
752 bResult = FALSE;
753 break;
754 }
755 }
756
757 return bResult;
758 }
759
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)760 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
761 {
762 MS_BOOL bResult = TRUE;
763 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
764 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
765
766 switch (u8MBox)
767 {
768 case E_HVD_HI_0:
769 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
770 break;
771 case E_HVD_HI_1:
772 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
773 break;
774 case E_HVD_RISC_0:
775 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
776 break;
777 case E_HVD_RISC_1:
778 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
779 break;
780 case E_HVD_VPU_HI_0:
781 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
782 break;
783 case E_HVD_VPU_HI_1:
784 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
785 break;
786 case E_HVD_VPU_RISC_0:
787 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
788 break;
789 case E_HVD_VPU_RISC_1:
790 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
791 break;
792 default:
793 break;
794 }
795
796 return bResult;
797 }
798
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)799 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
800 {
801 MS_BOOL bResult = TRUE;
802 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
803 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
804
805 switch (u8MBox)
806 {
807 case E_HVD_HI_0:
808 {
809 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
810 break;
811 }
812 case E_HVD_HI_1:
813 {
814 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
815 break;
816 }
817 case E_HVD_RISC_0:
818 {
819 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
820 break;
821 }
822 case E_HVD_RISC_1:
823 {
824 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
825 break;
826 }
827 case E_HVD_VPU_RISC_0:
828 {
829 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
830 break;
831 }
832 case E_HVD_VPU_RISC_1:
833 {
834 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
835 break;
836 }
837 default:
838 {
839 bResult = FALSE;
840 break;
841 }
842 }
843
844 return bResult;
845 }
846
847 #if 0
848 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
849 {
850 switch (u8MBox)
851 {
852 case E_HVD_RISC_0:
853 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
854 break;
855 case E_HVD_RISC_1:
856 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
857 break;
858 case E_HVD_VPU_RISC_0:
859 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
860 break;
861 case E_HVD_VPU_RISC_1:
862 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
863 break;
864 default:
865 break;
866 }
867 }
868 #endif
869
_HVD_EX_GetPC(void)870 static MS_U32 _HVD_EX_GetPC(void)
871 {
872 MS_U32 u32PC = 0;
873 u32PC = HAL_VPU_EX_GetProgCnt();
874 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
875 return u32PC;
876 }
877
_HVD_EX_GetESWritePtr(MS_U32 u32Id)878 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
879 {
880 MS_U32 u32Data = 0;
881 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
882 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
883
884 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
885 {
886 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
887
888 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
889 {
890 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
891
892 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
893 }
894 }
895 else
896 {
897 #if HVD_ENABLE_MVC
898 MS_U8 u8ViewIdx = 0;
899 if(HAL_HVD_EX_CheckMVCID(u32Id))
900 {
901 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
902 }
903 if(u8ViewIdx != 0) /// 2nd ES ptr.
904 {
905 u32Data = pShm->u32ES2WritePtr;
906 }
907 else
908 {
909 u32Data = pShm->u32ESWritePtr;
910 }
911 #else
912 u32Data = pShm->u32ESWritePtr;
913 #endif
914 }
915
916 return u32Data;
917 }
918
919 #define NAL_UNIT_LEN_BITS 21
920 #define NAL_UNIT_OFT_BITS 30
921 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
922 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
923 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
924
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)925 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
926 {
927 MS_U32 u32Data = 0;
928 MS_U8 u8TaskId = 0;
929 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
930 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
931 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
932 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
933 MS_U32 u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
934
935 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
936 #if HVD_ENABLE_MVC
937 if(HAL_HVD_EX_CheckMVCID(u32Id))
938 {
939 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
940 }
941 #endif /// HVD_ENABLE_MVC
942
943 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
944 {
945 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
946 {
947 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
948 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
949 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
950 MS_U32 *u32Adr;
951 MS_U32 u32Tmp;
952
953 if (u16ReadPtr == u16WritePtr)
954 {
955 u32Data = _HVD_EX_GetESWritePtr(u32Id);
956 }
957 else
958 {
959 if (u16ReadPtr)
960 u16ReadPtr--;
961 else
962 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
963
964 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
965
966 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
967 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
968 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
969 u32Data = u32Data | u32Tmp;
970
971 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
972 //while(1);
973 }
974 goto EXIT;
975 }
976 // set reg_poll_nal_rptr 0
977 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
978 // set reg_poll_nal_rptr 1
979 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
980
981 // read reg_nal_rptr_hi
982 #ifdef VDEC3
983 if (0 == pCtrl->u32BBUId)
984 #else
985 if (0 == u8TaskId)
986 #endif
987 {
988 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
989 u32Data >>= 6;
990 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
991 }
992 else
993 {
994 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
995 u32Data >>= 6;
996 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
997 }
998
999 u32Data <<= 3; // unit
1000
1001 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1002 {
1003 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1004
1005 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1006 {
1007 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1008 u32Data = u32ESWptr;
1009 }
1010 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1011 {
1012 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1013 u32Data = u32ESWptr;
1014 }
1015 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1016 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1017 {
1018 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1019 u32Data = u32ESWptr;
1020 }
1021 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1022 && ((u32Data - u32ESWptr) < 32)
1023 && (pCtrl->u32FlushRstPtr == 1))
1024 {
1025 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1026 u32Data = u32ESWptr;
1027 }
1028 }
1029
1030 // remove illegal pointer
1031 #if 1
1032 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1033 {
1034 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1035
1036 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1037 (u32PacketStaddr <
1038 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1039 {
1040 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1041 u32Data = pCtrl->u32LastESRptr;
1042 }
1043 }
1044 #endif
1045 }
1046 else
1047 {
1048 #if HVD_ENABLE_MVC
1049 MS_U8 u8ViewIdx = 0;
1050 if(HAL_HVD_EX_CheckMVCID(u32Id))
1051 {
1052 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1053 }
1054 if(u8ViewIdx != 0) /// 2nd ES ptr.
1055 {
1056 u32Data = pShm->u32ES2ReadPtr;
1057 }
1058 else
1059 {
1060 u32Data = pShm->u32ESReadPtr;
1061 }
1062 #else
1063 u32Data = pShm->u32ESReadPtr;
1064 #endif
1065 }
1066
1067 EXIT:
1068
1069 pCtrl->u32LastESRptr = u32Data;
1070
1071 return u32Data;
1072 }
1073
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1074 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1075 {
1076 MS_U16 u16TimeOut = 0xFFFF;
1077 MS_BOOL bResult = FALSE;
1078
1079 HVD_EX_MSG_DBG("Send ARG 0x%lx to HVD\n", u32Arg);
1080
1081 while (--u16TimeOut)
1082 {
1083 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1084 {
1085 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1086 break;
1087 }
1088 }
1089
1090 return bResult;
1091 }
1092
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1093 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1094 {
1095 MS_U16 u16TimeOut = 0xFFFF;
1096 MS_BOOL bResult = FALSE;
1097 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1098
1099 HVD_EX_MSG_DBG("Send CMD 0x%lx to HVD \n", u32Cmd);
1100
1101 #if HVD_ENABLE_MVC
1102 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1103 {
1104 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1105 }
1106 #endif /// HVD_ENABLE_MVC
1107
1108 HVD_EX_MSG_DBG("Send CMD 0x%lx to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1109
1110 while (--u16TimeOut)
1111 {
1112 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1113 {
1114 u32Cmd |= (u8TaskId << 24);
1115 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1116 break;
1117 }
1118 }
1119 return bResult;
1120 }
1121
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Command,MS_U32 u32CmdArg)1122 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Command, MS_U32 u32CmdArg)
1123 {
1124 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1125 #ifdef VDEC3
1126 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1127 MS_BOOL IsSent = FALSE;
1128 MS_BOOL IsMailBox = FALSE;
1129 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1130
1131 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Command))
1132 {
1133 do {
1134 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1135 if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL)
1136 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%lx arg=0x%lx\n", SentRet,u32Command, u32CmdArg);
1137 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1138 break;
1139 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1140 IsSent = TRUE;
1141 break;
1142 }
1143 else if (HVD_GetSysTime_ms() > u32timeout)
1144 {
1145 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%lx arg=0x%lx\n", u32Command, u32CmdArg);
1146 break;
1147 }
1148 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1149 }
1150 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Command))
1151 {
1152 do {
1153 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1154 if (!SentRet)
1155 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%lx arg=0x%lx\n", SentRet,u32Command, u32CmdArg);
1156 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1157 break;
1158 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1159 IsSent = TRUE;
1160 break;
1161 }
1162 else if (HVD_GetSysTime_ms() > u32timeout)
1163 {
1164 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%lx arg=0x%lx\n", u32Command, u32CmdArg);
1165 break;
1166 }
1167 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1168 }
1169 if (!IsSent) {
1170 IsMailBox = TRUE;
1171 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1172 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1173 #else
1174 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1175 #endif
1176 {
1177 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1178 if (HVD_GetSysTime_ms() > u32timeout)
1179 {
1180 HVD_EX_MSG_ERR("Timeout: cmd=0x%lx arg=0x%lx\n", u32Command, u32CmdArg);
1181 return E_HVD_RETURN_TIMEOUT;
1182 }
1183 #endif
1184
1185 #if 0
1186 if (u32Cmd == E_HVD_CMD_STOP)
1187 {
1188 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1189 #if HVD_ENABLE_MVC
1190 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1191 {
1192 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1193 }
1194 #endif /// HVD_ENABLE_MVC
1195 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1196
1197 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1198 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1199
1200 return E_HVD_RETURN_SUCCESS;
1201 }
1202 #endif
1203
1204 if((HVD_User_Cmd)u32Command < E_DUAL_CMD_BASE)
1205 {
1206 //_HVD_EX_GetPC();
1207 HAL_HVD_EX_Dump_FW_Status(u32Id);
1208 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1209 }
1210 }
1211
1212 #ifdef VDEC3
1213 }
1214 IsSent = FALSE;
1215 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1216 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Command) && !IsMailBox)
1217 {
1218 do {
1219 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Command);
1220 if (!SentRet)
1221 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%lx arg=0x%lx\n", SentRet,u32Command, u32CmdArg);
1222 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1223 break;
1224 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1225 IsSent = TRUE;
1226 break;
1227 }
1228 else if (HVD_GetSysTime_ms() > u32timeout)
1229 {
1230 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%lx arg=0x%lx\n", u32Command, u32CmdArg);
1231 break;
1232 }
1233 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1234 }
1235 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Command) && !IsMailBox)
1236 {
1237 do {
1238 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Command);
1239 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1240 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%lx arg=0x%lx\n", SentRet,u32Command, u32CmdArg);
1241 }
1242 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1243 break;
1244 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1245 IsSent = TRUE;
1246 break;
1247 }
1248 else if (HVD_GetSysTime_ms() > u32timeout)
1249 {
1250 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%lx arg=0x%lx\n", u32Command, u32CmdArg);
1251 break;
1252 }
1253 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1254 }
1255 if (!IsSent)
1256 {
1257 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1258 while (!_HVD_EX_SetCMD(u32Id, u32Command))
1259 #else
1260 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1261
1262 while (!_HVD_EX_SetCMD(u32Id, u32Command))
1263 #endif
1264 {
1265 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1266 if (HVD_GetSysTime_ms() > u32timeout)
1267 {
1268 HVD_EX_MSG_ERR("cmd timeout: %lx\n", u32Command);
1269 return E_HVD_RETURN_TIMEOUT;
1270 }
1271 #endif
1272 if(u32Command < E_DUAL_CMD_BASE)
1273 {
1274 //_HVD_EX_GetPC();
1275 HAL_HVD_EX_Dump_FW_Status(u32Id);
1276 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1277 }
1278 }
1279 #ifdef VDEC3
1280 }
1281 else
1282 {
1283 HAL_HVD_EX_FlushMemory();
1284 }
1285 #endif
1286 return E_HVD_RETURN_SUCCESS;
1287 }
1288
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1289 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1290 {
1291 #if HAL_HVD_ENABLE_MIU_PROTECT
1292 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
1293 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1294 #if SUPPORT_EVD
1295 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1296 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1297 #endif
1298 _HVD_MIU_SetReqMask(HVD_RW, bEnable);
1299 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1300 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1301 //HVD_Delay_ms(1);
1302 #endif
1303 return;
1304 }
1305
1306 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)1307 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
1308 {
1309 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1310
1311 if (u32CodecType == E_HVD_INIT_HW_HEVC
1312 #if SUPPORT_MSVP9
1313 || u32CodecType == E_HVD_INIT_HW_VP9
1314 #endif
1315 )
1316 return TRUE;
1317
1318 return FALSE;
1319 }
1320
_HAL_EX_IS_HVD(MS_U32 u32ModeFlag)1321 static MS_BOOL _HAL_EX_IS_HVD(MS_U32 u32ModeFlag) // VP8 isn't included
1322 {
1323 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1324
1325 if ((u32CodecType == E_HVD_INIT_HW_MVC) ||
1326 (u32CodecType == E_HVD_INIT_HW_AVC) ||
1327 (u32CodecType == E_HVD_INIT_HW_AVS) ||
1328 (u32CodecType == E_HVD_INIT_HW_RM))
1329 return TRUE;
1330
1331 return FALSE;
1332 }
1333
_HAL_EX_BBU_EVD_InUsed(void)1334 static MS_BOOL _HAL_EX_BBU_EVD_InUsed(void)
1335 {
1336 if (!pHVDHalContext)
1337 return FALSE;
1338
1339 MS_U32 i;
1340 MS_BOOL bRet = FALSE;
1341
1342 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1343 {
1344 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1345 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC)
1346 #if SUPPORT_MSVP9
1347 ||(pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP9)
1348 #endif
1349 ))
1350 {
1351 bRet = TRUE;
1352 break;
1353 }
1354 }
1355
1356 return bRet;
1357 }
1358
_HAL_EX_BBU_HVD_InUsed(void)1359 static MS_BOOL _HAL_EX_BBU_HVD_InUsed(void) // VP8 isn't included
1360 {
1361 if (!pHVDHalContext)
1362 return FALSE;
1363
1364 MS_U32 i;
1365 MS_BOOL bRet = FALSE;
1366
1367 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1368 {
1369 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1370 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVC) ||
1371 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVS) ||
1372 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_RM)))
1373 {
1374 bRet = TRUE;
1375 break;
1376 }
1377 }
1378
1379 return bRet;
1380 }
1381
_HAL_EX_BBU_VP8_InUsed(void)1382 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
1383 {
1384 if (!pHVDHalContext)
1385 return FALSE;
1386
1387 MS_U32 i;
1388 MS_BOOL bRet = FALSE;
1389
1390 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1391 {
1392 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
1393 {
1394 bRet = TRUE;
1395 break;
1396 }
1397 }
1398
1399 return bRet;
1400 }
1401
1402 #endif
1403
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1404 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1405 {
1406 MS_U16 u16Reg = 0;
1407 MS_U32 u32StAddr = 0;
1408 #ifdef VDEC3
1409 MS_U32 u32Length = 0;
1410 #endif
1411 //MS_BOOL bBitMIU1 = FALSE;
1412 //MS_BOOL bCodeMIU1 = FALSE;
1413 MS_U8 u8BitMiuSel = 0;
1414 MS_U8 u8CodeMiuSel = 0;
1415 MS_U8 u8FBMiuSel = 0;
1416 MS_U32 u32BitStartOffset;
1417 MS_U32 u32CodeStartOffset;
1418 MS_U32 u32FBStartOffset;
1419
1420 MS_U8 u8TaskId = 0;
1421 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1422 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1423 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1424 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1425
1426 // MS_U32 u32TmpStartOffset;
1427 MS_U8 u8TmpMiuSel;
1428
1429
1430
1431 if(pCtrl == NULL) return;
1432
1433 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1434 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1435 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1436
1437 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1438 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1439 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1440 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1441 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1442 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1443 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1444 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1445 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1446 (u8FBMiuSel << VDEC_PPIN_MIUSEL));
1447
1448 if (u8BitMiuSel != u8CodeMiuSel)
1449 {
1450 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
1451 }
1452 else
1453 {
1454 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
1455 }
1456
1457 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1458 {
1459 #ifdef VDEC3
1460 if (!_HAL_EX_BBU_VP8_InUsed())
1461 #endif
1462 {
1463 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1464
1465 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1466 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1467 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1468
1469 u32StAddr += VP8_BBU_TBL_SIZE;
1470
1471 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1472 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1473 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1474 }
1475
1476 // ES buffer
1477 #ifdef VDEC3
1478 if(pCtrl->bNStreamMode)
1479 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1480 else
1481 #endif
1482 u32StAddr = u32BitStartOffset;
1483
1484 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1485
1486 #ifdef VDEC3
1487 if (!_HAL_EX_BBU_VP8_InUsed())
1488 #endif
1489 {
1490 HVD_EX_MSG_ERR("u32FBStartOffset = 0x%lx ESB start addr=%lx\n", u32FBStartOffset, u32StAddr);
1491
1492 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1493 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1494
1495 #ifdef VDEC3
1496 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1497 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1498 #else
1499 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1500 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1501 #endif
1502
1503 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1504 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1505 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1506 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1507 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1508 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1509 }
1510
1511 return;
1512 }
1513
1514 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1515
1516 HVD_EX_MSG_COVERITY("[%d]NAL start addr=%lx\n",u8TaskId, u32StAddr);
1517
1518 #ifdef VDEC3
1519 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1520 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1521 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1522 {
1523 if (pCtrl->u32BBUId == 0)
1524 {
1525 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1526 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1527 // -1 is for NAL_TAB_LEN counts from zero.
1528 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1529 }
1530 else
1531 {
1532 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1533 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1534 // -1 is for NAL_TAB_LEN counts from zero.
1535 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1536 }
1537 }
1538 #else
1539 if (0 == u8TaskId)
1540 {
1541 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1542 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1543 // -1 is for NAL_TAB_LEN counts from zero.
1544 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1545 }
1546 else
1547 {
1548 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1549 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1550 // -1 is for NAL_TAB_LEN counts from zero.
1551 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1552 }
1553 #endif
1554
1555 // ES buffer
1556 #ifdef VDEC3
1557 if(!pCtrl->bNStreamMode || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1558 {
1559 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1560 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1561 }
1562 else
1563 {
1564 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1565 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1566 }
1567 #else
1568 u32StAddr = u32BitStartOffset;
1569 #endif
1570
1571 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1572
1573 HVD_EX_MSG_COVERITY("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1574
1575 #ifdef VDEC3
1576 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1577 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1578 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1579 {
1580 if (pCtrl->u32BBUId == 0)
1581 {
1582 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1583 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1584
1585 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1586 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1587 }
1588 else
1589 {
1590 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1591 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1592
1593 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1594 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1595 }
1596 }
1597 #else
1598 if (0 == u8TaskId)
1599 {
1600 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1601 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1602
1603 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1604 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1605 }
1606 else
1607 {
1608 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1609 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1610
1611 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1612 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1613 }
1614 #endif
1615
1616 // others
1617 #ifdef VDEC3
1618 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1619 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1620 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1621 {
1622 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1623
1624 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1625 {
1626 if (pCtrl->u32BBUId == 0)
1627 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1628 else
1629 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1630 }
1631 else
1632 {
1633 if (pCtrl->u32BBUId == 0)
1634 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1635 else
1636 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1637 }
1638 if (_HVD_EX_IS_BBU_TSP_MODE(u32Id))
1639 {
1640 HVD_PRINT("\033[1;32m[%s] %d u16Reg &= ~HVD_REG_BBU_TSP_INPUT\033[m\n",__FUNCTION__,__LINE__);
1641 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1642 }
1643
1644 if (pCtrl->u32BBUId == 0)
1645 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1646 else
1647 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1648
1649 if (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // RM
1650 {
1651 if (pCtrl->u32BBUId == 0) // force BBU to remove nothing, RM only
1652 u16Reg |= HVD_REG_BBU_PASER_DISABLE;
1653 else
1654 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2;
1655 }
1656 #if SUPPORT_MSVP9
1657 else if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1658 {
1659 if (pCtrl->u32BBUId == 0)
1660 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03;
1661 else
1662 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03_BS2;
1663 }
1664 #endif
1665 else // AVS or AVC or HEVC
1666 {
1667 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1668 {
1669 if (pCtrl->u32BBUId == 0)
1670 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1671 else
1672 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1673 }
1674 else // start code remained
1675 {
1676 if (pCtrl->u32BBUId == 0)
1677 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1678 else
1679 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1680 }
1681 }
1682
1683 if (pCtrl->u32BBUId == 0)
1684 {
1685 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1686 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1687 }
1688 else
1689 {
1690 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1691 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1692 }
1693 }
1694 #else
1695 if (0 == u8TaskId)
1696 {
1697 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1698
1699 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1700 {
1701 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1702 }
1703 else
1704 {
1705 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1706 }
1707 if (_HVD_EX_IS_BBU_TSP_MODE(u32Id))
1708 {
1709 HVD_PRINT("\033[1;31m][%s][%s] %d u16Reg &= ~HVD_REG_BBU_TSP_INPUT\033[m\n",__FILE__,__FUNCTION__,__LINE__);
1710 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1711 }
1712
1713 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1714
1715 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1716 {
1717 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1718 }
1719 else // AVS or AVC
1720 {
1721 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1722 {
1723 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1724 }
1725 else // start code remained
1726 {
1727 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1728 }
1729 }
1730
1731 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1732
1733 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1734 }
1735 else
1736 {
1737 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1738
1739 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1740 {
1741 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1742 }
1743 else
1744 {
1745 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1746 }
1747
1748 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1749
1750 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1751 {
1752 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1753 }
1754 else // AVS or AVC
1755 {
1756 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1757 {
1758 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1759 }
1760 else // start code remained
1761 {
1762 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1763 }
1764 }
1765
1766 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1767
1768 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1769 }
1770 #endif
1771
1772 #if (HVD_ENABLE_MVC)
1773 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1774 {
1775 /// Used sub stream to record sub view data.
1776 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1777 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1778
1779 if (u8BitMiuSel != u8CodeMiuSel)
1780 {
1781 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
1782 }
1783 else
1784 {
1785 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
1786 }
1787
1788
1789 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", u32StAddr);
1790 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
1791 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
1792 // -1 is for NAL_TAB_LEN counts from zero.
1793 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1794
1795 // ES buffer
1796 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1797
1798 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", u32StAddr, pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1799 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1800 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1801
1802 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1803 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1804
1805 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1806 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1807 {
1808 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1809 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1810 }
1811 else
1812 {
1813 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1814 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1815 }
1816 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1817 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1818 {
1819 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1820 }
1821 else // AVS or AVC
1822 {
1823 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1824 {
1825 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1826 }
1827 else // start code remained
1828 {
1829 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1830 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1831 }
1832 }
1833 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1834 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1835 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1836 }
1837 #endif
1838
1839 // MIF offset
1840 #if 0
1841 {
1842 MS_U16 offaddr = 0;
1843 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1844 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1845 {
1846 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1847 }
1848 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1849 offaddr = (MS_U16) ((u32StAddr) >> 20);
1850 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1851 //0x1FF; // 9 bits(L + H)
1852 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1853 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1854 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1855 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1856 {
1857 u16Reg |= HVD_REG_MIF_OFFSET_H;
1858 }
1859 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1860 }
1861 #endif
1862 }
1863
1864 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1865 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1866 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1867 {
1868 MS_U16 u16Reg = 0;
1869 MS_U32 u32StAddr = 0;
1870 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1871 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1872 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1873
1874 if(pCtrl == NULL) return;
1875
1876 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1877 {
1878 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1879
1880 // ES buffer
1881 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1882
1883 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1884 {
1885 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1886 }
1887
1888 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1889 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1890
1891 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1892 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1893
1894 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1895 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1896 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1897 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1898 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1899 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1900
1901 return;
1902 }
1903
1904 // ES buffer
1905 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1906
1907 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1908 {
1909 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1910 }
1911
1912 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1913
1914 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1915 {
1916 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1917 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1918
1919 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1920 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1921 }
1922 else
1923 {
1924 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1925 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1926
1927 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1928 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1929 }
1930 }
1931 #endif
1932
_HVD_EX_GetESLevel(MS_U32 u32Id)1933 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1934 {
1935 MS_U32 u32Wptr = 0;
1936 MS_U32 u32Rptr = 0;
1937 MS_U32 u32CurMBX = 0;
1938 MS_U32 u32ESsize = 0;
1939 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1940 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1941
1942 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1943 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1944 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1945
1946 if (u32Rptr >= u32Wptr)
1947 {
1948 u32CurMBX = u32Rptr - u32Wptr;
1949 }
1950 else
1951 {
1952 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1953 }
1954
1955 if (u32CurMBX == 0)
1956 {
1957 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1958 }
1959 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1960 {
1961 u32Ret = E_HVD_ESB_LEVEL_OVER;
1962 }
1963 else
1964 {
1965 u32CurMBX = u32ESsize - u32CurMBX;
1966 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1967 {
1968 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1969 }
1970 }
1971
1972 return u32Ret;
1973 }
1974
_HVD_EX_GetESQuantity(MS_U32 u32Id)1975 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1976 {
1977 MS_U32 u32Wptr = 0;
1978 MS_U32 u32Rptr = 0;
1979 MS_U32 u32ESsize = 0;
1980 MS_U32 u32Ret = 0;
1981 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1982
1983 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1984 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1985 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1986
1987
1988 if(u32Wptr >= u32Rptr)
1989 {
1990 u32Ret = u32Wptr - u32Rptr;
1991 }
1992 else
1993 {
1994 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1995 }
1996 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1997 return u32Ret;
1998 }
1999
2000
2001
2002 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2003 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2004 #else
2005 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2006 #endif
2007 {
2008 MS_U32 u32FirmVer = 0;
2009 MS_U32 u32Timeout = 20000;
2010 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2011
2012 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04lx\n", HAL_HVD_EX_GetHWVersionID());
2013
2014 #if HVD_ENABLE_TIME_MEASURE
2015 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2016 #endif
2017
2018 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2019
2020 VPU_EX_FWCodeCfg fwCfg;
2021 VPU_EX_TaskInfo taskInfo;
2022 VPU_EX_VLCTblCfg vlcCfg;
2023 #ifdef VDEC3
2024 VPU_EX_FBCfg fbCfg;
2025 #endif
2026 VPU_EX_NDecInitPara nDecInitPara;
2027
2028 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2029 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2030 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2031 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2032 #ifdef VDEC3_FB
2033 nDecInitPara.pVLCCfg = NULL;
2034 #else
2035 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2036 {
2037 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2038 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2039 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2040 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2041 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2042 nDecInitPara.pVLCCfg = &vlcCfg;
2043 }
2044 #endif
2045 nDecInitPara.pFWCodeCfg = &fwCfg;
2046 nDecInitPara.pTaskInfo = &taskInfo;
2047 #ifdef VDEC3
2048 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2049 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2050
2051 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2052 {
2053 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2054 }
2055
2056 nDecInitPara.pFBCfg = &fbCfg;
2057 #endif
2058
2059 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2060 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2061 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2062 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2063 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2064
2065 taskInfo.u32Id = u32Id;
2066
2067 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2068 {
2069 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2070 }
2071 #ifdef VDEC3
2072 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
2073 {
2074 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2075 }
2076 #if SUPPORT_MSVP9
2077 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2078 {
2079 HVD_PRINT("SUPPORT_MSVP9\n");
2080 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2081 }
2082 #endif
2083 #if SUPPORT_G2VP9
2084 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2085 {
2086 HVD_PRINT("SUPPORT_G2VP9\n");
2087 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2088 }
2089 #endif
2090 #endif
2091 else
2092 {
2093 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2094 }
2095
2096 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2097
2098 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2099 {
2100 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2101 }
2102 else
2103 {
2104 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2105 }
2106 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2107
2108 #ifdef SUPPORT_EVD
2109 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2110 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2111 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2112 #endif
2113
2114 if(TRUE == HVD_EX_GetRstFlag())
2115 {
2116 //Delete task for Rst
2117 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2118 {
2119 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2120 }
2121 HVD_EX_SetRstFlag(FALSE);
2122 }
2123
2124 const SYS_Info* sysInfo;
2125 sysInfo = MDrv_SYS_GetInfo();
2126 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
2127 {
2128 if(sysInfo->Chip.Version == VER_MUNICH)
2129 {
2130 HVD_EX_MSG_ERR("Munich does not support VP8 codec!!\n");
2131 return FALSE;
2132 }
2133 }
2134
2135 #ifdef VDEC3
2136 #if SUPPORT_MSVP9
2137 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2138 {
2139 if(sysInfo->Chip.Version == VER_MUNICH)
2140 {
2141 HVD_EX_MSG_ERR("Munich does not support VP9 codec!!\n");
2142 return FALSE;
2143 }
2144 }
2145 #endif
2146 #endif
2147
2148 #ifdef VDEC3
2149 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2150 #else
2151 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2152 #endif
2153 {
2154 HVD_EX_MSG_ERR("Task create fail!\n");
2155
2156 return FALSE;
2157 }
2158
2159 while (u32Timeout)
2160 {
2161 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2162
2163 if (u32FirmVer != 0)
2164 {
2165 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2166 break;
2167 }
2168 u32Timeout--;
2169 HVD_Delay_ms(1);
2170 }
2171
2172 #ifdef VDEC3_FB
2173 #if HVD_ENABLE_RV_FEATURE
2174 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2175
2176 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2177 {
2178 if(pShm->u32RM_VLCTableAddr == 0) {
2179 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2180 }
2181 else
2182 {
2183 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr+pShm->u32RM_VLCTableAddr));
2184 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2185 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2186 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2187 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2188 nDecInitPara.pVLCCfg = &vlcCfg;
2189 }
2190 }
2191
2192 if (nDecInitPara.pVLCCfg)
2193 {
2194 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2195 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2196 {
2197 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2198 return FALSE;
2199 }
2200 }
2201 #endif
2202 #endif
2203 if (u32Timeout > 0)
2204 {
2205 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2206
2207 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2208
2209 #ifdef VDEC3
2210 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2211 {
2212 case E_HVD_INIT_HW_AVC:
2213 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2214 break;
2215 case E_HVD_INIT_HW_AVS:
2216 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2217 break;
2218 case E_HVD_INIT_HW_RM:
2219 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2220 break;
2221 case E_HVD_INIT_HW_MVC:
2222 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2223 break;
2224 case E_HVD_INIT_HW_VP8:
2225 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2226 break;
2227 case E_HVD_INIT_HW_MJPEG:
2228 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2229 break;
2230 case E_HVD_INIT_HW_VP6:
2231 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2232 break;
2233 case E_HVD_INIT_HW_HEVC:
2234 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2235 break;
2236 case E_HVD_INIT_HW_VP9:
2237 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2238 break;
2239 default:
2240 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2241 break;
2242 }
2243 #endif
2244
2245 HVD_EX_MSG_INF("FW version binary=0x%lx, if=0x%lx\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2246 }
2247 else
2248 {
2249 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2250 HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2251
2252 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2253 {
2254 HVD_EX_MSG_ERR("Task delete fail!\n");
2255 }
2256
2257 return FALSE;
2258 }
2259
2260 #if HVD_ENABLE_TIME_MEASURE
2261 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2262 #endif
2263
2264 return TRUE;
2265 }
2266
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2267 static MS_U32 _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2268 {
2269 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2270 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2271 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2272 {
2273 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2274 }
2275 else
2276 {
2277 return *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2278 }
2279 }
2280
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2281 static MS_U32 _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2282 {
2283 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2284 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2285
2286 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2287 {
2288 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2289 }
2290 else
2291 {
2292 return *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2293 }
2294 }
2295
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2296 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2297 {
2298 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2299 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2300
2301 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2302 {
2303 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2304 {
2305 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2306 }
2307 }
2308 else
2309 {
2310 *((MS_U32 *) MsOS_PA2KSEG1(pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2311 }
2312 }
2313
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2314 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2315 {
2316 MS_U32 u32PTSWptr = HVD_U32_MAX;
2317 MS_U32 u32PTSRptr = HVD_U32_MAX;
2318 MS_U32 u32DestAddr = 0;
2319 HVD_PTS_Entry PTSEntry;
2320 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2321 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2322 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2323
2324 // update R & W ptr
2325 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2326
2327 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", u32PTSRptr, _HVD_EX_GetPTSTableWptr(u32Id));
2328
2329 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2330 {
2331 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%lx) \n", u32PTSRptr,
2332 (MS_U32) MAX_PTS_TABLE_SIZE);
2333 return E_HVD_RETURN_FAIL;
2334 }
2335
2336 // check queue is full or not
2337 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2338 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2339
2340 if (u32PTSWptr == u32PTSRptr)
2341 {
2342 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", u32PTSRptr,
2343 u32PTSWptr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2344 return E_HVD_RETURN_FAIL;
2345 }
2346
2347 // add one PTS entry
2348 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2349 PTSEntry.u32ID_L = pInfo->u32ID_L;
2350 PTSEntry.u32ID_H = pInfo->u32ID_H;
2351 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2352
2353 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2354
2355 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", MsOS_VA2PA(u32DestAddr));
2356
2357 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2358
2359 HAL_HVD_EX_FlushMemory();
2360
2361 // update Write ptr
2362 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2363
2364 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2365
2366 return E_HVD_RETURN_SUCCESS;
2367 }
2368
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2369 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2370 {
2371 //---------------------------------------------------
2372 // item format in nal table:
2373 // reserved |borken| u32NalOffset | u32NalLen
2374 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2375 //---------------------------------------------------
2376 MS_U32 u32Adr = 0;
2377 MS_U32 u32BBUNewWptr = 0;
2378 MS_U8 item[8];
2379 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2380 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2381 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2382 MS_U32 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2383
2384 #if HVD_ENABLE_MVC
2385 if(HAL_HVD_EX_CheckMVCID(u32Id))
2386 {
2387 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2388 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2389 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2390 {
2391 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2392 }
2393 }
2394 #endif /// HVD_ENABLE_MVC
2395
2396 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2397 {
2398 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2399 }
2400 else
2401 {
2402 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2403 }
2404 u32BBUNewWptr++;
2405 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2406
2407 // prepare nal entry
2408
2409 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2410 {
2411 // NAL len 22 bits , HEVC level5 constrain
2412 item[0] = u32NalLen & 0xff;
2413 item[1] = (u32NalLen >> 8) & 0xff;
2414 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2415 item[3] = (u32NalOffset >> 2) & 0xff;
2416 item[4] = (u32NalOffset >> 10) & 0xff;
2417 item[5] = (u32NalOffset >> 18) & 0xff;
2418 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2419 item[7] = 0;
2420 }
2421 else
2422 {
2423 item[0] = u32NalLen & 0xff;
2424 item[1] = (u32NalLen >> 8) & 0xff;
2425 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2426 item[3] = (u32NalOffset >> 3) & 0xff;
2427 item[4] = (u32NalOffset >> 11) & 0xff;
2428 item[5] = (u32NalOffset >> 19) & 0xff;
2429 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2430 item[7] = 0;
2431 }
2432
2433 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2434 {
2435 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2436 }
2437 else
2438 {
2439 // add nal entry
2440 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2441 }
2442
2443 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2444
2445 HAL_HVD_EX_FlushMemory();
2446
2447 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%lx\n", MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2448
2449 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2450 {
2451 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2452 }
2453 else
2454 {
2455 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2456 }
2457
2458 return E_HVD_RETURN_SUCCESS;
2459 }
2460
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2461 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2462 {
2463 MS_U8 item[8];
2464 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2465 MS_U32 u32Adr = 0;
2466 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2467 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2468 MS_U32 u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2469
2470 /*
2471 printf("nal2 offset=0x%x, len=0x%x\n",
2472 u32NalOffset2, u32NalLen2);
2473 */
2474
2475 item[0] = u32NalLen2 & 0xff;
2476 item[1] = (u32NalLen2 >> 8) & 0xff;
2477 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2478 item[3] = (u32NalOffset2 >> 3) & 0xff;
2479 item[4] = (u32NalOffset2 >> 11) & 0xff;
2480 item[5] = (u32NalOffset2 >> 19) & 0xff;
2481 item[6] = (u32NalOffset2 >> 27) & 0x07;
2482 item[7] = 0;
2483
2484 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2485 {
2486 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2487 }
2488 else
2489 {
2490 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2491 }
2492
2493 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2494
2495 HAL_HVD_EX_FlushMemory();
2496
2497 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2498 }
2499
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2500 static MS_U32 _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2501 {
2502 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2503 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2504
2505 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2506 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) )
2507 {
2508 MS_U16 i;
2509 MS_U32 u32VUIAddr;
2510 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2511
2512 HAL_HVD_EX_ReadMemory();
2513 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2514
2515 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2516 {
2517 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2518 {
2519 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2520 }
2521 else
2522 {
2523 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2524 }
2525 pData++;
2526 }
2527 }
2528 else
2529 {
2530 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2531 }
2532
2533 return (MS_U32) &(pHVDHalContext->g_hvd_VUIINFO);
2534 }
2535
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2536 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2537 {
2538 MS_U32 u32ReadPtr = 0;
2539 MS_U32 eRet = 0;
2540 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2541 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2542
2543 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2544 MS_U32 u32WritePtr = 0;
2545
2546 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2547 {
2548 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2549 }
2550 else
2551 {
2552 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2553 }
2554
2555 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%lx, bbu wptr=%lx\n", u8Idx, u32ReadPtr, u32WritePtr);
2556
2557 if (u32WritePtr >= u32ReadPtr)
2558 {
2559 eRet = u32WritePtr - u32ReadPtr;
2560 }
2561 else
2562 {
2563 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2564 }
2565
2566 #if 0
2567 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2568 {
2569 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2570 }
2571 else
2572 {
2573 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2574 }
2575
2576 #endif
2577 return eRet;
2578 }
2579
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2580 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2581 {
2582 MS_U32 u32ReadPtr = 0;
2583 MS_U32 eRet = 0;
2584 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2585
2586 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2587
2588 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2589 {
2590 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%lx) \n", u32ReadPtr,
2591 (MS_U32) MAX_PTS_TABLE_SIZE);
2592 return 0;
2593 }
2594
2595 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2596
2597 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2598 {
2599 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2600 }
2601 else
2602 {
2603 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2604 }
2605
2606 return eRet;
2607 }
2608
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2609 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2610 {
2611 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2612 MS_U16 u16QNum = pShm->u16DispQNumb;
2613 MS_U16 u16QPtr = pShm->u16DispQPtr;
2614 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2615
2616 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
2617 #if (HVD_ENABLE_MVC)
2618 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2619
2620 if(bMVC)
2621 {
2622 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2623 {
2624 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2625 MS_U16 u16UsedFrm = 0;
2626
2627 if (u16RealQPtr != u16QPtr)
2628 {
2629 if (u16RealQPtr > u16QPtr)
2630 {
2631 u16UsedFrm = u16RealQPtr - u16QPtr;
2632 }
2633 else
2634 {
2635 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2636 }
2637 }
2638
2639 if (u16QNum > u16UsedFrm)
2640 {
2641 volatile HVD_Frm_Information *pHvdFrm;
2642
2643 u16QNum -= u16UsedFrm;
2644 u16QPtr = u16RealQPtr;
2645 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2646
2647 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
2648 {
2649 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
2650
2651 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2652 {
2653 return NULL;
2654 }
2655 }
2656
2657 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2658 {
2659 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2660 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2661
2662 if ((u16QPtr%2) == 0)
2663 {
2664 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2665 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2666 }
2667 else
2668 {
2669 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2670 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2671 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2672 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2673 }
2674
2675 u16QPtr++;
2676 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2677 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2678
2679 return (HVD_Frm_Information*)(MS_U32)pHvdFrm;
2680 }
2681 }
2682
2683 return NULL;
2684 }
2685
2686 /* Add for Mobile Platform by Ted Sun */
2687 #if 0
2688 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
2689 {
2690 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
2691 }
2692 #endif
2693
2694 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2695 //search the next frame to display
2696 while (u16QNum > 0)
2697 {
2698 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2699 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2700 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2701
2702 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2703 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2704 {
2705 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2706 /// Check the depned view was initial when Output the base view.
2707 if((u16QPtr%2) == 0)
2708 {
2709 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2710 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2711 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2712 {
2713 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2714 ///printf("Return NULL.\n");
2715 return NULL;
2716 }
2717 }
2718
2719 //printf("V:%d.\n",u16QPtr);
2720 pHVDHalContext->_u16DispQPtr = u16QPtr;
2721 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2722 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%ld\n", u16QPtr,
2723 (MS_U32) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2724 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2725 return (HVD_Frm_Information *)(MS_U32) pHVDHalContext->pHvdFrm;
2726 }
2727
2728 u16QNum--;
2729 //go to next frame in the dispQ
2730 u16QPtr++;
2731
2732 if (u16QPtr >= pShm->u16DispQSize)
2733 {
2734 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2735 }
2736 }
2737 }
2738 else
2739 #endif ///HVD_ENABLE_MVC
2740 {
2741 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2742
2743 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2744 {
2745
2746 while (u16QNum != 0)
2747 {
2748 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2749
2750 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2751 {
2752 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2753 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2754 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2755 return (HVD_Frm_Information*)(MS_U32)pHvdFrm;
2756 }
2757 u16QNum--;
2758 //go to next frame in the dispQ
2759 u16QPtr++;
2760
2761 if (u16QPtr == pShm->u16DispQSize)
2762 {
2763 u16QPtr = 0; //wrap to the begin
2764 }
2765
2766 }
2767
2768
2769
2770 return NULL;
2771 }
2772 /* Add for Mobile Platform by Ted Sun */
2773 #if 0
2774 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
2775 {
2776 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
2777 }
2778 #endif
2779 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2780 //search the next frame to display
2781 while (u16QNum != 0)
2782 {
2783 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2784
2785 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2786 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2787 {
2788 pHVDHalContext->_u16DispQPtr = u16QPtr;
2789 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2790 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%ld\n", u16QPtr,
2791 (MS_U32) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2792 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2793 return (HVD_Frm_Information *)(MS_U32) pHVDHalContext->pHvdFrm;
2794 }
2795
2796 u16QNum--;
2797 //go to next frame in the dispQ
2798 u16QPtr++;
2799
2800 if (u16QPtr == pShm->u16DispQSize)
2801 {
2802 u16QPtr = 0; //wrap to the begin
2803 }
2804 }
2805 }
2806
2807 return NULL;
2808 }
2809
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2810 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2811 {
2812 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2813 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2814 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2815 {
2816 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2817 if(pVsyncBridgeExt != NULL)
2818 {
2819 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2820 }
2821 }
2822 return pFrmInfoExt;
2823 }
2824
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2825 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2826 {
2827 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2828 MS_U64 u64Ret = 0;
2829 #if SUPPORT_EVD
2830 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2831 #if SUPPORT_MSVP9
2832 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2833 #endif
2834 #endif
2835
2836 #if SUPPORT_EVD
2837 if (isEVD)
2838 {
2839 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2840 }
2841 else
2842 #endif
2843 #if SUPPORT_G2VP9
2844 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2845 {
2846 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2847 }
2848 else
2849 #endif
2850 {
2851 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2852 }
2853
2854 return u64Ret;
2855 }
2856
2857 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2858 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2859 {
2860 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2861 MS_U16 u16QNum = pShm->u16DispQNumb;
2862 MS_U16 u16QPtr = pShm->u16DispQPtr;
2863 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2864
2865 #if (HVD_ENABLE_MVC)
2866 if (HAL_HVD_EX_CheckMVCID(u32Id))
2867 {
2868 if (u16QNum == 1) return TRUE;
2869 }
2870 #endif
2871
2872 while (u16QNum != 0)
2873 {
2874 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2875 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2876 {
2877 return FALSE;
2878 }
2879 u16QNum--;
2880 u16QPtr++;
2881 if (u16QPtr == pShm->u16DispQSize)
2882 {
2883 u16QPtr = 0; //wrap to the begin
2884 }
2885 }
2886
2887 return TRUE;
2888 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2889 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2890 {
2891 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2892
2893 return &(_pHVDCtrls[u8DrvId]);
2894 }
2895
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2896 static MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
2897 {
2898 MS_U8 u8OffsetIdx = 0;
2899 MS_U8 u8SidBaseMask = 0xF0;
2900 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
2901
2902 switch (eSidBase)
2903 {
2904 case E_HAL_HVD_MAIN_STREAM_BASE:
2905 {
2906 u8OffsetIdx = 0;
2907 break;
2908 }
2909 case E_HAL_VPU_SUB_STREAM_BASE:
2910 {
2911 u8OffsetIdx = 1;
2912 break;
2913 }
2914 case E_HAL_VPU_MVC_STREAM_BASE:
2915 {
2916 u8OffsetIdx = 0;
2917 break;
2918 }
2919 #ifdef VDEC3
2920 case E_HAL_VPU_N_STREAM_BASE:
2921 {
2922 u8OffsetIdx = (u32Id>>8) & 0xF;
2923 break;
2924 }
2925 #endif
2926 default:
2927 {
2928 u8OffsetIdx = 0;
2929 break;
2930 }
2931 }
2932
2933 return u8OffsetIdx;
2934 }
2935 /*
2936 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
2937 {
2938 MS_U32 i = 0;
2939 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
2940 {
2941 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
2942 {
2943 return TRUE;
2944 }
2945 }
2946 return FALSE;
2947 }
2948 */
2949
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)2950 MS_U32 HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
2951 {
2952 MS_U32 u32PhyAddr = 0x0;
2953 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2954
2955 if (pCtrl->MemMap.u32CodeBufAddr == 0)
2956 {
2957 return 0;
2958 }
2959
2960 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
2961
2962 if (u32PhyAddr == 0xFFFFFFFFUL)
2963 {
2964 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2965 }
2966 else
2967 {
2968 // TEE, common + share_info
2969 u32PhyAddr += COMMON_AREA_SIZE;
2970 }
2971
2972 return MsOS_PA2KSEG1(u32PhyAddr);
2973 }
2974 /*
2975 void HAL_HVD_MVDMiuClientSel(MS_U8 u8MiuSel)
2976 {
2977 if (u8MiuSel == 0)
2978 {
2979 _HVD_WriteWordMask(MIU_CLIENT_SELECT_GP2, 0, MIU_CLIENT_SELECT_GP2_MVD);
2980 }
2981 else
2982 {
2983 _HVD_WriteWordMask(MIU_CLIENT_SELECT_GP2, MIU_CLIENT_SELECT_GP2_MVD, MIU_CLIENT_SELECT_GP2_MVD);
2984 }
2985 }
2986 */
2987
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)2988 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
2989 {
2990 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2991 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2992
2993 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
2994 {
2995 return 0;
2996 }
2997
2998 MS_PHY u32PhyAddr = 0x0;
2999 #if 0
3000 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3001
3002 if (u32PhyAddr == 0xFFFFFFFF)
3003 {
3004 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3005 }
3006 #endif
3007 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3008 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3009
3010 return MsOS_PA2KSEG1(u32PhyAddr);
3011 }
3012
3013
3014 #if SUPPORT_G2VP9 && defined(VDEC3)
3015
3016
3017 #ifdef __ARM_NEON__
3018 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3019 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3020 {
3021 uint32x4x4_t data, data2;
3022 MS_U8* raster2 = raster + tile_w * 4;
3023
3024 data = vld4q_u32((const uint32_t *)tile);
3025 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3026
3027 vst1q_u32((uint32_t *)raster, data.val[0]);
3028 raster += stride;
3029 vst1q_u32((uint32_t *)raster, data.val[1]);
3030 raster += stride;
3031 vst1q_u32((uint32_t *)raster, data.val[2]);
3032 raster += stride;
3033 vst1q_u32((uint32_t *)raster, data.val[3]);
3034
3035
3036 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3037 raster2 += stride;
3038 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3039 raster2 += stride;
3040 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3041 raster2 += stride;
3042 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3043 }
3044 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3045 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3046 {
3047 MS_U8* tile0 = tile;
3048 MS_U8* tile1 = tile+16;
3049 MS_U8* tile2 = tile+32;
3050 MS_U8* tile3 = tile+48;
3051 int i;
3052
3053 for (i=0; i<4; i++) {
3054 raster[i] = tile0[i];
3055 raster[4+i] = tile1[i];
3056 raster[8+i] = tile2[i];
3057 raster[12+i] = tile3[i];
3058 }
3059
3060 for (i=0; i<4; i++) {
3061 raster[stride+i] = tile0[4+i];
3062 raster[stride+4+i] = tile1[4+i];
3063 raster[stride+8+i] = tile2[4+i];
3064 raster[stride+12+i] = tile3[4+i];
3065 }
3066
3067 for (i=0; i<4; i++) {
3068 raster[2*stride+i] = tile0[8+i];
3069 raster[2*stride+4+i] = tile1[8+i];
3070 raster[2*stride+8+i] = tile2[8+i];
3071 raster[2*stride+12+i] = tile3[8+i];
3072 }
3073
3074 for (i=0; i<4; i++) {
3075 raster[3*stride+i] = tile0[12+i];
3076 raster[3*stride+4+i] = tile1[12+i];
3077 raster[3*stride+8+i] = tile2[12+i];
3078 raster[3*stride+12+i] = tile3[12+i];
3079 }
3080 }
3081 #endif
3082
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3083 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3084 {
3085 return y * stride * h + x * w * h;
3086 }
3087
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3088 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3089 {
3090 return y * stride * h + x * w;
3091 }
3092
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3093 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3094 {
3095 raster[0] = tile[0];
3096 raster[1] = tile[1];
3097 raster[2] = tile[2];
3098 raster[3] = tile[3];
3099 raster[stride] = tile[4];
3100 raster[stride + 1] = tile[5];
3101 raster[stride + 2] = tile[6];
3102 raster[stride + 3] = tile[7];
3103 raster[2 * stride] = tile[8];
3104 raster[2 * stride + 1] = tile[9];
3105 raster[2 * stride + 2] = tile[10];
3106 raster[2 * stride + 3] = tile[11];
3107 raster[3 * stride] = tile[12];
3108 raster[3 * stride + 1] = tile[13];
3109 raster[3 * stride + 2] = tile[14];
3110 raster[3 * stride + 3] = tile[15];
3111 }
3112
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3113 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3114 {
3115 const MS_U32 tile_w = 4;
3116 const MS_U32 tile_h = 4;
3117 MS_U32 tile_stride = w;
3118 MS_U32 x, y;
3119
3120 #ifdef __ARM_NEON__
3121 // To overlap load and store, handle two blocks at the same time.
3122 MS_U8 *dst1, *dst2;
3123 MS_U8 *src1, *src2;
3124
3125 dst1 = dst;
3126 src1 = src;
3127 for (y = 0; y < h / tile_h; y++)
3128 {
3129 dst2 = dst1;
3130 src2 = src1;
3131 for (x = 0; x <= (w/tile_w - 8); x+=8)
3132 {
3133 tile4x4_to_raster_8(
3134 dst2,
3135 src2,
3136 raster_stride, tile_w, tile_h);
3137 dst2 += tile_w * 8;
3138 src2 += tile_w * tile_h * 8;
3139 }
3140 dst1 += raster_stride * tile_h;
3141 src1 += tile_stride * tile_h;
3142 for (; x < w / tile_w; x++)
3143 {
3144 tile4x4_to_raster(
3145 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3146 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3147 raster_stride);
3148 }
3149 }
3150 #else
3151 for (y = 0; y < h / tile_h; y++)
3152 {
3153 for (x = 0; x <= (w/tile_w - 4); x+=4)
3154 {
3155 tile4x4_to_raster_4(
3156 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3157 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3158 raster_stride);
3159 }
3160 for (; x < w / tile_w; x++)
3161 {
3162 tile4x4_to_raster(
3163 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3164 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3165 raster_stride);
3166 }
3167 }
3168 #endif
3169 }
3170
3171
3172
3173
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3174 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3175 {
3176 // The cache should already been overwritten by other address so we ignore the flush call to improve performance
3177 //MsOS_MPool_Dcache_Flush((MS_U32)pVA, u32Size);
3178 }
3179
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3180 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3181 {
3182 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3183 #define FLUSH_CACHE_SIZE (256 * 1024)
3184 MS_U32 u32SkipSize = 0;
3185
3186 if (u32Size > FLUSH_CACHE_SIZE)
3187 {
3188 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3189 u32Size = FLUSH_CACHE_SIZE;
3190 }
3191
3192 MsOS_MPool_Dcache_Flush(((MS_U32)pVA) + u32SkipSize, u32Size);
3193 }
3194
3195
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3196 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3197 {
3198 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3199 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3200 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3201 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3202
3203 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3204
3205 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3206
3207 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3208 {
3209 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3210 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3211
3212 HVD_Delay_ms(1); // FIXME
3213
3214 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3215 continue;
3216
3217 HAL_HVD_EX_ReadMemory();
3218
3219 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3220 {
3221 MS_U8 *pSrcVA, *pDstVA;
3222 MS_U32 u32SrcPA, u32DstPA;
3223 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3224 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3225
3226 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3227 {
3228 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3229
3230 u16Width = pFrmInfo->u16Width;
3231 u16Height = pFrmInfo->u16Height;
3232 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3233 }
3234
3235 // Luma
3236 u32SrcMiuSel = pFrmInfo->u2Luma1Miu;
3237 u32DstMiuSel = pFrmInfo->u2Luma0Miu;
3238
3239 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3240 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3241
3242 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3243 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3244
3245 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3246
3247 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3248
3249 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3250
3251 // Chroma
3252 u32SrcMiuSel = pFrmInfo->u2Chroma1Miu;
3253 u32DstMiuSel = pFrmInfo->u2Chroma0Miu;
3254
3255 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3256 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3257
3258 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3259 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3260
3261 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3262
3263 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3264
3265 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3266
3267 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3268 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3269
3270 HAL_HVD_EX_FlushMemory();
3271 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3272
3273 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3274 break;
3275
3276 HAL_HVD_EX_ReadMemory();
3277 }
3278 }
3279
3280 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3281
3282 return TRUE;
3283 }
3284 #endif
3285
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3286 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3287 {
3288 #ifndef VDEC3
3289 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3290 #endif
3291 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3292 //MS_U8 u8MiuSel;
3293 //MS_U32 u32StartOffset;
3294
3295 #if SUPPORT_EVD
3296 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3297 #if SUPPORT_MSVP9
3298 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3299 #endif
3300 #endif
3301
3302 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3303 // re-setup clock.
3304 #if SUPPORT_G2VP9 && defined(VDEC3)
3305 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3306 #endif
3307 if (!HAL_VPU_EX_HVDInUsed())
3308 {
3309 printf("HVD power on\n");
3310 HAL_HVD_EX_PowerCtrl(TRUE);
3311 }
3312
3313 #if SUPPORT_EVD
3314 if (isEVD)
3315 {
3316 #ifdef VDEC3
3317 if (!HAL_VPU_EX_EVDInUsed())
3318 #endif
3319 {
3320 printf("EVD power on\n");
3321 HAL_EVD_EX_PowerCtrl(TRUE);
3322 }
3323 }
3324 #endif
3325
3326 #if SUPPORT_G2VP9 && defined(VDEC3)
3327 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3328 {
3329 if (!HAL_VPU_EX_G2VP9InUsed())
3330 {
3331 printf("G2 VP9 power on\n");
3332 HAL_VP9_EX_PowerCtrl(TRUE);
3333 }
3334 }
3335 #endif
3336
3337 if ((!HAL_VPU_EX_HVDInUsed()) && (DecoderType != E_VPU_EX_DECODER_MVD))
3338 {
3339 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3340 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3341 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3342 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3343
3344 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3345
3346 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3347
3348 /*
3349 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3350 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3351 {
3352 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr >= HAL_MIU1_BASE)
3353 {
3354 _HAL_HVD_Entry();
3355 HAL_HVD_MVDMiuClientSel(1);
3356 _HAL_HVD_Release();
3357 }
3358 else
3359 {
3360 _HAL_HVD_Entry();
3361 HAL_HVD_MVDMiuClientSel(0);
3362 _HAL_HVD_Release();
3363 }
3364 }*/
3365 }
3366
3367 #if SUPPORT_EVD
3368 if (isEVD)
3369 {
3370 #ifdef VDEC3
3371 if (!HAL_VPU_EX_EVDInUsed())
3372 #endif
3373 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3374 }
3375 #endif
3376
3377 #if SUPPORT_G2VP9 && defined(VDEC3)
3378 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3379 {
3380 if (!HAL_VPU_EX_G2VP9InUsed())
3381 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3382 }
3383 #endif
3384
3385
3386 #if SUPPORT_EVD
3387 if (isEVD)
3388 {
3389 #ifdef VDEC3
3390 if (!HAL_VPU_EX_EVDInUsed())
3391 #endif
3392 {
3393 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3394 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3395 }
3396
3397 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3398 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3399 {
3400 #ifdef VDEC3
3401 if (0 == pCtrl->u32BBUId)
3402 #else
3403 if (0 == u8TaskId)
3404 #endif
3405 {
3406 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3407 }
3408 else
3409 {
3410 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3411 }
3412 }
3413 goto RESET;
3414 }
3415 #endif
3416
3417 // HVD4, from JANUS and later chip
3418 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3419 {
3420 case E_HVD_INIT_HW_AVS:
3421 {
3422 #ifdef VDEC3
3423 if (0 == pCtrl->u32BBUId)
3424 #else
3425 if (0 == u8TaskId)
3426 #endif
3427 {
3428 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3429 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3430 }
3431 else
3432 {
3433 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3434 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3435 }
3436
3437 break;
3438 }
3439 case E_HVD_INIT_HW_RM:
3440 {
3441 #ifdef VDEC3
3442 if (0 == pCtrl->u32BBUId)
3443 #else
3444 if (0 == u8TaskId)
3445 #endif
3446 {
3447 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3448 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3449
3450 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3451 {
3452 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3453 }
3454 else // RV 8
3455 {
3456 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3457 }
3458 }
3459 else
3460 {
3461 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3462 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3463
3464 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3465 {
3466 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3467 }
3468 else // RV 8
3469 {
3470 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3471 }
3472
3473 }
3474
3475 break;
3476 }
3477 default:
3478 {
3479 #ifdef VDEC3
3480 if (0 == pCtrl->u32BBUId)
3481 #else
3482 if (0 == u8TaskId)
3483 #endif
3484 {
3485 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3486 }
3487 else
3488 {
3489 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3490 }
3491 break;
3492 }
3493 }
3494
3495 RESET:
3496 //T9: use miu128bit
3497 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3498
3499 if (!HAL_VPU_EX_HVDInUsed())
3500 {
3501 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3502 }
3503
3504 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3505
3506 #if SUPPORT_EVD
3507 if (isEVD)
3508 {
3509 #ifdef VDEC3
3510 if (!HAL_VPU_EX_EVDInUsed())
3511 #endif
3512 {
3513 printf("EVD miu 128 bits\n");
3514 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_256 & ~EVD_REG_RESET_MIU1_256));
3515 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_128 | EVD_REG_RESET_MIU1_128));
3516 }
3517 }
3518
3519 // This is for Clippers, Miami and Munich using 128 bits bbu
3520 if (isEVD)
3521 {
3522 printf("EVD BBU 128 bits\n");
3523 _HVD_Write2Byte(EVD_REG_BBU_MIU_WIDTH, EVD_REG_BBU_MIU_128);
3524 }
3525 #endif
3526 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3527 // Only ES buffer addrress needs to be set for VP8
3528 _HVD_EX_SetESBufferAddr(u32Id);
3529 #else
3530 if(DecoderType != E_VPU_EX_DECODER_MVD)
3531 {
3532 _HVD_EX_SetBufferAddr(u32Id);
3533 }
3534 #endif
3535 if (!HAL_VPU_EX_HVDInUsed())
3536 {
3537 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3538 }
3539
3540 #if SUPPORT_EVD
3541 if (isEVD)
3542 {
3543 #ifdef VDEC3
3544 if (!HAL_VPU_EX_EVDInUsed())
3545 #endif
3546 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3547 }
3548 #endif
3549 #if SUPPORT_G2VP9 && defined(VDEC3)
3550 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3551 {
3552 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3553
3554 if (!HAL_VPU_EX_G2VP9InUsed())
3555 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3556
3557 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3558 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3559 }
3560 #endif
3561
3562 return TRUE;
3563 }
3564
HAL_HVD_EX_DeinitHW(void)3565 MS_BOOL HAL_HVD_EX_DeinitHW(void)
3566 {
3567 MS_U16 u16Timeout = 1000;
3568
3569 _HVD_EX_SetMIUProtectMask(TRUE);
3570
3571 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
3572 HAL_EVD_EX_DeinitHW();
3573 #endif
3574
3575 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3576
3577 while (u16Timeout)
3578 {
3579 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3580 {
3581 break;
3582 }
3583 u16Timeout--;
3584 }
3585
3586 HAL_HVD_EX_PowerCtrl(FALSE);
3587
3588 _HVD_EX_SetMIUProtectMask(FALSE);
3589
3590 return TRUE;
3591 }
3592
HAL_HVD_EX_FlushMemory(void)3593 void HAL_HVD_EX_FlushMemory(void)
3594 {
3595 MsOS_FlushMemory();
3596 }
3597
HAL_HVD_EX_ReadMemory(void)3598 void HAL_HVD_EX_ReadMemory(void)
3599 {
3600 MsOS_ReadMemory();
3601 }
3602
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3603 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3604 {
3605 _pHVDCtrls = pHVDCtrlsBase;
3606 }
3607
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3608 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3609 {
3610 return;
3611 }
3612
HAL_HVD_EX_GetHWVersionID(void)3613 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3614 {
3615 return _HVD_Read2Byte(HVD_REG_REV_ID);
3616 }
3617
3618
HAL_HVD_EX_Init_Share_Mem(void)3619 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3620 {
3621 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3622 #if !defined(SUPPORT_X_MODEL_FEATURE)
3623 MS_U32 u32ShmId;
3624 MS_U32 u32Addr;
3625 MS_U32 u32BufSize;
3626
3627
3628 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3629 sizeof(HVD_Hal_CTX),
3630 &u32ShmId,
3631 &u32Addr,
3632 &u32BufSize,
3633 MSOS_SHM_QUERY))
3634 {
3635 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3636 sizeof(HVD_Hal_CTX),
3637 &u32ShmId,
3638 &u32Addr,
3639 &u32BufSize,
3640 MSOS_SHM_CREATE))
3641 {
3642 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3643 if(pHVDHalContext == NULL)
3644 {
3645 pHVDHalContext = &gHVDHalContext;
3646 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3647 _HVD_EX_Context_Init_HAL();
3648 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3649 }
3650 else
3651 {
3652 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3653 }
3654 //return FALSE;
3655 }
3656 else
3657 {
3658 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3659 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3660 _HVD_EX_Context_Init_HAL();
3661 }
3662 }
3663 else
3664 {
3665 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3666 }
3667 #else
3668 if(pHVDHalContext == NULL)
3669 {
3670 pHVDHalContext = &gHVDHalContext;
3671 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3672 _HVD_EX_Context_Init_HAL();
3673 }
3674 #endif
3675 _HAL_HVD_MutexCreate();
3676 #else
3677 if(pHVDHalContext == NULL)
3678 {
3679 pHVDHalContext = &gHVDHalContext;
3680 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3681 _HVD_EX_Context_Init_HAL();
3682 }
3683 #endif
3684
3685 return TRUE;
3686 }
3687
3688
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3689 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3690 {
3691 MS_U32 i = 0;
3692
3693 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3694 {
3695 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3696 return pHVDHalContext->_stHVDStream[0].eStreamId;
3697 }
3698 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3699 {
3700 for (i = 0;
3701 i <
3702 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3703 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3704 {
3705 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3706 {
3707 return pHVDHalContext->_stHVDStream[i].eStreamId;
3708 }
3709 }
3710 }
3711 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3712 {
3713 for (i = 0;
3714 i <
3715 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3716 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3717 {
3718 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3719 {
3720 return pHVDHalContext->_stHVDStream[i].eStreamId;
3721 }
3722 }
3723 }
3724 #ifdef VDEC3
3725 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3726 {
3727 i = eStreamType - E_HAL_HVD_N_STREAM;
3728 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3729 return pHVDHalContext->_stHVDStream[i].eStreamId;
3730 }
3731 #endif
3732
3733 return E_HAL_HVD_STREAM_NONE;
3734 }
3735
HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)3736 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)
3737 {
3738
3739
3740 // _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
3741 const SYS_Info* sysInfo;
3742 sysInfo = MDrv_SYS_GetInfo();
3743
3744
3745 if (bEnable)
3746 {
3747 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3748 if(sysInfo->Chip.Version == VER_MALDIVES)
3749 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
3750 }
3751 else
3752 {
3753 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3754 if(sysInfo->Chip.Version == VER_MALDIVES)
3755 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
3756 }
3757
3758 // fix to not inverse
3759 _HVD_WriteByteMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
3760
3761 switch (pHVDHalContext->u32HVDClockType)
3762 {
3763
3764 case 288: // for maldives only
3765 {
3766 if(sysInfo->Chip.Version == VER_MALDIVES)
3767 {
3768 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ_MALDIVES, TOP_CKG_HVD_CLK_MASK);
3769 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
3770 }
3771 else
3772 {
3773 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
3774 }
3775 break;
3776
3777 }
3778 case 240:
3779 {
3780 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
3781 if(sysInfo->Chip.Version == VER_MALDIVES)
3782 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
3783 break;
3784 }
3785 case 216:
3786 {
3787 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
3788 if(sysInfo->Chip.Version == VER_MALDIVES)
3789 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
3790 break;
3791 }
3792 case 172:
3793 {
3794 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
3795 if(sysInfo->Chip.Version == VER_MALDIVES)
3796 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
3797 break;
3798 }
3799 case 160:
3800 {
3801 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_160MHZ, TOP_CKG_HVD_CLK_MASK);
3802 if(sysInfo->Chip.Version == VER_MALDIVES)
3803 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
3804 break;
3805 }
3806 default:
3807 {
3808 // TODO://if(hvd_clk > miu_clk) set to TOP_CKG_HVD_IDB_CLK_HVD_MIU = 0
3809 if(sysInfo->Chip.Version == VER_MALDIVES)
3810 {
3811 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ_MALDIVES, TOP_CKG_HVD_CLK_MASK);
3812 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
3813 }
3814 else
3815 {
3816 _HVD_WriteByteMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
3817 }
3818 break;
3819 }
3820 }
3821
3822 return;
3823 }
3824
HAL_HVD_EX_InitRegBase(MS_U32 u32RegBase)3825 void HAL_HVD_EX_InitRegBase(MS_U32 u32RegBase)
3826 {
3827 u32HVDRegOSBase = u32RegBase;
3828 HAL_VPU_EX_InitRegBase(u32RegBase);
3829 }
3830
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_U32 drvprectrl)3831 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_U32 drvprectrl)
3832 {
3833 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
3834 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3835 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
3836 }
3837
HAL_HVD_EX_InitVariables(MS_U32 u32Id)3838 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
3839 {
3840 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3841 HVD_ShareMem *pShm = NULL;
3842 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3843 #if HVD_ENABLE_MVC
3844 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3845 #endif ///HVD_ENABLE_MVC
3846
3847 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
3848 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
3849 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
3850 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
3851 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
3852 int i;
3853 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
3854 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
3855 #if HVD_ENABLE_MVC
3856 if(bMVC)
3857 {
3858 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
3859 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
3860 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
3861 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
3862 }
3863 #endif ///HVD_ENABLE_MVC
3864
3865 // set a local copy of FW code address; assuming there is only one copy of FW,
3866 // no matter how many task will be created.
3867
3868 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3869
3870 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
3871
3872 // global variables
3873 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
3874
3875
3876 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
3877 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
3878 // Create mutex
3879 //_HAL_HVD_MutexCreate();
3880
3881 // fill HVD init variables
3882 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3883 {
3884 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
3885 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
3886 }
3887 else
3888 #if HVD_ENABLE_RV_FEATURE
3889 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
3890 {
3891 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
3892 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
3893 #ifdef VDEC3_FB
3894 pHVDHalContext->u32RV_VLCTableAddr = 0;
3895 #else
3896 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
3897 {
3898 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
3899 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
3900 }
3901 else
3902 {
3903 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%lx min:%lx\n",
3904 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
3905 return E_HVD_RETURN_INVALID_PARAMETER;
3906 }
3907 #endif
3908 }
3909 else
3910 #endif
3911 {
3912 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
3913 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
3914 #if HVD_ENABLE_MVC
3915 if(bMVC)
3916 {
3917 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
3918 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
3919 }
3920 #endif /// HVD_ENABLE_MVC
3921 pHVDHalContext->u32RV_VLCTableAddr = 0;
3922 }
3923
3924 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
3925 || ((pCtrl->MemMap.u32CodeBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
3926 || ((pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
3927 || ((pCtrl->MemMap.u32FrameBufVAddr <= (MS_U32) pShm) && ((MS_U32) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
3928 {
3929 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
3930 pCtrl->MemMap.u32CodeBufAddr,
3931 pCtrl->MemMap.u32FrameBufAddr,
3932 pCtrl->MemMap.u32BitstreamBufAddr,
3933 pCtrl->MemMap.u32MIU1BaseAddr,
3934 pCtrl->MemMap.u32MIU2BaseAddr);
3935 #if HVD_ENABLE_MVC
3936 if(bMVC)
3937 {
3938 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
3939 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr)<= (MS_U32)pShm)&& ( (MS_U32)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
3940 {
3941 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", pCtrl->MemMap.u32BitstreamBufAddr);
3942 }
3943 }
3944 #endif /// HVD_ENABLE_MVC
3945
3946 return E_HVD_RETURN_SUCCESS;
3947 }
3948 else
3949 {
3950 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
3951 MS_PA2KSEG1((MS_U32) pShm),
3952 pCtrl->MemMap.u32CodeBufAddr,
3953 pCtrl->MemMap.u32FrameBufAddr,
3954 pCtrl->MemMap.u32BitstreamBufAddr,
3955 pCtrl->MemMap.u32MIU1BaseAddr,
3956 pCtrl->MemMap.u32MIU2BaseAddr);
3957 return E_HVD_RETURN_INVALID_PARAMETER;
3958 }
3959 }
3960
3961 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)3962 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
3963 #else
3964 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
3965 #endif
3966 {
3967 MS_U32 u32Addr = 0;
3968 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3969 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3970 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3971
3972 MS_U32 u32TmpStartOffset;
3973 MS_U8 u8TmpMiuSel;
3974
3975 memset(pShm, 0, sizeof(HVD_ShareMem));
3976
3977 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
3978
3979 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
3980 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
3981 #ifdef VDEC3
3982 if (bFWdecideFB || bCMAUsed)
3983 {
3984 pShm->u32FrameBufAddr = 0;
3985 pShm->u32FrameBufSize = 0;
3986 }
3987 else
3988 #endif
3989 {
3990 pShm->u32FrameBufAddr = u32Addr;
3991 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
3992 }
3993
3994 pShm->DispInfo.u16DispWidth = 1;
3995 pShm->DispInfo.u16DispHeight = 1;
3996 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
3997 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
3998 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
3999 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4000 //Chip info
4001 pShm->u16ChipID = E_MSTAR_CHIP_MUNICH;
4002 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4003 // PreSetControl
4004 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bOnePendingBuffer)
4005 {
4006 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4007 }
4008 if (_HVD_EX_IS_BBU_TSP_MODE(u32Id))
4009 {
4010 pShm->bUseTSPInBBUMode = TRUE;
4011 HVD_PRINT("\033[1;36m[%s] %d set PRESET_TSP_IN_BBU_MODE pShm->u32PreSetControl = %x\033[m\n",__FUNCTION__,__LINE__,(unsigned int)(pShm->u32PreSetControl));
4012 }
4013 else
4014 pShm->bUseTSPInBBUMode = FALSE;
4015
4016
4017 if ((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
4018 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4019 {
4020 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4021
4022 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
4023
4024 pShm->u32IapGnBufAddr = u32Addr;
4025 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufSize;
4026
4027 }
4028
4029 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4030 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4031 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4032 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4033 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4034 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4035
4036 if ((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stPreConnectDispPath.bEnable))
4037 {
4038 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4039
4040 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stPreConnectDispPath.stDynmcDispPath.bConnect;
4041 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
4042 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4043 }
4044
4045 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4046 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4047 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4048 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4049 else
4050 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4051 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4052 {
4053 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4054 {
4055 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4056 }
4057 else
4058 {
4059 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4060 }
4061 }
4062 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4063 {
4064 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4065 {
4066 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4067 }
4068 else
4069 {
4070 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4071 }
4072 }
4073 else
4074 {
4075 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4076 }
4077
4078 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
4079 E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4080 {
4081 pShm->bUseWbMvop = 0;
4082 }
4083 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4084
4085 #if (VPU_FORCE_MIU_MODE)
4086 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4087
4088 pShm->u32FWBaseAddr = u32TmpStartOffset;
4089
4090 #else
4091 ///TODO:
4092 /*
4093 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4094
4095 if(u8TmpMiuSel == E_CHIP_MIU_0)
4096 {
4097 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4098 }
4099 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4100 {
4101 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4102 }
4103 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4104 {
4105 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4106 }
4107 */
4108 #endif
4109 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4110 #else
4111 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4112 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4113 {
4114 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4115 }
4116 pShm->u32FWBaseAddr = u32Addr;
4117 #endif
4118
4119 // RM only
4120 #if HVD_ENABLE_RV_FEATURE
4121 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4122 && (pCtrl->InitParams.pRVFileInfo != NULL))
4123 {
4124 MS_U32 i = 0;
4125
4126 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4127 {
4128 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4129 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4130 }
4131
4132 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4133 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4134 #ifdef VDEC3_FB
4135 pShm->u32RM_VLCTableAddr = 0;
4136 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4137 #else
4138 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4139
4140 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4141 u32Addr = u32TmpStartOffset;
4142
4143 pShm->u32RM_VLCTableAddr = u32Addr;
4144 #endif
4145 }
4146 #endif
4147
4148 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4149 && (pCtrl->InitParams.pRVFileInfo != NULL))
4150 {
4151 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4152 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4153 }
4154
4155 //if(pCtrl->InitParams.bColocateBBUMode)
4156 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4157 {
4158 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4159 }
4160
4161 #if SUPPORT_G2VP9
4162 // Enable SW detile support for G2 VP9
4163 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4164 {
4165 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4166 }
4167 #endif
4168
4169 HAL_HVD_EX_FlushMemory();
4170
4171 return E_HVD_RETURN_SUCCESS;
4172 }
4173 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4174 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4175 #else
4176 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4177 #endif
4178 {
4179 MS_BOOL bInitRet = FALSE;
4180
4181 #if 0
4182 // check MVD power on
4183 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4184 {
4185 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4186 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4187 HVD_Delay_ms(1);
4188 }
4189 // Check VPU power on
4190 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4191 {
4192 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4193 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4194 HVD_Delay_ms(1);
4195 }
4196 // check HVD power on
4197 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4198 {
4199 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4200 HAL_HVD_EX_PowerCtrl(TRUE);
4201 HVD_Delay_ms(1);
4202 }
4203 #endif
4204 #ifdef VDEC3
4205 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4206 #else
4207 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4208 #endif
4209 if (!bInitRet)
4210 {
4211 return E_HVD_RETURN_FAIL;
4212 }
4213
4214 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4215
4216 if (!bInitRet)
4217 {
4218 return E_HVD_RETURN_FAIL;
4219 }
4220
4221 return E_HVD_RETURN_SUCCESS;
4222 }
4223
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4224 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4225 {
4226 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4227
4228 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4229
4230 return E_HVD_RETURN_SUCCESS;
4231 }
4232
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_U32 u32Data)4233 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_U32 u32Data)
4234 {
4235 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4236 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4237 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4238 MS_BOOL bMVC = FALSE;
4239 #if HVD_ENABLE_MVC
4240 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4241 #endif
4242
4243 switch (u32type)
4244 {
4245 // share memory
4246 // switch
4247 case E_HVD_SDATA_FRAMEBUF_ADDR:
4248 {
4249 pShm->u32FrameBufAddr = u32Data;
4250 break;
4251 }
4252 case E_HVD_SDATA_FRAMEBUF_SIZE:
4253 {
4254 pShm->u32FrameBufSize = u32Data;
4255 break;
4256 }
4257 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4258 {
4259 pShm->u32FrameBuf2Addr = u32Data;
4260 break;
4261 }
4262 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4263 {
4264 pShm->u32FrameBuf2Size = u32Data;
4265 break;
4266 }
4267 case E_HVD_SDATA_CMA_USED:
4268 {
4269 pShm->bCMA_Use = u32Data;
4270 break;
4271 }
4272 case E_HVD_SDATA_CMA_ALLOC_DONE:
4273 {
4274 pShm->bCMA_AllocDone = u32Data;
4275 break;
4276 }
4277 case E_HVD_SDATA_CMA_TWO_MIU:
4278 {
4279 pShm->bCMA_TwoMIU = u32Data;
4280 break;
4281 }
4282 case E_HVD_SDATA_RM_PICTURE_SIZES:
4283 {
4284 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4285 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4286 break;
4287 }
4288 case E_HVD_SDATA_ERROR_CODE:
4289 {
4290 pShm->u16ErrCode = (MS_U16) u32Data;
4291 break;
4292 }
4293 case E_HVD_SDATA_DISP_INFO_TH:
4294 {
4295 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4296 sizeof(HVD_DISP_THRESHOLD));
4297 break;
4298 }
4299 case E_HVD_SDATA_FW_FLUSH_STATUS:
4300 {
4301 pShm->u8FlushStatus = (MS_U8)u32Data;
4302 break;
4303 }
4304 case E_HVD_SDATA_DMX_FRAMERATE:
4305 {
4306 pShm->u32DmxFrameRate = u32Data;
4307 break;
4308 }
4309 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4310 {
4311 pShm->u32DmxFrameRateBase = u32Data;
4312 break;
4313 }
4314 case E_HVD_SDATA_MIU_SEL:
4315 {
4316 pShm->u32VDEC_MIU_SEL = u32Data;
4317 break;
4318 }
4319 // SRAM
4320
4321 // Mailbox
4322 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4323 {
4324 if (u32Data != 0)
4325 {
4326 pShm->bEnableDispCtrl = TRUE;
4327 pShm->bIsTrigDisp = TRUE;
4328 }
4329 else
4330 {
4331 pShm->bEnableDispCtrl = FALSE;
4332 }
4333
4334 break;
4335 }
4336 case E_HVD_SDATA_GET_DISP_INFO_START:
4337 {
4338 pShm->bSpsChange = FALSE;
4339 break;
4340 }
4341 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4342 {
4343 pShm->u32VirtualBoxWidth = u32Data;
4344 break;
4345 }
4346 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4347 {
4348 pShm->u32VirtualBoxHeight = u32Data;
4349 break;
4350 }
4351 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4352 {
4353 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4354 {
4355 //printf("DispFrame DqPtr: %d\n", u32Data);
4356 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4357 }
4358 break;
4359 }
4360 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4361 {
4362 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4363 {
4364 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4365 {
4366 //printf("DispFrame DqPtr: %ld\n", u32Data);
4367 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4368 }
4369 }
4370 break;
4371 }
4372 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4373 {
4374 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4375 {
4376 if (bMVC)
4377 {
4378 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4379 {
4380 //ALOGE("R1: %x", u32Data);
4381 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4382 }
4383 else
4384 {
4385 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4386 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4387 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4388 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4389 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4390 }
4391 }
4392 else
4393 {
4394 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4395 }
4396 }
4397 else
4398 {
4399 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4400 {
4401 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4402 }
4403 }
4404 break;
4405 }
4406 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
4407 {
4408 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
4409 break;
4410 }
4411
4412 default:
4413 break;
4414 }
4415
4416 HAL_HVD_EX_FlushMemory();
4417
4418 return eRet;
4419 }
4420
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4421 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4422 {
4423 MS_S64 s64Ret = 0;
4424 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4425
4426 HAL_HVD_EX_ReadMemory();
4427
4428 switch (eType)
4429 {
4430 case E_HVD_GDATA_PTS_STC_DIFF:
4431 s64Ret = pShm->s64PtsStcDiff;
4432 break;
4433 default:
4434 break;
4435 }
4436
4437 return s64Ret;
4438 }
4439
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4440 MS_U32 HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4441 {
4442 MS_U32 u32Ret = 0;
4443 //static MS_U64 u64pts_real = 0;
4444 MS_U64 u64pts_low = 0;
4445 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4446 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4447
4448 HAL_HVD_EX_ReadMemory();
4449
4450 if(pShm == NULL)
4451 {
4452 printf("########## VDEC patch for Debug ###########\n");
4453 return 0x0;
4454 }
4455
4456 switch (eType)
4457 {
4458 // share memory
4459 // switch
4460 case E_HVD_GDATA_DISP_INFO_ADDR:
4461 {
4462 u32Ret = (MS_U32) (&pShm->DispInfo);
4463 break;
4464 }
4465 case E_HVD_GDATA_MIU_SEL:
4466 u32Ret = pShm->u32VDEC_MIU_SEL;
4467 break;
4468 case E_HVD_GDATA_FRAMEBUF_ADDR:
4469 u32Ret = pShm->u32FrameBufAddr;
4470 break;
4471 case E_HVD_GDATA_FRAMEBUF_SIZE:
4472 u32Ret = pShm->u32FrameBufSize;
4473 break;
4474 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4475 u32Ret = pShm->u32FrameBuf2Addr;
4476 break;
4477 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4478 u32Ret = pShm->u32FrameBuf2Size;
4479 break;
4480 case E_HVD_GDATA_CMA_ALLOC_DONE:
4481 u32Ret = pShm->bCMA_AllocDone;
4482 break;
4483 case E_HVD_GDATA_CMA_USED:
4484 u32Ret = pShm->bCMA_Use;
4485 break;
4486 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
4487 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
4488 break;
4489 // report
4490 case E_HVD_GDATA_PTS:
4491 {
4492 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
4493 break;
4494 }
4495 case E_HVD_GDATA_U64PTS:
4496 {
4497 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
4498 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
4499 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4500 u32Ret = (MS_U32)(&(pHVDHalContext->u64pts_real));
4501 break;
4502 }
4503 case E_HVD_GDATA_U64PTS_PRE_PARSE:
4504 {
4505 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
4506 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
4507 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4508 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4509 break;
4510 }
4511 case E_HVD_GDATA_DECODE_CNT:
4512 {
4513 u32Ret = pShm->u32DecodeCnt;
4514 break;
4515 }
4516 case E_HVD_GDATA_DATA_ERROR_CNT:
4517 {
4518 u32Ret = pShm->u32DataErrCnt;
4519 break;
4520 }
4521 case E_HVD_GDATA_DEC_ERROR_CNT:
4522 {
4523 u32Ret = pShm->u32DecErrCnt;
4524 break;
4525 }
4526 case E_HVD_GDATA_ERROR_CODE:
4527 {
4528 u32Ret = (MS_U32) (pShm->u16ErrCode);
4529 break;
4530 }
4531 case E_HVD_GDATA_VPU_IDLE_CNT:
4532 {
4533 u32Ret = pShm->u32VPUIdleCnt;
4534 break;
4535 }
4536 case E_HVD_GDATA_DISP_FRM_INFO:
4537 {
4538 u32Ret = (MS_U32) (&pShm->DispFrmInfo);
4539 break;
4540 }
4541 case E_HVD_GDATA_DEC_FRM_INFO:
4542 {
4543 u32Ret = (MS_U32) (&pShm->DecoFrmInfo);
4544 break;
4545 }
4546 case E_HVD_GDATA_ES_LEVEL:
4547 {
4548 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
4549 break;
4550 }
4551 #if HVD_ENABLE_MVC
4552 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
4553 {
4554 u32Ret= (MS_U32) (&(pShm->DispFrmInfo_Sub));
4555 break;
4556 }
4557 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
4558 {
4559 u32Ret= (MS_U32) (&(pShm->DecoFrmInfo_Sub));
4560 break;
4561 }
4562 #endif
4563
4564 // user data
4565 case E_HVD_GDATA_USERDATA_WPTR:
4566 {
4567 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
4568 break;
4569 }
4570 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
4571 {
4572 u32Ret = (MS_U32) (pShm->u8UserCCIdx);
4573 break;
4574 }
4575 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
4576 {
4577 u32Ret = (MS_U32) (pShm->u32UserCCBase);
4578 break;
4579 }
4580 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
4581 {
4582 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
4583 break;
4584 }
4585 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
4586 {
4587 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
4588 break;
4589 }
4590 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
4591 {
4592 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
4593 break;
4594 }
4595 // report - modes
4596 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
4597 {
4598 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
4599 break;
4600 }
4601 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
4602 {
4603 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
4604 break;
4605 }
4606 case E_HVD_GDATA_IS_ERR_CONCEAL:
4607 {
4608 u32Ret = pShm->ModeStatus.bIsErrConceal;
4609 break;
4610 }
4611 case E_HVD_GDATA_IS_SYNC_ON:
4612 {
4613 u32Ret = pShm->ModeStatus.bIsSyncOn;
4614 break;
4615 }
4616 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
4617 {
4618 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
4619 break;
4620 }
4621 case E_HVD_GDATA_SYNC_MODE:
4622 {
4623 u32Ret = pShm->ModeStatus.u8SyncType;
4624 break;
4625 }
4626 case E_HVD_GDATA_SKIP_MODE:
4627 {
4628 u32Ret = pShm->ModeStatus.u8SkipMode;
4629 break;
4630 }
4631 case E_HVD_GDATA_DROP_MODE:
4632 {
4633 u32Ret = pShm->ModeStatus.u8DropMode;
4634 break;
4635 }
4636 case E_HVD_GDATA_DISPLAY_DURATION:
4637 {
4638 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
4639 break;
4640 }
4641 case E_HVD_GDATA_FRC_MODE:
4642 {
4643 u32Ret = pShm->ModeStatus.u8FrcMode;
4644 break;
4645 }
4646 case E_HVD_GDATA_NEXT_PTS:
4647 {
4648 u32Ret = pShm->u32NextPTS;
4649 break;
4650 }
4651 case E_HVD_GDATA_DISP_Q_SIZE:
4652 {
4653 u32Ret = pShm->u16DispQSize;
4654 break;
4655 }
4656 case E_HVD_GDATA_DISP_Q_PTR:
4657 {
4658 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
4659 break;
4660 }
4661 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
4662 {
4663 u32Ret = (MS_U32) _HVD_EX_GetNextDispFrame(u32Id);
4664 break;
4665 }
4666 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
4667 {
4668 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
4669 break;
4670 }
4671 case E_HVD_GDATA_REAL_FRAMERATE:
4672 {
4673 // return VPS/VUI timing info framerate, and 0 if timing info not exist
4674 u32Ret = pShm->u32RealFrameRate;
4675 break;
4676 }
4677 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
4678 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
4679 break;
4680 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
4681 u32Ret=((MS_U32)(pShm->u32Frm_packing_arr_data_addr));
4682 break;
4683 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
4684 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
4685 break;
4686 case E_HVD_GDATA_FW_STATUS_FLAG:
4687 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
4688 break;
4689
4690 // internal control
4691 case E_HVD_GDATA_IS_1ST_FRM_RDY:
4692 {
4693 u32Ret = pShm->bIs1stFrameRdy;
4694 break;
4695 }
4696 case E_HVD_GDATA_IS_I_FRM_FOUND:
4697 {
4698 u32Ret = pShm->bIsIFrmFound;
4699 break;
4700 }
4701 case E_HVD_GDATA_IS_SYNC_START:
4702 {
4703 u32Ret = pShm->bIsSyncStart;
4704 break;
4705 }
4706 case E_HVD_GDATA_IS_SYNC_REACH:
4707 {
4708 u32Ret = pShm->bIsSyncReach;
4709 break;
4710 }
4711 case E_HVD_GDATA_FW_VERSION_ID:
4712 {
4713 u32Ret = pShm->u32FWVersionID;
4714 break;
4715 }
4716 case E_HVD_GDATA_FW_IF_VERSION_ID:
4717 {
4718 u32Ret = pShm->u32FWIfVersionID;
4719 break;
4720 }
4721 case E_HVD_GDATA_BBU_Q_NUMB:
4722 {
4723 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
4724 break;
4725 }
4726 case E_HVD_GDATA_DEC_Q_NUMB:
4727 {
4728 u32Ret = pShm->u16DecQNumb;
4729 break;
4730 }
4731 case E_HVD_GDATA_DISP_Q_NUMB:
4732 {
4733 u32Ret = pShm->u16DispQNumb;
4734 break;
4735 }
4736 case E_HVD_GDATA_PTS_Q_NUMB:
4737 {
4738 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
4739 break;
4740 }
4741 case E_HVD_GDATA_FW_INIT_DONE:
4742 {
4743 u32Ret = pShm->bInitDone;
4744 break;
4745 }
4746 // debug
4747 case E_HVD_GDATA_SKIP_CNT:
4748 {
4749 u32Ret = pShm->u32SkipCnt;
4750 break;
4751 }
4752 case E_HVD_GDATA_GOP_CNT:
4753 {
4754 u32Ret = pShm->u32DropCnt;
4755 break;
4756 }
4757 case E_HVD_GDATA_DISP_CNT:
4758 {
4759 u32Ret = pShm->u32DispCnt;
4760 break;
4761 }
4762 case E_HVD_GDATA_DROP_CNT:
4763 {
4764 u32Ret = pShm->u32DropCnt;
4765 break;
4766 }
4767 case E_HVD_GDATA_DISP_STC:
4768 {
4769 u32Ret = pShm->u32DispSTC;
4770 break;
4771 }
4772 case E_HVD_GDATA_VSYNC_CNT:
4773 {
4774 u32Ret = pShm->u32VsyncCnt;
4775 break;
4776 }
4777 case E_HVD_GDATA_MAIN_LOOP_CNT:
4778 {
4779 u32Ret = pShm->u32MainLoopCnt;
4780 break;
4781 }
4782
4783 // AVC
4784 case E_HVD_GDATA_AVC_LEVEL_IDC:
4785 {
4786 u32Ret = pShm->u16AVC_SPS_LevelIDC;
4787 break;
4788 }
4789 case E_HVD_GDATA_AVC_LOW_DELAY:
4790 {
4791 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
4792 break;
4793 }
4794 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
4795 {
4796 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
4797 break;
4798 }
4799 case E_HVD_GDATA_FW_FLUSH_STATUS:
4800 {
4801 u32Ret = (MS_U32) (pShm->u8FlushStatus);
4802 break;
4803 }
4804 case E_HVD_GDATA_FW_CODEC_TYPE:
4805 {
4806 u32Ret = pShm->u32CodecType;
4807 break;
4808 }
4809 case E_HVD_GDATA_FW_ES_BUF_STATUS:
4810 {
4811
4812 u32Ret = (MS_U32)pShm->u8ESBufStatus;
4813 break;
4814 }
4815 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
4816 {
4817 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
4818 {
4819 u32Ret = 1;
4820 }
4821 else
4822 {
4823 u32Ret = 0;
4824 }
4825 break;
4826 }
4827
4828 // SRAM
4829
4830 // Mailbox
4831 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
4832 {
4833 u32Ret = pShm->u32FwState;
4834 break;
4835 }
4836 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
4837 {
4838 u32Ret = pShm->bSpsChange;
4839 break;
4840 }
4841 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
4842 {
4843 u32Ret = pShm->bSpsChange;
4844
4845 if (pShm->bSpsChange &&
4846 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
4847 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
4848 {
4849 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
4850 }
4851
4852 break;
4853 }
4854 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
4855 {
4856 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4857
4858 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
4859 {
4860 u32Ret = pShm->u32FwInfo;
4861 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
4862 }
4863 break;
4864 }
4865 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
4866 {
4867 if (pShm->bIsTrigDisp) // not clear yet
4868 {
4869 u32Ret = FALSE;
4870 }
4871 else
4872 {
4873 u32Ret = TRUE;
4874 }
4875 break;
4876 }
4877 case E_HVD_GDATA_ES_READ_PTR:
4878 {
4879 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
4880 break;
4881 }
4882 case E_HVD_GDATA_ES_WRITE_PTR:
4883 {
4884 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
4885 break;
4886 }
4887 case E_HVD_GDATA_BBU_READ_PTR:
4888 {
4889 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
4890 break;
4891 }
4892 case E_HVD_GDATA_BBU_WRITE_PTR:
4893 {
4894 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4895 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4896 {
4897 u32Ret = pHVDHalContext->u32VP8BBUWptr;
4898 }
4899 else
4900 {
4901 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4902 }
4903 break;
4904 }
4905 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
4906 {
4907 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4908
4909 u32Ret = pCtrl->u32BBUWptr_Fired;
4910
4911 break;
4912 }
4913 case E_HVD_GDATA_VPU_PC_CNT:
4914 {
4915 u32Ret = _HVD_EX_GetPC();
4916 break;
4917 }
4918 case E_HVD_GDATA_ES_QUANTITY:
4919 {
4920 u32Ret=_HVD_EX_GetESQuantity(u32Id);
4921 break;
4922 }
4923
4924
4925 // FW def
4926 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
4927 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
4928 break;
4929
4930 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
4931 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
4932 break;
4933 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
4934 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
4935 break;
4936 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
4937 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
4938 break;
4939 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
4940 u32Ret = MAX_PTS_TABLE_SIZE;
4941 break;
4942 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
4943 u32Ret = pShm->u32HVD_DUMMY_WRITE_ADDR;
4944 break;
4945 case E_HVD_GDATA_FW_DS_BUF_ADDR:
4946 u32Ret = pShm->u32HVD_DYNAMIC_SCALING_ADDR;
4947 break;
4948 case E_HVD_GDATA_FW_DS_BUF_SIZE:
4949 u32Ret = pShm->u32DSBuffSize; //3k or 6k
4950 break;
4951 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
4952 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
4953 break;
4954 case E_HVD_GDATA_FW_DS_INFO_ADDR:
4955 u32Ret = pShm->u32HVD_SCALER_INFO_ADDR;
4956 break;
4957 case E_HVD_GDATA_FW_DS_IS_ENABLED:
4958 {
4959 if (pShm->bDSIsRunning)
4960 {
4961 u32Ret = TRUE;
4962 }
4963 else
4964 {
4965 u32Ret = FALSE;
4966 }
4967 break;
4968 }
4969 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
4970 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
4971 break;
4972 case E_HVD_GDATA_FIELD_PIC_FLAG:
4973 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
4974 break;
4975 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
4976 u32Ret = pShm->u32SeamlessTSStatus;
4977 break;
4978 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
4979 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
4980 break;
4981 #ifdef VDEC3
4982 case E_HVD_GDATA_FW_VBBU_ADDR:
4983 u32Ret = pShm->u32HVD_VBBU_DRAM_ST_ADDR;
4984 break;
4985 #endif
4986 case E_HVD_GDATA_SEQ_CHANGE_INFO:
4987 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
4988 break;
4989 default:
4990 break;
4991 }
4992 return u32Ret;
4993 }
4994
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)4995 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
4996 {
4997 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4998 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
4999 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5000
5001 _HAL_HVD_Entry();
5002
5003 // check if old SVD cmds
5004 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5005 {
5006 HVD_EX_MSG_ERR("Old SVD FW cmd(%lx %lx) used in HVD.\n", u32Cmd, u32CmdArg);
5007
5008 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5009 }
5010
5011 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5012 {
5013 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5014 }
5015
5016 #if HVD_ENABLE_MVC
5017 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5018 {
5019 if (HAL_HVD_EX_CheckMVCID(u32Id) && u32Cmd == E_HVD_CMD_FLUSH)
5020 {
5021 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5022 }
5023 }
5024 #endif
5025
5026 if (u32Cmd == E_HVD_CMD_FLUSH &&
5027 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5028 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5029 {
5030 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5031 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5032 {
5033 _HAL_HVD_Release();
5034 HVD_Delay_ms(1);
5035 _HAL_HVD_Entry();
5036 }
5037
5038 }
5039
5040 HVD_EX_MSG_DBG("cmd=0x%lx, arg=0x%lx\n", u32Cmd, u32CmdArg);
5041
5042 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5043
5044 _HAL_HVD_Return(eRet);
5045 }
5046
HAL_HVD_EX_DeInit(MS_U32 u32Id)5047 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5048 {
5049 HVD_Return eRet = E_HVD_RETURN_FAIL;
5050 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5051 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5052 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5053 // MS_U8 u8MiuSel;
5054 // MS_U32 u32StartOffset;
5055
5056
5057 #if HVD_ENABLE_TIME_MEASURE
5058 MS_U32 ExitTimeCnt = 0;
5059 ExitTimeCnt = HVD_GetSysTime_ms();
5060 #endif
5061
5062 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_U32)pCtrl->MemMap.u32CodeBufAddr);
5063
5064 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5065
5066 if (E_HVD_RETURN_SUCCESS != eRet)
5067 {
5068 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5069 }
5070
5071 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5072
5073 if (E_HVD_RETURN_SUCCESS != eRet)
5074 {
5075 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5076 }
5077
5078 // check FW state to make sure it's STOP DONE
5079 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5080 {
5081 if (HVD_GetSysTime_ms() > u32Timeout)
5082 {
5083 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%lx\n", HAL_VPU_EX_GetProgCnt());
5084
5085 //return E_HVD_RETURN_TIMEOUT;
5086 eRet = E_HVD_RETURN_TIMEOUT;
5087 break;
5088 }
5089 }
5090
5091 VPU_EX_FWCodeCfg fwCfg;
5092 VPU_EX_TaskInfo taskInfo;
5093 VPU_EX_NDecInitPara nDecInitPara;
5094
5095 nDecInitPara.pFWCodeCfg = &fwCfg;
5096 nDecInitPara.pTaskInfo = &taskInfo;
5097
5098 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5099 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5100
5101 taskInfo.u32Id = u32Id;
5102 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5103 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5104
5105 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5106 {
5107 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5108 }
5109 else
5110 {
5111 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5112 }
5113
5114 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5115 {
5116 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5117 }
5118
5119 /* clear es buffer */
5120 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5121 {
5122 //printf("Clear ES buffer\n");
5123
5124 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5125 }
5126
5127 //_HAL_HVD_MutexDelete();
5128
5129 #if HVD_ENABLE_TIME_MEASURE
5130 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5131 #endif
5132
5133 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5134 #ifndef VDEC3
5135 // reset bbu wptr
5136 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5137 {
5138 if(TRUE == HAL_VPU_EX_HVDInUsed())
5139 {
5140 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5141 {
5142 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5143 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5144 }
5145 else
5146 {
5147 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5148 {
5149 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5150 }
5151 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5152 }
5153 }
5154 else
5155 {
5156 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5157 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5158 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5159 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5160 {
5161 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5162 {
5163 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5164 }
5165 }
5166 else
5167 {
5168 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5169 }
5170 }
5171 }
5172 #endif
5173 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5174
5175 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5176 {
5177 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5178 }
5179 /*
5180 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5181 {
5182 if(pCtrl->MemMap.u32FrameBufAddr >= HAL_MIU1_BASE)
5183 {
5184 _HAL_HVD_Entry();
5185 HAL_HVD_MVDMiuClientSel(1);
5186 _HAL_HVD_Release();
5187 }
5188 else
5189 {
5190 _HAL_HVD_Entry();
5191 HAL_HVD_MVDMiuClientSel(0);
5192 _HAL_HVD_Release();
5193 }
5194 }
5195 */
5196 HVD_EX_MSG_DBG("success\n");
5197
5198 return eRet;
5199 }
5200
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5201 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5202 {
5203 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5204 MS_U32 u32Addr = 0;
5205 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5206 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5207
5208 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5209
5210 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5211 {
5212 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5213
5214 if (E_HVD_RETURN_SUCCESS != eRet)
5215 {
5216 return eRet;
5217 }
5218 }
5219
5220 HVD_EX_MSG_ERR(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5221 printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5222
5223 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5224 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5225 {
5226 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5227
5228 if (E_HVD_RETURN_SUCCESS != eRet)
5229 {
5230 return eRet;
5231 }
5232 }
5233
5234 u32Addr = pInfo->u32Staddr;
5235
5236 if (pInfo->bRVBrokenPacket)
5237 {
5238 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5239 }
5240
5241 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5242 {
5243 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5244 }
5245 else
5246 {
5247 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5248 }
5249
5250 if (E_HVD_RETURN_SUCCESS != eRet)
5251 {
5252 return eRet;
5253 }
5254
5255 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5256 {
5257 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5258 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5259
5260 if (E_HVD_RETURN_SUCCESS != eRet)
5261 {
5262 return eRet;
5263 }
5264 }
5265
5266 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5267
5268 // do not add local pointer
5269 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5270 {
5271 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5272
5273 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5274 (u32PacketStAddr <
5275 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5276 {
5277 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5278 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5279 }
5280 else
5281 {
5282 //null packet
5283 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5284 pCtrl->LastNal.u32NalSize = 0;
5285 }
5286 }
5287 else
5288 {
5289 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5290 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5291 }
5292
5293 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5294 pCtrl->u32BBUPacketCnt++;
5295
5296 return eRet;
5297 }
5298
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5299 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5300 {
5301 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5302 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5303 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5304 if(bCurrentStatus == bEnable)
5305 return;
5306
5307 if (bEnable)
5308 {
5309 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5310 }
5311 else
5312 {
5313 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5314 }
5315 }
5316
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5317 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5318 {
5319 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5320 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5321
5322 if (bEnable)
5323 {
5324 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5325 }
5326 else
5327 {
5328 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5329 }
5330 }
5331
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5332 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5333 {
5334 MS_U32 u32RB = 0;
5335 switch(eISRType)
5336 {
5337 case E_HWDEC_ISR_HVD:
5338 u32RB = REG_HVD_BASE;
5339 break;
5340 #if SUPPORT_EVD
5341 case E_HWDEC_ISR_EVD:
5342 u32RB = REG_EVD_BASE;
5343 break;
5344 #endif
5345 #if SUPPORT_G2VP9
5346 case E_HWDEC_ISR_G2VP9:
5347 break;
5348 #endif
5349 default:
5350 break;
5351 }
5352 if(u32RB)
5353 {
5354 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5355 }
5356 }
5357
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5358 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5359 {
5360 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5361 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5362
5363 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5364 }
5365
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5366 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5367 {
5368 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5369 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5370
5371 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5372 {
5373 return FALSE;
5374 }
5375 else
5376 {
5377 return TRUE;
5378 }
5379 }
5380
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5381 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5382 {
5383 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5384
5385 if (pCtrl)
5386 {
5387 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5388 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5389 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5390 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5391 {
5392 return FALSE;
5393 }
5394 else
5395 {
5396 return TRUE;
5397 }
5398 }
5399 else
5400 {
5401 return FALSE;
5402 }
5403 }
5404
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5405 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5406 {
5407 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5408 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5409 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5410
5411 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5412 {
5413 HAL_HVD_EX_ReadMemory();
5414
5415 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5416 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5417
5418 HVD_EX_MSG_DBG("PTS table: WptrAddr:%lx RptrAddr:%lx ByteCnt:%lx PreWptr:%lx\n",
5419 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
5420 }
5421
5422 return TRUE;
5423 }
5424
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)5425 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
5426 {
5427 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5428 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5429 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5430 MS_U32 u32Data;
5431 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5432
5433 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
5434
5435 HAL_HVD_EX_FlushMemory();
5436 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5437 {
5438 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5439 pCtrl->LastNal.u32NalAddr = u32Data;
5440 pCtrl->LastNal.u32NalSize = 0;
5441 }
5442
5443 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5444 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
5445
5446 return TRUE;
5447 }
5448
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)5449 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
5450 {
5451 if (bEnable)
5452 {
5453 if (HAL_VPU_EX_IsEVDR2())
5454 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5455 else
5456 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
5457 }
5458 else
5459 {
5460 #if defined (__aeon__)
5461 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5462 #else // defined (__mips__)
5463 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
5464 #endif
5465 }
5466 }
5467
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)5468 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
5469 {
5470 return 0;
5471 }
5472
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)5473 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
5474 {
5475 return;
5476 }
5477
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)5478 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
5479 {
5480 //if( u16Clock == 0 )
5481 return 216; //140;
5482 //if( )
5483 }
5484
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)5485 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
5486 {
5487 //MS_BOOL bBitMIU1 = FALSE;
5488 //MS_BOOL bCodeMIU1 = FALSE;
5489 MS_U8 u8BitMiuSel = 0;
5490 MS_U8 u8CodeMiuSel = 0;
5491 MS_U32 u32BitStartOffset;
5492 MS_U32 u32CodeStartOffset;
5493 //MS_U8 u8MiuSel;
5494 //MS_U32 u32StartOffset;
5495 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5496 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5497 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5498 MS_U32 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
5499
5500 #if HVD_ENABLE_MVC
5501 if(HAL_HVD_EX_CheckMVCID(u32Id))
5502 {
5503 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
5504 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
5505 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
5506 {
5507 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
5508 }
5509 }
5510 #endif /// HVD_ENABLE_MVC
5511
5512 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
5513 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5514 HVD_EX_MSG_COVERITY("u32BitStartOffset = 0x%lx u32CodeStartOffset = 0x%lx \n", u32BitStartOffset,u32CodeStartOffset);
5515
5516 if (u8BitMiuSel != u8CodeMiuSel)
5517 {
5518 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
5519 BDMA_Result bdmaRlt;
5520 MS_U32 u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5521
5522 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5523 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
5524 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5525
5526 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
5527
5528 if (E_BDMA_OK != bdmaRlt)
5529 {
5530 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
5531 }
5532 #else
5533 MS_U32 u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5534
5535 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5536 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
5537 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5538
5539 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
5540 #endif
5541 }
5542
5543 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
5544
5545 HAL_HVD_EX_FlushMemory();
5546
5547 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5548 {
5549 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
5550 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
5551 }
5552 else
5553 {
5554 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
5555
5556 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5557 }
5558 }
5559
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)5560 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
5561 {
5562 if (bEnable)
5563 {
5564 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5565 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
5566 }
5567 else
5568 {
5569 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
5570 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
5571 }
5572 }
5573
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)5574 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
5575 {
5576 MS_U32 tmp1 = 0;
5577 MS_U32 tmp2 = 0;
5578 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5579
5580 HAL_HVD_EX_ReadMemory();
5581
5582 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
5583 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
5584
5585 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
5586 {
5587 MS_U32 u32Tmp = u32UartCtrl;
5588
5589 HVD_EX_MSG_DBG("\n");
5590 u32UartCtrl = 0; // turn off debug message to prevent other function prints
5591 printf("\tSystime=%lu, FWVersionID=0x%lx, FwState=0x%lx, ErrCode=0x%lx, ProgCnt=0x%lx\n",
5592 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
5593
5594 printf("\tTime: DispSTC=%lu, DispT=%lu, DecT=%lu, CurrentPts=%lu, Last Cmd=0x%lx, Arg=0x%lx, Rdy1=0x%lx, Rdy2=0x%lx\n",
5595 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
5596 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
5597 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
5598
5599 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
5600 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
5601 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
5602
5603 printf("\tQueue: BBUQNumb=%lu, DecQNumb=%d, DispQNumb=%d, ESR=%lu, ESRfromFW=%lu, ESW=%lu, ESLevel=%lu\n",
5604 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
5605 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
5606 _HVD_EX_GetESLevel(u32Id));
5607
5608 printf("\tCounter: DecodeCnt=%lu, DispCnt=%lu, DataErrCnt=%lu, DecErrCnt=%lu, SkipCnt=%lu, DropCnt=%lu, idle=%lu, MainLoopCnt=%lu, VsyncCnt=%lu\n",
5609 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
5610 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
5611 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
5612 printf
5613 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
5614 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
5615 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
5616 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
5617 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
5618 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
5619 pShm->ModeStatus.bShowOneField);
5620
5621 u32UartCtrl = u32Tmp; // recover debug level
5622 }
5623 }
5624
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)5625 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
5626 {
5627 MS_U8 *u32Addr = NULL;
5628 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5629 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5630
5631 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
5632 {
5633 return;
5634 }
5635
5636 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
5637
5638 *u32NalSize = *(u32Addr + 2) & 0x1f;
5639 *u32NalSize <<= 8;
5640 *u32NalSize |= *(u32Addr + 1) & 0xff;
5641 *u32NalSize <<= 8;
5642 *u32NalSize |= *(u32Addr) & 0xff;
5643
5644 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
5645 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
5646 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
5647 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
5648 }
5649
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)5650 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
5651 {
5652 MS_U32 u32CurIdx = 0;
5653 MS_BOOL bFinished = FALSE;
5654 MS_U32 u32NalOffset = 0;
5655 MS_U32 u32NalSize = 0;
5656 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5657
5658 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
5659 {
5660 return;
5661 }
5662
5663 u32CurIdx = u32StartIdx;
5664
5665 do
5666 {
5667 if (u32CurIdx == u32EndIdx)
5668 {
5669 bFinished = TRUE;
5670 }
5671
5672 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
5673
5674 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
5675 {
5676 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%lu Offset:%lx Size:%lx\n", u32CurIdx, u32NalOffset, u32NalSize);
5677 }
5678
5679 u32CurIdx++;
5680
5681 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
5682 {
5683 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5684 }
5685 } while (bFinished == TRUE);
5686 }
5687
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)5688 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
5689 {
5690 MS_U32 i = 0;
5691 MS_U32 value = 0;
5692
5693 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
5694 {
5695 HVD_EX_MSG_DBG("\n");
5696
5697 for (i = 0; i <= u32Num; i++)
5698 {
5699 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
5700 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
5701 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
5702
5703 if (value == 0)
5704 {
5705 break;
5706 }
5707
5708 printf(" %08lx", value);
5709
5710 if (((i % 8) + 1) == 8)
5711 {
5712 printf(" |%lu\n", i + 1);
5713 }
5714 }
5715
5716 printf("\nHVD Dump HW status End: total number:%lu\n", i);
5717 }
5718 }
5719
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)5720 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
5721 {
5722 if (pDrvCtrl)
5723 {
5724 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
5725 }
5726 }
5727
5728 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)5729 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
5730 {
5731 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
5732 }
5733
HAL_HVD_EX_GetView(MS_U32 u32Id)5734 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
5735 {
5736 #ifdef VDEC3
5737 if( (0xFF & (u32Id >> 16)) == 0x1)
5738 return E_VDEC_EX_SUB_VIEW;
5739 else
5740 return E_VDEC_EX_MAIN_VIEW;
5741 #else
5742 if( (0xFF & (u32Id >> 8)) == 0x10)
5743 return E_VDEC_EX_MAIN_VIEW;
5744 else
5745 return E_VDEC_EX_SUB_VIEW;
5746 #endif
5747 }
5748 #endif ///HVD_ENABLE_MVC
5749
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)5750 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
5751 {
5752 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
5753 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
5754 return;
5755 }
5756
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)5757 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id)
5758 {
5759 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
5760 return;
5761 }
5762
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)5763 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
5764 {
5765 MS_U64 _hw_max_pixel = 0;
5766 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
5767
5768 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%ld, MAX:%lld\n", __FUNCTION__,
5769 u16HSize, u16VSize, u32FrmRate, _hw_max_pixel);
5770 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
5771 }
5772
5773
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)5774 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
5775 {
5776 #if 1
5777 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5778 MS_U16 u16QNum = pShm->u16DispQNumb;
5779 MS_U16 u16QPtr = pShm->u16DispQPtr;
5780 // MS_U16 u16QSize = pShm->u16DispQSize;
5781 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
5782 MS_U32 u32DispQNum = 0;
5783 #if HVD_ENABLE_MVC
5784 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
5785
5786 if(bMVC)
5787 {
5788 #if 0
5789 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
5790 {
5791 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
5792 }
5793 #endif
5794
5795 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
5796 //search the next frame to display
5797 while (u16QNum > 0)
5798 {
5799 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
5800 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
5801 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
5802
5803 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
5804 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
5805 {
5806 /// For MVC. Output views after the pair of (base and depend) views were decoded.
5807 /// Check the depned view was initial when Output the base view.
5808 if((u16QPtr%2) == 0)
5809 {
5810 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
5811 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
5812 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
5813 {
5814 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
5815 ///printf("Return NULL.\n");
5816 break;
5817 }
5818 }
5819 u32DispQNum++;
5820 }
5821
5822 u16QNum--;
5823 //go to next frame in the dispQ
5824 u16QPtr++;
5825
5826 if (u16QPtr >= pShm->u16DispQSize)
5827 {
5828 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
5829 }
5830 }
5831 }
5832 else
5833 #endif ///HVD_ENABLE_MVC
5834 {
5835 #if 0
5836 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
5837 {
5838 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
5839 }
5840 #endif
5841 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
5842 //search the next frame to display
5843 while (u16QNum != 0)
5844 {
5845 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
5846
5847 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
5848 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
5849 {
5850 u32DispQNum++;
5851 }
5852
5853 u16QNum--;
5854 //go to next frame in the dispQ
5855 u16QPtr++;
5856
5857 if (u16QPtr == pShm->u16DispQSize)
5858 {
5859 u16QPtr = 0; //wrap to the begin
5860 }
5861 }
5862 }
5863
5864 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
5865 return u32DispQNum;
5866 #else
5867 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
5868 return pShm->u16DispQNumb;
5869 #endif
5870 }
5871
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)5872 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
5873 {
5874 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5875 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
5876 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
5877 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
5878 #if SUPPORT_G2VP9 && defined(VDEC3)
5879 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
5880 #else // Not using G2 VP9 implies using Mstar EVD VP9
5881 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
5882 #endif
5883 else
5884 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
5885 }
5886
5887 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)5888 void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)
5889 {
5890 if (bEnable)
5891 {
5892 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
5893 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
5894 }
5895 else
5896 {
5897 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
5898 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
5899 }
5900
5901 switch (pHVDHalContext->u32EVDClockType)
5902 {
5903 case 240:
5904 {
5905 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_288MHZ, TOP_CKG_EVD_PPU_MASK);
5906 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
5907 break;
5908 }
5909 case 216:
5910 {
5911 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
5912 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_216MHZ, TOP_CKG_EVD_MASK);
5913 break;
5914 }
5915 case 172:
5916 {
5917 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_216MHZ, TOP_CKG_EVD_PPU_MASK);
5918 //_HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
5919 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_172MHZ, TOP_CKG_EVD_MASK);
5920 break;
5921 }
5922 case 160:
5923 {
5924 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_172MHZ, TOP_CKG_EVD_PPU_MASK);
5925 //_HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
5926 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_160MHZ, TOP_CKG_EVD_MASK);
5927 break;
5928 }
5929 default:
5930 {
5931 _HVD_WriteByteMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_288MHZ, TOP_CKG_EVD_PPU_MASK);
5932 _HVD_WriteByteMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
5933 break;
5934 }
5935 }
5936
5937 return;
5938 }
5939
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)5940 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
5941 {
5942 #ifndef VDEC3
5943 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
5944 #endif
5945 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5946 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5947 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5948
5949 #ifdef VDEC3
5950 if (0 == pCtrl->u32BBUId)
5951 #else
5952 if (0 == u8TaskId)
5953 #endif
5954 {
5955 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
5956 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
5957 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)) & (~HVD_REG_BBU_TSP_INPUT));
5958 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)));
5959 }
5960 else
5961 {
5962 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
5963 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
5964 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)) & (~HVD_REG_BBU_TSP_INPUT_BS2));
5965 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)));
5966 }
5967
5968 return;
5969 }
5970
HAL_EVD_EX_DeinitHW(void)5971 static MS_BOOL HAL_EVD_EX_DeinitHW(void)
5972 {
5973 MS_U16 u16Timeout = 1000;
5974
5975 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
5976
5977 while (u16Timeout)
5978 {
5979 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
5980 {
5981 break;
5982 }
5983 u16Timeout--;
5984 }
5985
5986 HAL_EVD_EX_PowerCtrl(FALSE);
5987
5988 return TRUE;
5989 }
5990 #endif
5991
5992 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)5993 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
5994 {
5995 if (bEnable)
5996 {
5997 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
5998 }
5999 else
6000 {
6001 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6002 }
6003
6004 switch (pHVDHalContext->u32VP9ClockType)
6005 {
6006 case 432:
6007 {
6008 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6009 break;
6010 }
6011 case 384:
6012 {
6013 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6014 break;
6015 }
6016 case 345:
6017 {
6018 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6019 break;
6020 }
6021 case 320:
6022 {
6023 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6024 break;
6025 }
6026 case 288:
6027 {
6028 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6029 break;
6030 }
6031 case 240:
6032 {
6033 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6034 break;
6035 }
6036 case 216:
6037 {
6038 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6039 break;
6040 }
6041 case 456:
6042 {
6043 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_EVDPLL, TOP_CKG_VP9_CLK_MASK);
6044 break;
6045 }
6046 case 480:
6047 {
6048 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_EVDPLL, TOP_CKG_VP9_CLK_MASK);
6049 break;
6050 }
6051 default:
6052 {
6053 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6054 break;
6055 }
6056 }
6057
6058 return;
6059 }
6060
HAL_VP9_EX_DeinitHW(void)6061 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6062 {
6063 MS_U16 u16Timeout = 1000;
6064
6065 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6066
6067 while (u16Timeout)
6068 {
6069 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6070 {
6071 break;
6072 }
6073 u16Timeout--;
6074 }
6075
6076 HAL_VP9_EX_PowerCtrl(FALSE);
6077
6078 return TRUE;
6079 }
6080 #endif
6081
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6082 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6083 {
6084 return TRUE;
6085 }
HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)6086 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
6087 {
6088 _HVD_EX_SetBufferAddr(u32Id);
6089 }
6090
6091 /*
6092 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6093 {
6094 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6095
6096 if(pCtrl->InitParams.u16ChipECONum == 0)
6097 return FALSE;
6098 else
6099 return TRUE;
6100
6101 }
6102 */
6103
_HVD_EX_IS_BBU_TSP_MODE(MS_U32 u32Id)6104 MS_BOOL _HVD_EX_IS_BBU_TSP_MODE(MS_U32 u32Id)
6105 {
6106 return FALSE;
6107 }
_HVD_EX_BBU_Get_TaskRunning(MS_U32 u32Id)6108 MS_BOOL _HVD_EX_BBU_Get_TaskRunning(MS_U32 u32Id)
6109 {
6110 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6111 return pHVDHalContext->bBBU_running[u8Idx];
6112 }
6113
_HVD_EX_BBU_Set_TaskRunning(MS_U32 u32Id,MS_BOOL val)6114 void _HVD_EX_BBU_Set_TaskRunning(MS_U32 u32Id,MS_BOOL val)
6115 {
6116 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6117 pHVDHalContext->bBBU_running[u8Idx] = val;
6118 }
6119
_HVD_EX_GetESOffsetIncrease(MS_U32 u32Id,MS_U32 inc,MS_U32 offset)6120 MS_U32 _HVD_EX_GetESOffsetIncrease(MS_U32 u32Id, MS_U32 inc, MS_U32 offset)
6121 {
6122 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6123 return (offset + inc < pCtrl->MemMap.u32BitstreamBufSize)?(offset + inc):(offset + inc - pCtrl->MemMap.u32BitstreamBufSize);
6124 }
6125
_HVD_EX_GetESOffsetMinus(MS_U32 u32Id,MS_U32 mis,MS_U32 offset)6126 MS_U32 _HVD_EX_GetESOffsetMinus(MS_U32 u32Id, MS_U32 mis, MS_U32 offset)
6127 {
6128 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6129 return (offset >= mis)?(offset - mis):(offset + pCtrl->MemMap.u32BitstreamBufSize - mis);
6130 }
6131
_HVD_EX_ES_DBG_PRINT(MS_U32 u32Id,MS_U32 offset,MS_U32 length)6132 void _HVD_EX_ES_DBG_PRINT(MS_U32 u32Id, MS_U32 offset, MS_U32 length)
6133 {
6134 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6135 int idx = 0;
6136 MS_U32 newOffset = 0;
6137 HVD_PRINT("\033[1;33m [%s][%s] %d offset = %x \n\033[1;36m",__FILE__,__FUNCTION__,__LINE__,(unsigned int)offset);
6138 for(idx = 0;idx<length;idx++)
6139 {
6140 newOffset = _HVD_EX_GetESOffsetIncrease(u32Id, idx, offset);
6141 char* tempPtr = (char*)(pCtrl->MemMap.u32BitstreamBufVAddr + newOffset);
6142 HVD_PRINT("%02x ",(unsigned int)(*tempPtr));
6143
6144 if(idx % 4 ==3 || idx % 8 == 7)
6145 HVD_PRINT(" ");
6146 if(idx % 32 ==31)
6147 HVD_PRINT("\n");
6148 }
6149 }
6150
_HVD_EX_BBU_FindStartCode(MS_U32 u32Id,MS_U32 * u32Offset,MS_U32 u32ESRptr,MS_U32 u32ESWptr)6151 MS_BOOL _HVD_EX_BBU_FindStartCode(MS_U32 u32Id,MS_U32* u32Offset, MS_U32 u32ESRptr, MS_U32 u32ESWptr)
6152 {
6153
6154 return false;
6155 }
6156
6157
6158
HAL_HVD_EX_BBU_Task(MS_U32 u32Id)6159 void HAL_HVD_EX_BBU_Task(MS_U32 u32Id)
6160 {
6161
6162 }
6163
6164
6165
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6166 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6167 {
6168
6169
6170 }
6171
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6172 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6173 {
6174
6175 }
HAL_HVD_EX_GetEVDHWBuffer(void)6176 MS_U32 HAL_HVD_EX_GetEVDHWBuffer(void)
6177 {
6178 return EVD_HW_BUFFER;
6179 }
6180 #endif
6181