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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #ifndef MSOS_TYPE_NUTTX 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 121 #define VPU_FORCE_MIU_MODE 1 122 #define HVD_ENABLE_IQMEM 0 123 #define VPU_IQMEM_BASE 0xe0000000 124 125 126 #define ENABLE_DECOMPRESS_FUNCTION TRUE 127 128 #define VPU_CLOCK_240MHZ BITS(4:2,0) 129 #define VPU_CLOCK_216MHZ BITS(4:2,1) 130 #define VPU_CLOCK_192MHZ BITS(4:2,2) 131 #define VPU_CLOCK_12MHZ BITS(4:2,3) 132 #define VPU_CLOCK_320MHZ BITS(4:2,4) 133 #define VPU_CLOCK_288MHZ BITS(4:2,5) 134 #define VPU_CLOCK_432MHZ BITS(4:2,6) 135 #define VPU_CLOCK_384MHZ BITS(4:2,7) 136 137 138 #define VPU_HI_MBOX0 0 139 #define VPU_HI_MBOX1 1 140 #define VPU_RISC_MBOX0 2 141 #define VPU_RISC_MBOX1 3 142 143 144 #define VPU_EX_TimerDelayMS(x) \ 145 do \ 146 { \ 147 volatile MS_U32 ticks = 0; \ 148 while (ticks < (((MS_U32) (x)) << 13)) \ 149 { \ 150 ticks++; \ 151 } \ 152 } while(0) 153 154 #ifdef VDEC3 155 #define HAL_VPU_INVALID_BBU_ID 0xFFFFFFFF 156 #define VPU_MAX_DEC_NUM 16 157 #else 158 #define VPU_MAX_DEC_NUM 2 159 #endif 160 #define CHECK_NULL_PTR(vbbu_addr) (((void *)(vbbu_addr)) == NULL) 161 162 //------------------------------------------------------------------------------------------------- 163 // Type and Structure 164 //------------------------------------------------------------------------------------------------- 165 typedef enum 166 { 167 E_HAL_HVD_STREAM_NONE = 0x0, 168 169 //Support TSP/TS/File mode 170 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 171 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 172 E_HAL_HVD_MAIN_STREAM_MAX, 173 174 //Only support file mode 175 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 176 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 177 E_HAL_HVD_SUB_STREAM1, 178 E_HAL_HVD_SUB_STREAM_MAX, 179 180 #ifdef VDEC3 181 E_HAL_HVD_N_STREAM_BASE = 0x40, 182 E_HAL_HVD_N_STREAM0 = E_HAL_HVD_N_STREAM_BASE, 183 E_HAL_HVD_N_STREAM_MAX = E_HAL_HVD_N_STREAM0 + VPU_MAX_DEC_NUM, 184 #endif 185 186 //Only support MVC stream 187 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 188 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 189 E_HAL_HVD_MVC_Sub_View, 190 E_HAL_HVD_MVC_STREAM_MAX, 191 } HAL_HVD_StreamId; 192 193 typedef enum 194 { 195 E_VPU_EX_DECODER_NONE = 0, 196 E_VPU_EX_DECODER_GET, 197 E_VPU_EX_DECODER_GET_MVC, 198 E_VPU_EX_DECODER_MVD, 199 E_VPU_EX_DECODER_HVD, 200 E_VPU_EX_DECODER_MJPEG, 201 E_VPU_EX_DECODER_RVD, 202 E_VPU_EX_DECODER_MVC, 203 E_VPU_EX_DECODER_VP8, 204 #ifdef VDEC3 205 E_VPU_EX_DECODER_EVD, 206 #if SUPPORT_G2VP9 207 E_VPU_EX_DECODER_G2VP9, 208 #endif 209 #endif 210 } VPU_EX_DecoderType; 211 212 typedef enum 213 { 214 E_VPU_EX_CLOCK_240MHZ = VPU_CLOCK_240MHZ, 215 E_VPU_EX_CLOCK_216MHZ = VPU_CLOCK_216MHZ, 216 E_VPU_EX_CLOCK_192MHZ = VPU_CLOCK_192MHZ, 217 E_VPU_EX_CLOCK_12MHZ = VPU_CLOCK_12MHZ, 218 E_VPU_EX_CLOCK_320MHZ = VPU_CLOCK_320MHZ, 219 E_VPU_EX_CLOCK_288MHZ = VPU_CLOCK_288MHZ, 220 E_VPU_EX_CLOCK_432MHZ = VPU_CLOCK_432MHZ, 221 E_VPU_EX_CLOCK_384MHZ = VPU_CLOCK_384MHZ, 222 223 } VPU_EX_ClockSpeed; 224 225 226 typedef enum 227 { 228 E_HAL_VPU_STREAM_NONE = 0x0, 229 230 //Support TSP/TS File/File mode 231 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 232 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 233 E_HAL_VPU_MAIN_STREAM_MAX, 234 235 //Only support file mode 236 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 237 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 238 E_HAL_VPU_SUB_STREAM_MAX, 239 240 #ifdef VDEC3 241 E_HAL_VPU_N_STREAM_BASE = 0x40, 242 E_HAL_VPU_N_STREAM0 = E_HAL_VPU_N_STREAM_BASE, 243 E_HAL_VPU_N_STREAM_MAX = E_HAL_VPU_N_STREAM0 + VPU_MAX_DEC_NUM, 244 #endif 245 246 //Only support MVC stream 247 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 248 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 249 E_HAL_VPU_MVC_SUB_VIEW, 250 E_HAL_VPU_MVC_STREAM_MAX, 251 } HAL_VPU_StreamId; 252 253 typedef enum 254 { 255 //Support TSP/TS/File mode 256 E_HAL_VPU_MAIN_STREAM, 257 258 //Only support file mode 259 E_HAL_VPU_SUB_STREAM, 260 261 //Only support MVC mode 262 E_HAL_VPU_MVC_STREAM, 263 264 #ifdef VDEC3 265 E_HAL_VPU_N_STREAM, 266 #endif 267 } HAL_VPU_StreamType; 268 269 typedef enum 270 { 271 //Support TSP/TS/File mode 272 E_VPU_EX_INPUT_TSP, 273 //Only support file mode 274 E_VPU_EX_INPUT_FILE, 275 E_VPU_EX_INPUT_NONE, 276 } VPU_EX_SourceType; 277 278 typedef enum 279 { 280 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 281 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 282 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 283 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 284 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 285 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 286 } VPU_EX_UartLevel; 287 288 typedef enum 289 { 290 E_VPU_EX_FW_VER_CTRLR = 0, 291 E_VPU_EX_FW_VER_MVD_FW, 292 E_VPU_EX_FW_VER_HVD_FW, 293 E_VPU_EX_FW_VER_MVD_IF, 294 E_VPU_EX_FW_VER_HVD_IF, 295 } VPU_EX_FWVerType; 296 297 /// DecodeMode for f/w tasks 298 typedef enum 299 { 300 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 301 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 302 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 303 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 304 } VPU_EX_DecMode; 305 306 /// CmdMode for KOREA3D or PIP mode 307 typedef enum 308 { 309 //Group1:Set Korea3DTV mode 310 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 311 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 312 E_VPU_CMD_MODE_KR3D_FORCE_P, 313 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 314 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 315 316 //Group2:Set PIP mode 317 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 318 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 319 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 320 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 321 } VPU_EX_CmdMode; 322 323 #define CMA_DRV_DIRECT_INIT 324 #ifdef CMA_DRV_DIRECT_INIT 325 /// input source select enumerator 326 typedef enum 327 { 328 ///DTV mode 329 E_VPU_EX_SRC_MODE_DTV = 0, 330 ///TS file mode 331 E_VPU_EX_SRC_MODE_TS_FILE, 332 ///generic file mode 333 E_VPU_EX_SRC_MODE_FILE, 334 /// TS file and dual ES buffer mode 335 E_VPU_EX_SRC_MODE_TS_FILE_DUAL_ES, 336 ///generic file and dual ES buffer mode 337 E_VPU_EX_SRC_MODE_FILE_DUAL_ES, 338 } VPU_EX_SrcMode; 339 340 /// codec type enumerator 341 typedef enum 342 { 343 ///unsupported codec type 344 E_VPU_EX_CODEC_TYPE_NONE = 0, 345 ///MPEG 1/2 346 E_VPU_EX_CODEC_TYPE_MPEG2, 347 ///H263 (short video header) 348 E_VPU_EX_CODEC_TYPE_H263, 349 ///MPEG4 (default) 350 E_VPU_EX_CODEC_TYPE_MPEG4, 351 ///MPEG4 (Divx311) 352 E_VPU_EX_CODEC_TYPE_DIVX311, 353 ///MPEG4 (Divx412) 354 E_VPU_EX_CODEC_TYPE_DIVX412, 355 ///FLV 356 E_VPU_EX_CODEC_TYPE_FLV, 357 ///VC1 advanced profile (VC1) 358 E_VPU_EX_CODEC_TYPE_VC1_ADV, 359 ///VC1 main profile (RCV) 360 E_VPU_EX_CODEC_TYPE_VC1_MAIN, 361 ///Real Video version 8 362 E_VPU_EX_CODEC_TYPE_RV8, 363 ///Real Video version 9 and 10 364 E_VPU_EX_CODEC_TYPE_RV9, 365 ///H264 366 E_VPU_EX_CODEC_TYPE_H264, 367 ///AVS 368 E_VPU_EX_CODEC_TYPE_AVS, 369 ///MJPEG 370 E_VPU_EX_CODEC_TYPE_MJPEG, 371 ///MVC 372 E_VPU_EX_CODEC_TYPE_MVC, 373 ///VP8 374 E_VPU_EX_CODEC_TYPE_VP8, 375 ///HEVC 376 E_VPU_EX_CODEC_TYPE_HEVC, 377 ///VP9 378 E_VPU_EX_CODEC_TYPE_VP9, 379 // HEVC Dolby vision 380 E_VPU_EX_CODEC_TYPE_HEVC_DV, 381 E_VPU_EX_CODEC_TYPE_NUM 382 } VPU_EX_CodecType; 383 #endif 384 385 typedef struct 386 { 387 VPU_EX_ClockSpeed eClockSpeed; 388 MS_BOOL bClockInv; 389 MS_S32 s32VPUMutexID; 390 MS_U32 u32VPUMutexTimeout; 391 MS_U8 u8MiuSel; 392 } VPU_EX_InitParam; 393 394 typedef struct 395 { 396 MS_U32 u32Id; 397 HAL_VPU_StreamId eVpuId; 398 VPU_EX_SourceType eSrcType; 399 VPU_EX_DecoderType eDecType; 400 MS_U8 u8HalId; // hal MVD/HVD id 401 MS_U32 u32HeapSize; 402 } VPU_EX_TaskInfo; 403 404 typedef struct 405 { 406 MS_VIRT u32DstAddr; 407 MS_VIRT u32DstSize; 408 MS_VIRT u32BinSize; 409 MS_VIRT u32BinAddr; 410 MS_U8 u8SrcType; 411 } VPU_EX_FWCodeCfg; 412 413 typedef struct 414 { 415 MS_VIRT u32DstAddr; 416 MS_VIRT u32BinAddr; 417 MS_VIRT u32BinSize; 418 MS_VIRT u32FrameBufAddr; 419 MS_VIRT u32VLCTableOffset; 420 } VPU_EX_VLCTblCfg; 421 422 #ifdef VDEC3 423 typedef struct 424 { 425 MS_VIRT u32FrameBufAddr; 426 MS_VIRT u32FrameBufSize; 427 } VPU_EX_FBCfg; 428 #endif 429 430 /// VPU init parameters for dual decoder 431 typedef struct 432 { 433 VPU_EX_FWCodeCfg *pFWCodeCfg; 434 VPU_EX_TaskInfo *pTaskInfo; 435 VPU_EX_VLCTblCfg *pVLCCfg; 436 #ifdef VDEC3 437 VPU_EX_FBCfg *pFBCfg; 438 #endif 439 } VPU_EX_NDecInitPara; 440 441 typedef struct 442 { 443 MS_U8 u8DecMod; 444 MS_U8 u8CodecCnt; 445 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 446 MS_U8 u8ArgSize; 447 MS_U32 u32Arg; 448 } VPU_EX_DecModCfg; 449 450 typedef enum 451 { 452 E_VDEC_EX_CODEC_PROFILE_NONE, 453 454 E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, 455 456 E_VDEC_EX_CODEC_PROFILE_MP4_ASP, 457 458 E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, 459 460 E_VDEC_EX_CODEC_PROFILE_VC1_AP, 461 462 E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, 463 464 E_VDEC_EX_CODEC_PROFILE_VP9_0, 465 E_VDEC_EX_CODEC_PROFILE_VP9_2, 466 467 E_VDEC_EX_CODEC_PROFILE_H264_CBP, 468 E_VDEC_EX_CODEC_PROFILE_H264_BP, 469 E_VDEC_EX_CODEC_PROFILE_H264_XP, 470 E_VDEC_EX_CODEC_PROFILE_H264_MP, 471 E_VDEC_EX_CODEC_PROFILE_H264_HIP, 472 E_VDEC_EX_CODEC_PROFILE_H264_PHIP, 473 E_VDEC_EX_CODEC_PROFILE_H264_CHIP, 474 E_VDEC_EX_CODEC_PROFILE_H264_HI10P, 475 E_VDEC_EX_CODEC_PROFILE_H264_HI422P, 476 E_VDEC_EX_CODEC_PROFILE_H264_HI444PP, 477 478 E_VDEC_EX_CODEC_PROFILE_H265_MAIN, 479 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, 480 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_12, 481 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_10, 482 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_12, 483 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444, 484 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_10, 485 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_12, 486 487 E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, 488 489 } VDEC_EX_CODEC_CAP_PROFILE_INFO; 490 491 typedef enum 492 { 493 E_VDEC_EX_CODEC_LEVEL_NONE, 494 495 E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, 496 497 E_VDEC_EX_CODEC_LEVEL_MP4_L5, 498 499 E_VDEC_EX_CODEC_LEVEL_VC1_L3, 500 501 E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, 502 503 504 E_VDEC_EX_CODEC_LEVEL_H264_1, 505 E_VDEC_EX_CODEC_LEVEL_H264_1B, 506 E_VDEC_EX_CODEC_LEVEL_H264_1_1, 507 E_VDEC_EX_CODEC_LEVEL_H264_1_2, 508 E_VDEC_EX_CODEC_LEVEL_H264_1_3, 509 E_VDEC_EX_CODEC_LEVEL_H264_2, 510 E_VDEC_EX_CODEC_LEVEL_H264_2_1, 511 E_VDEC_EX_CODEC_LEVEL_H264_2_2, 512 E_VDEC_EX_CODEC_LEVEL_H264_3, 513 E_VDEC_EX_CODEC_LEVEL_H264_3_1, 514 E_VDEC_EX_CODEC_LEVEL_H264_3_2, 515 E_VDEC_EX_CODEC_LEVEL_H264_4, 516 E_VDEC_EX_CODEC_LEVEL_H264_4_1, 517 E_VDEC_EX_CODEC_LEVEL_H264_4_2, 518 E_VDEC_EX_CODEC_LEVEL_H264_5, 519 E_VDEC_EX_CODEC_LEVEL_H264_5_1, 520 E_VDEC_EX_CODEC_LEVEL_H264_5_2, 521 522 E_VDEC_EX_CODEC_LEVEL_H265_1, 523 E_VDEC_EX_CODEC_LEVEL_H265_2, 524 E_VDEC_EX_CODEC_LEVEL_H265_2_1, 525 E_VDEC_EX_CODEC_LEVEL_H265_3, 526 E_VDEC_EX_CODEC_LEVEL_H265_3_1, 527 E_VDEC_EX_CODEC_LEVEL_H265_4_MT, 528 E_VDEC_EX_CODEC_LEVEL_H265_4_HT, 529 E_VDEC_EX_CODEC_LEVEL_H265_4_1_MT, 530 E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, 531 E_VDEC_EX_CODEC_LEVEL_H265_5_MT, 532 E_VDEC_EX_CODEC_LEVEL_H265_5_HT, 533 E_VDEC_EX_CODEC_LEVEL_H265_5_1_MT, 534 E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, 535 E_VDEC_EX_CODEC_LEVEL_H265_5_2_MT, 536 E_VDEC_EX_CODEC_LEVEL_H265_5_2_HT, 537 E_VDEC_EX_CODEC_LEVEL_H265_6_MT, 538 E_VDEC_EX_CODEC_LEVEL_H265_6_HT, 539 E_VDEC_EX_CODEC_LEVEL_H265_6_1_MT, 540 E_VDEC_EX_CODEC_LEVEL_H265_6_1_HT, 541 E_VDEC_EX_CODEC_LEVEL_H265_6_2_MT, 542 E_VDEC_EX_CODEC_LEVEL_H265_6_2_HT, 543 544 E_VDEC_EX_CODEC_LEVEL_AVS_6010860, 545 546 } VDEC_EX_CODEC_CAP_LEVEL_INFO; 547 548 549 typedef enum 550 { 551 E_VDEC_EX_CODEC_VERSION_NONE, 552 553 E_VDEC_EX_CODEC_VERSION_DIVX_311, 554 E_VDEC_EX_CODEC_VERSION_DIVX_4, 555 E_VDEC_EX_CODEC_VERSION_DIVX_5, 556 E_VDEC_EX_CODEC_VERSION_DIVX_6, 557 558 E_VDEC_EX_CODEC_VERSION_FLV_1, 559 560 E_VDEC_EX_CODEC_VERSION_H263_1, 561 562 } VDEC_EX_CODEC_CAP_VERSION_INFO; 563 564 typedef struct 565 { 566 MS_U16 u16CodecCapWidth; 567 MS_U16 u16CodecCapHeight; 568 MS_U8 u8CodecCapFrameRate; 569 VDEC_EX_CODEC_CAP_PROFILE_INFO u8CodecCapProfile; 570 VDEC_EX_CODEC_CAP_VERSION_INFO u8CodecCapVersion; 571 VDEC_EX_CODEC_CAP_LEVEL_INFO u8CodecCapLevel; 572 MS_U32 u32CodecType; 573 MS_U32 u32BitRate; 574 }VDEC_EX_CODEC_CAP_INFO; 575 576 577 typedef struct 578 { 579 union 580 { 581 struct 582 { 583 MS_U8 reg_offset; 584 MS_U8 reg_bank; 585 }; 586 MS_U16 reg__bank_offset; 587 }; 588 }VPU_REG_ADDRESS; 589 590 //------------------------------------------------------------------------------------------------- 591 // Function and Variable 592 //------------------------------------------------------------------------------------------------- 593 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 594 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 595 #ifdef VDEC3 596 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId); 597 #else 598 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 599 #endif 600 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 601 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 602 603 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 604 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase); 605 606 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 607 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 608 MS_BOOL HAL_VPU_EX_DeInit(void); 609 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 610 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 611 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr); 612 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 613 void HAL_VPU_EX_SwRstRelse(void); 614 void HAL_VPU_EX_SwRelseMAU(void); 615 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Address); 616 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Address, MS_U32 u32Value); 617 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 618 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 619 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 620 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 621 MS_U32 HAL_VPU_EX_GetProgCnt(void); 622 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 623 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr); 624 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 625 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id); 626 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id); 627 MS_BOOL HAL_VPU_EX_IsPowered(void); 628 MS_BOOL HAL_VPU_EX_IsRsted(void); 629 MS_BOOL HAL_VPU_EX_IsEVDR2(void); 630 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 631 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 632 #ifdef VDEC3 633 MS_BOOL HAL_VPU_EX_EVDInUsed(void); 634 #if SUPPORT_G2VP9 635 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void); 636 #endif 637 #endif 638 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable); 639 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 640 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 641 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 642 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 643 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo); 644 MS_BOOL HAL_VPU_EX_Efuse_Support_VPX(void); 645 646 MS_VIRT HAL_VPU_EX_MIU1BASE(void); 647 MS_VIRT HAL_VPU_EX_GetSHMAddr(void); 648 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 649 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(void); 650 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 651 #ifdef VDEC3 652 typedef enum 653 { 654 E_HVD_CMDQ_CMD, 655 E_HVD_CMDQ_ARG, 656 } HVD_COMMAND_QUEUE_TYPE; 657 658 typedef enum 659 { 660 E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL, 661 E_HVD_COMMAND_QUEUE_NOT_INITIALED, 662 E_HVD_COMMAND_QUEUE_FULL, 663 E_HVD_COMMAND_QUEUE_SEND_FAIL, 664 } HVD_DRAM_COMMAND_QUEUE_SEND_STATUS; 665 666 667 typedef struct 668 { 669 MS_VIRT u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 670 MS_U32 u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 671 MS_U64 u64TimeStamp; ///< Packet time stamp. unit: ms. 672 MS_U32 u32ID_L; ///< Packet ID low part. 673 MS_U32 u32ID_H; ///< Packet ID high part. 674 } HAL_VPU_EX_PacketInfo; 675 // *****************Virtual BBU function***************** 676 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr); 677 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr); 678 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 679 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 680 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr); 681 // *****************General dram command queue function***************** 682 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd); 683 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd); 684 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg); 685 // *****************Dram command queue function***************** 686 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue); 687 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue); 688 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 689 // *****************Display dram command queue function***************** 690 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue); 691 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue); 692 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 693 // *****************General purpose function***************** 694 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr); 695 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bIsNstreamMode); 696 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo); 697 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType); 698 #ifdef CMA_DRV_DIRECT_INIT 699 // *****************CMA function***************** 700 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode, 701 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize); 702 #endif 703 #endif 704 #ifdef VDEC3_FB 705 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType); 706 #endif 707 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size); 708 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx); 709 MS_U8 HAL_VPU_EX_CheckFreeStream(void); 710 711 #else 712 typedef struct 713 { 714 MS_PHY Bitstream_Addr_Main; 715 MS_U32 Bitstream_Len_Main; 716 MS_PHY Bitstream_Addr_Sub; 717 MS_U32 Bitstream_Len_Sub; 718 MS_PHY MIU1_BaseAddr; 719 } VPU_EX_LOCK_DOWN_REGISTER; 720 721 722 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr); 723 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 724 725 #endif 726 #endif // _HAL_VPU_EX_H_ 727 728