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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 // 94 /// @file regMVD.h 95 /// @brief Hardware register definition for Video Decoder 96 /// @author MStar Semiconductor Inc. 97 // 98 /////////////////////////////////////////////////////////////////////////////////// 99 100 #ifndef _REG_MVD_H_ 101 #define _REG_MVD_H_ 102 103 104 //////////////////////////////////////////////////////////////////////////////// 105 // Constant & Macro Definition 106 //////////////////////////////////////////////////////////////////////////////// 107 //------------------------------------------------------------------------------ 108 // Base Address 109 //------------------------------------------------------------------------------ 110 #define MVD_REG_BASE 0x1100UL // 0x1100 - 0x11FF 111 #define CHIP_REG_BASE 0x1E00UL // 0x1E00 - 0x1EFF 112 113 #define MIU0_REG_BASE 0x1200UL 114 #define MIU1_REG_BASE 0x0600UL 115 116 #define MIU0_REG_BASE2 0x61500UL 117 #define MIU1_REG_BASE2 0x62200UL 118 119 120 //------------------------------------------------------------------------------ 121 // MIU register 122 //------------------------------------------------------------------------------ 123 //MIU request mask 124 #define MIU0_RQ0_MASK_L (MIU0_REG_BASE + 0x23*2) 125 #define MIU0_RQ0_MASK_H (MIU0_REG_BASE + 0x23*2 +1) 126 #define MIU0_RQ1_MASK_L (MIU0_REG_BASE + 0x33*2) 127 #define MIU0_RQ1_MASK_H (MIU0_REG_BASE + 0x33*2 +1) 128 #define MIU0_RQ2_MASK_L (MIU0_REG_BASE + 0x43*2) 129 #define MIU0_RQ2_MASK_H (MIU0_REG_BASE + 0x43*2 +1) 130 #define MIU0_RQ3_MASK_L (MIU0_REG_BASE + 0x53*2) 131 #define MIU0_RQ3_MASK_H (MIU0_REG_BASE + 0x53*2 +1) 132 #define MIU0_RQ4_MASK_L (MIU0_REG_BASE2 + 0x0003*2) 133 #define MIU0_RQ4_MASK_H (MIU0_REG_BASE2 + 0x0003*2 +1) 134 135 #define MIU0_SEL0_L (MIU0_REG_BASE + 0xF0) 136 #define MIU0_SEL0_H (MIU0_REG_BASE + 0xF1) 137 #define MIU0_SEL2_L (MIU0_REG_BASE + 0xF4) 138 #define MIU0_SEL2_H (MIU0_REG_BASE + 0xF5) 139 #define MIU0_SEL3_L (MIU0_REG_BASE + 0xF6) 140 #define MIU0_SEL3_H (MIU0_REG_BASE + 0xF7) 141 142 #define MIU1_RQ0_MASK_L (MIU1_REG_BASE + 0x23*2) 143 #define MIU1_RQ0_MASK_H (MIU1_REG_BASE + 0x23*2 +1) 144 #define MIU1_RQ1_MASK_L (MIU1_REG_BASE + 0x33*2) 145 #define MIU1_RQ1_MASK_H (MIU1_REG_BASE + 0x33*2 +1) 146 #define MIU1_RQ2_MASK_L (MIU1_REG_BASE + 0x43*2) 147 #define MIU1_RQ2_MASK_H (MIU1_REG_BASE + 0x43*2 +1) 148 #define MIU1_RQ3_MASK_L (MIU1_REG_BASE + 0x53*2) 149 #define MIU1_RQ3_MASK_H (MIU1_REG_BASE + 0x53*2 +1) 150 #define MIU1_RQ4_MASK_L (MIU1_REG_BASE2 + 0x0003*2) 151 #define MIU1_RQ4_MASK_H (MIU1_REG_BASE2 + 0x0003*2 +1) 152 153 154 //------------------------------------------------------------------------------ 155 // MVD Reg 156 //------------------------------------------------------------------------------ 157 #define MVD_CTRL_RST BIT0//1: reset MVD; 0: release reset 158 #define MVD_CTRL_CLR_INT BIT2//Clear MVD interrupt. 159 #define MVD_CTRL_CLK_SYNCMODE BIT4//1: sync_mode; 0: async_mode 160 #define MVD_CTRL_CLK_ALLON BIT5//1: enable all clocks in mvd 161 #define MVD_CTRL_DISCONNECT_MIU BIT6//1: disconnect; 0: release reset 162 #define MVD_CTRL (MVD_REG_BASE + 0x00) 163 164 #define MVD_STATUS_READY BIT1 165 #define MVD_STATUS (MVD_REG_BASE + 0x01) 166 #define MVD_T8_MIU_128_0 BIT2 // enable MVD to 128 bit mode 167 #define MVD_T8_MIU_128_1 BIT3 // enable MVD to 128 bit mode 168 #define MVD_COMMAND (MVD_REG_BASE + 0x02) 169 #define MVD_ARG0 (MVD_REG_BASE + 0x04) 170 #define MVD_ARG1 (MVD_REG_BASE + 0x05) 171 #define MVD_ARG2 (MVD_REG_BASE + 0x06) 172 #define MVD_ARG3 (MVD_REG_BASE + 0x07) 173 #define MVD_ARG4 (MVD_REG_BASE + 0x08) 174 #define MVD_ARG5 (MVD_REG_BASE + 0x09) 175 176 #define MVD_SLQCTRL_WADR_RELOAD BIT0 //reload "slq_wadr" into write address 177 //w reload: program 1, then program 0, and reload complete 178 #define MVD_SLQCTRL_RADR_PROBE BIT1 //SLQ read address probe 179 #define MVD_SLQCTRL_WADR_PROBE BIT2 //SLQ write address probe 180 //r/w probe: program 1, then program 0, and read "slq_caddr" 181 #define MVD_SLQCTRL (MVD_REG_BASE + 0x16) 182 183 //SLQ write address value[24:0] 184 #define MVD_SLQ_WADR0 (MVD_REG_BASE + 0x18) 185 #define MVD_SLQ_WADR1 (MVD_REG_BASE + 0x19) 186 #define MVD_SLQ_WADR2 (MVD_REG_BASE + 0x1A) 187 #define MVD_SLQ_WADR3 (MVD_REG_BASE + 0x1B) 188 189 //SLQ probe address value[24:0] 190 #define MVD_SLQ_CADR0 (MVD_REG_BASE + 0x1C) 191 #define MVD_SLQ_CADR1 (MVD_REG_BASE + 0x1D) 192 #define MVD_SLQ_CADR2 (MVD_REG_BASE + 0x1E) 193 #define MVD_SLQ_CADR3 (MVD_REG_BASE + 0x1F) 194 195 //CRC in/out 196 #define MVD_CRC_CTL (MVD_REG_BASE + 0x23) 197 #define MVD_CRC_CTL_FIRE BIT6 198 #define MVD_CRC_CTL_DONE BIT7 199 #define MVD_CRC_HSIZE (MVD_REG_BASE + 0x22) //CRC hsize[13:4] 200 #define MVD_CRC_VSIZE (MVD_REG_BASE + 0x24) //CRC vsize[13:0] 201 #define MVD_CRC_STRIP (MVD_REG_BASE + 0x26) //CRC strip[13:0] 202 #define MVD_CRC_Y_START (MVD_REG_BASE + 0x28) //CRC y start address[25:0] 203 #define MVD_CRC_Y_START_LEN BMASK(25:0) 204 #define MVD_CRC_UV_START (MVD_REG_BASE + 0x2C) //CRC uv start address[25:0] 205 #define MVD_CRC_UV_START_LEN BMASK(25:0) 206 #define MVD_CRC_Y_L (MVD_REG_BASE + 0x30) 207 #define MVD_CRC_Y_H (MVD_REG_BASE + 0x32) 208 #define MVD_CRC_UV_L (MVD_REG_BASE + 0x34) 209 #define MVD_CRC_UV_H (MVD_REG_BASE + 0x36) 210 211 #define REG_CHIPTOP_BASE 0x0b00UL 212 213 #define REG_CKG_MVD_SYNC (REG_CHIPTOP_BASE + 0x38*2 +1) 214 #define CKG_MVD_SYNC_GATED BIT0 215 216 #define REG_CKG_MVD (REG_CHIPTOP_BASE + 0x39*2) 217 #define CKG_MVD_GATED BIT0 218 #define CKG_MVD_INVERT BIT1 219 #define CKG_MVD_MASK (BIT4 | BIT3 | BIT2) 220 #define CKG_MVD_216MHZ (0 << 2) 221 #define CKG_MVD_192MHZ (1 << 2) 222 #define CKG_MVD_172MHZ (2 << 2) 223 #define CKG_MVD_144MHZ (3 << 2) 224 #define CKG_MVD_CLK_MIU (4 << 2) //clk_miu_p 225 #define CKG_MVD_123MHZ (5 << 2) 226 #define CKG_MVD_MPLL_DIV2 (6 << 2) //mempll_clk_buf_div2 227 #define CKG_MVD_XTAL_CLK (7 << 2) //XTAL clock 228 229 #define REG_CKG_MVD2 (REG_CHIPTOP_BASE + 0x39*2 +1) 230 #define CKG_MVD2_GATED BIT0 231 #define CKG_MVD2_INVERT BIT1 232 #define CKG_MVD2_MASK (BIT4 | BIT3 | BIT2) 233 #define CKG_MVD2_216MHZ (0 << 2) 234 #define CKG_MVD2_192MHZ (1 << 2) 235 #define CKG_MVD2_172MHZ (2 << 2) 236 #define CKG_MVD2_144MHZ (3 << 2) 237 #define CKG_MVD2_CLK_MIU (4 << 2) //clk_miu_p 238 #define CKG_MVD2_123MHZ (5 << 2) 239 #define CKG_MVD2_MPLL_DIV2 (6 << 2) //mempll_clk_buf_div2 240 #define CKG_MVD2_XTAL_CLK (7 << 2) //XTAL clock 241 242 #define REG_CKG_MVD_CHROMA_A (REG_CHIPTOP_BASE + 0x3d*2) 243 #define CKG_MVD_CHROMA_A_GATED BIT0 244 #define CKG_MVD_CHROMA_A_INVERT BIT1 245 246 #define REG_CKG_MVD_CHROMA_B (REG_CHIPTOP_BASE + 0x3d*2) 247 #define CKG_MVD_CHROMA_B_GATED BIT4 248 #define CKG_MVD_CHROMA_B_INVERT BIT5 249 250 #define REG_CKG_MVD_CHROMA_C (REG_CHIPTOP_BASE + 0x3d*2 + 1) 251 #define CKG_MVD_CHROMA_C_GATED BIT0 252 #define CKG_MVD_CHROMA_C_INVERT BIT1 253 254 #define REG_CKG_MVD_LUMA_A (REG_CHIPTOP_BASE + 0x3a*2 + 1) 255 #define CKG_MVD_LUMA_A_GATED BIT0 256 #define CKG_MVD_LUMA_A_INVERT BIT1 257 258 #define REG_CKG_MVD_LUMA_B (REG_CHIPTOP_BASE + 0x3b*2) 259 #define CKG_MVD_LUMA_B_GATED BIT0 260 #define CKG_MVD_LUMA_B_INVERT BIT1 261 262 #define REG_CKG_MVD_LUMA_C (REG_CHIPTOP_BASE + 0x3b*2 + 1) 263 #define CKG_MVD_LUMA_C_GATED BIT0 264 #define CKG_MVD_LUMA_C_INVERT BIT1 265 266 267 #define REG_CKG_MVD_RMEM (REG_CHIPTOP_BASE + 0x3c*2) 268 #define CKG_MVD_RMEM_GATED BIT0 269 #define CKG_MVD_RMEM_INVERT BIT1 270 271 #define REG_CKG_MVD_RMEM1 (REG_CHIPTOP_BASE + 0x3c*2 + 1) 272 #define CKG_MVD_RMEM1_GATED BIT0 273 #define CKG_MVD_RMEM1_INVERT BIT1 274 275 #define REG_CKG_MVD_RREFDAT (REG_CHIPTOP_BASE + 0x3e*2) 276 #define CKG_MVD_RREFDAT_GATED BIT0 277 #define CKG_MVD_RREFDAT_INVERT BIT1 278 279 #define REG_CKG_VD_AEON (REG_CHIPTOP_BASE + 0x30*2) 280 #define CKG_VD_AEON_GATED BIT0 281 #define CKG_VD_AEON_INVERT BIT1 282 #define CKG_VD_AEON_MASK (BIT6 | BIT5 | BIT4 | BIT3 | BIT2) 283 #define CKG_VD_AEON_160MHZ (0 << 2) 284 //Notice: The clock 160M comes from UTMI. 285 //Please start UTMI's clock before you switch to 160M 286 #define CKG_VD_AEON_144MHZ (1 << 2) 287 #define CKG_VD_AEON_123MHZ (2 << 2) 288 #define CKG_VD_AEON_108MHZ (3 << 2) 289 #define CKG_VD_AEON_96MHZ (4 << 2) 290 #define CKG_VD_AEON_72MHZ (5 << 2) 291 #define CKG_VD_AEON_DISABLE0 (6 << 2) //disable 292 #define CKG_VD_AEON_DISABLE1 (7 << 2) //disable 293 #define CKG_VD_AEON_CLK_MCU (1 << 5) //01xxx 294 #define CKG_VD_AEON_CLK_MIU (2 << 5) //10xxx 295 #define CKG_VD_AEON_XTAL (3 << 5) //11xxx 296 297 298 #define REG_CHIP_ID_MAJOR (CHIP_REG_BASE + 0xCC) 299 #define REG_CHIP_ID_MINOR (CHIP_REG_BASE + 0xCD) 300 #define REG_CHIP_VERSION (CHIP_REG_BASE + 0xCE) 301 #define REG_CHIP_REVISION (CHIP_REG_BASE + 0xCF) 302 303 #endif // _REG_MVD_H_ 304 305