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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_HVD_H_ 96 #define _HAL_HVD_H_ 97 #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE) 98 99 //------------------------------------------------------------------------------------------------- 100 // Macro and Define 101 //------------------------------------------------------------------------------------------------- 102 // Feature 103 #define HAL_HVD_ENABLE_MUTEX_PROTECT HVD_ENABLE_MUTEX_PROTECT 104 #define HAL_HVD_ENABLE_MIU_PROTECT HVD_ENABLE_MIU_RST_PROTECT 105 #define HAL_HVD_ENABLE_VPU_CMD 1 106 #define HAL_CHIP_SUPPORT_EVD 107 108 // MBox type of FW cmd 109 #if (HAL_HVD_ENABLE_VPU_CMD) 110 #define HAL_HVD_CMD_MBOX E_HVD_VPU_HI_0 111 #define HAL_HVD_CMD_ARG_MBOX E_HVD_VPU_HI_1 112 #else 113 #define HAL_HVD_CMD_MBOX E_HVD_HI_0 114 #define HAL_HVD_CMD_ARG_MBOX E_HVD_HI_1 115 #endif 116 // MBox other usages 117 #define HAL_HVD_REG_ISR_VPU E_HVD_VPU_RISC_1 118 #define HAL_HVD_REG_FW_STATE E_HVD_RISC_0 119 #define HAL_HVD_REG_ISR_HVD E_HVD_RISC_1 120 #define HAL_HVD_REG_DISP_INFO_COPYED E_HVD_RISC_1 121 #define HAL_HVD_REG_DISP_INFO_CHANGE E_HVD_RISC_1 122 #define HAL_HVD_REG_DISP_CTL E_HVD_HI_0 123 124 #define PRESET_ONE_PENDING_BUFFER (1 << 0) /// For AVC, one pending buffer mode, reduce from two to one 125 #define PRESET_FRAMERATE_HANDLING (1 << 1) /// For AVC, Handle frame rate by input frame rate when sequence did not have frame rate info. 126 127 #if defined(CHIP_T3) 128 // patch for HW bug 129 #define HVD_MIU1_BASE_ADDRESS 0x08000000UL//0x10000000UL 130 #else // CHIP_U3 131 #define HVD_MIU1_BASE_ADDRESS 0x08000000UL 132 #endif 133 134 #define HVD_RV_BROKENBYUS_BIT 29 135 136 #ifdef VDEC3 137 #define HAL_HVD_INVALID_BBU_ID 0xFFFFFFFF 138 #endif 139 140 //------------------------------------------------------------------------------------------------- 141 // Type and Structure 142 //------------------------------------------------------------------------------------------------- 143 144 typedef enum 145 { 146 E_HVD_HI_0, 147 E_HVD_HI_1, 148 E_HVD_RISC_0, 149 E_HVD_RISC_1, 150 E_HVD_VPU_HI_0, 151 E_HVD_VPU_HI_1, 152 E_HVD_VPU_RISC_0, 153 E_HVD_VPU_RISC_1, 154 } HVD_MBOX_TYPE; 155 156 typedef enum 157 { 158 //Support TSP/TS/File mode 159 E_HAL_HVD_MAIN_STREAM, 160 161 //Only support file mode 162 E_HAL_HVD_SUB_STREAM, 163 164 //Only support MVC mode 165 E_HAL_HVD_MVC_STREAM, 166 167 #ifdef VDEC3 168 E_HAL_HVD_N_STREAM, 169 #endif 170 } HAL_HVD_StreamType; 171 172 #ifdef VDEC3 173 typedef enum 174 { 175 E_HAL_HVD_AVC, 176 E_HAL_HVD_AVS, 177 E_HAL_HVD_RM, 178 E_HAL_HVD_MVC, 179 E_HAL_HVD_VP8, 180 E_HAL_HVD_MJPEG, 181 E_HAL_HVD_VP6, 182 E_HAL_HVD_HEVC, 183 E_HAL_HVD_VP9, 184 E_HAL_HVD_HEVC_DV, 185 E_HAL_HVD_NONE, 186 } HAL_HVD_CodecType; 187 188 typedef enum 189 { 190 E_HAL_HVD_STATE_STOP, 191 E_HAL_HVD_STATE_RUNNING, 192 E_HAL_HVD_STATE_PAUSING, 193 E_HAL_HVD_STATE_PAUSE_DONE 194 } HAL_HVD_Task_State; 195 196 #endif 197 198 typedef struct 199 { 200 HAL_HVD_StreamId eStreamId; 201 MS_BOOL bUsed; 202 MS_BOOL bDispOutSide; 203 MS_PHY u32PTSPreWptr; 204 MS_U32 u32PTSByteCnt; 205 MS_U32 u32BBUWptr; 206 MS_U32 u32BBUEntryNum; 207 MS_U32 u32BBUEntryNumTH; 208 MS_U32 u32DispQIndex; 209 MS_U32 u32PrivateData; 210 MS_U32 u32FreeData; 211 MS_U32 u32RegBase; 212 MS_BOOL bfirstGetFrmInfoDone; 213 #ifdef VDEC3 214 HAL_HVD_CodecType u32CodecType; 215 HAL_HVD_Task_State ePpTaskState; 216 MS_S32 s32HvdPpTaskId; 217 #endif 218 } HVD_EX_Stream; 219 220 typedef struct 221 { 222 MS_BOOL bColocateBBUMode; 223 224 }HVD_EX_PreSet; 225 226 //------------------------------------------------------------------------------------------------- 227 // Function and Variable 228 //------------------------------------------------------------------------------------------------- 229 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType); 230 MS_BOOL HAL_HVD_EX_DeinitHW(void); 231 void HAL_HVD_EX_FlushMemory(void); 232 void HAL_HVD_EX_ReadMemory(void); 233 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase); 234 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange); 235 MS_U32 HAL_HVD_EX_GetHWVersionID(void); 236 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType); 237 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable); 238 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase); 239 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id); 240 #ifdef VDEC3 241 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id); 242 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId); 243 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed); 244 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB); 245 #else 246 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id); 247 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id); 248 #endif 249 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data); 250 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType); 251 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType); 252 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id); 253 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id); 254 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate); 255 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg); 256 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id); 257 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo); 258 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable); 259 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable); 260 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType); 261 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id); 262 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id); 263 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id); 264 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id); 265 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id); 266 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable); 267 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr); 268 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data); 269 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock); 270 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id); 271 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable); 272 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id); 273 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num); 274 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl); 275 void HVD_EX_SetRstFlag(MS_BOOL bRst); 276 MS_BOOL HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id); 277 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id); 278 279 #if HVD_ENABLE_MVC 280 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id); 281 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id); 282 #endif ///HVD_ENABLE_MVC 283 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void); 284 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id); 285 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id); 286 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id); 287 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable); 288 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag); 289 #if SUPPORT_EVD 290 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id); 291 #endif 292 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void); 293 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id); 294 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl); 295 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id); 296 void HAL_HVD_MVDMiuClientSel(MS_U8 u8MiuSel); 297 typedef enum 298 { 299 E_BBU_FSM_START = 0, 300 E_BBU_FSM_0, 301 E_BBU_FSM_00, 302 E_BBU_FSM_001, 303 } VDEC_EX_BBU_FSM_STATE; 304 305 306 void HAL_HVD_EX_BBU_Proc(MS_U32 u32Id); 307 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32Id); 308 309 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void); 310 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 pDV_Stream_Profile); 311 #endif 312 #endif // _HAL_HVD_H_ 313 314