1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include <string.h>
101 #include "drvHVD_Common.h"
102
103 // Internal Definition
104 #include "drvHVD_def.h"
105 #include "fwHVD_if.h"
106 #include "halVPU_EX.h"
107 #include "halHVD_EX.h"
108 #include "regHVD_EX.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Driver Compiler Options
112 //-------------------------------------------------------------------------------------------------
113 #if !defined(MSOS_TYPE_NUTTX) || defined(SUPPORT_X_MODEL_FEATURE)
114
115 //-------------------------------------------------------------------------------------------------
116 // Local Defines
117 //-------------------------------------------------------------------------------------------------
118 #define RV_VLC_TABLE_SIZE 0x20000
119 /* Add for Mobile Platform by Ted Sun */
120 //#define HVD_DISPQ_PREFETCH_COUNT 2
121 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
122 #define VPU_QMEM_BASE 0x20000000UL
123
124 //max support pixel(by chip capacity)
125 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
126 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
127 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
128
129 #if 0
130 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
131 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
132 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
133 static MS_U16 _u16DispQPtr = 0;
134 #endif
135
136 //---------------------------------- Mutex settings -----------------------------------------
137 #if HAL_HVD_ENABLE_MUTEX_PROTECT
138 #define _HAL_HVD_MutexCreate() \
139 do \
140 { \
141 if (s32HVDMutexID < 0) \
142 { \
143 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
144 } \
145 } while (0)
146
147 #define _HAL_HVD_MutexDelete() \
148 do \
149 { \
150 if (s32HVDMutexID >= 0) \
151 { \
152 OSAL_HVD_MutexDelete(s32HVDMutexID); \
153 s32HVDMutexID = -1; \
154 } \
155 } while (0)
156
157 #define _HAL_HVD_Entry() \
158 do \
159 { \
160 if (s32HVDMutexID >= 0) \
161 { \
162 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
163 { \
164 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
165 } \
166 } \
167 } while (0)
168
169 #define _HAL_HVD_Return(_ret_) \
170 do \
171 { \
172 if (s32HVDMutexID >= 0) \
173 { \
174 OSAL_HVD_MutexRelease(s32HVDMutexID); \
175 } \
176 return _ret_; \
177 } while(0)
178
179 #define _HAL_HVD_Release() \
180 do \
181 { \
182 if (s32HVDMutexID >= 0) \
183 { \
184 OSAL_HVD_MutexRelease(s32HVDMutexID); \
185 } \
186 } while (0)
187 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
188
189 #define _HAL_HVD_MutexCreate()
190 #define _HAL_HVD_MutexDelete()
191 #define _HAL_HVD_Entry()
192 #define _HAL_HVD_Return(_ret) {return _ret;}
193 #define _HAL_HVD_Release()
194
195 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
196
197 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
198 #define IS_TASK_ALIVE(id) ((id) != -1)
199 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
200
201 //------------------------------ MIU SETTINGS ----------------------------------
202 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
203 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
204 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
205 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
206 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
207 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
208
209 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
210 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
211 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
212 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
213 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(3))
214 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
215
216 #define _MaskMiu2Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(4))
217 #define _MaskMiu2Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(4))
219 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(0))
222
223
224 #define HVD_MVD_RW_0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == 0))
225 #define HVD_MVD_RW_1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
226 #define HVD_MVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == 0))
227 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
228 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
229 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == 0))
230
231 #define HVD_MVD_RW_0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4)) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == 0))
232 #define HVD_MVD_RW_1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
233 #define HVD_MVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12)) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == 0))
234 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
235 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
236 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == 0))
237
238 #define HVD_MVD_RW_0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == BIT(4)))
239 #define HVD_MVD_RW_1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == BIT(6)))
240 #define HVD_MVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == BIT(12)))
241 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == BIT(2)))
242 #define HVD_HVD_RW_MIF1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == BIT(3)))
243 #define HVD_HVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == BIT(0)))
244
245
246 #if SUPPORT_EVD
247 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
248 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
249 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
250 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
251 #define _MaskMiu2Req_EVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
252 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
253
254
255
256
257 #define HVD_EVD_RW_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
258 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
259 #define HVD_EVD_RW_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
260 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
261 #define HVD_EVD_RW_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
262 #define HVD_EVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
263 #endif
264
265 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
266 do \
267 { \
268 if (HVD_##miu_clients##_ON_MIU0 == 1) \
269 { \
270 _MaskMiuReq_##miu_clients(mask); \
271 } \
272 else \
273 { \
274 if (HVD_##miu_clients##_ON_MIU1 == 1) \
275 { \
276 _MaskMiu1Req_##miu_clients(mask); \
277 } \
278 else if (HVD_##miu_clients##_ON_MIU2 == 1) \
279 { \
280 _MaskMiu2Req_##miu_clients(mask); \
281 } \
282 } \
283 } while (0)
284
285 // check RM is supported or not
286 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
287 #ifdef VDEC3
288 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
289 #else
290 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
291 #endif
292
293 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
294
295 //-------------------------------------------------------------------------------------------------
296 // Local Structures
297 //-------------------------------------------------------------------------------------------------
298
299 //-------------------------------------------------------------------------------------------------
300 // Local Functions Prototype
301 //-------------------------------------------------------------------------------------------------
302 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
303 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
304 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
305 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
306 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
307 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
308 static MS_U32 _HVD_EX_GetPC(void);
309 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
310 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
311 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
312 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
313 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
314 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
315 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
316 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
317 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
318 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
319 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
320 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
321 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
322 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
323 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
324 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
325 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
326 #if SUPPORT_EVD
327 static void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable);
328 static MS_BOOL HAL_EVD_EX_DeinitHW(void);
329 #endif
330 #if SUPPORT_G2VP9 && defined(VDEC3)
331 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
332 #endif
333 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
334 #if SUPPORT_G2VP9 && defined(VDEC3)
335 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
336 #endif
337 //-------------------------------------------------------------------------------------------------
338 // Global Variables
339 //-------------------------------------------------------------------------------------------------
340 #if defined (__aeon__)
341 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
342 #else
343 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
344 #endif
345 #if HAL_HVD_ENABLE_MUTEX_PROTECT
346 MS_S32 s32HVDMutexID = -1;
347 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
348 #endif
349
350
351 #define HVD_EX_STACK_SIZE 4096
352 //-------------------------------------------------------------------------------------------------
353 // Local Variables
354 //-------------------------------------------------------------------------------------------------
355 typedef struct
356 {
357
358 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
359 MS_U8 g_hvd_nal_fill_pair[2][8];
360 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
361 MS_U16 _u16DispQPtr;
362 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
363
364 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
365 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
366 MS_U32 u32VPUClockType;
367 MS_U32 u32HVDClockType;//160
368 #if SUPPORT_EVD
369 MS_U32 u32EVDClockType;
370 #endif
371 #if SUPPORT_G2VP9 && defined(VDEC3)
372 MS_U32 u32VP9ClockType;
373 #endif
374 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
375
376 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
377 MS_BOOL g_RstFlag;
378 MS_U64 u64pts_real;
379 MS_PHY u32VP8BBUWptr;
380 MS_PHY u32EVDBBUWptr;
381 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
382 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
383 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
384 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
385 //pre_set
386 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
387 } HVD_Hal_CTX;
388
389 HVD_Hal_CTX* pHVDHalContext = NULL;
390 HVD_Hal_CTX gHVDHalContext;
391 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
392
393 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
394 {
395 {FALSE},
396 {FALSE},
397 {FALSE},
398 #ifdef VDEC3
399 {FALSE},
400 #endif
401 };
402
403 //-------------------------------------------------------------------------------------------------
404 // Debug Functions
405 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)406 void HVD_EX_SetRstFlag(MS_BOOL bRst)
407 {
408 pHVDHalContext->g_RstFlag = bRst;
409 }
HVD_EX_GetRstFlag(void)410 MS_BOOL HVD_EX_GetRstFlag(void)
411 {
412 return pHVDHalContext->g_RstFlag;
413 }
414
415 //-------------------------------------------------------------------------------------------------
416 // Local Functions
417 //-------------------------------------------------------------------------------------------------
418
419 #ifdef VDEC3
420 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
421 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)422 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
423 {
424
425 MS_U32 ret = TRUE;
426 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
427
428 if(pCtrl == NULL || pstTaskInfo == NULL)
429 return FALSE;
430
431 pstTaskInfo->u32Id = u32Id;
432
433 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
434 {
435 case E_HVD_INIT_HW_RM:
436 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
437 break;
438 case E_HVD_INIT_HW_VP8:
439 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
440 break;
441 case E_HVD_INIT_HW_MVC:
442 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
443 break;
444 case E_HVD_INIT_HW_HEVC:
445 case E_HVD_INIT_HW_HEVC_DV:
446 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
447 break;
448 #if SUPPORT_MSVP9
449 case E_HVD_INIT_HW_VP9:
450 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
451 break;
452 #endif
453 #if SUPPORT_G2VP9
454 case E_HVD_INIT_HW_VP9:
455 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
456 break;
457 #endif
458 default:
459 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
460 break;
461 }
462
463 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
464
465 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
466 {
467 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
468 }
469 else
470 {
471 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
472 }
473
474 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
475
476 #ifdef SUPPORT_EVD
477 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
478 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
479 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
480 #endif
481 return ret;
482
483 }
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)484 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
485 {
486 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
487 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
488 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
489 _HAL_HVD_Entry();
490
491 if(pCtrl == NULL)
492 _HAL_HVD_Return(ret);
493
494 VPU_EX_TaskInfo taskInfo;
495 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
496
497 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
498
499 taskInfo.u8HalId = u8Idx;
500 ret = HAL_VPU_EX_GetBBUId(u32Id,&taskInfo, pCtrl->bNStreamMode);
501
502 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
503 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
504
505 _HAL_HVD_Return(ret);
506 }
507
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)508 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
509 {
510 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
511 MS_BOOL ret = FALSE;
512 _HAL_HVD_Entry();
513
514 if(pCtrl == NULL)
515 _HAL_HVD_Return(ret);
516 VPU_EX_TaskInfo taskInfo;
517 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
518
519 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
520
521 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
522
523 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
524 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
525
526 _HAL_HVD_Return(ret);
527 }
528 #endif
529
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)530 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
531 {
532 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
533 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
534 pstHVDStream->s32HvdPpTaskId = -1;
535 }
536
_HVD_EX_Context_Init_HAL(void)537 static void _HVD_EX_Context_Init_HAL(void)
538 {
539 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
540 pHVDHalContext->u32VPUClockType = 432;
541 pHVDHalContext->u32HVDClockType = 384;
542 #if SUPPORT_EVD
543 pHVDHalContext->u32EVDClockType = 576;
544 #endif
545 #if SUPPORT_G2VP9 && defined(VDEC3)
546 pHVDHalContext->u32VP9ClockType = 384;
547 #endif
548 #ifdef VDEC3
549 MS_U8 i;
550
551 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
552 {
553 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
554 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
555 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
556 }
557 #else
558 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
559 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
560 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
561 #endif
562 }
563
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)564 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
565 {
566 MS_U16 u16Ret = 0;
567 #if (HVD_ENABLE_MVC || (!VDEC3))
568 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
569 #endif
570 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
571 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
572 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
573 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
574
575 #if HVD_ENABLE_MVC
576 if(HAL_HVD_EX_CheckMVCID(u32Id))
577 {
578 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
579 }
580 #endif /// HVD_ENABLE_MVC
581
582 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
583 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
584
585 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
586 {
587 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
588 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
589 }
590 else
591 #ifdef VDEC3
592 if (0 == pCtrl->u32BBUId)
593 #else
594 if (0 == u8TaskId)
595 #endif
596 {
597 //if(pCtrl->InitParams.bColocateBBUMode)
598 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
599 u16Ret = pShm->u32ColocateBBUReadPtr;
600 else
601 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
602 }
603 else
604 {
605 //if(pCtrl->InitParams.bColocateBBUMode)
606 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
607 u16Ret = pShm->u32ColocateBBUReadPtr;
608 else
609 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
610 }
611
612 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
613 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
614
615 return u16Ret;
616 }
617
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)618 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
619 {
620 MS_U16 u16Ret = 0;
621 #if (HVD_ENABLE_MVC || (!VDEC3))
622 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
623 #endif
624 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
625 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
626 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
627 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
628
629 #if HVD_ENABLE_MVC
630 if (HAL_HVD_EX_CheckMVCID(u32Id))
631 {
632 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
633 }
634 #endif /// HVD_ENABLE_MVC
635 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
636 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
637
638 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
639 {
640 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
641 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
642 }
643 else
644 #ifdef VDEC3
645 if (0 == pDrvCtrl->u32BBUId)
646 #else
647 if (0 == u8TaskId)
648 #endif
649 {
650 //if(pDrvCtrl->InitParams.bColocateBBUMode)
651 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
652 u16Ret = pShm->u32ColocateBBUWritePtr;
653 else
654 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
655 }
656 else
657 {
658 //if(pDrvCtrl->InitParams.bColocateBBUMode)
659 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
660 u16Ret = pShm->u32ColocateBBUWritePtr;
661 else
662 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
663 }
664
665 return u16Ret;
666 }
667
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)668 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
669 {
670 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
671 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
672
673 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
674 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
675 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
676 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
677 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
678 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
679 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
680 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
681 }
682
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)683 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
684 {
685 #if (HVD_ENABLE_MVC || (!VDEC3))
686 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
687 #endif
688 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
689 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
690 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
691 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
692
693 #if HVD_ENABLE_MVC
694 if (HAL_HVD_EX_CheckMVCID(u32Id))
695 {
696 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
697 }
698 #endif /// HVD_ENABLE_MVC
699
700 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
701 {
702 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
703 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
704 }
705 else
706 #ifdef VDEC3
707 if (0 == pCtrl->u32BBUId)
708 #else
709 if (0 == u8TaskId)
710 #endif
711 {
712 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
713 //if(pCtrl->InitParams.bColocateBBUMode)
714 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
715 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
716 }
717 else
718 {
719 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
720 //if(pCtrl->InitParams.bColocateBBUMode)
721 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
722 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
723 }
724
725 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
726 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
727
728 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
729 }
730
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)731 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
732 {
733 MS_BOOL bResult = TRUE;
734 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
735 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
736
737 switch (u8MBox)
738 {
739 case E_HVD_HI_0:
740 {
741 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
742 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
743 break;
744 }
745 case E_HVD_HI_1:
746 {
747 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
748 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
749 break;
750 }
751 case E_HVD_VPU_HI_0:
752 {
753 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
754 break;
755 }
756 case E_HVD_VPU_HI_1:
757 {
758 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
759 break;
760 }
761 default:
762 {
763 bResult = FALSE;
764 break;
765 }
766 }
767
768 return bResult;
769 }
770
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)771 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
772 {
773 MS_BOOL bResult = TRUE;
774 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
775 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
776
777 switch (u8MBox)
778 {
779 case E_HVD_HI_0:
780 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
781 break;
782 case E_HVD_HI_1:
783 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
784 break;
785 case E_HVD_RISC_0:
786 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
787 break;
788 case E_HVD_RISC_1:
789 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
790 break;
791 case E_HVD_VPU_HI_0:
792 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
793 break;
794 case E_HVD_VPU_HI_1:
795 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
796 break;
797 case E_HVD_VPU_RISC_0:
798 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
799 break;
800 case E_HVD_VPU_RISC_1:
801 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
802 break;
803 default:
804 break;
805 }
806
807 return bResult;
808 }
809
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)810 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
811 {
812 MS_BOOL bResult = TRUE;
813 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
814 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
815
816 switch (u8MBox)
817 {
818 case E_HVD_HI_0:
819 {
820 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
821 break;
822 }
823 case E_HVD_HI_1:
824 {
825 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
826 break;
827 }
828 case E_HVD_RISC_0:
829 {
830 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
831 break;
832 }
833 case E_HVD_RISC_1:
834 {
835 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
836 break;
837 }
838 case E_HVD_VPU_RISC_0:
839 {
840 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
841 break;
842 }
843 case E_HVD_VPU_RISC_1:
844 {
845 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
846 break;
847 }
848 default:
849 {
850 bResult = FALSE;
851 break;
852 }
853 }
854
855 return bResult;
856 }
857
858 #if 0
859 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
860 {
861 switch (u8MBox)
862 {
863 case E_HVD_RISC_0:
864 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
865 break;
866 case E_HVD_RISC_1:
867 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
868 break;
869 case E_HVD_VPU_RISC_0:
870 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
871 break;
872 case E_HVD_VPU_RISC_1:
873 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
874 break;
875 default:
876 break;
877 }
878 }
879 #endif
880
_HVD_EX_GetPC(void)881 static MS_U32 _HVD_EX_GetPC(void)
882 {
883 MS_U32 u32PC = 0;
884 u32PC = HAL_VPU_EX_GetProgCnt();
885 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
886 return u32PC;
887 }
888
_HVD_EX_GetESWritePtr(MS_U32 u32Id)889 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
890 {
891 MS_U32 u32Data = 0;
892 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
893 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
894
895 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
896 {
897 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
898
899 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
900 {
901 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
902
903 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
904 }
905 }
906 else
907 {
908 #if HVD_ENABLE_MVC
909 MS_U8 u8ViewIdx = 0;
910 if(HAL_HVD_EX_CheckMVCID(u32Id))
911 {
912 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
913 }
914 if(u8ViewIdx != 0) /// 2nd ES ptr.
915 {
916 u32Data = pShm->u32ES2WritePtr;
917 }
918 else
919 {
920 u32Data = pShm->u32ESWritePtr;
921 }
922 #else
923 u32Data = pShm->u32ESWritePtr;
924 #endif
925 }
926
927 return u32Data;
928 }
929
930 #define NAL_UNIT_LEN_BITS 21
931 #define NAL_UNIT_OFT_BITS 30
932 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
933 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
934 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
935
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)936 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
937 {
938 MS_U32 u32Data = 0;
939 MS_U8 u8TaskId = 0;
940 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
941 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
942 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
943 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
944 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
945
946 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
947 #if HVD_ENABLE_MVC
948 if(HAL_HVD_EX_CheckMVCID(u32Id))
949 {
950 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
951 }
952 #endif /// HVD_ENABLE_MVC
953
954 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
955 {
956 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
957 {
958 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
959 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
960 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
961 MS_U32 *u32Adr;
962 MS_U32 u32Tmp;
963
964 if (u16ReadPtr == u16WritePtr)
965 {
966 u32Data = _HVD_EX_GetESWritePtr(u32Id);
967 }
968 else
969 {
970 if (u16ReadPtr)
971 u16ReadPtr--;
972 else
973 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
974
975 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
976
977 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
978 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
979 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
980 u32Data = u32Data | u32Tmp;
981
982 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
983 //while(1);
984 }
985 goto EXIT;
986 }
987 // set reg_poll_nal_rptr 0
988 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
989 // set reg_poll_nal_rptr 1
990 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
991
992 // read reg_nal_rptr_hi
993 #ifdef VDEC3
994 if (0 == pCtrl->u32BBUId)
995 #else
996 if (0 == u8TaskId)
997 #endif
998 {
999 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
1000 u32Data >>= 6;
1001 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
1002 }
1003 else
1004 {
1005 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
1006 u32Data >>= 6;
1007 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
1008 }
1009
1010 u32Data <<= 3; // unit
1011
1012 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1013 {
1014 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1015
1016 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1017 {
1018 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1019 u32Data = u32ESWptr;
1020 }
1021 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1022 {
1023 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1024 u32Data = u32ESWptr;
1025 }
1026 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1027 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1028 {
1029 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1030 u32Data = u32ESWptr;
1031 }
1032 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1033 && ((u32Data - u32ESWptr) < 32)
1034 && (pCtrl->u32FlushRstPtr == 1))
1035 {
1036 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1037 u32Data = u32ESWptr;
1038 }
1039 }
1040
1041 // remove illegal pointer
1042 #if 1
1043 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1044 {
1045 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1046
1047 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1048 (u32PacketStaddr <
1049 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1050 {
1051 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1052 u32Data = pCtrl->u32LastESRptr;
1053 }
1054 }
1055 #endif
1056 }
1057 else
1058 {
1059 #if HVD_ENABLE_MVC
1060 MS_U8 u8ViewIdx = 0;
1061 if(HAL_HVD_EX_CheckMVCID(u32Id))
1062 {
1063 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1064 }
1065 if(u8ViewIdx != 0) /// 2nd ES ptr.
1066 {
1067 u32Data = pShm->u32ES2ReadPtr;
1068 }
1069 else
1070 {
1071 u32Data = pShm->u32ESReadPtr;
1072 }
1073 #else
1074 u32Data = pShm->u32ESReadPtr;
1075 #endif
1076 }
1077
1078 EXIT:
1079
1080 pCtrl->u32LastESRptr = u32Data;
1081
1082 return u32Data;
1083 }
1084
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1085 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1086 {
1087 MS_U16 u16TimeOut = 0xFFFF;
1088 MS_BOOL bResult = FALSE;
1089
1090 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1091
1092 while (--u16TimeOut)
1093 {
1094 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1095 {
1096 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1097 break;
1098 }
1099 }
1100
1101 return bResult;
1102 }
1103
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1104 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1105 {
1106 MS_U16 u16TimeOut = 0xFFFF;
1107 MS_BOOL bResult = FALSE;
1108 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1109
1110 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1111
1112 #if HVD_ENABLE_MVC
1113 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1114 {
1115 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1116 }
1117 #endif /// HVD_ENABLE_MVC
1118
1119 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1120
1121 while (--u16TimeOut)
1122 {
1123 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1124 {
1125 u32Cmd |= (u8TaskId << 24);
1126 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1127 break;
1128 }
1129 }
1130 return bResult;
1131 }
1132
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1133 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1134 {
1135 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1136 #ifdef VDEC3
1137 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1138 MS_BOOL IsSent = FALSE;
1139 MS_BOOL IsMailBox = FALSE;
1140 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1141
1142 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1143 {
1144 do {
1145 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1146 if (!SentRet)
1147 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1148 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1149 break;
1150 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1151 IsSent = TRUE;
1152 break;
1153 }
1154 else if (HVD_GetSysTime_ms() > u32timeout)
1155 {
1156 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1157 break;
1158 }
1159 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1160 }
1161 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1162 {
1163 do {
1164 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1165 if (!SentRet)
1166 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1167 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1168 break;
1169 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1170 IsSent = TRUE;
1171 break;
1172 }
1173 else if (HVD_GetSysTime_ms() > u32timeout)
1174 {
1175 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1176 break;
1177 }
1178 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1179 }
1180 if (!IsSent) {
1181 IsMailBox = TRUE;
1182 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1183 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1184 #else
1185 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1186 #endif
1187 {
1188 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1189 if (HVD_GetSysTime_ms() > u32timeout)
1190 {
1191 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1192 return E_HVD_RETURN_TIMEOUT;
1193 }
1194 #endif
1195
1196 #if 0
1197 if (u32Cmd == E_HVD_CMD_STOP)
1198 {
1199 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1200 #if HVD_ENABLE_MVC
1201 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1202 {
1203 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1204 }
1205 #endif /// HVD_ENABLE_MVC
1206 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1207
1208 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1209 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1210
1211 return E_HVD_RETURN_SUCCESS;
1212 }
1213 #endif
1214
1215 if(u32Cmd < E_DUAL_CMD_BASE)
1216 {
1217 //_HVD_EX_GetPC();
1218 HAL_HVD_EX_Dump_FW_Status(u32Id);
1219 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1220 }
1221 }
1222
1223 #ifdef VDEC3
1224 }
1225 IsSent = FALSE;
1226 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1227 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1228 {
1229 do {
1230 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1231 if (!SentRet)
1232 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1233 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1234 break;
1235 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1236 IsSent = TRUE;
1237 break;
1238 }
1239 else if (HVD_GetSysTime_ms() > u32timeout)
1240 {
1241 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1242 break;
1243 }
1244 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1245 }
1246 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1247 {
1248 do {
1249 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1250 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1251 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1252 }
1253 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1254 break;
1255 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1256 IsSent = TRUE;
1257 break;
1258 }
1259 else if (HVD_GetSysTime_ms() > u32timeout)
1260 {
1261 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1262 break;
1263 }
1264 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1265 }
1266 if (!IsSent)
1267 {
1268 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1269 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1270 #else
1271 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1272
1273 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1274 #endif
1275 {
1276 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1277 if (HVD_GetSysTime_ms() > u32timeout)
1278 {
1279 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1280 return E_HVD_RETURN_TIMEOUT;
1281 }
1282 #endif
1283 if(u32Cmd < E_DUAL_CMD_BASE)
1284 {
1285 //_HVD_EX_GetPC();
1286 HAL_HVD_EX_Dump_FW_Status(u32Id);
1287 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1288 }
1289 }
1290 #ifdef VDEC3
1291 }
1292 else
1293 {
1294 HAL_HVD_EX_FlushMemory();
1295 }
1296 #endif
1297 return E_HVD_RETURN_SUCCESS;
1298 }
1299
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1300 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1301 {
1302 #if HAL_HVD_ENABLE_MIU_PROTECT
1303 _HVD_MIU_SetReqMask(MVD_RW_0, bEnable);
1304 _HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
1305 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1306 #if SUPPORT_EVD
1307 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1308 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1309 #endif
1310 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
1311 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
1312 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1313 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1314 //HVD_Delay_ms(1);
1315 #endif
1316 return;
1317 }
1318
1319 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)1320 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
1321 {
1322 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1323
1324 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
1325 #if SUPPORT_MSVP9
1326 || u32CodecType == E_HVD_INIT_HW_VP9
1327 #endif
1328 )
1329 return TRUE;
1330
1331 return FALSE;
1332 }
1333
_HAL_EX_IS_HVD(MS_U32 u32ModeFlag)1334 static MS_BOOL _HAL_EX_IS_HVD(MS_U32 u32ModeFlag) // VP8 isn't included
1335 {
1336 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1337
1338 if ((u32CodecType == E_HVD_INIT_HW_MVC) ||
1339 (u32CodecType == E_HVD_INIT_HW_AVC) ||
1340 (u32CodecType == E_HVD_INIT_HW_AVS) ||
1341 (u32CodecType == E_HVD_INIT_HW_RM))
1342 return TRUE;
1343
1344 return FALSE;
1345 }
1346
_HAL_EX_BBU_EVD_InUsed(void)1347 static MS_BOOL _HAL_EX_BBU_EVD_InUsed(void)
1348 {
1349 if (!pHVDHalContext)
1350 return FALSE;
1351
1352 MS_U32 i;
1353 MS_BOOL bRet = FALSE;
1354
1355 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1356 {
1357 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1358 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC)
1359 || (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC_DV)
1360 #if SUPPORT_MSVP9
1361 ||(pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP9)
1362 #endif
1363 ))
1364 {
1365 bRet = TRUE;
1366 break;
1367 }
1368 }
1369
1370 return bRet;
1371 }
1372
_HAL_EX_BBU_HVD_InUsed(void)1373 static MS_BOOL _HAL_EX_BBU_HVD_InUsed(void) // VP8 isn't included
1374 {
1375 if (!pHVDHalContext)
1376 return FALSE;
1377
1378 MS_U32 i;
1379 MS_BOOL bRet = FALSE;
1380
1381 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1382 {
1383 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1384 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVC) ||
1385 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVS) ||
1386 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_RM)))
1387 {
1388 bRet = TRUE;
1389 break;
1390 }
1391 }
1392
1393 return bRet;
1394 }
1395
_HAL_EX_BBU_VP8_InUsed(void)1396 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
1397 {
1398 if (!pHVDHalContext)
1399 return FALSE;
1400
1401 MS_U32 i;
1402 MS_BOOL bRet = FALSE;
1403
1404 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1405 {
1406 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
1407 {
1408 bRet = TRUE;
1409 break;
1410 }
1411 }
1412
1413 return bRet;
1414 }
1415
1416 #endif
1417
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1418 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1419 {
1420 MS_U16 u16Reg = 0;
1421 MS_VIRT u32StAddr = 0;
1422 #ifdef VDEC3
1423 MS_U32 u32Length = 0;
1424 #endif
1425 //MS_BOOL bBitMIU1 = FALSE;
1426 //MS_BOOL bCodeMIU1 = FALSE;
1427 MS_U8 u8BitMiuSel = 0;
1428 MS_U8 u8CodeMiuSel = 0;
1429 MS_U8 u8FBMiuSel = 0;
1430 MS_U32 u32BitStartOffset;
1431 MS_U32 u32CodeStartOffset;
1432 MS_U32 u32FBStartOffset;
1433
1434 MS_U8 u8TaskId = 0;
1435 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1436 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1437 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1438 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1439
1440 // MS_U32 u32TmpStartOffset;
1441 MS_U8 u8TmpMiuSel;
1442
1443
1444
1445 if(pCtrl == NULL) return;
1446
1447 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1448 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1449 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1450
1451 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1452 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1453 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1454 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1455 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1456 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1457 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1458 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1459 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1460 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
1461 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
1462
1463 if (u8BitMiuSel != u8CodeMiuSel)
1464 {
1465 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
1466 }
1467 else
1468 {
1469 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
1470 }
1471
1472 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1473 {
1474 #ifdef VDEC3
1475 if (!_HAL_EX_BBU_VP8_InUsed())
1476 #endif
1477 {
1478 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1479
1480 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1481 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1482 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1483
1484 u32StAddr += VP8_BBU_TBL_SIZE;
1485
1486 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1487 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1488 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1489 }
1490
1491 // ES buffer
1492 #ifdef VDEC3
1493 if(pCtrl->bNStreamMode)
1494 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1495 else
1496 #endif
1497 u32StAddr = u32BitStartOffset;
1498
1499 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1500
1501 #ifdef VDEC3
1502 if (!_HAL_EX_BBU_VP8_InUsed())
1503 #endif
1504 {
1505 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1506
1507 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1508 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1509
1510 #ifdef VDEC3
1511 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1512 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1513 #else
1514 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1515 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1516 #endif
1517
1518 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1519 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1520 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1521 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1522 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1523 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1524 }
1525
1526 return;
1527 }
1528
1529 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1530
1531 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
1532
1533 #ifdef VDEC3
1534 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1535 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1536 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1537 {
1538 if (pCtrl->u32BBUId == 0)
1539 {
1540 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1541 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1542 // -1 is for NAL_TAB_LEN counts from zero.
1543 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1544 }
1545 else
1546 {
1547 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1548 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1549 // -1 is for NAL_TAB_LEN counts from zero.
1550 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1551 }
1552 }
1553 #else
1554 if (0 == u8TaskId)
1555 {
1556 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1557 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1558 // -1 is for NAL_TAB_LEN counts from zero.
1559 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1560 }
1561 else
1562 {
1563 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1564 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1565 // -1 is for NAL_TAB_LEN counts from zero.
1566 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1567 }
1568 #endif
1569
1570 // ES buffer
1571 #ifdef VDEC3
1572 if(!pCtrl->bNStreamMode || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1573 {
1574 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1575 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1576 }
1577 else
1578 {
1579 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1580 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1581 }
1582 #else
1583 u32StAddr = u32BitStartOffset;
1584 #endif
1585
1586 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1587
1588 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1589
1590 #ifdef VDEC3
1591 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1592 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1593 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1594 {
1595 if (pCtrl->u32BBUId == 0)
1596 {
1597 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1598 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1599
1600 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1601 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1602 }
1603 else
1604 {
1605 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1606 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1607
1608 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1609 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1610 }
1611 }
1612 #else
1613 if (0 == u8TaskId)
1614 {
1615 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1616 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1617
1618 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1619 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1620 }
1621 else
1622 {
1623 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1624 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1625
1626 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1627 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1628 }
1629 #endif
1630
1631 // others
1632 #ifdef VDEC3
1633 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1634 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1635 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1636 {
1637 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1638
1639 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1640 {
1641 if (pCtrl->u32BBUId == 0)
1642 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1643 else
1644 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1645 }
1646 else
1647 {
1648 if (pCtrl->u32BBUId == 0)
1649 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1650 else
1651 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1652 }
1653
1654 if (pCtrl->u32BBUId == 0)
1655 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1656 else
1657 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1658
1659 if (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // RM
1660 {
1661 if (pCtrl->u32BBUId == 0) // force BBU to remove nothing, RM only
1662 u16Reg |= HVD_REG_BBU_PASER_DISABLE;
1663 else
1664 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2;
1665 }
1666 #if SUPPORT_MSVP9
1667 else if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1668 {
1669 if (pCtrl->u32BBUId == 0)
1670 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03;
1671 else
1672 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03_BS2;
1673 }
1674 #endif
1675 else // AVS or AVC or HEVC or HEVC_DV
1676 {
1677 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1678 {
1679 if (pCtrl->u32BBUId == 0)
1680 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1681 else
1682 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1683 }
1684 else // start code remained
1685 {
1686 if (pCtrl->u32BBUId == 0)
1687 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1688 else
1689 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1690 }
1691 }
1692
1693 if (pCtrl->u32BBUId == 0)
1694 {
1695 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1696 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1697 }
1698 else
1699 {
1700 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1701 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1702 }
1703 }
1704 #else
1705 if (0 == u8TaskId)
1706 {
1707 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1708
1709 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1710 {
1711 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1712 }
1713 else
1714 {
1715 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1716 }
1717
1718 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1719
1720 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1721 {
1722 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1723 }
1724 else // AVS or AVC
1725 {
1726 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1727 {
1728 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1729 }
1730 else // start code remained
1731 {
1732 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1733 }
1734 }
1735
1736 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1737
1738 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1739 }
1740 else
1741 {
1742 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1743
1744 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1745 {
1746 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1747 }
1748 else
1749 {
1750 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1751 }
1752
1753 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1754
1755 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1756 {
1757 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1758 }
1759 else // AVS or AVC
1760 {
1761 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1762 {
1763 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1764 }
1765 else // start code remained
1766 {
1767 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1768 }
1769 }
1770
1771 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1772
1773 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1774 }
1775 #endif
1776
1777 #if (HVD_ENABLE_MVC)
1778 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1779 {
1780 /// Used sub stream to record sub view data.
1781 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1782 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1783
1784 if (u8BitMiuSel != u8CodeMiuSel)
1785 {
1786 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
1787 }
1788 else
1789 {
1790 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
1791 }
1792
1793
1794 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
1795 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
1796 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
1797 // -1 is for NAL_TAB_LEN counts from zero.
1798 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1799
1800 // ES buffer
1801 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1802
1803 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1804 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1805 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1806
1807 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1808 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1809
1810 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1811 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1812 {
1813 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1814 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1815 }
1816 else
1817 {
1818 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1819 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1820 }
1821 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1822 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1823 {
1824 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1825 }
1826 else // AVS or AVC
1827 {
1828 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1829 {
1830 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1831 }
1832 else // start code remained
1833 {
1834 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1835 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1836 }
1837 }
1838 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1839 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1840 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1841 }
1842 #endif
1843
1844 // MIF offset
1845 #if 0
1846 {
1847 MS_U16 offaddr = 0;
1848 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1849 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1850 {
1851 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1852 }
1853 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1854 offaddr = (MS_U16) ((u32StAddr) >> 20);
1855 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1856 //0x1FF; // 9 bits(L + H)
1857 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1858 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1859 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1860 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1861 {
1862 u16Reg |= HVD_REG_MIF_OFFSET_H;
1863 }
1864 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1865 }
1866 #endif
1867 }
1868
1869 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1870 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1871 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1872 {
1873 MS_U16 u16Reg = 0;
1874 MS_U32 u32StAddr = 0;
1875 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1876 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1877 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1878
1879 if(pCtrl == NULL) return;
1880
1881 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1882 {
1883 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1884
1885 // ES buffer
1886 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1887
1888 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1889 {
1890 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1891 }
1892
1893 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1894 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1895
1896 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1897 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1898
1899 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1900 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1901 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1902 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1903 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1904 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1905
1906 return;
1907 }
1908
1909 // ES buffer
1910 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1911
1912 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1913 {
1914 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1915 }
1916
1917 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1918
1919 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1920 {
1921 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1922 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1923
1924 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1925 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1926 }
1927 else
1928 {
1929 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1930 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1931
1932 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1933 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1934 }
1935 }
1936 #endif
1937
_HVD_EX_GetESLevel(MS_U32 u32Id)1938 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1939 {
1940 MS_U32 u32Wptr = 0;
1941 MS_U32 u32Rptr = 0;
1942 MS_U32 u32CurMBX = 0;
1943 MS_U32 u32ESsize = 0;
1944 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1945 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1946
1947 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1948 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1949 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1950
1951 if (u32Rptr >= u32Wptr)
1952 {
1953 u32CurMBX = u32Rptr - u32Wptr;
1954 }
1955 else
1956 {
1957 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1958 }
1959
1960 if (u32CurMBX == 0)
1961 {
1962 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1963 }
1964 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1965 {
1966 u32Ret = E_HVD_ESB_LEVEL_OVER;
1967 }
1968 else
1969 {
1970 u32CurMBX = u32ESsize - u32CurMBX;
1971 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1972 {
1973 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1974 }
1975 }
1976
1977 return u32Ret;
1978 }
1979
_HVD_EX_GetESQuantity(MS_U32 u32Id)1980 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1981 {
1982 MS_U32 u32Wptr = 0;
1983 MS_U32 u32Rptr = 0;
1984 MS_U32 u32ESsize = 0;
1985 MS_U32 u32Ret = 0;
1986 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1987
1988 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1989 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1990 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1991
1992
1993 if(u32Wptr >= u32Rptr)
1994 {
1995 u32Ret = u32Wptr - u32Rptr;
1996 }
1997 else
1998 {
1999 u32Ret = u32ESsize - u32Rptr + u32Wptr;
2000 }
2001 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
2002 return u32Ret;
2003 }
2004
2005 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)2006 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
2007 {
2008
2009 MS_U32 u32Timeout = 20000;
2010
2011 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
2012 {
2013
2014 HAL_VPU_EX_IQMemSetDAMode(TRUE);
2015
2016 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
2017
2018
2019 while (u32Timeout)
2020 {
2021
2022 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
2023 {
2024 break;
2025 }
2026 u32Timeout--;
2027 HVD_Delay_ms(1);
2028 }
2029
2030 HAL_VPU_EX_IQMemSetDAMode(FALSE);
2031
2032 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
2033
2034 if (u32Timeout==0)
2035 {
2036 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
2037 return FALSE;
2038 }
2039
2040
2041 }
2042 return TRUE;
2043 }
2044
2045 #endif
2046
2047 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2048 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2049 #else
2050 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2051 #endif
2052 {
2053 MS_U32 u32FirmVer = 0;
2054 MS_U32 u32Timeout = 20000;
2055 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2056
2057 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2058
2059 #if HVD_ENABLE_TIME_MEASURE
2060 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2061 #endif
2062
2063 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2064
2065 VPU_EX_FWCodeCfg fwCfg;
2066 VPU_EX_TaskInfo taskInfo;
2067 VPU_EX_VLCTblCfg vlcCfg;
2068 #ifdef VDEC3
2069 VPU_EX_FBCfg fbCfg;
2070 #endif
2071 VPU_EX_NDecInitPara nDecInitPara;
2072
2073 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2074 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2075 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2076 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2077 #ifdef VDEC3_FB
2078 nDecInitPara.pVLCCfg = NULL;
2079 #else
2080 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2081 {
2082 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2083 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2084 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2085 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2086 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2087 nDecInitPara.pVLCCfg = &vlcCfg;
2088 }
2089 #endif
2090 nDecInitPara.pFWCodeCfg = &fwCfg;
2091 nDecInitPara.pTaskInfo = &taskInfo;
2092 #ifdef VDEC3
2093 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2094 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2095
2096 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2097 {
2098 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2099 }
2100
2101 nDecInitPara.pFBCfg = &fbCfg;
2102 #endif
2103
2104 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2105 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2106 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2107 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2108 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2109
2110 taskInfo.u32Id = u32Id;
2111
2112 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2113 {
2114 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2115 }
2116 #ifdef VDEC3
2117 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2118 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
2119 {
2120 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2121 }
2122 #if SUPPORT_MSVP9
2123 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2124 {
2125 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2126 }
2127 #endif
2128 #if SUPPORT_G2VP9
2129 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2130 {
2131 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2132 }
2133 #endif
2134 #endif
2135 else
2136 {
2137 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2138 }
2139
2140 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2141
2142 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2143 {
2144 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2145 }
2146 else
2147 {
2148 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2149 }
2150 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2151
2152 #ifdef SUPPORT_EVD
2153 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2154 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2155 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2156 #endif
2157
2158 if(TRUE == HVD_EX_GetRstFlag())
2159 {
2160 //Delete task for Rst
2161 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2162 {
2163 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2164 }
2165 HVD_EX_SetRstFlag(FALSE);
2166 }
2167
2168 #if (HVD_ENABLE_IQMEM)
2169 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2170 #endif
2171
2172 #ifdef VDEC3
2173 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2174 #else
2175 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2176 #endif
2177 {
2178 HVD_EX_MSG_ERR("Task create fail!\n");
2179
2180 return FALSE;
2181 }
2182
2183 while (u32Timeout)
2184 {
2185 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2186
2187 if (u32FirmVer != 0)
2188 {
2189 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2190 break;
2191 }
2192 u32Timeout--;
2193 HVD_Delay_ms(1);
2194 }
2195
2196 #ifdef VDEC3_FB
2197 #if HVD_ENABLE_RV_FEATURE
2198 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2199
2200 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2201 {
2202 if(pShm->u32RM_VLCTableAddr == 0) {
2203 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2204 }
2205 else
2206 {
2207 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2208 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2209 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2210 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2211 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2212 nDecInitPara.pVLCCfg = &vlcCfg;
2213 }
2214 }
2215
2216 if (nDecInitPara.pVLCCfg)
2217 {
2218 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2219 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2220 {
2221 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2222 return FALSE;
2223 }
2224 }
2225 #endif
2226 #endif
2227 if (u32Timeout > 0)
2228 {
2229 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2230
2231 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2232
2233 #ifdef VDEC3
2234 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2235 {
2236 case E_HVD_INIT_HW_AVC:
2237 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2238 break;
2239 case E_HVD_INIT_HW_AVS:
2240 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2241 break;
2242 case E_HVD_INIT_HW_RM:
2243 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2244 break;
2245 case E_HVD_INIT_HW_MVC:
2246 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2247 break;
2248 case E_HVD_INIT_HW_VP8:
2249 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2250 break;
2251 case E_HVD_INIT_HW_MJPEG:
2252 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2253 break;
2254 case E_HVD_INIT_HW_VP6:
2255 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2256 break;
2257 case E_HVD_INIT_HW_HEVC:
2258 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2259 break;
2260 case E_HVD_INIT_HW_VP9:
2261 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2262 break;
2263 case E_HVD_INIT_HW_HEVC_DV:
2264 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
2265 break;
2266 default:
2267 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2268 break;
2269 }
2270 #endif
2271
2272 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2273 }
2274 else
2275 {
2276 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2277 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2278
2279 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2280 {
2281 HVD_EX_MSG_ERR("Task delete fail!\n");
2282 }
2283
2284 return FALSE;
2285 }
2286
2287
2288
2289 #if (HVD_ENABLE_IQMEM)
2290
2291 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2292 {
2293
2294 HAL_HVD_EX_IQMem_Init(u32Id);
2295 }
2296 else{
2297 HVD_EX_MSG_DBG("not support IQMEM\n");
2298 }
2299 #endif
2300
2301
2302
2303
2304
2305
2306 #if HVD_ENABLE_TIME_MEASURE
2307 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2308 #endif
2309
2310 return TRUE;
2311 }
2312
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2313 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2314 {
2315 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2316 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2317 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2318 {
2319 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2320 }
2321 else
2322 {
2323 return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2324 }
2325 }
2326
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2327 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2328 {
2329 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2330 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2331
2332 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2333 {
2334 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2335 }
2336 else
2337 {
2338 return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2339 }
2340 }
2341
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2342 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2343 {
2344 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2345 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2346
2347 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2348 {
2349 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2350 {
2351 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2352 }
2353 }
2354 else
2355 {
2356 *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2357 }
2358 }
2359
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2360 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2361 {
2362 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2363 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2364 MS_VIRT u32DestAddr = 0;
2365 HVD_PTS_Entry PTSEntry;
2366 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2367 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2368 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2369
2370 // update R & W ptr
2371 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2372
2373 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2374
2375 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2376 {
2377 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2378 (MS_U32) MAX_PTS_TABLE_SIZE);
2379 return E_HVD_RETURN_FAIL;
2380 }
2381
2382 // check queue is full or not
2383 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2384 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2385
2386 if (u32PTSWptr == u32PTSRptr)
2387 {
2388 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2389 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2390 return E_HVD_RETURN_FAIL;
2391 }
2392
2393 // add one PTS entry
2394 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2395 PTSEntry.u32ID_L = pInfo->u32ID_L;
2396 PTSEntry.u32ID_H = pInfo->u32ID_H;
2397 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2398
2399 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2400
2401 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2402
2403 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2404
2405 HAL_HVD_EX_FlushMemory();
2406
2407 // update Write ptr
2408 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2409
2410 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2411
2412 return E_HVD_RETURN_SUCCESS;
2413 }
2414
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2415 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2416 {
2417 //---------------------------------------------------
2418 // item format in nal table:
2419 // reserved |borken| u32NalOffset | u32NalLen
2420 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2421 //---------------------------------------------------
2422 MS_VIRT u32Adr = 0;
2423 MS_U32 u32BBUNewWptr = 0;
2424 MS_U8 item[8];
2425 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2426 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2427 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2428 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2429
2430 #if HVD_ENABLE_MVC
2431 if(HAL_HVD_EX_CheckMVCID(u32Id))
2432 {
2433 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2434 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2435 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2436 {
2437 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2438 }
2439 }
2440 #endif /// HVD_ENABLE_MVC
2441
2442 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2443 {
2444 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2445 }
2446 else
2447 {
2448 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2449 }
2450 u32BBUNewWptr++;
2451 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2452
2453 // prepare nal entry
2454
2455 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
2456 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2457 {
2458 // NAL len 22 bits , HEVC level5 constrain
2459 item[0] = u32NalLen & 0xff;
2460 item[1] = (u32NalLen >> 8) & 0xff;
2461 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2462 item[3] = (u32NalOffset >> 2) & 0xff;
2463 item[4] = (u32NalOffset >> 10) & 0xff;
2464 item[5] = (u32NalOffset >> 18) & 0xff;
2465 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2466 item[7] = 0;
2467 }
2468 else
2469 {
2470 item[0] = u32NalLen & 0xff;
2471 item[1] = (u32NalLen >> 8) & 0xff;
2472 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2473 item[3] = (u32NalOffset >> 3) & 0xff;
2474 item[4] = (u32NalOffset >> 11) & 0xff;
2475 item[5] = (u32NalOffset >> 19) & 0xff;
2476 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2477 item[7] = 0;
2478 }
2479
2480 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2481 {
2482 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2483 }
2484 else
2485 {
2486 // add nal entry
2487 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2488 }
2489
2490 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2491
2492 HAL_HVD_EX_FlushMemory();
2493
2494 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2495
2496 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2497 {
2498 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2499 }
2500 else
2501 {
2502 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2503 }
2504
2505 return E_HVD_RETURN_SUCCESS;
2506 }
2507
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2508 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2509 {
2510 MS_U8 item[8];
2511 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2512 MS_VIRT u32Adr = 0;
2513 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2514 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2515 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2516
2517 /*
2518 printf("nal2 offset=0x%x, len=0x%x\n",
2519 u32NalOffset2, u32NalLen2);
2520 */
2521
2522 item[0] = u32NalLen2 & 0xff;
2523 item[1] = (u32NalLen2 >> 8) & 0xff;
2524 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2525 item[3] = (u32NalOffset2 >> 3) & 0xff;
2526 item[4] = (u32NalOffset2 >> 11) & 0xff;
2527 item[5] = (u32NalOffset2 >> 19) & 0xff;
2528 item[6] = (u32NalOffset2 >> 27) & 0x07;
2529 item[7] = 0;
2530
2531 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2532 {
2533 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2534 }
2535 else
2536 {
2537 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2538 }
2539
2540 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2541
2542 HAL_HVD_EX_FlushMemory();
2543
2544 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2545 }
2546
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2547 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2548 {
2549 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2550 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2551
2552 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2553 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2554 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2555 {
2556 MS_U16 i;
2557 MS_PHY u32VUIAddr;
2558 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2559
2560 HAL_HVD_EX_ReadMemory();
2561 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2562
2563 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2564 {
2565 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2566 {
2567 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2568 }
2569 else
2570 {
2571 *pData = *((MS_VIRT *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2572 }
2573 pData++;
2574 }
2575 }
2576 else
2577 {
2578 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2579 }
2580
2581 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2582 }
2583
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2584 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2585 {
2586 MS_U32 u32ReadPtr = 0;
2587 MS_U32 eRet = 0;
2588 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2589 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2590
2591 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2592 MS_U32 u32WritePtr = 0;
2593
2594 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2595 {
2596 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2597 }
2598 else
2599 {
2600 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2601 }
2602
2603 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2604
2605 if (u32WritePtr >= u32ReadPtr)
2606 {
2607 eRet = u32WritePtr - u32ReadPtr;
2608 }
2609 else
2610 {
2611 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2612 }
2613
2614 #if 0
2615 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2616 {
2617 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2618 }
2619 else
2620 {
2621 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2622 }
2623
2624 #endif
2625 return eRet;
2626 }
2627
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2628 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2629 {
2630 MS_U32 u32ReadPtr = 0;
2631 MS_U32 eRet = 0;
2632 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2633
2634 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2635
2636 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2637 {
2638 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2639 (MS_U32) MAX_PTS_TABLE_SIZE);
2640 return 0;
2641 }
2642
2643 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2644
2645 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2646 {
2647 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2648 }
2649 else
2650 {
2651 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2652 }
2653
2654 return eRet;
2655 }
2656
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)2657 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2658 {
2659 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2660
2661 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2662 }
2663
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2664 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2665 {
2666 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2667 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2668
2669 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2670 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2671 HAL_HVD_EX_ReadMemory();
2672 MS_U16 u16QNum = pShm->u16DispQNumb;
2673 MS_U16 u16QPtr = pShm->u16DispQPtr;
2674
2675 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2676
2677 if (bDolbyVision)
2678 {
2679 if (pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
2680 {
2681 return NULL;
2682 }
2683 else
2684 {
2685 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = FALSE;
2686 }
2687 }
2688
2689 #if (HVD_ENABLE_MVC)
2690 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2691
2692 if(bMVC || (bDolbyVision && !pShm->bSingleLayer))
2693 {
2694 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2695 {
2696 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2697 MS_U16 u16UsedFrm = 0;
2698 MS_U16 u16ResvFrmNum = ((u16RealQPtr % 2) == 0) ? 1 : 0; // need to check the next frame num is exist when get first frame.
2699 if (u16RealQPtr != u16QPtr)
2700 {
2701 if (u16RealQPtr > u16QPtr)
2702 {
2703 u16UsedFrm = u16RealQPtr - u16QPtr;
2704 }
2705 else
2706 {
2707 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2708 }
2709 }
2710
2711 if (u16QNum > (u16UsedFrm + u16ResvFrmNum))
2712 {
2713 u16QNum -= u16UsedFrm;
2714 u16QPtr = u16RealQPtr;
2715 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2716
2717 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2718 {
2719 if ((u16QPtr % 2) == 0)
2720 {
2721 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr + 1];
2722
2723 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2724 {
2725 return NULL;
2726 }
2727 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2728 if(bDolbyVision)
2729 {
2730 //HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, uid:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2731 }
2732 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2733 }
2734 else
2735 {
2736 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2737 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2738 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2739 volatile HVD_Frm_Information *pHvdFrmPrv = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1]; // must be odd
2740
2741 if(bDolbyVision)
2742 {
2743 //HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, uid:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2744 #if 0 // dump dolby metadata calculated by FW
2745 unsigned char *dump_addr = (unsigned char *)((void *)pShm + pShm->u32HVD_DBG_DUMP_ADDR - (u8Idx * 0x100000 + HVD_SHARE_MEM_ST_OFFSET));
2746 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2747 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2748 unsigned int i = 0;
2749 unsigned char arr[33] = {0};
2750 if(pVsyncBridgeExt != NULL)
2751 {
2752 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[u16QPtr]);
2753 }
2754 dump_addr += 32 * pFrmInfoExt->u8CurrentIndex;
2755 for (i = 0; i < 32; i++)
2756 {
2757 arr[i] = *(dump_addr + i);
2758 }
2759 HVD_PRINT("[md5]%02d=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x %02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x", (unsigned int)pFrmInfoExt->u8CurrentIndex, arr[0], arr[1], arr[2], arr[3], arr[4], arr[5], arr[6], arr[7], arr[8], arr[9], arr[10], arr[11], arr[12], arr[13], arr[14], arr[15], arr[16], arr[17], arr[18], arr[19], arr[20], arr[21], arr[22], arr[23], arr[24], arr[25], arr[26], arr[27], arr[28], arr[29], arr[30], arr[31]);
2760 #endif
2761 if(DIFF(pHvdFrmPrv->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
2762 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pHvdFrmPrv->u32TimeStamp, pHvdFrm->u32TimeStamp);
2763 }
2764 pHvdFrmPrv->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2765 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2766 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2767 }
2768 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2769 u16QPtr++;
2770 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2771 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2772
2773 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2774 }
2775 }
2776
2777 return NULL;
2778 }
2779
2780 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2781 //search the next frame to display
2782 while (u16QNum > 0)
2783 {
2784 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2785 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2786 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2787
2788 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2789 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2790 {
2791 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2792 /// Check the depned view was initial when Output the base view.
2793 if((u16QPtr%2) == 0)
2794 {
2795 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2796 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2797 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2798 {
2799 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2800 ///printf("Return NULL.\n");
2801 return NULL;
2802 }
2803 }
2804
2805 //printf("V:%d.\n",u16QPtr);
2806 pHVDHalContext->_u16DispQPtr = u16QPtr;
2807 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2808 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2809 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2810 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2811 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2812 }
2813
2814 u16QNum--;
2815 //go to next frame in the dispQ
2816 u16QPtr++;
2817
2818 if (u16QPtr >= pShm->u16DispQSize)
2819 {
2820 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2821 }
2822 }
2823 }
2824 else
2825 #endif ///HVD_ENABLE_MVC
2826 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
2827 if (_HVD_EX_IsHevcInterlaceField(u32Id))
2828 {
2829 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
2830 volatile HVD_Frm_Information *pHvdFrm_first = NULL;
2831
2832 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
2833 return NULL;
2834 }
2835
2836 while (u16QNum != 0)
2837 {
2838 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2839 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2840 {
2841 if (!first_field) // second get frame, we will check at least one paired in disp queue.
2842 {
2843 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2844 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2845 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2846
2847 if(pHvdFrm->u8FieldType == 1 || pHvdFrm->u8FieldType == 9 || pHvdFrm->u8FieldType == 11)
2848 pHvdFrm->u8FieldType = 0;
2849 else
2850 pHvdFrm->u8FieldType = 1;
2851 return (HVD_Frm_Information *)pHvdFrm;
2852 }
2853 else // first get frame, we will check at least one paired in disp queue.
2854 {
2855 if (pHvdFrm_first == NULL)
2856 {
2857 pHvdFrm_first = pHvdFrm;
2858 }
2859 else
2860 {
2861 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2862 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
2863
2864 //After flush, we cannot get the correct field type of first field from sei, so we use second field type to decide first field type.
2865 if (pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 0xff)
2866 {
2867 if (pHvdFrm->u8FieldType == 9)
2868 pHvdFrm_first->u8FieldType = 12;
2869 else if (pHvdFrm->u8FieldType == 10)
2870 pHvdFrm_first->u8FieldType = 11;
2871 else if (pHvdFrm->u8FieldType == 10)
2872 pHvdFrm_first->u8FieldType = 11;
2873 else if (pHvdFrm->u8FieldType == 1)
2874 pHvdFrm_first->u8FieldType = 2;
2875 else if (pHvdFrm->u8FieldType == 2)
2876 pHvdFrm_first->u8FieldType = 1;
2877 else
2878 {
2879 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2880 return NULL;
2881 }
2882 if ((pHvdFrm_first->u32ID_L >> 16) & 0x1)
2883 pHvdFrm_first->u32ID_L |= (1 << 16);
2884 else
2885 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2886 }
2887 else if (pHvdFrm_first->u8FieldType == 9 || pHvdFrm_first->u8FieldType == 10)
2888 {
2889 if (pHvdFrm_first->u8FieldType == 9 && pHvdFrm->u8FieldType == 12)
2890 {
2891 pHvdFrm_first->u32ID_L |= (1 << 16);
2892 pHvdFrm->u32ID_L |= (1 << 16);
2893 }
2894 else if (pHvdFrm_first->u8FieldType == 10 && pHvdFrm->u8FieldType == 11)
2895 {
2896 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2897 pHvdFrm->u32ID_L &= (~(1 << 16));
2898 }
2899 else
2900 {
2901 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2902 return NULL;
2903 }
2904 }
2905 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
2906 if (pHvdFrm_first->u8FieldType == 1 || pHvdFrm_first->u8FieldType == 9 || pHvdFrm_first->u8FieldType == 11)
2907 pHvdFrm_first->u8FieldType = 0;
2908 else
2909 pHvdFrm_first->u8FieldType = 1;
2910 return (HVD_Frm_Information *)pHvdFrm_first;
2911 }
2912 }
2913 }
2914 u16QNum--;
2915 //go to next frame in the dispQ
2916 u16QPtr++;
2917
2918 if (u16QPtr == pShm->u16DispQSize)
2919 {
2920 u16QPtr = 0; //wrap to the begin
2921 }
2922
2923 }
2924 return NULL;
2925 }
2926 else
2927 {
2928 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2929
2930 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2931 {
2932
2933 while (u16QNum != 0)
2934 {
2935 pHvdFrm = (volatile HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2936
2937 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2938 {
2939 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2940 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2941 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2942 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2943 }
2944 u16QNum--;
2945 //go to next frame in the dispQ
2946 if (bDolbyVision)
2947 u16QPtr += 2; // single layer must in even ptr
2948 else
2949 u16QPtr++;
2950
2951 if (u16QPtr >= pShm->u16DispQSize)
2952 {
2953 u16QPtr = 0; //wrap to the begin
2954 }
2955 }
2956
2957 return NULL;
2958 }
2959
2960 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2961 //search the next frame to display
2962 while (u16QNum != 0)
2963 {
2964 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2965
2966 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2967 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2968 {
2969 pHVDHalContext->_u16DispQPtr = u16QPtr;
2970 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2971 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2972 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2973 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2974 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2975 }
2976
2977 u16QNum--;
2978 //go to next frame in the dispQ
2979 u16QPtr++;
2980
2981 if (u16QPtr == pShm->u16DispQSize)
2982 {
2983 u16QPtr = 0; //wrap to the begin
2984 }
2985 }
2986 }
2987
2988 return NULL;
2989 }
2990
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2991 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2992 {
2993 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2994 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2995 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2996 {
2997 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2998 if(pVsyncBridgeExt != NULL)
2999 {
3000 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
3001 }
3002 }
3003 return pFrmInfoExt;
3004 }
3005
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)3006 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
3007 {
3008 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3009 MS_U64 u64Ret = 0;
3010 #if SUPPORT_EVD
3011 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
3012 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3013 #if SUPPORT_MSVP9
3014 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3015 #endif
3016 #endif
3017
3018 #if SUPPORT_EVD
3019 if (isEVD)
3020 {
3021 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
3022 }
3023 else
3024 #endif
3025 #if SUPPORT_G2VP9
3026 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3027 {
3028 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
3029 }
3030 else
3031 #endif
3032 {
3033 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
3034 }
3035
3036 return u64Ret;
3037 }
3038
3039 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)3040 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
3041 {
3042 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3043 MS_U16 u16QNum = pShm->u16DispQNumb;
3044 MS_U16 u16QPtr = pShm->u16DispQPtr;
3045 static volatile HVD_Frm_Information *pHvdFrm = NULL;
3046 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3047 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3048 MS_BOOL bMVC = FALSE;
3049 #if HVD_ENABLE_MVC
3050 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3051 #endif
3052
3053
3054 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
3055 {
3056 if (u16QNum == 1) return TRUE;
3057 }
3058
3059 while (u16QNum != 0)
3060 {
3061 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3062 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3063 {
3064 return FALSE;
3065 }
3066 u16QNum--;
3067 if (bDolbyVision)
3068 u16QPtr += 2; // single layer must in even ptr
3069 else
3070 u16QPtr++;
3071
3072 if (u16QPtr >= pShm->u16DispQSize)
3073 {
3074 u16QPtr = 0; //wrap to the begin
3075 }
3076 }
3077
3078 return TRUE;
3079 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)3080 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
3081 {
3082 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3083
3084 return &(_pHVDCtrls[u8DrvId]);
3085 }
3086
_HVD_EX_GetStreamIdx(MS_U32 u32Id)3087 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
3088 {
3089 MS_U8 u8OffsetIdx = 0;
3090 MS_U8 u8SidBaseMask = 0xF0;
3091 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
3092
3093 switch (eSidBase)
3094 {
3095 case E_HAL_HVD_MAIN_STREAM_BASE:
3096 {
3097 u8OffsetIdx = 0;
3098 break;
3099 }
3100 case E_HAL_VPU_SUB_STREAM_BASE:
3101 {
3102 u8OffsetIdx = 1;
3103 break;
3104 }
3105 case E_HAL_VPU_MVC_STREAM_BASE:
3106 {
3107 u8OffsetIdx = 0;
3108 break;
3109 }
3110 #ifdef VDEC3
3111 case E_HAL_VPU_N_STREAM_BASE:
3112 {
3113 u8OffsetIdx = (u32Id>>8) & 0xF;
3114 break;
3115 }
3116 #endif
3117 default:
3118 {
3119 u8OffsetIdx = 0;
3120 break;
3121 }
3122 }
3123
3124 return u8OffsetIdx;
3125 }
3126 /*
3127 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3128 {
3129 MS_U32 i = 0;
3130 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3131 {
3132 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
3133 {
3134 return TRUE;
3135 }
3136 }
3137 return FALSE;
3138 }
3139 */
3140
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3141 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3142 {
3143 MS_PHY u32PhyAddr = 0x0;
3144 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3145
3146 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3147 {
3148 return 0;
3149 }
3150
3151 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3152
3153 if (u32PhyAddr == 0xFFFFFFFF) //boris
3154 {
3155 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3156 }
3157 else
3158 {
3159 // TEE, common + share_info
3160 u32PhyAddr += COMMON_AREA_SIZE;
3161 }
3162
3163 return MsOS_PA2KSEG1(u32PhyAddr);
3164 }
3165
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3166 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3167 {
3168 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3169 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3170
3171 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3172 {
3173 return 0;
3174 }
3175
3176 MS_PHY u32PhyAddr = 0x0;
3177 #if 0
3178 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3179
3180 if (u32PhyAddr == 0xFFFFFFFF)
3181 {
3182 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3183 }
3184 #endif
3185 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3186 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3187
3188 return MsOS_PA2KSEG1(u32PhyAddr);
3189 }
3190
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3191 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3192 {
3193
3194 if (u8MiuSel == E_CHIP_MIU_0)
3195 {
3196 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3197 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3198 }
3199 else if (u8MiuSel == E_CHIP_MIU_1)
3200 {
3201 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3202 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3203 }
3204 else // 2
3205 {
3206 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3207 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3208 }
3209
3210 }
3211
3212 #if SUPPORT_G2VP9 && defined(VDEC3)
3213 #ifdef __ARM_NEON__
3214 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3215 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3216 {
3217 uint32x4x4_t data, data2;
3218 MS_U8* raster2 = raster + tile_w * 4;
3219
3220 data = vld4q_u32((const uint32_t *)tile);
3221 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3222
3223 vst1q_u32((uint32_t *)raster, data.val[0]);
3224 raster += stride;
3225 vst1q_u32((uint32_t *)raster, data.val[1]);
3226 raster += stride;
3227 vst1q_u32((uint32_t *)raster, data.val[2]);
3228 raster += stride;
3229 vst1q_u32((uint32_t *)raster, data.val[3]);
3230
3231
3232 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3233 raster2 += stride;
3234 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3235 raster2 += stride;
3236 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3237 raster2 += stride;
3238 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3239 }
3240 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3241 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3242 {
3243 MS_U8* tile0 = tile;
3244 MS_U8* tile1 = tile+16;
3245 MS_U8* tile2 = tile+32;
3246 MS_U8* tile3 = tile+48;
3247 int i;
3248
3249 for (i=0; i<4; i++) {
3250 raster[i] = tile0[i];
3251 raster[4+i] = tile1[i];
3252 raster[8+i] = tile2[i];
3253 raster[12+i] = tile3[i];
3254 }
3255
3256 for (i=0; i<4; i++) {
3257 raster[stride+i] = tile0[4+i];
3258 raster[stride+4+i] = tile1[4+i];
3259 raster[stride+8+i] = tile2[4+i];
3260 raster[stride+12+i] = tile3[4+i];
3261 }
3262
3263 for (i=0; i<4; i++) {
3264 raster[2*stride+i] = tile0[8+i];
3265 raster[2*stride+4+i] = tile1[8+i];
3266 raster[2*stride+8+i] = tile2[8+i];
3267 raster[2*stride+12+i] = tile3[8+i];
3268 }
3269
3270 for (i=0; i<4; i++) {
3271 raster[3*stride+i] = tile0[12+i];
3272 raster[3*stride+4+i] = tile1[12+i];
3273 raster[3*stride+8+i] = tile2[12+i];
3274 raster[3*stride+12+i] = tile3[12+i];
3275 }
3276 }
3277 #endif // #ifdef __ARM_NEON__
3278
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3279 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3280 {
3281 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3282 u32Id,
3283 E_TASK_PRI_MEDIUM,
3284 TRUE,
3285 NULL,
3286 32, // stack size..
3287 "HVD_PostProcess_task");
3288
3289 if (s32HvdPpTaskId < 0)
3290 {
3291 HVD_EX_MSG_ERR("Pp Task create failed\n");
3292
3293 return FALSE;
3294 }
3295
3296 HVD_EX_MSG_DBG("Pp Task create success\n");
3297 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3298
3299 return TRUE;
3300 }
3301
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3302 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3303 {
3304 return y * stride * h + x * w * h;
3305 }
3306
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3307 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3308 {
3309 return y * stride * h + x * w;
3310 }
3311
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3312 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3313 {
3314 raster[0] = tile[0];
3315 raster[1] = tile[1];
3316 raster[2] = tile[2];
3317 raster[3] = tile[3];
3318 raster[stride] = tile[4];
3319 raster[stride + 1] = tile[5];
3320 raster[stride + 2] = tile[6];
3321 raster[stride + 3] = tile[7];
3322 raster[2 * stride] = tile[8];
3323 raster[2 * stride + 1] = tile[9];
3324 raster[2 * stride + 2] = tile[10];
3325 raster[2 * stride + 3] = tile[11];
3326 raster[3 * stride] = tile[12];
3327 raster[3 * stride + 1] = tile[13];
3328 raster[3 * stride + 2] = tile[14];
3329 raster[3 * stride + 3] = tile[15];
3330 }
3331
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3332 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3333 {
3334 const MS_U32 tile_w = 4;
3335 const MS_U32 tile_h = 4;
3336 MS_U32 tile_stride = w;
3337 MS_U32 x, y;
3338 MS_U8 *dst1, *dst2;
3339 MS_U8 *src1, *src2;
3340
3341 #ifdef __ARM_NEON__
3342 // To overlap load and store, handle two blocks at the same time.
3343 dst1 = dst;
3344 src1 = src;
3345 for (y = 0; y < h / tile_h; y++)
3346 {
3347 dst2 = dst1;
3348 src2 = src1;
3349 for (x = 0; x <= (w/tile_w - 8); x+=8)
3350 {
3351 tile4x4_to_raster_8(
3352 dst2,
3353 src2,
3354 raster_stride, tile_w, tile_h);
3355 dst2 += tile_w * 8;
3356 src2 += tile_w * tile_h * 8;
3357 }
3358 dst1 += raster_stride * tile_h;
3359 src1 += tile_stride * tile_h;
3360 for (; x < w / tile_w; x++)
3361 {
3362 tile4x4_to_raster(
3363 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3364 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3365 raster_stride);
3366 }
3367 }
3368 #else
3369 dst1 = NULL;
3370 src1 = NULL;
3371 dst2 = NULL;
3372 src2 = NULL;
3373
3374 for (y = 0; y < h / tile_h; y++)
3375 {
3376 for (x = 0; x <= (w/tile_w - 4); x+=4)
3377 {
3378 tile4x4_to_raster_4(
3379 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3380 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3381 raster_stride);
3382 }
3383 for (; x < w / tile_w; x++)
3384 {
3385 tile4x4_to_raster(
3386 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3387 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3388 raster_stride);
3389 }
3390 }
3391 #endif
3392 }
3393
3394 #define FLUSH_CACHE_SIZE (256 * 1024)
3395
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3396 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3397 {
3398 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3399 if (u32Size > FLUSH_CACHE_SIZE)
3400 u32Size = FLUSH_CACHE_SIZE;
3401
3402 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3403 }
3404
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3405 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3406 {
3407 MS_U32 u32SkipSize = 0;
3408
3409 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3410 if (u32Size > FLUSH_CACHE_SIZE)
3411 {
3412 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3413 u32Size = FLUSH_CACHE_SIZE;
3414 }
3415
3416 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3417 }
3418
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3419 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3420 {
3421 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3422 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3423 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3424 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3425
3426 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3427
3428 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3429
3430 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3431 {
3432 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3433 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3434
3435 HVD_Delay_ms(1); // FIXME
3436
3437 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3438 continue;
3439
3440 HAL_HVD_EX_ReadMemory();
3441
3442 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3443 {
3444 MS_U8 *pSrcVA, *pDstVA;
3445 MS_U32 u32SrcPA, u32DstPA;
3446 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3447 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3448
3449 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3450 {
3451 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3452
3453 u16Width = pFrmInfo->u16Width;
3454 u16Height = pFrmInfo->u16Height;
3455 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3456 }
3457
3458 // Luma
3459 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3460 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3461
3462 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3463 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3464
3465 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3466 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3467
3468 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3469
3470 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3471
3472 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3473
3474 // Chroma
3475 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3476 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3477
3478 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3479 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3480
3481 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3482 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3483
3484 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3485
3486 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3487
3488 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3489
3490 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3491 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3492 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3493
3494 HAL_HVD_EX_FlushMemory();
3495
3496 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3497 break;
3498
3499 HAL_HVD_EX_ReadMemory();
3500 }
3501 }
3502
3503 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3504
3505 return TRUE;
3506 }
3507 #endif
3508
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3509 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3510 {
3511 #ifndef VDEC3
3512 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3513 #endif
3514 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3515 // MS_U8 u8MiuSel;
3516 // MS_U32 u32StartOffset;
3517
3518 #if SUPPORT_EVD
3519 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
3520 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3521 #if SUPPORT_MSVP9
3522 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3523 #endif
3524 #endif
3525 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
3526 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3527
3528 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3529 // re-setup clock.
3530 #if SUPPORT_G2VP9 && defined(VDEC3)
3531 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3532 #endif
3533
3534
3535 if (!HAL_VPU_EX_HVDInUsed())
3536 {
3537 printf("HVD power on\n");
3538 HAL_HVD_EX_PowerCtrl(TRUE);
3539 }
3540
3541 #if SUPPORT_EVD
3542 if (isEVD) /// Disable it for disable H264 IMI
3543 {
3544 #ifdef VDEC3
3545 if (!HAL_VPU_EX_EVDInUsed())
3546 #endif
3547 {
3548 printf("EVD power on\n");
3549 HAL_EVD_EX_PowerCtrl(TRUE);
3550 }
3551 }
3552 #endif
3553
3554 #if SUPPORT_G2VP9 && defined(VDEC3)
3555 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3556 {
3557 if (!HAL_VPU_EX_G2VP9InUsed())
3558 {
3559 printf("G2 VP9 power on\n");
3560 HAL_VP9_EX_PowerCtrl(TRUE);
3561 }
3562 }
3563 #endif
3564
3565 if ((!HAL_VPU_EX_HVDInUsed()) )
3566 {
3567 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3568 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3569 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3570 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3571
3572 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3573
3574 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
3575 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3576 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256);
3577 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256);
3578 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128);
3579 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128);
3580
3581 #if 0
3582 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3583 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3584 {
3585 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
3586
3587 _HAL_HVD_Entry();
3588 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3589 _HAL_HVD_Release();
3590
3591 }
3592 #endif
3593 }
3594
3595 #if SUPPORT_EVD
3596 if (isEVD)
3597 {
3598 #ifdef VDEC3
3599 if (!HAL_VPU_EX_EVDInUsed())
3600 #endif
3601 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3602 }
3603 #endif
3604
3605 #if SUPPORT_G2VP9 && defined(VDEC3)
3606 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3607 {
3608 if (!HAL_VPU_EX_G2VP9InUsed())
3609 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3610 }
3611 #endif
3612
3613
3614 if(pCtrl == NULL)
3615 {
3616 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3617 //return FALSE;
3618 goto RESET;
3619 }
3620
3621 #if SUPPORT_EVD
3622 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
3623 {
3624 #ifdef VDEC3
3625 if (!HAL_VPU_EX_EVDInUsed())
3626 #endif
3627 {
3628 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3629 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3630 }
3631
3632 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3633 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3634 {
3635 #ifdef VDEC3
3636 if (0 == pCtrl->u32BBUId)
3637 #else
3638 if (0 == u8TaskId)
3639 #endif
3640 {
3641 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3642 }
3643 else
3644 {
3645 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3646 }
3647 }
3648 goto RESET;
3649 }
3650 #endif
3651
3652 // HVD4, from JANUS and later chip
3653 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3654 {
3655 case E_HVD_INIT_HW_AVS:
3656 {
3657 #ifdef VDEC3
3658 if (0 == pCtrl->u32BBUId)
3659 #else
3660 if (0 == u8TaskId)
3661 #endif
3662 {
3663 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3664 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3665 }
3666 else
3667 {
3668 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3669 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3670 }
3671
3672 break;
3673 }
3674 case E_HVD_INIT_HW_RM:
3675 {
3676 #ifdef VDEC3
3677 if (0 == pCtrl->u32BBUId)
3678 #else
3679 if (0 == u8TaskId)
3680 #endif
3681 {
3682 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3683 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3684
3685 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3686 {
3687 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3688 }
3689 else // RV 8
3690 {
3691 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3692 }
3693 }
3694 else
3695 {
3696 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3697 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3698
3699 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3700 {
3701 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3702 }
3703 else // RV 8
3704 {
3705 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3706 }
3707
3708 }
3709
3710 break;
3711 }
3712 default:
3713 {
3714 #ifdef VDEC3
3715 if (0 == pCtrl->u32BBUId)
3716 #else
3717 if (0 == u8TaskId)
3718 #endif
3719 {
3720 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3721 }
3722 else
3723 {
3724 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3725 }
3726 break;
3727 }
3728 }
3729
3730 RESET:
3731
3732 #if 0 //Manhattan: use miu256bit
3733 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3734
3735 if (!HAL_VPU_EX_HVDInUsed())
3736 {
3737 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3738 }
3739
3740 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3741 #endif
3742
3743 #if SUPPORT_EVD
3744 if (isEVD)
3745 {
3746 #ifdef VDEC3
3747 if (!HAL_VPU_EX_EVDInUsed())
3748 #endif
3749 {
3750 printf("EVD miu 256 bits\n");
3751 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3752 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3753 }
3754 }
3755 #endif
3756 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3757 // Only ES buffer addrress needs to be set for VP8
3758 _HVD_EX_SetESBufferAddr(u32Id);
3759 #else
3760 if(DecoderType != E_VPU_EX_DECODER_MVD)
3761 {
3762 _HVD_EX_SetBufferAddr(u32Id);
3763 }
3764 #endif
3765 if (!HAL_VPU_EX_HVDInUsed())
3766 {
3767 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3768 }
3769
3770 #if SUPPORT_EVD
3771 if (isEVD)
3772 {
3773 #ifdef VDEC3
3774 if (!HAL_VPU_EX_EVDInUsed())
3775 #endif
3776 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3777 }
3778 #endif
3779
3780 #if SUPPORT_G2VP9 && defined(VDEC3)
3781 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3782 {
3783 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3784
3785 if (!HAL_VPU_EX_G2VP9InUsed())
3786 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3787
3788 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3789 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3790 }
3791 #endif
3792
3793 return TRUE;
3794 }
3795
HAL_HVD_EX_DeinitHW(void)3796 MS_BOOL HAL_HVD_EX_DeinitHW(void)
3797 {
3798 MS_U16 u16Timeout = 1000;
3799
3800 _HVD_EX_SetMIUProtectMask(TRUE);
3801
3802 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
3803 HAL_EVD_EX_DeinitHW();
3804 #endif
3805
3806 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3807
3808 while (u16Timeout)
3809 {
3810 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3811 {
3812 break;
3813 }
3814 u16Timeout--;
3815 }
3816
3817 HAL_HVD_EX_PowerCtrl(FALSE);
3818
3819 _HVD_EX_SetMIUProtectMask(FALSE);
3820
3821 return TRUE;
3822 }
3823
HAL_HVD_EX_FlushMemory(void)3824 void HAL_HVD_EX_FlushMemory(void)
3825 {
3826 MsOS_FlushMemory();
3827 }
3828
HAL_HVD_EX_ReadMemory(void)3829 void HAL_HVD_EX_ReadMemory(void)
3830 {
3831 MsOS_ReadMemory();
3832 }
3833
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3834 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3835 {
3836 _pHVDCtrls = pHVDCtrlsBase;
3837 }
3838
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3839 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3840 {
3841 return;
3842 }
3843
HAL_HVD_EX_GetHWVersionID(void)3844 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3845 {
3846 return _HVD_Read2Byte(HVD_REG_REV_ID);
3847 }
3848
3849
HAL_HVD_EX_Init_Share_Mem(void)3850 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3851 {
3852 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3853 #if !defined(SUPPORT_X_MODEL_FEATURE)
3854 MS_U32 u32ShmId;
3855 MS_VIRT u32Addr;
3856 MS_U32 u32BufSize;
3857
3858
3859 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3860 sizeof(HVD_Hal_CTX),
3861 &u32ShmId,
3862 &u32Addr,
3863 &u32BufSize,
3864 MSOS_SHM_QUERY))
3865 {
3866 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3867 sizeof(HVD_Hal_CTX),
3868 &u32ShmId,
3869 &u32Addr,
3870 &u32BufSize,
3871 MSOS_SHM_CREATE))
3872 {
3873 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3874 if(pHVDHalContext == NULL)
3875 {
3876 pHVDHalContext = &gHVDHalContext;
3877 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3878 _HVD_EX_Context_Init_HAL();
3879 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3880 }
3881 else
3882 {
3883 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3884 }
3885 //return FALSE;
3886 }
3887 else
3888 {
3889 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3890 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3891 _HVD_EX_Context_Init_HAL();
3892 }
3893 }
3894 else
3895 {
3896 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3897 }
3898 #else
3899 if(pHVDHalContext == NULL)
3900 {
3901 pHVDHalContext = &gHVDHalContext;
3902 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3903 _HVD_EX_Context_Init_HAL();
3904 }
3905 #endif
3906 _HAL_HVD_MutexCreate();
3907 #else
3908 if(pHVDHalContext == NULL)
3909 {
3910 pHVDHalContext = &gHVDHalContext;
3911 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3912 _HVD_EX_Context_Init_HAL();
3913 }
3914 #endif
3915
3916 return TRUE;
3917 }
3918
3919
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3920 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3921 {
3922 MS_U32 i = 0;
3923
3924 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3925 {
3926 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3927 return pHVDHalContext->_stHVDStream[0].eStreamId;
3928 }
3929 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3930 {
3931 for (i = 0;
3932 i <
3933 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3934 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3935 {
3936 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3937 {
3938 return pHVDHalContext->_stHVDStream[i].eStreamId;
3939 }
3940 }
3941 }
3942 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3943 {
3944 for (i = 0;
3945 i <
3946 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3947 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3948 {
3949 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3950 {
3951 return pHVDHalContext->_stHVDStream[i].eStreamId;
3952 }
3953 }
3954 }
3955 #ifdef VDEC3
3956 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3957 {
3958 i = eStreamType - E_HAL_HVD_N_STREAM;
3959 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3960 return pHVDHalContext->_stHVDStream[i].eStreamId;
3961 }
3962 #endif
3963
3964 return E_HAL_HVD_STREAM_NONE;
3965 }
3966
HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)3967 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)
3968 {
3969 if (bEnable)
3970 {
3971 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3972 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3973 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3974 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
3975 }
3976 else
3977 {
3978 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3979 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3980 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3981 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
3982 }
3983
3984 // fix to not inverse
3985 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
3986
3987 switch (pHVDHalContext->u32HVDClockType)
3988 {
3989 #if 0 //for overclocking
3990 case 432:
3991 {
3992 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
3993 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3994 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3995 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
3996 break;
3997 }
3998 #endif
3999 case 384:
4000 {
4001 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4002 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4003 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4004 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4005 break;
4006 }
4007 case 345:
4008 {
4009 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
4010 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4011 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4012 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4013 break;
4014 }
4015 case 320:
4016 {
4017 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
4018 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_345MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4019 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4020 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4021 break;
4022 }
4023 case 288:
4024 {
4025 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4026 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4027 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4028 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4029 break;
4030 }
4031 case 240:
4032 {
4033 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
4034 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4035 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4036 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4037 break;
4038 }
4039 case 216:
4040 {
4041 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
4042 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4043 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4044 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
4045 break;
4046 }
4047 case 172:
4048 {
4049 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
4050 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4051 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4052 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
4053 break;
4054 }
4055
4056 default:
4057 {
4058 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4059 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4060 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4061 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4062 break;
4063 }
4064 }
4065
4066 return;
4067 }
4068
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4069 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4070 {
4071 u32HVDRegOSBase = u32RegBase;
4072 HAL_VPU_EX_InitRegBase(u32RegBase);
4073 }
4074
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4075 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4076 {
4077 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4078 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4079 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4080 }
4081
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4082 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4083 {
4084 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4085 HVD_ShareMem *pShm = NULL;
4086 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4087 #if HVD_ENABLE_MVC
4088 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4089 #endif ///HVD_ENABLE_MVC
4090
4091 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4092 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4093 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4094 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4095 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4096 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = TRUE;
4097 int i;
4098 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4099 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4100 #if HVD_ENABLE_MVC
4101 if(bMVC)
4102 {
4103 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4104 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4105 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4106 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4107 }
4108 #endif ///HVD_ENABLE_MVC
4109
4110 // set a local copy of FW code address; assuming there is only one copy of FW,
4111 // no matter how many task will be created.
4112
4113 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4114
4115 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4116
4117 // global variables
4118 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4119
4120
4121 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4122 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4123 // Create mutex
4124 //_HAL_HVD_MutexCreate();
4125
4126 // fill HVD init variables
4127 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4128 {
4129 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4130 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4131 }
4132 else
4133 #if HVD_ENABLE_RV_FEATURE
4134 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4135 {
4136 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4137 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4138 #ifdef VDEC3_FB
4139 pHVDHalContext->u32RV_VLCTableAddr = 0;
4140 #else
4141 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4142 {
4143 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4144 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4145 }
4146 else
4147 {
4148 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4149 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4150 return E_HVD_RETURN_INVALID_PARAMETER;
4151 }
4152 #endif
4153 }
4154 else
4155 #endif
4156 {
4157 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4158 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4159 #if HVD_ENABLE_MVC
4160 if(bMVC)
4161 {
4162 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4163 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4164 }
4165 #endif /// HVD_ENABLE_MVC
4166 pHVDHalContext->u32RV_VLCTableAddr = 0;
4167 }
4168
4169 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4170 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4171 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4172 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4173 {
4174 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4175 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4176 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4177 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4178 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4179 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4180 #if HVD_ENABLE_MVC
4181 if(bMVC)
4182 {
4183 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4184 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4185 {
4186 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4187 }
4188 }
4189 #endif /// HVD_ENABLE_MVC
4190
4191 return E_HVD_RETURN_SUCCESS;
4192 }
4193 else
4194 {
4195 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4196 (unsigned long)MS_PA2KSEG1((MS_VIRT) pShm),
4197 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4198 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4199 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4200 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4201 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4202 return E_HVD_RETURN_INVALID_PARAMETER;
4203 }
4204 }
4205
4206 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4207 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4208 #else
4209 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4210 #endif
4211 {
4212 MS_U32 u32Addr = 0;
4213 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4214 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4215 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4216
4217 MS_U32 u32TmpStartOffset;
4218 MS_U8 u8TmpMiuSel;
4219
4220
4221 memset(pShm, 0, sizeof(HVD_ShareMem));
4222
4223 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4224
4225 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4226 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4227 #ifdef VDEC3
4228 if (bFWdecideFB || bCMAUsed)
4229 {
4230 pShm->u32FrameBufAddr = 0;
4231 pShm->u32FrameBufSize = 0;
4232 }
4233 else
4234 #endif
4235 {
4236 pShm->u32FrameBufAddr = u32Addr;
4237 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4238 }
4239
4240 // FIXME: need to use the avaliable task resource instead of using next task resource
4241 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
4242 pShm->u8ExternalHeapIdx = u8Idx + 1;
4243 else
4244 pShm->u8ExternalHeapIdx = 0xFF;
4245
4246 pShm->DispInfo.u16DispWidth = 1;
4247 pShm->DispInfo.u16DispHeight = 1;
4248 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4249 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4250 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4251 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4252 //Chip info
4253 pShm->u16ChipID = E_MSTAR_CHIP_MACAN;
4254 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4255 // PreSetControl
4256 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bOnePendingBuffer)
4257 {
4258 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4259 }
4260
4261 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bCalFrameRate)
4262 {
4263 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
4264 }
4265
4266 pShm->bUseTSPInBBUMode = FALSE;
4267
4268
4269 if ((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
4270 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4271 {
4272 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4273
4274 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
4275
4276 pShm->u32IapGnBufAddr = u32Addr;
4277 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufSize;
4278
4279 }
4280
4281 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4282 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4283 {
4284 case E_HVD_DEF_MFCODEC_DEFAULT:
4285 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4286 break;
4287 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4288 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4289 break;
4290 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4291 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4292 break;
4293 default:
4294 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4295 }
4296 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4297 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4298 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4299 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4300 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4301 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4302
4303 if ((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stPreConnectDispPath.bEnable))
4304 {
4305 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4306 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stPreConnectDispPath.stDynmcDispPath.bConnect;
4307 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
4308 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4309 }
4310
4311 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4312 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
4313 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4314 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4315 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4316 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4317 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4318 else
4319 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4320 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4321 {
4322 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4323 {
4324 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4325 }
4326 else
4327 {
4328 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4329 }
4330 }
4331 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4332 {
4333 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4334 {
4335 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4336 }
4337 else
4338 {
4339 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4340 }
4341 }
4342 else
4343 {
4344 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4345 }
4346
4347 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4348 {
4349 pShm->bHVDIMIEnable = FALSE;
4350 }
4351
4352 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4353 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4354 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4355 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4356 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4357 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4358 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4359 (E_HVD_INIT_HW_MVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4360 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4361 {
4362 pShm->bUseWbMvop = 1;
4363 }
4364 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4365
4366 #if (VPU_FORCE_MIU_MODE)
4367 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4368
4369 pShm->u32FWBaseAddr = u32TmpStartOffset;
4370
4371 #else
4372 ///TODO:
4373 /*
4374 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4375
4376 if(u8TmpMiuSel == E_CHIP_MIU_0)
4377 {
4378 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4379 }
4380 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4381 {
4382 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4383 }
4384 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4385 {
4386 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4387 }
4388 */
4389 #endif
4390 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4391 #else
4392 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4393 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4394 {
4395 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4396 }
4397 pShm->u32FWBaseAddr = u32Addr;
4398 #endif
4399
4400 // RM only
4401 #if HVD_ENABLE_RV_FEATURE
4402 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4403 && (pCtrl->InitParams.pRVFileInfo != NULL))
4404 {
4405 MS_U32 i = 0;
4406
4407 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4408 {
4409 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4410 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4411 }
4412
4413 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4414 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4415 #ifdef VDEC3_FB
4416 pShm->u32RM_VLCTableAddr = 0;
4417 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4418 #else
4419 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4420
4421 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4422 u32Addr = u32TmpStartOffset;
4423
4424 pShm->u32RM_VLCTableAddr = u32Addr;
4425 #endif
4426 }
4427 #endif
4428
4429 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4430 && (pCtrl->InitParams.pRVFileInfo != NULL))
4431 {
4432 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4433 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4434 }
4435
4436 //if(pCtrl->InitParams.bColocateBBUMode)
4437 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4438 {
4439 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4440 }
4441
4442 #if SUPPORT_G2VP9
4443 // Enable SW detile support for G2 VP9
4444 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4445 {
4446 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4447 }
4448 #endif
4449
4450 HAL_HVD_EX_FlushMemory();
4451
4452 return E_HVD_RETURN_SUCCESS;
4453 }
4454 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4455 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4456 #else
4457 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4458 #endif
4459 {
4460 MS_BOOL bInitRet = FALSE;
4461
4462 #if 0
4463 // check MVD power on
4464 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4465 {
4466 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4467 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4468 HVD_Delay_ms(1);
4469 }
4470 // Check VPU power on
4471 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4472 {
4473 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4474 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4475 HVD_Delay_ms(1);
4476 }
4477 // check HVD power on
4478 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4479 {
4480 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4481 HAL_HVD_EX_PowerCtrl(TRUE);
4482 HVD_Delay_ms(1);
4483 }
4484 #endif
4485 #ifdef VDEC3
4486 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4487 #else
4488 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4489 #endif
4490 if (!bInitRet)
4491 {
4492 return E_HVD_RETURN_FAIL;
4493 }
4494
4495 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4496
4497 if (!bInitRet)
4498 {
4499 return E_HVD_RETURN_FAIL;
4500 }
4501
4502 return E_HVD_RETURN_SUCCESS;
4503 }
4504
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4505 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4506 {
4507 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4508
4509 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4510
4511 return E_HVD_RETURN_SUCCESS;
4512 }
4513
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4514 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4515 {
4516 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4517 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4518 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4519 MS_BOOL bMVC = FALSE;
4520 #if HVD_ENABLE_MVC
4521 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4522 #endif
4523
4524 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4525 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4526
4527 switch (u32type)
4528 {
4529 // share memory
4530 // switch
4531 case E_HVD_SDATA_FRAMEBUF_ADDR:
4532 {
4533 pShm->u32FrameBufAddr = u32Data;
4534 break;
4535 }
4536 case E_HVD_SDATA_FRAMEBUF_SIZE:
4537 {
4538 pShm->u32FrameBufSize = u32Data;
4539 break;
4540 }
4541 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4542 {
4543 pShm->u32FrameBuf2Addr = u32Data;
4544 break;
4545 }
4546 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4547 {
4548 pShm->u32FrameBuf2Size = u32Data;
4549 break;
4550 }
4551 case E_HVD_SDATA_CMA_USED:
4552 {
4553 pShm->bCMA_Use = u32Data;
4554 break;
4555 }
4556 case E_HVD_SDATA_CMA_ALLOC_DONE:
4557 {
4558 pShm->bCMA_AllocDone = u32Data;
4559 break;
4560 }
4561 case E_HVD_SDATA_CMA_TWO_MIU:
4562 {
4563 pShm->bCMA_TwoMIU = u32Data;
4564 break;
4565 }
4566 case E_HVD_SDATA_RM_PICTURE_SIZES:
4567 {
4568 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4569 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4570 break;
4571 }
4572 case E_HVD_SDATA_ERROR_CODE:
4573 {
4574 pShm->u16ErrCode = (MS_U16) u32Data;
4575 break;
4576 }
4577 case E_HVD_SDATA_DISP_INFO_TH:
4578 {
4579 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4580 sizeof(HVD_DISP_THRESHOLD));
4581 break;
4582 }
4583 case E_HVD_SDATA_FW_FLUSH_STATUS:
4584 {
4585 pShm->u8FlushStatus = (MS_U8)u32Data;
4586 break;
4587 }
4588 case E_HVD_SDATA_DMX_FRAMERATE:
4589 {
4590 pShm->u32DmxFrameRate = u32Data;
4591 break;
4592 }
4593 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4594 {
4595 pShm->u32DmxFrameRateBase = u32Data;
4596 break;
4597 }
4598 case E_HVD_SDATA_MIU_SEL:
4599 {
4600 pShm->u32VDEC_MIU_SEL = u32Data;
4601 break;
4602 }
4603 case E_HVD_SDATA_DV_XC_SHM_SIZE:
4604 {
4605 pShm->u32DolbyVisionXCShmSize = u32Data;
4606 break;
4607 }
4608 // SRAM
4609
4610 // Mailbox
4611 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4612 {
4613 if (u32Data != 0)
4614 {
4615 pShm->bEnableDispCtrl = TRUE;
4616 pShm->bIsTrigDisp = TRUE;
4617 }
4618 else
4619 {
4620 pShm->bEnableDispCtrl = FALSE;
4621 }
4622
4623 break;
4624 }
4625 case E_HVD_SDATA_GET_DISP_INFO_START:
4626 {
4627 pShm->bSpsChange = FALSE;
4628 break;
4629 }
4630 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4631 {
4632 pShm->u32VirtualBoxWidth = u32Data;
4633 break;
4634 }
4635 case E_HVD_SDATA_DV_INFO:
4636 {
4637 pShm->u8DVLevelFromDriverAPI = (MS_U8)(u32Data & 0xff);
4638 pShm->u8DVProfileFromDriverAPI = (MS_U8)((u32Data >> 8) & 0xff);
4639 pShm->u8DolbyMetaReorder = (MS_U8)((u32Data >> 16) & 0xff);
4640
4641 break;
4642 }
4643 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4644 {
4645 pShm->u32VirtualBoxHeight = u32Data;
4646 break;
4647 }
4648 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4649 {
4650 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4651 {
4652 //printf("DispFrame DqPtr: %d\n", u32Data);
4653 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4654 }
4655 break;
4656 }
4657 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4658 {
4659 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4660 {
4661 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4662 {
4663 //printf("DispFrame DqPtr: %ld\n", u32Data);
4664 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4665 }
4666 }
4667 break;
4668 }
4669 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4670 {
4671 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4672 {
4673 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
4674 {
4675 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4676 {
4677 //ALOGE("R1: %x", u32Data);
4678 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4679 }
4680 else
4681 {
4682 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4683 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4684 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4685 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4686 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4687 }
4688 }
4689 else
4690 {
4691 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4692 }
4693 }
4694 else
4695 {
4696 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4697 {
4698 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4699 }
4700 }
4701 break;
4702 }
4703 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
4704 {
4705 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
4706 break;
4707 }
4708 case E_HVD_SDATA_HDR_PERFRAME:
4709 {
4710 if (u32Data != 0)
4711 {
4712 pShm->u8IsDoblyHDR10 = TRUE;
4713 }
4714 else
4715 {
4716 pShm->u8IsDoblyHDR10 = FALSE;
4717 }
4718 break;
4719 }
4720 #if (HVD_ENABLE_IQMEM)
4721 case E_HVD_SDATA_FW_IQMEM_CTRL:
4722 {
4723 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4724 break;
4725
4726 }
4727 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4728 {
4729 if (u32Data != 0)
4730 {
4731 pShm->bIQmemEnableIfSupport= TRUE;
4732 }
4733 else
4734 {
4735 pShm->bIQmemEnableIfSupport= FALSE;
4736 }
4737
4738
4739 break;
4740
4741 }
4742 #endif
4743 case E_HVD_SDATA_VP9HDR10INFO:
4744 {
4745 int i,j;
4746 HVD_Config_VP9HDR10* stVP9HDR10Info = (HVD_Config_VP9HDR10*) u32Data;
4747
4748 pShm->VP9HDR10Info.u32Version = stVP9HDR10Info->u32Version;
4749 pShm->VP9HDR10Info.u8MatrixCoefficients = stVP9HDR10Info->u8MatrixCoefficients;
4750 pShm->VP9HDR10Info.u8BitsPerChannel = stVP9HDR10Info->u8BitsPerChannel;
4751 pShm->VP9HDR10Info.u8ChromaSubsamplingHorz = stVP9HDR10Info->u8ChromaSubsamplingHorz;
4752 pShm->VP9HDR10Info.u8ChromaSubsamplingVert = stVP9HDR10Info->u8ChromaSubsamplingVert;
4753 pShm->VP9HDR10Info.u8CbSubsamplingHorz = stVP9HDR10Info->u8CbSubsamplingHorz;
4754 pShm->VP9HDR10Info.u8CbSubsamplingVert = stVP9HDR10Info->u8CbSubsamplingVert;
4755 pShm->VP9HDR10Info.u8ChromaSitingHorz = stVP9HDR10Info->u8ChromaSitingHorz;
4756 pShm->VP9HDR10Info.u8ChromaSitingVert = stVP9HDR10Info->u8ChromaSitingVert;
4757 pShm->VP9HDR10Info.u8ColorRange = stVP9HDR10Info->u8ColorRange;
4758 pShm->VP9HDR10Info.u8TransferCharacteristics = stVP9HDR10Info->u8TransferCharacteristics;
4759 pShm->VP9HDR10Info.u8ColourPrimaries = stVP9HDR10Info->u8ColourPrimaries;
4760 pShm->VP9HDR10Info.u16MaxCLL = stVP9HDR10Info->u16MaxCLL;
4761 pShm->VP9HDR10Info.u16MaxFALL = stVP9HDR10Info->u16MaxFALL;
4762 pShm->VP9HDR10Info.u32MaxLuminance = stVP9HDR10Info->u32MaxLuminance;
4763 pShm->VP9HDR10Info.u32MinLuminance = stVP9HDR10Info->u32MinLuminance;
4764
4765 for(i=0;i<2;i++)
4766 {
4767 pShm->VP9HDR10Info.u16WhitePoint[i] = stVP9HDR10Info->u16WhitePoint[i];
4768 }
4769
4770 for(i=0;i<3;i++)
4771 {
4772 for(j=0;j<2;j++)
4773 {
4774 pShm->VP9HDR10Info.u16Primaries[i][j] = stVP9HDR10Info->u16Primaries[i][j];
4775 }
4776 }
4777 pShm->u8VP9HDR10InfoVaild = TRUE;
4778 break;
4779 }
4780 default:
4781 break;
4782 }
4783
4784 HAL_HVD_EX_FlushMemory();
4785
4786 return eRet;
4787 }
4788
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4789 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4790 {
4791 MS_S64 s64Ret = 0;
4792 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4793
4794 HAL_HVD_EX_ReadMemory();
4795
4796 switch (eType)
4797 {
4798 case E_HVD_GDATA_PTS_STC_DIFF:
4799 s64Ret = pShm->s64PtsStcDiff;
4800 break;
4801 default:
4802 break;
4803 }
4804
4805 return s64Ret;
4806 }
4807
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4808 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4809 {
4810 MS_VIRT u32Ret = 0;
4811 //static MS_U64 u64pts_real = 0;
4812 MS_U64 u64pts_low = 0;
4813 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4814 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4815
4816 HAL_HVD_EX_ReadMemory();
4817
4818 if(pShm == NULL)
4819 {
4820 printf("########## VDEC patch for Debug ###########\n");
4821 return 0x0;
4822 }
4823
4824 switch (eType)
4825 {
4826 // share memory
4827 // switch
4828 case E_HVD_GDATA_DISP_INFO_ADDR:
4829 {
4830 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4831 break;
4832 }
4833 case E_HVD_GDATA_MIU_SEL:
4834 u32Ret = pShm->u32VDEC_MIU_SEL;
4835 break;
4836 case E_HVD_GDATA_FRAMEBUF_ADDR:
4837 u32Ret = pShm->u32FrameBufAddr;
4838 break;
4839 case E_HVD_GDATA_FRAMEBUF_SIZE:
4840 u32Ret = pShm->u32FrameBufSize;
4841 break;
4842 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4843 u32Ret = pShm->u32FrameBuf2Addr;
4844 break;
4845 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4846 u32Ret = pShm->u32FrameBuf2Size;
4847 break;
4848 case E_HVD_GDATA_CMA_ALLOC_DONE:
4849 u32Ret = pShm->bCMA_AllocDone;
4850 break;
4851 case E_HVD_GDATA_CMA_USED:
4852 u32Ret = pShm->bCMA_Use;
4853 break;
4854 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
4855 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
4856 break;
4857 // report
4858 case E_HVD_GDATA_PTS:
4859 {
4860 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
4861 break;
4862 }
4863 case E_HVD_GDATA_U64PTS:
4864 {
4865 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
4866 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
4867 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4868 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4869 break;
4870 }
4871 case E_HVD_GDATA_U64PTS_PRE_PARSE:
4872 {
4873 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
4874 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
4875 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4876 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4877 break;
4878 }
4879 case E_HVD_GDATA_DECODE_CNT:
4880 {
4881 u32Ret = pShm->u32DecodeCnt;
4882 break;
4883 }
4884 case E_HVD_GDATA_DATA_ERROR_CNT:
4885 {
4886 u32Ret = pShm->u32DataErrCnt;
4887 break;
4888 }
4889 case E_HVD_GDATA_DEC_ERROR_CNT:
4890 {
4891 u32Ret = pShm->u32DecErrCnt;
4892 break;
4893 }
4894 case E_HVD_GDATA_ERROR_CODE:
4895 {
4896 u32Ret = (MS_U32) (pShm->u16ErrCode);
4897 break;
4898 }
4899 case E_HVD_GDATA_VPU_IDLE_CNT:
4900 {
4901 u32Ret = pShm->u32VPUIdleCnt;
4902 break;
4903 }
4904 case E_HVD_GDATA_DISP_FRM_INFO:
4905 {
4906 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
4907 break;
4908 }
4909 case E_HVD_GDATA_DEC_FRM_INFO:
4910 {
4911 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
4912 break;
4913 }
4914 case E_HVD_GDATA_ES_LEVEL:
4915 {
4916 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
4917 break;
4918 }
4919 #if HVD_ENABLE_MVC
4920 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
4921 {
4922 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
4923 break;
4924 }
4925 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
4926 {
4927 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
4928 break;
4929 }
4930 #endif
4931
4932 // user data
4933 case E_HVD_GDATA_USERDATA_WPTR:
4934 {
4935 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
4936 break;
4937 }
4938 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
4939 {
4940 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
4941 break;
4942 }
4943 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
4944 {
4945 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
4946 break;
4947 }
4948 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
4949 {
4950 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
4951 break;
4952 }
4953 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
4954 {
4955 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
4956 break;
4957 }
4958 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
4959 {
4960 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
4961 break;
4962 }
4963 // report - modes
4964 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
4965 {
4966 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
4967 break;
4968 }
4969 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
4970 {
4971 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
4972 break;
4973 }
4974 case E_HVD_GDATA_IS_ERR_CONCEAL:
4975 {
4976 u32Ret = pShm->ModeStatus.bIsErrConceal;
4977 break;
4978 }
4979 case E_HVD_GDATA_IS_SYNC_ON:
4980 {
4981 u32Ret = pShm->ModeStatus.bIsSyncOn;
4982 break;
4983 }
4984 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
4985 {
4986 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
4987 break;
4988 }
4989 case E_HVD_GDATA_SYNC_MODE:
4990 {
4991 u32Ret = pShm->ModeStatus.u8SyncType;
4992 break;
4993 }
4994 case E_HVD_GDATA_SKIP_MODE:
4995 {
4996 u32Ret = pShm->ModeStatus.u8SkipMode;
4997 break;
4998 }
4999 case E_HVD_GDATA_DROP_MODE:
5000 {
5001 u32Ret = pShm->ModeStatus.u8DropMode;
5002 break;
5003 }
5004 case E_HVD_GDATA_DISPLAY_DURATION:
5005 {
5006 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
5007 break;
5008 }
5009 case E_HVD_GDATA_FRC_MODE:
5010 {
5011 u32Ret = pShm->ModeStatus.u8FrcMode;
5012 break;
5013 }
5014 case E_HVD_GDATA_NEXT_PTS:
5015 {
5016 u32Ret = pShm->u32NextPTS;
5017 break;
5018 }
5019 case E_HVD_GDATA_DISP_Q_SIZE:
5020 {
5021 u32Ret = pShm->u16DispQSize;
5022 break;
5023 }
5024 case E_HVD_GDATA_DISP_Q_PTR:
5025 {
5026 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
5027 break;
5028 }
5029 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
5030 {
5031 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
5032 break;
5033 }
5034 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
5035 {
5036 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
5037 break;
5038 }
5039 case E_HVD_GDATA_REAL_FRAMERATE:
5040 {
5041 // return VPS/VUI timing info framerate, and 0 if timing info not exist
5042 u32Ret = pShm->u32RealFrameRate;
5043 break;
5044 }
5045 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
5046 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
5047 break;
5048 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
5049 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
5050 break;
5051 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
5052 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
5053 break;
5054 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
5055 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
5056 break;
5057 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
5058 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
5059 break;
5060 case E_HVD_GDATA_FW_STATUS_FLAG:
5061 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
5062 break;
5063
5064 // internal control
5065 case E_HVD_GDATA_IS_1ST_FRM_RDY:
5066 {
5067 u32Ret = pShm->bIs1stFrameRdy;
5068 break;
5069 }
5070 case E_HVD_GDATA_IS_I_FRM_FOUND:
5071 {
5072 u32Ret = pShm->bIsIFrmFound;
5073 break;
5074 }
5075 case E_HVD_GDATA_IS_SYNC_START:
5076 {
5077 u32Ret = pShm->bIsSyncStart;
5078 break;
5079 }
5080 case E_HVD_GDATA_IS_SYNC_REACH:
5081 {
5082 u32Ret = pShm->bIsSyncReach;
5083 break;
5084 }
5085 case E_HVD_GDATA_FW_VERSION_ID:
5086 {
5087 u32Ret = pShm->u32FWVersionID;
5088 break;
5089 }
5090 case E_HVD_GDATA_FW_IF_VERSION_ID:
5091 {
5092 u32Ret = pShm->u32FWIfVersionID;
5093 break;
5094 }
5095 case E_HVD_GDATA_BBU_Q_NUMB:
5096 {
5097 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
5098 break;
5099 }
5100 case E_HVD_GDATA_DEC_Q_NUMB:
5101 {
5102 u32Ret = pShm->u16DecQNumb;
5103 break;
5104 }
5105 case E_HVD_GDATA_DISP_Q_NUMB:
5106 {
5107 u32Ret = pShm->u16DispQNumb;
5108 break;
5109 }
5110 case E_HVD_GDATA_PTS_Q_NUMB:
5111 {
5112 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
5113 break;
5114 }
5115 case E_HVD_GDATA_FW_INIT_DONE:
5116 {
5117 u32Ret = pShm->bInitDone;
5118 break;
5119 }
5120 // debug
5121 case E_HVD_GDATA_SKIP_CNT:
5122 {
5123 u32Ret = pShm->u32SkipCnt;
5124 break;
5125 }
5126 case E_HVD_GDATA_GOP_CNT:
5127 {
5128 u32Ret = pShm->u32DropCnt;
5129 break;
5130 }
5131 case E_HVD_GDATA_DISP_CNT:
5132 {
5133 u32Ret = pShm->u32DispCnt;
5134 break;
5135 }
5136 case E_HVD_GDATA_DROP_CNT:
5137 {
5138 u32Ret = pShm->u32DropCnt;
5139 break;
5140 }
5141 case E_HVD_GDATA_DISP_STC:
5142 {
5143 u32Ret = pShm->u32DispSTC;
5144 break;
5145 }
5146 case E_HVD_GDATA_VSYNC_CNT:
5147 {
5148 u32Ret = pShm->u32VsyncCnt;
5149 break;
5150 }
5151 case E_HVD_GDATA_MAIN_LOOP_CNT:
5152 {
5153 u32Ret = pShm->u32MainLoopCnt;
5154 break;
5155 }
5156
5157 // AVC
5158 case E_HVD_GDATA_AVC_LEVEL_IDC:
5159 {
5160 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5161 break;
5162 }
5163 case E_HVD_GDATA_AVC_LOW_DELAY:
5164 {
5165 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5166 break;
5167 }
5168 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5169 {
5170 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5171 break;
5172 }
5173 case E_HVD_GDATA_FW_FLUSH_STATUS:
5174 {
5175 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5176 break;
5177 }
5178 case E_HVD_GDATA_FW_CODEC_TYPE:
5179 {
5180 u32Ret = pShm->u32CodecType;
5181 break;
5182 }
5183 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5184 {
5185 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5186 break;
5187 }
5188 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5189 {
5190 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5191 {
5192 u32Ret = 1;
5193 }
5194 else
5195 {
5196 u32Ret = 0;
5197 }
5198 break;
5199 }
5200
5201 // SRAM
5202
5203 // Mailbox
5204 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5205 {
5206 u32Ret = pShm->u32FwState;
5207 break;
5208 }
5209 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5210 {
5211 u32Ret = pShm->bSpsChange;
5212 break;
5213 }
5214 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5215 {
5216 u32Ret = pShm->bSpsChange;
5217
5218 if (pShm->bSpsChange &&
5219 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5220 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5221 {
5222 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5223 }
5224
5225 break;
5226 }
5227 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5228 {
5229 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5230
5231 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5232 {
5233 u32Ret = pShm->u32FwInfo;
5234 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5235 }
5236 break;
5237 }
5238 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5239 {
5240 if (pShm->bIsTrigDisp) // not clear yet
5241 {
5242 u32Ret = FALSE;
5243 }
5244 else
5245 {
5246 u32Ret = TRUE;
5247 }
5248 break;
5249 }
5250 case E_HVD_GDATA_ES_READ_PTR:
5251 {
5252 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5253 break;
5254 }
5255 case E_HVD_GDATA_ES_WRITE_PTR:
5256 {
5257 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5258 break;
5259 }
5260 case E_HVD_GDATA_BBU_READ_PTR:
5261 {
5262 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5263 break;
5264 }
5265 case E_HVD_GDATA_BBU_WRITE_PTR:
5266 {
5267 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5268 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5269 {
5270 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5271 }
5272 else
5273 {
5274 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5275 }
5276 break;
5277 }
5278 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5279 {
5280 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5281
5282 u32Ret = pCtrl->u32BBUWptr_Fired;
5283
5284 break;
5285 }
5286 case E_HVD_GDATA_VPU_PC_CNT:
5287 {
5288 u32Ret = _HVD_EX_GetPC();
5289 break;
5290 }
5291 case E_HVD_GDATA_ES_QUANTITY:
5292 {
5293 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5294 break;
5295 }
5296
5297
5298 // FW def
5299 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5300 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5301 break;
5302
5303 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5304 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5305 break;
5306 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5307 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5308 break;
5309 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5310 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5311 break;
5312 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5313 u32Ret = MAX_PTS_TABLE_SIZE;
5314 break;
5315 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5316 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5317 break;
5318 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5319 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5320 break;
5321 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5322 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5323 break;
5324 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5325 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5326 break;
5327 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5328 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5329 break;
5330 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5331 {
5332 if (pShm->bDSIsRunning)
5333 {
5334 u32Ret = TRUE;
5335 }
5336 else
5337 {
5338 u32Ret = FALSE;
5339 }
5340 break;
5341 }
5342 #if (HVD_ENABLE_IQMEM)
5343 case E_HVD_GDATA_FW_IQMEM_CTRL:
5344 {
5345
5346 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5347
5348 break;
5349 }
5350 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5351 {
5352 if(pShm->bIsIQMEMSupport){
5353 u32Ret = TRUE;
5354 }
5355 else{
5356
5357 u32Ret = FALSE;
5358 }
5359
5360 break;
5361 }
5362 #endif
5363 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5364 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5365 break;
5366 case E_HVD_GDATA_FIELD_PIC_FLAG:
5367 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5368 break;
5369 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5370 u32Ret = pShm->u32SeamlessTSStatus;
5371 break;
5372 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5373 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5374 break;
5375 #ifdef VDEC3
5376 case E_HVD_GDATA_FW_VBBU_ADDR:
5377 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5378 break;
5379 #endif
5380 case E_HVD_GDATA_SEQ_CHANGE_INFO:
5381 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
5382 break;
5383 case E_HVD_GDATA_GET_NOT_SUPPORT_INFO:
5384 u32Ret = pShm->u32NotSupportInfo;
5385 break;
5386 default:
5387 break;
5388 }
5389 return u32Ret;
5390 }
5391
HAL_HVD_EX_GetDVSupportProfiles(void)5392 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
5393 {
5394 #if 0 // wait avc finish DV dual job
5395 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5396 #else
5397 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5398 #endif
5399 }
5400
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)5401 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
5402 {
5403 switch (u32DV_Stream_Profile)
5404 {
5405 #if 0 // wait avc finish DV dual job
5406 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
5407 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
5408 #endif
5409
5410 #if 0 // unsupported profile
5411 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
5412 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5413 #endif
5414
5415 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
5416 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5417
5418 #if 0 // unsupported profile
5419 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
5420 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5421 #endif
5422
5423 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
5424 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5425
5426 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
5427 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5428
5429 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
5430 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5431
5432 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
5433 default:
5434 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5435 }
5436 }
5437
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5438 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5439 {
5440 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5441 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5442 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5443
5444 _HAL_HVD_Entry();
5445
5446 // check if old SVD cmds
5447 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5448 {
5449 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5450
5451 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5452 }
5453
5454 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5455 {
5456 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5457 }
5458
5459 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5460 {
5461 if (u32Cmd == E_HVD_CMD_FLUSH)
5462 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5463 }
5464
5465 if (u32Cmd == E_HVD_CMD_FLUSH &&
5466 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5467 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5468 {
5469 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5470 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5471 {
5472 _HAL_HVD_Release();
5473 HVD_Delay_ms(1);
5474 _HAL_HVD_Entry();
5475 }
5476 }
5477
5478 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5479
5480 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5481
5482 _HAL_HVD_Return(eRet);
5483 }
5484
HAL_HVD_EX_DeInit(MS_U32 u32Id)5485 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5486 {
5487 HVD_Return eRet = E_HVD_RETURN_FAIL;
5488 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5489 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5490 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5491 MS_U8 u8MiuSel;
5492 MS_U32 u32StartOffset;
5493
5494
5495 #if HVD_ENABLE_TIME_MEASURE
5496 MS_U32 ExitTimeCnt = 0;
5497 ExitTimeCnt = HVD_GetSysTime_ms();
5498 #endif
5499
5500 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5501
5502 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5503
5504 if (E_HVD_RETURN_SUCCESS != eRet)
5505 {
5506 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5507 }
5508
5509 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5510
5511 if (E_HVD_RETURN_SUCCESS != eRet)
5512 {
5513 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5514 }
5515
5516 // check FW state to make sure it's STOP DONE
5517 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5518 {
5519 if (HVD_GetSysTime_ms() > u32Timeout)
5520 {
5521 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5522
5523 //return E_HVD_RETURN_TIMEOUT;
5524 eRet = E_HVD_RETURN_TIMEOUT;
5525 break;
5526 }
5527 }
5528
5529 VPU_EX_FWCodeCfg fwCfg;
5530 VPU_EX_TaskInfo taskInfo;
5531 VPU_EX_NDecInitPara nDecInitPara;
5532
5533 nDecInitPara.pFWCodeCfg = &fwCfg;
5534 nDecInitPara.pTaskInfo = &taskInfo;
5535
5536 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5537 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5538
5539 taskInfo.u32Id = u32Id;
5540 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5541 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5542
5543 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5544 {
5545 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5546 }
5547 else
5548 {
5549 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5550 }
5551
5552 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5553 {
5554 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5555 }
5556
5557 /* clear es buffer */
5558 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5559 {
5560 //printf("Clear ES buffer\n");
5561
5562 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5563 }
5564
5565 //_HAL_HVD_MutexDelete();
5566
5567 #if HVD_ENABLE_TIME_MEASURE
5568 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5569 #endif
5570
5571 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5572 #ifndef VDEC3
5573 // reset bbu wptr
5574 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5575 {
5576 if(TRUE == HAL_VPU_EX_HVDInUsed())
5577 {
5578 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5579 {
5580 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5581 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5582 }
5583 else
5584 {
5585 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5586 {
5587 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5588 }
5589 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5590 }
5591 }
5592 else
5593 {
5594 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5595 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5596 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5597 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5598 {
5599 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5600 {
5601 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5602 }
5603 }
5604 else
5605 {
5606 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5607 }
5608 }
5609 }
5610 #endif
5611 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5612
5613 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5614 {
5615 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5616 }
5617
5618 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5619 {
5620
5621 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5622
5623 _HAL_HVD_Entry();
5624 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5625 _HAL_HVD_Release();
5626
5627 }
5628 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
5629 HVD_EX_MSG_DBG("success\n");
5630
5631 return eRet;
5632 }
5633
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5634 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5635 {
5636 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5637 MS_U32 u32Addr = 0;
5638 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5639 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5640
5641 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5642
5643 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5644 {
5645 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5646
5647 if (E_HVD_RETURN_SUCCESS != eRet)
5648 {
5649 return eRet;
5650 }
5651 }
5652
5653 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5654
5655 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5656 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5657 {
5658 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5659
5660 if (E_HVD_RETURN_SUCCESS != eRet)
5661 {
5662 return eRet;
5663 }
5664 }
5665
5666 u32Addr = pInfo->u32Staddr;
5667
5668 if (pInfo->bRVBrokenPacket)
5669 {
5670 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5671 }
5672
5673 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5674 {
5675 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5676 }
5677 else
5678 {
5679 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5680 }
5681
5682 if (E_HVD_RETURN_SUCCESS != eRet)
5683 {
5684 return eRet;
5685 }
5686
5687 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5688 {
5689 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5690 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5691
5692 if (E_HVD_RETURN_SUCCESS != eRet)
5693 {
5694 return eRet;
5695 }
5696 }
5697
5698 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5699
5700 // do not add local pointer
5701 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5702 {
5703 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5704
5705 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5706 (u32PacketStAddr <
5707 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5708 {
5709 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5710 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5711 }
5712 else
5713 {
5714 //null packet
5715 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5716 pCtrl->LastNal.u32NalSize = 0;
5717 }
5718 }
5719 else
5720 {
5721 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5722 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5723 }
5724
5725 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5726 pCtrl->u32BBUPacketCnt++;
5727
5728 return eRet;
5729 }
5730
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5731 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5732 {
5733 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5734 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5735 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5736 if(bCurrentStatus == bEnable)
5737 return;
5738
5739 if (bEnable)
5740 {
5741 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5742 }
5743 else
5744 {
5745 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5746 }
5747 }
5748
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5749 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5750 {
5751 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5752 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5753
5754 if (bEnable)
5755 {
5756 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5757 }
5758 else
5759 {
5760 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5761 }
5762 }
5763
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5764 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5765 {
5766 MS_U32 u32RB = 0;
5767 switch(eISRType)
5768 {
5769 case E_HWDEC_ISR_HVD:
5770 u32RB = REG_HVD_BASE;
5771 break;
5772 #if SUPPORT_EVD
5773 case E_HWDEC_ISR_EVD:
5774 u32RB = REG_EVD_BASE;
5775 break;
5776 #endif
5777 #if SUPPORT_G2VP9
5778 case E_HWDEC_ISR_G2VP9:
5779 break;
5780 #endif
5781 default:
5782 break;
5783 }
5784 if(u32RB)
5785 {
5786 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5787 }
5788 }
5789
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5790 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5791 {
5792 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5793 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5794
5795 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5796 }
5797
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5798 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5799 {
5800 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5801 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5802
5803 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5804 {
5805 return FALSE;
5806 }
5807 else
5808 {
5809 return TRUE;
5810 }
5811 }
5812
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5813 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5814 {
5815 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5816
5817 if (pCtrl)
5818 {
5819 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5820 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5821 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5822 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5823 {
5824 return FALSE;
5825 }
5826 else
5827 {
5828 return TRUE;
5829 }
5830 }
5831 else
5832 {
5833 return FALSE;
5834 }
5835 }
5836
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5837 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5838 {
5839 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5840 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5841 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5842
5843 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5844 {
5845 HAL_HVD_EX_ReadMemory();
5846
5847 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5848 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5849
5850 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
5851 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
5852 }
5853
5854 return TRUE;
5855 }
5856
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)5857 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
5858 {
5859 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5860 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5861 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5862 MS_U32 u32Data;
5863 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5864
5865 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
5866
5867 HAL_HVD_EX_FlushMemory();
5868 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5869 {
5870 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5871 pCtrl->LastNal.u32NalAddr = u32Data;
5872 pCtrl->LastNal.u32NalSize = 0;
5873 }
5874
5875 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5876 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
5877
5878 return TRUE;
5879 }
5880
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)5881 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
5882 {
5883 if (bEnable)
5884 {
5885 if (HAL_VPU_EX_IsEVDR2())
5886 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5887 else
5888 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
5889 }
5890 else
5891 {
5892 #if defined (__aeon__)
5893 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5894 #else // defined (__mips__)
5895 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
5896 #endif
5897 }
5898 }
5899
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)5900 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
5901 {
5902 return 0;
5903 }
5904
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)5905 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
5906 {
5907 return;
5908 }
5909
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)5910 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
5911 {
5912 //if( u16Clock == 0 )
5913 return 216; //140;
5914 //if( )
5915 }
5916
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)5917 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
5918 {
5919 //MS_BOOL bBitMIU1 = FALSE;
5920 //MS_BOOL bCodeMIU1 = FALSE;
5921 MS_U8 u8BitMiuSel = 0;
5922 MS_U8 u8CodeMiuSel = 0;
5923 MS_U32 u32BitStartOffset;
5924 MS_U32 u32CodeStartOffset;
5925 //MS_U8 u8MiuSel;
5926 //MS_U32 u32StartOffset;
5927 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5928 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5929 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5930 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
5931
5932 #if HVD_ENABLE_MVC
5933 if(HAL_HVD_EX_CheckMVCID(u32Id))
5934 {
5935 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
5936 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
5937 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
5938 {
5939 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
5940 }
5941 }
5942 #endif /// HVD_ENABLE_MVC
5943
5944 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
5945 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5946
5947
5948
5949
5950 if (u8BitMiuSel != u8CodeMiuSel)
5951 {
5952 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
5953 BDMA_Result bdmaRlt;
5954 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5955
5956 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5957 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
5958 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5959
5960 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
5961
5962 if (E_BDMA_OK != bdmaRlt)
5963 {
5964 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
5965 }
5966 #else
5967 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5968
5969 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5970 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
5971 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5972
5973 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
5974 #endif
5975 }
5976
5977 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
5978
5979 HAL_HVD_EX_FlushMemory();
5980
5981 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5982 {
5983 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
5984 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
5985 }
5986 else
5987 {
5988 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
5989
5990 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5991 }
5992 }
5993
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)5994 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
5995 {
5996 if (bEnable)
5997 {
5998 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5999 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
6000 }
6001 else
6002 {
6003 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
6004 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
6005 }
6006 }
6007
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)6008 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
6009 {
6010 MS_U32 tmp1 = 0;
6011 MS_U32 tmp2 = 0;
6012 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6013
6014 HAL_HVD_EX_ReadMemory();
6015
6016 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
6017 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
6018
6019 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6020 {
6021 MS_U32 u32Tmp = u32UartCtrl;
6022
6023 HVD_EX_MSG_DBG("\n");
6024 u32UartCtrl = 0; // turn off debug message to prevent other function prints
6025 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
6026 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
6027
6028 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
6029 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
6030 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
6031 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
6032
6033 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
6034 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
6035 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
6036
6037 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
6038 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
6039 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
6040 _HVD_EX_GetESLevel(u32Id));
6041
6042 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
6043 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
6044 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
6045 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
6046 printf
6047 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
6048 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
6049 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
6050 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
6051 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
6052 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
6053 pShm->ModeStatus.bShowOneField);
6054
6055 u32UartCtrl = u32Tmp; // recover debug level
6056 }
6057 }
6058
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)6059 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
6060 {
6061 MS_U8 *u32Addr = NULL;
6062 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6063 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6064
6065 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6066 {
6067 return;
6068 }
6069
6070 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
6071
6072 *u32NalSize = *(u32Addr + 2) & 0x1f;
6073 *u32NalSize <<= 8;
6074 *u32NalSize |= *(u32Addr + 1) & 0xff;
6075 *u32NalSize <<= 8;
6076 *u32NalSize |= *(u32Addr) & 0xff;
6077
6078 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
6079 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
6080 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
6081 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
6082 }
6083
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)6084 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
6085 {
6086 MS_U32 u32CurIdx = 0;
6087 MS_BOOL bFinished = FALSE;
6088 MS_U32 u32NalOffset = 0;
6089 MS_U32 u32NalSize = 0;
6090 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6091
6092 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
6093 {
6094 return;
6095 }
6096
6097 u32CurIdx = u32StartIdx;
6098
6099 do
6100 {
6101 if (u32CurIdx == u32EndIdx)
6102 {
6103 bFinished = TRUE;
6104 }
6105
6106 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
6107
6108 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
6109 {
6110 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
6111 }
6112
6113 u32CurIdx++;
6114
6115 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6116 {
6117 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6118 }
6119 } while (bFinished == TRUE);
6120 }
6121
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)6122 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
6123 {
6124 MS_U32 i = 0;
6125 MS_U32 value = 0;
6126
6127 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6128 {
6129 HVD_EX_MSG_DBG("\n");
6130
6131 for (i = 0; i <= u32Num; i++)
6132 {
6133 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
6134 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
6135 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
6136
6137 if (value == 0)
6138 {
6139 break;
6140 }
6141
6142 printf(" %08x", value);
6143
6144 if (((i % 8) + 1) == 8)
6145 {
6146 printf(" |%u\n", i + 1);
6147 }
6148 }
6149
6150 printf("\nHVD Dump HW status End: total number:%u\n", i);
6151 }
6152 }
6153
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)6154 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
6155 {
6156 if (pDrvCtrl)
6157 {
6158 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
6159 }
6160 }
6161
6162 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)6163 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
6164 {
6165 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
6166 }
6167
HAL_HVD_EX_GetView(MS_U32 u32Id)6168 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
6169 {
6170 if( (0xFF & (u32Id >> 8)) == 0x10)
6171 return E_VDEC_EX_MAIN_VIEW;
6172 else
6173 return E_VDEC_EX_SUB_VIEW;
6174 }
6175 #endif ///HVD_ENABLE_MVC
6176
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)6177 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
6178 {
6179 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
6180 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
6181 return;
6182 }
6183
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)6184 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
6185 {
6186 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
6187 return;
6188 }
6189
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)6190 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
6191 {
6192 MS_U64 _hw_max_pixel = 0;
6193 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6194
6195 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6196 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6197 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6198 }
6199
6200
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6201 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6202 {
6203 #if 1
6204 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6205 MS_U16 u16QNum = pShm->u16DispQNumb;
6206 MS_U16 u16QPtr = pShm->u16DispQPtr;
6207 // MS_U16 u16QSize = pShm->u16DispQSize;
6208 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6209 MS_U32 u32DispQNum = 0;
6210 #if HVD_ENABLE_MVC
6211 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6212
6213 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6214 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
6215
6216 if(bMVC || bDolbyVision)
6217 {
6218 #if 0
6219 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6220 {
6221 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6222 }
6223 #endif
6224
6225 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6226 //search the next frame to display
6227 while (u16QNum > 0)
6228 {
6229 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6230 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6231 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6232
6233 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6234 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6235 {
6236 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6237 /// Check the depned view was initial when Output the base view.
6238 if((u16QPtr%2) == 0)
6239 {
6240 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6241 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6242 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6243 {
6244 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6245 ///printf("Return NULL.\n");
6246 continue;
6247 }
6248 }
6249 u32DispQNum++;
6250 }
6251
6252 u16QNum--;
6253 //go to next frame in the dispQ
6254 u16QPtr++;
6255
6256 if (u16QPtr >= pShm->u16DispQSize)
6257 {
6258 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6259 }
6260 }
6261 }
6262 else
6263 #endif ///HVD_ENABLE_MVC
6264 {
6265 #if 0
6266 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6267 {
6268 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6269 }
6270 #endif
6271 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6272 //search the next frame to display
6273 while (u16QNum != 0)
6274 {
6275 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6276
6277 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6278 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6279 {
6280 u32DispQNum++;
6281 }
6282
6283 u16QNum--;
6284 //go to next frame in the dispQ
6285 u16QPtr++;
6286
6287 if (u16QPtr == pShm->u16DispQSize)
6288 {
6289 u16QPtr = 0; //wrap to the begin
6290 }
6291 }
6292 }
6293
6294 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6295 return u32DispQNum;
6296 #else
6297 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6298 return pShm->u16DispQNumb;
6299 #endif
6300 }
6301
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6302 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6303 {
6304 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6305 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
6306 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
6307 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6308 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6309 #if SUPPORT_G2VP9 && defined(VDEC3)
6310 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6311 #else // Not using G2 VP9 implies using Mstar EVD VP9
6312 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6313 #endif
6314 else
6315 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6316 }
6317
6318 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)6319 void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)
6320 {
6321 if (bEnable)
6322 {
6323 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6324 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6325 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6326 }
6327 else
6328 {
6329 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6330 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6331 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6332 }
6333
6334 switch (pHVDHalContext->u32EVDClockType)
6335 {
6336 case 576:
6337 {
6338 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6339 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6340 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_576MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
6341 break;
6342 }
6343 case 480:
6344 {
6345 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6346 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6347 break;
6348 }
6349 case 384:
6350 {
6351 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6352 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6353 break;
6354 }
6355 case 320:
6356 {
6357 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6358 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6359 break;
6360 }
6361 case 240:
6362 {
6363 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6364 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6365 break;
6366 }
6367 case 192:
6368 {
6369 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6370 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6371 break;
6372 }
6373 default:
6374 {
6375 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6376 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_MASK);
6377 break;
6378 }
6379 }
6380
6381 return;
6382 }
6383
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6384 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6385 {
6386 #ifndef VDEC3
6387 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6388 #endif
6389 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6390
6391 #ifdef VDEC3
6392 if (0 == pCtrl->u32BBUId)
6393 #else
6394 if (0 == u8TaskId)
6395 #endif
6396 {
6397 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6398 }
6399 else
6400 {
6401 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6402 }
6403
6404 return;
6405 }
6406
HAL_EVD_EX_DeinitHW(void)6407 static MS_BOOL HAL_EVD_EX_DeinitHW(void)
6408 {
6409 MS_U16 u16Timeout = 1000;
6410
6411 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6412
6413 while (u16Timeout)
6414 {
6415 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6416 {
6417 break;
6418 }
6419 u16Timeout--;
6420 }
6421
6422 HAL_EVD_EX_PowerCtrl(FALSE);
6423
6424 return TRUE;
6425 }
6426 #endif
6427
6428 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6429 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6430 {
6431 if (bEnable)
6432 {
6433 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6434 }
6435 else
6436 {
6437 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6438 }
6439
6440 switch (pHVDHalContext->u32VP9ClockType)
6441 {
6442 case 432:
6443 {
6444 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6445 break;
6446 }
6447 case 384:
6448 {
6449 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6450 break;
6451 }
6452 case 345:
6453 {
6454 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6455 break;
6456 }
6457 case 320:
6458 {
6459 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6460 break;
6461 }
6462 case 288:
6463 {
6464 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6465 break;
6466 }
6467 case 240:
6468 {
6469 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6470 break;
6471 }
6472 case 216:
6473 {
6474 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6475 break;
6476 }
6477 case 172:
6478 {
6479 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6480 break;
6481 }
6482 default:
6483 {
6484 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6485 break;
6486 }
6487 }
6488
6489 return;
6490 }
6491
HAL_VP9_EX_DeinitHW(void)6492 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6493 {
6494 MS_U16 u16Timeout = 1000;
6495
6496 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6497
6498 while (u16Timeout)
6499 {
6500 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6501 {
6502 break;
6503 }
6504 u16Timeout--;
6505 }
6506
6507 HAL_VP9_EX_PowerCtrl(FALSE);
6508
6509 return TRUE;
6510 }
6511 #endif
6512
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6513 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6514 {
6515 return TRUE;
6516 }
HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)6517 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
6518 {
6519 _HVD_EX_SetBufferAddr(u32Id);
6520 }
6521
6522
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6523 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6524 {
6525 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6526
6527 if(pCtrl->InitParams.u16ChipECONum == 0)
6528 return FALSE;
6529 else
6530 return TRUE;
6531
6532 }
6533
6534
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6535 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6536 {
6537
6538 }
6539
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6540 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6541 {
6542
6543 }
6544 #endif
6545