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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE) 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 121 #define VPU_FORCE_MIU_MODE 1 122 #define VPU_ENABLE_IQMEM 1 123 #define VPU_IQMEM_BASE 0xe0000000 124 125 126 #define ENABLE_DECOMPRESS_FUNCTION TRUE 127 128 #define VPU_CLOCK_240MHZ BITS(6:2,0) 129 #define VPU_CLOCK_216MHZ BITS(6:2,1) 130 #define VPU_CLOCK_192MHZ BITS(6:2,2) 131 #define VPU_CLOCK_172MHZ BITS(6:2,3) 132 133 #define VPU_ICG_EN BIT(8) 134 //#define VPU_LITE_ICG_EN BIT(9) 135 136 #define VPU_HI_MBOX0 0 137 #define VPU_HI_MBOX1 1 138 #define VPU_RISC_MBOX0 2 139 #define VPU_RISC_MBOX1 3 140 141 142 #define VPU_EX_TimerDelayMS(x) \ 143 do \ 144 { \ 145 volatile MS_U32 ticks = 0; \ 146 while (ticks < (((MS_U32) (x)) << 13)) \ 147 { \ 148 ticks++; \ 149 } \ 150 } while(0) 151 152 #ifdef VDEC3 153 #define VPU_BBU_NAL_TBL BIT(0) 154 #define VPU_BBU_ES_BUFFER BIT(1) 155 #define HAL_VPU_INVALID_BBU_ID 0xFFFFFFFF 156 #define VPU_MAX_DEC_NUM 16 157 #else 158 #define VPU_MAX_DEC_NUM 2 159 #endif 160 #define CHECK_NULL_PTR(vbbu_addr) (((void *)(vbbu_addr)) == NULL) 161 162 //------------------------------------------------------------------------------------------------- 163 // Type and Structure 164 //------------------------------------------------------------------------------------------------- 165 typedef enum 166 { 167 E_HAL_HVD_STREAM_NONE = 0x0, 168 169 //Support TSP/TS/File mode 170 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 171 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 172 E_HAL_HVD_MAIN_STREAM_MAX, 173 174 //Only support file mode 175 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 176 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 177 E_HAL_HVD_SUB_STREAM1, 178 E_HAL_HVD_SUB_STREAM_MAX, 179 180 #ifdef VDEC3 181 E_HAL_HVD_N_STREAM_BASE = 0x40, 182 E_HAL_HVD_N_STREAM0 = E_HAL_HVD_N_STREAM_BASE, 183 E_HAL_HVD_N_STREAM_MAX = E_HAL_HVD_N_STREAM0 + VPU_MAX_DEC_NUM, 184 #endif 185 186 //Only support MVC stream 187 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 188 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 189 E_HAL_HVD_MVC_Sub_View, 190 E_HAL_HVD_MVC_STREAM_MAX, 191 } HAL_HVD_StreamId; 192 193 typedef enum 194 { 195 E_VPU_EX_DECODER_NONE = 0, 196 E_VPU_EX_DECODER_GET, 197 E_VPU_EX_DECODER_GET_MVC, 198 E_VPU_EX_DECODER_MVD, 199 E_VPU_EX_DECODER_HVD, 200 E_VPU_EX_DECODER_MJPEG, 201 E_VPU_EX_DECODER_RVD, 202 E_VPU_EX_DECODER_MVC, 203 E_VPU_EX_DECODER_VP8, 204 #ifdef VDEC3 205 E_VPU_EX_DECODER_EVD, 206 #if SUPPORT_G2VP9 207 E_VPU_EX_DECODER_G2VP9, 208 #endif 209 #endif 210 } VPU_EX_DecoderType; 211 212 #ifdef CONFIG_MSTAR_CLKM 213 typedef enum 214 { 215 E_VPU_EX_CLKPORT_MVD = 0, 216 E_VPU_EX_CLKPORT_MVD_CORE, 217 E_VPU_EX_CLKPORT_MVD_PAS, 218 E_VPU_EX_CLKPORT_HVD, 219 E_VPU_EX_CLKPORT_HVD_IDB, 220 E_VPU_EX_CLKPORT_HVD_AEC, 221 E_VPU_EX_CLKPORT_HVD_AEC_LITE, 222 E_VPU_EX_CLKPORT_VP8, 223 E_VPU_EX_CLKPORT_EVD, 224 E_VPU_EX_CLKPORT_EVD_PPU, 225 E_VPU_EX_CLKPORT_EVD_LITE, 226 E_VPU_EX_CLKPORT_EVD_PPU_LITE, 227 E_VPU_EX_CLKPORT_VD_MHEG5, 228 E_VPU_EX_CLKPORT_VD_MHEG5_LITE, 229 } VPU_EX_ClkPortType; 230 #endif 231 232 typedef enum 233 { 234 E_VPU_EX_CLOCK_240MHZ = VPU_CLOCK_240MHZ, 235 E_VPU_EX_CLOCK_216MHZ = VPU_CLOCK_216MHZ, 236 E_VPU_EX_CLOCK_192MHZ = VPU_CLOCK_192MHZ, 237 E_VPU_EX_CLOCK_172MHZ = VPU_CLOCK_172MHZ, 238 } VPU_EX_ClockSpeed; 239 240 typedef enum 241 { 242 E_HAL_VPU_STREAM_NONE = 0x0, 243 244 //Support TSP/TS File/File mode 245 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 246 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 247 E_HAL_VPU_MAIN_STREAM_MAX, 248 249 //Only support file mode 250 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 251 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 252 E_HAL_VPU_SUB_STREAM_MAX, 253 254 #ifdef VDEC3 255 E_HAL_VPU_N_STREAM_BASE = 0x40, 256 E_HAL_VPU_N_STREAM0 = E_HAL_VPU_N_STREAM_BASE, 257 E_HAL_VPU_N_STREAM_MAX = E_HAL_VPU_N_STREAM0 + VPU_MAX_DEC_NUM, 258 #endif 259 260 //Only support MVC stream 261 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 262 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 263 E_HAL_VPU_MVC_SUB_VIEW, 264 E_HAL_VPU_MVC_STREAM_MAX, 265 } HAL_VPU_StreamId; 266 267 typedef enum 268 { 269 //Support TSP/TS/File mode 270 E_HAL_VPU_MAIN_STREAM, 271 272 //Only support file mode 273 E_HAL_VPU_SUB_STREAM, 274 275 //Only support MVC mode 276 E_HAL_VPU_MVC_STREAM, 277 278 #ifdef VDEC3 279 E_HAL_VPU_N_STREAM, 280 #endif 281 } HAL_VPU_StreamType; 282 283 typedef enum 284 { 285 //Support TSP/TS/File mode 286 E_VPU_EX_INPUT_TSP, 287 //Only support file mode 288 E_VPU_EX_INPUT_FILE, 289 E_VPU_EX_INPUT_NONE, 290 } VPU_EX_SourceType; 291 292 typedef enum 293 { 294 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 295 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 296 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 297 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 298 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 299 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 300 } VPU_EX_UartLevel; 301 302 typedef enum 303 { 304 E_VPU_EX_FW_VER_CTRLR = 0, 305 E_VPU_EX_FW_VER_MVD_FW, 306 E_VPU_EX_FW_VER_HVD_FW, 307 E_VPU_EX_FW_VER_MVD_IF, 308 E_VPU_EX_FW_VER_HVD_IF, 309 } VPU_EX_FWVerType; 310 311 /// DecodeMode for f/w tasks 312 typedef enum 313 { 314 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 315 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 316 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 317 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 318 } VPU_EX_DecMode; 319 320 /// CmdMode for KOREA3D or PIP mode 321 typedef enum 322 { 323 //Group1:Set Korea3DTV mode 324 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 325 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 326 E_VPU_CMD_MODE_KR3D_FORCE_P, 327 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 328 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 329 330 //Group2:Set PIP mode 331 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 332 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 333 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 334 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 335 } VPU_EX_CmdMode; 336 337 /// input source select enumerator 338 typedef enum 339 { 340 ///DTV mode 341 E_VPU_EX_SRC_MODE_DTV = 0, 342 ///TS file mode 343 E_VPU_EX_SRC_MODE_TS_FILE, 344 ///generic file mode 345 E_VPU_EX_SRC_MODE_FILE, 346 /// TS file and dual ES buffer mode 347 E_VPU_EX_SRC_MODE_TS_FILE_DUAL_ES, 348 ///generic file and dual ES buffer mode 349 E_VPU_EX_SRC_MODE_FILE_DUAL_ES, 350 } VPU_EX_SrcMode; 351 352 /// codec type enumerator 353 typedef enum 354 { 355 ///unsupported codec type 356 E_VPU_EX_CODEC_TYPE_NONE = 0, 357 ///MPEG 1/2 358 E_VPU_EX_CODEC_TYPE_MPEG2, 359 ///H263 (short video header) 360 E_VPU_EX_CODEC_TYPE_H263, 361 ///MPEG4 (default) 362 E_VPU_EX_CODEC_TYPE_MPEG4, 363 ///MPEG4 (Divx311) 364 E_VPU_EX_CODEC_TYPE_DIVX311, 365 ///MPEG4 (Divx412) 366 E_VPU_EX_CODEC_TYPE_DIVX412, 367 ///FLV 368 E_VPU_EX_CODEC_TYPE_FLV, 369 ///VC1 advanced profile (VC1) 370 E_VPU_EX_CODEC_TYPE_VC1_ADV, 371 ///VC1 main profile (RCV) 372 E_VPU_EX_CODEC_TYPE_VC1_MAIN, 373 ///Real Video version 8 374 E_VPU_EX_CODEC_TYPE_RV8, 375 ///Real Video version 9 and 10 376 E_VPU_EX_CODEC_TYPE_RV9, 377 ///H264 378 E_VPU_EX_CODEC_TYPE_H264, 379 ///AVS 380 E_VPU_EX_CODEC_TYPE_AVS, 381 ///MJPEG 382 E_VPU_EX_CODEC_TYPE_MJPEG, 383 ///MVC 384 E_VPU_EX_CODEC_TYPE_MVC, 385 ///VP8 386 E_VPU_EX_CODEC_TYPE_VP8, 387 ///HEVC 388 E_VPU_EX_CODEC_TYPE_HEVC, 389 ///VP9 390 E_VPU_EX_CODEC_TYPE_VP9, 391 // HEVC Dolby vision 392 E_VPU_EX_CODEC_TYPE_HEVC_DV, 393 E_VPU_EX_CODEC_TYPE_NUM 394 } VPU_EX_CodecType; 395 396 /// record origin stream type for VPU hal 397 typedef enum 398 { 399 E_VPU_ORIGINAL_MAIN_STREAM = 0, 400 E_VPU_ORIGINAL_SUB_STREAM, 401 E_VPU_ORIGINAL_N_STREAM, 402 } VPU_EX_Original_Stream; 403 404 typedef struct 405 { 406 VPU_EX_ClockSpeed eClockSpeed; 407 MS_BOOL bClockInv; 408 MS_S32 s32VPUMutexID; 409 MS_U32 u32VPUMutexTimeout; 410 MS_U8 u8MiuSel; 411 } VPU_EX_InitParam; 412 413 typedef struct 414 { 415 MS_U32 u32Id; 416 HAL_VPU_StreamId eVpuId; 417 VPU_EX_SourceType eSrcType; 418 VPU_EX_DecoderType eDecType; 419 MS_U8 u8HalId; // hal MVD/HVD id 420 MS_U32 u32HeapSize; 421 } VPU_EX_TaskInfo; 422 423 typedef struct 424 { 425 MS_VIRT u32DstAddr; 426 MS_VIRT u32DstSize; 427 MS_VIRT u32BinSize; 428 MS_VIRT u32BinAddr; 429 MS_U8 u8SrcType; 430 } VPU_EX_FWCodeCfg; 431 432 typedef struct 433 { 434 MS_VIRT u32DstAddr; 435 MS_VIRT u32BinAddr; 436 MS_VIRT u32BinSize; 437 MS_VIRT u32FrameBufAddr; 438 MS_VIRT u32VLCTableOffset; 439 } VPU_EX_VLCTblCfg; 440 441 #ifdef VDEC3 442 typedef struct 443 { 444 MS_VIRT u32FrameBufAddr; 445 MS_VIRT u32FrameBufSize; 446 } VPU_EX_FBCfg; 447 #endif 448 449 /// VPU init parameters for dual decoder 450 typedef struct 451 { 452 VPU_EX_FWCodeCfg *pFWCodeCfg; 453 VPU_EX_TaskInfo *pTaskInfo; 454 VPU_EX_VLCTblCfg *pVLCCfg; 455 #ifdef VDEC3 456 VPU_EX_FBCfg *pFBCfg; 457 #endif 458 } VPU_EX_NDecInitPara; 459 460 typedef struct 461 { 462 MS_U8 u8DecMod; 463 MS_U8 u8CodecCnt; 464 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 465 MS_U8 u8ArgSize; 466 MS_U32 u32Arg; 467 } VPU_EX_DecModCfg; 468 469 470 typedef enum 471 { 472 E_VDEC_EX_CODEC_PROFILE_NONE, 473 474 E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, 475 476 E_VDEC_EX_CODEC_PROFILE_MP4_ASP, 477 478 E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, 479 480 E_VDEC_EX_CODEC_PROFILE_VC1_AP, 481 482 E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, 483 484 E_VDEC_EX_CODEC_PROFILE_VP9_0, 485 E_VDEC_EX_CODEC_PROFILE_VP9_2, 486 487 E_VDEC_EX_CODEC_PROFILE_H264_CBP, 488 E_VDEC_EX_CODEC_PROFILE_H264_BP, 489 E_VDEC_EX_CODEC_PROFILE_H264_XP, 490 E_VDEC_EX_CODEC_PROFILE_H264_MP, 491 E_VDEC_EX_CODEC_PROFILE_H264_HIP, 492 E_VDEC_EX_CODEC_PROFILE_H264_PHIP, 493 E_VDEC_EX_CODEC_PROFILE_H264_CHIP, 494 E_VDEC_EX_CODEC_PROFILE_H264_HI10P, 495 E_VDEC_EX_CODEC_PROFILE_H264_HI422P, 496 E_VDEC_EX_CODEC_PROFILE_H264_HI444PP, 497 498 E_VDEC_EX_CODEC_PROFILE_H265_MAIN, 499 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, 500 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_12, 501 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_10, 502 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_12, 503 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444, 504 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_10, 505 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_12, 506 507 E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, 508 509 510 } VDEC_EX_CODEC_CAP_PROFILE_INFO; 511 512 typedef enum 513 { 514 E_VDEC_EX_CODEC_LEVEL_NONE, 515 516 E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, 517 518 E_VDEC_EX_CODEC_LEVEL_MP4_L5, 519 520 E_VDEC_EX_CODEC_LEVEL_VC1_L3, 521 522 E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, 523 524 525 E_VDEC_EX_CODEC_LEVEL_H264_1, 526 E_VDEC_EX_CODEC_LEVEL_H264_1B, 527 E_VDEC_EX_CODEC_LEVEL_H264_1_1, 528 E_VDEC_EX_CODEC_LEVEL_H264_1_2, 529 E_VDEC_EX_CODEC_LEVEL_H264_1_3, 530 E_VDEC_EX_CODEC_LEVEL_H264_2, 531 E_VDEC_EX_CODEC_LEVEL_H264_2_1, 532 E_VDEC_EX_CODEC_LEVEL_H264_2_2, 533 E_VDEC_EX_CODEC_LEVEL_H264_3, 534 E_VDEC_EX_CODEC_LEVEL_H264_3_1, 535 E_VDEC_EX_CODEC_LEVEL_H264_3_2, 536 E_VDEC_EX_CODEC_LEVEL_H264_4, 537 E_VDEC_EX_CODEC_LEVEL_H264_4_1, 538 E_VDEC_EX_CODEC_LEVEL_H264_4_2, 539 E_VDEC_EX_CODEC_LEVEL_H264_5, 540 E_VDEC_EX_CODEC_LEVEL_H264_5_1, 541 E_VDEC_EX_CODEC_LEVEL_H264_5_2, 542 543 E_VDEC_EX_CODEC_LEVEL_H265_1, 544 E_VDEC_EX_CODEC_LEVEL_H265_2, 545 E_VDEC_EX_CODEC_LEVEL_H265_2_1, 546 E_VDEC_EX_CODEC_LEVEL_H265_3, 547 E_VDEC_EX_CODEC_LEVEL_H265_3_1, 548 E_VDEC_EX_CODEC_LEVEL_H265_4_MT, 549 E_VDEC_EX_CODEC_LEVEL_H265_4_HT, 550 E_VDEC_EX_CODEC_LEVEL_H265_4_1_MT, 551 E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, 552 E_VDEC_EX_CODEC_LEVEL_H265_5_MT, 553 E_VDEC_EX_CODEC_LEVEL_H265_5_HT, 554 E_VDEC_EX_CODEC_LEVEL_H265_5_1_MT, 555 E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, 556 E_VDEC_EX_CODEC_LEVEL_H265_5_2_MT, 557 E_VDEC_EX_CODEC_LEVEL_H265_5_2_HT, 558 E_VDEC_EX_CODEC_LEVEL_H265_6_MT, 559 E_VDEC_EX_CODEC_LEVEL_H265_6_HT, 560 E_VDEC_EX_CODEC_LEVEL_H265_6_1_MT, 561 E_VDEC_EX_CODEC_LEVEL_H265_6_1_HT, 562 E_VDEC_EX_CODEC_LEVEL_H265_6_2_MT, 563 E_VDEC_EX_CODEC_LEVEL_H265_6_2_HT, 564 565 E_VDEC_EX_CODEC_LEVEL_AVS_6010860, 566 567 } VDEC_EX_CODEC_CAP_LEVEL_INFO; 568 569 570 typedef enum 571 { 572 E_VDEC_EX_CODEC_VERSION_NONE, 573 574 E_VDEC_EX_CODEC_VERSION_DIVX_311, 575 E_VDEC_EX_CODEC_VERSION_DIVX_4, 576 E_VDEC_EX_CODEC_VERSION_DIVX_5, 577 E_VDEC_EX_CODEC_VERSION_DIVX_6, 578 579 E_VDEC_EX_CODEC_VERSION_FLV_1, 580 581 E_VDEC_EX_CODEC_VERSION_H263_1, 582 583 } VDEC_EX_CODEC_CAP_VERSION_INFO; 584 585 typedef struct DLL_PACKED 586 { 587 MS_U16 u16CodecCapWidth; 588 MS_U16 u16CodecCapHeight; 589 MS_U8 u8CodecCapFrameRate; 590 VDEC_EX_CODEC_CAP_PROFILE_INFO u8CodecCapProfile; 591 VDEC_EX_CODEC_CAP_VERSION_INFO u8CodecCapVersion; 592 VDEC_EX_CODEC_CAP_LEVEL_INFO u8CodecCapLevel; 593 MS_U32 u32CodecType; 594 MS_U32 u32Reserved1; 595 }VDEC_EX_CODEC_CAP_INFO; 596 597 //------------------------------------------------------------------------------------------------- 598 // Function and Variable 599 //------------------------------------------------------------------------------------------------- 600 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex); 601 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 602 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 603 #ifdef VDEC3 604 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId); 605 #else 606 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 607 #endif 608 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 609 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 610 611 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 612 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase); 613 614 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 615 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 616 MS_BOOL HAL_VPU_EX_DeInit(void); 617 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 618 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 619 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr); 620 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 621 void HAL_VPU_EX_SwRstRelse(void); 622 void HAL_VPU_EX_SwRelseMAU(void); 623 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Address); 624 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Address, MS_U32 u32Value); 625 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 626 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 627 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 628 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 629 MS_U32 HAL_VPU_EX_GetProgCnt(void); 630 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 631 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr); 632 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 633 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id); 634 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id); 635 MS_BOOL HAL_VPU_EX_IsPowered(void); 636 MS_BOOL HAL_VPU_EX_IsRsted(void); 637 MS_BOOL HAL_VPU_EX_IsEVDR2(void); 638 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 639 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 640 #ifdef VDEC3 641 MS_BOOL HAL_VPU_EX_EVDInUsed(void); 642 #if SUPPORT_G2VP9 643 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void); 644 #endif 645 #endif 646 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable); 647 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 648 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 649 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 650 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 651 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo); 652 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id); 653 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id); 654 void HAL_VPU_EX_Mutex_Lock(void); 655 void HAL_VPU_EX_Mutex_UnLock(void); 656 657 MS_VIRT HAL_VPU_EX_MIU1BASE(void); 658 MS_VIRT HAL_VPU_EX_GetSHMAddr(void); 659 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 660 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr); 661 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 662 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass); 663 void HAL_VPU_EX_ForceSwRst(void); 664 665 #ifdef VDEC3 666 typedef enum 667 { 668 E_HVD_CMDQ_CMD, 669 E_HVD_CMDQ_ARG, 670 } HVD_COMMAND_QUEUE_TYPE; 671 672 typedef enum 673 { 674 E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL, 675 E_HVD_COMMAND_QUEUE_NOT_INITIALED, 676 E_HVD_COMMAND_QUEUE_FULL, 677 E_HVD_COMMAND_QUEUE_SEND_FAIL, 678 } HVD_DRAM_COMMAND_QUEUE_SEND_STATUS; 679 680 681 typedef struct 682 { 683 MS_VIRT u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 684 MS_U32 u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 685 MS_U64 u64TimeStamp; ///< Packet time stamp. unit: ms. 686 MS_U32 u32ID_L; ///< Packet ID low part. 687 MS_U32 u32ID_H; ///< Packet ID high part. 688 MS_U8 u8Version; ///< Packet version 0 means u32Offset is the offset of ES buffer 689 ///< 1 means u32Offset is used as esHandleID 690 } HAL_VPU_EX_PacketInfo; 691 // *****************Virtual BBU function***************** 692 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr); 693 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr); 694 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 695 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 696 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr); 697 // *****************General dram command queue function***************** 698 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd); 699 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd); 700 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg); 701 // *****************Dram command queue function***************** 702 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue); 703 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue); 704 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 705 // *****************Display dram command queue function***************** 706 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue); 707 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue); 708 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 709 // *****************General purpose function***************** 710 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr); 711 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit); 712 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit); 713 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType); 714 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU); 715 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo); 716 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType); 717 // *****************CMA function***************** 718 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode, 719 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize); 720 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut); 721 #endif 722 #ifdef VDEC3_FB 723 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType); 724 #endif 725 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size); 726 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx); 727 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream); 728 #ifdef CONFIG_MSTAR_CLKM 729 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable); 730 #endif 731 732 #else 733 typedef struct 734 { 735 MS_PHY Bitstream_Addr_Main; 736 MS_U32 Bitstream_Len_Main; 737 MS_PHY Bitstream_Addr_Sub; 738 MS_U32 Bitstream_Len_Sub; 739 MS_PHY MIU1_BaseAddr; 740 } VPU_EX_LOCK_DOWN_REGISTER; 741 742 743 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr); 744 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 745 746 #endif 747 #endif // _HAL_VPU_EX_H_ 748 749