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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE) 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 121 #define VPU_FORCE_MIU_MODE 1 122 #define VPU_ENABLE_IQMEM 1 123 #define VPU_IQMEM_BASE 0xe0000000 124 125 126 #define ENABLE_DECOMPRESS_FUNCTION TRUE 127 128 #define VPU_CLOCK_480MHZ BITS(6:2,3) 129 #define VPU_CLOCK_432MHZ BITS(6:2,6) 130 #define VPU_CLOCK_384MHZ BITS(6:2,7) 131 #define VPU_ICG_EN BIT(8) 132 //#define VPU_LITE_ICG_EN BIT(9) 133 134 #define VPU_HI_MBOX0 0 135 #define VPU_HI_MBOX1 1 136 #define VPU_RISC_MBOX0 2 137 #define VPU_RISC_MBOX1 3 138 139 140 #define VPU_EX_TimerDelayMS(x) \ 141 do \ 142 { \ 143 volatile MS_U32 ticks = 0; \ 144 while (ticks < (((MS_U32) (x)) << 13)) \ 145 { \ 146 ticks++; \ 147 } \ 148 } while(0) 149 150 #ifdef VDEC3 151 #define VPU_BBU_NAL_TBL BIT(0) 152 #define VPU_BBU_ES_BUFFER BIT(1) 153 #define HAL_VPU_INVALID_BBU_ID 0xFFFFFFFF 154 #define VPU_MAX_DEC_NUM 16 155 #else 156 #define VPU_MAX_DEC_NUM 2 157 #endif 158 #define CHECK_NULL_PTR(vbbu_addr) (((void *)(vbbu_addr)) == NULL) 159 160 //------------------------------------------------------------------------------------------------- 161 // Type and Structure 162 //------------------------------------------------------------------------------------------------- 163 typedef enum 164 { 165 E_HAL_HVD_STREAM_NONE = 0x0, 166 167 //Support TSP/TS/File mode 168 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 169 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 170 E_HAL_HVD_MAIN_STREAM_MAX, 171 172 //Only support file mode 173 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 174 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 175 E_HAL_HVD_SUB_STREAM1, 176 E_HAL_HVD_SUB_STREAM_MAX, 177 178 #ifdef VDEC3 179 E_HAL_HVD_N_STREAM_BASE = 0x40, 180 E_HAL_HVD_N_STREAM0 = E_HAL_HVD_N_STREAM_BASE, 181 E_HAL_HVD_N_STREAM_MAX = E_HAL_HVD_N_STREAM0 + VPU_MAX_DEC_NUM, 182 #endif 183 184 //Only support MVC stream 185 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 186 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 187 E_HAL_HVD_MVC_Sub_View, 188 E_HAL_HVD_MVC_STREAM_MAX, 189 } HAL_HVD_StreamId; 190 191 typedef enum 192 { 193 E_VPU_EX_DECODER_NONE = 0, 194 E_VPU_EX_DECODER_GET, 195 E_VPU_EX_DECODER_GET_MVC, 196 E_VPU_EX_DECODER_MVD, 197 E_VPU_EX_DECODER_HVD, 198 E_VPU_EX_DECODER_MJPEG, 199 E_VPU_EX_DECODER_RVD, 200 E_VPU_EX_DECODER_MVC, 201 E_VPU_EX_DECODER_VP8, 202 #ifdef VDEC3 203 E_VPU_EX_DECODER_EVD, 204 #if SUPPORT_G2VP9 205 E_VPU_EX_DECODER_G2VP9, 206 #endif 207 #endif 208 } VPU_EX_DecoderType; 209 210 #ifdef CONFIG_MSTAR_CLKM 211 typedef enum 212 { 213 E_VPU_EX_CLKPORT_MVD = 0, 214 E_VPU_EX_CLKPORT_MVD_CORE, 215 E_VPU_EX_CLKPORT_MVD_PAS, 216 E_VPU_EX_CLKPORT_HVD, 217 E_VPU_EX_CLKPORT_HVD_IDB, 218 E_VPU_EX_CLKPORT_HVD_AEC, 219 E_VPU_EX_CLKPORT_HVD_AEC_LITE, 220 E_VPU_EX_CLKPORT_VP8, 221 E_VPU_EX_CLKPORT_EVD, 222 E_VPU_EX_CLKPORT_EVD_PPU, 223 E_VPU_EX_CLKPORT_EVD_LITE, 224 E_VPU_EX_CLKPORT_EVD_PPU_LITE, 225 E_VPU_EX_CLKPORT_VD_MHEG5, 226 E_VPU_EX_CLKPORT_VD_MHEG5_LITE, 227 } VPU_EX_ClkPortType; 228 #endif 229 230 typedef enum 231 { 232 E_VPU_EX_CLOCK_480MHZ = VPU_CLOCK_480MHZ, 233 E_VPU_EX_CLOCK_432MHZ = VPU_CLOCK_432MHZ, 234 E_VPU_EX_CLOCK_384MHZ = VPU_CLOCK_384MHZ, 235 } VPU_EX_ClockSpeed; 236 237 typedef enum 238 { 239 E_HAL_VPU_STREAM_NONE = 0x0, 240 241 //Support TSP/TS File/File mode 242 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 243 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 244 E_HAL_VPU_MAIN_STREAM_MAX, 245 246 //Only support file mode 247 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 248 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 249 E_HAL_VPU_SUB_STREAM_MAX, 250 251 #ifdef VDEC3 252 E_HAL_VPU_N_STREAM_BASE = 0x40, 253 E_HAL_VPU_N_STREAM0 = E_HAL_VPU_N_STREAM_BASE, 254 E_HAL_VPU_N_STREAM_MAX = E_HAL_VPU_N_STREAM0 + VPU_MAX_DEC_NUM, 255 #endif 256 257 //Only support MVC stream 258 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 259 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 260 E_HAL_VPU_MVC_SUB_VIEW, 261 E_HAL_VPU_MVC_STREAM_MAX, 262 } HAL_VPU_StreamId; 263 264 typedef enum 265 { 266 //Support TSP/TS/File mode 267 E_HAL_VPU_MAIN_STREAM, 268 269 //Only support file mode 270 E_HAL_VPU_SUB_STREAM, 271 272 //Only support MVC mode 273 E_HAL_VPU_MVC_STREAM, 274 275 #ifdef VDEC3 276 E_HAL_VPU_N_STREAM, 277 #endif 278 } HAL_VPU_StreamType; 279 280 typedef enum 281 { 282 //Support TSP/TS/File mode 283 E_VPU_EX_INPUT_TSP, 284 //Only support file mode 285 E_VPU_EX_INPUT_FILE, 286 E_VPU_EX_INPUT_NONE, 287 } VPU_EX_SourceType; 288 289 typedef enum 290 { 291 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 292 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 293 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 294 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 295 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 296 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 297 } VPU_EX_UartLevel; 298 299 typedef enum 300 { 301 E_VPU_EX_FW_VER_CTRLR = 0, 302 E_VPU_EX_FW_VER_MVD_FW, 303 E_VPU_EX_FW_VER_HVD_FW, 304 E_VPU_EX_FW_VER_MVD_IF, 305 E_VPU_EX_FW_VER_HVD_IF, 306 } VPU_EX_FWVerType; 307 308 /// DecodeMode for f/w tasks 309 typedef enum 310 { 311 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 312 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 313 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 314 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 315 } VPU_EX_DecMode; 316 317 /// CmdMode for KOREA3D or PIP mode 318 typedef enum 319 { 320 //Group1:Set Korea3DTV mode 321 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 322 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 323 E_VPU_CMD_MODE_KR3D_FORCE_P, 324 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 325 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 326 327 //Group2:Set PIP mode 328 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 329 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 330 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 331 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 332 } VPU_EX_CmdMode; 333 334 /// input source select enumerator 335 typedef enum 336 { 337 ///DTV mode 338 E_VPU_EX_SRC_MODE_DTV = 0, 339 ///TS file mode 340 E_VPU_EX_SRC_MODE_TS_FILE, 341 ///generic file mode 342 E_VPU_EX_SRC_MODE_FILE, 343 /// TS file and dual ES buffer mode 344 E_VPU_EX_SRC_MODE_TS_FILE_DUAL_ES, 345 ///generic file and dual ES buffer mode 346 E_VPU_EX_SRC_MODE_FILE_DUAL_ES, 347 } VPU_EX_SrcMode; 348 349 /// codec type enumerator 350 typedef enum 351 { 352 ///unsupported codec type 353 E_VPU_EX_CODEC_TYPE_NONE = 0, 354 ///MPEG 1/2 355 E_VPU_EX_CODEC_TYPE_MPEG2, 356 ///H263 (short video header) 357 E_VPU_EX_CODEC_TYPE_H263, 358 ///MPEG4 (default) 359 E_VPU_EX_CODEC_TYPE_MPEG4, 360 ///MPEG4 (Divx311) 361 E_VPU_EX_CODEC_TYPE_DIVX311, 362 ///MPEG4 (Divx412) 363 E_VPU_EX_CODEC_TYPE_DIVX412, 364 ///FLV 365 E_VPU_EX_CODEC_TYPE_FLV, 366 ///VC1 advanced profile (VC1) 367 E_VPU_EX_CODEC_TYPE_VC1_ADV, 368 ///VC1 main profile (RCV) 369 E_VPU_EX_CODEC_TYPE_VC1_MAIN, 370 ///Real Video version 8 371 E_VPU_EX_CODEC_TYPE_RV8, 372 ///Real Video version 9 and 10 373 E_VPU_EX_CODEC_TYPE_RV9, 374 ///H264 375 E_VPU_EX_CODEC_TYPE_H264, 376 ///AVS 377 E_VPU_EX_CODEC_TYPE_AVS, 378 ///MJPEG 379 E_VPU_EX_CODEC_TYPE_MJPEG, 380 ///MVC 381 E_VPU_EX_CODEC_TYPE_MVC, 382 ///VP8 383 E_VPU_EX_CODEC_TYPE_VP8, 384 ///HEVC 385 E_VPU_EX_CODEC_TYPE_HEVC, 386 ///VP9 387 E_VPU_EX_CODEC_TYPE_VP9, 388 // HEVC Dolby vision 389 E_VPU_EX_CODEC_TYPE_HEVC_DV, 390 E_VPU_EX_CODEC_TYPE_NUM 391 } VPU_EX_CodecType; 392 393 /// record origin stream type for VPU hal 394 typedef enum 395 { 396 E_VPU_ORIGINAL_MAIN_STREAM = 0, 397 E_VPU_ORIGINAL_SUB_STREAM, 398 E_VPU_ORIGINAL_N_STREAM, 399 } VPU_EX_Original_Stream; 400 401 typedef struct 402 { 403 VPU_EX_ClockSpeed eClockSpeed; 404 MS_BOOL bClockInv; 405 MS_S32 s32VPUMutexID; 406 MS_U32 u32VPUMutexTimeout; 407 MS_U8 u8MiuSel; 408 } VPU_EX_InitParam; 409 410 typedef struct 411 { 412 MS_U32 u32Id; 413 HAL_VPU_StreamId eVpuId; 414 VPU_EX_SourceType eSrcType; 415 VPU_EX_DecoderType eDecType; 416 MS_U8 u8HalId; // hal MVD/HVD id 417 MS_U32 u32HeapSize; 418 } VPU_EX_TaskInfo; 419 420 typedef struct 421 { 422 MS_VIRT u32DstAddr; 423 MS_VIRT u32DstSize; 424 MS_VIRT u32BinSize; 425 MS_VIRT u32BinAddr; 426 MS_U8 u8SrcType; 427 } VPU_EX_FWCodeCfg; 428 429 typedef struct 430 { 431 MS_VIRT u32DstAddr; 432 MS_VIRT u32BinAddr; 433 MS_VIRT u32BinSize; 434 MS_VIRT u32FrameBufAddr; 435 MS_VIRT u32VLCTableOffset; 436 } VPU_EX_VLCTblCfg; 437 438 #ifdef VDEC3 439 typedef struct 440 { 441 MS_VIRT u32FrameBufAddr; 442 MS_VIRT u32FrameBufSize; 443 } VPU_EX_FBCfg; 444 #endif 445 446 /// VPU init parameters for dual decoder 447 typedef struct 448 { 449 VPU_EX_FWCodeCfg *pFWCodeCfg; 450 VPU_EX_TaskInfo *pTaskInfo; 451 VPU_EX_VLCTblCfg *pVLCCfg; 452 #ifdef VDEC3 453 VPU_EX_FBCfg *pFBCfg; 454 #endif 455 } VPU_EX_NDecInitPara; 456 457 typedef struct 458 { 459 MS_U8 u8DecMod; 460 MS_U8 u8CodecCnt; 461 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 462 MS_U8 u8ArgSize; 463 MS_U32 u32Arg; 464 } VPU_EX_DecModCfg; 465 466 467 typedef enum 468 { 469 E_VDEC_EX_CODEC_PROFILE_NONE, 470 471 E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, 472 473 E_VDEC_EX_CODEC_PROFILE_MP4_ASP, 474 475 E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, 476 477 E_VDEC_EX_CODEC_PROFILE_VC1_AP, 478 479 E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, 480 481 E_VDEC_EX_CODEC_PROFILE_VP9_0, 482 E_VDEC_EX_CODEC_PROFILE_VP9_2, 483 484 E_VDEC_EX_CODEC_PROFILE_H264_CBP, 485 E_VDEC_EX_CODEC_PROFILE_H264_BP, 486 E_VDEC_EX_CODEC_PROFILE_H264_XP, 487 E_VDEC_EX_CODEC_PROFILE_H264_MP, 488 E_VDEC_EX_CODEC_PROFILE_H264_HIP, 489 E_VDEC_EX_CODEC_PROFILE_H264_PHIP, 490 E_VDEC_EX_CODEC_PROFILE_H264_CHIP, 491 E_VDEC_EX_CODEC_PROFILE_H264_HI10P, 492 E_VDEC_EX_CODEC_PROFILE_H264_HI422P, 493 E_VDEC_EX_CODEC_PROFILE_H264_HI444PP, 494 495 E_VDEC_EX_CODEC_PROFILE_H265_MAIN, 496 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, 497 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_12, 498 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_10, 499 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_422_12, 500 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444, 501 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_10, 502 E_VDEC_EX_CODEC_PROFILE_H265_MAIN_444_12, 503 504 E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, 505 506 507 } VDEC_EX_CODEC_CAP_PROFILE_INFO; 508 509 typedef enum 510 { 511 E_VDEC_EX_CODEC_LEVEL_NONE, 512 513 E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, 514 515 E_VDEC_EX_CODEC_LEVEL_MP4_L5, 516 517 E_VDEC_EX_CODEC_LEVEL_VC1_L3, 518 519 E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, 520 521 522 E_VDEC_EX_CODEC_LEVEL_H264_1, 523 E_VDEC_EX_CODEC_LEVEL_H264_1B, 524 E_VDEC_EX_CODEC_LEVEL_H264_1_1, 525 E_VDEC_EX_CODEC_LEVEL_H264_1_2, 526 E_VDEC_EX_CODEC_LEVEL_H264_1_3, 527 E_VDEC_EX_CODEC_LEVEL_H264_2, 528 E_VDEC_EX_CODEC_LEVEL_H264_2_1, 529 E_VDEC_EX_CODEC_LEVEL_H264_2_2, 530 E_VDEC_EX_CODEC_LEVEL_H264_3, 531 E_VDEC_EX_CODEC_LEVEL_H264_3_1, 532 E_VDEC_EX_CODEC_LEVEL_H264_3_2, 533 E_VDEC_EX_CODEC_LEVEL_H264_4, 534 E_VDEC_EX_CODEC_LEVEL_H264_4_1, 535 E_VDEC_EX_CODEC_LEVEL_H264_4_2, 536 E_VDEC_EX_CODEC_LEVEL_H264_5, 537 E_VDEC_EX_CODEC_LEVEL_H264_5_1, 538 E_VDEC_EX_CODEC_LEVEL_H264_5_2, 539 540 E_VDEC_EX_CODEC_LEVEL_H265_1, 541 E_VDEC_EX_CODEC_LEVEL_H265_2, 542 E_VDEC_EX_CODEC_LEVEL_H265_2_1, 543 E_VDEC_EX_CODEC_LEVEL_H265_3, 544 E_VDEC_EX_CODEC_LEVEL_H265_3_1, 545 E_VDEC_EX_CODEC_LEVEL_H265_4_MT, 546 E_VDEC_EX_CODEC_LEVEL_H265_4_HT, 547 E_VDEC_EX_CODEC_LEVEL_H265_4_1_MT, 548 E_VDEC_EX_CODEC_LEVEL_H265_4_1_HT, 549 E_VDEC_EX_CODEC_LEVEL_H265_5_MT, 550 E_VDEC_EX_CODEC_LEVEL_H265_5_HT, 551 E_VDEC_EX_CODEC_LEVEL_H265_5_1_MT, 552 E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, 553 E_VDEC_EX_CODEC_LEVEL_H265_5_2_MT, 554 E_VDEC_EX_CODEC_LEVEL_H265_5_2_HT, 555 E_VDEC_EX_CODEC_LEVEL_H265_6_MT, 556 E_VDEC_EX_CODEC_LEVEL_H265_6_HT, 557 E_VDEC_EX_CODEC_LEVEL_H265_6_1_MT, 558 E_VDEC_EX_CODEC_LEVEL_H265_6_1_HT, 559 E_VDEC_EX_CODEC_LEVEL_H265_6_2_MT, 560 E_VDEC_EX_CODEC_LEVEL_H265_6_2_HT, 561 562 E_VDEC_EX_CODEC_LEVEL_AVS_6010860, 563 564 } VDEC_EX_CODEC_CAP_LEVEL_INFO; 565 566 567 typedef enum 568 { 569 E_VDEC_EX_CODEC_VERSION_NONE, 570 571 E_VDEC_EX_CODEC_VERSION_DIVX_311, 572 E_VDEC_EX_CODEC_VERSION_DIVX_4, 573 E_VDEC_EX_CODEC_VERSION_DIVX_5, 574 E_VDEC_EX_CODEC_VERSION_DIVX_6, 575 576 E_VDEC_EX_CODEC_VERSION_FLV_1, 577 578 E_VDEC_EX_CODEC_VERSION_H263_1, 579 580 } VDEC_EX_CODEC_CAP_VERSION_INFO; 581 582 typedef struct DLL_PACKED 583 { 584 MS_U16 u16CodecCapWidth; 585 MS_U16 u16CodecCapHeight; 586 MS_U8 u8CodecCapFrameRate; 587 VDEC_EX_CODEC_CAP_PROFILE_INFO u8CodecCapProfile; 588 VDEC_EX_CODEC_CAP_VERSION_INFO u8CodecCapVersion; 589 VDEC_EX_CODEC_CAP_LEVEL_INFO u8CodecCapLevel; 590 MS_U32 u32CodecType; 591 MS_U32 u32Reserved1; 592 }VDEC_EX_CODEC_CAP_INFO; 593 594 //------------------------------------------------------------------------------------------------- 595 // Function and Variable 596 //------------------------------------------------------------------------------------------------- 597 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex); 598 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 599 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 600 #ifdef VDEC3 601 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId); 602 #else 603 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 604 #endif 605 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 606 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 607 608 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 609 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase); 610 611 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 612 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 613 MS_BOOL HAL_VPU_EX_DeInit(void); 614 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 615 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 616 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr); 617 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 618 void HAL_VPU_EX_SwRstRelse(void); 619 void HAL_VPU_EX_SwRelseMAU(void); 620 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Address); 621 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Address, MS_U32 u32Value); 622 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 623 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 624 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 625 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 626 MS_U32 HAL_VPU_EX_GetProgCnt(void); 627 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 628 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr); 629 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 630 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id); 631 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id); 632 MS_BOOL HAL_VPU_EX_IsPowered(void); 633 MS_BOOL HAL_VPU_EX_IsRsted(void); 634 MS_BOOL HAL_VPU_EX_IsEVDR2(void); 635 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 636 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 637 #ifdef VDEC3 638 MS_BOOL HAL_VPU_EX_EVDInUsed(void); 639 #if SUPPORT_G2VP9 640 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void); 641 #endif 642 #endif 643 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable); 644 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 645 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 646 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 647 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 648 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo); 649 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id); 650 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id); 651 void HAL_VPU_EX_Mutex_Lock(void); 652 void HAL_VPU_EX_Mutex_UnLock(void); 653 654 MS_VIRT HAL_VPU_EX_MIU1BASE(void); 655 MS_VIRT HAL_VPU_EX_GetSHMAddr(void); 656 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 657 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr); 658 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 659 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass); 660 void HAL_VPU_EX_ForceSwRst(void); 661 662 #ifdef VDEC3 663 typedef enum 664 { 665 E_HVD_CMDQ_CMD, 666 E_HVD_CMDQ_ARG, 667 } HVD_COMMAND_QUEUE_TYPE; 668 669 typedef enum 670 { 671 E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL, 672 E_HVD_COMMAND_QUEUE_NOT_INITIALED, 673 E_HVD_COMMAND_QUEUE_FULL, 674 E_HVD_COMMAND_QUEUE_SEND_FAIL, 675 } HVD_DRAM_COMMAND_QUEUE_SEND_STATUS; 676 677 678 typedef struct 679 { 680 MS_VIRT u32Offset; ///< Packet offset from bitstream buffer base address. unit: byte. 681 MS_U32 u32Length; ///< Packet size. unit: byte. ==> Move _VDEC_EX_ReparseVP8Packet to FW 682 MS_U64 u64TimeStamp; ///< Packet time stamp. unit: ms. 683 MS_U32 u32ID_L; ///< Packet ID low part. 684 MS_U32 u32ID_H; ///< Packet ID high part. 685 } HAL_VPU_EX_PacketInfo; 686 // *****************Virtual BBU function***************** 687 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr); 688 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr); 689 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 690 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr); 691 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr); 692 // *****************General dram command queue function***************** 693 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd); 694 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd); 695 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg); 696 // *****************Dram command queue function***************** 697 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue); 698 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue); 699 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 700 // *****************Display dram command queue function***************** 701 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue); 702 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue); 703 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg); 704 // *****************General purpose function***************** 705 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr); 706 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit); 707 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit); 708 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType); 709 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU); 710 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo); 711 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType); 712 // *****************CMA function***************** 713 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode, 714 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize); 715 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut); 716 #endif 717 #ifdef VDEC3_FB 718 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType); 719 #endif 720 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size); 721 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx); 722 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream); 723 #ifdef CONFIG_MSTAR_CLKM 724 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable); 725 #endif 726 727 #else 728 typedef struct 729 { 730 MS_PHY Bitstream_Addr_Main; 731 MS_U32 Bitstream_Len_Main; 732 MS_PHY Bitstream_Addr_Sub; 733 MS_U32 Bitstream_Len_Sub; 734 MS_PHY MIU1_BaseAddr; 735 } VPU_EX_LOCK_DOWN_REGISTER; 736 737 738 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr); 739 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 740 741 #endif 742 #endif // _HAL_VPU_EX_H_ 743 744