1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
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11 //
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15 //
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20 //
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32 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
134 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #if 0
138 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
139 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
140 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
141 static MS_U16 _u16DispQPtr = 0;
142 #endif
143
144 #define IS_TASK_ALIVE(id) ((id) != -1)
145 #ifndef UNUSED
146 #define UNUSED(x) (void)(x)
147 #endif
148
149
150 //---------------------------------- Mutex settings -----------------------------------------
151 #if HAL_HVD_ENABLE_MUTEX_PROTECT
152 #define _HAL_HVD_MutexCreate() \
153 do \
154 { \
155 if (s32HVDMutexID < 0) \
156 { \
157 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
158 } \
159 } while (0)
160
161 #define _HAL_HVD_MutexDelete() \
162 do \
163 { \
164 if (s32HVDMutexID >= 0) \
165 { \
166 OSAL_HVD_MutexDelete(s32HVDMutexID); \
167 s32HVDMutexID = -1; \
168 } \
169 } while (0)
170
171 #define _HAL_HVD_Entry() \
172 do \
173 { \
174 if (s32HVDMutexID >= 0) \
175 { \
176 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
177 { \
178 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
179 } \
180 } \
181 } while (0)
182
183 #define _HAL_HVD_Return(_ret_) \
184 do \
185 { \
186 if (s32HVDMutexID >= 0) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 return _ret_; \
191 } while(0)
192
193 #define _HAL_HVD_Release() \
194 do \
195 { \
196 if (s32HVDMutexID >= 0) \
197 { \
198 OSAL_HVD_MutexRelease(s32HVDMutexID); \
199 } \
200 } while (0)
201 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define _HAL_HVD_MutexCreate()
204 #define _HAL_HVD_MutexDelete()
205 #define _HAL_HVD_Entry()
206 #define _HAL_HVD_Return(_ret) {return _ret;}
207 #define _HAL_HVD_Release()
208
209 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
210
211 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
212 #define IS_TASK_ALIVE(id) ((id) != -1)
213 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
214
215 //------------------------------ MIU SETTINGS ----------------------------------
216 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(6))
217 //#define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(2))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
222
223 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(6))
224 //#define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(2))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
227 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(5))
228 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(3))
229
230
231 #define HVD_MVD_RW_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == 0))
232 #define HVD_MVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == 0))
233 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0))
234 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0))
235 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0))
236
237 #define HVD_MVD_RW_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == BIT(6)))
238 #define HVD_MVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == BIT(10)))
239 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)))
240 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == BIT(5)))
241 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == BIT(11)))
242
243
244
245 #if SUPPORT_EVD
246 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
247 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
248 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(2))
249
250 #define _MaskMiu1Req_EVD_RW1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
251 #define _MaskMiu1Req_EVD_RW2( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(1))
252 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(2))
253
254
255
256
257 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0))
258 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == 0))
259 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == 0))
260
261 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)))
262 #define HVD_EVD_RW2_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == BIT(1)))
263 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == BIT(10)))
264
265 #endif
266
267 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
268 do \
269 { \
270 if (HVD_##miu_clients##_ON_MIU0 == 1) \
271 { \
272 _MaskMiuReq_##miu_clients(mask); \
273 } \
274 else \
275 { \
276 if (HVD_##miu_clients##_ON_MIU1 == 1) \
277 { \
278 _MaskMiu1Req_##miu_clients(mask); \
279 } \
280 } \
281 } while (0)
282
283 // check RM is supported or not
284 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
285 #ifdef VDEC3
286 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
287 #else
288 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
289 #endif
290
291 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
292
293 //-------------------------------------------------------------------------------------------------
294 // Local Structures
295 //-------------------------------------------------------------------------------------------------
296
297 //-------------------------------------------------------------------------------------------------
298 // Local Functions Prototype
299 //-------------------------------------------------------------------------------------------------
300 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
301 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
302 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
303 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
304 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
305 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
306 static MS_U32 _HVD_EX_GetPC(void);
307 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
308 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
309 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
310 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
311 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
312 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
313 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
314 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
315 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
316 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
317 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
318 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
319 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
320 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
321 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
322 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
323 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
324 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed, MS_BOOL *isAVCUsed);
325 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable);
326 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable);
327 #if SUPPORT_EVD
328 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
329 #endif
330 #ifdef CONFIG_MSTAR_CLKM
331 static void HAL_EVD_EX_PowerCtrl_CLKM(MS_U32 u32Id, MS_BOOL bEnable);
332 #endif
333 #if SUPPORT_G2VP9 && defined(VDEC3)
334 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
335 #endif
336 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
337 #if SUPPORT_G2VP9 && defined(VDEC3)
338 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
339 #endif
340
341 //-------------------------------------------------------------------------------------------------
342 // Global Variables
343 //-------------------------------------------------------------------------------------------------
344 #if defined (__aeon__)
345 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
346 #else
347 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
348 #endif
349 #if HAL_HVD_ENABLE_MUTEX_PROTECT
350 MS_S32 s32HVDMutexID = -1;
351 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
352 #endif
353
354
355 #define HVD_EX_STACK_SIZE 4096
356 //-------------------------------------------------------------------------------------------------
357 // Local Variables
358 //-------------------------------------------------------------------------------------------------
359 typedef struct
360 {
361
362 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
363 MS_U8 g_hvd_nal_fill_pair[2][8];
364 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
365 MS_U16 _u16DispQPtr;
366 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
367
368 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
369 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
370 MS_U32 u32VPUClockType;
371 MS_U32 u32HVDClockType;//160
372 #if SUPPORT_EVD
373 MS_U32 u32EVDClockType;
374 #endif
375 #if SUPPORT_G2VP9 && defined(VDEC3)
376 MS_U32 u32VP9ClockType;
377 #endif
378 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
379
380 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
381 MS_BOOL g_RstFlag;
382 MS_U64 u64pts_real;
383 MS_PHY u32VP8BBUWptr;
384 MS_PHY u32EVDBBUWptr;
385 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
386 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
387 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
388 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
389 //pre_set
390 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
391 } HVD_Hal_CTX;
392
393 HVD_Hal_CTX* pHVDHalContext = NULL;
394 HVD_Hal_CTX gHVDHalContext;
395 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
396
397 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
398 {
399 {FALSE},
400 {FALSE},
401 {FALSE},
402 #ifdef VDEC3
403 {FALSE},
404 #endif
405 };
406
407 //-------------------------------------------------------------------------------------------------
408 // Debug Functions
409 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)410 void HVD_EX_SetRstFlag(MS_BOOL bRst)
411 {
412 pHVDHalContext->g_RstFlag = bRst;
413 }
HVD_EX_GetRstFlag(void)414 MS_BOOL HVD_EX_GetRstFlag(void)
415 {
416 return pHVDHalContext->g_RstFlag;
417 }
418
419 //-------------------------------------------------------------------------------------------------
420 // Local Functions
421 //-------------------------------------------------------------------------------------------------
422 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)423 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
424 {
425 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
426
427 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
428 #if SUPPORT_MSVP9
429 || u32CodecType == E_HVD_INIT_HW_VP9
430 #endif
431 )
432 return TRUE;
433
434 return FALSE;
435 }
436
_HAL_EX_BBU_VP8_InUsed(void)437 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
438 {
439 if (!pHVDHalContext)
440 return FALSE;
441
442 MS_U32 i;
443 MS_BOOL bRet = FALSE;
444
445 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
446 {
447 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
448 {
449 bRet = TRUE;
450 break;
451 }
452 }
453
454 return bRet;
455 }
456
457 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
458 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)459 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
460 {
461
462 MS_U32 ret = TRUE;
463 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
464
465 if(pCtrl == NULL || pstTaskInfo == NULL)
466 return FALSE;
467
468 pstTaskInfo->u32Id = u32Id;
469
470 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
471 {
472 case E_HVD_INIT_HW_RM:
473 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
474 break;
475 case E_HVD_INIT_HW_VP8:
476 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
477 break;
478 case E_HVD_INIT_HW_MVC:
479 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
480 break;
481 case E_HVD_INIT_HW_HEVC:
482 case E_HVD_INIT_HW_HEVC_DV:
483 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
484 break;
485 #if SUPPORT_MSVP9
486 case E_HVD_INIT_HW_VP9:
487 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
488 break;
489 #endif
490 #if SUPPORT_G2VP9
491 case E_HVD_INIT_HW_VP9:
492 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
493 break;
494 #endif
495 default:
496 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
497 break;
498 }
499
500 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
501
502 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
503 {
504 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
505 }
506 else
507 {
508 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
509 }
510
511 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
512
513 #ifdef SUPPORT_EVD
514 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
515 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
516 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
517 #endif
518 return ret;
519
520 }
521
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)522 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
523 {
524 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
525 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
526 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
527 _HAL_HVD_Entry();
528
529 if(pCtrl == NULL)
530 _HAL_HVD_Return(ret);
531
532 VPU_EX_TaskInfo taskInfo;
533 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
534
535 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
536
537 taskInfo.u8HalId = u8Idx;
538 ret = HAL_VPU_EX_GetBBUId(u32Id, &taskInfo, pCtrl->bShareBBU);
539
540 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
541 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
542
543 _HAL_HVD_Return(ret);
544 }
545
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)546 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
547 {
548 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
549 MS_BOOL ret = FALSE;
550 _HAL_HVD_Entry();
551
552 if(pCtrl == NULL)
553 _HAL_HVD_Return(ret);
554 VPU_EX_TaskInfo taskInfo;
555 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
556
557 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
558
559 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
560
561 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
562 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
563
564 _HAL_HVD_Return(ret);
565 }
566
HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId)567 MS_BOOL HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId)
568 {
569 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
570 MS_BOOL ret = FALSE;
571 _HAL_HVD_Entry();
572
573 if(pCtrl == NULL)
574 _HAL_HVD_Return(ret);
575 VPU_EX_TaskInfo taskInfo;
576 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
577
578 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
579
580 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, taskInfo.eDecType);
581
582 _HAL_HVD_Return(TRUE);
583 }
584 #endif
585
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)586 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
587 {
588 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
589 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
590 pstHVDStream->s32HvdPpTaskId = -1;
591 }
592
_HVD_EX_Context_Init_HAL(void)593 static void _HVD_EX_Context_Init_HAL(void)
594 {
595 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
596 pHVDHalContext->u32VPUClockType = 480;
597 pHVDHalContext->u32HVDClockType = 384;
598 #if SUPPORT_EVD
599 pHVDHalContext->u32EVDClockType = 576;
600 #endif
601 #if SUPPORT_G2VP9 && defined(VDEC3)
602 pHVDHalContext->u32VP9ClockType = 384;
603 #endif
604 #ifdef VDEC3
605 MS_U8 i;
606
607 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
608 {
609 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
610 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
611 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
612 }
613 #else
614 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
615 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
616 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
617 #endif
618 }
619
620
_HVD_EX_Get_REG_NAL_RPTR_HI(MS_U32 u32Id)621 static MS_U32 _HVD_EX_Get_REG_NAL_RPTR_HI(MS_U32 u32Id)
622 {
623 #if (HVD_ENABLE_MVC || (!VDEC3))
624 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
625 #endif
626 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
627 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
628 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
629 //HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
630
631 #if HVD_ENABLE_MVC
632 if(HAL_HVD_EX_CheckMVCID(u32Id))
633 {
634 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
635 }
636 #endif /// HVD_ENABLE_MVC
637
638
639 MS_U32 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI(u32RB);
640
641 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
642
643
644 #ifdef VDEC3
645 if ((0 == pCtrl->u32BBUId))
646 #else
647 if ((0 == u8TaskId))
648 #endif
649 {
650 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI(u32RB);
651
652 }
653 #ifdef VDEC3
654 else if (1 == pCtrl->u32BBUId)
655 #else
656 else if (1 == u8TaskId)
657 #endif
658 {
659 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS2(u32RB);
660 }
661 #ifdef VDEC3
662 else if (2 == pCtrl->u32BBUId)
663 #else
664 else if (2 == u8TaskId)
665 #endif
666 {
667 if(isEVD)
668 u32RegNalRptrHi = EVD_REG_NAL_RPTR_HI_BS3;
669 else
670 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS5;
671 }
672 #ifdef VDEC3
673 else if (3 == pCtrl->u32BBUId)
674 #else
675 else if (3 == u8TaskId)
676 #endif
677 {
678 if(isEVD)
679 u32RegNalRptrHi = EVD_REG_NAL_RPTR_HI_BS4;
680 else
681 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS6;
682 }
683 else
684 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
685
686
687 return u32RegNalRptrHi;
688
689 }
690
691
_HVD_EX_Get_REG_NAL_WPTR_HI(MS_U32 u32Id)692 static MS_U32 _HVD_EX_Get_REG_NAL_WPTR_HI(MS_U32 u32Id)
693 {
694 #if (HVD_ENABLE_MVC || (!VDEC3))
695 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
696 #endif
697 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
698 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
699 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
700 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
701
702 #if HVD_ENABLE_MVC
703 if(HAL_HVD_EX_CheckMVCID(u32Id))
704 {
705 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
706 }
707 #endif /// HVD_ENABLE_MVC
708
709
710 MS_U32 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI(u32RB);
711
712 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
713
714
715
716 #ifdef VDEC3
717 if ((0 == pCtrl->u32BBUId))
718 #else
719 if ((0 == u8TaskId))
720 #endif
721 {
722 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI(u32RB);
723
724 }
725 #ifdef VDEC3
726 else if (1 == pCtrl->u32BBUId)
727 #else
728 else if (1 == u8TaskId)
729 #endif
730 {
731 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS2(u32RB);
732 }
733 #ifdef VDEC3
734 else if (2 == pCtrl->u32BBUId)
735 #else
736 else if (2 == u8TaskId)
737 #endif
738 {
739 if(isEVD)
740 u32RegNalWptrHi = EVD_REG_NAL_WPTR_HI_BS3;
741 else
742 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS5;
743 }
744 #ifdef VDEC3
745 else if (3 == pCtrl->u32BBUId)
746 #else
747 else if (3 == u8TaskId)
748 #endif
749 {
750 if(isEVD)
751 u32RegNalWptrHi = EVD_REG_NAL_WPTR_HI_BS4;
752 else
753 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS6;
754 }
755 else
756 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
757
758
759 return u32RegNalWptrHi;
760
761 }
762
763
764
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)765 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
766 {
767 MS_U16 u16Ret = 0;
768 #if (HVD_ENABLE_MVC || (!VDEC3))
769 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
770 #endif
771 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
772 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
773 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
774 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
775
776 #if HVD_ENABLE_MVC
777 if(HAL_HVD_EX_CheckMVCID(u32Id))
778 {
779 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
780 }
781 #endif /// HVD_ENABLE_MVC
782
783 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
784 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
785
786 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
787 {
788 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
789 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
790 }
791 else
792 {
793 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
794 u16Ret = pShm->u32ColocateBBUReadPtr;
795 else
796 u16Ret = _HVD_Read2Byte(_HVD_EX_Get_REG_NAL_RPTR_HI(u32Id));
797 }
798
799 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
800 if(isEVD)
801 {
802 HVD_EX_MSG_DBG("isEVD: %d, Task0=%d, Task1=%d, Task2=%d, Task4=%d\n",
803 isEVD, _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)), _HVD_Read2Byte(EVD_REG_NAL_RPTR_HI_BS3), _HVD_Read2Byte(EVD_REG_NAL_RPTR_HI_BS4));
804 }
805 else
806 {
807 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task4=%d\n",
808 isEVD, _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS5), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS6));
809
810 }
811
812 return u16Ret;
813 }
814
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)815 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
816 {
817 MS_U16 u16Ret = 0;
818 #if (HVD_ENABLE_MVC || (!VDEC3))
819 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
820 #endif
821 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
822 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
823 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
824 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
825
826 #if HVD_ENABLE_MVC
827 if (HAL_HVD_EX_CheckMVCID(u32Id))
828 {
829 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
830 }
831 #endif /// HVD_ENABLE_MVC
832 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
833 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
834
835 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
836 {
837 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
838 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
839 }
840 else
841 {
842 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
843 u16Ret = pShm->u32ColocateBBUWritePtr;
844 else
845 u16Ret = _HVD_Read2Byte(_HVD_EX_Get_REG_NAL_WPTR_HI(u32Id));
846
847 }
848
849 return u16Ret;
850 }
851
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)852 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
853 {
854 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
855 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
856
857 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
858 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
859 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
860 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
861 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
862 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
863 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
864 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
865
866
867
868 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS5, 0);
869 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
870 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS6, 0);
871 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
872 _HVD_Write2Byte(EVD_REG_NAL_RPTR_HI_BS3, 0);
873 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
874 _HVD_Write2Byte(EVD_REG_NAL_RPTR_HI_BS4, 0);
875 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
876
877 }
878
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)879 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
880 {
881 #if (HVD_ENABLE_MVC || (!VDEC3))
882 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
883 #endif
884 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
885 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
886 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
887 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
888
889 #if HVD_ENABLE_MVC
890 if (HAL_HVD_EX_CheckMVCID(u32Id))
891 {
892 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
893 }
894 #endif /// HVD_ENABLE_MVC
895
896 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
897 {
898 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
899 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
900 }
901 else
902 {
903 _HVD_Write2Byte(_HVD_EX_Get_REG_NAL_WPTR_HI(u32Id), u16BBUNewWptr);
904 //if(pCtrl->InitParams.bColocateBBUMode)
905 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
906 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
907
908 }
909
910
911
912 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
913
914 if(isEVD)
915 {
916 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task3=%d\n",
917 isEVD, _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)), _HVD_Read2Byte(EVD_REG_NAL_WPTR_HI_BS3), _HVD_Read2Byte(EVD_REG_NAL_WPTR_HI_BS4));
918 }
919 else
920 {
921 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task3=%d\n",
922 isEVD, _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS5), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS6));
923 }
924
925 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
926 }
927
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)928 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
929 {
930 MS_BOOL bResult = TRUE;
931 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
932 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
933
934 switch (u8MBox)
935 {
936 case E_HVD_HI_0:
937 {
938 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
939 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
940 break;
941 }
942 case E_HVD_HI_1:
943 {
944 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
945 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
946 break;
947 }
948 case E_HVD_VPU_HI_0:
949 {
950 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
951 break;
952 }
953 case E_HVD_VPU_HI_1:
954 {
955 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
956 break;
957 }
958 default:
959 {
960 bResult = FALSE;
961 break;
962 }
963 }
964
965 return bResult;
966 }
967
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)968 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
969 {
970 MS_BOOL bResult = TRUE;
971 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
972 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
973
974 switch (u8MBox)
975 {
976 case E_HVD_HI_0:
977 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
978 break;
979 case E_HVD_HI_1:
980 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
981 break;
982 case E_HVD_RISC_0:
983 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
984 break;
985 case E_HVD_RISC_1:
986 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
987 break;
988 case E_HVD_VPU_HI_0:
989 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
990 break;
991 case E_HVD_VPU_HI_1:
992 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
993 break;
994 case E_HVD_VPU_RISC_0:
995 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
996 break;
997 case E_HVD_VPU_RISC_1:
998 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
999 break;
1000 default:
1001 break;
1002 }
1003
1004 return bResult;
1005 }
1006
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)1007 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
1008 {
1009 MS_BOOL bResult = TRUE;
1010 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1011 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1012
1013 switch (u8MBox)
1014 {
1015 case E_HVD_HI_0:
1016 {
1017 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
1018 break;
1019 }
1020 case E_HVD_HI_1:
1021 {
1022 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
1023 break;
1024 }
1025 case E_HVD_RISC_0:
1026 {
1027 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
1028 break;
1029 }
1030 case E_HVD_RISC_1:
1031 {
1032 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
1033 break;
1034 }
1035 case E_HVD_VPU_RISC_0:
1036 {
1037 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
1038 break;
1039 }
1040 case E_HVD_VPU_RISC_1:
1041 {
1042 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
1043 break;
1044 }
1045 default:
1046 {
1047 bResult = FALSE;
1048 break;
1049 }
1050 }
1051
1052 return bResult;
1053 }
1054
1055 #if 0
1056 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
1057 {
1058 switch (u8MBox)
1059 {
1060 case E_HVD_RISC_0:
1061 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
1062 break;
1063 case E_HVD_RISC_1:
1064 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
1065 break;
1066 case E_HVD_VPU_RISC_0:
1067 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
1068 break;
1069 case E_HVD_VPU_RISC_1:
1070 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
1071 break;
1072 default:
1073 break;
1074 }
1075 }
1076 #endif
1077
_HVD_EX_GetPC(void)1078 static MS_U32 _HVD_EX_GetPC(void)
1079 {
1080 MS_U32 u32PC = 0;
1081 u32PC = HAL_VPU_EX_GetProgCnt();
1082 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
1083 return u32PC;
1084 }
1085
_HVD_EX_Get_REG_ES_RPTR_L(MS_U32 u32Id)1086 static MS_U32 _HVD_EX_Get_REG_ES_RPTR_L(MS_U32 u32Id)
1087 {
1088 #if (HVD_ENABLE_MVC || (!VDEC3))
1089 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1090 #endif
1091 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1092 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1093 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1094 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1095
1096 #if HVD_ENABLE_MVC
1097 if(HAL_HVD_EX_CheckMVCID(u32Id))
1098 {
1099 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1100 }
1101 #endif /// HVD_ENABLE_MVC
1102
1103
1104 MS_U32 u32RegESRptrLow = HVD_REG_ESB_RPTR(u32RB);
1105
1106 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1107
1108
1109
1110 #ifdef VDEC3
1111 if ((0 == pCtrl->u32BBUId))
1112 #else
1113 if ((0 == u8TaskId))
1114 #endif
1115 {
1116 u32RegESRptrLow = HVD_REG_ESB_RPTR(u32RB);
1117
1118 }
1119 #ifdef VDEC3
1120 else if (1 == pCtrl->u32BBUId)
1121 #else
1122 else if (1 == u8TaskId)
1123 #endif
1124 {
1125 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS2(u32RB);
1126 }
1127 #ifdef VDEC3
1128 else if (2 == pCtrl->u32BBUId)
1129 #else
1130 else if (2 == u8TaskId)
1131 #endif
1132 {
1133 if(isEVD)
1134 u32RegESRptrLow = EVD_REG_ESB_RPTR_L_BS3;
1135 else
1136 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS5;
1137 }
1138 #ifdef VDEC3
1139 else if (3 == pCtrl->u32BBUId)
1140 #else
1141 else if (3 == u8TaskId)
1142 #endif
1143 {
1144 if(isEVD)
1145 u32RegESRptrLow = EVD_REG_ESB_RPTR_L_BS4;
1146 else
1147 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS6;
1148 }
1149 else
1150 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1151
1152
1153 return u32RegESRptrLow;
1154
1155 }
1156
_HVD_EX_Get_REG_ES_RPTR_H(MS_U32 u32Id)1157 static MS_U32 _HVD_EX_Get_REG_ES_RPTR_H(MS_U32 u32Id)
1158 {
1159 #if (HVD_ENABLE_MVC || (!VDEC3))
1160 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1161 #endif
1162 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1163 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1164 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1165 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1166
1167 #if HVD_ENABLE_MVC
1168 if(HAL_HVD_EX_CheckMVCID(u32Id))
1169 {
1170 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1171 }
1172 #endif /// HVD_ENABLE_MVC
1173
1174
1175 MS_U32 u32RegESRptrHi = HVD_REG_ESB_RPTR_H(u32RB);
1176
1177 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1178
1179
1180
1181 #ifdef VDEC3
1182 if ((0 == pCtrl->u32BBUId))
1183 #else
1184 if ((0 == u8TaskId))
1185 #endif
1186 {
1187 u32RegESRptrHi = HVD_REG_ESB_RPTR_H(u32RB);
1188
1189 }
1190 #ifdef VDEC3
1191 else if (1 == pCtrl->u32BBUId)
1192 #else
1193 else if (1 == u8TaskId)
1194 #endif
1195 {
1196 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS2(u32RB);
1197 }
1198 #ifdef VDEC3
1199 else if (2 == pCtrl->u32BBUId)
1200 #else
1201 else if (2 == u8TaskId)
1202 #endif
1203 {
1204 if(isEVD)
1205 u32RegESRptrHi = EVD_REG_ESB_RPTR_H_BS3;
1206 else
1207 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS5;
1208 }
1209 #ifdef VDEC3
1210 else if (3 == pCtrl->u32BBUId)
1211 #else
1212 else if (3 == u8TaskId)
1213 #endif
1214 {
1215 if(isEVD)
1216 u32RegESRptrHi = EVD_REG_ESB_RPTR_H_BS4;
1217 else
1218 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS6;
1219 }
1220 else
1221 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1222
1223
1224 return u32RegESRptrHi;
1225
1226 }
1227
1228
1229
1230
_HVD_EX_Get_NAL_TBL_ST_ADDR_L(MS_U32 u32Id)1231 static MS_U32 _HVD_EX_Get_NAL_TBL_ST_ADDR_L(MS_U32 u32Id)
1232 {
1233 #if (HVD_ENABLE_MVC || (!VDEC3))
1234 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1235 #endif
1236 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1237 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1238 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1239 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1240
1241 #if HVD_ENABLE_MVC
1242 if(HAL_HVD_EX_CheckMVCID(u32Id))
1243 {
1244 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1245 }
1246 #endif /// HVD_ENABLE_MVC
1247
1248
1249 MS_U32 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L(u32RB);
1250
1251 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1252
1253
1254
1255 #ifdef VDEC3
1256 if ((0 == pCtrl->u32BBUId))
1257 #else
1258 if ((0 == u8TaskId))
1259 #endif
1260 {
1261 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L(u32RB);
1262
1263 }
1264 #ifdef VDEC3
1265 else if (1 == pCtrl->u32BBUId)
1266 #else
1267 else if (1 == u8TaskId)
1268 #endif
1269 {
1270 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB);
1271 }
1272 #ifdef VDEC3
1273 else if (2 == pCtrl->u32BBUId)
1274 #else
1275 else if (2 == u8TaskId)
1276 #endif
1277 {
1278 if(isEVD)
1279 u32RegNalTblAddrLo = EVD_REG_NAL_TBL_ST_ADDR_L_BS3;
1280 else
1281 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS5;
1282 }
1283 #ifdef VDEC3
1284 else if (3 == pCtrl->u32BBUId)
1285 #else
1286 else if (3 == u8TaskId)
1287 #endif
1288 {
1289 if(isEVD)
1290 u32RegNalTblAddrLo = EVD_REG_NAL_TBL_ST_ADDR_L_BS4;
1291 else
1292 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS6;
1293 }
1294 else
1295 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1296
1297
1298 return u32RegNalTblAddrLo;
1299
1300 }
1301
1302
_HVD_EX_Get_NAL_TBL_ST_ADDR_H(MS_U32 u32Id)1303 static MS_U32 _HVD_EX_Get_NAL_TBL_ST_ADDR_H(MS_U32 u32Id)
1304 {
1305 #if (HVD_ENABLE_MVC || (!VDEC3))
1306 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1307 #endif
1308 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1309 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1310 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1311 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1312
1313 #if HVD_ENABLE_MVC
1314 if(HAL_HVD_EX_CheckMVCID(u32Id))
1315 {
1316 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1317 }
1318 #endif /// HVD_ENABLE_MVC
1319
1320
1321 MS_U32 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H(u32RB);
1322
1323 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1324
1325
1326
1327 #ifdef VDEC3
1328 if ((0 == pCtrl->u32BBUId))
1329 #else
1330 if ((0 == u8TaskId))
1331 #endif
1332 {
1333 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H(u32RB);
1334
1335 }
1336 #ifdef VDEC3
1337 else if (1 == pCtrl->u32BBUId)
1338 #else
1339 else if (1 == u8TaskId)
1340 #endif
1341 {
1342 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB);
1343 }
1344 #ifdef VDEC3
1345 else if (2 == pCtrl->u32BBUId)
1346 #else
1347 else if (2 == u8TaskId)
1348 #endif
1349 {
1350 if(isEVD)
1351 u32RegNalTblAddrHi = EVD_REG_NAL_TBL_ST_ADDR_H_BS3;
1352 else
1353 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS5;
1354 }
1355 #ifdef VDEC3
1356 else if (3 == pCtrl->u32BBUId)
1357 #else
1358 else if (3 == u8TaskId)
1359 #endif
1360 {
1361 if(isEVD)
1362 u32RegNalTblAddrHi = EVD_REG_NAL_TBL_ST_ADDR_H_BS4;
1363 else
1364 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS6;
1365 }
1366 else
1367 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1368
1369
1370 return u32RegNalTblAddrHi;
1371
1372 }
1373
_HVD_EX_Get_NAL_TAB_LEN(MS_U32 u32Id)1374 static MS_U32 _HVD_EX_Get_NAL_TAB_LEN(MS_U32 u32Id)
1375 {
1376 #if (HVD_ENABLE_MVC || (!VDEC3))
1377 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1378 #endif
1379 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1380 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1381 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1382 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1383
1384 #if HVD_ENABLE_MVC
1385 if(HAL_HVD_EX_CheckMVCID(u32Id))
1386 {
1387 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1388 }
1389 #endif /// HVD_ENABLE_MVC
1390
1391
1392 MS_U32 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN(u32RB);
1393
1394 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1395
1396
1397
1398 #ifdef VDEC3
1399 if ((0 == pCtrl->u32BBUId))
1400 #else
1401 if ((0 == u8TaskId))
1402 #endif
1403 {
1404 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN(u32RB);
1405
1406 }
1407 #ifdef VDEC3
1408 else if (1 == pCtrl->u32BBUId)
1409 #else
1410 else if (1 == u8TaskId)
1411 #endif
1412 {
1413 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS2(u32RB);
1414 }
1415 #ifdef VDEC3
1416 else if (2 == pCtrl->u32BBUId)
1417 #else
1418 else if (2 == u8TaskId)
1419 #endif
1420 {
1421 if(isEVD)
1422 u32RegNalTblLen = EVD_REG_NAL_TAB_LEN_BS3;
1423 else
1424 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS5;
1425 }
1426 #ifdef VDEC3
1427 else if (3 == pCtrl->u32BBUId)
1428 #else
1429 else if (3 == u8TaskId)
1430 #endif
1431 {
1432 if(isEVD)
1433 u32RegNalTblLen = EVD_REG_NAL_TAB_LEN_BS4;
1434 else
1435 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS6;
1436 }
1437 else
1438 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1439
1440
1441 return u32RegNalTblLen;
1442
1443 }
1444
1445
1446
_HVD_EX_Get_ESB_ST_ADDR_L(MS_U32 u32Id)1447 static MS_U32 _HVD_EX_Get_ESB_ST_ADDR_L(MS_U32 u32Id)
1448 {
1449 #if (HVD_ENABLE_MVC || (!VDEC3))
1450 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1451 #endif
1452 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1453 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1454 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1455 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1456
1457 #if HVD_ENABLE_MVC
1458 if(HAL_HVD_EX_CheckMVCID(u32Id))
1459 {
1460 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1461 }
1462 #endif /// HVD_ENABLE_MVC
1463
1464
1465 MS_U32 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L(u32RB);
1466
1467 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1468
1469
1470
1471 #ifdef VDEC3
1472 if ((0 == pCtrl->u32BBUId))
1473 #else
1474 if ((0 == u8TaskId))
1475 #endif
1476 {
1477 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L(u32RB);
1478
1479 }
1480 #ifdef VDEC3
1481 else if (1 == pCtrl->u32BBUId)
1482 #else
1483 else if (1 == u8TaskId)
1484 #endif
1485 {
1486 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS2(u32RB);
1487 }
1488 #ifdef VDEC3
1489 else if (2 == pCtrl->u32BBUId)
1490 #else
1491 else if (2 == u8TaskId)
1492 #endif
1493 {
1494 if(isEVD)
1495 u32RegEsbAddrLo = EVD_REG_ESB_ST_ADDR_L_BS3;
1496 else
1497 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS5;
1498 }
1499 #ifdef VDEC3
1500 else if (3 == pCtrl->u32BBUId)
1501 #else
1502 else if (3 == u8TaskId)
1503 #endif
1504 {
1505 if(isEVD)
1506 u32RegEsbAddrLo = EVD_REG_ESB_ST_ADDR_L_BS4;
1507 else
1508 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS6;
1509 }
1510 else
1511 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1512
1513
1514 return u32RegEsbAddrLo;
1515
1516 }
1517
1518
_HVD_EX_Get_ESB_ST_ADDR_H(MS_U32 u32Id)1519 static MS_U32 _HVD_EX_Get_ESB_ST_ADDR_H(MS_U32 u32Id)
1520 {
1521 #if (HVD_ENABLE_MVC || (!VDEC3))
1522 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1523 #endif
1524 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1525 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1526 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1527 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1528
1529 #if HVD_ENABLE_MVC
1530 if(HAL_HVD_EX_CheckMVCID(u32Id))
1531 {
1532 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1533 }
1534 #endif /// HVD_ENABLE_MVC
1535
1536
1537 MS_U32 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H(u32RB);
1538
1539 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1540
1541
1542
1543 #ifdef VDEC3
1544 if ((0 == pCtrl->u32BBUId))
1545 #else
1546 if ((0 == u8TaskId))
1547 #endif
1548 {
1549 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H(u32RB);
1550
1551 }
1552 #ifdef VDEC3
1553 else if (1 == pCtrl->u32BBUId)
1554 #else
1555 else if (1 == u8TaskId)
1556 #endif
1557 {
1558 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS2(u32RB);
1559 }
1560 #ifdef VDEC3
1561 else if (2 == pCtrl->u32BBUId)
1562 #else
1563 else if (2 == u8TaskId)
1564 #endif
1565 {
1566 if(isEVD)
1567 u32RegEsbAddrHi = EVD_REG_ESB_ST_ADDR_H_BS3;
1568 else
1569 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS5;
1570 }
1571 #ifdef VDEC3
1572 else if (3 == pCtrl->u32BBUId)
1573 #else
1574 else if (3 == u8TaskId)
1575 #endif
1576 {
1577 if(isEVD)
1578 u32RegEsbAddrHi = EVD_REG_ESB_ST_ADDR_H_BS4;
1579 else
1580 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS6;
1581 }
1582 else
1583 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1584
1585
1586 return u32RegEsbAddrHi;
1587
1588 }
1589
1590
1591
_HVD_EX_Get_ESB_LENGTH_L(MS_U32 u32Id)1592 static MS_U32 _HVD_EX_Get_ESB_LENGTH_L(MS_U32 u32Id)
1593 {
1594 #if (HVD_ENABLE_MVC || (!VDEC3))
1595 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1596 #endif
1597 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1598 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1599 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1600 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1601
1602 #if HVD_ENABLE_MVC
1603 if(HAL_HVD_EX_CheckMVCID(u32Id))
1604 {
1605 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1606 }
1607 #endif /// HVD_ENABLE_MVC
1608
1609
1610 MS_U32 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L(u32RB);
1611
1612 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1613
1614
1615
1616 #ifdef VDEC3
1617 if ((0 == pCtrl->u32BBUId))
1618 #else
1619 if ((0 == u8TaskId))
1620 #endif
1621 {
1622 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L(u32RB);
1623
1624 }
1625 #ifdef VDEC3
1626 else if (1 == pCtrl->u32BBUId)
1627 #else
1628 else if (1 == u8TaskId)
1629 #endif
1630 {
1631 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS2(u32RB);
1632 }
1633 #ifdef VDEC3
1634 else if (2 == pCtrl->u32BBUId)
1635 #else
1636 else if (2 == u8TaskId)
1637 #endif
1638 {
1639 if(isEVD)
1640 u32RegEsbLenLo = EVD_REG_ESB_LENGTH_L_BS3;
1641 else
1642 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS5;
1643 }
1644 #ifdef VDEC3
1645 else if (3 == pCtrl->u32BBUId)
1646 #else
1647 else if (3 == u8TaskId)
1648 #endif
1649 {
1650 if(isEVD)
1651 u32RegEsbLenLo = EVD_REG_ESB_LENGTH_L_BS4;
1652 else
1653 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS6;
1654 }
1655 else
1656 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1657
1658
1659 return u32RegEsbLenLo;
1660
1661 }
1662
1663
_HVD_EX_Get_ESB_LENGTH_H(MS_U32 u32Id)1664 static MS_U32 _HVD_EX_Get_ESB_LENGTH_H(MS_U32 u32Id)
1665 {
1666 #if (HVD_ENABLE_MVC || (!VDEC3))
1667 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1668 #endif
1669 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1670 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1671 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1672 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1673
1674 #if HVD_ENABLE_MVC
1675 if(HAL_HVD_EX_CheckMVCID(u32Id))
1676 {
1677 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1678 }
1679 #endif /// HVD_ENABLE_MVC
1680
1681
1682 MS_U32 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H(u32RB);
1683
1684 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1685
1686
1687
1688 #ifdef VDEC3
1689 if ((0 == pCtrl->u32BBUId))
1690 #else
1691 if ((0 == u8TaskId))
1692 #endif
1693 {
1694 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H(u32RB);
1695
1696 }
1697 #ifdef VDEC3
1698 else if (1 == pCtrl->u32BBUId)
1699 #else
1700 else if (1 == u8TaskId)
1701 #endif
1702 {
1703 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS2(u32RB);
1704 }
1705 #ifdef VDEC3
1706 else if (2 == pCtrl->u32BBUId)
1707 #else
1708 else if (2 == u8TaskId)
1709 #endif
1710 {
1711 if(isEVD)
1712 u32RegEsbLenHi = EVD_REG_ESB_LENGTH_H_BS3;
1713 else
1714 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS5;
1715 }
1716 #ifdef VDEC3
1717 else if (3 == pCtrl->u32BBUId)
1718 #else
1719 else if (3 == u8TaskId)
1720 #endif
1721 {
1722 if(isEVD)
1723 u32RegEsbLenHi = EVD_REG_ESB_LENGTH_H_BS4;
1724 else
1725 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS6;
1726 }
1727 else
1728 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1729
1730
1731 return u32RegEsbLenHi;
1732
1733 }
1734
1735
_HVD_EX_Get_MIF_BBU(MS_U32 u32Id)1736 static MS_U32 _HVD_EX_Get_MIF_BBU(MS_U32 u32Id)
1737 {
1738 #if (HVD_ENABLE_MVC || (!VDEC3))
1739 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1740 #endif
1741 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1742 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1743 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1744 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1745
1746 #if HVD_ENABLE_MVC
1747 if(HAL_HVD_EX_CheckMVCID(u32Id))
1748 {
1749 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1750 }
1751 #endif /// HVD_ENABLE_MVC
1752
1753
1754 MS_U32 u32RegMIFBBU = HVD_REG_MIF_BBU(u32RB);
1755
1756 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1757
1758
1759
1760 #ifdef VDEC3
1761 if ((0 == pCtrl->u32BBUId))
1762 #else
1763 if ((0 == u8TaskId))
1764 #endif
1765 {
1766 u32RegMIFBBU = HVD_REG_MIF_BBU(u32RB);
1767
1768 }
1769 #ifdef VDEC3
1770 else if (1 == pCtrl->u32BBUId)
1771 #else
1772 else if (1 == u8TaskId)
1773 #endif
1774 {
1775 u32RegMIFBBU = HVD_REG_MIF_BBU_BS2(u32RB);
1776 }
1777 #ifdef VDEC3
1778 else if (2 == pCtrl->u32BBUId)
1779 #else
1780 else if (2 == u8TaskId)
1781 #endif
1782 {
1783 if(isEVD)
1784 u32RegMIFBBU = EVD_REG_MIF_BBU_BS3;
1785 else
1786 u32RegMIFBBU = HVD_REG_MIF_BBU_BS5;
1787 }
1788 #ifdef VDEC3
1789 else if (3 == pCtrl->u32BBUId)
1790 #else
1791 else if (3 == u8TaskId)
1792 #endif
1793 {
1794 if(isEVD)
1795 u32RegMIFBBU = EVD_REG_MIF_BBU_BS4;
1796 else
1797 u32RegMIFBBU = HVD_REG_MIF_BBU_BS6;
1798 }
1799 else
1800 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1801
1802
1803 return u32RegMIFBBU;
1804
1805 }
1806
1807
1808
_HVD_EX_GetESWritePtr(MS_U32 u32Id)1809 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
1810 {
1811 MS_U32 u32Data = 0;
1812 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1813 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1814
1815 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1816 {
1817 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
1818
1819 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
1820 {
1821 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
1822
1823 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
1824 }
1825 }
1826 else
1827 {
1828 #if HVD_ENABLE_MVC
1829 MS_U8 u8ViewIdx = 0;
1830 if(HAL_HVD_EX_CheckMVCID(u32Id))
1831 {
1832 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1833 }
1834 if(u8ViewIdx != 0) /// 2nd ES ptr.
1835 {
1836 u32Data = pShm->u32ES2WritePtr;
1837 }
1838 else
1839 {
1840 u32Data = pShm->u32ESWritePtr;
1841 }
1842 #else
1843 u32Data = pShm->u32ESWritePtr;
1844 #endif
1845 }
1846
1847 return u32Data;
1848 }
1849
1850 #define NAL_UNIT_LEN_BITS 21
1851 #define NAL_UNIT_OFT_BITS 30
1852 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
1853 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
1854 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
1855
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)1856 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
1857 {
1858 MS_U32 u32Data = 0;
1859 MS_U8 u8TaskId = 0;
1860 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1861 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1862 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1863 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1864 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
1865
1866 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1867 #if HVD_ENABLE_MVC
1868 if(HAL_HVD_EX_CheckMVCID(u32Id))
1869 {
1870 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1871 }
1872 #endif /// HVD_ENABLE_MVC
1873
1874 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
1875 {
1876 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
1877 {
1878 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1879 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1880 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
1881 MS_U32 *u32Adr;
1882 MS_U32 u32Tmp;
1883
1884 if (u16ReadPtr == u16WritePtr)
1885 {
1886 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1887 }
1888 else
1889 {
1890 if (u16ReadPtr)
1891 u16ReadPtr--;
1892 else
1893 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1894
1895 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1896
1897 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1898 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1899 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1900 u32Data = u32Data | u32Tmp;
1901
1902 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1903 //while(1);
1904 }
1905 goto EXIT;
1906 }
1907 // set reg_poll_nal_rptr 0
1908 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1909 // set reg_poll_nal_rptr 1
1910 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1911
1912
1913
1914
1915
1916 // read reg_nal_rptr_hi
1917
1918 u32Data = _HVD_Read2Byte(_HVD_EX_Get_REG_ES_RPTR_L(u32Id)) & 0xFFC0;
1919 u32Data >>= 6;
1920 u32Data |= _HVD_Read2Byte(_HVD_EX_Get_REG_ES_RPTR_H(u32Id)) << 10;
1921
1922 u32Data <<= 3; // unit
1923
1924 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1925 {
1926 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1927
1928 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1929 {
1930 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1931 u32Data = u32ESWptr;
1932 }
1933 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1934 {
1935 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1936 u32Data = u32ESWptr;
1937 }
1938 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1939 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1940 {
1941 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1942 u32Data = u32ESWptr;
1943 }
1944 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1945 && ((u32Data - u32ESWptr) < 32)
1946 && (pCtrl->u32FlushRstPtr == 1))
1947 {
1948 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1949 u32Data = u32ESWptr;
1950 }
1951 }
1952
1953 // remove illegal pointer
1954 #if 1
1955 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1956 {
1957 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1958
1959 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1960 (u32PacketStaddr <
1961 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1962 {
1963 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1964 u32Data = pCtrl->u32LastESRptr;
1965 }
1966 }
1967 #endif
1968 }
1969 else
1970 {
1971 #if HVD_ENABLE_MVC
1972 MS_U8 u8ViewIdx = 0;
1973 if(HAL_HVD_EX_CheckMVCID(u32Id))
1974 {
1975 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1976 }
1977 if(u8ViewIdx != 0) /// 2nd ES ptr.
1978 {
1979 u32Data = pShm->u32ES2ReadPtr;
1980 }
1981 else
1982 {
1983 u32Data = pShm->u32ESReadPtr;
1984 }
1985 #else
1986 u32Data = pShm->u32ESReadPtr;
1987 #endif
1988 }
1989
1990 EXIT:
1991
1992 pCtrl->u32LastESRptr = u32Data;
1993
1994 return u32Data;
1995 }
1996
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1997 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1998 {
1999 MS_U16 u16TimeOut = 0xFFFF;
2000 MS_BOOL bResult = FALSE;
2001
2002 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
2003
2004 while (--u16TimeOut)
2005 {
2006 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
2007 {
2008 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
2009 break;
2010 }
2011 }
2012
2013 return bResult;
2014 }
2015
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)2016 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
2017 {
2018 MS_U16 u16TimeOut = 0xFFFF;
2019 MS_BOOL bResult = FALSE;
2020 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2021
2022 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
2023
2024 #if HVD_ENABLE_MVC
2025 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
2026 {
2027 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
2028 }
2029 #endif /// HVD_ENABLE_MVC
2030
2031 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
2032
2033 while (--u16TimeOut)
2034 {
2035 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
2036 {
2037 u32Cmd |= (u8TaskId << 24);
2038 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
2039 break;
2040 }
2041 }
2042 return bResult;
2043 }
2044
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)2045 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
2046 {
2047 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2048 #ifdef VDEC3
2049 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
2050 MS_BOOL IsSent = FALSE;
2051 MS_BOOL IsMailBox = FALSE;
2052 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2053
2054 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
2055 {
2056 do {
2057 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
2058 if (!SentRet)
2059 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2060 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2061 break;
2062 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2063 IsSent = TRUE;
2064 break;
2065 }
2066 else if (HVD_GetSysTime_ms() > u32timeout)
2067 {
2068 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2069 break;
2070 }
2071 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2072 }
2073 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
2074 {
2075 do {
2076 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
2077 if (!SentRet)
2078 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2079 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2080 break;
2081 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2082 IsSent = TRUE;
2083 break;
2084 }
2085 else if (HVD_GetSysTime_ms() > u32timeout)
2086 {
2087 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2088 break;
2089 }
2090 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2091 }
2092 if (!IsSent) {
2093 IsMailBox = TRUE;
2094 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2095 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
2096 #else
2097 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
2098 #endif
2099 {
2100 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2101 if (HVD_GetSysTime_ms() > u32timeout)
2102 {
2103 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2104 return E_HVD_RETURN_TIMEOUT;
2105 }
2106 #endif
2107
2108 #if 0
2109 if (u32Cmd == E_HVD_CMD_STOP)
2110 {
2111 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2112 #if HVD_ENABLE_MVC
2113 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
2114 {
2115 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
2116 }
2117 #endif /// HVD_ENABLE_MVC
2118 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
2119
2120 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
2121 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
2122
2123 return E_HVD_RETURN_SUCCESS;
2124 }
2125 #endif
2126
2127 if(u32Cmd < E_DUAL_CMD_BASE)
2128 {
2129 //_HVD_EX_GetPC();
2130 HAL_HVD_EX_Dump_FW_Status(u32Id);
2131 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
2132 }
2133 }
2134
2135 #ifdef VDEC3
2136 }
2137 IsSent = FALSE;
2138 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2139 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
2140 {
2141 do {
2142 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
2143 if (!SentRet)
2144 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2145 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2146 break;
2147 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
2148 IsSent = TRUE;
2149 break;
2150 }
2151 else if (HVD_GetSysTime_ms() > u32timeout)
2152 {
2153 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2154 break;
2155 }
2156 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2157 }
2158 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
2159 {
2160 do {
2161 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
2162 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2163 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2164 }
2165 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2166 break;
2167 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
2168 IsSent = TRUE;
2169 break;
2170 }
2171 else if (HVD_GetSysTime_ms() > u32timeout)
2172 {
2173 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2174 break;
2175 }
2176 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2177 }
2178 if (!IsSent)
2179 {
2180 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2181 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
2182 #else
2183 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2184
2185 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
2186 #endif
2187 {
2188 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2189 if (HVD_GetSysTime_ms() > u32timeout)
2190 {
2191 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
2192 return E_HVD_RETURN_TIMEOUT;
2193 }
2194 #endif
2195 if(u32Cmd < E_DUAL_CMD_BASE)
2196 {
2197 //_HVD_EX_GetPC();
2198 HAL_HVD_EX_Dump_FW_Status(u32Id);
2199 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
2200 }
2201 }
2202 #ifdef VDEC3
2203 }
2204 else
2205 {
2206 HAL_HVD_EX_FlushMemory();
2207 }
2208 #endif
2209 return E_HVD_RETURN_SUCCESS;
2210 }
2211
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)2212 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
2213 {
2214 #if HAL_HVD_ENABLE_MIU_PROTECT
2215 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
2216 //_HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
2217 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
2218 #if SUPPORT_EVD
2219 _HVD_MIU_SetReqMask(EVD_RW1, bEnable);
2220 _HVD_MIU_SetReqMask(EVD_RW2, bEnable);
2221 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
2222 #endif
2223 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
2224 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
2225 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
2226 HAL_VPU_EX_MIU_RW_Protect(bEnable);
2227 //HVD_Delay_ms(1);
2228 #endif
2229 return;
2230 }
2231
_HVD_EX_SetBufferAddr(MS_U32 u32Id)2232 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
2233 {
2234 MS_U16 u16Reg = 0;
2235 MS_VIRT u32StAddr = 0;
2236 #ifdef VDEC3
2237 MS_U32 u32Length = 0;
2238 #endif
2239 MS_U8 u8BitMiuSel = 0;
2240 MS_U8 u8CodeMiuSel = 0;
2241 MS_U8 u8FBMiuSel = 0;
2242 MS_U8 u8TmpMiuSel = 0;
2243
2244 MS_U32 u32BitStartOffset;
2245 MS_U32 u32CodeStartOffset;
2246 MS_U32 u32FBStartOffset;
2247
2248 #ifndef VDEC3
2249 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2250 #endif
2251 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2252 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2253 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
2254
2255 _HAL_HVD_Entry();
2256
2257 if (pCtrl == NULL)
2258 {
2259 _HAL_HVD_Return();
2260 }
2261
2262 MS_BOOL bIsEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
2263 MS_BOOL bESBufferAlreadySet = FALSE;
2264 VPU_EX_TaskInfo taskInfo;
2265 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2266
2267 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
2268
2269 bESBufferAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
2270
2271
2272
2273 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
2274 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
2275 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
2276
2277 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
2278 (u8BitMiuSel << VDEC_BS_MIUSEL) |
2279 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
2280 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
2281 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
2282 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
2283 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
2284 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
2285 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
2286 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
2287 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
2288
2289 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2290 {
2291 // ES buffer
2292 #ifdef VDEC3
2293 if(pCtrl->bShareBBU)
2294 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
2295 else
2296 #endif
2297 u32StAddr = u32BitStartOffset;
2298
2299 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
2300
2301 #ifdef VDEC3
2302 if (!_HAL_EX_BBU_VP8_InUsed())
2303 #endif
2304 {
2305 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
2306
2307 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
2308 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
2309
2310 #ifdef VDEC3
2311 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
2312 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
2313 #else
2314 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2315 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2316 #endif
2317
2318 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
2319 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
2320 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
2321 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
2322 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
2323 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
2324 }
2325
2326 _HAL_HVD_Return();
2327 }
2328
2329 // ES buffer
2330 #ifdef VDEC3
2331 if(!pCtrl->bShareBBU || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
2332 {
2333 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2334 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
2335 }
2336 else
2337 {
2338 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
2339 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
2340 }
2341 #else
2342 u32StAddr = u32BitStartOffset;
2343 #endif
2344
2345 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
2346
2347 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
2348
2349 #ifdef VDEC3
2350 if (!bESBufferAlreadySet)
2351 {
2352 _HVD_Write2Byte(_HVD_EX_Get_ESB_ST_ADDR_L(u32Id), HVD_LWORD(u32StAddr >> 3));
2353 _HVD_Write2Byte(_HVD_EX_Get_ESB_ST_ADDR_H(u32Id), HVD_HWORD(u32StAddr >> 3));
2354
2355 _HVD_Write2Byte(_HVD_EX_Get_ESB_LENGTH_L(u32Id), HVD_LWORD(u32Length));
2356 _HVD_Write2Byte(_HVD_EX_Get_ESB_LENGTH_H(u32Id), HVD_HWORD(u32Length));
2357 }
2358 #else
2359 if (0 == u8TaskId)
2360 {
2361 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
2362 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
2363
2364 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2365 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2366 }
2367 else
2368 {
2369 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2370 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2371
2372 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2373 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2374 }
2375 #endif
2376
2377 // others
2378 #ifdef VDEC3
2379 if (!bESBufferAlreadySet)
2380 {
2381 u16Reg = _HVD_Read2Byte(_HVD_EX_Get_MIF_BBU(u32Id));
2382
2383 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2384 {
2385 if (pCtrl->u32BBUId == 0)
2386 u16Reg |= HVD_REG_BBU_TSP_INPUT;
2387 else if (pCtrl->u32BBUId == 1)
2388 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2389 else if (pCtrl->u32BBUId == 2)
2390 {
2391 if(bIsEVD)
2392 u16Reg |= EVD_REG_BBU_TSP_INPUT_BS3;
2393 else
2394 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS5;
2395 }
2396 else
2397 {
2398 if(bIsEVD)
2399 u16Reg |= EVD_REG_BBU_TSP_INPUT_BS4;
2400 else
2401 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS6;
2402 }
2403 }
2404 else
2405 {
2406 if (pCtrl->u32BBUId == 0)
2407 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
2408 else if (pCtrl->u32BBUId == 1)
2409 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2410 else if (pCtrl->u32BBUId == 2)
2411 {
2412 if(bIsEVD)
2413 u16Reg &= ~EVD_REG_BBU_TSP_INPUT_BS3;
2414 else
2415 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS5;
2416 }
2417 else
2418 {
2419 if(bIsEVD)
2420 u16Reg &= ~EVD_REG_BBU_TSP_INPUT_BS4;
2421 else
2422 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS6;
2423 }
2424 }
2425
2426 // do not set parsing setting in DRV, and we set it in FW (hvd_switch_bbu)
2427 if (pCtrl->u32BBUId == 0)
2428 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
2429 else if(pCtrl->u32BBUId == 1)
2430 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2431 else if(pCtrl->u32BBUId == 2)
2432 {
2433 if(bIsEVD)
2434 u16Reg &= ~EVD_REG_BBU_PASER_MASK_BS3;
2435 else
2436 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS5;
2437 }
2438 else
2439 {
2440 if(bIsEVD)
2441 u16Reg &= ~EVD_REG_BBU_PASER_MASK_BS4;
2442 else
2443 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS6;
2444 }
2445
2446 if (pCtrl->u32BBUId == 0)
2447 {
2448 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
2449 }
2450 else if (pCtrl->u32BBUId == 1)
2451 {
2452 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2453 }
2454 else if (pCtrl->u32BBUId == 2)
2455 {
2456 if(bIsEVD)
2457 u16Reg |= EVD_REG_BBU_AUTO_NAL_TAB_BS3;
2458 else
2459 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS5;
2460 }
2461 else
2462 {
2463 if(bIsEVD)
2464 u16Reg |= EVD_REG_BBU_AUTO_NAL_TAB_BS4;
2465 else
2466 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS6;
2467 }
2468
2469 _HVD_Write2Byte(_HVD_EX_Get_MIF_BBU(u32Id), u16Reg);
2470 }
2471 #else
2472 if (0 == u8TaskId)
2473 {
2474 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
2475
2476 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2477 {
2478 u16Reg |= HVD_REG_BBU_TSP_INPUT;
2479 }
2480 else
2481 {
2482 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
2483 }
2484
2485 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
2486
2487 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2488 {
2489 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
2490 }
2491 else // AVS or AVC
2492 {
2493 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2494 {
2495 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
2496 }
2497 else // start code remained
2498 {
2499 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
2500 }
2501 }
2502
2503 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
2504
2505 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
2506 }
2507 else
2508 {
2509 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
2510
2511 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2512 {
2513 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2514 }
2515 else
2516 {
2517 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2518 }
2519
2520 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2521
2522 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2523 {
2524 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
2525 }
2526 else // AVS or AVC
2527 {
2528 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2529 {
2530 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
2531 }
2532 else // start code remained
2533 {
2534 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
2535 }
2536 }
2537
2538 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2539
2540 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
2541 }
2542 #endif
2543
2544 #if (HVD_ENABLE_MVC)
2545 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2546 {
2547 /// Used sub stream to record sub view data.
2548 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
2549 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
2550
2551 // ES buffer
2552 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
2553
2554 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
2555 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2556 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2557
2558 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
2559 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
2560
2561 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
2562 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2563 {
2564 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2565 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
2566 }
2567 else
2568 {
2569 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2570 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
2571 }
2572 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2573 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2574 {
2575 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
2576 }
2577 else // AVS or AVC
2578 {
2579 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2580 {
2581 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
2582 }
2583 else // start code remained
2584 {
2585 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
2586 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
2587 }
2588 }
2589 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2590 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
2591 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
2592 }
2593 #endif
2594
2595 // MIF offset
2596 #if 0
2597 {
2598 MS_U16 offaddr = 0;
2599 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
2600 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2601 {
2602 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2603 }
2604 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
2605 offaddr = (MS_U16) ((u32StAddr) >> 20);
2606 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
2607 //0x1FF; // 9 bits(L + H)
2608 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
2609 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
2610 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
2611 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
2612 {
2613 u16Reg |= HVD_REG_MIF_OFFSET_H;
2614 }
2615 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
2616 }
2617 #endif
2618
2619 if (!bESBufferAlreadySet)
2620 {
2621 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
2622 }
2623
2624 _HAL_HVD_Return();
2625 }
2626
2627 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
2628 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
2629 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
2630 {
2631 MS_U16 u16Reg = 0;
2632 MS_U32 u32StAddr = 0;
2633 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2634 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2635 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
2636
2637 if(pCtrl == NULL) return;
2638
2639 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2640 {
2641 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
2642
2643 // ES buffer
2644 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2645
2646 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2647 {
2648 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2649 }
2650
2651 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
2652 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
2653
2654 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2655 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2656
2657 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
2658 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
2659 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
2660 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
2661 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
2662 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
2663
2664 return;
2665 }
2666
2667 // ES buffer
2668 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2669
2670 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2671 {
2672 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2673 }
2674
2675 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
2676
2677 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
2678 {
2679 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
2680 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
2681
2682 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2683 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2684 }
2685 else
2686 {
2687 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2688 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2689
2690 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2691 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2692 }
2693 }
2694 #endif
2695
_HVD_EX_GetESLevel(MS_U32 u32Id)2696 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
2697 {
2698 MS_U32 u32Wptr = 0;
2699 MS_U32 u32Rptr = 0;
2700 MS_U32 u32CurMBX = 0;
2701 MS_U32 u32ESsize = 0;
2702 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
2703 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2704
2705 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2706 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2707 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2708
2709 if (u32Rptr >= u32Wptr)
2710 {
2711 u32CurMBX = u32Rptr - u32Wptr;
2712 }
2713 else
2714 {
2715 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
2716 }
2717
2718 if (u32CurMBX == 0)
2719 {
2720 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2721 }
2722 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
2723 {
2724 u32Ret = E_HVD_ESB_LEVEL_OVER;
2725 }
2726 else
2727 {
2728 u32CurMBX = u32ESsize - u32CurMBX;
2729 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
2730 {
2731 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2732 }
2733 }
2734
2735 return u32Ret;
2736 }
2737
_HVD_EX_GetESQuantity(MS_U32 u32Id)2738 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
2739 {
2740 MS_U32 u32Wptr = 0;
2741 MS_U32 u32Rptr = 0;
2742 MS_U32 u32ESsize = 0;
2743 MS_U32 u32Ret = 0;
2744 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2745
2746 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2747 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2748 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2749
2750
2751 if(u32Wptr >= u32Rptr)
2752 {
2753 u32Ret = u32Wptr - u32Rptr;
2754 }
2755 else
2756 {
2757 u32Ret = u32ESsize - u32Rptr + u32Wptr;
2758 }
2759 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
2760 return u32Ret;
2761 }
2762
2763 #if 0//(HVD_ENABLE_IQMEM)
2764 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
2765 {
2766
2767 MS_U32 u32Timeout = 20000;
2768
2769 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
2770 {
2771
2772 HAL_VPU_EX_IQMemSetDAMode(TRUE);
2773
2774 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
2775
2776
2777 while (u32Timeout)
2778 {
2779
2780 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
2781 {
2782 break;
2783 }
2784 u32Timeout--;
2785 HVD_Delay_ms(1);
2786 }
2787
2788 HAL_VPU_EX_IQMemSetDAMode(FALSE);
2789
2790 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
2791
2792 if (u32Timeout==0)
2793 {
2794 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
2795 return FALSE;
2796 }
2797
2798
2799 }
2800 return TRUE;
2801 }
2802
2803 #endif
2804
2805 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2806 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2807 #else
2808 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2809 #endif
2810 {
2811 MS_U32 u32FirmVer = 0;
2812 MS_U32 u32Timeout = 20000;
2813 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2814
2815 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2816
2817 #if HVD_ENABLE_TIME_MEASURE
2818 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2819 #endif
2820
2821 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2822
2823 VPU_EX_FWCodeCfg fwCfg;
2824 VPU_EX_TaskInfo taskInfo;
2825 VPU_EX_VLCTblCfg vlcCfg;
2826 #ifdef VDEC3
2827 VPU_EX_FBCfg fbCfg;
2828 #endif
2829 VPU_EX_NDecInitPara nDecInitPara;
2830
2831 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2832 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2833 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2834 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2835 #ifdef VDEC3_FB
2836 nDecInitPara.pVLCCfg = NULL;
2837 #else
2838 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2839 {
2840 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2841 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2842 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2843 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2844 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2845 nDecInitPara.pVLCCfg = &vlcCfg;
2846 }
2847 #endif
2848 nDecInitPara.pFWCodeCfg = &fwCfg;
2849 nDecInitPara.pTaskInfo = &taskInfo;
2850 #ifdef VDEC3
2851 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2852 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2853
2854 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2855 {
2856 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2857 }
2858
2859 nDecInitPara.pFBCfg = &fbCfg;
2860 #endif
2861
2862 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2863 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2864 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2865 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2866 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2867
2868 taskInfo.u32Id = u32Id;
2869
2870 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2871 {
2872 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2873 }
2874 #ifdef VDEC3
2875 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2876 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
2877 {
2878 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2879 }
2880 #if SUPPORT_MSVP9
2881 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2882 {
2883 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2884 }
2885 #endif
2886 #if SUPPORT_G2VP9
2887 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2888 {
2889 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2890 }
2891 #endif
2892 #endif
2893 else
2894 {
2895 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2896 }
2897
2898 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2899
2900 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2901 {
2902 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2903 }
2904 else
2905 {
2906 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2907 }
2908 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2909
2910 #ifdef SUPPORT_EVD
2911 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2912 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2913 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2914 #endif
2915
2916 if(TRUE == HVD_EX_GetRstFlag())
2917 {
2918 //Delete task for Rst
2919 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2920 {
2921 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2922 }
2923 HVD_EX_SetRstFlag(FALSE);
2924 }
2925
2926 #if 0//(HVD_ENABLE_IQMEM)
2927 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2928 #endif
2929
2930 #ifdef VDEC3
2931 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2932 #else
2933 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2934 #endif
2935 {
2936 HVD_EX_MSG_ERR("Task create fail!\n");
2937
2938 return FALSE;
2939 }
2940
2941 while (u32Timeout)
2942 {
2943 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2944
2945 if (u32FirmVer != 0)
2946 {
2947 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2948 break;
2949 }
2950 u32Timeout--;
2951 HVD_Delay_ms(1);
2952 }
2953
2954 #ifdef VDEC3_FB
2955 #if HVD_ENABLE_RV_FEATURE
2956 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2957
2958 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2959 {
2960 if(pShm->u32RM_VLCTableAddr == 0) {
2961 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2962 }
2963 else
2964 {
2965 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2966 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2967 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2968 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2969 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2970 nDecInitPara.pVLCCfg = &vlcCfg;
2971 }
2972 }
2973
2974 if (nDecInitPara.pVLCCfg)
2975 {
2976 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2977 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2978 {
2979 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2980 return FALSE;
2981 }
2982 }
2983 #endif
2984 #endif
2985 if (u32Timeout > 0)
2986 {
2987 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2988
2989 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2990
2991 #ifdef VDEC3
2992 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2993 {
2994 case E_HVD_INIT_HW_AVC:
2995 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2996 break;
2997 case E_HVD_INIT_HW_AVS:
2998 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2999 break;
3000 case E_HVD_INIT_HW_RM:
3001 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
3002 break;
3003 case E_HVD_INIT_HW_MVC:
3004 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
3005 break;
3006 case E_HVD_INIT_HW_VP8:
3007 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
3008 break;
3009 case E_HVD_INIT_HW_MJPEG:
3010 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
3011 break;
3012 case E_HVD_INIT_HW_VP6:
3013 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
3014 break;
3015 case E_HVD_INIT_HW_HEVC:
3016 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
3017 break;
3018 case E_HVD_INIT_HW_VP9:
3019 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
3020 break;
3021 case E_HVD_INIT_HW_HEVC_DV:
3022 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
3023 break;
3024 default:
3025 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
3026 break;
3027 }
3028 #endif
3029
3030 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
3031 }
3032 else
3033 {
3034 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
3035 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
3036
3037 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
3038 {
3039 HVD_EX_MSG_ERR("Task delete fail!\n");
3040 }
3041
3042 return FALSE;
3043 }
3044
3045
3046
3047 #if 0//(HVD_ENABLE_IQMEM)
3048
3049 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
3050 {
3051
3052 HAL_HVD_EX_IQMem_Init(u32Id);
3053 }
3054 else{
3055 HVD_EX_MSG_DBG("not support IQMEM\n");
3056 }
3057 #endif
3058
3059
3060
3061
3062
3063
3064 #if HVD_ENABLE_TIME_MEASURE
3065 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
3066 #endif
3067
3068 return TRUE;
3069 }
3070
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)3071 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
3072 {
3073 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3074 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3075 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
3076 {
3077 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
3078 }
3079 else
3080 {
3081 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3082 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3083 }
3084 }
3085
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)3086 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
3087 {
3088 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3089 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3090
3091 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
3092 {
3093 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
3094 }
3095 else
3096 {
3097 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3098 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3099 }
3100 }
3101
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)3102 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
3103 {
3104 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3105 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3106
3107 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
3108 {
3109 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
3110 {
3111 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
3112 }
3113 }
3114 else
3115 {
3116 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
3117 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
3118 }
3119 }
3120
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)3121 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
3122 {
3123 MS_VIRT u32PTSWptr = HVD_U32_MAX;
3124 MS_VIRT u32PTSRptr = HVD_U32_MAX;
3125 MS_VIRT u32DestAddr = 0;
3126 HVD_PTS_Entry PTSEntry;
3127 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3128 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3129 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3130
3131 // update R & W ptr
3132 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
3133
3134 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
3135
3136 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
3137 {
3138 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
3139 (MS_U32) MAX_PTS_TABLE_SIZE);
3140 return E_HVD_RETURN_FAIL;
3141 }
3142
3143 // check queue is full or not
3144 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
3145 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
3146
3147 if (u32PTSWptr == u32PTSRptr)
3148 {
3149 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
3150 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
3151 return E_HVD_RETURN_FAIL;
3152 }
3153
3154 // add one PTS entry
3155 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
3156 PTSEntry.u32ID_L = pInfo->u32ID_L;
3157 PTSEntry.u32ID_H = pInfo->u32ID_H;
3158 PTSEntry.u32PTS = pInfo->u32TimeStamp;
3159
3160 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
3161
3162 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
3163
3164 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
3165
3166 HAL_HVD_EX_FlushMemory();
3167
3168 // update Write ptr
3169 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
3170
3171 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
3172
3173 return E_HVD_RETURN_SUCCESS;
3174 }
3175
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)3176 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
3177 {
3178 //---------------------------------------------------
3179 // item format in nal table:
3180 // reserved |borken| u32NalOffset | u32NalLen
3181 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
3182 //---------------------------------------------------
3183 MS_VIRT u32Adr = 0;
3184 MS_U32 u32BBUNewWptr = 0;
3185 MS_U8 item[8];
3186 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3187 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3188 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3189 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
3190
3191 #if HVD_ENABLE_MVC
3192 if(HAL_HVD_EX_CheckMVCID(u32Id))
3193 {
3194 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
3195 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
3196 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
3197 {
3198 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
3199 }
3200 }
3201 #endif /// HVD_ENABLE_MVC
3202
3203 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3204 {
3205 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
3206 }
3207 else
3208 {
3209 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
3210 }
3211 u32BBUNewWptr++;
3212 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
3213
3214 // prepare nal entry
3215
3216 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
3217 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3218 {
3219 // NAL len 22 bits , HEVC level5 constrain
3220 item[0] = u32NalLen & 0xff;
3221 item[1] = (u32NalLen >> 8) & 0xff;
3222 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
3223 item[3] = (u32NalOffset >> 2) & 0xff;
3224 item[4] = (u32NalOffset >> 10) & 0xff;
3225 item[5] = (u32NalOffset >> 18) & 0xff;
3226 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
3227 item[7] = 0;
3228 }
3229 else
3230 {
3231 item[0] = u32NalLen & 0xff;
3232 item[1] = (u32NalLen >> 8) & 0xff;
3233 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
3234 item[3] = (u32NalOffset >> 3) & 0xff;
3235 item[4] = (u32NalOffset >> 11) & 0xff;
3236 item[5] = (u32NalOffset >> 19) & 0xff;
3237 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
3238 item[7] = 0;
3239 }
3240
3241 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3242 {
3243 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
3244 }
3245 else
3246 {
3247 // add nal entry
3248 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
3249 }
3250
3251 HVD_memcpy((void *) u32Adr, (void *) item, 8);
3252
3253 HAL_HVD_EX_FlushMemory();
3254
3255 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
3256
3257 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3258 {
3259 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
3260 }
3261 else
3262 {
3263 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
3264 }
3265
3266 return E_HVD_RETURN_SUCCESS;
3267 }
3268
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)3269 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
3270 {
3271 MS_U8 item[8];
3272 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3273 MS_VIRT u32Adr = 0;
3274 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3275 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3276 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
3277
3278 /*
3279 printf("nal2 offset=0x%x, len=0x%x\n",
3280 u32NalOffset2, u32NalLen2);
3281 */
3282
3283 item[0] = u32NalLen2 & 0xff;
3284 item[1] = (u32NalLen2 >> 8) & 0xff;
3285 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
3286 item[3] = (u32NalOffset2 >> 3) & 0xff;
3287 item[4] = (u32NalOffset2 >> 11) & 0xff;
3288 item[5] = (u32NalOffset2 >> 19) & 0xff;
3289 item[6] = (u32NalOffset2 >> 27) & 0x07;
3290 item[7] = 0;
3291
3292 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3293 {
3294 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
3295 }
3296 else
3297 {
3298 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
3299 }
3300
3301 HVD_memcpy((void *) u32Adr, (void *) item, 8);
3302
3303 HAL_HVD_EX_FlushMemory();
3304
3305 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
3306 }
3307
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)3308 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
3309 {
3310 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3311 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3312
3313 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
3314 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
3315 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
3316 {
3317 MS_U16 i;
3318 MS_PHY u32VUIAddr;
3319 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
3320
3321 HAL_HVD_EX_ReadMemory();
3322 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
3323
3324 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
3325 {
3326 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
3327 {
3328 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
3329 }
3330 else
3331 {
3332 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
3333 }
3334 pData++;
3335 }
3336 }
3337 else
3338 {
3339 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
3340 }
3341
3342 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
3343 }
3344
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)3345 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
3346 {
3347 MS_U32 u32ReadPtr = 0;
3348 MS_U32 eRet = 0;
3349 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3350 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3351
3352 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
3353 MS_U32 u32WritePtr = 0;
3354
3355 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3356 {
3357 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
3358 }
3359 else
3360 {
3361 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
3362 }
3363
3364 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
3365
3366 if (u32WritePtr >= u32ReadPtr)
3367 {
3368 eRet = u32WritePtr - u32ReadPtr;
3369 }
3370 else
3371 {
3372 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
3373 }
3374
3375 #if 0
3376 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
3377 {
3378 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
3379 }
3380 else
3381 {
3382 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
3383 }
3384
3385 #endif
3386 return eRet;
3387 }
3388
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)3389 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
3390 {
3391 MS_U32 u32ReadPtr = 0;
3392 MS_U32 eRet = 0;
3393 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3394
3395 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
3396
3397 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
3398 {
3399 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
3400 (MS_U32) MAX_PTS_TABLE_SIZE);
3401 return 0;
3402 }
3403
3404 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3405
3406 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
3407 {
3408 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
3409 }
3410 else
3411 {
3412 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
3413 }
3414
3415 return eRet;
3416 }
3417
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)3418 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
3419 {
3420 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3421
3422 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
3423 }
3424
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)3425 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
3426 {
3427 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3428 MS_U16 u16QNum = pShm->u16DispQNumb;
3429 MS_U16 u16QPtr = pShm->u16DispQPtr;
3430 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3431
3432 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3433 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3434
3435 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
3436 static MS_BOOL bfirstTime = TRUE;
3437 if (bDolbyVision)
3438 {
3439 if (bfirstTime && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
3440 {
3441 return NULL;
3442 }
3443 else
3444 {
3445 bfirstTime = FALSE;
3446 }
3447 }
3448
3449 #if (HVD_ENABLE_MVC)
3450 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3451 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
3452 {
3453 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3454 {
3455 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
3456 MS_U16 u16UsedFrm = 0;
3457
3458 if (u16RealQPtr != u16QPtr)
3459 {
3460 if (u16RealQPtr > u16QPtr)
3461 {
3462 u16UsedFrm = u16RealQPtr - u16QPtr;
3463 }
3464 else
3465 {
3466 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
3467 }
3468 }
3469
3470 if (u16QNum > u16UsedFrm)
3471 {
3472 u16QNum -= u16UsedFrm;
3473 u16QPtr = u16RealQPtr;
3474 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
3475
3476 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
3477 {
3478 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
3479
3480 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
3481 {
3482 return NULL;
3483 }
3484 }
3485
3486 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3487 {
3488 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
3489 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3490
3491 if ((u16QPtr%2) == 0)
3492 {
3493 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
3494 if(bDolbyVision)
3495 HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData);
3496 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
3497 }
3498 else
3499 {
3500 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
3501 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
3502 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
3503 if(bDolbyVision)
3504 {
3505 HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData);
3506
3507 volatile HVD_Frm_Information *pPrevHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr-1];//BL
3508 if(DIFF(pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
3509 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp);
3510 }
3511 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
3512 }
3513
3514 u16QPtr++;
3515 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
3516 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
3517
3518 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
3519 }
3520 }
3521
3522 return NULL;
3523 }
3524
3525 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
3526 //search the next frame to display
3527 while (u16QNum > 0)
3528 {
3529 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
3530 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
3531 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3532
3533 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
3534 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3535 {
3536 /// For MVC. Output views after the pair of (base and depend) views were decoded.
3537 /// Check the depned view was initial when Output the base view.
3538 if((u16QPtr%2) == 0)
3539 {
3540 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
3541 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
3542 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
3543 {
3544 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
3545 ///printf("Return NULL.\n");
3546 return NULL;
3547 }
3548 }
3549
3550 //printf("V:%d.\n",u16QPtr);
3551 pHVDHalContext->_u16DispQPtr = u16QPtr;
3552 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
3553 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
3554 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
3555 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
3556 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
3557 }
3558
3559 u16QNum--;
3560 //go to next frame in the dispQ
3561 u16QPtr++;
3562
3563 if (u16QPtr >= pShm->u16DispQSize)
3564 {
3565 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
3566 }
3567 }
3568 }
3569 else
3570 #endif ///HVD_ENABLE_MVC
3571 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
3572 if (_HVD_EX_IsHevcInterlaceField(u32Id))
3573 {
3574 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
3575 volatile HVD_Frm_Information *pHvdFrm_first = NULL;
3576
3577 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
3578 return NULL;
3579 }
3580
3581 while (u16QNum != 0)
3582 {
3583 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3584 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3585 {
3586 if (!first_field) // second get frame, we will check at least one paired in disp queue.
3587 {
3588 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3589 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
3590 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
3591
3592 if(pHvdFrm->u8FieldType == EVD_TOP_FIELD || pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
3593 pHvdFrm->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
3594 else
3595 pHvdFrm->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
3596 return (HVD_Frm_Information *)pHvdFrm;
3597 }
3598 else // first get frame, we will check at least one paired in disp queue.
3599 {
3600 if (pHvdFrm_first == NULL)
3601 {
3602 pHvdFrm_first = pHvdFrm;
3603 }
3604 else
3605 {
3606 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3607 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
3608
3609 //After flush, we cannot get the correct field type of first field from sei, so we use second field type to decide first field type.
3610 if (pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 0xff)
3611 {
3612 if (pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV)
3613 pHvdFrm_first->u8FieldType = EVD_BOTTOM_WITH_NEXT;
3614 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_PREV)
3615 pHvdFrm_first->u8FieldType = EVD_TOP_WITH_NEXT;
3616 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_PREV)
3617 pHvdFrm_first->u8FieldType = EVD_TOP_WITH_NEXT;
3618 else if (pHvdFrm->u8FieldType == EVD_TOP_FIELD)
3619 pHvdFrm_first->u8FieldType = EVD_BOTTOM_FIELD;
3620 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_FIELD)
3621 pHvdFrm_first->u8FieldType = EVD_TOP_FIELD;
3622 else
3623 {
3624 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
3625 return NULL;
3626 }
3627 if ((pHvdFrm_first->u32ID_L >> 16) & 0x1)
3628 pHvdFrm_first->u32ID_L |= (1 << 16);
3629 else
3630 pHvdFrm_first->u32ID_L &= (~(1 << 16));
3631 }
3632 else if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV)
3633 {
3634 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV && pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_NEXT)
3635 {
3636 pHvdFrm_first->u32ID_L |= (1 << 16);
3637 pHvdFrm->u32ID_L |= (1 << 16);
3638 }
3639 else if (pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV && pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
3640 {
3641 pHvdFrm_first->u32ID_L &= (~(1 << 16));
3642 pHvdFrm->u32ID_L &= (~(1 << 16));
3643 }
3644 else
3645 {
3646 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
3647 return NULL;
3648 }
3649 }
3650 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
3651 if (pHvdFrm_first->u8FieldType == EVD_TOP_FIELD || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_NEXT)
3652 pHvdFrm_first->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
3653 else
3654 pHvdFrm_first->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
3655 return (HVD_Frm_Information *)pHvdFrm_first;
3656 }
3657 }
3658 }
3659 u16QNum--;
3660 //go to next frame in the dispQ
3661 u16QPtr++;
3662
3663 if (u16QPtr == pShm->u16DispQSize)
3664 {
3665 u16QPtr = 0; //wrap to the begin
3666 }
3667
3668 }
3669 return NULL;
3670 }
3671 else
3672 {
3673 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3674 {
3675
3676 while (u16QNum != 0)
3677 {
3678 pHvdFrm = (volatile HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
3679
3680 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3681 {
3682 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
3683 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3684 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
3685 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
3686 }
3687 u16QNum--;
3688 //go to next frame in the dispQ
3689 if (bDolbyVision)
3690 u16QPtr += 2; // single layer must in even ptr
3691 else
3692 u16QPtr++;
3693
3694 if (u16QPtr >= pShm->u16DispQSize)
3695 {
3696 u16QPtr = 0; //wrap to the begin
3697 }
3698 }
3699
3700 return NULL;
3701 }
3702
3703 //printf("Q: %d %d\n", u16QNum, u16QPtr);
3704 //search the next frame to display
3705 while (u16QNum != 0)
3706 {
3707 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3708
3709 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
3710 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3711 {
3712 pHVDHalContext->_u16DispQPtr = u16QPtr;
3713 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
3714 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
3715 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
3716 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
3717 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
3718 }
3719
3720 u16QNum--;
3721 //go to next frame in the dispQ
3722 u16QPtr++;
3723
3724 if (u16QPtr == pShm->u16DispQSize)
3725 {
3726 u16QPtr = 0; //wrap to the begin
3727 }
3728 }
3729 }
3730
3731 return NULL;
3732 }
3733
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)3734 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
3735 {
3736 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3737 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
3738 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3739 {
3740 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
3741 if(pVsyncBridgeExt != NULL)
3742 {
3743 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
3744 }
3745 }
3746 return pFrmInfoExt;
3747 }
3748
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)3749 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
3750 {
3751 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3752 MS_U64 u64Ret = 0;
3753
3754 #if SUPPORT_EVD
3755 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
3756 if (isEVD)
3757 {
3758 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
3759 }
3760 else
3761 #endif
3762 #if SUPPORT_G2VP9
3763 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3764 {
3765 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
3766 }
3767 else
3768 #endif
3769 {
3770 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
3771 }
3772
3773 return u64Ret;
3774 }
3775
3776 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)3777 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
3778 {
3779 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3780 MS_U16 u16QNum = pShm->u16DispQNumb;
3781 MS_U16 u16QPtr = pShm->u16DispQPtr;
3782 static volatile HVD_Frm_Information *pHvdFrm = NULL;
3783 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3784 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3785 MS_BOOL bMVC = FALSE;
3786 #if HVD_ENABLE_MVC
3787 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3788 #endif
3789
3790
3791 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
3792 {
3793 if (u16QNum == 1) return TRUE;
3794 }
3795
3796 while (u16QNum != 0)
3797 {
3798 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3799 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3800 {
3801 return FALSE;
3802 }
3803 u16QNum--;
3804
3805 if (bDolbyVision)
3806 u16QPtr += 2; // single layer must in even ptr
3807 else
3808 u16QPtr++;
3809
3810 if (u16QPtr >= pShm->u16DispQSize)
3811 {
3812 u16QPtr = 0; //wrap to the begin
3813 }
3814 }
3815
3816 return TRUE;
3817 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)3818 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
3819 {
3820 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3821
3822 return &(_pHVDCtrls[u8DrvId]);
3823 }
3824
_HVD_EX_GetStreamIdx(MS_U32 u32Id)3825 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
3826 {
3827 MS_U8 u8OffsetIdx = 0;
3828 MS_U8 u8SidBaseMask = 0xF0;
3829 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
3830
3831 switch (eSidBase)
3832 {
3833 case E_HAL_HVD_MAIN_STREAM_BASE:
3834 {
3835 u8OffsetIdx = 0;
3836 break;
3837 }
3838 case E_HAL_VPU_SUB_STREAM_BASE:
3839 {
3840 u8OffsetIdx = 1;
3841 break;
3842 }
3843 case E_HAL_VPU_MVC_STREAM_BASE:
3844 {
3845 u8OffsetIdx = 0;
3846 break;
3847 }
3848 #ifdef VDEC3
3849 case E_HAL_VPU_N_STREAM_BASE:
3850 {
3851 u8OffsetIdx = (u32Id>>8) & 0xF;
3852 break;
3853 }
3854 #endif
3855 default:
3856 {
3857 u8OffsetIdx = 0;
3858 break;
3859 }
3860 }
3861
3862 return u8OffsetIdx;
3863 }
3864 /*
3865 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3866 {
3867 MS_U32 i = 0;
3868 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3869 {
3870 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
3871 {
3872 return TRUE;
3873 }
3874 }
3875 return FALSE;
3876 }
3877 */
3878
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3879 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3880 {
3881 MS_PHY u32PhyAddr = 0x0;
3882 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3883
3884 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3885 {
3886 return 0;
3887 }
3888
3889 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3890
3891 if (u32PhyAddr == 0xFFFFFFFF) //boris
3892 {
3893 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3894 }
3895 else
3896 {
3897 // TEE, common + share_info
3898 u32PhyAddr += COMMON_AREA_SIZE;
3899 }
3900
3901 return MsOS_PA2KSEG1(u32PhyAddr);
3902 }
3903
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3904 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3905 {
3906 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3907 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3908
3909 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3910 {
3911 return 0;
3912 }
3913
3914 MS_PHY u32PhyAddr = 0x0;
3915 #if 0
3916 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3917
3918 if (u32PhyAddr == 0xFFFFFFFF)
3919 {
3920 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3921 }
3922 #endif
3923 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3924 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3925
3926 return MsOS_PA2KSEG1(u32PhyAddr);
3927 }
3928
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3929 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3930 {
3931
3932 if (u8MiuSel == E_CHIP_MIU_0)
3933 {
3934 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3935 //_HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3936 }
3937 else if (u8MiuSel == E_CHIP_MIU_1)
3938 {
3939 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3940 //_HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3941 }
3942 /*
3943 else // 2
3944 {
3945 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3946 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3947 }*/
3948
3949 }
3950
3951 #if SUPPORT_G2VP9 && defined(VDEC3)
3952 #ifdef __ARM_NEON__
3953 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3954 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3955 {
3956 uint32x4x4_t data, data2;
3957 MS_U8* raster2 = raster + tile_w * 4;
3958
3959 data = vld4q_u32((const uint32_t *)tile);
3960 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3961
3962 vst1q_u32((uint32_t *)raster, data.val[0]);
3963 raster += stride;
3964 vst1q_u32((uint32_t *)raster, data.val[1]);
3965 raster += stride;
3966 vst1q_u32((uint32_t *)raster, data.val[2]);
3967 raster += stride;
3968 vst1q_u32((uint32_t *)raster, data.val[3]);
3969
3970
3971 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3972 raster2 += stride;
3973 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3974 raster2 += stride;
3975 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3976 raster2 += stride;
3977 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3978 }
3979 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3980 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3981 {
3982 MS_U8* tile0 = tile;
3983 MS_U8* tile1 = tile+16;
3984 MS_U8* tile2 = tile+32;
3985 MS_U8* tile3 = tile+48;
3986 int i;
3987
3988 for (i=0; i<4; i++) {
3989 raster[i] = tile0[i];
3990 raster[4+i] = tile1[i];
3991 raster[8+i] = tile2[i];
3992 raster[12+i] = tile3[i];
3993 }
3994
3995 for (i=0; i<4; i++) {
3996 raster[stride+i] = tile0[4+i];
3997 raster[stride+4+i] = tile1[4+i];
3998 raster[stride+8+i] = tile2[4+i];
3999 raster[stride+12+i] = tile3[4+i];
4000 }
4001
4002 for (i=0; i<4; i++) {
4003 raster[2*stride+i] = tile0[8+i];
4004 raster[2*stride+4+i] = tile1[8+i];
4005 raster[2*stride+8+i] = tile2[8+i];
4006 raster[2*stride+12+i] = tile3[8+i];
4007 }
4008
4009 for (i=0; i<4; i++) {
4010 raster[3*stride+i] = tile0[12+i];
4011 raster[3*stride+4+i] = tile1[12+i];
4012 raster[3*stride+8+i] = tile2[12+i];
4013 raster[3*stride+12+i] = tile3[12+i];
4014 }
4015 }
4016 #endif // #ifdef __ARM_NEON__
4017
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)4018 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
4019 {
4020 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
4021 u32Id,
4022 E_TASK_PRI_MEDIUM,
4023 TRUE,
4024 NULL,
4025 32, // stack size..
4026 "HVD_PostProcess_task");
4027
4028 if (s32HvdPpTaskId < 0)
4029 {
4030 HVD_EX_MSG_ERR("Pp Task create failed\n");
4031
4032 return FALSE;
4033 }
4034
4035 HVD_EX_MSG_DBG("Pp Task create success\n");
4036 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
4037
4038 return TRUE;
4039 }
4040
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)4041 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
4042 {
4043 return y * stride * h + x * w * h;
4044 }
4045
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)4046 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
4047 {
4048 return y * stride * h + x * w;
4049 }
4050
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)4051 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
4052 {
4053 raster[0] = tile[0];
4054 raster[1] = tile[1];
4055 raster[2] = tile[2];
4056 raster[3] = tile[3];
4057 raster[stride] = tile[4];
4058 raster[stride + 1] = tile[5];
4059 raster[stride + 2] = tile[6];
4060 raster[stride + 3] = tile[7];
4061 raster[2 * stride] = tile[8];
4062 raster[2 * stride + 1] = tile[9];
4063 raster[2 * stride + 2] = tile[10];
4064 raster[2 * stride + 3] = tile[11];
4065 raster[3 * stride] = tile[12];
4066 raster[3 * stride + 1] = tile[13];
4067 raster[3 * stride + 2] = tile[14];
4068 raster[3 * stride + 3] = tile[15];
4069 }
4070
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)4071 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
4072 {
4073 const MS_U32 tile_w = 4;
4074 const MS_U32 tile_h = 4;
4075 MS_U32 tile_stride = w;
4076 MS_U32 x, y;
4077 MS_U8 *dst1, *dst2;
4078 MS_U8 *src1, *src2;
4079
4080 #ifdef __ARM_NEON__
4081 // To overlap load and store, handle two blocks at the same time.
4082 dst1 = dst;
4083 src1 = src;
4084 for (y = 0; y < h / tile_h; y++)
4085 {
4086 dst2 = dst1;
4087 src2 = src1;
4088 for (x = 0; x <= (w/tile_w - 8); x+=8)
4089 {
4090 tile4x4_to_raster_8(
4091 dst2,
4092 src2,
4093 raster_stride, tile_w, tile_h);
4094 dst2 += tile_w * 8;
4095 src2 += tile_w * tile_h * 8;
4096 }
4097 dst1 += raster_stride * tile_h;
4098 src1 += tile_stride * tile_h;
4099 for (; x < w / tile_w; x++)
4100 {
4101 tile4x4_to_raster(
4102 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4103 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4104 raster_stride);
4105 }
4106 }
4107 #else
4108 dst1 = NULL;
4109 src1 = NULL;
4110 dst2 = NULL;
4111 src2 = NULL;
4112
4113 for (y = 0; y < h / tile_h; y++)
4114 {
4115 for (x = 0; x <= (w/tile_w - 4); x+=4)
4116 {
4117 tile4x4_to_raster_4(
4118 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4119 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4120 raster_stride);
4121 }
4122 for (; x < w / tile_w; x++)
4123 {
4124 tile4x4_to_raster(
4125 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4126 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4127 raster_stride);
4128 }
4129 }
4130 #endif
4131 }
4132
4133 #define FLUSH_CACHE_SIZE (256 * 1024)
4134
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)4135 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
4136 {
4137 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
4138 if (u32Size > FLUSH_CACHE_SIZE)
4139 u32Size = FLUSH_CACHE_SIZE;
4140
4141 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
4142 }
4143
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)4144 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
4145 {
4146 MS_U32 u32SkipSize = 0;
4147
4148 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
4149 if (u32Size > FLUSH_CACHE_SIZE)
4150 {
4151 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
4152 u32Size = FLUSH_CACHE_SIZE;
4153 }
4154
4155 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
4156 }
4157
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)4158 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
4159 {
4160 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
4161 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4162 MS_U32 u32SrcMiuSel, u32DstMiuSel;
4163 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
4164
4165 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
4166
4167 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
4168
4169 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
4170 {
4171 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
4172 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
4173
4174 HVD_Delay_ms(1); // FIXME
4175
4176 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
4177 continue;
4178
4179 HAL_HVD_EX_ReadMemory();
4180
4181 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
4182 {
4183 MS_U8 *pSrcVA, *pDstVA;
4184 MS_U32 u32SrcPA, u32DstPA;
4185 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
4186 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
4187
4188 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
4189 {
4190 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
4191
4192 u16Width = pFrmInfo->u16Width;
4193 u16Height = pFrmInfo->u16Height;
4194 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
4195 }
4196
4197 // Luma
4198 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
4199 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
4200
4201 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
4202 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
4203
4204 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
4205 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
4206
4207 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
4208
4209 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
4210
4211 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
4212
4213 // Chroma
4214 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
4215 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
4216
4217 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
4218 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
4219
4220 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
4221 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
4222
4223 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
4224
4225 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
4226
4227 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
4228
4229 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
4230 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
4231 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
4232
4233 HAL_HVD_EX_FlushMemory();
4234
4235 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
4236 break;
4237
4238 HAL_HVD_EX_ReadMemory();
4239 }
4240 }
4241
4242 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
4243
4244 return TRUE;
4245 }
4246 #endif
4247
HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id,MS_BOOL * isVP8Used,MS_BOOL * isAECUsed,MS_BOOL * isAVCUsed)4248 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed , MS_BOOL *isAVCUsed)
4249 {
4250 MS_U8 i ;
4251 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
4252
4253 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM ; i++)
4254 {
4255 if( _pHVDCtrls[i].bUsed && (i != u8DrvId))
4256 {
4257 MS_U32 u32TempModeFlag = (_pHVDCtrls[i].InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ;
4258 if((E_HVD_INIT_HW_VP8 == u32TempModeFlag))
4259 {
4260 *isVP8Used = TRUE ;
4261 }
4262 else if((E_HVD_INIT_HW_VP9 == u32TempModeFlag) || (E_HVD_INIT_HW_AVS == u32TempModeFlag))
4263 {
4264 *isAECUsed = TRUE ;
4265 }
4266 else if((E_HVD_INIT_HW_AVC == u32TempModeFlag))
4267 {
4268 *isAVCUsed = TRUE ;
4269 }
4270 }
4271 }
4272 }
4273
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)4274 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
4275 {
4276 #ifndef VDEC3
4277 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4278 #endif
4279 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4280 MS_BOOL isVP8Used = FALSE;
4281 MS_BOOL isAECUsed = FALSE;
4282 MS_BOOL isAVCUsed = FALSE;
4283 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
4284 // MS_U8 u8MiuSel;
4285 // MS_U32 u32StartOffset;
4286
4287 #if SUPPORT_EVD
4288 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
4289 #else
4290 MS_BOOL isEVD = FALSE;
4291 #endif
4292 MS_BOOL isHVD = !isEVD;
4293
4294 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
4295 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4296
4297 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
4298 // re-setup clock.
4299 #if SUPPORT_G2VP9 && defined(VDEC3)
4300 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4301 #endif
4302
4303 if(isHVD)
4304 {
4305 if(!HAL_VPU_EX_HVDInUsed())
4306 {
4307 printf("HVD power on\n");
4308 #ifdef CONFIG_MSTAR_CLKM
4309 HAL_HVD_EX_PowerCtrl_CLKM(u32Id, TRUE);
4310 #else
4311 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
4312 #endif
4313 }
4314
4315 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4316 {
4317 HAL_VP8_PowerCtrl(TRUE);
4318 }
4319 else if(!isAECUsed &&( E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4320 {
4321 HAL_AEC_PowerCtrl(TRUE);
4322 }
4323
4324 #ifdef CONFIG_MSTAR_SRAMPD
4325 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
4326 HVD_Delay_ms(1);
4327 #endif
4328 }
4329
4330 #if SUPPORT_EVD
4331 #ifdef VDEC3
4332 if (isEVD)
4333 {
4334 if(!HAL_VPU_EX_EVDInUsed())
4335 {
4336 printf("EVD power on\n");
4337 #ifdef CONFIG_MSTAR_CLKM
4338 HAL_EVD_EX_PowerCtrl_CLKM(u32Id, TRUE);
4339 #else
4340 HAL_EVD_EX_PowerCtrl(u32Id, TRUE);
4341 #endif
4342 }
4343 if(!isAECUsed && (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4344 {
4345 HAL_AEC_PowerCtrl(TRUE);
4346 }
4347 }
4348 #endif
4349 #endif
4350
4351
4352
4353
4354 #if SUPPORT_G2VP9 && defined(VDEC3)
4355 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4356 {
4357 if (!HAL_VPU_EX_G2VP9InUsed())
4358 {
4359 printf("G2 VP9 power on\n");
4360 HAL_VP9_EX_PowerCtrl(TRUE);
4361 }
4362 }
4363 #endif
4364
4365 if ((!HAL_VPU_EX_HVDInUsed()) )
4366 {
4367 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
4368 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
4369 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
4370 _HVD_EX_ResetMainSubBBUWptr(u32Id);
4371
4372 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
4373
4374 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
4375 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
4376 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_128 , HVD_REG_RESET_MIU_128);
4377 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_128 , HVD_REG_RESET_MIU1_128 );
4378 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_256 );
4379 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_256);
4380 //BWA
4381 _HVD_Write2Byte(HVD_REG_BWA_CLK, ((_HVD_Read2Byte(HVD_REG_BWA_CLK))&((~HVD_REG_CLK_HVD_SW_OV_EN & ~HVD_REG_CLK_HVD_IDB_SW_OV_EN))));
4382
4383 #if 0
4384 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
4385 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4386 {
4387 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
4388
4389 _HAL_HVD_Entry();
4390 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
4391 _HAL_HVD_Release();
4392
4393 }
4394 #endif
4395 }
4396
4397 #if SUPPORT_EVD
4398 if (isEVD)
4399 {
4400 #ifdef VDEC3
4401 if (!HAL_VPU_EX_EVDInUsed())
4402 #endif
4403 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
4404 }
4405 #endif
4406
4407 #if SUPPORT_G2VP9 && defined(VDEC3)
4408 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4409 {
4410 if (!HAL_VPU_EX_G2VP9InUsed())
4411 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
4412 }
4413 #endif
4414
4415
4416 if(pCtrl == NULL)
4417 {
4418 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
4419 //return FALSE;
4420 goto RESET;
4421 }
4422
4423 #if SUPPORT_EVD
4424 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
4425 {
4426 #ifdef VDEC3
4427 if (!HAL_VPU_EX_EVDInUsed())
4428 #endif
4429 {
4430 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4431 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
4432 }
4433
4434 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
4435 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
4436 {
4437 #ifdef VDEC3
4438 if (0 == pCtrl->u32BBUId)
4439 #else
4440 if (0 == u8TaskId)
4441 #endif
4442 {
4443 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
4444 }
4445 #ifdef VDEC3
4446 else if (1 == pCtrl->u32BBUId)
4447 #else
4448 else if (1 == u8TaskId)
4449 #endif
4450 {
4451 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
4452 }
4453 #ifdef VDEC3
4454 else if (2 == pCtrl->u32BBUId)
4455 #else
4456 else if (2 == u8TaskId)
4457 #endif
4458 {
4459 _HVD_WriteWordMask(EVD_BBU23_SETTING, REG_TSP2EVD_EN_BS3, REG_TSP2EVD_EN_BS3);
4460 }
4461 else
4462 {
4463 #ifdef VDEC3
4464 if (pCtrl->u32BBUId > 3)
4465 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
4466 #else
4467 if (u8TaskId > 3)
4468 printf("Error u8TaskId = %d , %s:%d\n",u8TaskId,__FUNCTION__,__LINE__);
4469 #endif
4470
4471 _HVD_WriteWordMask(EVD_BBU23_SETTING, REG_TSP2EVD_EN_BS4, REG_TSP2EVD_EN_BS4);
4472 }
4473 }
4474 goto RESET;
4475 }
4476 #endif
4477
4478 // HVD4, from JANUS and later chip
4479 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
4480 {
4481 case E_HVD_INIT_HW_AVS:
4482 {
4483 #ifdef VDEC3
4484 if (0 == pCtrl->u32BBUId)
4485 #else
4486 if (0 == u8TaskId)
4487 #endif
4488 {
4489 _HVD_WriteWordMask(HVD_REG_RESET, 0,
4490 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4491 }
4492 else
4493 {
4494 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
4495 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4496 }
4497
4498 break;
4499 }
4500 case E_HVD_INIT_HW_RM:
4501 {
4502 #ifdef VDEC3
4503 if (0 == pCtrl->u32BBUId)
4504 #else
4505 if (0 == u8TaskId)
4506 #endif
4507 {
4508 _HVD_WriteWordMask(HVD_REG_RESET, 0,
4509 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4510
4511 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
4512 {
4513 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
4514 }
4515 else // RV 8
4516 {
4517 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
4518 }
4519 }
4520 else
4521 {
4522 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
4523 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4524
4525 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
4526 {
4527 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
4528 }
4529 else // RV 8
4530 {
4531 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
4532 }
4533
4534 }
4535
4536 break;
4537 }
4538 default:
4539 {
4540 #ifdef VDEC3
4541 if (0 == pCtrl->u32BBUId)
4542 #else
4543 if (0 == u8TaskId)
4544 #endif
4545 {
4546 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4547 }
4548 else
4549 {
4550 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4551 }
4552 break;
4553 }
4554 }
4555
4556 RESET:
4557
4558 #if 0 //use miu256bit
4559 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
4560
4561 if (!HAL_VPU_EX_HVDInUsed())
4562 {
4563 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
4564 }
4565
4566 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
4567 #endif
4568
4569 #if SUPPORT_EVD
4570 if (isEVD)
4571 {
4572 #ifdef VDEC3
4573 if (!HAL_VPU_EX_EVDInUsed())
4574 #endif
4575 {
4576 printf("EVD miu 128 bits\n");
4577 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_256 & ~EVD_REG_RESET_MIU1_256));
4578 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_128 | EVD_REG_RESET_MIU1_128));
4579 printf("EVD BBU 128 bits\n");
4580 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) & ~REG_BBU_MIU_256));
4581 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) | REG_BBU_MIU_128));
4582 _HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) & ~REG_CLK_EVD_SW_OV_EN & ~REG_CLK_EVD_PPU_SW_OV_EN));//set 0 firmware
4583 }
4584 }
4585 #endif
4586 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
4587 // Only ES buffer addrress needs to be set for VP8
4588 _HVD_EX_SetESBufferAddr(u32Id);
4589 #else
4590 if(DecoderType != E_VPU_EX_DECODER_MVD)
4591 {
4592 _HVD_EX_SetBufferAddr(u32Id);
4593 }
4594 #endif
4595 if (!HAL_VPU_EX_HVDInUsed())
4596 {
4597 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
4598 }
4599
4600 #if SUPPORT_EVD
4601 if (isEVD)
4602 {
4603 #ifdef VDEC3
4604 if (!HAL_VPU_EX_EVDInUsed())
4605 #endif
4606 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
4607 }
4608 #endif
4609
4610 #if SUPPORT_G2VP9 && defined(VDEC3)
4611 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4612 {
4613 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4614
4615 if (!HAL_VPU_EX_G2VP9InUsed())
4616 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
4617
4618 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
4619 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
4620 }
4621 #endif
4622
4623 return TRUE;
4624 }
4625
HAL_HVD_EX_DeinitHW(MS_U32 u32Id)4626 MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id)
4627 {
4628 MS_U16 u16Timeout = 1000;
4629 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4630 MS_BOOL isVP8Used = FALSE;
4631 MS_BOOL isAECUsed = FALSE;
4632 MS_BOOL isAVCUsed = FALSE;
4633 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed , &isAVCUsed);
4634
4635 #if SUPPORT_EVD
4636 if(!isAVCUsed && E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) && !HAL_VPU_EX_EVDInUsed())
4637 {
4638 HAL_EVD_EX_DeinitHW(u32Id);//no AVC/EVD use , close EVD power
4639 }
4640 #endif
4641
4642 if(TRUE == HAL_VPU_EX_HVDInUsed())
4643 {
4644 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4645 {
4646 HAL_VP8_PowerCtrl(FALSE);
4647 }
4648 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4649 {
4650 HAL_AEC_PowerCtrl(FALSE);
4651 }
4652 return FALSE;
4653 }
4654 else
4655 {
4656 _HVD_EX_SetMIUProtectMask(TRUE);
4657
4658 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
4659
4660 while (u16Timeout)
4661 {
4662 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
4663 {
4664 break;
4665 }
4666 u16Timeout--;
4667 }
4668
4669 #ifdef CONFIG_MSTAR_CLKM
4670 HAL_HVD_EX_PowerCtrl_CLKM(u32Id, FALSE);
4671 #else
4672 HAL_HVD_EX_PowerCtrl(u32Id, FALSE);
4673 #endif
4674
4675 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4676 {
4677 HAL_VP8_PowerCtrl(FALSE);
4678 }
4679 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4680 {
4681 HAL_AEC_PowerCtrl(FALSE);
4682 }
4683
4684 #ifdef CONFIG_MSTAR_SRAMPD
4685 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
4686 HVD_Delay_ms(1);
4687 #endif
4688
4689 _HVD_EX_SetMIUProtectMask(FALSE);
4690
4691 return TRUE;
4692 }
4693
4694 return FALSE;
4695 }
4696
HAL_HVD_EX_FlushMemory(void)4697 void HAL_HVD_EX_FlushMemory(void)
4698 {
4699 MsOS_FlushMemory();
4700 }
4701
HAL_HVD_EX_ReadMemory(void)4702 void HAL_HVD_EX_ReadMemory(void)
4703 {
4704 MsOS_ReadMemory();
4705 }
4706
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)4707 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
4708 {
4709 _pHVDCtrls = pHVDCtrlsBase;
4710 }
4711
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)4712 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
4713 {
4714 return;
4715 }
4716
HAL_HVD_EX_GetHWVersionID(void)4717 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
4718 {
4719 return _HVD_Read2Byte(HVD_REG_REV_ID);
4720 }
4721
4722
HAL_HVD_EX_Init_Share_Mem(void)4723 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
4724 {
4725 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
4726 #if !defined(SUPPORT_X_MODEL_FEATURE)
4727 MS_U32 u32ShmId;
4728 MS_VIRT u32Addr;
4729 MS_U32 u32BufSize;
4730
4731
4732 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
4733 sizeof(HVD_Hal_CTX),
4734 &u32ShmId,
4735 &u32Addr,
4736 &u32BufSize,
4737 MSOS_SHM_QUERY))
4738 {
4739 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
4740 sizeof(HVD_Hal_CTX),
4741 &u32ShmId,
4742 &u32Addr,
4743 &u32BufSize,
4744 MSOS_SHM_CREATE))
4745 {
4746 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
4747 if(pHVDHalContext == NULL)
4748 {
4749 pHVDHalContext = &gHVDHalContext;
4750 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4751 _HVD_EX_Context_Init_HAL();
4752 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
4753 }
4754 else
4755 {
4756 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
4757 }
4758 //return FALSE;
4759 }
4760 else
4761 {
4762 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
4763 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
4764 _HVD_EX_Context_Init_HAL();
4765 }
4766 }
4767 else
4768 {
4769 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
4770 }
4771 #else
4772 if(pHVDHalContext == NULL)
4773 {
4774 pHVDHalContext = &gHVDHalContext;
4775 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4776 _HVD_EX_Context_Init_HAL();
4777 }
4778 #endif
4779 _HAL_HVD_MutexCreate();
4780 #else
4781 if(pHVDHalContext == NULL)
4782 {
4783 pHVDHalContext = &gHVDHalContext;
4784 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4785 _HVD_EX_Context_Init_HAL();
4786 }
4787 #endif
4788
4789 return TRUE;
4790 }
4791
4792
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)4793 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
4794 {
4795 MS_U32 i = 0;
4796
4797 if (eStreamType == E_HAL_HVD_MVC_STREAM)
4798 {
4799 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
4800 return pHVDHalContext->_stHVDStream[0].eStreamId;
4801 }
4802 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
4803 {
4804 for (i = 0;
4805 i <
4806 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
4807 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
4808 {
4809 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
4810 {
4811 return pHVDHalContext->_stHVDStream[i].eStreamId;
4812 }
4813 }
4814 }
4815 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
4816 {
4817 for (i = 0;
4818 i <
4819 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
4820 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
4821 {
4822 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
4823 {
4824 return pHVDHalContext->_stHVDStream[i].eStreamId;
4825 }
4826 }
4827 }
4828 #ifdef VDEC3
4829 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
4830 {
4831 i = eStreamType - E_HAL_HVD_N_STREAM;
4832 if (!pHVDHalContext->_stHVDStream[i].bUsed)
4833 return pHVDHalContext->_stHVDStream[i].eStreamId;
4834 }
4835 #endif
4836
4837 return E_HAL_HVD_STREAM_NONE;
4838 }
4839
HAL_VP8_PowerCtrl(MS_BOOL bEnable)4840 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable)
4841 {
4842 if (bEnable)
4843 {
4844 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
4845
4846 switch (pHVDHalContext->u32HVDClockType)
4847 {
4848 case 384:
4849 {
4850 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4851 break;
4852 }
4853 case 288:
4854 {
4855 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4856 break;
4857 }
4858 default:
4859 {
4860 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4861 break;
4862 }
4863 }
4864 }
4865 else
4866 {
4867 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
4868 }
4869
4870 }
4871
HAL_AEC_PowerCtrl(MS_BOOL bEnable)4872 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable)
4873 {
4874 if (bEnable)
4875 {
4876 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4877
4878 switch (pHVDHalContext->u32HVDClockType)
4879 {
4880 case 384:
4881 {
4882 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4883 break;
4884 }
4885 case 288:
4886 {
4887 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4888 break;
4889 }
4890 default:
4891 {
4892 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4893 break;
4894 }
4895 }
4896 }
4897 else
4898 {
4899 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4900 }
4901
4902 }
4903
4904
HAL_HVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)4905 void HAL_HVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
4906 {
4907
4908 if (bEnable)
4909 {
4910 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4911 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4912 }
4913 else
4914 {
4915 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4916 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4917 }
4918
4919 // fix to not inverse
4920 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
4921
4922 switch (pHVDHalContext->u32HVDClockType)
4923 {
4924 #if 0 //for overclocking
4925 case 432:
4926 {
4927 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
4928 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4929 break;
4930 }
4931 #endif
4932 case 384:
4933 {
4934 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4935 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4936 break;
4937 }
4938 case 288:
4939 {
4940 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4941 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4942 break;
4943 }
4944 default:
4945 {
4946 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4947 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4948 break;
4949 }
4950 }
4951 }
4952
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4953 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4954 {
4955 u32HVDRegOSBase = u32RegBase;
4956 HAL_VPU_EX_InitRegBase(u32RegBase);
4957 }
4958
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4959 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4960 {
4961 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4962 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4963 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4964 }
4965
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4966 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4967 {
4968 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4969 HVD_ShareMem *pShm = NULL;
4970 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4971 #if HVD_ENABLE_MVC
4972 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4973 #endif ///HVD_ENABLE_MVC
4974
4975 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4976 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4977 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4978 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4979 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4980 int i;
4981 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4982 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4983 #if HVD_ENABLE_MVC
4984 if(bMVC)
4985 {
4986 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4987 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4988 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4989 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4990 }
4991 #endif ///HVD_ENABLE_MVC
4992
4993 // set a local copy of FW code address; assuming there is only one copy of FW,
4994 // no matter how many task will be created.
4995
4996 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4997
4998 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4999
5000 // global variables
5001 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
5002
5003
5004 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
5005 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
5006 // Create mutex
5007 //_HAL_HVD_MutexCreate();
5008
5009 // fill HVD init variables
5010 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5011 {
5012 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
5013 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
5014 }
5015 else
5016 #if HVD_ENABLE_RV_FEATURE
5017 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
5018 {
5019 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
5020 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
5021 #ifdef VDEC3_FB
5022 pHVDHalContext->u32RV_VLCTableAddr = 0;
5023 #else
5024 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
5025 {
5026 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
5027 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
5028 }
5029 else
5030 {
5031 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
5032 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
5033 return E_HVD_RETURN_INVALID_PARAMETER;
5034 }
5035 #endif
5036 }
5037 else
5038 #endif
5039 {
5040 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
5041 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
5042 #if HVD_ENABLE_MVC
5043 if(bMVC)
5044 {
5045 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
5046 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
5047 }
5048 #endif /// HVD_ENABLE_MVC
5049 pHVDHalContext->u32RV_VLCTableAddr = 0;
5050 }
5051
5052 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
5053 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
5054 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
5055 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
5056 {
5057 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
5058 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
5059 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
5060 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
5061 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
5062 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
5063 #if HVD_ENABLE_MVC
5064 if(bMVC)
5065 {
5066 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
5067 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
5068 {
5069 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
5070 }
5071 }
5072 #endif /// HVD_ENABLE_MVC
5073
5074 return E_HVD_RETURN_SUCCESS;
5075 }
5076 else
5077 {
5078 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
5079 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
5080 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
5081 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
5082 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
5083 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
5084 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
5085 return E_HVD_RETURN_INVALID_PARAMETER;
5086 }
5087 }
5088
5089 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)5090 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
5091 #else
5092 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
5093 #endif
5094 {
5095 MS_U32 u32Addr = 0;
5096 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5097 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5098 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5099
5100 MS_U32 u32TmpStartOffset;
5101 MS_U8 u8TmpMiuSel;
5102
5103
5104 memset(pShm, 0, sizeof(HVD_ShareMem));
5105
5106 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
5107
5108 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
5109 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
5110 #ifdef VDEC3
5111 if (bFWdecideFB || bCMAUsed)
5112 {
5113 pShm->u32FrameBufAddr = 0;
5114 pShm->u32FrameBufSize = 0;
5115 }
5116 else
5117 #endif
5118 {
5119 pShm->u32FrameBufAddr = u32Addr;
5120 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
5121 }
5122
5123 // FIXME: need to use the avaliable task resource instead of using next task resource
5124 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
5125 pShm->u8ExternalHeapIdx = u8Idx + 1;
5126 else
5127 pShm->u8ExternalHeapIdx = 0xFF;
5128 pShm->DispInfo.u16DispWidth = 1;
5129 pShm->DispInfo.u16DispHeight = 1;
5130 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
5131 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
5132 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
5133 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
5134 //Chip info
5135 pShm->u16ChipID = E_MSTAR_CHIP_K6;
5136 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
5137 // PreSetControl
5138 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
5139 {
5140 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
5141 }
5142
5143 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
5144 {
5145 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
5146 }
5147
5148
5149 pShm->bUseTSPInBBUMode = FALSE;
5150
5151
5152 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
5153 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
5154 {
5155 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
5156
5157 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
5158
5159 pShm->u32IapGnBufAddr = u32Addr;
5160 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
5161
5162 }
5163
5164 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
5165 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
5166 {
5167 case E_HVD_DEF_MFCODEC_DEFAULT:
5168 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
5169 break;
5170 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
5171 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
5172 break;
5173 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
5174 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
5175 break;
5176 default:
5177 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
5178 }
5179
5180 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
5181 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
5182 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
5183
5184 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
5185 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
5186 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
5187 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
5188 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
5189 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
5190
5191 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.bEnable))
5192 {
5193 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
5194
5195 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.bConnect;
5196 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
5197 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
5198
5199 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, pShm->stDynmcDispPath.u8DispPath);
5200 }
5201 else
5202 {
5203 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
5204
5205 MS_U8 u8Connect = FALSE;
5206 MS_U8 u8Path = E_CTL_DISPLAY_PATH_NONE;
5207 switch (pCtrl->eStream)
5208 {
5209 case E_HVD_ORIGINAL_MAIN_STREAM:
5210 u8Connect = TRUE;
5211 u8Path = E_CTL_DISPLAY_PATH_MVOP_0;
5212 break;
5213 case E_HVD_ORIGINAL_SUB_STREAM:
5214 u8Connect = TRUE;
5215 u8Path = E_CTL_DISPLAY_PATH_MVOP_1;
5216 break;
5217 case E_HVD_ORIGINAL_N_STREAM:
5218 default:
5219 u8Connect = FALSE;
5220 u8Path = E_CTL_DISPLAY_PATH_NONE;
5221 break;
5222 }
5223
5224 pShm->stDynmcDispPath.u8Connect = u8Connect;
5225 pShm->stDynmcDispPath.u8DispPath = u8Path;
5226 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
5227
5228 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, u8Path);
5229 }
5230
5231 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5232 {
5233 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.bEnable))
5234 {
5235 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
5236 pShm->u8InputTSP = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.u8InputTsp;
5237
5238 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
5239 }
5240 else
5241 {
5242 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
5243
5244 MS_U8 u8Input = E_CTL_INPUT_TSP_NONE;
5245 switch (pCtrl->eStream)
5246 {
5247 case E_HVD_ORIGINAL_MAIN_STREAM:
5248 u8Input = E_CTL_INPUT_TSP_0;
5249 break;
5250 case E_HVD_ORIGINAL_SUB_STREAM:
5251 u8Input = E_CTL_INPUT_TSP_1;
5252 break;
5253 case E_HVD_ORIGINAL_N_STREAM:
5254 default:
5255 u8Input = E_CTL_INPUT_TSP_NONE;
5256 break;
5257 }
5258
5259 pShm->u8InputTSP = u8Input;
5260
5261 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
5262 }
5263 }
5264 else
5265 {
5266 HVD_EX_MSG_DBG("[NDec][0x%x][%d] not TSP input, ignore PRESET_CONNECT_INPUT_TSP \n", u32Id, u8Idx);
5267 }
5268
5269 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
5270 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
5271 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
5272 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
5273 else
5274 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
5275 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
5276 {
5277 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
5278 {
5279 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
5280 }
5281 else
5282 {
5283 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
5284 }
5285 }
5286 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
5287 {
5288 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
5289 {
5290 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
5291 }
5292 else
5293 {
5294 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
5295 }
5296 }
5297 else
5298 {
5299 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
5300 }
5301
5302 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5303 {
5304 pShm->bHVDIMIEnable = TRUE;
5305 }
5306
5307 #if 0
5308 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
5309 {
5310 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
5311 }
5312 #endif
5313
5314 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5315 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5316 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5317 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5318 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5319 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5320 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5321 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5322 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
5323 {
5324 pShm->bUseWbMvop = 1;
5325 }
5326
5327
5328 // disable AVC fluidplay temporarily
5329 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
5330 || E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5331 {
5332 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
5333 }
5334
5335 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
5336
5337 #if (VPU_FORCE_MIU_MODE)
5338 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5339
5340 pShm->u32FWBaseAddr = u32TmpStartOffset;
5341
5342 #else
5343 ///TODO:
5344 /*
5345 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5346
5347 if(u8TmpMiuSel == E_CHIP_MIU_0)
5348 {
5349 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
5350 }
5351 else if(u8TmpMiuSel == E_CHIP_MIU_1)
5352 {
5353 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
5354 }
5355 else if(u8TmpMiuSel == E_CHIP_MIU_2)
5356 {
5357 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
5358 }
5359 */
5360 #endif
5361 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
5362 #else
5363 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
5364 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
5365 {
5366 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
5367 }
5368 pShm->u32FWBaseAddr = u32Addr;
5369 #endif
5370
5371 // RM only
5372 #if HVD_ENABLE_RV_FEATURE
5373 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
5374 && (pCtrl->InitParams.pRVFileInfo != NULL))
5375 {
5376 MS_U32 i = 0;
5377
5378 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
5379 {
5380 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
5381 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
5382 }
5383
5384 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
5385 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
5386 #ifdef VDEC3_FB
5387 pShm->u32RM_VLCTableAddr = 0;
5388 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
5389 #else
5390 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
5391
5392 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
5393 u32Addr = u32TmpStartOffset;
5394
5395 pShm->u32RM_VLCTableAddr = u32Addr;
5396 #endif
5397 }
5398 #endif
5399
5400 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5401 && (pCtrl->InitParams.pRVFileInfo != NULL))
5402 {
5403 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
5404 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
5405 }
5406
5407 //if(pCtrl->InitParams.bColocateBBUMode)
5408 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
5409 {
5410 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5411 }
5412
5413 #if SUPPORT_G2VP9
5414 // Enable SW detile support for G2 VP9
5415 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5416 {
5417 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
5418 }
5419 #endif
5420
5421 HAL_HVD_EX_FlushMemory();
5422
5423 return E_HVD_RETURN_SUCCESS;
5424 }
5425 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)5426 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
5427 #else
5428 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
5429 #endif
5430 {
5431 MS_BOOL bInitRet = FALSE;
5432
5433 #if 0
5434 // check MVD power on
5435 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
5436 {
5437 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
5438 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5439 HVD_Delay_ms(1);
5440 }
5441 // Check VPU power on
5442 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
5443 {
5444 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
5445 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
5446 HVD_Delay_ms(1);
5447 }
5448 // check HVD power on
5449 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
5450 {
5451 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
5452 HAL_HVD_EX_PowerCtrl(TRUE);
5453 HVD_Delay_ms(1);
5454 }
5455 #endif
5456 #ifdef VDEC3
5457 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
5458 #else
5459 bInitRet = _HVD_EX_SetRegCPU(u32Id);
5460 #endif
5461 if (!bInitRet)
5462 {
5463 return E_HVD_RETURN_FAIL;
5464 }
5465
5466 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
5467
5468 if (!bInitRet)
5469 {
5470 return E_HVD_RETURN_FAIL;
5471 }
5472
5473 return E_HVD_RETURN_SUCCESS;
5474 }
5475
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)5476 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
5477 {
5478 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5479
5480 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
5481
5482 return E_HVD_RETURN_SUCCESS;
5483 }
5484
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)5485 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
5486 {
5487 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5488 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5489 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5490 MS_BOOL bMVC = FALSE;
5491 #if HVD_ENABLE_MVC
5492 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
5493 #endif
5494
5495 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5496 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
5497
5498 switch (u32type)
5499 {
5500 // share memory
5501 // switch
5502 case E_HVD_SDATA_FRAMEBUF_ADDR:
5503 {
5504 pShm->u32FrameBufAddr = u32Data;
5505 break;
5506 }
5507 case E_HVD_SDATA_FRAMEBUF_SIZE:
5508 {
5509 pShm->u32FrameBufSize = u32Data;
5510 break;
5511 }
5512 case E_HVD_SDATA_FRAMEBUF2_ADDR:
5513 {
5514 pShm->u32FrameBuf2Addr = u32Data;
5515 break;
5516 }
5517 case E_HVD_SDATA_FRAMEBUF2_SIZE:
5518 {
5519 pShm->u32FrameBuf2Size = u32Data;
5520 break;
5521 }
5522 case E_HVD_SDATA_MAX_CMA_SIZE:
5523 {
5524 pShm->u32MaxCMAFrameBufSize = u32Data;
5525 break;
5526 }
5527 case E_HVD_SDATA_MAX_CMA_SIZE2:
5528 {
5529 pShm->u32MaxCMAFrameBuf2Size = u32Data;
5530 break;
5531 }
5532 case E_HVD_SDATA_CMA_USED:
5533 {
5534 pShm->bCMA_Use = u32Data;
5535 break;
5536 }
5537 case E_HVD_SDATA_CMA_ALLOC_DONE:
5538 {
5539 pShm->bCMA_AllocDone = u32Data;
5540 break;
5541 }
5542 case E_HVD_SDATA_CMA_TWO_MIU:
5543 {
5544 pShm->bCMA_TwoMIU = u32Data;
5545 break;
5546 }
5547 case E_HVD_SDATA_RM_PICTURE_SIZES:
5548 {
5549 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
5550 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
5551 break;
5552 }
5553 case E_HVD_SDATA_ERROR_CODE:
5554 {
5555 pShm->u16ErrCode = (MS_U16) u32Data;
5556 break;
5557 }
5558 case E_HVD_SDATA_DISP_INFO_TH:
5559 {
5560 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
5561 sizeof(HVD_DISP_THRESHOLD));
5562 break;
5563 }
5564 case E_HVD_SDATA_FW_FLUSH_STATUS:
5565 {
5566 pShm->u8FlushStatus = (MS_U8)u32Data;
5567 break;
5568 }
5569 case E_HVD_SDATA_DMX_FRAMERATE:
5570 {
5571 pShm->u32DmxFrameRate = u32Data;
5572 break;
5573 }
5574 case E_HVD_SDATA_DMX_FRAMERATEBASE:
5575 {
5576 pShm->u32DmxFrameRateBase = u32Data;
5577 break;
5578 }
5579 case E_HVD_SDATA_MIU_SEL:
5580 {
5581 pShm->u32VDEC_MIU_SEL = u32Data;
5582 break;
5583 }
5584 // SRAM
5585
5586 // Mailbox
5587 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
5588 {
5589 if (u32Data != 0)
5590 {
5591 pShm->bEnableDispCtrl = TRUE;
5592 pShm->bIsTrigDisp = TRUE;
5593 }
5594 else
5595 {
5596 pShm->bEnableDispCtrl = FALSE;
5597 }
5598
5599 break;
5600 }
5601 case E_HVD_SDATA_GET_DISP_INFO_START:
5602 {
5603 pShm->bSpsChange = FALSE;
5604 break;
5605 }
5606 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
5607 {
5608 pShm->u32VirtualBoxWidth = u32Data;
5609 break;
5610 }
5611 case E_HVD_SDATA_DV_INFO:
5612 {
5613 MS_U8 u8DVLevel = u32Data & 0x00ff;
5614 MS_U8 u8DVProfile = (u32Data >> 8) & 0x00ff;
5615
5616 pShm->u8DVLevelFromDriverAPI = u8DVLevel;
5617 pShm->u8DVProfileFromDriverAPI = u8DVProfile;
5618 }
5619 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
5620 {
5621 pShm->u32VirtualBoxHeight = u32Data;
5622 break;
5623 }
5624 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
5625 {
5626 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
5627 {
5628 //printf("DispFrame DqPtr: %d\n", u32Data);
5629 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
5630 }
5631 break;
5632 }
5633 case E_HVD_SDATA_DISPQ_STATUS_DISP:
5634 {
5635 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
5636 {
5637 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
5638 {
5639 //printf("DispFrame DqPtr: %ld\n", u32Data);
5640 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
5641 }
5642 }
5643 break;
5644 }
5645 case E_HVD_SDATA_DISPQ_STATUS_FREE:
5646 {
5647 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5648 {
5649 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
5650 {
5651 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
5652 {
5653 //ALOGE("R1: %x", u32Data);
5654 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
5655 }
5656 else
5657 {
5658 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
5659 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
5660 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
5661 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
5662 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
5663 }
5664 }
5665 else
5666 {
5667 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
5668 }
5669 }
5670 else
5671 {
5672 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
5673 {
5674 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
5675 }
5676 }
5677 break;
5678 }
5679 #if 0//(HVD_ENABLE_IQMEM)
5680 case E_HVD_SDATA_FW_IQMEM_CTRL:
5681 {
5682 pShm->u8IQmemCtrl= (MS_U8)u32Data;
5683 break;
5684
5685 }
5686 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
5687 {
5688 if (u32Data != 0)
5689 {
5690 pShm->bIQmemEnableIfSupport= TRUE;
5691 }
5692 else
5693 {
5694 pShm->bIQmemEnableIfSupport= FALSE;
5695 }
5696
5697
5698 break;
5699
5700 }
5701 #endif
5702 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
5703 {
5704 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
5705 break;
5706 }
5707
5708 default:
5709 break;
5710 }
5711
5712 HAL_HVD_EX_FlushMemory();
5713
5714 return eRet;
5715 }
5716
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)5717 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
5718 {
5719 MS_S64 s64Ret = 0;
5720 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5721
5722 HAL_HVD_EX_ReadMemory();
5723
5724 switch (eType)
5725 {
5726 case E_HVD_GDATA_PTS_STC_DIFF:
5727 s64Ret = pShm->s64PtsStcDiff;
5728 break;
5729 case E_HVD_GDATA_TS_SEAMLESS_TARGET_PTS:
5730 s64Ret = (MS_S64)(pShm->u64SeamlessTargetPTS); //33bit PTS is compatible in S64
5731 break;
5732 default:
5733 break;
5734 }
5735
5736 return s64Ret;
5737 }
5738
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)5739 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
5740 {
5741 MS_VIRT u32Ret = 0;
5742 //static MS_U64 u64pts_real = 0;
5743 MS_U64 u64pts_low = 0;
5744 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5745 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5746
5747 HAL_HVD_EX_ReadMemory();
5748
5749 if(pShm == NULL)
5750 {
5751 printf("########## VDEC patch for Debug ###########\n");
5752 return 0x0;
5753 }
5754
5755 switch (eType)
5756 {
5757 // share memory
5758 // switch
5759 case E_HVD_GDATA_DISP_INFO_ADDR:
5760 {
5761 u32Ret = (MS_VIRT) (&pShm->DispInfo);
5762 break;
5763 }
5764 case E_HVD_GDATA_MIU_SEL:
5765 u32Ret = pShm->u32VDEC_MIU_SEL;
5766 break;
5767 case E_HVD_GDATA_FRAMEBUF_ADDR:
5768 u32Ret = pShm->u32FrameBufAddr;
5769 break;
5770 case E_HVD_GDATA_FRAMEBUF_SIZE:
5771 u32Ret = pShm->u32FrameBufSize;
5772 break;
5773 case E_HVD_GDATA_FRAMEBUF2_ADDR:
5774 u32Ret = pShm->u32FrameBuf2Addr;
5775 break;
5776 case E_HVD_GDATA_FRAMEBUF2_SIZE:
5777 u32Ret = pShm->u32FrameBuf2Size;
5778 break;
5779 case E_HVD_GDATA_CMA_ALLOC_DONE:
5780 u32Ret = pShm->bCMA_AllocDone;
5781 break;
5782 case E_HVD_GDATA_CMA_USED:
5783 u32Ret = pShm->bCMA_Use;
5784 break;
5785 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
5786 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
5787 break;
5788 // report
5789 case E_HVD_GDATA_PTS:
5790 {
5791 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
5792 break;
5793 }
5794 case E_HVD_GDATA_U64PTS:
5795 {
5796 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
5797 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
5798 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5799 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5800 break;
5801 }
5802 case E_HVD_GDATA_U64PTS_PRE_PARSE:
5803 {
5804 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
5805 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
5806 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5807 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5808 break;
5809 }
5810 case E_HVD_GDATA_DECODE_CNT:
5811 {
5812 u32Ret = pShm->u32DecodeCnt;
5813 break;
5814 }
5815 case E_HVD_GDATA_DATA_ERROR_CNT:
5816 {
5817 u32Ret = pShm->u32DataErrCnt;
5818 break;
5819 }
5820 case E_HVD_GDATA_DEC_ERROR_CNT:
5821 {
5822 u32Ret = pShm->u32DecErrCnt;
5823 break;
5824 }
5825 case E_HVD_GDATA_ERROR_CODE:
5826 {
5827 u32Ret = (MS_U32) (pShm->u16ErrCode);
5828 break;
5829 }
5830 case E_HVD_GDATA_VPU_IDLE_CNT:
5831 {
5832 u32Ret = pShm->u32VPUIdleCnt;
5833 break;
5834 }
5835 case E_HVD_GDATA_DISP_FRM_INFO:
5836 {
5837 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
5838 break;
5839 }
5840 case E_HVD_GDATA_DEC_FRM_INFO:
5841 {
5842 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
5843 break;
5844 }
5845 case E_HVD_GDATA_ES_LEVEL:
5846 {
5847 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
5848 break;
5849 }
5850 #if HVD_ENABLE_MVC
5851 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
5852 {
5853 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
5854 break;
5855 }
5856 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
5857 {
5858 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
5859 break;
5860 }
5861 #endif
5862
5863 // user data
5864 case E_HVD_GDATA_USERDATA_WPTR:
5865 {
5866 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
5867 break;
5868 }
5869 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
5870 {
5871 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
5872 break;
5873 }
5874 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
5875 {
5876 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
5877 break;
5878 }
5879 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
5880 {
5881 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
5882 break;
5883 }
5884 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
5885 {
5886 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
5887 break;
5888 }
5889 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
5890 {
5891 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
5892 break;
5893 }
5894 // report - modes
5895 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
5896 {
5897 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
5898 break;
5899 }
5900 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
5901 {
5902 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
5903 break;
5904 }
5905 case E_HVD_GDATA_IS_ERR_CONCEAL:
5906 {
5907 u32Ret = pShm->ModeStatus.bIsErrConceal;
5908 break;
5909 }
5910 case E_HVD_GDATA_IS_SYNC_ON:
5911 {
5912 u32Ret = pShm->ModeStatus.bIsSyncOn;
5913 break;
5914 }
5915 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
5916 {
5917 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
5918 break;
5919 }
5920 case E_HVD_GDATA_SYNC_MODE:
5921 {
5922 u32Ret = pShm->ModeStatus.u8SyncType;
5923 break;
5924 }
5925 case E_HVD_GDATA_SKIP_MODE:
5926 {
5927 u32Ret = pShm->ModeStatus.u8SkipMode;
5928 break;
5929 }
5930 case E_HVD_GDATA_DROP_MODE:
5931 {
5932 u32Ret = pShm->ModeStatus.u8DropMode;
5933 break;
5934 }
5935 case E_HVD_GDATA_DISPLAY_DURATION:
5936 {
5937 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
5938 break;
5939 }
5940 case E_HVD_GDATA_FRC_MODE:
5941 {
5942 u32Ret = pShm->ModeStatus.u8FrcMode;
5943 break;
5944 }
5945 case E_HVD_GDATA_NEXT_PTS:
5946 {
5947 u32Ret = pShm->u32NextPTS;
5948 break;
5949 }
5950 case E_HVD_GDATA_DISP_Q_SIZE:
5951 {
5952 u32Ret = pShm->u16DispQSize;
5953 break;
5954 }
5955 case E_HVD_GDATA_DISP_Q_PTR:
5956 {
5957 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
5958 break;
5959 }
5960 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
5961 {
5962 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
5963 break;
5964 }
5965 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
5966 {
5967 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
5968 break;
5969 }
5970 case E_HVD_GDATA_REAL_FRAMERATE:
5971 {
5972 // return VPS/VUI timing info framerate, and 0 if timing info not exist
5973 u32Ret = pShm->u32RealFrameRate;
5974 break;
5975 }
5976 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
5977 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
5978 break;
5979 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
5980 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
5981 break;
5982 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
5983 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
5984 break;
5985 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
5986 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
5987 break;
5988 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
5989 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
5990 break;
5991 case E_HVD_GDATA_FW_STATUS_FLAG:
5992 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
5993 break;
5994
5995 // internal control
5996 case E_HVD_GDATA_IS_1ST_FRM_RDY:
5997 {
5998 u32Ret = pShm->bIs1stFrameRdy;
5999 break;
6000 }
6001 case E_HVD_GDATA_IS_I_FRM_FOUND:
6002 {
6003 u32Ret = pShm->bIsIFrmFound;
6004 break;
6005 }
6006 case E_HVD_GDATA_IS_SYNC_START:
6007 {
6008 u32Ret = pShm->bIsSyncStart;
6009 break;
6010 }
6011 case E_HVD_GDATA_IS_SYNC_REACH:
6012 {
6013 u32Ret = pShm->bIsSyncReach;
6014 break;
6015 }
6016 case E_HVD_GDATA_FW_VERSION_ID:
6017 {
6018 u32Ret = pShm->u32FWVersionID;
6019 break;
6020 }
6021 case E_HVD_GDATA_FW_IF_VERSION_ID:
6022 {
6023 u32Ret = pShm->u32FWIfVersionID;
6024 break;
6025 }
6026 case E_HVD_GDATA_BBU_Q_NUMB:
6027 {
6028 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
6029 break;
6030 }
6031 case E_HVD_GDATA_DEC_Q_NUMB:
6032 {
6033 u32Ret = pShm->u16DecQNumb;
6034 break;
6035 }
6036 case E_HVD_GDATA_DISP_Q_NUMB:
6037 {
6038 u32Ret = pShm->u16DispQNumb;
6039 break;
6040 }
6041 case E_HVD_GDATA_PTS_Q_NUMB:
6042 {
6043 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
6044 break;
6045 }
6046 case E_HVD_GDATA_FW_INIT_DONE:
6047 {
6048 u32Ret = pShm->bInitDone;
6049 break;
6050 }
6051 // debug
6052 case E_HVD_GDATA_SKIP_CNT:
6053 {
6054 u32Ret = pShm->u32SkipCnt;
6055 break;
6056 }
6057 case E_HVD_GDATA_GOP_CNT:
6058 {
6059 u32Ret = pShm->u32DropCnt;
6060 break;
6061 }
6062 case E_HVD_GDATA_DISP_CNT:
6063 {
6064 u32Ret = pShm->u32DispCnt;
6065 break;
6066 }
6067 case E_HVD_GDATA_DROP_CNT:
6068 {
6069 u32Ret = pShm->u32DropCnt;
6070 break;
6071 }
6072 case E_HVD_GDATA_DISP_STC:
6073 {
6074 u32Ret = pShm->u32DispSTC;
6075 break;
6076 }
6077 case E_HVD_GDATA_VSYNC_CNT:
6078 {
6079 u32Ret = pShm->u32VsyncCnt;
6080 break;
6081 }
6082 case E_HVD_GDATA_MAIN_LOOP_CNT:
6083 {
6084 u32Ret = pShm->u32MainLoopCnt;
6085 break;
6086 }
6087
6088 // AVC
6089 case E_HVD_GDATA_AVC_LEVEL_IDC:
6090 {
6091 u32Ret = pShm->u16AVC_SPS_LevelIDC;
6092 break;
6093 }
6094 case E_HVD_GDATA_AVC_LOW_DELAY:
6095 {
6096 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
6097 break;
6098 }
6099 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
6100 {
6101 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
6102 break;
6103 }
6104 case E_HVD_GDATA_FW_FLUSH_STATUS:
6105 {
6106 u32Ret = (MS_U32) (pShm->u8FlushStatus);
6107 break;
6108 }
6109 case E_HVD_GDATA_FW_CODEC_TYPE:
6110 {
6111 u32Ret = pShm->u32CodecType;
6112 break;
6113 }
6114 case E_HVD_GDATA_FW_ES_BUF_STATUS:
6115 {
6116 u32Ret = (MS_U32)pShm->u8ESBufStatus;
6117 break;
6118 }
6119 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
6120 {
6121 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
6122 {
6123 u32Ret = 1;
6124 }
6125 else
6126 {
6127 u32Ret = 0;
6128 }
6129 break;
6130 }
6131
6132 // SRAM
6133
6134 // Mailbox
6135 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
6136 {
6137 u32Ret = pShm->u32FwState;
6138 break;
6139 }
6140 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
6141 {
6142 u32Ret = pShm->bSpsChange;
6143 break;
6144 }
6145 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
6146 {
6147 u32Ret = pShm->bSpsChange;
6148
6149 if (pShm->bSpsChange &&
6150 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
6151 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
6152 {
6153 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
6154 }
6155
6156 break;
6157 }
6158 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
6159 {
6160 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6161
6162 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
6163 {
6164 u32Ret = pShm->u32FwInfo;
6165 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
6166 }
6167 break;
6168 }
6169 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
6170 {
6171 if (pShm->bIsTrigDisp) // not clear yet
6172 {
6173 u32Ret = FALSE;
6174 }
6175 else
6176 {
6177 u32Ret = TRUE;
6178 }
6179 break;
6180 }
6181 case E_HVD_GDATA_ES_READ_PTR:
6182 {
6183 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6184 break;
6185 }
6186 case E_HVD_GDATA_ES_WRITE_PTR:
6187 {
6188 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
6189 break;
6190 }
6191 case E_HVD_GDATA_BBU_READ_PTR:
6192 {
6193 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
6194 break;
6195 }
6196 case E_HVD_GDATA_BBU_WRITE_PTR:
6197 {
6198 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6199 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6200 {
6201 u32Ret = pHVDHalContext->u32VP8BBUWptr;
6202 }
6203 else
6204 {
6205 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
6206 }
6207 break;
6208 }
6209 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
6210 {
6211 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6212
6213 u32Ret = pCtrl->u32BBUWptr_Fired;
6214
6215 break;
6216 }
6217 case E_HVD_GDATA_VPU_PC_CNT:
6218 {
6219 u32Ret = _HVD_EX_GetPC();
6220 break;
6221 }
6222 case E_HVD_GDATA_ES_QUANTITY:
6223 {
6224 u32Ret=_HVD_EX_GetESQuantity(u32Id);
6225 break;
6226 }
6227
6228
6229 // FW def
6230 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
6231 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
6232 break;
6233
6234 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
6235 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
6236 break;
6237 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
6238 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
6239 break;
6240 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
6241 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6242 break;
6243 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
6244 u32Ret = MAX_PTS_TABLE_SIZE;
6245 break;
6246 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
6247 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
6248 break;
6249 case E_HVD_GDATA_FW_DS_BUF_ADDR:
6250 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
6251 break;
6252 case E_HVD_GDATA_FW_DS_BUF_SIZE:
6253 u32Ret = pShm->u32DSBuffSize; //3k or 6k
6254 break;
6255 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
6256 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
6257 break;
6258 case E_HVD_GDATA_FW_DS_INFO_ADDR:
6259 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
6260 break;
6261 case E_HVD_GDATA_FW_DS_IS_ENABLED:
6262 {
6263 if (pShm->bDSIsRunning)
6264 {
6265 u32Ret = TRUE;
6266 }
6267 else
6268 {
6269 u32Ret = FALSE;
6270 }
6271 break;
6272 }
6273 #if 0//(HVD_ENABLE_IQMEM)
6274 case E_HVD_GDATA_FW_IQMEM_CTRL:
6275 {
6276
6277 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
6278
6279 break;
6280 }
6281 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
6282 {
6283 if(pShm->bIsIQMEMSupport){
6284 u32Ret = TRUE;
6285 }
6286 else{
6287
6288 u32Ret = FALSE;
6289 }
6290
6291 break;
6292 }
6293 #endif
6294 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
6295 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
6296 break;
6297 case E_HVD_GDATA_FIELD_PIC_FLAG:
6298 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
6299 break;
6300 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
6301 u32Ret = pShm->u32SeamlessTSStatus;
6302 break;
6303 case E_HVD_GDATA_TS_SEAMLESS_TARGET_POC:
6304 u32Ret = pShm->u32SeamlessTargetPOC;
6305 break;
6306 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
6307 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
6308 break;
6309 #ifdef VDEC3
6310 case E_HVD_GDATA_FW_VBBU_ADDR:
6311 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
6312 break;
6313 #endif
6314 case E_HVD_GDATA_SEQ_CHANGE_INFO:
6315 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
6316 break;
6317 case E_HVD_GDATA_GET_NOT_SUPPORT_INFO:
6318 u32Ret = pShm->u32NotSupportInfo;
6319 break;
6320 case E_HVD_GDATA_GET_MIN_TSP_DATA_SIZE:
6321 u32Ret = pShm->u32CurMinTspDataSize;
6322 break;
6323 default:
6324 break;
6325 }
6326 return u32Ret;
6327 }
6328
HAL_HVD_EX_Get_DV_Support_Profiles(void)6329 MS_U32 HAL_HVD_EX_Get_DV_Support_Profiles(void)
6330 {
6331 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
6332 }
6333
HAL_HVD_EX_Get_DV_Support_Highest_Level(DV_Stream_Profile pDV_Stream_Profile)6334 DV_Stream_Level HAL_HVD_EX_Get_DV_Support_Highest_Level(DV_Stream_Profile pDV_Stream_Profile)
6335 {
6336 switch (pDV_Stream_Profile)
6337 {
6338 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
6339 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
6340
6341 #if 0// unsupported profile
6342 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
6343 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6344 #endif
6345
6346 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
6347 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6348
6349 #if 0// unsupported profile
6350 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
6351 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6352 #endif
6353
6354 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
6355 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6356
6357 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
6358 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
6359
6360 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
6361 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6362
6363 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
6364 default:
6365 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6366 }
6367 }
6368
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)6369 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
6370 {
6371 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
6372 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
6373 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6374
6375 _HAL_HVD_Entry();
6376
6377 // check if old SVD cmds
6378 if (u32Cmd < E_HVD_CMD_SVD_BASE)
6379 {
6380 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
6381
6382 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
6383 }
6384
6385 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
6386 {
6387 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
6388 }
6389
6390 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
6391 {
6392 if (u32Cmd == E_HVD_CMD_FLUSH)
6393 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
6394 }
6395
6396 if (u32Cmd == E_HVD_CMD_FLUSH &&
6397 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
6398 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
6399 {
6400 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
6401 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
6402 {
6403 _HAL_HVD_Release();
6404 HVD_Delay_ms(1);
6405 _HAL_HVD_Entry();
6406 }
6407 }
6408
6409 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
6410
6411 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
6412
6413 _HAL_HVD_Return(eRet);
6414 }
6415
HAL_HVD_EX_DeInit(MS_U32 u32Id)6416 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
6417 {
6418 HVD_Return eRet = E_HVD_RETURN_FAIL;
6419 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6420 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6421 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
6422 MS_U8 u8MiuSel;
6423 MS_U32 u32StartOffset;
6424 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6425
6426 #if HVD_ENABLE_TIME_MEASURE
6427 MS_U32 ExitTimeCnt = 0;
6428 ExitTimeCnt = HVD_GetSysTime_ms();
6429 #endif
6430
6431 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
6432
6433 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
6434
6435 if (E_HVD_RETURN_SUCCESS != eRet)
6436 {
6437 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
6438 }
6439
6440 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
6441
6442 if (E_HVD_RETURN_SUCCESS != eRet)
6443 {
6444 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
6445 }
6446
6447 // check FW state to make sure it's STOP DONE
6448 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
6449 {
6450 if (HVD_GetSysTime_ms() > u32Timeout)
6451 {
6452 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
6453
6454 //return E_HVD_RETURN_TIMEOUT;
6455 eRet = E_HVD_RETURN_TIMEOUT;
6456 break;
6457 }
6458 }
6459
6460 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
6461 {
6462 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
6463 pShm->u8VdecPlusDropRatio,
6464 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
6465 pShm->u32VdecPlusDropCnt,
6466 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
6467 pShm->u32VdecPlusDecCnt,
6468 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
6469 }
6470 else
6471 {
6472 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
6473 pShm->u8VdecPlusDropRatio,
6474 pShm->u32VdecPlusDropCnt,
6475 pShm->u32VdecPlusDecCnt,
6476 pShm->u32VdecPlusDispPicCnt);
6477 }
6478
6479 VPU_EX_FWCodeCfg fwCfg;
6480 VPU_EX_TaskInfo taskInfo;
6481 VPU_EX_NDecInitPara nDecInitPara;
6482
6483 nDecInitPara.pFWCodeCfg = &fwCfg;
6484 nDecInitPara.pTaskInfo = &taskInfo;
6485
6486 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
6487 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
6488
6489 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);//power control
6490 #if 0
6491 taskInfo.u32Id = u32Id;
6492 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
6493 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
6494 #endif
6495
6496 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6497 {
6498 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
6499 }
6500 else
6501 {
6502 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
6503 }
6504
6505 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
6506 {
6507 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
6508 }
6509
6510 /* clear es buffer */
6511 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
6512 {
6513 //printf("Clear ES buffer\n");
6514
6515 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
6516 }
6517
6518 //_HAL_HVD_MutexDelete();
6519
6520 #if HVD_ENABLE_TIME_MEASURE
6521 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
6522 #endif
6523
6524 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
6525 #ifndef VDEC3
6526 // reset bbu wptr
6527 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6528 {
6529 if(TRUE == HAL_VPU_EX_HVDInUsed())
6530 {
6531 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
6532 {
6533 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
6534 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
6535 }
6536 else
6537 {
6538 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
6539 {
6540 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
6541 }
6542 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
6543 }
6544 }
6545 else
6546 {
6547 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
6548 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
6549 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
6550 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6551 {
6552 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
6553 {
6554 _HVD_EX_ResetMainSubBBUWptr(u32Id);
6555 }
6556 }
6557 else
6558 {
6559 _HVD_EX_ResetMainSubBBUWptr(u32Id);
6560 }
6561 }
6562 }
6563 #endif
6564 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
6565
6566 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6567 {
6568 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
6569 }
6570
6571 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
6572 {
6573
6574 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
6575
6576 _HAL_HVD_Entry();
6577 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
6578 _HAL_HVD_Release();
6579
6580 }
6581
6582 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
6583 HVD_EX_MSG_DBG("success\n");
6584
6585 return eRet;
6586 }
6587
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)6588 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
6589 {
6590 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
6591 MS_U32 u32Addr = 0;
6592 HVD_EX_Drv_Ctrl *pCtrl = NULL;
6593 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6594
6595 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6596
6597 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
6598 {
6599 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
6600
6601 if (E_HVD_RETURN_SUCCESS != eRet)
6602 {
6603 return eRet;
6604 }
6605 }
6606
6607 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
6608
6609 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
6610 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6611 {
6612 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
6613
6614 if (E_HVD_RETURN_SUCCESS != eRet)
6615 {
6616 return eRet;
6617 }
6618 }
6619
6620 u32Addr = pInfo->u32Staddr;
6621
6622 if (pInfo->bRVBrokenPacket)
6623 {
6624 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
6625 }
6626
6627 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
6628 {
6629 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
6630 }
6631 else
6632 {
6633 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
6634 }
6635
6636 if (E_HVD_RETURN_SUCCESS != eRet)
6637 {
6638 return eRet;
6639 }
6640
6641 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6642 {
6643 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
6644 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
6645
6646 if (E_HVD_RETURN_SUCCESS != eRet)
6647 {
6648 return eRet;
6649 }
6650 }
6651
6652 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
6653
6654 // do not add local pointer
6655 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
6656 {
6657 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
6658
6659 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
6660 (u32PacketStAddr <
6661 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
6662 {
6663 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
6664 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
6665 }
6666 else
6667 {
6668 //null packet
6669 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
6670 pCtrl->LastNal.u32NalSize = 0;
6671 }
6672 }
6673 else
6674 {
6675 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
6676 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
6677 }
6678
6679 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
6680 pCtrl->u32BBUPacketCnt++;
6681
6682 return eRet;
6683 }
6684
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)6685 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
6686 {
6687 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6688 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6689 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
6690 if(bCurrentStatus == bEnable)
6691 return;
6692
6693 if (bEnable)
6694 {
6695 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
6696 }
6697 else
6698 {
6699 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
6700 }
6701 }
6702
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)6703 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
6704 {
6705 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6706 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6707
6708 if (bEnable)
6709 {
6710 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
6711 }
6712 else
6713 {
6714 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
6715 }
6716 }
6717
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)6718 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
6719 {
6720 MS_U32 u32RB = 0;
6721 switch(eISRType)
6722 {
6723 case E_HWDEC_ISR_HVD:
6724 u32RB = REG_HVD_BASE;
6725 break;
6726 #if SUPPORT_EVD
6727 case E_HWDEC_ISR_EVD:
6728 u32RB = REG_EVD_BASE;
6729 break;
6730 #endif
6731 #if SUPPORT_G2VP9
6732 case E_HWDEC_ISR_G2VP9:
6733 break;
6734 #endif
6735 default:
6736 break;
6737 }
6738 if(u32RB)
6739 {
6740 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
6741 }
6742 }
6743
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)6744 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
6745 {
6746 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6747 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6748
6749 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
6750 }
6751
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)6752 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
6753 {
6754 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6755 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6756
6757 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
6758 {
6759 return FALSE;
6760 }
6761 else
6762 {
6763 return TRUE;
6764 }
6765 }
6766
HAL_HVD_EX_IsAlive(MS_U32 u32Id)6767 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
6768 {
6769 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6770
6771 if (pCtrl)
6772 {
6773 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
6774 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
6775 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
6776 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
6777 {
6778 return FALSE;
6779 }
6780 else
6781 {
6782 return TRUE;
6783 }
6784 }
6785 else
6786 {
6787 return FALSE;
6788 }
6789 }
6790
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)6791 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
6792 {
6793 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6794 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6795 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6796
6797 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6798 {
6799 HAL_HVD_EX_ReadMemory();
6800
6801 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
6802 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
6803
6804 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
6805 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
6806 }
6807
6808 return TRUE;
6809 }
6810
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)6811 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
6812 {
6813 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6814 HVD_EX_Drv_Ctrl *pCtrl = NULL;
6815 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6816 MS_U32 u32Data;
6817 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6818
6819 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
6820
6821 HAL_HVD_EX_FlushMemory();
6822 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
6823 {
6824 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6825 pCtrl->LastNal.u32NalAddr = u32Data;
6826 pCtrl->LastNal.u32NalSize = 0;
6827 }
6828
6829 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6830 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
6831
6832 return TRUE;
6833 }
6834
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)6835 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
6836 {
6837 if (bEnable)
6838 {
6839 if (HAL_VPU_EX_IsEVDR2())
6840 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6841 else
6842 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
6843 }
6844 else
6845 {
6846 #if defined (__aeon__)
6847 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6848 #else // defined (__mips__)
6849 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
6850 #endif
6851 }
6852 }
6853
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)6854 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
6855 {
6856 return 0;
6857 }
6858
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)6859 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
6860 {
6861 return;
6862 }
6863
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)6864 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
6865 {
6866 //if( u16Clock == 0 )
6867 return 216; //140;
6868 //if( )
6869 }
6870
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)6871 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
6872 {
6873 //MS_BOOL bBitMIU1 = FALSE;
6874 //MS_BOOL bCodeMIU1 = FALSE;
6875 MS_U8 u8BitMiuSel = 0;
6876 MS_U8 u8CodeMiuSel = 0;
6877 MS_U32 u32BitStartOffset;
6878 MS_U32 u32CodeStartOffset;
6879 //MS_U8 u8MiuSel;
6880 //MS_U32 u32StartOffset;
6881 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6882 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6883 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6884 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
6885
6886 #if HVD_ENABLE_MVC
6887 if(HAL_HVD_EX_CheckMVCID(u32Id))
6888 {
6889 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
6890 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
6891 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
6892 {
6893 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
6894 }
6895 }
6896 #endif /// HVD_ENABLE_MVC
6897
6898 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6899 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6900
6901
6902
6903
6904 if (u8BitMiuSel != u8CodeMiuSel)
6905 {
6906 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
6907 BDMA_Result bdmaRlt;
6908 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6909
6910 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6911 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
6912 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6913
6914 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
6915
6916 if (E_BDMA_OK != bdmaRlt)
6917 {
6918 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
6919 }
6920 #else
6921 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6922
6923 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6924 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
6925 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6926
6927 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
6928 #endif
6929 }
6930
6931 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
6932
6933 HAL_HVD_EX_FlushMemory();
6934
6935 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6936 {
6937 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
6938 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
6939 }
6940 else
6941 {
6942 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
6943
6944 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
6945 }
6946 }
6947
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)6948 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
6949 {
6950 if (bEnable)
6951 {
6952 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
6953 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
6954 }
6955 else
6956 {
6957 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
6958 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
6959 }
6960 }
6961
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)6962 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
6963 {
6964 MS_U32 tmp1 = 0;
6965 MS_U32 tmp2 = 0;
6966 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6967
6968 HAL_HVD_EX_ReadMemory();
6969
6970 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
6971 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
6972
6973 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6974 {
6975 MS_U32 u32Tmp = u32UartCtrl;
6976
6977 HVD_EX_MSG_DBG("\n");
6978 u32UartCtrl = 0; // turn off debug message to prevent other function prints
6979 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
6980 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
6981
6982 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
6983 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
6984 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
6985 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
6986
6987 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
6988 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
6989 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
6990
6991 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
6992 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
6993 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
6994 _HVD_EX_GetESLevel(u32Id));
6995
6996 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
6997 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
6998 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
6999 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
7000 printf
7001 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
7002 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
7003 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
7004 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
7005 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
7006 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
7007 pShm->ModeStatus.bShowOneField);
7008
7009 u32UartCtrl = u32Tmp; // recover debug level
7010 }
7011 }
7012
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)7013 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
7014 {
7015 MS_U8 *u32Addr = NULL;
7016 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7017 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7018
7019 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
7020 {
7021 return;
7022 }
7023
7024 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
7025
7026 *u32NalSize = *(u32Addr + 2) & 0x1f;
7027 *u32NalSize <<= 8;
7028 *u32NalSize |= *(u32Addr + 1) & 0xff;
7029 *u32NalSize <<= 8;
7030 *u32NalSize |= *(u32Addr) & 0xff;
7031
7032 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
7033 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
7034 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
7035 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
7036 }
7037
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)7038 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
7039 {
7040 MS_U32 u32CurIdx = 0;
7041 MS_BOOL bFinished = FALSE;
7042 MS_U32 u32NalOffset = 0;
7043 MS_U32 u32NalSize = 0;
7044 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7045
7046 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
7047 {
7048 return;
7049 }
7050
7051 u32CurIdx = u32StartIdx;
7052
7053 do
7054 {
7055 if (u32CurIdx == u32EndIdx)
7056 {
7057 bFinished = TRUE;
7058 }
7059
7060 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
7061
7062 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
7063 {
7064 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
7065 }
7066
7067 u32CurIdx++;
7068
7069 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
7070 {
7071 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
7072 }
7073 } while (bFinished == TRUE);
7074 }
7075
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)7076 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
7077 {
7078 MS_U32 i = 0;
7079 MS_U32 value = 0;
7080
7081 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
7082 {
7083 HVD_EX_MSG_DBG("\n");
7084
7085 for (i = 0; i <= u32Num; i++)
7086 {
7087 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
7088 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
7089 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
7090
7091 if (value == 0)
7092 {
7093 break;
7094 }
7095
7096 printf(" %08x", value);
7097
7098 if (((i % 8) + 1) == 8)
7099 {
7100 printf(" |%u\n", i + 1);
7101 }
7102 }
7103
7104 printf("\nHVD Dump HW status End: total number:%u\n", i);
7105 }
7106 }
7107
HAL_HVD_EX_GetDVSupportProfiles(void)7108 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
7109 {
7110 #if 0 // wait avc finish DV dual job
7111 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
7112 #else
7113 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
7114 #endif
7115 }
7116
7117
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)7118 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
7119 {
7120 switch (u32DV_Stream_Profile)
7121 {
7122 #if 0 // wait avc finish DV dual job
7123 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
7124 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
7125 #endif
7126
7127 #if 0 // unsupported profile
7128 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
7129 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7130 #endif
7131
7132 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
7133 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7134
7135 #if 0 // unsupported profile
7136 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
7137 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7138 #endif
7139
7140 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
7141 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7142
7143 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
7144 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
7145
7146 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
7147 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7148
7149 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
7150 default:
7151 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7152 }
7153 }
7154
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)7155 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
7156 {
7157 if (pDrvCtrl)
7158 {
7159 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
7160 }
7161 }
7162
7163 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)7164 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
7165 {
7166 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
7167 }
7168
HAL_HVD_EX_GetView(MS_U32 u32Id)7169 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
7170 {
7171 if( (0xFF & (u32Id >> 8)) == 0x10)
7172 return E_VDEC_EX_MAIN_VIEW;
7173 else
7174 return E_VDEC_EX_SUB_VIEW;
7175 }
7176 #endif ///HVD_ENABLE_MVC
7177
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)7178 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
7179 {
7180 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
7181 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
7182 return;
7183 }
7184
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)7185 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
7186 {
7187 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
7188 return;
7189 }
7190
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)7191 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
7192 {
7193 MS_U64 _hw_max_pixel = 0;
7194 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
7195
7196 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
7197 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
7198 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
7199 }
7200
7201
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)7202 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
7203 {
7204 #if 1
7205 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7206 MS_U16 u16QNum = pShm->u16DispQNumb;
7207 MS_U16 u16QPtr = pShm->u16DispQPtr;
7208 // MS_U16 u16QSize = pShm->u16DispQSize;
7209 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
7210 MS_U32 u32DispQNum = 0;
7211 #if HVD_ENABLE_MVC
7212 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
7213
7214 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7215 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
7216
7217 if(bMVC || bDolbyVision)
7218 {
7219 #if 0
7220 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
7221 {
7222 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
7223 }
7224 #endif
7225
7226 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
7227 //search the next frame to display
7228 while (u16QNum > 0)
7229 {
7230 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
7231 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
7232 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
7233
7234 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
7235 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
7236 {
7237 /// For MVC. Output views after the pair of (base and depend) views were decoded.
7238 /// Check the depned view was initial when Output the base view.
7239 if((u16QPtr%2) == 0)
7240 {
7241 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
7242 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
7243 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
7244 {
7245 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
7246 ///printf("Return NULL.\n");
7247 continue;
7248 }
7249 }
7250 u32DispQNum++;
7251 }
7252
7253 u16QNum--;
7254 //go to next frame in the dispQ
7255 u16QPtr++;
7256
7257 if (u16QPtr >= pShm->u16DispQSize)
7258 {
7259 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
7260 }
7261 }
7262 }
7263 else
7264 #endif ///HVD_ENABLE_MVC
7265 {
7266 #if 0
7267 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
7268 {
7269 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
7270 }
7271 #endif
7272 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
7273 //search the next frame to display
7274 while (u16QNum != 0)
7275 {
7276 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
7277
7278 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
7279 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
7280 {
7281 u32DispQNum++;
7282 }
7283
7284 u16QNum--;
7285 //go to next frame in the dispQ
7286 u16QPtr++;
7287
7288 if (u16QPtr == pShm->u16DispQSize)
7289 {
7290 u16QPtr = 0; //wrap to the begin
7291 }
7292 }
7293 }
7294
7295 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
7296 return u32DispQNum;
7297 #else
7298 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
7299 return pShm->u16DispQNumb;
7300 #endif
7301 }
7302
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)7303 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
7304 {
7305 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7306 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
7307 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
7308 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
7309 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
7310 #if SUPPORT_G2VP9 && defined(VDEC3)
7311 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
7312 #else // Not using G2 VP9 implies using Mstar EVD VP9
7313 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
7314 #endif
7315 else
7316 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
7317 }
7318
7319 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)7320 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
7321 {
7322 #ifdef CONFIG_MSTAR_CLKM
7323 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
7324 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
7325 #else
7326 if (bEnable)
7327 {
7328 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
7329 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
7330 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
7331 }
7332 else
7333 {
7334 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
7335 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
7336 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
7337 }
7338
7339 switch (pHVDHalContext->u32EVDClockType)
7340 {
7341 case 576:
7342 {
7343 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
7344 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
7345 break;
7346 }
7347 case 532:
7348 {
7349 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
7350 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
7351 break;
7352 }
7353 case 456:
7354 {
7355 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
7356 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
7357 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
7358 }
7359 case 466:
7360 {
7361 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
7362 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
7363 break;
7364 }
7365 case 480:
7366 {
7367 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
7368 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
7369 break;
7370 }
7371 case 384:
7372 {
7373 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
7374 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
7375 break;
7376 }
7377 case 320:
7378 {
7379 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
7380 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
7381 break;
7382 }
7383 case 240:
7384 {
7385 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
7386 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
7387 break;
7388 }
7389 case 192:
7390 {
7391 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
7392 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
7393 break;
7394 }
7395 default:
7396 {
7397 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
7398 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
7399 break;
7400 }
7401 }
7402 #endif
7403 #ifdef CONFIG_MSTAR_SRAMPD
7404 if (bEnable)
7405 {
7406 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
7407 HVD_Delay_ms(1);
7408 }
7409 else
7410 {
7411 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
7412 HVD_Delay_ms(1);
7413 }
7414 #endif
7415 return;
7416 }
7417
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)7418 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
7419 {
7420 #ifndef VDEC3
7421 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
7422 #endif
7423 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7424
7425 #ifdef VDEC3
7426 if (0 == pCtrl->u32BBUId)
7427 #else
7428 if (0 == u8TaskId)
7429 #endif
7430 {
7431 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
7432 }
7433 #ifdef VDEC3
7434 else if (1 == pCtrl->u32BBUId)
7435 #else
7436 else if (1 == u8TaskId)
7437 #endif
7438 {
7439 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
7440 }
7441 #ifdef VDEC3
7442 else if (2 == pCtrl->u32BBUId)
7443 #else
7444 else if (2 == u8TaskId)
7445 #endif
7446 {
7447 _HVD_Write2Byte(EVD_BBU23_SETTING, (_HVD_Read2Byte(EVD_BBU23_SETTING) & ~REG_TSP2EVD_EN_BS3)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for bbu3-DTV mode
7448 }
7449 else
7450 {
7451 #ifdef VDEC3
7452 if (pCtrl->u32BBUId > 3)
7453 printf("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
7454 #else
7455 if (u8TaskId > 3)
7456 printf("Error u8TaskId = %d , %s:%d\n",u8TaskId,__FUNCTION__,__LINE__);
7457 #endif
7458 _HVD_Write2Byte(EVD_BBU23_SETTING, (_HVD_Read2Byte(EVD_BBU23_SETTING) & ~REG_TSP2EVD_EN_BS4)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for bbu4-DTV mode
7459 }
7460 return;
7461 }
7462
HAL_EVD_EX_DeinitHW(MS_U32 u32Id)7463 MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id)
7464 {
7465 MS_U16 u16Timeout = 1000;
7466 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7467 MS_BOOL isVP8Used = FALSE;
7468 MS_BOOL isAECUsed = FALSE;
7469 MS_BOOL isAVCUsed = FALSE;
7470 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
7471
7472 if(TRUE == HAL_VPU_EX_EVDInUsed())
7473 {
7474 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7475 {
7476 HAL_AEC_PowerCtrl(FALSE);
7477 }
7478 return FALSE;
7479 }
7480 else if(!isAVCUsed)
7481 {
7482 _HVD_EX_SetMIUProtectMask(TRUE);
7483 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
7484
7485 while (u16Timeout)
7486 {
7487 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
7488 {
7489 break;
7490 }
7491 u16Timeout--;
7492 }
7493 #ifdef CONFIG_MSTAR_CLKM
7494 HAL_EVD_EX_PowerCtrl_CLKM(u32Id, FALSE);
7495 #else
7496 HAL_EVD_EX_PowerCtrl(u32Id, FALSE);
7497 #endif
7498
7499 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7500 {
7501 HAL_AEC_PowerCtrl(FALSE);
7502 }
7503
7504 _HVD_EX_SetMIUProtectMask(FALSE);
7505 return TRUE;
7506 }
7507
7508 return FALSE;
7509 }
7510 #endif
7511
7512 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)7513 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
7514 {
7515 if (bEnable)
7516 {
7517 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
7518 }
7519 else
7520 {
7521 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
7522 }
7523
7524 switch (pHVDHalContext->u32VP9ClockType)
7525 {
7526 case 432:
7527 {
7528 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
7529 break;
7530 }
7531 case 384:
7532 {
7533 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
7534 break;
7535 }
7536 case 345:
7537 {
7538 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
7539 break;
7540 }
7541 case 320:
7542 {
7543 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
7544 break;
7545 }
7546 case 288:
7547 {
7548 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
7549 break;
7550 }
7551 case 240:
7552 {
7553 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
7554 break;
7555 }
7556 case 216:
7557 {
7558 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
7559 break;
7560 }
7561 case 172:
7562 {
7563 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
7564 break;
7565 }
7566 default:
7567 {
7568 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
7569 break;
7570 }
7571 }
7572
7573 return;
7574 }
7575
HAL_VP9_EX_DeinitHW(void)7576 MS_BOOL HAL_VP9_EX_DeinitHW(void)
7577 {
7578 MS_U16 u16Timeout = 1000;
7579
7580 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
7581
7582 while (u16Timeout)
7583 {
7584 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
7585 {
7586 break;
7587 }
7588 u16Timeout--;
7589 }
7590
7591 HAL_VP9_EX_PowerCtrl(FALSE);
7592
7593 return TRUE;
7594 }
7595 #endif
7596
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)7597 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
7598 {
7599 return TRUE;
7600 }
7601
HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)7602 void HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)
7603 {
7604 MS_VIRT u32StAddr = 0;
7605 MS_U8 u8BitMiuSel = 0;
7606 MS_U8 u8CodeMiuSel = 0;
7607 MS_U8 u8TmpMiuSel = 0;
7608 MS_U32 u32BitStartOffset;
7609 MS_U32 u32CodeStartOffset;
7610
7611 #ifndef VDEC3
7612 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
7613 #endif
7614 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7615 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7616 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
7617 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7618
7619 _HAL_HVD_Entry();
7620
7621 if (pCtrl == NULL)
7622 {
7623 _HAL_HVD_Return();
7624 }
7625
7626 MS_BOOL bNalTblAlreadySet = FALSE;
7627 VPU_EX_TaskInfo taskInfo;
7628 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
7629 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
7630
7631 bNalTblAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
7632
7633
7634
7635 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
7636 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
7637
7638 if (u8BitMiuSel != u8CodeMiuSel)
7639 {
7640 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
7641 }
7642 else
7643 {
7644 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
7645 }
7646
7647 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7648 {
7649 #ifdef VDEC3
7650 if (!_HAL_EX_BBU_VP8_InUsed())
7651 #endif
7652 {
7653 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
7654
7655 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
7656 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
7657 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7658
7659 u32StAddr += VP8_BBU_TBL_SIZE;
7660
7661 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
7662 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
7663 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7664 }
7665
7666 _HAL_HVD_Return();
7667 }
7668
7669 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
7670
7671 #ifdef VDEC3
7672 if (!bNalTblAlreadySet)
7673 {
7674 _HVD_Write2Byte(_HVD_EX_Get_NAL_TBL_ST_ADDR_L(u32Id), (MS_U16) (u32StAddr >> 3));
7675 _HVD_Write2Byte(_HVD_EX_Get_NAL_TBL_ST_ADDR_H(u32Id), (MS_U16) (u32StAddr >> 19));
7676 // -1 is for NAL_TAB_LEN counts from zero.
7677 _HVD_Write2Byte(_HVD_EX_Get_NAL_TAB_LEN(u32Id), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7678 }
7679 #else
7680 if (0 == u8TaskId)
7681 {
7682 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
7683 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
7684 // -1 is for NAL_TAB_LEN counts from zero.
7685 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7686 }
7687 else
7688 {
7689 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
7690 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
7691 // -1 is for NAL_TAB_LEN counts from zero.
7692 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7693 }
7694 #endif
7695
7696
7697 #if (HVD_ENABLE_MVC)
7698 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
7699 {
7700 /// Used sub stream to record sub view data.
7701 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
7702 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
7703
7704 if (u8BitMiuSel != u8CodeMiuSel)
7705 {
7706 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
7707 }
7708 else
7709 {
7710 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
7711 }
7712
7713 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
7714 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
7715 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
7716 // -1 is for NAL_TAB_LEN counts from zero.
7717 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
7718 }
7719 #endif
7720
7721 if (!bNalTblAlreadySet)
7722 {
7723 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
7724 }
7725
7726 _HAL_HVD_Return();
7727 }
7728
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)7729 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
7730 {
7731 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7732
7733 if(pCtrl->InitParams.u16ChipECONum == 0)
7734 return FALSE;
7735 else
7736 return TRUE;
7737 }
7738
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)7739 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
7740 {
7741
7742 }
7743
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)7744 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
7745 {
7746
7747 }
7748 #endif
7749