1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include <string.h>
104 #endif
105
106 #if defined(REDLION_LINUX_KERNEL_ENVI)
107 #include "drvHVD_Common.h"
108 #else
109 #include "MsCommon.h"
110 #endif
111
112 #include "MsOS.h"
113 #include "asmCPU.h"
114
115
116 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
117
118 // Internal Definition
119 #include "regVPU_EX.h"
120 #include "halVPU_EX.h"
121 #include "halCHIP.h"
122 #include "drvSYS.h"
123 #if defined(VDEC3)
124 #include "../../../drv/hvd_v3/drvHVD_def.h"
125 #include "../hvd_v3/fwHVD_if.h"
126 #include "../mvd_v3/mvd4_interface.h"
127 #include "halHVD_EX.h"
128 #else
129 #include "../../../drv/hvd_v3/drvHVD_def.h"
130 #include "../hvd_v3/fwHVD_if.h"
131 #include "../mvd_v3/mvd4_interface.h"
132 #endif
133 #include "controller.h"
134
135 #if (ENABLE_DECOMPRESS_FUNCTION == TRUE)
136 #include "ms_decompress.h"
137 #include "ms_decompress_priv.h"
138 #endif
139 #include "../../drv/mbx/apiMBX_St.h"
140 #include "../../drv/mbx/apiMBX.h"
141
142 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
143 #include "drvSERFLASH.h"
144 #define HVD_FLASHcpy(DESTADDR, SRCADDR, LEN, Flag) MDrv_SERFLASH_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), SPIDMA_OPCFG_DEF)
145 #endif
146
147 #ifdef MSOS_TYPE_LINUX_KERNEL
148 #define VPRINTF printk
149 #else
150 #ifndef ANDROID
151 #define VPRINTF printf
152 #else
153 #include <sys/mman.h>
154 #include <cutils/ashmem.h>
155 #include <cutils/log.h>
156 #define VPRINTF ALOGD
157 #endif
158 #endif
159
160 #ifdef CONFIG_MSTAR_CLKM
161 #include "drvCLKM.h"
162 #endif
163 //-------------------------------------------------------------------------------------------------
164 // Driver Compiler Options
165 //-------------------------------------------------------------------------------------------------
166
167
168 //-------------------------------------------------------------------------------------------------
169 // Local Defines
170 //-------------------------------------------------------------------------------------------------
171 #define VPU_CTL_INTERFACE_VER 0x00000001 //the interface version of VPU driver
172
173 #define VPU_MIU1BASE_ADDR 0x40000000UL //Notice: this define must be comfirm with designer
174 #ifdef VDEC3
175 #define MAX_EVD_BBU_COUNT 2 // This definition is chip-dependent.
176 #define MAX_HVD_BBU_COUNT 2 // The Chip after Monaco(included) have two EVD BBU, must check this definition when bring up
177 #define MAX_MVD_SLQ_COUNT 2
178 #define MAX_SUPPORT_DECODER_NUM 16
179 #else
180 #define MAX_SUPPORT_DECODER_NUM 2
181 #endif
182 typedef enum
183 {
184 E_VDEC_EX_REE_TO_TEE_MBX_MSG_NULL,
185 E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode,
186 E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR,
187 } VDEC_REE_TO_TEE_MBX_MSG_TYPE;
188
189
190 typedef enum
191 {
192 E_VDEC_EX_TEE_TO_REE_MBX_MSG_NULL,
193 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID,
194 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE,
195 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS,
196 E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL
197 } VDEC_TEE_TO_REE_MBX_ACK_TYPE;
198
199 typedef enum
200 {
201 E_VPU_UART_CTRL_DISABLE = BIT(4),
202 E_VPU_UART_CTRL_ERR = BIT(0),
203 E_VPU_UART_CTRL_INFO = BIT(1),
204 E_VPU_UART_CTRL_DBG = BIT(2),
205 E_VPU_UART_CTRL_FW = BIT(3),
206 E_VPU_UART_CTRL_MUST = BIT(4),
207 E_VPU_UART_CTRL_TRACE = BIT(5),
208 } VPU_EX_UartCtrl;
209
210 typedef struct
211 {
212 HAL_VPU_StreamId eStreamId;
213 VPU_EX_DecoderType eDecodertype;
214 } VPU_EX_Stream;
215
216 typedef struct
217 {
218 MS_BOOL bSTCSetMode;
219 MS_U32 u32STCIndex;
220 } VPU_EX_STC;
221
222 #define VPU_MSG_ERR(format, args...) \
223 do \
224 { \
225 if (u32VpuUartCtrl & E_VPU_UART_CTRL_ERR) \
226 { \
227 printf("[VPU][ERR]%s:", __FUNCTION__); \
228 printf(format, ##args); \
229 } \
230 } while (0)
231
232 #define VPU_MSG_DBG(format, args...) \
233 do \
234 { \
235 if (u32VpuUartCtrl & E_VPU_UART_CTRL_DBG) \
236 { \
237 printf("[VPU][DBG]%s:", __FUNCTION__); \
238 printf(format, ##args); \
239 } \
240 } while (0)
241
242 #define VPU_MSG_INFO(format, args...) \
243 do \
244 { \
245 if (u32VpuUartCtrl & E_VPU_UART_CTRL_INFO) \
246 { \
247 printf("[VPU][INF]%s:", __FUNCTION__); \
248 printf(format, ##args); \
249 } \
250 } while (0)
251
252 //------------------------------ MIU SETTINGS ----------------------------------
253 #ifdef EVDR2
254 #define _MaskMiuReq_VPU_D_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
255 #define _MaskMiuReq_VPU_Q_RW(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK, m, BIT(6))
256 #define _MaskMiuReq_VPU_I_R(m) _VPU_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(0))
257
258 #define _MaskMiu1Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
259 #define _MaskMiu1Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK, m, BIT(6))
260 #define _MaskMiu1Req_VPU_I_R(m) _VPU_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(0))
261
262 #define _MaskMiu2Req_VPU_D_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
263 #define _MaskMiu2Req_VPU_Q_RW(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK, m, BIT(6))
264 #define _MaskMiu2Req_VPU_I_R(m) _VPU_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(0))
265
266
267 #define VPU_D_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
268 #define VPU_Q_RW_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
269 #define VPU_I_R_ON_MIU0 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)) //g08
270 #define VPU_D_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
271 #define VPU_Q_RW_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == BIT(6)) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == 0))
272 #define VPU_I_R_ON_MIU1 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == BIT(0)) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == 0)) //g08
273 #define VPU_D_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == BIT(6)))
274 #define VPU_Q_RW_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0) & BIT(6)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0) & BIT(6)) == BIT(6)))
275 #define VPU_I_R_ON_MIU2 (((_VPU_ReadByte(MIU0_REG_SEL0+1) & BIT(0)) == 0) && ((_VPU_ReadByte(MIU2_REG_SEL0+1) & BIT(0)) == BIT(0))) //g08
276 #endif
277
278
279
280 #define _VPU_MIU_SetReqMask(miu_clients, mask) \
281 do \
282 { \
283 if (miu_clients##_ON_MIU0 == 1) \
284 { \
285 _MaskMiuReq_##miu_clients(mask); \
286 } \
287 else \
288 { \
289 if (miu_clients##_ON_MIU1 == 1) \
290 { \
291 _MaskMiu1Req_##miu_clients(mask); \
292 } \
293 else if (miu_clients##_ON_MIU2 == 1) \
294 { \
295 _MaskMiu2Req_##miu_clients(mask); \
296 } \
297 } \
298 } while(0)
299
300
301
302
303 #if ENABLE_VPU_MUTEX_PROTECTION
304 MS_S32 s32VPUMutexID = -1;
305 MS_U8 _u8VPU_Mutex[] = { "VPU_Mutex" };
306
307 #define _HAL_VPU_MutexCreate() \
308 if (s32VPUMutexID < 0) \
309 { \
310 s32VPUMutexID = MsOS_CreateMutex(E_MSOS_FIFO,(char*)_u8VPU_Mutex, MSOS_PROCESS_SHARED); \
311 }
312
313 #define _HAL_VPU_MutexDelete() \
314 if (s32VPUMutexID >= 0) \
315 { \
316 MsOS_DeleteMutex(s32VPUMutexID); \
317 s32VPUMutexID = -1; \
318 }
319
320 #define _HAL_VPU_Entry() \
321 if (s32VPUMutexID >= 0) \
322 { \
323 if (!MsOS_ObtainMutex(s32VPUMutexID, VPU_DEFAULT_MUTEX_TIMEOUT)) \
324 { \
325 printf("[HAL VPU][%06d] Mutex taking timeout\n", __LINE__); \
326 } \
327 }
328
329 #define _HAL_VPU_Return(_ret) \
330 { \
331 if (s32VPUMutexID >= 0) \
332 { \
333 MsOS_ReleaseMutex(s32VPUMutexID); \
334 } \
335 return _ret; \
336 }
337
338 #define _HAL_VPU_Release() \
339 { \
340 if (s32VPUMutexID >= 0) \
341 { \
342 MsOS_ReleaseMutex(s32VPUMutexID); \
343 } \
344 }
345 #else
346 #define _HAL_VPU_MutexCreate()
347 #define _HAL_VPU_MutexDelete()
348 #define _HAL_VPU_Entry()
349 #define _HAL_VPU_Return(_ret) {return _ret;}
350 #define _HAL_VPU_Release()
351 #endif
352
353 #define VPU_FW_MEM_OFFSET 0x100000UL // 1M
354 #define VPU_CMD_TIMEOUT 1000 // 1 sec
355
356 //-------------------------------------------------------------------------------------------------
357 // Local Structures
358 //-------------------------------------------------------------------------------------------------
359 typedef struct _VPU_HWInitFunc
360 {
361 MS_BOOL (*pfMVDHW_Init)(void);
362 MS_BOOL (*pfMVDHW_Deinit)(void);
363 MS_BOOL (*pfHVDHW_Init)(MS_U32 u32Arg);
364 MS_BOOL (*pfHVDHW_Deinit)(void);
365 } VPU_HWInitFunc;
366
367 typedef struct
368 {
369 MS_U32 u32ApiHW_Version; //<Version of current structure>
370 MS_U16 u16ApiHW_Length; //<Length of this structure>
371
372 MS_U8 u8Cap_Support_Decoder_Num;
373
374 MS_BOOL bCap_Support_MPEG2;
375 MS_BOOL bCap_Support_H263;
376 MS_BOOL bCap_Support_MPEG4;
377 MS_BOOL bCap_Support_DIVX311;
378 MS_BOOL bCap_Support_DIVX412;
379 MS_BOOL bCap_Support_FLV;
380 MS_BOOL bCap_Support_VC1ADV;
381 MS_BOOL bCap_Support_VC1MAIN;
382
383 MS_BOOL bCap_Support_RV8;
384 MS_BOOL bCap_Support_RV9;
385 MS_BOOL bCap_Support_H264;
386 MS_BOOL bCap_Support_AVS;
387 MS_BOOL bCap_Support_AVS_PLUS;
388 MS_BOOL bCap_Support_MJPEG;
389 MS_BOOL bCap_Support_MVC;
390 MS_BOOL bCap_Support_VP8;
391 MS_BOOL bCap_Support_VP9;
392 MS_BOOL bCap_Support_HEVC;
393
394 /*New HW Cap and Feature add in struct at the end*/
395 }VDEC_HwCap;
396
397 //-------------------------------------------------------------------------------------------------
398 // Local Functions Prototype
399 //-------------------------------------------------------------------------------------------------
400 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType);
401 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id);
402 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo);
403
404 //-------------------------------------------------------------------------------------------------
405 // Global Variables
406 //-------------------------------------------------------------------------------------------------
407 extern HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg);
408 extern MS_BOOL HAL_MVD_InitHW(VPU_EX_SourceType SourceType,VPU_EX_DecoderType eDecType);
409 extern MS_BOOL HAL_MVD_DeinitHW(VPU_EX_SourceType SourceType, VPU_EX_DecoderType eDecType);
410 extern MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType);
411 extern MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id);
412 extern MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id);
413 extern MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id);
414 #if SUPPORT_G2VP9 && defined(VDEC3)
415 extern MS_BOOL HAL_VP9_EX_DeinitHW(void);
416 #endif
417 #if defined (__aeon__)
418 static MS_VIRT u32VPURegOSBase = 0xA0000000UL;
419 #else
420 static MS_VIRT u32VPURegOSBase = 0xBF200000UL;
421 #endif
422
423 //-------------------------------------------------------------------------------------------------
424 // Local Variables
425 //-------------------------------------------------------------------------------------------------
426 #if 0
427
428 static MS_BOOL _bVPUPowered = FALSE;
429 static MS_BOOL _bVPURsted = FALSE;
430 static MS_BOOL _bVPUSingleMode = FALSE;
431 static VPU_EX_DecModCfg _stVPUDecMode;
432
433 static MS_U8 u8TaskCnt = 0;
434
435 static MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
436
437 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
438 static VPU_EX_Stream _stVPUStream[] =
439 {
440 {E_HAL_VPU_MAIN_STREAM0, E_VPU_EX_DECODER_NONE},
441 {E_HAL_VPU_SUB_STREAM0, E_VPU_EX_DECODER_NONE},
442 };
443 static VPU_HWInitFunc stHWInitFunc =
444 {
445 &HAL_MVD_InitHW,
446 &HAL_MVD_DeinitHW,
447 &HAL_HVD_EX_InitHW,
448 &HAL_HVD_EX_DeinitHW,
449 };
450
451 #endif
452
453 #if VPU_ENABLE_EMBEDDED_FW_BINARY
454 static const MS_U8 u8HVD_FW_Binary[] = {
455 #include "fwVPU.dat"
456 };
457
458 #if HVD_ENABLE_RV_FEATURE
459 static const MS_U8 u8HVD_VLC_Binary[] = {
460 #include "fwVPU_VLC.dat"
461 };
462 #endif
463 #endif
464
465
466 #ifdef VDEC3
467 typedef struct
468 {
469 MS_BOOL bTSP;
470 MS_U8 u8RegSetting; //NAL_TBL: BIT(0), ES_BUFFER: BIT(1)
471 MS_U32 u32Used;
472 } BBU_STATE;
473
474 typedef struct
475 {
476 MS_BOOL bTSP;
477 MS_BOOL bUsedbyMVD;
478 MS_U32 u32Used;
479 } SLQ_STATE;
480 #endif
481
482 typedef struct
483 {
484 MS_BOOL _bVPUPowered;
485 MS_BOOL _bVPURsted;
486 MS_BOOL _bVPUSingleMode;
487 VPU_EX_DecModCfg _stVPUDecMode;
488 MS_U8 u8TaskCnt;
489 //Notice: this function must be consistent with _VPU_EX_GetOffsetIdx()
490 #ifdef VDEC3
491 VPU_EX_Stream _stVPUStream[MAX_SUPPORT_DECODER_NUM];
492 #else
493 VPU_EX_Stream _stVPUStream[2];
494 #endif
495
496 VPU_HWInitFunc stHWInitFunc;
497
498 MS_BOOL bVpuExReloadFW;
499 MS_BOOL bVpuExLoadFWRlt;
500 MS_VIRT u32VPUSHMAddr; //PA
501 MS_BOOL bEnableVPUSecureMode;
502
503 MS_VIRT u32FWShareInfoAddr[MAX_SUPPORT_DECODER_NUM];
504 MS_BOOL bEnableDymanicFBMode;
505 MS_PHY u32DynamicFBAddress;
506 MS_U32 u32DynamicFBSize;
507 #ifdef VDEC3
508 MS_VIRT u32FWCodeAddr;
509 MS_VIRT u32BitstreamAddress[MAX_SUPPORT_DECODER_NUM];
510
511 BBU_STATE stHVD_BBU_STATE[MAX_HVD_BBU_COUNT];
512 BBU_STATE stEVD_BBU_STATE[MAX_EVD_BBU_COUNT];
513 SLQ_STATE stMVD_SLQ_STATE[MAX_MVD_SLQ_COUNT];
514
515 MS_U8 u8HALId[MAX_SUPPORT_DECODER_NUM];
516 #endif
517 MS_U8 u8ForceRst;
518 VPU_EX_STC _stVPUSTCMode[MAX_SUPPORT_DECODER_NUM];
519 } VPU_Hal_CTX;
520
521 //global variables
522 VPU_Hal_CTX* pVPUHalContext = NULL;
523 VPU_Hal_CTX gVPUHalContext;
524 MS_U32 u32VpuUartCtrl = (E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_MUST);
525 MS_BOOL bVPUMbxInitFlag = 0;
526 MS_U8 u8VPUMbxMsgClass = 0;
527 MBX_Msg VPUReeToTeeMbxMsg;
528 MBX_Msg VPUTeeToReeMbxMsg;
529
530 //-------------------------------------------------------------------------------------------------
531 // Debug Functions
532 //-------------------------------------------------------------------------------------------------
533
534
535 //-------------------------------------------------------------------------------------------------
536 // Local Functions
537 //-------------------------------------------------------------------------------------------------
538
_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)539 static MS_BOOL _VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
540 {
541 #if HVD_ENABLE_RV_FEATURE
542 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
543 {
544 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
545 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
546 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
547
548 if (pVlcCfg->u32BinSize)
549 {
550 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
551
552 MS_U32 u32Start;
553 MS_U32 u32StartOffset;
554 MS_U8 u8MiuSel;
555
556 // Get MIU selection and offset from physical address = 0x30000000
557 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pVlcCfg->u32FrameBufAddr);
558
559
560 if(u8MiuSel == E_CHIP_MIU_0)
561 cpyflag = E_SPIDMA_DEV_MIU0;
562 else if(u8MiuSel == E_CHIP_MIU_1)
563 cpyflag = E_SPIDMA_DEV_MIU1;
564 else if(u8MiuSel == E_CHIP_MIU_2)
565 cpyflag = E_SPIDMA_DEV_MIU2;
566
567 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
568 {
569 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
570 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
571
572 return FALSE;
573 }
574 }
575 else
576 {
577 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
578 return FALSE;
579 }
580 #else
581 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
582 return FALSE;
583 #endif
584 }
585 else
586 {
587 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
588 {
589 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
590 {
591 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
592 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
593
594 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
595 BDMA_Result bdmaRlt;
596 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
597
598 u32DstAdd = pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset;
599 u32SrcAdd = pVlcCfg->u32BinAddr;
600 u32tabsize = pVlcCfg->u32BinSize;
601 //bdmaRlt = MDrv_BDMA_MemCopy(u32SrcAdd, u32DstAdd, SLQ_TBL_SIZE);
602 MsOS_FlushMemory();
603 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
604
605 if (E_BDMA_OK != bdmaRlt)
606 {
607 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
608 }
609 #else
610 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
611 #endif
612 }
613 else
614 {
615 VPU_MSG_ERR
616 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
617 return FALSE;
618 }
619 }
620 else
621 {
622 #if VPU_ENABLE_EMBEDDED_FW_BINARY
623 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
624 MS_U8 *pu8HVD_VLC_Binary;
625
626 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
627
628 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
629 pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset, ((MS_U32) pu8HVD_VLC_Binary),
630 (MS_U32) sizeof(u8HVD_VLC_Binary));
631
632 HVD_memcpy((void *) (pVlcCfg->u32FrameBufAddr + pVlcCfg->u32VLCTableOffset),
633 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
634 #else
635 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
636 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long)u8HVD_VLC_Binary,
637 (MS_U32) sizeof(u8HVD_VLC_Binary));
638
639 HVD_memcpy(pVlcCfg->u32DstAddr, ((unsigned long)u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
640 #endif
641 #else
642 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
643 return FALSE;
644 #endif
645 }
646 }
647 #endif
648
649 return TRUE;
650 }
651
652 //Notice: this function must be consistent with _stVPUStream[]
_VPU_EX_GetOffsetIdx(MS_U32 u32Id)653 MS_U8 _VPU_EX_GetOffsetIdx(MS_U32 u32Id)
654 {
655 MS_U8 u8OffsetIdx = 0;
656 MS_U8 u8VSidBaseMask = 0xF0;
657 HAL_VPU_StreamId eVSidBase = (HAL_VPU_StreamId)(u32Id & u8VSidBaseMask);
658
659 switch (eVSidBase)
660 {
661 case E_HAL_VPU_MAIN_STREAM_BASE:
662 {
663 u8OffsetIdx = 0;
664 break;
665 }
666 case E_HAL_VPU_SUB_STREAM_BASE:
667 {
668 u8OffsetIdx = 1;
669 break;
670 }
671 case E_HAL_VPU_MVC_STREAM_BASE:
672 {
673 u8OffsetIdx = 0;
674 break;
675 }
676 #ifdef VDEC3
677 case E_HAL_VPU_N_STREAM_BASE:
678 {
679 u8OffsetIdx = u32Id & 0x0F;
680 break;
681 }
682 #endif
683 default:
684 {
685 u8OffsetIdx = 0;
686 break;
687 }
688 }
689
690 /*
691 VPU_MSG_DBG("u32Id=0x%lx, eVSidBase=0x%x, u8OffsetIdx=0x%x\n",
692 u32Id, eVSidBase, u8OffsetIdx);
693 */
694 return u8OffsetIdx;
695 }
696
HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)697 MS_U8 HAL_VPU_EX_GetOffsetIdx(MS_U32 u32Id)
698 {
699 return _VPU_EX_GetOffsetIdx(u32Id);
700 }
701
_VPU_EX_Context_Init(void)702 static void _VPU_EX_Context_Init(void)
703 {
704 #ifdef VDEC3
705 MS_U8 i;
706
707 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
708 {
709 pVPUHalContext->_stVPUStream[i].eStreamId = E_HAL_VPU_N_STREAM0 + i;
710 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
711 }
712
713 for (i = 0; i < MAX_HVD_BBU_COUNT; i++)
714 {
715 pVPUHalContext->stHVD_BBU_STATE[i].bTSP = FALSE;
716 pVPUHalContext->stHVD_BBU_STATE[i].u32Used = 0;
717 }
718
719 for (i = 0; i < MAX_EVD_BBU_COUNT; i++)
720 {
721 pVPUHalContext->stEVD_BBU_STATE[i].bTSP = FALSE;
722 pVPUHalContext->stEVD_BBU_STATE[i].u32Used = 0;
723 }
724
725 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
726 {
727 pVPUHalContext->stMVD_SLQ_STATE[i].bTSP = FALSE;
728 pVPUHalContext->stMVD_SLQ_STATE[i].bUsedbyMVD= FALSE;
729 pVPUHalContext->stMVD_SLQ_STATE[i].u32Used = 0;
730 }
731 #else
732 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MAIN_STREAM0;
733 pVPUHalContext->_stVPUStream[1].eStreamId = E_HAL_VPU_SUB_STREAM0;
734 #endif
735 pVPUHalContext->bVpuExReloadFW = TRUE;
736 pVPUHalContext->u8ForceRst = 0;
737
738 }
739
HAL_VPU_EX_ForceSwRst(void)740 void HAL_VPU_EX_ForceSwRst(void)
741 {
742 pVPUHalContext->u8ForceRst = 1;
743 }
744
_VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo * pTaskInfo)745 static HVD_User_Cmd _VPU_EX_MapCtrlCmd(VPU_EX_TaskInfo *pTaskInfo)
746 {
747 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
748 MS_U8 u8OffsetIdx = 0;
749
750 if (NULL == pTaskInfo)
751 {
752 return eCmd;
753 }
754
755 u8OffsetIdx = _VPU_EX_GetOffsetIdx(pTaskInfo->u32Id);
756
757 VPU_MSG_INFO("input TaskInfo u32Id=0x%08x eVpuId=0x%x src=0x%x dec=0x%x\n",
758 pTaskInfo->u32Id, pTaskInfo->eVpuId, pTaskInfo->eSrcType, pTaskInfo->eDecType);
759
760 #ifdef VDEC3
761 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
762 {
763 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
764 {
765 eCmd = E_NST_CMD_TASK_MVD_TSP;
766 }
767 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
768 {
769 eCmd = E_NST_CMD_TASK_MVD_SLQ;
770 }
771 }
772 #else
773 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
774 {
775 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
776 {
777 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_TSP : E_DUAL_CMD_TASK1_MVD_TSP;
778 }
779 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
780 {
781 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_MVD_SLQ : E_DUAL_CMD_TASK1_MVD_SLQ;
782 }
783 }
784 #endif
785 #ifdef VDEC3
786 #if SUPPORT_G2VP9
787 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
788 #else
789 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
790 #endif
791 {
792 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
793 {
794 eCmd = E_NST_CMD_TASK_HVD_TSP;
795 }
796 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
797 {
798 eCmd = E_NST_CMD_TASK_HVD_BBU;
799 }
800 }
801 #else
802 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
803 {
804 if (E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType)
805 {
806 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_TSP : E_DUAL_CMD_TASK1_HVD_TSP;
807 }
808 else if (E_VPU_EX_INPUT_FILE == pTaskInfo->eSrcType)
809 {
810 eCmd = (u8OffsetIdx == 0) ? E_DUAL_CMD_TASK0_HVD_BBU : E_DUAL_CMD_TASK1_HVD_BBU;
811 }
812 }
813 #endif
814
815 VPU_MSG_INFO("output: eCmd=0x%x offsetIdx=0x%x\n", eCmd, u8OffsetIdx);
816 return eCmd;
817 }
818
_VPU_EX_InitHW(VPU_EX_TaskInfo * pTaskInfo)819 static MS_BOOL _VPU_EX_InitHW(VPU_EX_TaskInfo *pTaskInfo)
820 {
821 if (!pTaskInfo)
822 {
823 VPU_MSG_ERR("null input\n");
824 return FALSE;
825 }
826
827 //Check if we need to init MVD HW
828 if ((E_VPU_EX_INPUT_TSP == pTaskInfo->eSrcType) ||
829 (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType))
830 {
831 //Init HW
832 if (FALSE == HAL_VPU_EX_MVDInUsed())
833 {
834 if (TRUE != HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
835 {
836 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
837 return FALSE;
838 }
839 }
840 else
841 {
842 VPU_MSG_ERR("(%d): do nothing\n", __LINE__);
843 }
844 }
845
846 //MVD use sub mvop
847 if((E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType) &&
848 #ifdef VDEC3
849 (pTaskInfo->u8HalId == 1) )
850 #else
851 (E_HAL_VPU_SUB_STREAM0 == pTaskInfo->eVpuId))
852 #endif
853 {
854 VPU_MSG_ERR("Force turn on HVD\n");
855 if(!HAL_VPU_EX_HVDInUsed())
856 {
857 if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
858 {
859 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
860 {
861 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
862 return FALSE;
863 }
864 }
865 else
866 {
867 VPU_MSG_INFO("%s MVD 3DTV sub\n",__FUNCTION__);
868 #ifdef CONFIG_MSTAR_CLKM
869 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
870 #else
871 HAL_HVD_EX_PowerCtrl(pTaskInfo->u32Id, TRUE);
872 #endif
873 }
874 }
875 else
876 {
877 VPU_MSG_ERR("(%d): do nothing, HVD already init\n", __LINE__);
878 }
879 }
880
881 //Check if we need to init HVD HW
882 #ifdef VDEC3
883 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
884 #else
885 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
886 #endif
887 {
888 if (!HAL_VPU_EX_MVDInUsed())
889 {
890 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
891 {
892 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
893 return FALSE;
894 }
895 }
896
897 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
898 {
899 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed\n", __LINE__);
900 return FALSE;
901 }
902 #if SUPPORT_MSVP9
903 if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
904 {
905 _VPU_WriteWordMask(REG_CLKGEN1_RESERVERD0, SELECT_CLK_HVD_AEC_P_216, SELECT_CLK_HVD_AEC_P_MASK); //for VP9 dqmem
906 }
907 #endif
908 }
909
910 #if SUPPORT_G2VP9 && defined(VDEC3)
911 if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
912 {
913 if (!HAL_VPU_EX_MVDInUsed())
914 {
915 if (!HAL_MVD_InitHW(pTaskInfo->eSrcType,pTaskInfo->eDecType))
916 {
917 VPU_MSG_ERR("(%d):HAL_MVD_InitHW failed\n", __LINE__);
918 return FALSE;
919 }
920 }
921 if (!HAL_HVD_EX_InitHW(pTaskInfo->u32Id,pTaskInfo->eDecType))
922 {
923 VPU_MSG_ERR("(%d):HAL_HVD_EX_InitHW failed for VP9\n", __LINE__);
924 return FALSE;
925 }
926 }
927 #endif
928
929 return TRUE;
930 }
931
_VPU_EX_InClock(MS_U32 u32type)932 static MS_U32 _VPU_EX_InClock(MS_U32 u32type)
933 {
934 switch (u32type)
935 {
936 case VPU_CLOCK_240MHZ:
937 return 240000000UL;
938 case VPU_CLOCK_216MHZ:
939 return 216000000UL;
940 case VPU_CLOCK_192MHZ:
941 return 192000000UL;
942 case VPU_CLOCK_12MHZ:
943 return 12000000UL;
944 case VPU_CLOCK_320MHZ:
945 return 320000000UL;
946 case VPU_CLOCK_288MHZ:
947 return 288000000UL;
948 case VPU_CLOCK_432MHZ:
949 return 432000000UL;
950 default:
951 return 384000000UL;
952 }
953 }
954
955
956 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_LINUX_KERNEL)
957 //For REE
HAL_VPU_EX_REE_RegisterMBX(void)958 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void)
959 {
960 //#ifndef MSOS_TYPE_LINUX_KERNEL
961 #if 1
962 MS_U8 ClassNum = 0;
963 MBX_Result result;
964
965 #if 0
966 if (bVPUMbxInitFlag == TRUE)
967 {
968 return TRUE;
969 }
970 #endif
971
972 if (E_MBX_SUCCESS != MApi_MBX_Init(E_MBX_CPU_MIPS,E_MBX_ROLE_HK,1000))
973 {
974 VPU_MSG_ERR("VDEC_TEE MApi_MBX_Init fail\n");
975 return FALSE;
976 }
977 else
978 {
979 MApi_MBX_Enable(TRUE);
980 }
981
982 result = MApi_MBX_QueryDynamicClass(E_MBX_CPU_MIPS_VPE1, "VDEC_TEE", (MS_U8 *)&ClassNum);
983
984 if (E_MBX_SUCCESS != result)
985 {
986 VPU_MSG_ERR("VDEC_TEE MApi_MBX_QueryDynamicClass fail,result %d\n",(unsigned int)result);
987 return FALSE;
988 }
989
990 result = MApi_MBX_RegisterMSG(ClassNum, 10);
991
992 if (( E_MBX_SUCCESS != result) && ( E_MBX_ERR_SLOT_AREADY_OPENNED != result ))
993 {
994 VPU_MSG_ERR("%s fail\n",__FUNCTION__);
995 return FALSE;
996 }
997 else
998 {
999 bVPUMbxInitFlag = TRUE;
1000 u8VPUMbxMsgClass = ClassNum;
1001 return TRUE;
1002 }
1003 #else
1004 return FALSE;
1005 #endif
1006 }
1007
1008 //#ifdef MBX_2K
1009 #if 1
_VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)1010 VDEC_TEE_TO_REE_MBX_ACK_TYPE _VPU_EX_REE_SendMBXMsg(VDEC_REE_TO_TEE_MBX_MSG_TYPE msg_type)
1011 {
1012 MBX_Result result;
1013 VDEC_TEE_TO_REE_MBX_ACK_TYPE u8Index;
1014
1015 if (pVPUHalContext->bEnableVPUSecureMode == FALSE)
1016 {
1017 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_NO_TEE;
1018 }
1019
1020 if (bVPUMbxInitFlag == FALSE)
1021 {
1022 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_INVALID;
1023 }
1024
1025 VPUReeToTeeMbxMsg.eRoleID = E_MBX_CPU_MIPS_VPE1;
1026 VPUReeToTeeMbxMsg.u8Ctrl = 0;
1027 VPUReeToTeeMbxMsg.eMsgType = E_MBX_MSG_TYPE_INSTANT;
1028 VPUReeToTeeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1029 VPUReeToTeeMbxMsg.u8Index = msg_type;
1030
1031 result = MApi_MBX_SendMsg(&VPUReeToTeeMbxMsg);
1032 if (E_MBX_SUCCESS != result)
1033 {
1034 printf("VDEC_TEE Send MBX fail,result %d\n",(unsigned int)result);
1035 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1036 }
1037
1038 // Receive Reply ACK from TEE side.
1039 memset(&VPUTeeToReeMbxMsg, 0, sizeof(MBX_Msg));
1040
1041 VPUTeeToReeMbxMsg.u8MsgClass = u8VPUMbxMsgClass;
1042
1043 #if 0 // marked temperarily, wait kernel team to fix MApi_MBX_RecvMsg.
1044 if(E_MBX_SUCCESS != MApi_MBX_RecvMsg(TEE_MBX_MSG_CLASS, &(TEE_TO_REE_MBX_MSG), 20, MBX_CHECK_INSTANT_MSG))
1045 {
1046 VPU_MSG_ERR("VDEC get Secure world ACK fail\n");
1047 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1048 }
1049 else
1050 #else
1051 do
1052 {
1053 result = MApi_MBX_RecvMsg(u8VPUMbxMsgClass, &VPUTeeToReeMbxMsg, 2000, MBX_CHECK_INSTANT_MSG);
1054 } while(E_MBX_SUCCESS != result);
1055 #endif
1056 {
1057 u8Index = VPUTeeToReeMbxMsg.u8Index;
1058 VPU_MSG_DBG("VDEC get ACK cmd:%x\n", u8Index);
1059
1060 if (E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL == u8Index)
1061 {
1062 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_FAIL;
1063 }
1064 }
1065
1066 return E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS;
1067 }
1068 #endif
1069
HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)1070 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(MS_U32 U32Type,MS_PHY u32SHMAddr,MS_PHY u32SHMSize,MS_PHY u32MIU1Addr)
1071 {
1072 if(U32Type == SYS_TEEINFO_OSTYPE_NUTTX)
1073 {
1074 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_GETSHMBASEADDR) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1075 {
1076 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1077 return FALSE;
1078 }
1079 else
1080 {
1081 MS_VIRT u32VPUSHMoffset = (VPUTeeToReeMbxMsg.u8Parameters[0]&0xff) |
1082 ((VPUTeeToReeMbxMsg.u8Parameters[1]<<8)&0xff00)|
1083 ((VPUTeeToReeMbxMsg.u8Parameters[2]<<16)&0xff0000)|
1084 ((VPUTeeToReeMbxMsg.u8Parameters[3]<<24)&0xff000000);
1085 MS_U32 u32VPUSHMsize = (VPUTeeToReeMbxMsg.u8Parameters[4]&0xff) |
1086 ((VPUTeeToReeMbxMsg.u8Parameters[5]<<8)&0xff00)|
1087 ((VPUTeeToReeMbxMsg.u8Parameters[6]<<16)&0xff0000)|
1088 ((VPUTeeToReeMbxMsg.u8Parameters[7]<<24)&0xff000000);
1089
1090 VPU_MSG_INFO("u32VPUSHMoffset %lx,u32VPUSHMsize %x,miu %d\n",(unsigned long)u32VPUSHMoffset,(unsigned int)u32VPUSHMsize,VPUTeeToReeMbxMsg.u8Parameters[8]);
1091
1092
1093 MS_U32 u32Start;
1094
1095 if(VPUTeeToReeMbxMsg.u8Parameters[8] == 1)
1096 {
1097 _miu_offset_to_phy(E_CHIP_MIU_1, u32VPUSHMoffset, u32Start);
1098 pVPUHalContext->u32VPUSHMAddr = u32Start;
1099 }
1100 else if(VPUTeeToReeMbxMsg.u8Parameters[8] == 2)
1101 {
1102 _miu_offset_to_phy(E_CHIP_MIU_2, u32VPUSHMoffset, u32Start);
1103 pVPUHalContext->u32VPUSHMAddr = u32Start;
1104
1105 }
1106 else // == 0
1107 {
1108 pVPUHalContext->u32VPUSHMAddr = u32VPUSHMoffset;
1109 }
1110 }
1111 }
1112 else if(U32Type == SYS_TEEINFO_OSTYPE_OPTEE)
1113 {
1114 MS_U32 u32Offset;
1115 if((u32SHMAddr >= u32MIU1Addr) && (u32MIU1Addr!=0))
1116 {
1117 u32Offset = u32SHMAddr-u32MIU1Addr;
1118 _miu_offset_to_phy(E_CHIP_MIU_1, u32Offset, pVPUHalContext->u32VPUSHMAddr);
1119 }
1120 else
1121 {
1122 pVPUHalContext->u32VPUSHMAddr = u32SHMAddr;
1123 }
1124 }
1125 return TRUE;
1126 }
1127
HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)1128 MS_BOOL HAL_VPU_Set_MBX_param(MS_U8 u8APIMbxMsgClass)
1129 {
1130 bVPUMbxInitFlag = TRUE;
1131 u8VPUMbxMsgClass = u8APIMbxMsgClass;
1132 return TRUE;
1133 }
1134
1135 #endif
1136
HAL_VPU_EX_GetFWReload(void)1137 MS_BOOL HAL_VPU_EX_GetFWReload(void)
1138 {
1139 return pVPUHalContext->bVpuExReloadFW;
1140 }
1141
_VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)1142 static MS_BOOL _VPU_EX_IsNeedDecompress(MS_VIRT u32SrcAddr)
1143 {
1144 if(*((MS_U8*)(u32SrcAddr))=='V' && *((MS_U8*)(u32SrcAddr+1))=='D'
1145 && *((MS_U8*)(u32SrcAddr+2))=='E' && *((MS_U8*)(u32SrcAddr+3))=='C'
1146 && *((MS_U8*)(u32SrcAddr+4))=='3' && *((MS_U8*)(u32SrcAddr+5))=='1'
1147 && *((MS_U8*)(u32SrcAddr+0xe8))=='V' && *((MS_U8*)(u32SrcAddr+0xe9))=='D'
1148 && *((MS_U8*)(u32SrcAddr+0xea))=='E' && *((MS_U8*)(u32SrcAddr+0xeb))=='C'
1149 && *((MS_U8*)(u32SrcAddr+0xec))=='3' && *((MS_U8*)(u32SrcAddr+0xed))=='0'
1150 )
1151 {
1152 return FALSE;
1153 }
1154 else
1155 {
1156 return TRUE;
1157 }
1158 }
1159
_VPU_EX_InitAll(VPU_EX_NDecInitPara * pInitPara)1160 static MS_BOOL _VPU_EX_InitAll(VPU_EX_NDecInitPara *pInitPara)
1161 {
1162 MS_PHY u32fwPA = NULL; //physical address
1163 VPU_EX_ClockSpeed eClkSpeed = E_VPU_EX_CLOCK_432MHZ;
1164
1165 if (TRUE == HAL_VPU_EX_IsPowered())
1166 {
1167 VPU_MSG_DBG("IsPowered\n");
1168 return TRUE;
1169 }
1170 else
1171 {
1172 //VPU hold
1173 HAL_VPU_EX_SwRst(FALSE);
1174
1175 //VPU clock on
1176 VPU_EX_InitParam VPUInitParams = {eClkSpeed, FALSE, -1, VPU_DEFAULT_MUTEX_TIMEOUT, TRUE};
1177
1178 if (VPU_I_R_ON_MIU0)
1179 VPUInitParams.u8MiuSel = 0;
1180 else if (VPU_I_R_ON_MIU1)
1181 VPUInitParams.u8MiuSel = 1;
1182 else if (VPU_I_R_ON_MIU2)
1183 VPUInitParams.u8MiuSel = 2;
1184
1185 HAL_VPU_EX_Init(&VPUInitParams);
1186 }
1187
1188 VPU_EX_FWCodeCfg *pFWCodeCfg = NULL;
1189 VPU_EX_TaskInfo *pTaskInfo = NULL;
1190 VPU_EX_VLCTblCfg *pVlcCfg = NULL;
1191
1192 if (pInitPara)
1193 {
1194 pFWCodeCfg = pInitPara->pFWCodeCfg;
1195 pTaskInfo = pInitPara->pTaskInfo;
1196 pVlcCfg = pInitPara->pVLCCfg;
1197 }
1198 else
1199 {
1200 VPU_MSG_DBG("(%d) NULL para\n", __LINE__);
1201 return FALSE;
1202 }
1203
1204 u32fwPA = MsOS_VA2PA(pFWCodeCfg->u32DstAddr);
1205 //#ifdef MBX_2K
1206 #if 1
1207 #if (defined(MSOS_TYPE_LINUX)||defined(MSOS_TYPE_LINUX_KERNEL))
1208 if(pVPUHalContext->bEnableVPUSecureMode == TRUE)
1209 {
1210 SYS_TEEINFO teemode;
1211 MDrv_SYS_ReadKernelCmdLine();
1212 MDrv_SYS_GetTEEInfo(&teemode);
1213 if(teemode.OsType == SYS_TEEINFO_OSTYPE_NUTTX)
1214 {
1215 VPU_MSG_INFO("Load VDEC f/w code in Secure World\n");
1216
1217 if (FALSE == HAL_VPU_EX_GetFWReload())
1218 {
1219 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
1220 {
1221 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
1222 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1223 {
1224 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1225 return FALSE;
1226 }
1227 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1228 }
1229 else
1230 {
1231 //Check f/w prefix "VDEC30"
1232 if (_VPU_EX_IsNeedDecompress(pFWCodeCfg->u32DstAddr) != FALSE)
1233 {
1234 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
1235 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1236 {
1237 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1238 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1239 return FALSE;
1240 }
1241 }
1242 else
1243 {
1244 VPU_MSG_INFO("Skip loading fw this time!!!\n");
1245 }
1246 }
1247 }
1248 else
1249 {
1250 if(_VPU_EX_REE_SendMBXMsg(E_VDEC_EX_REE_TO_TEE_MBX_MSG_FW_LoadCode) != E_VDEC_EX_TEE_TO_REE_MBX_ACK_MSG_ACTION_SUCCESS)
1251 {
1252 VPU_MSG_ERR("[Error] VDEC load code in Secure world fail!\n");
1253 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
1254 return FALSE;
1255 }
1256 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
1257 }
1258 }
1259 }
1260 else
1261 #endif
1262 #endif
1263 {
1264 VPU_MSG_INFO("Load VDEC f/w code in Normal World\n");
1265
1266 if (!HAL_VPU_EX_LoadCode(pFWCodeCfg))
1267 {
1268 VPU_MSG_ERR("HAL_VPU_EX_LoadCode fail!\n");
1269 return FALSE;
1270 }
1271 }
1272
1273 if (pVlcCfg)
1274 {
1275 if (!_VPU_EX_LoadVLCTable(pVlcCfg, pFWCodeCfg->u8SrcType))
1276 {
1277 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1278 return FALSE;
1279 }
1280 }
1281
1282 if (!HAL_VPU_EX_CPUSetting(u32fwPA))
1283 {
1284 VPU_MSG_ERR("HAL_VPU_EX_CPUSetting fail!\n");
1285 return FALSE;
1286 }
1287
1288 //Init HW
1289 if (FALSE == _VPU_EX_InitHW(pTaskInfo))
1290 {
1291 VPU_MSG_ERR("(%d): InitHW failed\n", __LINE__);
1292 //_MVD_INIT_FAIL_RET();
1293 return FALSE;
1294 }
1295 else
1296 {
1297 VPU_MSG_DBG("(%d): InitHW success\n", __LINE__);
1298 }
1299
1300 //set vpu clock to FW
1301 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1302 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1303
1304 ctl_ptr->statue = CTL_STU_NONE;
1305 //notify controller the interface version of VPU driver.
1306 ctl_ptr->ctl_interface = VPU_CTL_INTERFACE_VER;
1307 ctl_ptr->vpu_clk = _VPU_EX_InClock(eClkSpeed);
1308 MsOS_FlushMemory();
1309 VPU_MSG_DBG("clock speed=0x%x\n", ctl_ptr->vpu_clk);
1310
1311 //Release VPU: For dual decoder, we only release VPU if it is not released yet.
1312 if (TRUE == HAL_VPU_EX_IsRsted())
1313 {
1314 VPU_MSG_DBG("VPU_IsRsted\n");
1315 return TRUE;
1316 }
1317 else
1318 {
1319 HAL_VPU_EX_SwRstRelse();
1320 }
1321
1322 return TRUE;
1323 }
1324
_VPU_EX_DeinitHW(VPU_EX_TaskInfo * pTaskInfo)1325 static MS_BOOL _VPU_EX_DeinitHW(VPU_EX_TaskInfo *pTaskInfo)
1326 {
1327 MS_BOOL bRet = FALSE;
1328 #if defined(VDEC3)
1329 MS_BOOL isEVD = (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType);
1330 #else
1331 MS_BOOL isEVD = FALSE ;
1332 #endif
1333 MS_BOOL isHVD = (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1334 || (E_VPU_EX_DECODER_VP8 == pTaskInfo->eDecType)
1335 || (E_VPU_EX_DECODER_MVC == pTaskInfo->eDecType);
1336
1337 if (FALSE == HAL_VPU_EX_MVDInUsed())
1338 {
1339 bRet = HAL_MVD_DeinitHW(pTaskInfo->eSrcType, pTaskInfo->eDecType);
1340 }
1341
1342 if (TRUE == isHVD)
1343 {
1344 bRet = HAL_HVD_EX_DeinitHW(pTaskInfo->u32Id);
1345 }
1346
1347 #if defined(VDEC3)
1348 if (TRUE == isEVD)
1349 {
1350 bRet = HAL_EVD_EX_DeinitHW(pTaskInfo->u32Id);
1351 }
1352 #endif
1353
1354 #if SUPPORT_G2VP9 && defined(VDEC3)
1355 if (FALSE == HAL_VPU_EX_G2VP9InUsed())
1356 {
1357 bRet = HAL_VP9_EX_DeinitHW();
1358 }
1359 #endif
1360 return bRet;
1361 }
1362
_VPU_EX_DeinitAll(VPU_EX_NDecInitPara * pInitPara)1363 static MS_BOOL _VPU_EX_DeinitAll(VPU_EX_NDecInitPara *pInitPara)
1364 {
1365 HAL_VPU_EX_SwRst(TRUE);
1366 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
1367 HAL_VPU_EX_DeInit();
1368
1369 return TRUE;
1370 }
1371
_VPU_EX_GetActiveCodecCnt(void)1372 static MS_U8 _VPU_EX_GetActiveCodecCnt(void)
1373 {
1374 MS_U32 i;
1375 MS_U8 u8ActiveCnt = 0;
1376 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
1377 {
1378 if (E_VPU_EX_DECODER_NONE != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1379 E_VPU_EX_DECODER_GET != pVPUHalContext->_stVPUStream[i].eDecodertype &&
1380 E_VPU_EX_DECODER_GET_MVC != pVPUHalContext->_stVPUStream[i].eDecodertype)
1381 {
1382 u8ActiveCnt++;
1383 }
1384 }
1385 if (pVPUHalContext->u8TaskCnt != u8ActiveCnt)
1386 {
1387 VPU_MSG_ERR("Err u8TaskCnt(%d) != u8ActiveCnt(%d)\n", pVPUHalContext->u8TaskCnt, u8ActiveCnt);
1388 }
1389 VPU_MSG_DBG(" = %d\n", u8ActiveCnt);
1390 return u8ActiveCnt;
1391 }
_VPU_EX_ClockInv(MS_BOOL bEnable)1392 static void _VPU_EX_ClockInv(MS_BOOL bEnable)
1393 {
1394 if (TRUE)
1395 {
1396 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_INV);
1397 }
1398 else
1399 {
1400 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_INV, TOP_CKG_VPU_INV);
1401 }
1402 }
1403
_VPU_EX_ClockSpeed(MS_U32 u32type)1404 static void _VPU_EX_ClockSpeed(MS_U32 u32type)
1405 {
1406 switch (u32type)
1407 {
1408 case VPU_CLOCK_240MHZ:
1409 case VPU_CLOCK_216MHZ:
1410 case VPU_CLOCK_192MHZ:
1411 case VPU_CLOCK_12MHZ:
1412 case VPU_CLOCK_320MHZ:
1413 case VPU_CLOCK_288MHZ:
1414 case VPU_CLOCK_384MHZ:
1415 case VPU_CLOCK_432MHZ:
1416 _VPU_WriteWordMask(REG_TOP_VPU, u32type, TOP_CKG_VPU_CLK_MASK);
1417 break;
1418 default:
1419 _VPU_WriteWordMask(REG_TOP_VPU, VPU_CLOCK_384MHZ, TOP_CKG_VPU_CLK_MASK);
1420 break;
1421 }
1422 }
1423 #ifdef HAL_FEATURE_MAU
_VPU_EX_MAU_IDLE(void)1424 static MS_BOOL _VPU_EX_MAU_IDLE(void)
1425 {
1426 if (((_VPU_Read2Byte(MAU1_ARB0_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE)
1427 && ((_VPU_Read2Byte(MAU1_ARB1_DBG0) & MAU1_FSM_CS_MASK) == MAU1_FSM_CS_IDLE))
1428 {
1429 return TRUE;
1430 }
1431 return FALSE;
1432 }
1433 #endif
1434
1435
1436 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
_VPU_EX_DecompressBin(MS_VIRT u32SrcAddr,MS_U32 u32SrcSize,MS_VIRT u32DestAddr,MS_VIRT u32SlidingAddr)1437 static MS_BOOL _VPU_EX_DecompressBin(MS_VIRT u32SrcAddr, MS_U32 u32SrcSize, MS_VIRT u32DestAddr, MS_VIRT u32SlidingAddr)
1438 {
1439 if(_VPU_EX_IsNeedDecompress(u32SrcAddr))
1440 {
1441 ms_VDECDecompressInit((MS_U8*)u32SlidingAddr, (MS_U8*)u32DestAddr);
1442 ms_VDECDecompress((MS_U8*)u32SrcAddr, u32SrcSize);
1443 ms_VDECDecompressDeInit();
1444 return TRUE;
1445 }
1446 else
1447 {
1448 return FALSE;
1449 }
1450 }
1451 #endif
1452
HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)1453 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable)
1454 {
1455 MS_BOOL bRet = TRUE;
1456 pVPUHalContext->_bVPUSingleMode = bEnable;
1457 return bRet;
1458 }
1459
HAL_VPU_EX_SetSTCMode(MS_U32 u32Id,MS_U32 u32STCIndex)1460 MS_BOOL HAL_VPU_EX_SetSTCMode(MS_U32 u32Id, MS_U32 u32STCIndex)
1461 {
1462 MS_BOOL bRet = TRUE;
1463 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
1464 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].bSTCSetMode = TRUE;
1465 pVPUHalContext->_stVPUSTCMode[u8OffsetIdx].u32STCIndex = u32STCIndex;
1466
1467 return bRet;
1468 }
1469
HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg * pstCfg)1470 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg)
1471 {
1472 MS_BOOL bRet = TRUE;
1473 MS_U8 i=0;
1474 if (pstCfg != NULL)
1475 {
1476 pVPUHalContext->_stVPUDecMode.u8DecMod = pstCfg->u8DecMod;
1477 pVPUHalContext->_stVPUDecMode.u8CodecCnt = pstCfg->u8CodecCnt;
1478 for (i=0; ((i<pstCfg->u8CodecCnt)&&(i<VPU_MAX_DEC_NUM)); i++)
1479 {
1480 pVPUHalContext->_stVPUDecMode.u8CodecType[i] = pstCfg->u8CodecType[i];
1481 }
1482 pVPUHalContext->_stVPUDecMode.u8ArgSize = pstCfg->u8ArgSize;
1483 pVPUHalContext->_stVPUDecMode.u32Arg = pstCfg->u32Arg;
1484 }
1485 else
1486 {
1487 bRet = FALSE;
1488 }
1489 return bRet;
1490 }
1491
1492 //static MS_BOOL bVpuExReloadFW = TRUE;
1493 //static MS_BOOL bVpuExLoadFWRlt = FALSE;
HAL_VPU_EX_SetFWReload(MS_BOOL bReload)1494 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload)
1495 {
1496 pVPUHalContext->bVpuExReloadFW = bReload;
1497 //printf("%s bVpuExReloadFW = %x\n", __FUNCTION__, bVpuExReloadFW);
1498 return TRUE;
1499 }
1500
1501
1502 //-------------------------------------------------------------------------------------------------
1503 // Global Functions
1504 //-------------------------------------------------------------------------------------------------
1505 #ifdef VDEC3_FB
HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg * pVlcCfg,MS_U8 u8FwSrcType)1506 MS_BOOL HAL_VPU_EX_LoadVLCTable(VPU_EX_VLCTblCfg *pVlcCfg, MS_U8 u8FwSrcType)
1507 {
1508 #if HVD_ENABLE_RV_FEATURE
1509 if (E_HVD_FW_INPUT_SOURCE_FLASH == u8FwSrcType)
1510 {
1511 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
1512 VPU_MSG_DBG("Load VLC outF2D: dest:0x%lx source:%lx size:%lx\n",
1513 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1514
1515 if (pVlcCfg->u32BinSize)
1516 {
1517 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
1518
1519 if (HAL_MIU1_BASE <= MsOS_VA2PA(pVlcCfg->u32DstAddr))
1520 {
1521 cpyflag = E_SPIDMA_DEV_MIU1;
1522 }
1523 else
1524 {
1525 cpyflag = E_SPIDMA_DEV_MIU0;
1526 }
1527
1528 if (!HVD_FLASHcpy(MsOS_VA2PA(pVlcCfg->u32DstAddr), MsOS_VA2PA(pVlcCfg->u32BinAddr), pVlcCfg->u32BinSize, cpyflag))
1529 {
1530 VPU_MSG_ERR("HVD_BDMAcpy VLC table Flash 2 DRAM failed: dest:0x%lx src:0x%lx size:0x%lx flag:%lu\n",
1531 pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize, (MS_U32) cpyflag);
1532
1533 return FALSE;
1534 }
1535 }
1536 else
1537 {
1538 VPU_MSG_ERR("During copy VLC from Flash to Dram, the source size of FW is zero\n");
1539 return FALSE;
1540 }
1541 #else
1542 VPU_MSG_ERR("driver not enable to use BDMA copy VLC from flash 2 sdram.\n");
1543 return FALSE;
1544 #endif
1545 }
1546 else
1547 {
1548 if (E_HVD_FW_INPUT_SOURCE_DRAM == u8FwSrcType)
1549 {
1550 if ((pVlcCfg->u32BinAddr != 0) && (pVlcCfg->u32BinSize != 0))
1551 {
1552 VPU_MSG_INFO("Load VLC outD2D: dest:0x%lx source:%lx size:%lx\n",
1553 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long)pVlcCfg->u32BinAddr, (unsigned long)pVlcCfg->u32BinSize);
1554
1555 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
1556 BDMA_Result bdmaRlt;
1557
1558 MsOS_FlushMemory();
1559 bdmaRlt = HVD_dmacpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1560
1561 if (E_BDMA_OK != bdmaRlt)
1562 {
1563 VPU_MSG_ERR("MDrv_BDMA_MemCopy fail in %s(), ret=%x!\n", __FUNCTION__, bdmaRlt);
1564 }
1565 #else
1566 HVD_memcpy(pVlcCfg->u32DstAddr, pVlcCfg->u32BinAddr, pVlcCfg->u32BinSize);
1567 #endif
1568 }
1569 else
1570 {
1571 VPU_MSG_ERR
1572 ("During copy VLC from out Dram to Dram, the source size or virtual address of VLC is zero\n");
1573 return FALSE;
1574 }
1575 }
1576 else
1577 {
1578 #if VPU_ENABLE_EMBEDDED_FW_BINARY
1579 #ifdef HVD_CACHE_TO_UNCACHE_CONVERT
1580 MS_U8 *pu8HVD_VLC_Binary;
1581
1582 pu8HVD_VLC_Binary = (MS_U8 *) ((MS_U32) u8HVD_VLC_Binary | 0xA0000000);
1583
1584 VPU_MSG_DBG("Load VLC inD2D: dest:0x%lx source:%lx size:%lx\n",
1585 (unsigned long)pVlcCfg->u32DstAddr, (unsigned long) pu8HVD_VLC_Binary),
1586 (MS_U32) sizeof(u8HVD_VLC_Binary));
1587
1588 HVD_memcpy((void *) (pVlcCfg->u32DstAddr),
1589 (void *) ((MS_U32) pu8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1590 #else
1591 VPU_MSG_INFO("Load VLC inD2D: dest:0x%lx source:%lx size:%x\n",
1592 (unsigned long)MsOS_VA2PA(pVlcCfg->u32DstAddr), (unsigned long) u8HVD_VLC_Binary,
1593 (MS_U32) sizeof(u8HVD_VLC_Binary));
1594
1595 HVD_memcpy(pVlcCfg->u32DstAddr, ((MS_VIRT) u8HVD_VLC_Binary), sizeof(u8HVD_VLC_Binary));
1596 #endif
1597 #else
1598 VPU_MSG_ERR("driver not enable to use embedded VLC binary.\n");
1599 return FALSE;
1600 #endif
1601 }
1602 }
1603 #endif
1604
1605 return TRUE;
1606 }
1607 #endif
1608 #ifdef VDEC3
HAL_VPU_EX_TaskCreate(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara,MS_BOOL bFWdecideFB,MS_U32 u32BBUId)1609 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara, MS_BOOL bFWdecideFB, MS_U32 u32BBUId)
1610 #else
1611 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1612 #endif
1613 {
1614 VPU_EX_TaskInfo *pTaskInfo = pInitPara->pTaskInfo;
1615 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
1616 HVD_User_Cmd eCmd = E_HVD_CMD_INVALID_CMD;
1617 VPU_EX_DecoderType eDecType = E_VPU_EX_DECODER_NONE;
1618 MS_U32 u32Arg = 0xFFFFFFFF;
1619 MS_U32 u32Timeout = 0;
1620 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
1621 MS_U32 u32CmdArg = 0;
1622 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
1623 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
1624
1625 _HAL_VPU_Entry();
1626 //Check FW buffer size
1627 if (1 == u8Offset)
1628 {
1629 MS_VIRT u32MinFWBuffSize = (u8Offset + 1) * VPU_FW_MEM_OFFSET;
1630 MS_VIRT u32CurFWBuffSize = pInitPara->pFWCodeCfg->u32DstSize;
1631
1632 if (u32CurFWBuffSize < u32MinFWBuffSize)
1633 {
1634 VPU_MSG_ERR("FW BuffSize(0x%lx < 0x%lx) is too small!\n", (unsigned long)u32CurFWBuffSize, (unsigned long)u32MinFWBuffSize);
1635 _HAL_VPU_Release();
1636 return FALSE;
1637 }
1638 }
1639
1640 if(( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id))
1641 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype)
1642 &&(E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
1643 {
1644 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
1645 }
1646 #ifdef VDEC3
1647 pVPUHalContext->u32FWCodeAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1648 #endif
1649
1650 if (0 == pVPUHalContext->u8TaskCnt)
1651 {
1652 //No task is created, need to load f/w, etc.
1653 VPU_MSG_DBG("u8TaskCnt=%d\n", pVPUHalContext->u8TaskCnt);
1654
1655 if (!_VPU_EX_InitAll(pInitPara))
1656 {
1657 VPU_MSG_DBG("(%d) fail to InitAll\n", __LINE__);
1658 _HAL_VPU_Release();
1659 return FALSE;
1660 }
1661
1662 //Check if controller finish initialization: clear mailbox, etc.
1663 //Need to check it before sending any controller commands!
1664 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1665 while (CTL_STU_NONE == ctl_ptr->statue)
1666 {
1667 if (HVD_GetSysTime_ms() > u32Timeout)
1668 {
1669 VPU_MSG_ERR("Ctl init timeout, st=%x\n", ctl_ptr->statue);
1670 VPU_MSG_ERR("version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1671 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1672 MS_U32 t=0;
1673 for (t=0; t<30; t++)
1674 {
1675 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1676 }
1677 _HAL_VPU_Release();
1678 return FALSE;
1679 }
1680
1681 MsOS_ReadMemory();
1682 }
1683
1684 VPU_MSG_INFO("ctl_init_done: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1685 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1686
1687 }
1688 else
1689 {
1690 if (pVPUHalContext->_bVPUSingleMode)
1691 {
1692 //Show error message
1693 printf("This task will use dram instead of sram!!!\n");
1694 VPU_MSG_INFO("VDEC warn: this task will use dram instead of sram!!!\n");
1695 }
1696
1697 if (!_VPU_EX_InitHW(pInitPara->pTaskInfo))
1698 {
1699 VPU_MSG_DBG("(%d) fail to InitHW\n", __LINE__);
1700 _HAL_VPU_Release();
1701 return FALSE;
1702 }
1703 if (pInitPara->pVLCCfg)
1704 {
1705 if (!_VPU_EX_LoadVLCTable(pInitPara->pVLCCfg, pInitPara->pFWCodeCfg->u8SrcType))
1706 {
1707 VPU_MSG_ERR("HAL_VPU_LoadVLCTable fail!\n");
1708 _HAL_VPU_Release();
1709 return FALSE;
1710 }
1711 }
1712 }
1713
1714
1715 #ifdef VDEC3
1716 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1717 {
1718 VDEC_VBBU *pTemp4 = (VDEC_VBBU *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VBBU_TABLE_START + u8Offset*VPU_FW_MEM_OFFSET);
1719
1720 memset(pTemp4,0,sizeof(VDEC_VBBU));
1721
1722 *((unsigned int*)(pTemp4->u8Reserved)) = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr)-HAL_MIU1_BASE;
1723
1724 DISPQ_IN_DRAM *pTemp = (DISPQ_IN_DRAM *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + DISP_QUEUE_START + u8Offset*VPU_FW_MEM_OFFSET);
1725
1726 memset(pTemp,0,sizeof(DISPQ_IN_DRAM));
1727
1728 CMD_QUEUE *pTemp2 = (CMD_QUEUE *)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VCOMMANDQ_INFO_START + u8Offset*VPU_FW_MEM_OFFSET);
1729
1730 memset(pTemp2,0,sizeof(CMD_QUEUE));
1731
1732 pTemp2->u32HVD_DISPCMDQ_DRAM_ST_ADDR = VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1733
1734 pTemp2->u32HVD_CMDQ_DRAM_ST_ADDR = VNORMAL_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET;
1735
1736 unsigned char* pTemp3 = (unsigned char*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + VDISP_COMMANDQ_START + u8Offset*VPU_FW_MEM_OFFSET);
1737
1738 memset(pTemp3,0,0x2000);
1739
1740 unsigned int* pVersion = (unsigned int*)MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + OFFSET_BASE + u8Offset*VPU_FW_MEM_OFFSET);
1741
1742 memset((void*)pVersion,0,0x8);
1743
1744 *pVersion = 1; //0:diu, 1:wb
1745 }
1746
1747 #endif
1748
1749 #if 1 // For TEE
1750 #ifdef VDEC3
1751 #if SUPPORT_G2VP9
1752 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType ||
1753 E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1754 #else
1755 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1756 #endif
1757 #else
1758 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1759 #endif
1760 {
1761 MS_VIRT u32FWPhyAddr = MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr);
1762
1763 if (pVPUHalContext->u32FWShareInfoAddr[u8Offset] == 0xFFFFFFFFUL)
1764 {
1765 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
1766 }
1767 else
1768 {
1769 ctl_ptr->u32TaskShareInfoAddr[u8Offset] = pVPUHalContext->u32FWShareInfoAddr[u8Offset] - u32FWPhyAddr;
1770 }
1771
1772 MsOS_FlushMemory();
1773 VPU_MSG_DBG("task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1774
1775 ///printf("DRV side, share info offset = 0x%lx\n", pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
1776 ///printf("FW side, task share info offset = 0x%x\n", ctl_ptr->u32TaskShareInfoAddr[u8Offset]);
1777 }
1778 #endif
1779
1780 if ((pVPUHalContext->bEnableDymanicFBMode == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1781 {
1782 ctl_ptr->FB_ADDRESS = pVPUHalContext->u32DynamicFBAddress;
1783 ctl_ptr->FB_Total_SIZE = pVPUHalContext->u32DynamicFBSize;
1784
1785 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_COMMON, 0);
1786
1787 MsOS_FlushMemory();
1788 }
1789
1790 if (pVPUHalContext->_stVPUSTCMode[u8Offset].bSTCSetMode)
1791 {
1792 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_STC_MODE, pVPUHalContext->_stVPUSTCMode[u8Offset].u32STCIndex);
1793 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1794 {
1795 VPU_MSG_ERR("E_HVD_CMD_STC_MODE NG eCtrlRet=%x\n", eCtrlRet);
1796 }
1797 }
1798
1799 if ((TRUE==pVPUHalContext->_bVPUSingleMode) || (E_VPU_DEC_MODE_SINGLE==pVPUHalContext->_stVPUDecMode.u8DecMod))
1800 {
1801 //Issue E_DUAL_CMD_SINGLE_TASK to FW controller
1802 //arg=1 to get better performance for single task
1803 u32CmdArg = (pVPUHalContext->_bVPUSingleMode) ? 1 : 0;
1804 VPU_MSG_DBG("Issue E_DUAL_CMD_SINGLE_TASK to FW controller arg=%x\n", u32CmdArg);
1805 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_SINGLE_TASK, u32CmdArg);
1806 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1807 {
1808 VPU_MSG_ERR("E_DUAL_CMD_SINGLE_TASK NG eCtrlRet=%x\n", eCtrlRet);
1809 }
1810 }
1811 else if (E_VPU_DEC_MODE_DUAL_3D==pVPUHalContext->_stVPUDecMode.u8DecMod)
1812 {
1813 if(pVPUHalContext->_stVPUDecMode.u8CodecType[0] != pVPUHalContext->_stVPUDecMode.u8CodecType[1])
1814 {
1815 switch (pVPUHalContext->_stVPUDecMode.u32Arg)
1816 {
1817 case E_VPU_CMD_MODE_KR3D_INTERLACE:
1818 u32CmdArg = CTL_MODE_3DTV;
1819 break;
1820 case E_VPU_CMD_MODE_KR3D_FORCE_P:
1821 u32CmdArg = CTL_MODE_3DTV_PROG;
1822 break;
1823 case E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH:
1824 u32CmdArg = CTL_MODE_3DTV_TWO_PITCH;
1825 break;
1826 case E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH:
1827 u32CmdArg = CTL_MODE_3DTV_PROG_TWO_PITCH;
1828 break;
1829 default:
1830 u32CmdArg = CTL_MODE_3DTV;
1831 VPU_MSG_INFO("%x not defined, use CTL_MODE_3DTV for KR3D\n", pVPUHalContext->_stVPUDecMode.u32Arg);
1832 break;
1833 }
1834 }
1835 else
1836 {
1837 u32CmdArg = CTL_MODE_3DWMV;
1838 }
1839 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1840 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1841 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1842 {
1843 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1844 }
1845 }
1846 else if(E_VPU_DEC_MODE_DUAL_INDIE == pVPUHalContext->_stVPUDecMode.u8DecMod)
1847 {
1848 if(E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC == pVPUHalContext->_stVPUDecMode.u32Arg)
1849 {
1850 u32CmdArg = CTL_MODE_ONE_STC;
1851 }
1852 else
1853 {
1854 u32CmdArg = (pVPUHalContext->_stVPUDecMode.u32Arg==E_VPU_CMD_MODE_PIP_SYNC_SWITCH) ? CTL_MODE_SWITCH_STC : CTL_MODE_NORMAL;
1855 }
1856 VPU_MSG_DBG("Issue E_DUAL_CMD_MODE to FW controller arg=%x\n", u32CmdArg);
1857 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_CMD_MODE, u32CmdArg);
1858 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
1859 {
1860 VPU_MSG_ERR("E_DUAL_CMD_MODE NG eCtrlRet=%x\n", eCtrlRet);
1861 }
1862 }
1863
1864 eCmd = _VPU_EX_MapCtrlCmd(pTaskInfo);
1865 #if defined(SUPPORT_NEW_MEM_LAYOUT)
1866 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1867 #ifdef VDEC3
1868 {
1869 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1870 }
1871 #else
1872 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + OFFSET_BASE;
1873 #endif
1874
1875 #ifdef VDEC3
1876 #if SUPPORT_G2VP9
1877 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1878 #else
1879 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1880 #endif
1881 {
1882 u32Arg = (u32BBUId << VDEC_BBU_ID_SHIFT) + (u8Offset * VPU_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
1883 }
1884 #else
1885 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1886 u32Arg = u8Offset * VPU_FW_MEM_OFFSET + HVD_SHARE_MEM_ST_OFFSET;
1887 #endif
1888 else
1889 {
1890 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1891 _HAL_VPU_Release();
1892 return FALSE;
1893 }
1894 #else
1895 u32Arg = u8Offset * VPU_FW_MEM_OFFSET;
1896 #endif
1897
1898 VPRINTF("[NDec][%s][%d] create task : id 0x%x, cmd 0x%x, arg 0x%x, bbuID %d, offset %d \n", __FUNCTION__, __LINE__, u32Id, eCmd, u32Arg, u32BBUId, u8Offset);
1899 HAL_HVD_EX_SetCmd(u32Id, eCmd, u32Arg);
1900
1901 MsOS_ReadMemory();
1902 VPU_MSG_INFO("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1903 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1904
1905 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
1906 while (CTL_TASK_CMDRDY != ctl_ptr->task_statue[u8Offset])
1907 {
1908 if (HVD_GetSysTime_ms() > u32Timeout)
1909 {
1910 VPU_MSG_ERR("Task %d creation timeout\n", u8Offset);
1911 MS_U32 t=0;
1912 for (t=0; t<30; t++)
1913 {
1914 VPU_MSG_DBG("_pc=0x%x\n", HAL_VPU_EX_GetProgCnt());
1915 }
1916 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1917 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
1918 VPU_MSG_ERR("set bVpuExLoadFWRlt as FALSE\n\n");
1919 _HAL_VPU_Release();
1920 return FALSE;
1921 //#endif
1922 }
1923
1924 MsOS_ReadMemory();
1925 }
1926
1927 VPU_MSG_INFO("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
1928 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
1929
1930 #ifdef VDEC3
1931 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType || E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1932 #else
1933 if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1934 #endif
1935 {
1936 HAL_HVD_EX_SetNalTblAddr(u32Id);
1937 }
1938
1939 if (E_VPU_EX_DECODER_MVD == pTaskInfo->eDecType)
1940 {
1941 eDecType = E_VPU_EX_DECODER_MVD;
1942 }
1943 else if (E_VPU_EX_DECODER_HVD == pTaskInfo->eDecType)
1944 {
1945 eDecType = E_VPU_EX_DECODER_HVD;
1946 }
1947 #ifdef VDEC3
1948 else if (E_VPU_EX_DECODER_EVD == pTaskInfo->eDecType)
1949 {
1950 eDecType = E_VPU_EX_DECODER_EVD;
1951 }
1952 #if SUPPORT_G2VP9
1953 else if (E_VPU_EX_DECODER_G2VP9 == pTaskInfo->eDecType)
1954 {
1955 eDecType = E_VPU_EX_DECODER_G2VP9;
1956 }
1957 #endif
1958 #endif
1959 else
1960 {
1961 VPU_MSG_ERR("Can't find eDecType! %d\n", pTaskInfo->eDecType);
1962 _HAL_VPU_Release();
1963 return FALSE;
1964 }
1965
1966 #ifdef VDEC3
1967 if ((bFWdecideFB == TRUE) && (pVPUHalContext->u8TaskCnt == 0))
1968 {
1969 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBADDR, pInitPara->pFBCfg->u32FrameBufAddr);
1970 HAL_HVD_EX_SetCmd(u32Id, E_DUAL_R2_CMD_FBSIZE, pInitPara->pFBCfg->u32FrameBufSize);
1971 }
1972 #endif
1973
1974 if (pTaskInfo->eDecType != eDecType)
1975 {
1976 VPU_MSG_ERR("warning pTaskInfo->eDecType=%x not %x\n",
1977 pTaskInfo->eDecType, eDecType);
1978 }
1979 goto _SAVE_DEC_TYPE;
1980
1981 _SAVE_DEC_TYPE:
1982 if (pVPUHalContext->_stVPUStream[u8Offset].eStreamId == (u32Id & 0xFF))
1983 {
1984 pVPUHalContext->_stVPUStream[u8Offset].eDecodertype = eDecType;
1985 }
1986 else
1987 {
1988 VPU_MSG_ERR("Cannot save eDecType!!\n");
1989 }
1990
1991 (pVPUHalContext->u8TaskCnt)++;
1992 _HAL_VPU_Release();
1993 return TRUE;
1994 }
1995
HAL_VPU_EX_TaskDelete(MS_U32 u32Id,VPU_EX_NDecInitPara * pInitPara)1996 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara)
1997 {
1998 HVD_Return eRet;
1999 #ifdef VDEC3
2000 HVD_User_Cmd eCmd = E_NST_CMD_DEL_TASK;
2001 #else
2002 HVD_User_Cmd eCmd = E_DUAL_CMD_DEL_TASK;
2003 #endif
2004 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
2005 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
2006
2007 _HAL_VPU_Entry();
2008 VPU_MSG_DBG("DecType=%d\n", pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype);
2009
2010 eRet = HAL_HVD_EX_SetCmd(u32Id, eCmd, u8OffsetIdx);
2011 if(eRet != E_HVD_RETURN_SUCCESS)
2012 {
2013 VPU_MSG_ERR("VPU fail to DEL Task %d\n", eRet);
2014 }
2015
2016 {
2017 struct _ctl_info *ctl_ptr = (struct _ctl_info *)
2018 MsOS_PA2KSEG1(MsOS_VA2PA(pInitPara->pFWCodeCfg->u32DstAddr) + CTL_INFO_ADDR);
2019 u32Timeout = HVD_GetSysTime_ms() + VPU_CMD_TIMEOUT;
2020
2021 MsOS_ReadMemory();
2022
2023 VPU_MSG_DBG("before: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2024 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2025
2026 while (CTL_TASK_NONE != ctl_ptr->task_statue[u8OffsetIdx])
2027 {
2028 if (HVD_GetSysTime_ms() > u32Timeout)
2029 {
2030 VPU_MSG_ERR("Task %u deletion timeout\n", u8OffsetIdx);
2031 pVPUHalContext->bVpuExLoadFWRlt = FALSE; ///error handling
2032 VPU_MSG_ERR("Set bVpuExLoadFWRlt as FALSE\n");
2033
2034 if(pVPUHalContext->u8TaskCnt == 1)
2035 {
2036 VPU_MSG_ERR("Due to one task remain, driver can force delete task\n");
2037 break;
2038 }
2039 else if(pVPUHalContext->u8TaskCnt == 2)
2040 {
2041 VPU_MSG_ERR("Due to two tasks remain, driver can't force delete task\n");
2042 break;
2043 }
2044 else
2045 {
2046 VPU_MSG_ERR("Task number is not correct\n");
2047 _HAL_VPU_Release();
2048 return FALSE;
2049 }
2050 }
2051
2052 MsOS_ReadMemory();
2053 }
2054
2055 VPU_MSG_DBG("after: version=0x%x, statue=0x%x, last_ctl_cmd=0x%x, last_ctl_arg=0x%x, t0=%d, t1=%d\n",
2056 ctl_ptr->verion, ctl_ptr->statue, ctl_ptr->last_ctl_cmd, ctl_ptr->last_ctl_arg, ctl_ptr->task_statue[0], ctl_ptr->task_statue[1]);
2057 }
2058 #if SUPPORT_EVD
2059 if (pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype == E_VPU_EX_DECODER_EVD)
2060 {
2061 HAL_EVD_EX_ClearTSPInput(u32Id);
2062 }
2063 #endif
2064
2065 pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype = E_VPU_EX_DECODER_NONE;
2066 if( (u8OffsetIdx == 0) && (pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId == E_HAL_VPU_MVC_MAIN_VIEW))
2067 {
2068 pVPUHalContext->_stVPUStream[u8OffsetIdx].eStreamId = E_HAL_VPU_N_STREAM0;
2069 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2070 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2071 }
2072
2073 if (pVPUHalContext->u8TaskCnt)
2074 {
2075 (pVPUHalContext->u8TaskCnt)--;
2076 }
2077 else
2078 {
2079 VPU_MSG_DBG("Warning: u8TaskCnt=0\n");
2080 }
2081
2082 if (0 == pVPUHalContext->u8TaskCnt)
2083 {
2084 int i;
2085 VPU_MSG_DBG("u8TaskCnt=%d time to terminate\n", pVPUHalContext->u8TaskCnt);
2086 _VPU_EX_DeinitAll(pInitPara);
2087 HAL_VPU_EX_SetSingleDecodeMode(FALSE);
2088 pVPUHalContext->u32VPUSHMAddr = 0;
2089
2090 for (i = 0; i < MAX_SUPPORT_DECODER_NUM; i++)
2091 pVPUHalContext->u32FWShareInfoAddr[i] = 0xFFFFFFFFUL;
2092 }
2093 else
2094 {
2095 pVPUHalContext->u32FWShareInfoAddr[u8OffsetIdx] = 0xFFFFFFFFUL;
2096 _VPU_EX_DeinitHW(pInitPara->pTaskInfo);
2097 }
2098
2099 _HAL_VPU_Release();
2100 return TRUE;
2101 }
2102
HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg * pFWCodeCfg)2103 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg)
2104 {
2105 MS_VIRT u32DestAddr = pFWCodeCfg->u32DstAddr;
2106 MS_VIRT u32BinAddr = pFWCodeCfg->u32BinAddr;
2107 MS_U32 u32Size = pFWCodeCfg->u32BinSize;
2108 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2109 MS_U32 u32DestSize = pFWCodeCfg->u32DstSize;
2110 #endif
2111
2112 if (FALSE == HAL_VPU_EX_GetFWReload())
2113 {
2114 //printf("%s bFWReload FALSE!!!\n", __FUNCTION__);
2115 if (FALSE == pVPUHalContext->bVpuExLoadFWRlt)
2116 {
2117 VPU_MSG_INFO("Never load fw successfully, load it anyway!\n");
2118 }
2119 else
2120 {
2121 //Check f/w prefix "VDEC30"
2122 if (_VPU_EX_IsNeedDecompress(u32DestAddr)!=FALSE)
2123 {
2124 VPU_MSG_ERR("Wrong prefix: reload fw!\n");
2125 }
2126 else
2127 {
2128 VPU_MSG_INFO("Skip loading fw this time!!!\n");
2129 return TRUE;
2130 }
2131 }
2132 }
2133
2134 if (E_HVD_FW_INPUT_SOURCE_FLASH == pFWCodeCfg->u8SrcType)
2135 {
2136 #if VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM
2137 if (u32Size != 0)
2138 {
2139 SPIDMA_Dev cpyflag = E_SPIDMA_DEV_MIU1;
2140
2141
2142 MS_U32 u32Start;
2143 MS_U32 u32StartOffset;
2144 MS_U8 u8MiuSel;
2145
2146 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32DestAddr);
2147
2148
2149 if(u8MiuSel == E_CHIP_MIU_0)
2150 cpyflag = E_SPIDMA_DEV_MIU0;
2151 else if(u8MiuSel == E_CHIP_MIU_1)
2152 cpyflag = E_SPIDMA_DEV_MIU1;
2153 else if(u8MiuSel == E_CHIP_MIU_2)
2154 ; ///TODO: cpyflag = E_SPIDMA_DEV_MIU2;
2155
2156 if (!HVD_FLASHcpy(MsOS_VA2PA(u32DestAddr), MsOS_VA2PA(u32BinAddr), u32Size, cpyflag))
2157 {
2158 goto _load_code_fail;
2159 }
2160 }
2161 else
2162 {
2163 goto _load_code_fail;
2164 }
2165 #else
2166 goto _load_code_fail;
2167 #endif
2168 }
2169 else if (E_HVD_FW_INPUT_SOURCE_DRAM == pFWCodeCfg->u8SrcType)
2170 {
2171 if (u32BinAddr != 0 && u32Size != 0)
2172 {
2173 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2174 if(_VPU_EX_DecompressBin(u32BinAddr, u32Size, u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2175 {
2176 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2177 {
2178 VPU_MSG_INFO("Decompress ok!!!\n");
2179 }
2180 else
2181 {
2182 VPU_MSG_INFO("Decompress fail!!!\n");
2183 }
2184 }
2185 else
2186 #endif
2187 {
2188 HVD_memcpy(u32DestAddr, u32BinAddr, u32Size);
2189 }
2190 }
2191 else
2192 {
2193 goto _load_code_fail;
2194 }
2195 }
2196 else
2197 {
2198 #if VPU_ENABLE_EMBEDDED_FW_BINARY
2199 VPU_MSG_INFO("Load FW inD2D: dest=0x%lx, source=0x%lx, size=%d\n",
2200 (unsigned long)u32DestAddr, ((unsigned long) u8HVD_FW_Binary),
2201 (MS_U32) sizeof(u8HVD_FW_Binary));
2202
2203 #if (ENABLE_DECOMPRESS_FUNCTION==TRUE)
2204 if(_VPU_EX_DecompressBin((MS_VIRT)u8HVD_FW_Binary, (MS_U32)sizeof(u8HVD_FW_Binary), u32DestAddr, u32DestAddr+u32DestSize-WINDOW_SIZE)==TRUE)
2205 {
2206 if(_VPU_EX_IsNeedDecompress(u32DestAddr)==FALSE)
2207 {
2208 VPU_MSG_INFO("Decompress ok!!!\n");
2209 }
2210 else
2211 {
2212 VPU_MSG_INFO("Decompress fail!!!\n");
2213 }
2214 }
2215 else
2216 #endif
2217 {
2218 HVD_memcpy(u32DestAddr, (MS_VIRT)u8HVD_FW_Binary, sizeof(u8HVD_FW_Binary));
2219 }
2220 #else
2221 goto _load_code_fail;
2222 #endif
2223 }
2224
2225 MAsm_CPU_Sync();
2226 MsOS_FlushMemory();
2227
2228 if (FALSE == (*((MS_U8*)(u32DestAddr+6))=='R' && *((MS_U8*)(u32DestAddr+7))=='2'))
2229 {
2230 VPU_MSG_ERR("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(u32DestAddr+6), *(MS_U8*)(u32DestAddr+7));
2231 goto _load_code_fail;
2232 }
2233
2234 pVPUHalContext->bVpuExLoadFWRlt = TRUE;
2235 return TRUE;
2236
2237 _load_code_fail:
2238 pVPUHalContext->bVpuExLoadFWRlt = FALSE;
2239 return FALSE;
2240 }
2241
HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)2242 void HAL_VPU_EX_InitRegBase(MS_VIRT u32RegBase)
2243 {
2244 u32VPURegOSBase = u32RegBase;
2245 }
2246
HAL_VPU_EX_Init_Share_Mem(void)2247 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void)
2248 {
2249 #if ((defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS)) && (!defined(SUPPORT_X_MODEL_FEATURE)))
2250
2251 MS_U32 u32ShmId;
2252 MS_VIRT u32Addr;
2253 MS_U32 u32BufSize;
2254
2255
2256 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HAL VPU",
2257 sizeof(VPU_Hal_CTX),
2258 &u32ShmId,
2259 &u32Addr,
2260 &u32BufSize,
2261 MSOS_SHM_QUERY))
2262 {
2263 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HAL VPU",
2264 sizeof(VPU_Hal_CTX),
2265 &u32ShmId,
2266 &u32Addr,
2267 &u32BufSize,
2268 MSOS_SHM_CREATE))
2269 {
2270 VPU_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
2271 if(pVPUHalContext == NULL)
2272 {
2273 pVPUHalContext = &gVPUHalContext;
2274 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2275 _VPU_EX_Context_Init();
2276 printf("[%s]Global structure init Success!!!\n",__FUNCTION__);
2277 }
2278 else
2279 {
2280 printf("[%s]Global structure exists!!!\n",__FUNCTION__);
2281 }
2282 //return FALSE;
2283 }
2284 else
2285 {
2286 memset((MS_U8*)u32Addr,0,sizeof(VPU_Hal_CTX));
2287 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for one process
2288 _VPU_EX_Context_Init();
2289 }
2290 }
2291 else
2292 {
2293 pVPUHalContext = (VPU_Hal_CTX*)u32Addr; // for another process
2294 }
2295 #else
2296 if(pVPUHalContext == NULL)
2297 {
2298 pVPUHalContext = &gVPUHalContext;
2299 memset(pVPUHalContext,0,sizeof(VPU_Hal_CTX));
2300 _VPU_EX_Context_Init();
2301 }
2302 #endif
2303
2304 return TRUE;
2305
2306 }
2307
HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)2308 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType)
2309 {
2310 MS_U32 i = 0;
2311
2312 _HAL_VPU_MutexCreate();
2313
2314 _HAL_VPU_Entry();
2315
2316 if (E_HAL_VPU_MVC_STREAM == eStreamType)
2317 {
2318 if((E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[0].eDecodertype) && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[1].eDecodertype))
2319 {
2320 pVPUHalContext->_stVPUStream[0].eStreamId = E_HAL_VPU_MVC_MAIN_VIEW;
2321 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2322 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_GET_MVC;
2323 _HAL_VPU_Release();
2324 return pVPUHalContext->_stVPUStream[0].eStreamId; /// Need to check
2325 }
2326 }
2327 else if (E_HAL_VPU_MAIN_STREAM == eStreamType)
2328 {
2329 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2330 {
2331 if ((E_HAL_VPU_MAIN_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2332 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2333 {
2334 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2335 _HAL_VPU_Release();
2336 return pVPUHalContext->_stVPUStream[i].eStreamId;
2337 }
2338 }
2339 }
2340 else if (E_HAL_VPU_SUB_STREAM == eStreamType)
2341 {
2342 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2343 {
2344 if ((E_HAL_VPU_SUB_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2345 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2346 {
2347 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2348 _HAL_VPU_Release();
2349 return pVPUHalContext->_stVPUStream[i].eStreamId;
2350 }
2351 }
2352 }
2353 #ifdef VDEC3
2354 else if (eStreamType >= E_HAL_VPU_N_STREAM && eStreamType < (E_HAL_VPU_N_STREAM + VPU_MAX_DEC_NUM))
2355 {
2356 #if 1 // bound FW task to main/sub stream
2357 i = eStreamType - E_HAL_VPU_N_STREAM;
2358 if (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_NONE)
2359 {
2360 pVPUHalContext->_stVPUStream[i].eDecodertype = E_VPU_EX_DECODER_GET;
2361 _HAL_VPU_Release();
2362 return pVPUHalContext->_stVPUStream[i].eStreamId;
2363 }
2364 #else // dynamic select FW task id
2365 for (i = 0;i < MAX_SUPPORT_DECODER_NUM; i++)
2366 {
2367 if ((E_HAL_VPU_N_STREAM_BASE & pVPUHalContext->_stVPUStream[i].eStreamId)
2368 && (E_VPU_EX_DECODER_NONE == pVPUHalContext->_stVPUStream[i].eDecodertype))
2369 {
2370 return pVPUHalContext->_stVPUStream[i].eStreamId;
2371 }
2372 }
2373 #endif
2374 }
2375 #endif
2376
2377 _HAL_VPU_Release();
2378
2379 return E_HAL_VPU_STREAM_NONE;
2380 }
2381
HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)2382 MS_BOOL HAL_VPU_EX_ReleaseFreeStream(MS_U8 u8Idx)
2383 {
2384 _HAL_VPU_Entry();
2385
2386 if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET_MVC)
2387 {
2388 pVPUHalContext->_stVPUStream[0].eDecodertype = E_VPU_EX_DECODER_NONE;
2389 pVPUHalContext->_stVPUStream[1].eDecodertype = E_VPU_EX_DECODER_NONE;
2390 }
2391 else if(pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_GET)
2392 {
2393 pVPUHalContext->_stVPUStream[u8Idx].eDecodertype = E_VPU_EX_DECODER_NONE;
2394 }
2395
2396 _HAL_VPU_Release();
2397
2398 return TRUE;
2399 }
2400
HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)2401 MS_U8 HAL_VPU_EX_CheckFreeStream(VPU_EX_Original_Stream eStream)
2402 {
2403 MS_U8 u8Idx = 0;
2404
2405 //VPRINTF("[NDec][%s][%d] eStream = %d\n", __FUNCTION__, __LINE__, eStream);
2406
2407 if(eStream == E_VPU_ORIGINAL_MAIN_STREAM)
2408 {
2409 if(pVPUHalContext->_stVPUStream[0].eDecodertype == E_VPU_EX_DECODER_NONE)
2410 {
2411 //VPRINTF("[NDec][%s][%d] main stream using u8Idx = 0\n", __FUNCTION__, __LINE__);
2412 return 0;
2413 }
2414 }
2415 else if(eStream == E_VPU_ORIGINAL_SUB_STREAM)
2416 {
2417 if(pVPUHalContext->_stVPUStream[1].eDecodertype == E_VPU_EX_DECODER_NONE)
2418 {
2419 //VPRINTF("[NDec][%s][%d] sub stream using u8Idx = 1\n", __FUNCTION__, __LINE__);
2420 return 1;
2421 }
2422 }
2423
2424 for (u8Idx = 0; u8Idx < MAX_SUPPORT_DECODER_NUM; u8Idx++)
2425 {
2426 if (pVPUHalContext->_stVPUStream[u8Idx].eDecodertype == E_VPU_EX_DECODER_NONE)
2427 break;
2428 }
2429
2430 if (u8Idx >= MAX_SUPPORT_DECODER_NUM)
2431 {
2432 VPU_MSG_ERR("all vpu free streams are occupied \n");
2433 return -1;
2434 }
2435
2436 VPU_MSG_DBG("available vpu free stream %d \n", u8Idx);
2437 return u8Idx;
2438 }
2439
HAL_VPU_EX_Init(VPU_EX_InitParam * InitParams)2440 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams)
2441 {
2442 VPU_MSG_DBG("Inv=%d, clk=%d\n", InitParams->bClockInv, InitParams->eClockSpeed);
2443
2444 // enable module
2445 _VPU_EX_ClockInv(InitParams->bClockInv);
2446 _VPU_EX_ClockSpeed(InitParams->eClockSpeed);
2447 HAL_VPU_EX_PowerCtrl(TRUE);
2448
2449 #ifdef CONFIG_MSTAR_CLKM
2450 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, TRUE);
2451 #endif
2452
2453 #ifdef CONFIG_MSTAR_SRAMPD
2454 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2455 HVD_Delay_ms(1);
2456 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2457 HVD_Delay_ms(1);
2458 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2459 HVD_Delay_ms(1);
2460 #endif
2461 #if 1 //Create VPU's own mutex
2462 //_HAL_VPU_MutexCreate();
2463 #else
2464 pVPUHalContext->s32VPUMutexID = InitParams->s32VPUMutexID;
2465 pVPUHalContext->u32VPUMutexTimeOut = InitParams->u32VPUMutexTimeout;
2466 #endif
2467
2468 return TRUE;
2469 }
2470
HAL_VPU_EX_DeInit(void)2471 MS_BOOL HAL_VPU_EX_DeInit(void)
2472 {
2473 if (0 != _VPU_EX_GetActiveCodecCnt())
2474 {
2475 VPU_MSG_DBG("do nothing since codec is active.\n");
2476 return TRUE;
2477 }
2478
2479 memset(&(pVPUHalContext->_stVPUDecMode),0,sizeof(VPU_EX_DecModCfg));
2480
2481 #ifdef CONFIG_MSTAR_CLKM
2482 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VD_MHEG5, FALSE);
2483 #else
2484 HAL_VPU_EX_PowerCtrl(FALSE);
2485 #endif
2486
2487 #ifdef CONFIG_MSTAR_SRAMPD
2488 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2, CODEC_SRAM_HVD_R2);
2489 HVD_Delay_ms(1);
2490 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU0_BWP, CODEC_SRAM_HVD_R2_MIU0_BWP);
2491 HVD_Delay_ms(1);
2492 _VPU_WriteWordMask(REG_CODEC_SRAM_SD_EN, ~CODEC_SRAM_HVD_R2_MIU1_BWP, CODEC_SRAM_HVD_R2_MIU1_BWP);
2493 HVD_Delay_ms(1);
2494 #endif
2495
2496 HAL_VPU_EX_SwRelseMAU();
2497 //_HAL_VPU_MutexDelete();
2498
2499 return TRUE;
2500 }
2501
HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)2502 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable)
2503 {
2504 if (bEnable)
2505 {
2506 _VPU_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
2507 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, REG_CHIPTOP_DUMMY_CODEC_ENABLE, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2508 pVPUHalContext->_bVPUPowered = TRUE;
2509 }
2510 else
2511 {
2512 _VPU_WriteWordMask(REG_TOP_VPU, TOP_CKG_VPU_DIS, TOP_CKG_VPU_DIS);
2513 _VPU_WriteWordMask( REG_CHIPTOP_DUMMY_CODEC, 0, REG_CHIPTOP_DUMMY_CODEC_ENABLE);
2514 pVPUHalContext->_bVPUPowered = FALSE;
2515 }
2516 }
2517
HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)2518 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable)
2519 {
2520 _VPU_MIU_SetReqMask(VPU_D_RW, bEnable);
2521 _VPU_MIU_SetReqMask(VPU_Q_RW, bEnable);
2522 _VPU_MIU_SetReqMask(VPU_I_R, bEnable);
2523 VPU_EX_TimerDelayMS(1);
2524 }
2525
2526 ///-----------------------------------------------------------------------------
2527 /// config AVCH264 CPU
2528 /// @param u32StAddr \b IN: CPU binary code base address in DRAM.
2529 /// @param u8dlend_en \b IN: endian
2530 /// - 1, little endian
2531 /// - 0, big endian
2532 ///-----------------------------------------------------------------------------
HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)2533 MS_BOOL HAL_VPU_EX_CPUSetting(MS_PHY u32StAddr)
2534 {
2535 MS_BOOL bRet = TRUE;
2536 MS_U32 u32Offset = 0;
2537 MS_U16 tempreg = 0;
2538 MS_U8 u8MiuSel;
2539 //MS_U32 u32TmpStartOffset;
2540
2541 _phy_to_miu_offset(u8MiuSel, u32Offset, u32StAddr);
2542
2543 _VPU_Write2Byte(VPU_REG_SPI_BASE, 0xC000);
2544 _VPU_WriteWordMask( VPU_REG_MIU_LAST , 0 , VPU_REG_MIU_LAST_EN );
2545 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SPI_BOOT );
2546 _VPU_WriteWordMask( VPU_REG_CPU_SETTING , 0 , VPU_REG_CPU_SDRAM_BOOT );
2547 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_L, 0xc000);
2548 _VPU_Write2Byte(VPU_REG_DQMEM_MASK_H, 0xffff);
2549 _VPU_Write2Byte(VPU_REG_IO1_BASE, 0xf900); // UART BASE
2550 _VPU_Write2Byte(VPU_REG_IO2_BASE, 0xf000);
2551 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_L, 0x0000);
2552 _VPU_Write2Byte(VPU_REG_DQMEM_BASE_H, 0xf200);
2553
2554 #if (HVD_ENABLE_IQMEM)
2555 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_L, (MS_U16)(VPU_IQMEM_BASE & 0x0000ffff));
2556 _VPU_Write2Byte(VPU_REG_IQMEM_BASE_H, (MS_U16)((VPU_IQMEM_BASE>>16) & 0xffff));
2557 #endif
2558
2559 #if (VPU_FORCE_MIU_MODE)
2560 // Data sram base Unit: byte address
2561 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2562 _VPU_Write2Byte(VPU_REG_DCU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2563 // Instruction sram base Unit: byte address
2564 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_L, (MS_U16)(u32Offset & 0x0000ffff)) ;
2565 _VPU_Write2Byte(VPU_REG_ICU_SDR_BASE_H, (MS_U16)((u32Offset >>16) & 0xffff));
2566
2567 #ifndef HAL_FEATURE_MAU
2568 MS_U16 r2_miu_sel = (_VPU_Read2Byte(VPU_REG_R2_MI_SEL_BASE) & 0xfff);
2569 #endif
2570 VPRINTF("\033[1;32m[%s] %d u8MiuSel = %d r2_miu_sel = 0x%x \033[m\n",__FUNCTION__,__LINE__,u8MiuSel,r2_miu_sel);
2571
2572 //use force miu mode
2573 if(u8MiuSel == E_CHIP_MIU_0)
2574 {
2575 #ifdef HAL_FEATURE_MAU
2576 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2577 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2578 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2579 #else
2580 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel);//1 Manhattan has no MAU, use this register to select miu
2581 #endif
2582 }
2583 else if(u8MiuSel == E_CHIP_MIU_1)
2584 {
2585 #ifdef HAL_FEATURE_MAU
2586 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8900);
2587 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8b00);
2588 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2589 #else
2590 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0x5000);
2591 #endif
2592 }
2593 else //miu 2
2594 {
2595 #ifdef HAL_FEATURE_MAU
2596 _VPU_Write2Byte(MAU1_MIU_SEL, 0x8b00);
2597 _VPU_Write2Byte(MAU1_LV2_0_MIU_SEL, 0x8900);
2598 _VPU_Write2Byte(MAU1_LV2_1_MIU_SEL, 0x8900);
2599 #else
2600 _VPU_Write2Byte(VPU_REG_R2_MI_SEL_BASE, r2_miu_sel|0xa000);
2601 #endif
2602 }
2603 #else
2604 ///TODO:
2605 #endif
2606
2607
2608 tempreg = _VPU_Read2Byte(VPU_REG_CONTROL_SET);
2609 tempreg |= VPU_REG_IO2_EN;
2610 tempreg |= VPU_REG_QMEM_SPACE_EN;
2611 _VPU_Write2Byte(VPU_REG_CONTROL_SET, tempreg);
2612
2613 return bRet;
2614 }
2615
2616 ///-----------------------------------------------------------------------------
2617 /// Set IQMem data access mode or instruction fetch mode
2618 /// @param u8dlend_en \b IN: endian
2619 /// - 1, switch to data access mode
2620 /// - 0, switch to instruction fetch mode
2621 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)2622 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable)
2623 {
2624
2625 if(bEnable){
2626
2627 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)|0x10);
2628 _VPU_Write2Byte(VPU_REG_QMEM_OWNER, _VPU_Read2Byte(VPU_REG_QMEM_OWNER)&0xFFDE);
2629
2630 }
2631 else{
2632
2633 _VPU_Write2Byte(VPU_REG_IQMEM_SETTING, _VPU_Read2Byte(VPU_REG_IQMEM_SETTING)& 0xFFEF);
2634
2635 }
2636 }
2637
2638 ///-----------------------------------------------------------------------------
2639 /// H.264 SW reset
2640 /// @return TRUE or FALSE
2641 /// - TRUE, Success
2642 /// - FALSE, Failed
2643 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)2644 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2645 {
2646 MS_U16 tempreg = 0, tempreg1 = 0;
2647 MS_U16 idle_cnt;
2648 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2649 tempreg |= VPU_REG_CPU_STALL_EN;
2650 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2651
2652 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2653 // 0xf means VPU is not stalled
2654 if (tempreg & 0xf || pVPUHalContext->u8ForceRst == 1) {
2655 pVPUHalContext->u8ForceRst = 0;
2656 // write R2 RIU registers to select DCU/ICU debug data
2657 // Writing these registers here provides enough time for them to
2658 // take effect.
2659 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2660 tempreg1 |= VPU_REG_DCU_DBG_SEL_0 | VPU_REG_DCU_DBG_SEL_1;
2661 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2662 _VPU_Write2Byte(VPU_REG_ICU_DBG_SEL, 0);
2663
2664 // wait at least 1ms for VPU_REG_CPU_STALL_EN to take effect
2665 // This step is important because in the next step we want to make
2666 // sure "DCU is not replaying when R2 is stalled".
2667 idle_cnt = 100;
2668 do
2669 {
2670 if (--idle_cnt == 0)
2671 {
2672 printf("VPU_REG_CPU_STALL_EN is not set\n");
2673 break;
2674 }
2675 MsOS_DelayTask(1);
2676 } while ((_VPU_Read2Byte(VPU_REG_CPU_CONFIG) & VPU_REG_CPU_STALL_EN) == 0);
2677 // check CPU status: DCU should NOT be replaying
2678 // If R2 has been stalled, we can guarantee that if we found DCU is
2679 // NOT replaying, it will NOT replay later even CPU is going to issue
2680 // a load/store instruction.
2681 idle_cnt = 100;
2682 while (_VPU_Read2Byte(VPU_REG_CPU_STATUS) & VPU_REG_CPU_D_REPLAY)
2683 {
2684 if (--idle_cnt == 0)
2685 {
2686 printf("DCU is replaying\n");
2687 break;
2688 }
2689 MsOS_DelayTask(1);
2690 }
2691 // wait 1ms to prevent race condition between (1) DCU is not
2692 // replaying, and (2) BIU start to doing new job or ICU start to
2693 // fetch new instruction
2694 MsOS_DelayTask(1);
2695
2696 // check BIU should be empty
2697 idle_cnt = 100;
2698 while ( (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & VPU_REG_BIU_EMPTY) == 0 )
2699 {
2700 if (--idle_cnt == 0)
2701 {
2702 printf("BIU DCU idle time out~~~~~\n");
2703 break;
2704 }
2705 MsOS_DelayTask(1);
2706 }
2707
2708 // check CPU is not requesting ICU
2709 idle_cnt = 100;
2710 while (_VPU_Read2Byte(VPU_REG_ICU_DBG_DAT0) & VPU_REG_ICPU_REQ)
2711 {
2712 if (--idle_cnt == 0)
2713 {
2714 printf("CPU keeps requesting ICU\n");
2715 break;
2716 }
2717 MsOS_DelayTask(1);
2718 }
2719
2720 // wait 1ms to avoid race condition of (1) CPU stop requesting ICU, and
2721 // (2) ISB start to fetch
2722 MsOS_DelayTask(1);
2723
2724 // check ISB should be idle
2725 idle_cnt = 100;
2726 while ( (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & VPU_REG_ISB_IDLE) == 0 )
2727 {
2728 if (--idle_cnt == 0)
2729 {
2730 printf("ISB is busy\n");
2731 break;
2732 }
2733 MsOS_DelayTask(1);
2734 }
2735 }
2736 #ifdef HAL_FEATURE_MAU
2737 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2738 if (bCheckMauIdle)
2739 {
2740 MS_U32 mau_idle_cnt = 100;// ms
2741 while (mau_idle_cnt)
2742 {
2743 if (TRUE == _VPU_EX_MAU_IDLE())
2744 {
2745 break;
2746 }
2747 mau_idle_cnt--;
2748 MsOS_DelayTask(1);
2749 }
2750
2751 if (mau_idle_cnt == 0)
2752 {
2753 printf("MAU idle time out~~~~~\n");
2754 }
2755 }
2756 #endif
2757
2758 // this command set MIU to block R2 (does not ack R2's request)
2759 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2760
2761 #ifdef HAL_FEATURE_MAU
2762 // reset MAU
2763 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2764 tempreg1 |= MAU1_REG_SW_RESET;
2765 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2766 #if defined(UDMA_FPGA_ENVI)
2767 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2768 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2769 #endif
2770 #endif
2771
2772 // reset R2
2773 // We should trigger MIU reset before R2 reset. If we set MIU/R2 reset
2774 // by the same RIU write, the R2 reset signal may reach afifo eralier
2775 // than MIU reset and afifo write pointer will be reset to position 0.
2776 // In this case, afifo consider it is not empty because read/write
2777 // pointer are mismatch and then BIU sends out unpredicted MIU request.
2778 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2779 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2780 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2781 VPU_EX_TimerDelayMS(1);
2782 tempreg &= ~VPU_REG_CPU_R2_EN;
2783 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2784 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2785
2786 VPU_EX_TimerDelayMS(1);
2787
2788 // this command set MIU to accept R2 (can ack R2's request)
2789 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2790
2791 pVPUHalContext->_bVPURsted = FALSE;
2792 return TRUE;
2793 }
2794 /*
2795 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle)
2796 {
2797 MS_U16 tempreg = 0, tempreg1 = 0;
2798 #ifndef HAL_FEATURE_MAU
2799 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2800 tempreg |= VPU_REG_CPU_STALL_EN;
2801 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2802
2803 MS_U32 idle_cnt = 100;// ms
2804 while (idle_cnt)
2805 {
2806 if (_VPU_Read2Byte(VPU_REG_ICU_STATUS) & (VPU_REG_ISB_IDLE | VPU_REG_ICU_IDLE))
2807 {
2808 break;
2809 }
2810 idle_cnt--;
2811 MsOS_DelayTask(1);
2812 }
2813
2814 if (idle_cnt == 0)
2815 {
2816 printf("ISB ICU idle time out~~~~~\n");
2817 }
2818
2819 tempreg1 = _VPU_Read2Byte(VPU_REG_DCU_DBG_SEL);
2820 tempreg1 |= VPU_REG_DCU_DBG_SEL_0;
2821 tempreg1 |= VPU_REG_DCU_DBG_SEL_1;
2822 _VPU_Write2Byte(VPU_REG_DCU_DBG_SEL, tempreg1);
2823
2824 MS_U32 idle_cnt_1 = 100;// ms
2825 while (idle_cnt_1)
2826 {
2827 if (_VPU_Read2Byte(VPU_REG_DCU_STATUS) & (VPU_REG_BIU_EMPTY))
2828 {
2829 break;
2830 }
2831 idle_cnt_1--;
2832 MsOS_DelayTask(1);
2833 }
2834
2835 if (idle_cnt_1 == 0)
2836 {
2837 printf("BIU DCU idle time out~~~~~\n");
2838 }
2839
2840 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2841 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2842 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2843 VPU_EX_TimerDelayMS(1);
2844 tempreg &= ~VPU_REG_CPU_R2_EN;
2845 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2846 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2847
2848 #else
2849 //MAU has been removed since manhattan, so it is not necessary to check MAU status
2850
2851 if (bCheckMauIdle)
2852 {
2853 MS_U32 mau_idle_cnt = 100;// ms
2854 while (mau_idle_cnt)
2855 {
2856 if (TRUE == _VPU_EX_MAU_IDLE())
2857 {
2858 break;
2859 }
2860 mau_idle_cnt--;
2861 MsOS_DelayTask(1);
2862 }
2863
2864 if (mau_idle_cnt == 0)
2865 {
2866 printf("MAU idle time out~~~~~\n");
2867 }
2868 }
2869
2870
2871 HAL_VPU_EX_MIU_RW_Protect(TRUE);
2872
2873 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2874 tempreg1 |= MAU1_REG_SW_RESET;
2875 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2876
2877 #if defined(UDMA_FPGA_ENVI)
2878 tempreg = _VPU_Read2Byte(VPU_REG_RESET);
2879 _VPU_Write2Byte(VPU_REG_RESET, (tempreg& 0xfffd));
2880 #endif
2881
2882 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2883 tempreg &= ~VPU_REG_CPU_R2_EN;
2884 tempreg &= ~VPU_REG_CPU_SW_RSTZ;
2885 tempreg &= ~VPU_REG_CPU_MIU_SW_RSTZ;
2886 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2887 #endif
2888 VPU_EX_TimerDelayMS(1);
2889 HAL_VPU_EX_MIU_RW_Protect(FALSE);
2890
2891 pVPUHalContext->_bVPURsted = FALSE;
2892 return TRUE;
2893 }
2894 */
2895 ///-----------------------------------------------------------------------------
2896 /// CPU reset release
2897 ///-----------------------------------------------------------------------------
HAL_VPU_EX_SwRstRelse(void)2898 void HAL_VPU_EX_SwRstRelse(void)
2899 {
2900 MS_U16 tempreg = 0;
2901
2902 tempreg = _VPU_Read2Byte(VPU_REG_CPU_CONFIG);
2903 tempreg &= ~VPU_REG_CPU_STALL_EN;
2904 _VPU_Write2Byte(VPU_REG_CPU_CONFIG, tempreg);
2905
2906 tempreg = _VPU_Read2Byte(VPU_REG_CPU_SETTING);
2907 tempreg |= VPU_REG_CPU_MIU_SW_RSTZ;
2908 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2909 VPU_EX_TimerDelayMS(1);
2910 tempreg |= VPU_REG_CPU_SW_RSTZ;
2911 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2912 VPU_EX_TimerDelayMS(1);
2913 tempreg |= VPU_REG_CPU_R2_EN;
2914 _VPU_Write2Byte(VPU_REG_CPU_SETTING, tempreg);
2915 #ifdef HAL_FEATURE_MAU
2916 MS_U16 tempreg1 = 0;
2917 tempreg1 = _VPU_Read2Byte(MAU1_CPU_RST);
2918 tempreg1 &= ~MAU1_REG_SW_RESET;
2919 _VPU_Write2Byte(MAU1_CPU_RST, tempreg1);
2920 #endif
2921 pVPUHalContext->_bVPURsted = TRUE;
2922 }
2923
HAL_VPU_EX_SwRelseMAU(void)2924 void HAL_VPU_EX_SwRelseMAU(void)
2925 {
2926
2927 #ifdef HAL_FEATURE_MAU
2928 MS_U16 tempreg = 0;
2929 tempreg = _VPU_Read2Byte(MAU1_CPU_RST);
2930 tempreg &= ~MAU1_REG_SW_RESET;
2931 _VPU_Write2Byte(MAU1_CPU_RST, tempreg);
2932 #endif
2933 }
2934
HAL_VPU_EX_MemRead(MS_VIRT u32Addr)2935 MS_U32 HAL_VPU_EX_MemRead(MS_VIRT u32Addr)
2936 {
2937 MS_U32 u32value = 0;
2938
2939 return u32value;
2940 }
2941
HAL_VPU_EX_MemWrite(MS_VIRT u32Addr,MS_U32 u32value)2942 MS_BOOL HAL_VPU_EX_MemWrite(MS_VIRT u32Addr, MS_U32 u32value)
2943 {
2944 MS_BOOL bRet = TRUE;
2945
2946 return bRet;
2947 }
2948
2949 ///-----------------------------------------------------------------------------
2950 /// Check AVCH264 Ready or not
2951 /// @return TRUE or FALSE
2952 /// - TRUE, MailBox is free
2953 /// - FALSE, MailBox is busy
2954 /// @param u8MBox \b IN: MailBox to check
2955 /// - AVCH264_HI_MBOX0,
2956 /// - AVCH264_HI_MBOX1,
2957 /// - AVCH264_RISC_MBOX0,
2958 /// - AVCH264_RISC_MBOX1,
2959 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRdy(MS_U32 u32type)2960 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type)
2961 {
2962 MS_BOOL bResult = FALSE;
2963
2964 switch (u32type)
2965 {
2966 case VPU_HI_MBOX0:
2967 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
2968 break;
2969 case VPU_HI_MBOX1:
2970 bResult = (_VPU_Read2Byte(VPU_REG_HI_MBOX_RDY) & VPU_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
2971 break;
2972 case VPU_RISC_MBOX0:
2973 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
2974 break;
2975 case VPU_RISC_MBOX1:
2976 bResult = (_VPU_Read2Byte(VPU_REG_RISC_MBOX_RDY) & VPU_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
2977 break;
2978 default:
2979 break;
2980 }
2981 return bResult;
2982 }
2983
2984
2985 ///-----------------------------------------------------------------------------
2986 /// Read message from AVCH264
2987 /// @return TRUE or FALSE
2988 /// - TRUE, success
2989 /// - FALSE, failed
2990 /// @param u8MBox \b IN: MailBox to read
2991 /// - AVCH264_RISC_MBOX0
2992 /// - AVCH264_RISC_MBOX1
2993 /// @param u32Msg \b OUT: message read
2994 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxRead(MS_U32 u32type,MS_U32 * u32Msg)2995 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 * u32Msg)
2996 {
2997 MS_BOOL bResult = TRUE;
2998
2999 switch (u32type)
3000 {
3001 case VPU_HI_MBOX0:
3002 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_H)) << 16) |
3003 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX0_L)));
3004 break;
3005 case VPU_HI_MBOX1:
3006 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_H)) << 16) |
3007 ((MS_U32) (_VPU_Read2Byte(VPU_REG_HI_MBOX1_L)));
3008 break;
3009 case VPU_RISC_MBOX0:
3010 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_H)) << 16) |
3011 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX0_L)));
3012 break;
3013 case VPU_RISC_MBOX1:
3014 *u32Msg = ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_H)) << 16) |
3015 ((MS_U32) (_VPU_Read2Byte(VPU_REG_RISC_MBOX1_L)));
3016 break;
3017 default:
3018 *u32Msg = 0;
3019 bResult = FALSE;
3020 break;
3021 }
3022 return bResult;
3023 }
3024
3025 ///-----------------------------------------------------------------------------
3026 /// Mailbox from AVCH264 clear bit resest
3027 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxClear(MS_U32 u32type)3028 void HAL_VPU_EX_MBoxClear(MS_U32 u32type)
3029 {
3030 switch (u32type)
3031 {
3032 case VPU_RISC_MBOX0:
3033 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX0_CLR, VPU_REG_RISC_MBOX0_CLR);
3034 break;
3035 case VPU_RISC_MBOX1:
3036 _VPU_WriteWordMask(VPU_REG_RISC_MBOX_CLR, VPU_REG_RISC_MBOX1_CLR, VPU_REG_RISC_MBOX1_CLR);
3037 break;
3038 default:
3039 break;
3040 }
3041 }
3042
3043 ///-----------------------------------------------------------------------------
3044 /// Send message to AVCH264
3045 /// @return TRUE or FALSE
3046 /// - TRUE, Success
3047 /// - FALSE, Failed
3048 /// @param u8MBox \b IN: MailBox
3049 /// - AVCH264_HI_MBOX0,
3050 /// - AVCH264_HI_MBOX1,
3051 ///-----------------------------------------------------------------------------
HAL_VPU_EX_MBoxSend(MS_U32 u32type,MS_U32 u32Msg)3052 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg)
3053 {
3054 MS_BOOL bResult = TRUE;
3055
3056 VPU_MSG_DBG("type=%u, msg=0x%x\n", u32type, u32Msg);
3057
3058 switch (u32type)
3059 {
3060 case VPU_HI_MBOX0:
3061 {
3062 _VPU_Write4Byte(VPU_REG_HI_MBOX0_L, u32Msg);
3063 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX0_SET, VPU_REG_HI_MBOX0_SET);
3064 break;
3065 }
3066 case VPU_HI_MBOX1:
3067 {
3068 _VPU_Write4Byte(VPU_REG_HI_MBOX1_L, u32Msg);
3069 _VPU_WriteWordMask(VPU_REG_HI_MBOX_SET, VPU_REG_HI_MBOX1_SET, VPU_REG_HI_MBOX1_SET);
3070 break;
3071 }
3072 default:
3073 {
3074 bResult = FALSE;
3075 break;
3076 }
3077 }
3078
3079 return bResult;
3080 }
3081
HAL_VPU_EX_GetProgCnt(void)3082 MS_U32 HAL_VPU_EX_GetProgCnt(void)
3083 {
3084
3085 MS_U16 expc_l=0;
3086 MS_U16 expc_h=0;
3087 expc_l = _VPU_Read2Byte(VPU_REG_EXPC_L) & 0xFFFF;
3088 expc_h = _VPU_Read2Byte(VPU_REG_EXPC_H) & 0xFFFF;
3089 return (((MS_U32)expc_h) << 16) | (MS_U32)expc_l;
3090 }
3091
HAL_VPU_EX_GetTaskId(MS_U32 u32Id)3092 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id)
3093 {
3094 return _VPU_EX_GetOffsetIdx(u32Id);
3095 }
3096
HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id,MS_VIRT u32ShmAddr)3097 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_VIRT u32ShmAddr)
3098 {
3099 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3100
3101 if (u32ShmAddr == 0)
3102 {
3103 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = 0xFFFFFFFFUL;
3104 }
3105 else
3106 {
3107 if (u8Offset == 0)
3108 {
3109 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr;
3110 }
3111 else if (u8Offset == 1)
3112 {
3113 pVPUHalContext->u32FWShareInfoAddr[u8Offset] = u32ShmAddr + TEE_ONE_TASK_SHM_SIZE;
3114 }
3115 }
3116
3117 VPU_MSG_DBG("set PA ShareInfoAddr[%d] = 0x%lx \n", u8Offset, (unsigned long)pVPUHalContext->u32FWShareInfoAddr[u8Offset]);
3118 return;
3119 }
3120
HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)3121 MS_VIRT HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id)
3122 {
3123 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3124
3125 return pVPUHalContext->u32FWShareInfoAddr[u8Offset];
3126 }
3127
3128 #if defined(VDEC_FW31)
HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)3129 MS_VIRT HAL_VPU_EX_GetVsyncAddrOffset(MS_U32 u32Id)
3130 {
3131 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3132 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3133 MS_VIRT VsyncBridgeOffset = 0;
3134
3135 if (VPUSHMAddr != 0) // TEE project
3136 {
3137 if ((u8Offset == 0) || (u8Offset == 1))
3138 {
3139 VsyncBridgeOffset = VSYNC_BRIDGE_OFFSET;
3140 }
3141 else
3142 {
3143 VsyncBridgeOffset = VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3144 }
3145 }
3146 else // normal project
3147 {
3148 if ((u8Offset == 0) || (u8Offset == 1))
3149 {
3150 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_OFFSET;
3151 }
3152 else
3153 {
3154 VsyncBridgeOffset = COMMON_AREA_START + VSYNC_BRIDGE_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3155 }
3156 }
3157
3158 return VsyncBridgeOffset;
3159 }
3160
HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)3161 MS_VIRT HAL_VPU_EX_GetVsyncExtAddrOffset(MS_U32 u32Id)
3162 {
3163 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3164 MS_VIRT VPUSHMAddr = HAL_VPU_EX_GetSHMAddr();
3165 MS_VIRT VsyncBridgeExtOffset = 0;
3166
3167 if (VPUSHMAddr != 0) // TEE project
3168 {
3169 if ((u8Offset == 0) || (u8Offset == 1))
3170 {
3171 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_OFFSET;
3172 }
3173 else
3174 {
3175 VsyncBridgeExtOffset = VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3176 }
3177 }
3178 else // normal project
3179 {
3180 if ((u8Offset == 0) || (u8Offset == 1))
3181 {
3182 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_OFFSET;
3183 }
3184 else
3185 {
3186 VsyncBridgeExtOffset = COMMON_AREA_START + VSYNC_BRIDGE_EXT_NWAY_OFFSET + (u8Offset - 2) * VSYNC_BRIDGE_INFO_SIZE;
3187 }
3188 }
3189
3190 return VsyncBridgeExtOffset;
3191 }
3192 #endif
3193
HAL_VPU_EX_IsPowered(void)3194 MS_BOOL HAL_VPU_EX_IsPowered(void)
3195 {
3196 return pVPUHalContext->_bVPUPowered;
3197 }
3198
HAL_VPU_EX_IsRsted(void)3199 MS_BOOL HAL_VPU_EX_IsRsted(void)
3200 {
3201 return pVPUHalContext->_bVPURsted;
3202 }
3203
HAL_VPU_EX_IsEVDR2(void)3204 MS_BOOL HAL_VPU_EX_IsEVDR2(void)
3205 {
3206 #ifdef EVDR2
3207 return TRUE;
3208 #else
3209 return FALSE;
3210 #endif
3211 }
3212
HAL_VPU_EX_MVDInUsed(void)3213 MS_BOOL HAL_VPU_EX_MVDInUsed(void)
3214 {
3215 //MVD is in used for MVD or HVD_TSP mode.
3216 MS_U8 i;
3217 MS_U8 u8UseCnt = 0;
3218
3219 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3220 {
3221 if ((pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_MVD) ||
3222 #ifdef VDEC3
3223 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_EVD) ||
3224 #endif
3225 (pVPUHalContext->_stVPUStream[i].eDecodertype == E_VPU_EX_DECODER_HVD) )
3226 {
3227 u8UseCnt++;
3228 }
3229 }
3230
3231 VPU_MSG_DBG("MVD u8UseCnt=%d\n", u8UseCnt);
3232
3233 if (u8UseCnt != 0)
3234 {
3235 return TRUE;
3236 }
3237 else
3238 {
3239 return FALSE;
3240 }
3241 }
3242
HAL_VPU_EX_HVDInUsed(void)3243 MS_BOOL HAL_VPU_EX_HVDInUsed(void)
3244 {
3245 //HVD is in used for HVD or MVD in sub stream.
3246 MS_U8 i;
3247 MS_U8 u8UseCnt = 0;
3248 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3249 {
3250 if ((E_VPU_EX_DECODER_HVD == pVPUHalContext->_stVPUStream[i].eDecodertype))
3251 {
3252 u8UseCnt++;
3253 }
3254 }
3255
3256 VPU_MSG_DBG("HVD u8UseCnt=%d\n", u8UseCnt);
3257
3258 if (u8UseCnt != 0)
3259 {
3260 return TRUE;
3261 }
3262 else
3263 {
3264 return FALSE;
3265 }
3266 }
3267
HAL_VPU_EX_Mutex_Lock(void)3268 void HAL_VPU_EX_Mutex_Lock(void)
3269 {
3270 _HAL_VPU_Entry();
3271 }
3272
HAL_VPU_EX_Mutex_UnLock(void)3273 void HAL_VPU_EX_Mutex_UnLock(void)
3274 {
3275 _HAL_VPU_Release();
3276 }
3277
3278 #ifdef VDEC3
HAL_VPU_EX_EVDInUsed(void)3279 MS_BOOL HAL_VPU_EX_EVDInUsed(void)
3280 {
3281 MS_U8 i;
3282 MS_U8 u8UseCnt = 0;
3283
3284 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3285 {
3286 if (E_VPU_EX_DECODER_EVD == pVPUHalContext->_stVPUStream[i].eDecodertype)
3287 {
3288 u8UseCnt++;
3289 }
3290 }
3291
3292 VPU_MSG_DBG("EVD u8UseCnt=%d\n", u8UseCnt);
3293
3294 if (u8UseCnt != 0)
3295 {
3296 return TRUE;
3297 }
3298 else
3299 {
3300 return FALSE;
3301 }
3302 }
3303
3304 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VPU_EX_G2VP9InUsed(void)3305 MS_BOOL HAL_VPU_EX_G2VP9InUsed(void)
3306 {
3307 MS_U8 i;
3308 MS_U8 u8UseCnt = 0;
3309
3310 for (i = 0; i < sizeof(pVPUHalContext->_stVPUStream) / sizeof(pVPUHalContext->_stVPUStream[0]); i++)
3311 {
3312 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[i].eDecodertype)
3313 {
3314 u8UseCnt++;
3315 }
3316 }
3317
3318 VPU_MSG_DBG("G2 VP9 u8UseCnt=%d\n", u8UseCnt);
3319
3320 if (u8UseCnt != 0)
3321 {
3322 return TRUE;
3323 }
3324 else
3325 {
3326 return FALSE;
3327 }
3328 }
3329 #endif
3330 #endif
3331
3332 //-----------------------------------------------------------------------------
3333 /// @brief \b Function \b Name: MDrv_HVD_EX_SetDbgLevel()
3334 /// @brief \b Function \b Description: Set debug level
3335 /// @param -elevel \b IN : debug level
3336 //-----------------------------------------------------------------------------
HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)3337 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel)
3338 {
3339 printf("%s eLevel=0x%x\n", __FUNCTION__, eLevel);
3340
3341 switch (eLevel)
3342 {
3343 case E_VPU_EX_UART_LEVEL_ERR:
3344 {
3345 u32VpuUartCtrl = E_VPU_UART_CTRL_ERR;
3346 break;
3347 }
3348 case E_VPU_EX_UART_LEVEL_INFO:
3349 {
3350 u32VpuUartCtrl = E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_ERR;
3351 break;
3352 }
3353 case E_VPU_EX_UART_LEVEL_DBG:
3354 {
3355 u32VpuUartCtrl = E_VPU_UART_CTRL_DBG | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO;
3356 break;
3357 }
3358 case E_VPU_EX_UART_LEVEL_TRACE:
3359 {
3360 u32VpuUartCtrl = E_VPU_UART_CTRL_TRACE | E_VPU_UART_CTRL_ERR | E_VPU_UART_CTRL_INFO | E_VPU_UART_CTRL_DBG;
3361 break;
3362 }
3363 case E_VPU_EX_UART_LEVEL_FW:
3364 {
3365 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3366 break;
3367 }
3368 default:
3369 {
3370 u32VpuUartCtrl = E_VPU_UART_CTRL_DISABLE;
3371 break;
3372 }
3373 }
3374 }
3375
HAL_VPU_EX_GetFWVer(MS_U32 u32Id,VPU_EX_FWVerType eVerType)3376 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType)
3377 {
3378 HVD_Return eCtrlRet = E_HVD_RETURN_FAIL;
3379 MS_U32 u32CmdArg = (MS_U32)eVerType;
3380 MS_U32 u32Version = 0xFFFFFFFF;
3381 eCtrlRet = HAL_HVD_EX_SetCmd(u32Id, E_DUAL_VERSION, u32CmdArg);
3382 if (E_HVD_RETURN_SUCCESS != eCtrlRet)
3383 {
3384 VPU_MSG_ERR("E_DUAL_VERSION NG eCtrlRet=%x\n", eCtrlRet);
3385 return u32Version;
3386 }
3387
3388 MS_BOOL bRet = false;
3389 MS_U32 u32TimeOut = 0xFFFFFFFF;
3390
3391 while(--u32TimeOut)
3392 {
3393 if(HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0))
3394 {
3395 bRet = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, &u32Version);
3396 if (false == bRet)
3397 {
3398 VPU_MSG_ERR("E_DUAL_VERSION NG bRet=%x\n", bRet);
3399 return u32Version;
3400 }
3401
3402 _VPU_WriteWordMask( VPU_REG_RISC_MBOX_CLR , VPU_REG_RISC_MBOX0_CLR , VPU_REG_RISC_MBOX0_CLR);
3403 VPU_MSG_DBG("E_DUAL_VERSION arg=%x u32Version = 0x%x\n", u32CmdArg, u32Version);
3404 return u32Version;
3405 }
3406 }
3407
3408 VPU_MSG_ERR("get E_DUAL_VERSION=%x timeout", eVerType);
3409
3410 return u32Version;
3411 }
3412
HAL_VPU_EX_NotSupportDS(void)3413 MS_BOOL HAL_VPU_EX_NotSupportDS(void)
3414 {
3415 return TRUE;// maserati disable SN DS
3416 }
3417
3418 //-----------------------------------------------------------------------------
3419 /// @brief \b Function \b Name: HAL_VPU_EX_MIU1BASE()
3420 /// @brief \b Function \b Description: Get VPU MIU base address
3421 /// @return - vpu MIU1 base
3422 //-----------------------------------------------------------------------------
HAL_VPU_EX_MIU1BASE(void)3423 MS_VIRT HAL_VPU_EX_MIU1BASE(void)
3424 {
3425 return VPU_MIU1BASE_ADDR;
3426 }
3427
3428
HAL_VPU_EX_GetSHMAddr(void)3429 MS_VIRT HAL_VPU_EX_GetSHMAddr(void)
3430 {
3431 if(pVPUHalContext->bEnableVPUSecureMode == FALSE)
3432 {
3433 return 0;
3434 }
3435 return pVPUHalContext->u32VPUSHMAddr;
3436 }
HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)3437 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable)
3438 {
3439 pVPUHalContext->bEnableVPUSecureMode = enable;
3440 return TRUE;
3441 }
3442
HAL_VPU_EX_CHIP_Capability(void * pHWCap)3443 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap)
3444 {
3445 ((VDEC_HwCap*)pHWCap)->u8Cap_Support_Decoder_Num = 2;
3446
3447 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG2 = TRUE;
3448 ((VDEC_HwCap*)pHWCap)->bCap_Support_H263 = TRUE;
3449 ((VDEC_HwCap*)pHWCap)->bCap_Support_MPEG4 = TRUE;
3450 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX311 = TRUE;
3451 ((VDEC_HwCap*)pHWCap)->bCap_Support_DIVX412 = TRUE;
3452 ((VDEC_HwCap*)pHWCap)->bCap_Support_FLV = TRUE;
3453 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1ADV = TRUE;
3454 ((VDEC_HwCap*)pHWCap)->bCap_Support_VC1MAIN = TRUE;
3455
3456 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV8 = TRUE;
3457 ((VDEC_HwCap*)pHWCap)->bCap_Support_RV9 = TRUE;
3458 ((VDEC_HwCap*)pHWCap)->bCap_Support_H264 = TRUE;
3459 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS = TRUE;
3460 ((VDEC_HwCap*)pHWCap)->bCap_Support_MJPEG = TRUE;
3461 ((VDEC_HwCap*)pHWCap)->bCap_Support_MVC = TRUE;
3462 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP8 = TRUE;
3463 ((VDEC_HwCap*)pHWCap)->bCap_Support_HEVC = TRUE;
3464 ((VDEC_HwCap*)pHWCap)->bCap_Support_VP9 = TRUE;
3465 ((VDEC_HwCap*)pHWCap)->bCap_Support_AVS_PLUS = TRUE;
3466
3467 return TRUE;
3468 }
3469
3470 //-----------------------------------------------------------------------------
3471 /// @brief \b Function \b Name: HAL_VPU_EX_GetCodecCapInfo()
3472 /// @brief \b Function \b Description: Get chip codec capability (for vudu)
3473 /// @return - success/fail
3474 //-----------------------------------------------------------------------------
HAL_VPU_EX_GetCodecCapInfo(int eCodecType,VDEC_EX_CODEC_CAP_INFO * pCodecCapInfo)3475 MS_BOOL HAL_VPU_EX_GetCodecCapInfo( int eCodecType, VDEC_EX_CODEC_CAP_INFO *pCodecCapInfo)
3476 {
3477 #define MAX_CAPABILITY_INFO_NUM 8
3478 #define MAX_CODEC_TYPE_NUM 18
3479
3480 unsigned int capability[MAX_CODEC_TYPE_NUM][MAX_CAPABILITY_INFO_NUM] =
3481 {
3482 //width, height , frmrate, profile, level, version bit rate reserved2
3483 { 0, 0, 0, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 0, 0},//E_HVD_EX_CODEC_TYPE_NONE
3484 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP2_MAIN, E_VDEC_EX_CODEC_LEVEL_MP2_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG2
3485 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_H263_BASELINE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_H263_1, 40, 0},//E_HVD_EX_CODEC_TYPE_H263
3486 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_MP4_ASP, E_VDEC_EX_CODEC_LEVEL_MP4_L5, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_MPEG4
3487 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_311, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX311
3488 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_DIVX_6, 40, 0},//E_HVD_EX_CODEC_TYPE_DIVX412
3489 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_FLV_1, 40, 0},//E_HVD_EX_CODEC_TYPE_FLV
3490 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_VC1_AP, E_VDEC_EX_CODEC_LEVEL_VC1_L3, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_ADV
3491 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_RCV_MAIN, E_VDEC_EX_CODEC_LEVEL_RCV_HIGH, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_VC1_MAIN (RCV)
3492 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV8
3493 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 40, 0},//E_HVD_EX_CODEC_TYPE_RV9
3494 { 4096, 2160, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 135, 0},//E_HVD_EX_CODEC_TYPE_H264
3495 { 1920, 1080, 60, E_VDEC_EX_CODEC_PROFILE_AVS_BROADCASTING, E_VDEC_EX_CODEC_LEVEL_AVS_6010860, E_VDEC_EX_CODEC_VERSION_NONE, 50, 0},//E_HVD_EX_CODEC_TYPE_AVS
3496 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 10, 0},//E_HVD_EX_CODEC_TYPE_MJPEG
3497 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_H264_HIP, E_VDEC_EX_CODEC_LEVEL_H264_5_1, E_VDEC_EX_CODEC_VERSION_NONE, 80, 0},//E_HVD_EX_CODEC_TYPE_MVC
3498 { 1920, 1080, 30, E_VDEC_EX_CODEC_PROFILE_NONE, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 20, 0},//E_HVD_EX_CODEC_TYPE_VP8
3499 { 4096, 2160, 60, E_VDEC_EX_CODEC_PROFILE_H265_MAIN_10, E_VDEC_EX_CODEC_LEVEL_H265_5_1_HT, E_VDEC_EX_CODEC_VERSION_NONE, 160, 0},//E_HVD_EX_CODEC_TYPE_HEVC
3500 { 4096, 2160, 60, E_VDEC_EX_CODEC_PROFILE_VP9_2, E_VDEC_EX_CODEC_LEVEL_NONE, E_VDEC_EX_CODEC_VERSION_NONE, 160, 0},//E_HVD_EX_CODEC_TYPE_VP9
3501 };
3502
3503 if(eCodecType < MAX_CODEC_TYPE_NUM)
3504 {
3505 pCodecCapInfo->u16CodecCapWidth = capability[eCodecType][0];
3506 pCodecCapInfo->u16CodecCapHeight = capability[eCodecType][1];
3507 pCodecCapInfo->u8CodecCapFrameRate = capability[eCodecType][2];
3508 pCodecCapInfo->u8CodecCapProfile = capability[eCodecType][3];
3509 pCodecCapInfo->u8CodecCapLevel = capability[eCodecType][4];
3510 pCodecCapInfo->u8CodecCapVersion = capability[eCodecType][5];
3511 return TRUE;
3512 }
3513 else
3514 {
3515 return FALSE;
3516 }
3517 }
3518
3519 #ifdef VDEC3
HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3520 void HAL_VPU_EX_SetBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3521 {
3522 (void) u32Id;
3523 BBU_STATE *bbu_state;
3524
3525 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3526 || (eDecType == E_VPU_EX_DECODER_VP8)
3527 #if SUPPORT_G2VP9
3528 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3529 #endif
3530 )
3531 {
3532 // MVD should not call this function.
3533 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3534 return;
3535 }
3536
3537 switch (eDecType)
3538 {
3539 case E_VPU_EX_DECODER_EVD:
3540 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3541 break;
3542 case E_VPU_EX_DECODER_HVD:
3543 case E_VPU_EX_DECODER_RVD:
3544 case E_VPU_EX_DECODER_MVC:
3545 default:
3546 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3547 break;
3548 }
3549
3550 bbu_state[u32BBUId].u8RegSetting |= u8TypeBit;
3551 return;
3552 }
3553
HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType,MS_U8 u8TypeBit)3554 MS_BOOL HAL_VPU_EX_CheckBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType, MS_U8 u8TypeBit)
3555 {
3556 (void) u32Id;
3557 BBU_STATE *bbu_state;
3558
3559 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3560 || (eDecType == E_VPU_EX_DECODER_VP8)
3561 #if SUPPORT_G2VP9
3562 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3563 #endif
3564 )
3565 {
3566 // MVD should not call this function.
3567 // VP8 and G2_VP9 don't have the concept of BBU, so we just return TRUE and not set related registers.
3568 return TRUE;
3569 }
3570
3571 switch (eDecType)
3572 {
3573 case E_VPU_EX_DECODER_EVD:
3574 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3575 break;
3576 case E_VPU_EX_DECODER_HVD:
3577 case E_VPU_EX_DECODER_RVD:
3578 case E_VPU_EX_DECODER_MVC:
3579 default:
3580 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3581 break;
3582 }
3583
3584 return (bbu_state[u32BBUId].u8RegSetting & u8TypeBit);
3585 }
3586
HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_DecoderType eDecType)3587 void HAL_VPU_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_DecoderType eDecType)
3588 {
3589 (void) u32Id;
3590 BBU_STATE *bbu_state;
3591
3592 if ( (eDecType == E_VPU_EX_DECODER_MVD)
3593 || (eDecType == E_VPU_EX_DECODER_VP8)
3594 #if SUPPORT_G2VP9
3595 || (eDecType == E_VPU_EX_DECODER_G2VP9)
3596 #endif
3597 )
3598 {
3599 // MVD should not call this function.
3600 // VP8 and G2_VP9 don't have the concept of BBU, so we just return.
3601 return;
3602 }
3603
3604 switch (eDecType)
3605 {
3606 case E_VPU_EX_DECODER_EVD:
3607 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3608 break;
3609 case E_VPU_EX_DECODER_HVD:
3610 case E_VPU_EX_DECODER_RVD:
3611 case E_VPU_EX_DECODER_MVC:
3612 default:
3613 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3614 break;
3615 }
3616
3617 if (bbu_state[u32BBUId].u32Used == 0)
3618 {
3619 bbu_state[u32BBUId].u8RegSetting = 0;
3620 }
3621
3622 return;
3623 }
3624
HAL_VPU_EX_GetBBUId(MS_U32 u32Id,VPU_EX_TaskInfo * pTaskInfo,MS_BOOL bShareBBU)3625 MS_U32 HAL_VPU_EX_GetBBUId(MS_U32 u32Id, VPU_EX_TaskInfo *pTaskInfo, MS_BOOL bShareBBU)
3626 {
3627 MS_U32 i, max_bbu_cnt;
3628 MS_U32 retBBUId = HAL_VPU_INVALID_BBU_ID;
3629
3630 if(pTaskInfo == NULL)
3631 return retBBUId;
3632
3633 BBU_STATE *bbu_state;
3634 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3635 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3636
3637 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3638
3639 pVPUHalContext->u8HALId[u8TaskId] = pTaskInfo->u8HalId;
3640
3641 /* HVD_EX_MSG_ERR("[%d] DecType=0x%x \n", u32Id & 0xFF, pTaskInfo->eDecType);
3642 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3643 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3644
3645 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3646 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3647
3648 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3649 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3650 */
3651 #if 1
3652 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3653 {
3654 max_bbu_cnt = MAX_MVD_SLQ_COUNT;
3655 if (bTSP)
3656 {
3657 if ((u8TaskId < MAX_MVD_SLQ_COUNT) && (slq_state[u8TaskId].u32Used == 0))
3658 {
3659 VPRINTF("[NDec][0x%x][%d] MVD bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3660 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3661 slq_state[u8TaskId].bTSP = TRUE;
3662 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3663 return u8TaskId;
3664 }
3665 }
3666 else
3667 {
3668 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3669 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3670 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3671 {
3672 if (slq_state[i].u32Used != 0)
3673 {
3674 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && slq_state[i].bTSP == FALSE)
3675 {
3676 shared_bbu_idx = i; // recored the first used MM bbu for sharing
3677 }
3678 }
3679 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3680 {
3681 avaliable_bbu_idx = i; // recored the first empty bbu
3682 }
3683 }
3684
3685 VPRINTF("[NDec][0x%x][%d] MVD bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3686
3687 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // In Nstream mode, first priority is sharing bbu
3688 slq_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3689 slq_state[shared_bbu_idx].bTSP = FALSE;
3690 slq_state[shared_bbu_idx].bUsedbyMVD = TRUE;
3691 VPRINTF("[NDec][0x%x][%d] MVD shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3692 return shared_bbu_idx;
3693 }
3694 else if (slq_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3695 slq_state[u8TaskId].u32Used |= (1 << u8TaskId);
3696 slq_state[u8TaskId].bTSP = FALSE;
3697 slq_state[u8TaskId].bUsedbyMVD = TRUE;
3698
3699 if (bShareBBU == FALSE)
3700 {
3701 slq_state[u8TaskId].bTSP = TRUE;
3702 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3703 }
3704 VPRINTF("[NDec][0x%x][%d] MVD u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3705 return u8TaskId;
3706 }
3707 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3708 slq_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3709 slq_state[avaliable_bbu_idx].bTSP = FALSE;
3710 slq_state[avaliable_bbu_idx].bUsedbyMVD = TRUE;
3711
3712 if (bShareBBU == FALSE)
3713 {
3714 slq_state[avaliable_bbu_idx].bTSP = TRUE;
3715 VPRINTF("[NDec] MVD occupy one BBU_ID \n");
3716 }
3717 VPRINTF("[NDec][0x%x][%d] MVD avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3718 return avaliable_bbu_idx;
3719 }
3720 else {
3721 VPU_MSG_ERR("ERROR!!! MVD can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3722 }
3723 }
3724 }
3725 #if SUPPORT_G2VP9
3726 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3727 {
3728 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3729 // Don't care the return value, G2_VP9 will not use it.
3730 return 0;
3731 }
3732 #endif
3733 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3734 {
3735 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3736 // Don't care the return value, VP8 will not use it.
3737 MS_U8 u8Offset = _VPU_EX_GetOffsetIdx(u32Id);
3738 return u8Offset;
3739 //return 0;
3740 }
3741 else
3742 {
3743 switch (pTaskInfo->eDecType)
3744 {
3745 case E_VPU_EX_DECODER_EVD:
3746 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3747 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3748 break;
3749 case E_VPU_EX_DECODER_HVD:
3750 case E_VPU_EX_DECODER_RVD:
3751 case E_VPU_EX_DECODER_MVC:
3752 default:
3753 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3754 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3755 break;
3756 }
3757
3758 // FIXME: TSP assume bbu id = u8TaskId, so it does not support N decode. Use the same logic with MM to support it
3759 if (bTSP)
3760 {
3761 if ((u8TaskId < max_bbu_cnt) && (bbu_state[u8TaskId].u32Used == 0) && (slq_state[u8TaskId].u32Used == 0))
3762 {
3763 VPRINTF("[NDec][0x%x][%d] bTSP, use bbu %d \n", u32Id, u8TaskId, u8TaskId);
3764 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3765 bbu_state[u8TaskId].bTSP = TRUE;
3766 slq_state[u8TaskId].u32Used |= (1 << u8TaskId); // Record the HVD use the TSP parser
3767 slq_state[u8TaskId].bTSP = TRUE;
3768 slq_state[u8TaskId].bUsedbyMVD = FALSE;
3769 return u8TaskId;
3770 }
3771 }
3772 else
3773 {
3774 MS_U32 shared_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3775 MS_U32 avaliable_bbu_idx = HAL_VPU_INVALID_BBU_ID;
3776 for (i = 0; i < max_bbu_cnt; i++)
3777 {
3778 if (shared_bbu_idx == HAL_VPU_INVALID_BBU_ID && bbu_state[i].u32Used != 0)
3779 {
3780 if (bbu_state[i].bTSP == FALSE)
3781 {
3782 shared_bbu_idx = i;
3783 }
3784 }
3785 else if (avaliable_bbu_idx == HAL_VPU_INVALID_BBU_ID)
3786 {
3787 avaliable_bbu_idx = i;
3788 }
3789 }
3790
3791 VPRINTF("[NDec][0x%x][%d] bShareBBU %d, shared_bbu %d, avail_bbu %d \n", u32Id, u8TaskId, bShareBBU, shared_bbu_idx, avaliable_bbu_idx);
3792
3793 if ((bShareBBU == TRUE) && (shared_bbu_idx != HAL_VPU_INVALID_BBU_ID)) { // // In Nstream mode, first priority is sharing bbu
3794 bbu_state[shared_bbu_idx].u32Used |= (1 << u8TaskId);
3795 VPRINTF("[NDec][0x%x][%d] shared_bbu %d \n", u32Id, u8TaskId, shared_bbu_idx);
3796 return shared_bbu_idx;
3797 }
3798 else if (bbu_state[u8TaskId].u32Used == FALSE && u8TaskId < max_bbu_cnt) { // 2nd priority is task id
3799 bbu_state[u8TaskId].u32Used |= (1 << u8TaskId);
3800
3801 if (bShareBBU == FALSE)
3802 {
3803 bbu_state[u8TaskId].bTSP = TRUE;
3804 VPRINTF("[NDec] occupy one BBU_ID \n");
3805 }
3806 VPRINTF("[NDec][0x%x][%d] u8TaskId %d \n", u32Id, u8TaskId, u8TaskId);
3807 return u8TaskId;
3808 }
3809 else if (avaliable_bbu_idx != HAL_VPU_INVALID_BBU_ID && avaliable_bbu_idx < max_bbu_cnt) { // 3rd priority is avaliable bbu id
3810 bbu_state[avaliable_bbu_idx].u32Used |= (1 << u8TaskId);
3811
3812 if (bShareBBU == FALSE)
3813 {
3814 bbu_state[avaliable_bbu_idx].bTSP = TRUE;
3815 VPRINTF("[NDec] occupy one BBU_ID \n");
3816 }
3817 VPRINTF("[NDec][0x%x][%d] avaliable_bbu_idx %d \n", u32Id, u8TaskId, avaliable_bbu_idx);
3818 return avaliable_bbu_idx;
3819 }
3820 else {
3821 VPU_MSG_ERR("ERROR!!! can't get avaliable BBU ID taskId=%d at %s\n", u8TaskId, __FUNCTION__);
3822 }
3823 }
3824 }
3825 #else // The following source code is wiser selecting BBU id. Howerver, it need HW to support and we mark it temporarily.
3826 MS_U32 j;
3827 MS_BOOL Got = FALSE;
3828 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3829 {
3830 for (i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3831 {
3832 if(slq_state[i].u32Used != 0)
3833 {
3834 if(!bTSP && slq_state[i].bTSP == FALSE) // MVD non-first MM case
3835 {
3836 retBBUId = i;
3837 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3838 slq_state[retBBUId].bTSP = bTSP;
3839 slq_state[retBBUId].bUsedbyMVD = TRUE;
3840 return retBBUId;
3841 }
3842 }
3843 else if(!Got && slq_state[i].u32Used == 0) // MVD first MM or TS case
3844 {
3845 if(i < MAX_EVD_BBU_COUNT) // Trend to select used EVD BBU id
3846 {
3847 if(pVPUHalContext->stEVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stEVD_BBU_STATE[i].bTSP == FALSE)
3848 {
3849 Got = TRUE;
3850 retBBUId = i;
3851 }
3852 }
3853
3854 if(!Got && i < MAX_HVD_BBU_COUNT) // Trend to select used HVD BBU id
3855 {
3856 if(pVPUHalContext->stHVD_BBU_STATE[i].u32Used != 0 && pVPUHalContext->stHVD_BBU_STATE[i].bTSP == FALSE)
3857 {
3858 Got = TRUE;
3859 retBBUId = i;
3860 }
3861 }
3862
3863 if(!Got && retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used EVD BBU id, select the first BBU_ID
3864 retBBUId = i;
3865 }
3866 }
3867 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3868 {
3869 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3870 slq_state[retBBUId].bTSP = bTSP;
3871 slq_state[retBBUId].bUsedbyMVD = TRUE;
3872 }
3873 }
3874 #if SUPPORT_G2VP9
3875 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3876 {
3877 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
3878 // Don't care the return value, G2_VP9 will not use it.
3879 return 0;
3880 }
3881 #endif
3882 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
3883 {
3884 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
3885 // Don't care the return value, VP8 will not use it.
3886 return 0;
3887 }
3888 else // HVD/EVD case
3889 {
3890 switch (pTaskInfo->eDecType)
3891 {
3892 case E_VPU_EX_DECODER_EVD:
3893 case E_VPU_EX_DECODER_G2VP9:
3894 max_bbu_cnt = MAX_EVD_BBU_COUNT;
3895 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
3896 break;
3897 case E_VPU_EX_DECODER_HVD:
3898 case E_VPU_EX_DECODER_RVD:
3899 case E_VPU_EX_DECODER_MVC:
3900 default:
3901 max_bbu_cnt = MAX_HVD_BBU_COUNT;
3902 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
3903 break;
3904 }
3905
3906 for (i = 0; i < max_bbu_cnt; i++)
3907 {
3908 if(bbu_state[i].u32Used != 0)
3909 {
3910 if(!bTSP && bbu_state[i].bTSP == FALSE) // HVD/EVD non-first MM case
3911 {
3912 retBBUId = i;
3913 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3914 bbu_state[retBBUId].bTSP = bTSP;
3915 return retBBUId;
3916 }
3917 }
3918 else if(bbu_state[i].u32Used == 0) // HVD/EVD first MM or TS case
3919 {
3920 if(i < MAX_MVD_SLQ_COUNT)
3921 {
3922 if(!bTSP) //HVD/EVD first MM case
3923 {
3924 if( slq_state[i].u32Used != 0 && slq_state[i].bUsedbyMVD== TRUE) // HVD/EVD MM will trend to select used MVD SLQ id
3925 {
3926 retBBUId = i;
3927 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3928 bbu_state[retBBUId].bTSP = bTSP;
3929 return retBBUId;
3930 }
3931
3932 if(retBBUId == HAL_VPU_INVALID_BBU_ID) // if no used MVD SLQ id, select the first BBU_ID
3933 retBBUId = i;
3934 }
3935 else if(slq_state[i].u32Used == 0) //HVD/EVD TSP case, just find a empty slq id
3936 {
3937 retBBUId = i;
3938 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3939 bbu_state[retBBUId].bTSP = bTSP;
3940 slq_state[retBBUId].bUsedbyMVD = FALSE;
3941 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3942 slq_state[retBBUId].bTSP = bTSP;
3943 return retBBUId;
3944 }
3945 }
3946 }
3947 }
3948 if(retBBUId != HAL_VPU_INVALID_BBU_ID)
3949 {
3950 bbu_state[retBBUId].u32Used |= (1 << u8TaskId);
3951 bbu_state[retBBUId].bTSP = bTSP;
3952 if(bTSP)
3953 {
3954 slq_state[retBBUId].bUsedbyMVD = FALSE;
3955 slq_state[retBBUId].u32Used |= (1 << u8TaskId);
3956 slq_state[retBBUId].bTSP = bTSP;
3957 }
3958 }
3959 }
3960 #endif
3961 return retBBUId;
3962 }
3963
HAL_VPU_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId,VPU_EX_TaskInfo * pTaskInfo)3964 MS_BOOL HAL_VPU_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId, VPU_EX_TaskInfo *pTaskInfo)
3965 {
3966 MS_U32 max_bbu_cnt;
3967 BBU_STATE *bbu_state;
3968 SLQ_STATE *slq_state = &pVPUHalContext->stMVD_SLQ_STATE[0];
3969
3970 if(pTaskInfo == NULL)
3971 return FALSE;
3972 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3973 MS_BOOL bTSP = (pTaskInfo->eSrcType == E_VPU_EX_INPUT_TSP);
3974
3975 HVD_EX_MSG_DBG("[%d] DecType=0x%x \n", (int)(u32Id & 0xFF), pTaskInfo->eDecType);
3976 /* MS_U32 i;
3977 for(i = 0; i < MAX_MVD_SLQ_COUNT; i++)
3978 HVD_EX_MSG_ERR("slq_state[%d] u32Used=0x%x bTSP=%x bUsedbyMVD=%x\n",i,slq_state[i].u32Used,slq_state[i].bTSP,slq_state[i].bUsedbyMVD);
3979
3980 for(i = 0; i < MAX_EVD_BBU_COUNT; i++)
3981 HVD_EX_MSG_ERR("EVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stEVD_BBU_STATE[i].u32Used,pVPUHalContext->stEVD_BBU_STATE[i].bTSP);
3982
3983 for(i = 0; i < MAX_HVD_BBU_COUNT; i++)
3984 HVD_EX_MSG_ERR("HVD_BBU_state[%d] u32Used=0x%x bTSP=%x\n",i,pVPUHalContext->stHVD_BBU_STATE[i].u32Used,pVPUHalContext->stHVD_BBU_STATE[i].bTSP);
3985 */
3986 if(pTaskInfo->eDecType == E_VPU_EX_DECODER_MVD) // MVD case
3987 {
3988 // TO DO
3989 if(u32BBUId < MAX_MVD_SLQ_COUNT)
3990 {
3991 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
3992 slq_state[u32BBUId].bTSP = FALSE;
3993 slq_state[u32BBUId].bUsedbyMVD = FALSE;
3994 return TRUE;
3995 }
3996 }
3997 #if SUPPORT_G2VP9
3998 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_G2VP9) // G2_VP9 case
3999 {
4000 // G2_VP9 don't have the concept of BBU, so we don't need to record the hardware BBU usage situation
4001 return TRUE;
4002 }
4003 #endif
4004 else if(pTaskInfo->eDecType == E_VPU_EX_DECODER_VP8) // VP8 case
4005 {
4006 // G2_VP8 always use the same BBU, so we don't need to record the hardware BBU usage situation
4007 return TRUE;
4008 }
4009 else
4010 {
4011 switch (pTaskInfo->eDecType)
4012 {
4013 case E_VPU_EX_DECODER_EVD:
4014 max_bbu_cnt = MAX_EVD_BBU_COUNT;
4015 bbu_state = &pVPUHalContext->stEVD_BBU_STATE[0];
4016 break;
4017 case E_VPU_EX_DECODER_HVD:
4018 case E_VPU_EX_DECODER_RVD:
4019 case E_VPU_EX_DECODER_MVC:
4020 default:
4021 max_bbu_cnt = MAX_HVD_BBU_COUNT;
4022 bbu_state = &pVPUHalContext->stHVD_BBU_STATE[0];
4023 break;
4024 }
4025
4026 if (u32BBUId < max_bbu_cnt)
4027 {
4028 bbu_state[u32BBUId].u32Used &= ~(1 << u8TaskId);
4029 bbu_state[u32BBUId].bTSP = FALSE;
4030
4031 if (bTSP)
4032 {
4033 slq_state[u32BBUId].u32Used &= ~(1 << u8TaskId); // Record the HVD use the TSP parser
4034 slq_state[u32BBUId].bTSP = FALSE;
4035 slq_state[u32BBUId].bUsedbyMVD = FALSE;
4036 }
4037
4038 #if 1
4039 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, pTaskInfo->eDecType);
4040 #else
4041 if (bbu_state[u32BBUId].u32Used == 0)
4042 {
4043 bbu_state[u32BBUId].u8RegSetting = 0; // clear record of both NAL_TBL and ES_BUFFER
4044 }
4045 #endif
4046
4047 return TRUE;
4048 }
4049 }
4050 return FALSE;
4051 }
4052
HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)4053 MS_U32 HAL_VPU_EX_GetVBBUVacancy(MS_VIRT u32VBBUAddr)
4054 {
4055 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4056
4057 if (CHECK_NULL_PTR(pstVBBU))
4058 return 0;
4059 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4060 MS_U32 u32RdPtr = pstVBBU->u32RdPtr;
4061 MS_U32 u32Vacancy = 0;
4062
4063 if (u32WrPtr == u32RdPtr)
4064 {
4065 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT;
4066 }
4067 else if (u32WrPtr > u32RdPtr)
4068 {
4069 u32Vacancy = MAX_VDEC_VBBU_ENTRY_COUNT - (u32WrPtr - u32RdPtr);
4070 }
4071 else
4072 {
4073 u32Vacancy = u32RdPtr - u32WrPtr - 1;
4074 }
4075
4076 return u32Vacancy;
4077 }
4078
HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)4079 MS_U32 HAL_VPU_EX_GetInputQueueNum(MS_U32 u32Id)
4080 {
4081 return MAX_VDEC_VBBU_ENTRY_COUNT;
4082 }
4083
HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)4084 MS_PHY HAL_VPU_EX_GetFWCodeAddr(MS_U32 u32Id)
4085 {
4086 return pVPUHalContext->u32FWCodeAddr;
4087 }
4088
HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4089 MS_VIRT HAL_VPU_EX_GetESReadPtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4090 {
4091 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4092 #if SUPPORT_G2VP9
4093 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4094 #endif
4095
4096 if (CHECK_NULL_PTR(pstVBBU))
4097 return FALSE;
4098 MsOS_ReadMemory();
4099 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry *) &pstVBBU->stEntry[pstVBBU->u32RdPtr];
4100
4101 if(NULL == stEntry)
4102 {
4103 return 0;
4104 }
4105
4106 // ALOGE("JJJ1: %d %d %d", pstVBBU->u32RdPtr, pstVBBU->u32WrPtr, stEntry->u32Offset);
4107 if (pstVBBU->u32RdPtr == pstVBBU->u32WrPtr)
4108 {
4109 return HAL_VPU_EX_GetESWritePtr(u32Id, u32VBBUAddr);
4110 }
4111 else
4112 {
4113 #if SUPPORT_G2VP9
4114 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4115 {
4116 if (stEntry->u32Offset == 0)
4117 return 0;
4118 else
4119 return stEntry->u32Offset - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4120 }
4121 else
4122 #endif
4123 {
4124 return stEntry->u32Offset;
4125 }
4126 }
4127 }
4128
HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id,MS_VIRT u32VBBUAddr)4129 MS_VIRT HAL_VPU_EX_GetESWritePtr(MS_U32 u32Id, MS_VIRT u32VBBUAddr)
4130 {
4131 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4132 VDEC_VBBU_Entry *stEntry;
4133 #if SUPPORT_G2VP9
4134 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4135 #endif
4136
4137 MsOS_ReadMemory();
4138 if (CHECK_NULL_PTR(pstVBBU))
4139 return 0;
4140 MS_U32 u32WrPtr = pstVBBU->u32WrPtr;
4141
4142 if (u32WrPtr == 0)
4143 u32WrPtr = MAX_VDEC_VBBU_ENTRY_COUNT;
4144 else
4145 u32WrPtr--;
4146
4147 stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[u32WrPtr];
4148
4149 if(NULL == stEntry)
4150 {
4151 return 0;
4152 }
4153
4154 //ALOGE("JJJ2: %d %d %d %d", pstVBBU->u32RdPtr, u32WrPtr, stEntry->u32Offset, stEntry->u32Length);
4155 #if SUPPORT_G2VP9
4156 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4157 {
4158 if (stEntry->u32Offset == 0)
4159 return 0;
4160 else
4161 return stEntry->u32Offset + stEntry->u32Length - pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4162 }
4163 else
4164 #endif
4165 {
4166 return stEntry->u32Offset + stEntry->u32Length;
4167 }
4168 }
4169
HAL_VPU_EX_Push2VBBU(MS_U32 u32Id,HAL_VPU_EX_PacketInfo * stVpuPkt,MS_VIRT u32VBBUAddr)4170 MS_BOOL HAL_VPU_EX_Push2VBBU(MS_U32 u32Id, HAL_VPU_EX_PacketInfo *stVpuPkt, MS_VIRT u32VBBUAddr)
4171 {
4172 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4173 #if SUPPORT_G2VP9
4174 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4175 #endif
4176
4177 if (CHECK_NULL_PTR(pstVBBU) || CHECK_NULL_PTR(stVpuPkt))
4178 return FALSE;
4179 MsOS_ReadMemory();
4180 VDEC_VBBU_Entry *stEntry = (VDEC_VBBU_Entry*) &pstVBBU->stEntry[pstVBBU->u32WrPtr];
4181 MS_U32 u32NewWrPtr;
4182
4183 u32NewWrPtr = pstVBBU->u32WrPtr + 1;
4184 if (u32NewWrPtr == (MAX_VDEC_VBBU_ENTRY_COUNT + 1))
4185 {
4186 u32NewWrPtr = 0;
4187 }
4188
4189 if (u32NewWrPtr == pstVBBU->u32RdPtr) return FALSE;
4190
4191 stEntry->u32Offset = stVpuPkt->u32Offset;
4192
4193 #if SUPPORT_G2VP9
4194 if (E_VPU_EX_DECODER_G2VP9 == pVPUHalContext->_stVPUStream[u8OffsetIdx].eDecodertype)
4195 {
4196 stEntry->u32Offset += pVPUHalContext->u32BitstreamAddress[u8OffsetIdx];
4197 }
4198 #endif
4199
4200 stEntry->u32Length = stVpuPkt->u32Length;
4201 stEntry->u64TimeStamp = stVpuPkt->u64TimeStamp;
4202 stEntry->u32ID_H = stVpuPkt->u32ID_H;
4203 stEntry->u32ID_L = stVpuPkt->u32ID_L;
4204
4205 MsOS_FlushMemory();//make sure vbbu offset/length already flushed to memory before vbbu wptr advancing
4206
4207 pstVBBU->u32WrPtr = u32NewWrPtr;
4208
4209 //ALOGE("JJJ3: %d", pstVBBU->u32WrPtr);
4210
4211 MsOS_FlushMemory();
4212
4213 return TRUE;
4214 }
4215
HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)4216 MS_BOOL HAL_VPU_EX_IsVBBUEmpty(MS_VIRT u32VBBUAddr)
4217 {
4218 VDEC_VBBU *pstVBBU = (VDEC_VBBU *)MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + u32VBBUAddr);
4219
4220 if (CHECK_NULL_PTR(pstVBBU))
4221 return FALSE;
4222 return pstVBBU->u32RdPtr == pstVBBU->u32WrPtr;
4223 }
4224
4225 ///-----------------------------------------------------------------------------
4226 /// specify the command send to Mail box or DRAM
4227 /// @return TRUE or FALSE
4228 /// - TRUE, Mail box
4229 /// - FALSE, Dram
4230 /// @param u32Cmd \b IN: Command is going to be sned
4231 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)4232 MS_BOOL HAL_VPU_EX_IsMailBoxCMD(MS_U32 u32Cmd)
4233 {
4234 MS_BOOL bResult = TRUE;
4235
4236 switch (u32Cmd)
4237 {
4238 // *********** Runtime action Command
4239 /* case E_HVD_CMD_RELEASE_DISPQ:
4240 case E_HVD_CMD_UPDATE_DISPQ:
4241 case E_HVD_CMD_FLUSH_DEC_Q:
4242 case E_HVD_CMD_FLUSH:
4243 case E_HVD_CMD_PLAY:
4244 case E_HVD_CMD_PAUSE:
4245 case E_HVD_CMD_STOP:
4246 case E_HVD_CMD_STEP_DECODE:
4247 case E_HVD_CMD_SKIP_DEC:
4248 case E_HVD_CMD_DISP_I_DIRECT:*/
4249 // *********** Dual-Stream Create Task Command
4250 case E_DUAL_CMD_TASK0_HVD_BBU:
4251 case E_DUAL_CMD_TASK0_HVD_TSP:
4252 case E_DUAL_CMD_TASK0_MVD_SLQ:
4253 case E_DUAL_CMD_TASK0_MVD_TSP:
4254 case E_DUAL_CMD_TASK1_HVD_BBU:
4255 case E_DUAL_CMD_TASK1_HVD_TSP:
4256 case E_DUAL_CMD_MODE:
4257 #ifndef _WIN32
4258 case E_DUAL_CMD_TASK1_MVD_SLQ:
4259 case E_DUAL_CMD_TASK1_MVD_TSP:
4260 #endif
4261 case E_DUAL_CMD_DEL_TASK:
4262 case E_DUAL_CMD_SINGLE_TASK:
4263 case E_DUAL_VERSION:
4264 case E_DUAL_R2_CMD_EXIT:
4265 case E_DUAL_CMD_STC_MODE:
4266 #ifdef VDEC3
4267 case E_DUAL_R2_CMD_FBADDR:
4268 case E_DUAL_R2_CMD_FBSIZE:
4269 // *********** N-Streams
4270 case E_NST_CMD_TASK_HVD_TSP:
4271 case E_NST_CMD_TASK_HVD_BBU:
4272 case E_NST_CMD_TASK_MVD_TSP:
4273 case E_NST_CMD_TASK_MVD_SLQ:
4274 case E_NST_CMD_DEL_TASK:
4275 case E_NST_CMD_COMMON_MASK:
4276 case E_NST_CMD_COMMON_CMD1:
4277 #endif
4278 case E_DUAL_CMD_COMMON:
4279 {
4280 bResult = TRUE;
4281 }
4282 break;
4283 default:
4284 {
4285 bResult = FALSE;
4286 }
4287 break;
4288 }
4289
4290 return bResult;
4291 }
4292
4293 ///-----------------------------------------------------------------------------
4294 /// specify the command send to Mail box or DRAM
4295 /// @return TRUE or FALSE
4296 /// - TRUE, Mail box
4297 /// - FALSE, Dram
4298 /// @param u32Cmd \b IN: Command is going to be sned
4299 ///-----------------------------------------------------------------------------
HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)4300 MS_BOOL HAL_VPU_EX_IsDisplayQueueCMD(MS_U32 u32Cmd)
4301 {
4302 MS_BOOL bResult = TRUE;
4303
4304 switch (u32Cmd)
4305 {
4306 // *********** Runtime action Command
4307 case E_HVD_CMD_RELEASE_DISPQ:
4308 case E_HVD_CMD_UPDATE_DISPQ:
4309 case E_HVD_CMD_FLUSH_DEC_Q:
4310 case E_HVD_CMD_PAUSE:
4311 case E_HVD_CMD_FLUSH:
4312 case E_HVD_CMD_PLAY:
4313 case E_HVD_CMD_STOP:
4314 case E_HVD_CMD_SKIP_DEC:
4315 case E_HVD_CMD_DISP_I_DIRECT:
4316 case E_HVD_CMD_STEP_DECODE:
4317 case E_HVD_CMD_INC_DISPQ_NUM:
4318 case E_HVD_CMD_DYNAMIC_CONNECT_DISP_PATH:
4319 {
4320 bResult = TRUE;
4321 }
4322 break;
4323 default:
4324 {
4325 bResult = FALSE;
4326 }
4327 break;
4328 }
4329
4330 return bResult;
4331 }
4332
4333 ///-----------------------------------------------------------------------------
4334 /// Send message to HVD stream command queue
4335 /// @return TRUE or FALSE
4336 /// - TRUE, Success
4337 /// - FALSE, Failed
4338 /// @param u32DramAddr \b IN: address to be writen
4339 /// @param u32Msg \b IN: data to be writen
4340 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr,MS_U32 u32Msg)4341 MS_BOOL HAL_VPU_EX_DRAMCMDQueueSend(MS_VIRT u32DramAddr, MS_U32 u32Msg)
4342 {
4343 MS_BOOL bResult = TRUE;
4344
4345 VPU_MSG_DBG("Send to Command Queue Address=0x%lx, msg=0x%x\n", (unsigned long)u32DramAddr, u32Msg);
4346
4347 WRITE_LONG(u32DramAddr,u32Msg);
4348
4349 return bResult;
4350 }
4351
4352 ///-----------------------------------------------------------------------------
4353 /// Read task share memory to specify that task command queue is empty or not
4354 /// @return TRUE or FALSE
4355 /// - TRUE, Empty
4356 /// - FALSE, Non empty
4357 /// @param u32Id \b IN: Task information
4358 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsEmpty(void * cmd_queue)4359 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsEmpty(void *cmd_queue)
4360 {
4361 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4362 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4363 if (!cmd_q)
4364 {
4365 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4366 return FALSE;
4367 }
4368
4369 return cmd_q->u32HVD_STREAM_CMDQ_WD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4370 }
4371
4372 ///-----------------------------------------------------------------------------
4373 /// Read task share memory to specify that task command queue is full or not
4374 /// @return TRUE or FALSE
4375 /// - TRUE, Full
4376 /// - FALSE, Non full
4377 /// @param u32Id \b IN: Task information
4378 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMCMDQueueIsFull(void * cmd_queue)4379 MS_BOOL HAL_VPU_EX_DRAMCMDQueueIsFull(void *cmd_queue)
4380 {
4381 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4382 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4383 if (!cmd_q)
4384 {
4385 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4386 return TRUE;
4387 }
4388 MS_U32 NewWD = cmd_q->u32HVD_STREAM_CMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4389
4390 if(NewWD >= HVD_CMDQ_DRAM_ST_SIZE)
4391 NewWD -= HVD_CMDQ_DRAM_ST_SIZE;
4392
4393 return NewWD == cmd_q->u32HVD_STREAM_CMDQ_RD;
4394 }
4395
HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4396 MS_U32 HAL_VPU_EX_DRAMStreamCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4397 {
4398 MS_U32 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4399 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4400 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4401
4402 #if HVD_ENABLE_MVC
4403 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4404 {
4405 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4406 }
4407 #endif
4408
4409 if (CHECK_NULL_PTR(cmd_q))
4410 {
4411 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4412 return bResult;
4413 }
4414 MS_VIRT u32CmdQWdPtr;
4415
4416 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR))
4417 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4418
4419 if (HAL_VPU_EX_DRAMCMDQueueIsFull(cmd_q))
4420 return E_HVD_COMMAND_QUEUE_FULL;
4421 else
4422 {
4423 u32CmdQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_CMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_CMDQ_WD);
4424 }
4425
4426 switch (u8CmdType)
4427 {
4428 case E_HVD_CMDQ_CMD:
4429 {
4430 u32Msg |= (u8TaskID << 24);
4431 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr, u32Msg);
4432
4433 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4434
4435 if (bResult)
4436 {
4437 cmd_q->u32HVD_STREAM_CMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4438
4439 if (cmd_q->u32HVD_STREAM_CMDQ_WD == HVD_CMDQ_DRAM_ST_SIZE)
4440 cmd_q->u32HVD_STREAM_CMDQ_WD = 0;
4441
4442 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4443 }
4444 break;
4445 }
4446 case E_HVD_CMDQ_ARG:
4447 {
4448 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32CmdQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4449 if (bResult)
4450 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4451 break;
4452 }
4453 default:
4454 {
4455 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4456 break;
4457 }
4458 }
4459
4460 MsOS_FlushMemory();
4461
4462 return bResult;
4463 }
4464
4465 ///-----------------------------------------------------------------------------
4466 /// Read task share memory to specify that task display command queue is empty or not
4467 /// @return TRUE or FALSE
4468 /// - TRUE, Empty
4469 /// - FALSE, Non empty
4470 /// @param u32Id \b IN: Task information
4471 ///-----------------------------------------------------------------------------
HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void * cmd_queue)4472 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsEmpty(void *cmd_queue)
4473 {
4474 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4475 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4476 if (!cmd_q)
4477 {
4478 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4479 return FALSE;
4480 }
4481
4482 return cmd_q->u32HVD_STREAM_DISPCMDQ_WD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4483 }
4484
HAL_VPU_EX_DRAMDispCMDQueueIsFull(void * cmd_queue)4485 MS_BOOL HAL_VPU_EX_DRAMDispCMDQueueIsFull(void *cmd_queue)
4486 {
4487 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4488 CMD_QUEUE *cmd_q = (CMD_QUEUE *) cmd_queue;
4489 if (!cmd_q)
4490 {
4491 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4492 return TRUE;
4493 }
4494
4495 MS_U32 NewWD = cmd_q->u32HVD_STREAM_DISPCMDQ_WD + (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE); //preserve one slot
4496
4497 if(NewWD >= HVD_DISPCMDQ_DRAM_ST_SIZE)
4498 NewWD -= HVD_DISPCMDQ_DRAM_ST_SIZE;
4499
4500 return NewWD == cmd_q->u32HVD_STREAM_DISPCMDQ_RD;
4501 }
4502
HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id,void * cmd_queue,MS_U8 u8CmdType,MS_U32 u32Msg)4503 MS_U32 HAL_VPU_EX_DRAMStreamDispCMDQueueSend(MS_U32 u32Id, void *cmd_queue, MS_U8 u8CmdType, MS_U32 u32Msg)
4504 {
4505 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4506 CMD_QUEUE *cmd_q = (CMD_QUEUE *)cmd_queue;
4507 MS_U8 u8TaskID = HAL_VPU_EX_GetTaskId(u32Id);
4508
4509 #if HVD_ENABLE_MVC
4510 if (E_HAL_VPU_MVC_STREAM_BASE == u8TaskID)
4511 {
4512 u8TaskID = E_HAL_VPU_MAIN_STREAM_BASE;
4513 }
4514 #endif
4515
4516 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4517 //HVD_EX_MSG_DBG("DP shmAddr=%X u8TaskID = %X u8CmdType = %X u32Msg = %X\n", pShm, u8TaskID, u8CmdType, u32Msg);
4518
4519 if (CHECK_NULL_PTR(cmd_q))
4520 {
4521 VPU_MSG_ERR("Invalid parameter with share memory address=0x%lx %s:%d \n", (unsigned long)cmd_q, __FUNCTION__, __LINE__);
4522 return bResult;
4523 }
4524
4525 MS_VIRT u32DISPCMDQWdPtr;
4526
4527 if (CHECK_NULL_PTR((MS_VIRT)cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR))
4528 return E_HVD_COMMAND_QUEUE_NOT_INITIALED;
4529
4530 if (HAL_VPU_EX_DRAMDispCMDQueueIsFull(cmd_q))
4531 return E_HVD_COMMAND_QUEUE_FULL;
4532 else
4533 {
4534 u32DISPCMDQWdPtr = MsOS_PA2KSEG1(pVPUHalContext->u32FWCodeAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR + cmd_q->u32HVD_STREAM_DISPCMDQ_WD);
4535 }
4536
4537 // HVD_EX_MSG_DBG("VDispCmdQ_BASE_ADDR=%X PDispCmsQ_BASE_ADDR=%X u32DISPCMDQWdPtr=%X DISPCMDQ_TOTAL_SIZE = %X\n", cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, pVPUHalContext->u32FWCodeVAddr + cmd_q->u32HVD_DISPCMDQ_DRAM_ST_ADDR, u32DISPCMDQWdPtr,HVD_DISPCMDQ_DRAM_ST_SIZE);
4538
4539 switch (u8CmdType)
4540 {
4541 case E_HVD_CMDQ_CMD:
4542 {
4543 u32Msg |= (u8TaskID << 24);
4544 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr, u32Msg);
4545
4546 MsOS_FlushMemory();//make sure u32DISPCMDQWdPtr already flushed to memory
4547
4548 if (bResult)
4549 {
4550 cmd_q->u32HVD_STREAM_DISPCMDQ_WD += (HVD_DRAM_CMDQ_CMD_SIZE + HVD_DRAM_CMDQ_ARG_SIZE);
4551
4552 if (cmd_q->u32HVD_STREAM_DISPCMDQ_WD == HVD_DISPCMDQ_DRAM_ST_SIZE)
4553 cmd_q->u32HVD_STREAM_DISPCMDQ_WD = 0;
4554
4555 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4556 }
4557 break;
4558 }
4559 case E_HVD_CMDQ_ARG:
4560 {
4561 bResult = HAL_VPU_EX_DRAMCMDQueueSend(u32DISPCMDQWdPtr + HVD_DRAM_CMDQ_CMD_SIZE, u32Msg);
4562 if (bResult)
4563 bResult = E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL;
4564 break;
4565 }
4566 default:
4567 {
4568 bResult = E_HVD_COMMAND_QUEUE_SEND_FAIL;
4569 break;
4570 }
4571 }
4572
4573 MsOS_FlushMemory();
4574
4575 return bResult;
4576 }
4577
HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id,MS_VIRT u32BsAddr)4578 MS_BOOL HAL_VPU_EX_SetBitstreamBufAddress(MS_U32 u32Id, MS_VIRT u32BsAddr)
4579 {
4580 MS_U8 u8OffsetIdx = _VPU_EX_GetOffsetIdx(u32Id);
4581 MS_U32 u32StAddr;
4582 MS_U8 u8TmpMiuSel;
4583
4584 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32BsAddr);
4585
4586 pVPUHalContext->u32BitstreamAddress[u8OffsetIdx] = u32StAddr;
4587
4588 return TRUE;
4589 }
4590 #endif
4591
HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)4592 void HAL_VPU_EX_DynamicFBMode(MS_BOOL bEnable,MS_PHY u32address,MS_U32 u32Size)
4593 {
4594 pVPUHalContext->bEnableDymanicFBMode = bEnable;
4595
4596 if(u32address >= HAL_MIU1_BASE)
4597 {
4598 pVPUHalContext->u32DynamicFBAddress = u32address-HAL_MIU1_BASE;
4599 }
4600 else
4601 {
4602 pVPUHalContext->u32DynamicFBAddress = u32address;
4603 }
4604
4605 pVPUHalContext->u32DynamicFBSize = u32Size;
4606 }
4607 #ifdef CONFIG_MSTAR_CLKM
HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType,MS_BOOL bEnable)4608 void HAL_VPU_EX_SetClkManagement(VPU_EX_ClkPortType eClkPortType, MS_BOOL bEnable)
4609 {
4610 MS_S32 handle;
4611 switch(eClkPortType)
4612 {
4613 case E_VPU_EX_CLKPORT_MVD:
4614 {
4615 handle = Drv_Clkm_Get_Handle("g_clk_mvd");
4616 if(bEnable)
4617 {
4618 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4619 }
4620 else
4621 {
4622 Drv_Clkm_Clk_Gate_Disable(handle);
4623 }
4624 break;
4625 }
4626 case E_VPU_EX_CLKPORT_MVD_CORE:
4627 {
4628 handle = Drv_Clkm_Get_Handle("g_clk_mvd_core");
4629 if(bEnable)
4630 {
4631 Drv_Clkm_Set_Clk_Source(handle, "");
4632 }
4633 else
4634 {
4635 Drv_Clkm_Clk_Gate_Disable(handle);
4636 }
4637 break;
4638 }
4639 case E_VPU_EX_CLKPORT_MVD_PAS:
4640 {
4641 handle = Drv_Clkm_Get_Handle("g_clk_mvd_pas");
4642 if(bEnable)
4643 {
4644 Drv_Clkm_Set_Clk_Source(handle, "");
4645 }
4646 else
4647 {
4648 Drv_Clkm_Clk_Gate_Disable(handle);
4649 }
4650 break;
4651 }
4652 case E_VPU_EX_CLKPORT_HVD:
4653 {
4654 handle = Drv_Clkm_Get_Handle("g_clk_hvd");
4655 if(bEnable)
4656 {
4657 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4658 }
4659 else
4660 {
4661 Drv_Clkm_Clk_Gate_Disable(handle);
4662 }
4663 break;
4664 }
4665 case E_VPU_EX_CLKPORT_HVD_IDB:
4666 {
4667 handle = Drv_Clkm_Get_Handle("g_clk_hvd_idb");
4668 if(bEnable)
4669 {
4670 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4671 }
4672 else
4673 {
4674 Drv_Clkm_Clk_Gate_Disable(handle);
4675 }
4676 break;
4677 }
4678 case E_VPU_EX_CLKPORT_HVD_AEC:
4679 {
4680 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec");
4681 if(bEnable)
4682 {
4683 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4684 }
4685 else
4686 {
4687 Drv_Clkm_Clk_Gate_Disable(handle);
4688 }
4689 break;
4690 }
4691 case E_VPU_EX_CLKPORT_HVD_AEC_LITE:
4692 {
4693 handle = Drv_Clkm_Get_Handle("g_clk_hvd_aec_lite");
4694 if(bEnable)
4695 {
4696 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4697 }
4698 else
4699 {
4700 Drv_Clkm_Clk_Gate_Disable(handle);
4701 }
4702 break;
4703 }
4704 case E_VPU_EX_CLKPORT_VP8:
4705 {
4706 handle = Drv_Clkm_Get_Handle("g_clk_vp8");
4707 if(bEnable)
4708 {
4709 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4710 }
4711 else
4712 {
4713 Drv_Clkm_Clk_Gate_Disable(handle);
4714 }
4715 break;
4716 }
4717 case E_VPU_EX_CLKPORT_EVD:
4718 {
4719 handle = Drv_Clkm_Get_Handle("g_clk_evd");
4720 if(bEnable)
4721 {
4722 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4723 }
4724 else
4725 {
4726 Drv_Clkm_Clk_Gate_Disable(handle);
4727 }
4728 break;
4729 }
4730 case E_VPU_EX_CLKPORT_EVD_PPU:
4731 {
4732 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu");
4733 if(bEnable)
4734 {
4735 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4736 }
4737 else
4738 {
4739 Drv_Clkm_Clk_Gate_Disable(handle);
4740 }
4741 break;
4742 }
4743 case E_VPU_EX_CLKPORT_EVD_LITE:
4744 {
4745 handle = Drv_Clkm_Get_Handle("g_clk_evd_lite");
4746 if(bEnable)
4747 {
4748 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4749 }
4750 else
4751 {
4752 Drv_Clkm_Clk_Gate_Disable(handle);
4753 }
4754 break;
4755 }
4756 case E_VPU_EX_CLKPORT_EVD_PPU_LITE:
4757 {
4758 handle = Drv_Clkm_Get_Handle("g_clk_evd_ppu_lite");
4759 if(bEnable)
4760 {
4761 Drv_Clkm_Set_Clk_Source(handle, "FAST_MODE");
4762 }
4763 else
4764 {
4765 Drv_Clkm_Clk_Gate_Disable(handle);
4766 }
4767 break;
4768 }
4769 case E_VPU_EX_CLKPORT_VD_MHEG5:
4770 {
4771 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5");
4772 if(bEnable)
4773 {
4774 Drv_Clkm_Set_Clk_Source(handle, "");
4775 }
4776 else
4777 {
4778 Drv_Clkm_Clk_Gate_Disable(handle);
4779 }
4780 break;
4781 }
4782 case E_VPU_EX_CLKPORT_VD_MHEG5_LITE:
4783 {
4784 handle = Drv_Clkm_Get_Handle("g_clk_vd_mheg5_lite");
4785 if(bEnable)
4786 {
4787 Drv_Clkm_Set_Clk_Source(handle, "");
4788 }
4789 else
4790 {
4791 Drv_Clkm_Clk_Gate_Disable(handle);
4792 }
4793 break;
4794 }
4795 }
4796 }
4797 #endif //#ifdef CONFIG_MSTAR_CLKM
_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4798 MS_SIZE _VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4799 {
4800 MS_SIZE FrameBufferSize = 0;
4801
4802 switch(eCodecType)
4803 {
4804 case E_VPU_EX_CODEC_TYPE_MPEG2:
4805 case E_VPU_EX_CODEC_TYPE_H263:
4806 case E_VPU_EX_CODEC_TYPE_MPEG4:
4807 case E_VPU_EX_CODEC_TYPE_DIVX311:
4808 case E_VPU_EX_CODEC_TYPE_DIVX412:
4809 case E_VPU_EX_CODEC_TYPE_FLV:
4810 FrameBufferSize = 0x1E00000;
4811 break;
4812 case E_VPU_EX_CODEC_TYPE_VC1_ADV:
4813 case E_VPU_EX_CODEC_TYPE_VC1_MAIN:
4814 FrameBufferSize = 0x6C00000;
4815 break;
4816 case E_VPU_EX_CODEC_TYPE_RV8:
4817 case E_VPU_EX_CODEC_TYPE_RV9:
4818 FrameBufferSize = 0x1B00000;
4819 break;
4820 case E_VPU_EX_CODEC_TYPE_VP8:
4821 FrameBufferSize = 0x1500000;
4822 break;
4823 case E_VPU_EX_CODEC_TYPE_H264:
4824 FrameBufferSize = 0x8200000;
4825 //FrameBufferSize = 0x7A00000; //UHD 122MB ,5 ref frame
4826 //FrameBufferSize = 0x7A80000; //UHD 4K2K 16:19 126.5MB
4827 //FrameBufferSize = 0x8E00000; //UHD 4K2K 16:19 142MB
4828 break;
4829 case E_VPU_EX_CODEC_TYPE_AVS:
4830 FrameBufferSize = 0x1B00000;
4831 break;
4832 case E_VPU_EX_CODEC_TYPE_MJPEG:
4833 FrameBufferSize = 0x2800000;
4834 break;
4835 case E_VPU_EX_CODEC_TYPE_MVC:
4836 FrameBufferSize = 0x4200000;
4837 break;
4838 case E_VPU_EX_CODEC_TYPE_HEVC_DV:
4839 FrameBufferSize = 0xB000000;
4840 break;
4841 case E_VPU_EX_CODEC_TYPE_HEVC:
4842 #if SUPPORT_MSVP9
4843 case E_VPU_EX_CODEC_TYPE_VP9:
4844 #endif
4845 FrameBufferSize = 0xA000000;
4846 break;
4847 #if !SUPPORT_MSVP9
4848 case E_VPU_EX_CODEC_TYPE_VP9:
4849 FrameBufferSize = 0x7800000;
4850 break;
4851 #endif
4852 default:
4853 FrameBufferSize = 0;
4854 break;
4855 }
4856
4857 return FrameBufferSize;
4858 }
4859
HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)4860 MS_SIZE HAL_VPU_EX_GetFrameBufferDefaultSize(VPU_EX_CodecType eCodecType)
4861 {
4862 return _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4863 }
4864
4865 // To-do: Taking the source type into consideration
HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType,VPU_EX_SrcMode eSrcMode,MS_U64 * offset,MS_SIZE * length,MS_U64 total_length,MS_SIZE unUseSize)4866 MS_BOOL HAL_VPU_EX_GetCMAMemSize(VPU_EX_CodecType eCodecType, VPU_EX_SrcMode eSrcMode,
4867 MS_U64 *offset, MS_SIZE *length, MS_U64 total_length, MS_SIZE unUseSize)
4868 {
4869 MS_SIZE FrameBufferSize = 0;
4870
4871 if (!offset || !length)
4872 return FALSE;
4873
4874 total_length -= unUseSize;
4875 VPRINTF("[HAL][%s]:[%d] total_length:%llu, cType:%d, sType:%d\n", __FUNCTION__, __LINE__,
4876 (unsigned long long)total_length, (int)eCodecType, (int)eSrcMode);
4877
4878 FrameBufferSize = _VPU_EX_GetFrameBufferDefaultSize(eCodecType);
4879
4880 if(FrameBufferSize == 0)
4881 {
4882 return FALSE;
4883 }
4884 VPRINTF("[HAL][%s]:[%d] FrameSize:%llu, offset:%llu, length:%llu ", __FUNCTION__, __LINE__,
4885 (unsigned long long)FrameBufferSize, (unsigned long long)*offset, (unsigned long long)*length);
4886 if (total_length < FrameBufferSize)
4887 {
4888 *offset = unUseSize;
4889 *length = total_length;
4890 }
4891 else // todo, dual decode case
4892 {
4893 *offset = unUseSize;
4894 *length = FrameBufferSize;
4895 }
4896 return TRUE;
4897 }
4898
HAL_VPU_EX_strcmp(const char * string1,const char * string2)4899 static int HAL_VPU_EX_strcmp(const char *string1, const char *string2)
4900 {
4901 int iRet, i;
4902
4903 i = 0;
4904 while(string1[i] || string2[i])
4905 {
4906 iRet = string1[i] - string2[i];
4907 if(iRet)
4908 {
4909 return iRet;
4910 }
4911 i++;
4912 }
4913 return 0;
4914 }
4915
HAL_VPU_EX_GetCapability(MS_U8 * pu8CmdNameIn,void * pParamIn,void * pParamOut)4916 MS_BOOL HAL_VPU_EX_GetCapability(MS_U8 *pu8CmdNameIn, void *pParamIn, void *pParamOut)
4917 {
4918 typedef enum
4919 {
4920 E_CAP_NDEC_FB_MIU_SELECT,
4921 E_CAP_NDEC_NSTREAM_FB_SIZE,
4922 E_CAP_NDEC_NSTREAM_BS_SIZE,
4923 E_CAP_NDEC_SUPPORT_SHAREBBU,
4924 E_CAP_SUPPORT_ALLOCATOR,
4925
4926 } VPU_EX_GetCapabilityCmdId;
4927
4928 typedef struct
4929 {
4930 MS_U8 u8CmdId;
4931 MS_U8 u8CmdName[32];
4932
4933 } VPU_EX_GetCapabilityCmd;
4934
4935 static VPU_EX_GetCapabilityCmd stCapCmd[] =
4936 {
4937 {E_CAP_NDEC_FB_MIU_SELECT, "CAP_NDEC_FB_MIU_SELECT"},
4938 {E_CAP_NDEC_NSTREAM_FB_SIZE, "CAP_NDEC_NSTREAM_FB_SIZE"},
4939 {E_CAP_NDEC_NSTREAM_BS_SIZE, "CAP_NDEC_NSTREAM_BS_SIZE"},
4940 {E_CAP_NDEC_SUPPORT_SHAREBBU, "CAP_NDEC_SUPPORT_SHAREBBU"},
4941 {E_CAP_SUPPORT_ALLOCATOR, "CAP_SUPPORT_ALLOCATOR"},
4942 };
4943
4944 MS_U32 bRet = FALSE;
4945 MS_U32 u32TotalCmdCnt = sizeof(stCapCmd) / sizeof(stCapCmd[0]);
4946 MS_U32 u32CmdCnt;
4947
4948 for(u32CmdCnt = 0; u32CmdCnt < u32TotalCmdCnt; u32CmdCnt++)
4949 {
4950 if(HAL_VPU_EX_strcmp((const char *)(stCapCmd[u32CmdCnt].u8CmdName), (const char *)pu8CmdNameIn) == 0)
4951 {
4952 bRet = TRUE;
4953 switch(stCapCmd[u32CmdCnt].u8CmdId)
4954 {
4955 case E_CAP_NDEC_FB_MIU_SELECT:
4956 {
4957 VPU_EX_CodecType eCodecType = *((VPU_EX_CodecType *)pParamIn);
4958 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
4959 if((eCodecType == E_VPU_EX_CODEC_TYPE_HEVC) ||
4960 (eCodecType == E_VPU_EX_CODEC_TYPE_VP9) ||
4961 (eCodecType == E_VPU_EX_CODEC_TYPE_HEVC_DV))
4962 {
4963 *pSupport = TRUE;
4964 }
4965 else
4966 {
4967 *pSupport = FALSE;
4968 }
4969 }
4970 break;
4971
4972 // FIXME: Patch for waiting dynamic frame buffer and preset task_spec
4973 case E_CAP_NDEC_NSTREAM_FB_SIZE:
4974 {
4975 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
4976 *pSize = 0x1300000; // 19M
4977 }
4978 break;
4979
4980 // FIXME: Patch for waiting dynamic bitstream buffer
4981 case E_CAP_NDEC_NSTREAM_BS_SIZE:
4982 {
4983 MS_SIZE *pSize = (MS_SIZE *)pParamOut;
4984 *pSize = 0x400000; // 4M
4985 }
4986 break;
4987
4988 case E_CAP_NDEC_SUPPORT_SHAREBBU:
4989 {
4990 MS_BOOL *pbSupportShareBBU = (MS_BOOL *)pParamOut;
4991 *pbSupportShareBBU = TRUE;
4992 }
4993 break;
4994
4995 case E_CAP_SUPPORT_ALLOCATOR:
4996 {
4997 MS_BOOL *pSupport = (MS_BOOL *)pParamOut;
4998 *pSupport = TRUE;
4999 }
5000 break;
5001
5002 default:
5003 bRet = FALSE;
5004 break;
5005 }
5006 }
5007 }
5008
5009 return bRet;
5010 }
5011
5012 #else
5013 #include "halVPU_EX.h"
5014 #include "drvMMIO.h"
5015 #include "../../../../vdec_v2/hal/maserati/hvd_ex/regHVD_EX.h"
5016 #include "halCHIP.h"
5017
5018 #if defined(MSOS_TYPE_NUTTX)
5019 extern int lib_lowprintf(const char *fmt, ...);
5020 #define PRINTF lib_lowprintf
5021 #elif defined(MSOS_TYPE_OPTEE)
5022 #define PRINTF printf
5023 #endif
5024
5025 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
5026 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
5027
5028 MS_U8 u8FW_Binary[] = {
5029 #include "fwVPU.dat"
5030 };
5031
5032 MS_U32 u32HVDRegOSBase;
5033
HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)5034 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_VIRT addr)
5035 {
5036 //PRINTF("do load code,u32DestAddr %x\n",addr);
5037 memcpy((void*)addr, (void*)u8FW_Binary, sizeof(u8FW_Binary));
5038 MAsm_CPU_Sync();
5039 MsOS_FlushMemory();
5040
5041 if (FALSE == (*((MS_U8*)(addr+6))=='R' && *((MS_U8*)(addr+7))=='2'))
5042 {
5043 PRINTF("FW is not R2 version! _%x_ _%x_\n", *(MS_U8*)(addr+6), *(MS_U8*)(addr+7));
5044 return FALSE;
5045 }
5046 return TRUE;
5047 }
5048
HAL_VPU_EX_SetLockDownRegister(void * param)5049 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param)
5050 {
5051 #if 1
5052 MS_PHY u32StAddr_main;
5053 MS_PHY u32StAddr_sub;
5054 MS_U32 u32NonPMBankSize = 0;
5055 VPU_EX_LOCK_DOWN_REGISTER* register_lockdown;
5056
5057 if(param == NULL)
5058 {
5059 return FALSE;
5060 }
5061
5062 register_lockdown = (VPU_EX_LOCK_DOWN_REGISTER*)param;
5063
5064 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
5065
5066 // ES buffer
5067 u32StAddr_main = register_lockdown->Bitstream_Addr_Main;
5068 u32StAddr_sub = register_lockdown->Bitstream_Addr_Sub;
5069
5070
5071 MS_PHY u32StartOffset;
5072 MS_U8 u8MiuSel;
5073
5074 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_main);
5075 u32StAddr_main = u32StartOffset;
5076
5077 _phy_to_miu_offset(u8MiuSel, u32StartOffset, u32StAddr_sub);
5078 u32StAddr_sub = u32StartOffset;
5079
5080 //Lock down register
5081 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(REG_HVD_BASE), HVD_LWORD(u32StAddr_main >> 3));
5082 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(REG_HVD_BASE), HVD_HWORD(u32StAddr_main >> 3));
5083
5084 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2, HVD_LWORD(u32StAddr_sub >> 3));
5085 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2, HVD_HWORD(u32StAddr_sub >> 3));
5086 //~
5087
5088 // Lock Down
5089 //_HVD_Write2Byte(HVD_REG_HI_DUMMY_0, (_HVD_Read2Byte(HVD_REG_HI_DUMMY_0) | (HVD_REG_LOCK_REG_ESB_ST_ADR_L_H|HVD_REG_LOCK_REG_ESB_ST_ADR_L_H_BS2)));
5090 //~
5091 #endif
5092 return TRUE;
5093 }
5094
5095 #endif
5096