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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvHVD.h 98 /// @brief HVD Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_HVD_DEF_H_ 103 #define _DRV_HVD_DEF_H_ 104 105 #include "drvHVD_Common.h" 106 107 //------------------------------------------------------------------------------------------------- 108 // Driver Capability 109 //------------------------------------------------------------------------------------------------- 110 111 // HW capability 112 #define HVD_HW_SVD 1 113 #define HVD_HW_HVD 2 114 #if defined(CHIP_T2) 115 #define HVD_HW_VERSION HVD_HW_SVD 116 #else 117 #define HVD_HW_VERSION HVD_HW_HVD 118 #endif 119 120 //------------------------------------------------------------------------------------------------- 121 // Macro and Define 122 //------------------------------------------------------------------------------------------------- 123 // Feature switch 124 #if defined(REDLION_LINUX_KERNEL_ENVI) 125 #define HVD_ENABLE_MUTEX_PROTECT 0 126 #define HVD_ENABLE_MIU_RST_PROTECT 1 127 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 128 #define HVD_ENABLE_MSOS_SYSTEM_CALL 0 129 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 130 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 131 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 0 132 #define HVD_ENABLE_MSOS_MIU1_BASE 0 133 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 134 #define HVD_ENABLE_EMBEDDED_FW_BINARY 1 135 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 136 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 137 #define HVD_ENABLE_TIME_MEASURE 0 138 #define HVD_ENABLE_REINIT_FAILED 1 139 #define HVD_ENABLE_RV_FEATURE 0 140 #else 141 #define HVD_ENABLE_MUTEX_PROTECT 1 142 #define HVD_ENABLE_MIU_RST_PROTECT 1 143 #if 1//defined( MSOS_TYPE_LINUX) 144 #define HVD_ENABLE_AUTO_SET_REG_BASE 1 145 #else 146 #define HVD_ENABLE_AUTO_SET_REG_BASE 0 147 #endif 148 #if defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) //|| defined( MSOS_TYPE_NOS) 149 #define HVD_ENABLE_PATCH_ISFRAMERDY 0 150 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 151 #else 152 #define HVD_ENABLE_PATCH_ISFRAMERDY 1 153 #define HVD_ENABLE_MSOS_SYSTEM_CALL 1 154 #endif 155 #if defined(MSOS_TYPE_NOS) && (defined(CHIP_T3) || defined(CHIP_T8) || defined(CHIP_J2)) 156 #define HVD_ENABLE_STOP_ACCESS_OVER_256 1 157 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 1 158 #else 159 #define HVD_ENABLE_STOP_ACCESS_OVER_256 0 160 #define HVD_ENABLE_BDMA_2_BITSTREAMBUF 0 161 #endif 162 163 #define HVD_ENABLE_AUTO_AVI_NULL_PACKET 1 164 165 #if defined(CHIP_JANUS) 166 #define HVD_ENABLE_MSOS_MIU1_BASE 0 167 #else 168 #define HVD_ENABLE_MSOS_MIU1_BASE 1 169 #endif 170 171 #define HVD_ENABLE_CHECK_STATE_BEFORE_SET_CMD 0 172 #define HVD_ENABLE_WAIT_CMD_FINISHED 0 173 #define HVD_ENABLE_TIME_MEASURE 0 174 #define HVD_ENABLE_REINIT_FAILED 0 175 176 #if defined(CHIP_T2) || defined(CHIP_U3) || defined(CHIP_T3) || defined(CHIP_T4) || defined(CHIP_T7) 177 #define HVD_ENABLE_RV_FEATURE 0 178 #else 179 #define HVD_ENABLE_RV_FEATURE 0 180 #endif 181 182 #if defined(CHIP_T12) || \ 183 defined(CHIP_J2) || \ 184 defined(CHIP_A1) || \ 185 defined(CHIP_A2) || \ 186 defined(CHIP_A5) || \ 187 defined(CHIP_A5P) || \ 188 defined(CHIP_A7) || \ 189 defined(CHIP_A3) || \ 190 defined(CHIP_AMETHYST)|| \ 191 defined(CHIP_AGATE) || \ 192 defined(CHIP_EDISON) || \ 193 defined(CHIP_EMERALD)|| \ 194 defined(CHIP_EAGLE) || \ 195 defined(CHIP_EIFFEL) || \ 196 defined(CHIP_NIKE) || \ 197 defined(CHIP_MADISON) || \ 198 defined(CHIP_CLIPPERS) || \ 199 defined(CHIP_MIAMI) || \ 200 defined(CHIP_NUGGET) || \ 201 defined(CHIP_KAISER) || \ 202 defined(CHIP_NIKON) || \ 203 defined(CHIP_EINSTEIN)|| \ 204 defined(CHIP_NAPOLI) || \ 205 defined(CHIP_KERES) || \ 206 defined(CHIP_MONACO) || \ 207 defined(CHIP_MUJI) || \ 208 defined(CHIP_MUNICH) || \ 209 defined(CHIP_MONET) || \ 210 defined(CHIP_MANHATTAN) || \ 211 defined(CHIP_MASERATI) || \ 212 defined(CHIP_MESSI) || \ 213 defined(CHIP_MAXIM) || \ 214 defined(CHIP_K6) || \ 215 defined(CHIP_K6LITE) 216 #define HVD_ENABLE_MVC 1 217 #else 218 #define HVD_ENABLE_MVC 0 219 #endif 220 221 #endif 222 223 #define HVD_CMA_SUPPORT_MAX_MIU_NUM 2 224 #define HVD_CMA_SUPPORTMAX_BLOCK_NUM 2 225 226 #if defined(REDLION_LINUX_KERNEL_ENVI) 227 #include "drvHVD_redlion.h" 228 #endif 229 230 #if (HVD_ENABLE_MUTEX_PROTECT) || ( HVD_ENABLE_MSOS_SYSTEM_CALL ) 231 #include "osalHVD_EX.h" 232 #endif 233 234 #if HVD_ENABLE_MSOS_MIU1_BASE 235 #include "halCHIP.h" 236 #endif 237 238 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF 239 #include "drvBDMA.h" 240 #define HVD_dmacpy( DESTADDR, SRCADDR , LEN) MDrv_BDMA_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), E_BDMA_SDRAM2SDRAM1, BDMA_OPCFG_DEF) 241 #define HVD_BDMAcpy(DESTADDR, SRCADDR, LEN , Flag) MDrv_BDMA_CopyHnd((MS_PHY)(SRCADDR), (MS_PHY)(DESTADDR), (LEN), (Flag), BDMA_OPCFG_DEF) 242 #endif 243 244 245 #if defined(MSOS_TYPE_ECOS) 246 #define HVD_PRINT diag_printf 247 #define HVD_PRINTI diag_printf 248 #define HVD_PRINTD diag_printf 249 #define HVD_ERR diag_printf 250 #else 251 #include "ULog.h" 252 #define HVD_PRINT(format,args...) ULOGD("VDEC", format, ##args) 253 #define HVD_PRINTI(format,args...) ULOGI("VDEC", format, ##args) 254 #define HVD_PRINTD(format,args...) ULOGD("VDEC", format, ##args) 255 #define HVD_ERR(format,args...) ULOGE("VDEC", format, ##args) 256 #endif 257 258 259 #define HVD_EX_MSG_MUST(format, args...) \ 260 do \ 261 { \ 262 if (u32UartCtrl & E_HVD_UART_CTRL_MUST) \ 263 { \ 264 HVD_ERR("[HVD][MUST]%s:", __FUNCTION__); \ 265 HVD_ERR(format, ##args); \ 266 } \ 267 } while (0) 268 269 #define HVD_EX_MSG_ERR(format, args...) \ 270 do \ 271 { \ 272 if (u32UartCtrl & E_HVD_UART_CTRL_ERR) \ 273 { \ 274 HVD_ERR("[HVD][ERR]%s:", __FUNCTION__); \ 275 HVD_ERR(format, ##args); \ 276 } \ 277 } while (0) 278 279 #if ((defined(CHIP_A1) || defined(CHIP_A7) || defined(CHIP_AMETHYST) || defined(CHIP_EMERALD) || defined(CHIP_NUGGET) || defined(CHIP_NIKON)) && defined (__aeon__)) 280 #define HVD_EX_MSG_INF(format, args...) 281 #define HVD_EX_MSG_DBG(format, args...) 282 #define HVD_EX_MSG_TRACE() 283 #else 284 #define HVD_EX_MSG_INF(format, args...) \ 285 do \ 286 { \ 287 if (u32UartCtrl & E_HVD_UART_CTRL_INFO) \ 288 { \ 289 HVD_PRINTI("[HVD][INF]%s:", __FUNCTION__); \ 290 HVD_PRINTI(format, ##args); \ 291 } \ 292 } while (0) 293 294 #define HVD_EX_MSG_DBG(format, args...) \ 295 do \ 296 { \ 297 if (u32UartCtrl & E_HVD_UART_CTRL_DBG) \ 298 { \ 299 HVD_PRINTD("[HVD][DBG]%s:", __FUNCTION__); \ 300 HVD_PRINTD(format, ##args); \ 301 } \ 302 } while (0) 303 304 #define HVD_EX_MSG_TRACE() \ 305 do \ 306 { \ 307 if (u32UartCtrl & E_HVD_UART_CTRL_TRACE) \ 308 { \ 309 HVD_PRINTD("[HVD][TRA]%s:", __FUNCTION__); \ 310 } \ 311 } while (0) 312 #endif 313 314 // Configs 315 #define HVD_FW_IDLE_THRESHOLD 5000 // VPU ticks 316 #define HVD_BBU_ST_ADDR_IN_BITSTREAMBUF 0x400 317 318 #define HVD_DRV_CMD_WAIT_FINISH_TIMEOUT 100 319 #define HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT 1000 320 321 // Util or Functions 322 #define HVD_MAX3(x,y,z) (((x)>(y) ? (x):(y)) > (z) ? ((x)>(y) ? (x):(y)):(z)) 323 #define HVD_LWORD(x) (MS_U16)((x)&0xffff) 324 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff) 325 #define HVD_U32_MAX 0xffffffffUL 326 #define HVD_RV_BROKENBYUS_MASK 0x00800000 327 328 #ifdef MSOS_TYPE_LINUX 329 #if HVD_ENABLE_MSOS_SYSTEM_CALL 330 #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 331 #else 332 #define HVD_VA2PA(x ) (x)//(MS_U32)(MS_VA2PA( (void*)(x))) // fixme 333 #endif 334 #else 335 #define HVD_VA2PA(x) (x) 336 #endif 337 338 #if defined(REDLION_LINUX_KERNEL_ENVI) 339 #define HVD_PA2VA(x ) (MS_VIRT)MDrv_SYS_PA2NonCacheSeg((void*)(x)) 340 #else 341 #define HVD_PA2VA(x ) (MS_VIRT)MS_PA2KSEG1((MS_PHY)(x)) 342 #endif 343 344 #if 0//def memcpy 345 #define HVD_memcpy(x , y , z) memcpy(x, y, z) 346 #else 347 348 #if 0 349 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 350 do { \ 351 MS_U32 i = 0; \ 352 volatile MS_U8 *Dest = (volatile MS_U8 *)(pDstAddr ); \ 353 volatile MS_U8 *Src = ( volatile MS_U8 *)(pSrcAddr) ; \ 354 for (i = 0; i < (u32Size); i++) \ 355 { \ 356 Dest[i] = Src[i]; \ 357 } \ 358 }while(0) 359 #else 360 #define HVD_memcpy( pDstAddr, pSrcAddr, u32Size) \ 361 do { \ 362 register unsigned long u32I=0; \ 363 register unsigned long u32Dst = (unsigned long)pDstAddr; \ 364 void * pSrc = (void *)pSrcAddr; \ 365 MS_U32 _u32memsize = u32Size; \ 366 if( (u32Dst % 4) || ((unsigned long)pSrc % 4) ) \ 367 { \ 368 for( u32I=0; u32I< (unsigned long)(_u32memsize); u32I++) \ 369 { \ 370 ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 371 } \ 372 } \ 373 else \ 374 { \ 375 for( u32I=0; u32I < ((unsigned long)(u32Size)/4); u32I++) \ 376 { \ 377 ((volatile unsigned int *)u32Dst)[u32I] = ((volatile unsigned int *)pSrc)[u32I]; \ 378 } \ 379 if((_u32memsize)%4) \ 380 { \ 381 u32Dst += u32I*4; \ 382 pSrc = (void *)((unsigned long)pSrc + u32I*4); \ 383 for( u32I=0; u32I<((unsigned long)(_u32memsize)%4); u32I++) \ 384 { \ 385 ((volatile unsigned char *)u32Dst)[u32I] = ((volatile unsigned char *)pSrc)[u32I]; \ 386 } \ 387 } \ 388 } \ 389 }while(0) 390 #endif 391 392 #endif 393 394 395 396 #if HVD_ENABLE_MSOS_SYSTEM_CALL 397 #define HVD_Delay_ms(x) MsOS_DelayTaskUs(1000*x) 398 #define HVD_SYSTEM_DELAY_MS_TYPE 2 399 #elif defined(REDLION_LINUX_KERNEL_ENVI) 400 #define HVD_Delay_ms(x) msleep(x) 401 //#define HVD_Delay_ms(x) MHal_H264_Delay_ms(x) 402 #define HVD_SYSTEM_DELAY_MS_TYPE 3 403 #else 404 #define HVD_Delay_ms(x) \ 405 do { \ 406 volatile MS_U32 ticks=0; \ 407 while( ticks < ( ((MS_U32)(x)) <<13) ) \ 408 { \ 409 ticks++; \ 410 } \ 411 } while(0) 412 #define HVD_SYSTEM_DELAY_MS_TYPE 0 413 #endif // HVD_ENABLE_MSOS_SYSTEM_CALL 414 415 416 #define HVD_DumpMemory( addr, size , ascii , NonCacheMask) \ 417 do{ \ 418 MS_U32 i = 0; \ 419 MS_U32 j = 0; \ 420 MS_U8* temp = (MS_U8*)addr; \ 421 MS_U8 string[17] ; \ 422 HVD_EX_MSG_DBG("HVD Dump Memory addr: 0x%x ; size: 0x%x \r\n", addr, size); \ 423 temp = (MS_U8*)(((MS_U32)temp) | NonCacheMask); \ 424 memset(string , 0 , sizeof(string)); \ 425 for (j = 0; j < (size >> 4); j++) \ 426 { \ 427 if (ascii) \ 428 { \ 429 for (i = 0; i < 16; i++) \ 430 { \ 431 if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 432 string[i] = *(temp + i); \ 433 else \ 434 string[i] = '.'; \ 435 } \ 436 HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %s\n" \ 437 , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15) , string); \ 438 } \ 439 else \ 440 { \ 441 HVD_EX_MSG_DBG("0x%08x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n" \ 442 , j << 4 , *temp, *(temp + 1), *(temp + 2), *(temp + 3), *(temp + 4), *(temp + 5), *(temp + 6), *(temp + 7), *(temp + 8), *(temp + 9), *(temp + 10), *(temp + 11), *(temp + 12), *(temp + 13), *(temp + 14), *(temp + 15)); \ 443 } \ 444 temp += 16; \ 445 } \ 446 HVD_EX_MSG_DBG("0x%08x " , j << 4); \ 447 memset(string , 0 , sizeof(string)); \ 448 for (i = 0; i < (size & 0x0f); i++) \ 449 { \ 450 if (*(temp + i) >= 30 && *(temp + i) <= 126) \ 451 string[i] = *(temp + i); \ 452 else \ 453 string[i] = '.'; \ 454 HVD_EX_MSG_DBG("%02x ", *(MS_U8*)(temp + i)); \ 455 } \ 456 if (ascii) \ 457 { \ 458 for (; i < 16 ; i++) \ 459 HVD_EX_MSG_DBG(" "); \ 460 HVD_EX_MSG_DBG(" %s\n" , string); \ 461 } \ 462 else \ 463 HVD_EX_MSG_DBG("\n"); \ 464 }while(0) 465 466 467 #if HVD_ENABLE_MSOS_SYSTEM_CALL 468 #define HVD_GetSysTime_ms() MsOS_GetSystemTime() 469 #define HVD_SYSTEM_CLOCK_TYPE 1 470 #elif defined(REDLION_LINUX_KERNEL_ENVI) 471 #define HVD_GetSysTime_ms() MHal_H264_GetSyetemTime() 472 #define HVD_SYSTEM_CLOCK_TYPE 2 473 #else 474 #define HVD_GetSysTime_ms() 1 475 #define HVD_SYSTEM_CLOCK_TYPE 0 476 #endif // MsOS_GetSystemTime 477 478 #if HVD_ENABLE_MSOS_SYSTEM_CALL 479 #include "asmCPU.h" 480 #define HAL_MEMORY_BARRIER() MAsm_CPU_Sync() 481 #define HVD_MEMORY_BARRIER_TYPE 3 482 #else 483 #if defined (__mips__) 484 #define HAL_MEMORY_BARRIER() __asm__ volatile ("sync;") 485 #define HVD_MEMORY_BARRIER_TYPE 1 486 #elif defined (__aeon__) 487 #ifdef __AEONR2__ 488 #define HAL_MEMORY_BARRIER() __asm__ volatile ("b.syncwritebuffer;") 489 #define HVD_MEMORY_BARRIER_TYPE 22 490 #else 491 #if defined( CHIP_T2 ) 492 #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.msync;") 493 #define HVD_MEMORY_BARRIER_TYPE 21 494 #else 495 #define HAL_MEMORY_BARRIER() __asm__ volatile ("l.syncwritebuffer;") 496 #define HVD_MEMORY_BARRIER_TYPE 23 497 #endif 498 #endif 499 #else 500 #define HAL_MEMORY_BARRIER() 501 #define HVD_MEMORY_BARRIER_TYPE 0 502 #endif 503 #endif 504 505 #define HVD_DRV_MODE_EXTERNAL_DS_BUFFER (1 << 0) 506 507 //------------------------------------------------------------------------------------------------- 508 // Type and Structure 509 //------------------------------------------------------------------------------------------------- 510 typedef void (*HVD_ISRCallBack)(MS_U32 u32Sid); 511 512 typedef enum 513 { 514 E_HVD_RETURN_FAIL=0, 515 E_HVD_RETURN_SUCCESS, 516 E_HVD_RETURN_INVALID_PARAMETER, 517 E_HVD_RETURN_ILLEGAL_ACCESS, 518 E_HVD_RETURN_HARDWARE_BREAKDOWN, 519 E_HVD_RETURN_OUTOF_MEMORY, 520 E_HVD_RETURN_UNSUPPORTED, 521 E_HVD_RETURN_TIMEOUT, 522 E_HVD_RETURN_NOTREADY, 523 E_HVD_RETURN_MEMORY_OVERWIRTE, 524 E_HVD_RETURN_ES_FULL, 525 E_HVD_RETURN_RE_INIT, 526 E_HVD_RETURN_NOT_RUNNING, 527 } HVD_Return; 528 529 typedef enum 530 { 531 // share memory 532 E_HVD_GDATA_SHARE_MEM=0x1000, 533 // switch 534 //E_HVD_GDATA_SEMAPHORE, 535 E_HVD_GDATA_DISP_INFO_ADDR=(0x0100+E_HVD_GDATA_SHARE_MEM), 536 E_HVD_GDATA_MIU_SEL, 537 E_HVD_GDATA_FRAMEBUF_ADDR, 538 E_HVD_GDATA_FRAMEBUF_SIZE, 539 E_HVD_GDATA_FRAMEBUF2_ADDR, 540 E_HVD_GDATA_FRAMEBUF2_SIZE, 541 E_HVD_GDATA_CMA_USED, 542 E_HVD_GDATA_CMA_ALLOC_DONE, 543 E_HVD_GDATA_DYNMC_DISP_PATH_STATUS, 544 // report 545 E_HVD_GDATA_PTS=(0x0200+E_HVD_GDATA_SHARE_MEM), 546 E_HVD_GDATA_U64PTS, 547 E_HVD_GDATA_DECODE_CNT, 548 E_HVD_GDATA_DATA_ERROR_CNT, 549 E_HVD_GDATA_DEC_ERROR_CNT, 550 E_HVD_GDATA_ERROR_CODE, 551 E_HVD_GDATA_VPU_IDLE_CNT, 552 E_HVD_GDATA_DISP_FRM_INFO, 553 E_HVD_GDATA_DEC_FRM_INFO, 554 E_HVD_GDATA_ES_LEVEL, 555 E_HVD_GDATA_PTS_STC_DIFF, 556 #if HVD_ENABLE_MVC 557 E_HVD_GDATA_DISP_FRM_INFO_SUB, 558 E_HVD_GDATA_DEC_FRM_INFO_SUB, 559 #endif 560 E_HVD_GDATA_HVD_HW_MAX_PIXEL, 561 E_HVD_GDATA_TS_SEAMLESS_TARGET_PTS, 562 E_HVD_GDATA_TS_SEAMLESS_TARGET_POC, 563 564 // user data 565 E_HVD_GDATA_USERDATA_WPTR, 566 E_HVD_GDATA_USERDATA_IDX_TBL_ADDR, 567 E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR, 568 E_HVD_GDATA_USERDATA_PACKET_SIZE, 569 E_HVD_GDATA_USERDATA_IDX_TBL_SIZE, 570 E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE, 571 // report - modes 572 E_HVD_GDATA_IS_SHOW_ERR_FRM, 573 E_HVD_GDATA_IS_REPEAT_LAST_FIELD, 574 E_HVD_GDATA_IS_ERR_CONCEAL, 575 E_HVD_GDATA_IS_SYNC_ON, 576 E_HVD_GDATA_IS_PLAYBACK_FINISH, 577 E_HVD_GDATA_SYNC_MODE, 578 E_HVD_GDATA_SKIP_MODE, 579 E_HVD_GDATA_DROP_MODE, 580 E_HVD_GDATA_DISPLAY_DURATION, 581 E_HVD_GDATA_FRC_MODE, 582 E_HVD_GDATA_NEXT_PTS, 583 E_HVD_GDATA_DISP_Q_SIZE, 584 E_HVD_GDATA_DISP_Q_PTR, 585 E_HVD_GDATA_NEXT_DISP_FRM_INFO, 586 E_HVD_GDATA_REAL_FRAMERATE, 587 E_HVD_GDATA_IS_ORI_INTERLACE_MODE, 588 E_HVD_GDATA_FRM_PACKING_SEI_DATA, 589 E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG, 590 E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE, 591 E_HVD_GDATA_FIELD_PIC_FLAG, 592 E_HVD_GDATA_FW_STATUS_FLAG, 593 E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT, 594 E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA, 595 E_HVD_GDATA_U64PTS_PRE_PARSE, 596 E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO, 597 E_HVD_GDATA_SEQ_CHANGE_INFO, 598 599 // internal control 600 E_HVD_GDATA_IS_1ST_FRM_RDY=(0x0300+E_HVD_GDATA_SHARE_MEM), 601 E_HVD_GDATA_IS_I_FRM_FOUND, 602 E_HVD_GDATA_IS_SYNC_START, 603 E_HVD_GDATA_IS_SYNC_REACH, 604 E_HVD_GDATA_FW_VERSION_ID, 605 E_HVD_GDATA_FW_IF_VERSION_ID, 606 E_HVD_GDATA_BBU_Q_NUMB, 607 E_HVD_GDATA_DEC_Q_NUMB, 608 E_HVD_GDATA_DISP_Q_NUMB, 609 E_HVD_GDATA_PTS_Q_NUMB, 610 E_HVD_GDATA_FW_INIT_DONE, 611 E_HVD_GDATA_FW_IS_IQMEM_SUPPORT, 612 E_HVD_GDATA_FW_IQMEM_CTRL, 613 E_HVD_GDATA_FW_FLUSH_STATUS, 614 E_HVD_GDATA_FW_CODEC_TYPE, 615 E_HVD_GDATA_FW_ES_BUF_STATUS, 616 E_HVD_GDATA_TS_SEAMLESS_STATUS, 617 E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG, 618 E_HVD_GDATA_GET_NOT_SUPPORT_INFO, 619 E_HVD_GDATA_GET_MIN_TSP_DATA_SIZE, 620 621 // debug 622 E_HVD_GDATA_SKIP_CNT=(0x0400+E_HVD_GDATA_SHARE_MEM), 623 E_HVD_GDATA_GOP_CNT, 624 E_HVD_GDATA_DISP_CNT, 625 E_HVD_GDATA_DROP_CNT, 626 E_HVD_GDATA_DISP_STC, 627 E_HVD_GDATA_VSYNC_CNT, 628 E_HVD_GDATA_MAIN_LOOP_CNT, 629 // AVC 630 E_HVD_GDATA_AVC_LEVEL_IDC =(0x0500+E_HVD_GDATA_SHARE_MEM), 631 E_HVD_GDATA_AVC_LOW_DELAY, 632 E_HVD_GDATA_AVC_VUI_DISP_INFO, 633 //E_HVD_GDATA_AVC_SPS_ADDR, 634 635 // SRAM 636 E_HVD_GDATA_SRAM=0x2000, 637 //E_HVD_GDATA_AVC_NAL_CNT, 638 639 // Mailbox or Reg 640 E_HVD_GDATA_MBOX=0x3000, 641 E_HVD_GDATA_FW_STATE, // HVD RISC MBOX 0 (esp. FW init done) 642 E_HVD_GDATA_IS_DISP_INFO_UNCOPYED, // HVD RISC MBOX 0 (rdy only) 643 E_HVD_GDATA_IS_DISP_INFO_CHANGE, // HVD RISC MBOX 0 (rdy only) 644 E_HVD_GDATA_HVD_ISR_STATUS, // HVD RISC MBOX 1 (value only) 645 E_HVD_GDATA_IS_FRAME_SHOWED, // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable ) 646 E_HVD_GDATA_ES_READ_PTR, // 647 E_HVD_GDATA_ES_WRITE_PTR, // 648 E_HVD_GDATA_BBU_READ_PTR, // 649 E_HVD_GDATA_BBU_WRITE_PTR, // 650 E_HVD_GDATA_BBU_WRITE_PTR_FIRED, // 651 E_HVD_GDATA_VPU_PC_CNT, // 652 E_HVD_GDATA_ES_QUANTITY, 653 654 // FW def 655 E_HVD_GDATA_FW_DEF=0x4000, 656 E_HVD_GDATA_FW_MAX_DUMMY_FIFO, // AVC: 256Bytes AVS: 2kB RM:??? 657 E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY, 658 E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY, 659 E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB, 660 E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB, 661 E_HVD_GDATA_FW_DUMMY_WRITE_ADDR, 662 E_HVD_GDATA_FW_DS_BUF_ADDR, 663 E_HVD_GDATA_FW_DS_BUF_SIZE, 664 E_HVD_GDATA_FW_DS_VECTOR_DEPTH, 665 E_HVD_GDATA_FW_DS_INFO_ADDR, 666 E_HVD_GDATA_FW_DS_IS_ENABLED, 667 #ifdef VDEC3 668 E_HVD_GDATA_FW_VBBU_ADDR, 669 #endif 670 // BBU size 671 // default pitch number 672 // 673 } HVD_GetData; 674 675 typedef enum 676 { 677 // share memory 678 E_HVD_SDATA_SHARE_MEM = 0x1000, 679 // switch 680 E_HVD_SDATA_FRAMEBUF_ADDR = (0x0100 + E_HVD_SDATA_SHARE_MEM), 681 E_HVD_SDATA_FRAMEBUF_SIZE, 682 E_HVD_SDATA_ERROR_CODE, 683 E_HVD_SDATA_DISP_INFO_TH, 684 E_HVD_SDATA_FW_FLUSH_STATUS, 685 E_HVD_SDATA_DMX_FRAMERATE, 686 E_HVD_SDATA_DMX_FRAMERATEBASE, 687 E_HVD_SDATA_MIU_SEL, 688 E_HVD_SDATA_FRAMEBUF2_ADDR, 689 E_HVD_SDATA_FRAMEBUF2_SIZE, 690 E_HVD_SDATA_CMA_USED, 691 E_HVD_SDATA_CMA_ALLOC_DONE, 692 E_HVD_SDATA_CMA_TWO_MIU, 693 E_HVD_SDATA_MAX_CMA_SIZE, 694 E_HVD_SDATA_MAX_CMA_SIZE2, 695 E_HVD_SDATA_DV_XC_SHM_SIZE, 696 E_HVD_SDATA_DYNMC_DISP_PATH_STATUS, 697 // display info 698 //E_HVD_SDATA_HOR_SIZE=(0x0200|E_HVD_SDATA_SHARE_MEM), 699 // report 700 //E_HVD_SDATA_PTS=0x0200, 701 // internal control 702 //E_HVD_SDATA_IDLE_CNT=0x0300, 703 // debug 704 //E_HVD_SDATA_SKIP_CNT=0x0400, 705 // RM 706 E_HVD_SDATA_RM_PICTURE_SIZES = (0x0500 | E_HVD_SDATA_SHARE_MEM), 707 708 // SRAM 709 // Mailbox or Reg 710 E_HVD_SDATA_MAILBOX = 0x3000, 711 E_HVD_SDATA_FW_CODE_TYPE = (0x0000 | E_HVD_SDATA_MAILBOX), 712 E_HVD_SDATA_TRIGGER_DISP, 713 E_HVD_SDATA_GET_DISP_INFO_DONE, 714 E_HVD_SDATA_GET_DISP_INFO_START, 715 716 // FW def 717 E_HVD_SDATA_FW_DEF = 0x4000, 718 E_HVD_SDATA_VIRTUAL_BOX_WIDTH, 719 E_HVD_SDATA_VIRTUAL_BOX_HEIGHT, 720 //modify the state of the frame in DispQueue 721 E_HVD_SDATA_DISPQ_STATUS_VIEW, 722 E_HVD_SDATA_DISPQ_STATUS_DISP, 723 E_HVD_SDATA_DISPQ_STATUS_FREE, 724 E_HVD_SDATA_FW_IQMEM_CTRL, 725 E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, 726 E_HVD_SDATA_DV_INFO, 727 E_HVD_SDATA_HDR_PERFRAME, 728 E_HVD_SDATA_VP9HDR10INFO, 729 } HVD_SetData; 730 731 typedef enum 732 { 733 E_HVD_UART_CTRL_DISABLE = BIT(4), 734 E_HVD_UART_CTRL_ERR = BIT(0), 735 E_HVD_UART_CTRL_INFO = BIT(1), 736 E_HVD_UART_CTRL_DBG = BIT(2), 737 E_HVD_UART_CTRL_FW = BIT(3), 738 E_HVD_UART_CTRL_MUST = BIT(4), 739 E_HVD_UART_CTRL_TRACE = BIT(5), 740 } HVD_Uart_Ctrl; 741 742 typedef enum 743 { 744 E_HVD_INIT_HW_MASK = BMASK(3:0), ///< HW Type, should same as HVD_Codec_Type in fwHVD_if.h 745 E_HVD_INIT_HW_AVC = BITS(3:0, 0), ///< HW deflaut: AVC 0X00 746 E_HVD_INIT_HW_AVS = BITS(3:0, 1), ///< HW: AVS 0X01 747 E_HVD_INIT_HW_RM = BITS(3:0, 2), ///< HW: RM 0X10 748 E_HVD_INIT_HW_MVC = BITS(3:0, 3), ///< HW: MVC 0x11 749 E_HVD_INIT_HW_VP8 = BITS(3:0, 4), ///< HW: VP8 0X100 750 E_HVD_INIT_HW_MJPEG = BITS(3:0, 5), ///< HW: MJPEG 0x101 751 E_HVD_INIT_HW_VP6 = BITS(3:0, 6), ///< HW: VP6 0x110 752 E_HVD_INIT_HW_HEVC = BITS(3:0, 7), ///< HW: HEVC 0x111 753 E_HVD_INIT_HW_VP9 = BITS(3:0, 8), ///< HW: VP9 0x1000 754 E_HVD_INIT_HW_HEVC_DV = BITS(3:0, 9), ///< HW: HEVC_DV 0x1001 755 E_HVD_INIT_MAIN_MASK = BMASK(5:4), ///< main type 756 E_HVD_INIT_MAIN_FILE_RAW = BITS(5:4, 0), ///< main type: default: 0X00 757 E_HVD_INIT_MAIN_FILE_TS = BITS(5:4, 1), ///< main type: 0X01 758 E_HVD_INIT_MAIN_LIVE_STREAM = BITS(5:4, 2), ///< main type: 0X10 759 E_HVD_INIT_INPUT_MASK = BMASK(6:6), ///< process path for filling BBU table: file mode. use drive; TSP: use tsp mode 760 E_HVD_INIT_INPUT_TSP = BITS(6:6, 0), ///< tsp input( default) 761 E_HVD_INIT_INPUT_DRV = BITS(6:6, 1), ///< driver input 762 E_HVD_INIT_START_CODE_MASK = BMASK(7:7), ///< AVC FILE MODE ONLY: mkv, mp4 container use. 763 E_HVD_INIT_START_CODE_REMAINED = BITS(7:7, 0), ///< start code remained.(Defualt) 764 E_HVD_INIT_START_CODE_REMOVED = BITS(7:7, 1), ///< start code removed. 765 E_HVD_INIT_UTOPIA_ENVI = BIT(8), ///< check MIU sel and set it 766 E_HVD_INIT_DBG_FW = BIT(9), ///< check FW is debug version or not 767 E_HVD_INIT_DUAL_ES_MASK = BMASK(10:10), ///< Dual ES buffer iput. 768 E_HVD_INIT_DUAL_ES_DISABLE = BITS(10:10, 0), ///< Disable Dual ES buffer input. 769 E_HVD_INIT_DUAL_ES_ENABLE = BITS(10:10, 1), ///< Enable Dual ES buffer input. 770 //E_HVD_INIT_ENABLE_ISR_DISP = BIT( 8) , ///< enable display ISR. ISR occurs at every Vsync. 771 } HVD_Init_Mode_Flag; 772 773 typedef enum 774 { 775 E_HVD_PLAY_NORMAL, 776 E_HVD_PLAY_PAUSE, 777 E_HVD_PLAY_STEP_DISPLAY, 778 } HVD_Play_Type; 779 780 typedef enum 781 { 782 E_HVD_ESB_LEVEL_NORMAL = 0, 783 E_HVD_ESB_LEVEL_UNDER = BIT(0), 784 E_HVD_ESB_LEVEL_OVER = BIT(1), 785 } HVD_ESBuf_Level; 786 787 //----------------------------------------------------------------------------- 788 /// @brief \b Enum \b Name: HVD_FWInputSourceType 789 /// @brief \b Enum \b Description: The type of fw binary input source 790 //----------------------------------------------------------------------------- 791 typedef enum 792 { 793 E_HVD_FW_INPUT_SOURCE_NONE, ///< No input fw. 794 E_HVD_FW_INPUT_SOURCE_DRAM, ///< input source from DRAM. 795 E_HVD_FW_INPUT_SOURCE_FLASH, ///< input source from FLASH. 796 } HVD_FWInputSourceType; 797 798 //----------------------------------------------------------------------------- 799 /// @brief \b Enum \b Name: HVD_FB_Reduction_Type 800 /// @brief \b Enum \b Description: The type of frame buffer reduction type 801 //----------------------------------------------------------------------------- 802 typedef enum 803 { 804 E_HVD_FB_REDUCTION_TYPE_NONE = 0, ///< FB reduction disable 805 E_HVD_FB_REDUCTION_TYPE_1_2 = 1, ///< FB reduction 1/2 806 E_HVD_FB_REDUCTION_TYPE_1_4 = 2, ///< FB reduction 1/4 807 } HVD_FBReductionType; 808 809 typedef enum 810 { 811 E_VDEC_EX_MAIN_VIEW = 0, ///< MVC main view 812 E_VDEC_EX_SUB_VIEW, ///< MVC sub view 813 } VDEC_EX_View; 814 815 typedef enum 816 { 817 E_HVD_SECURE_MODE_NONE = 0, /// None secure 818 E_HVD_SECURE_MODE_TRUSTZONE /// Secure for TrustZone 819 } HVD_SECURE_MODE; 820 821 typedef enum 822 { 823 E_HWDEC_ISR_NONE = 0, 824 E_HWDEC_ISR_HVD = 1, // For HW Decoder check 825 E_HWDEC_ISR_EVD = 2, 826 E_HWDEC_ISR_G2VP9 = 3 827 } HWDEC_ISR_TYPE; 828 829 //HVD set MFcodec Mode 830 typedef enum 831 { 832 E_HVD_DEF_MFCODEC_DEFAULT = 0, 833 E_HVD_DEF_MFCODEC_FORCE_ENABLE, 834 E_HVD_DEF_MFCODEC_FORCE_DISABLE, 835 } HVD_MFCodec_mode; 836 837 typedef enum 838 { 839 E_HVD_DEF_FEATURE_DEFAULT = 0, 840 E_HVD_DEF_FEATURE_FORCE_MAIN_PROFILE = 1, //BIT0=1: HEVC Only support Main profile decode 841 E_HVD_DEF_FEATURE_DISABLE_TEMPORAL_SCALABILITY = 1 << 1, // Bit 1 = 1: do not support temporal scalibity 842 } HVD_Feature; 843 844 845 typedef enum 846 { 847 // Indicates Dolby Vision stream profile is Unsupported. 848 E_DV_STREAM_PROFILE_ID_UNSUPPORTED = 0x0, 849 // Indicates Dolby Vision stream profile is "dvav.per". 850 E_DV_STREAM_PROFILE_ID_DVAV_PER = 0x1, 851 // Indicates Dolby Vision stream profile is "dvav.pen". 852 E_DV_STREAM_PROFILE_ID_DVAV_PEN = 0x2, 853 // Indicates Dolby Vision stream profile is "dvhe.der". 854 E_DV_STREAM_PROFILE_ID_DVHE_DER = 0x4, 855 // Indicates Dolby Vision stream profile is "dvhe.den". 856 E_DV_STREAM_PROFILE_ID_DVHE_DEN = 0x8, 857 // Indicates Dolby Vision stream profile is "dvhe.dtr". 858 E_DV_STREAM_PROFILE_ID_DVHE_DTR = 0x10, 859 // Indicates Dolby Vision stream profile is "dvhe.stn". 860 E_DV_STREAM_PROFILE_ID_DVHE_STN = 0x20, 861 // Indicates Dolby Vision stream profile is "dvhe.dth". 862 E_DV_STREAM_PROFILE_ID_DVHE_DTH = 0x40, 863 } DV_Stream_Profile; 864 865 typedef enum 866 { 867 // Indicates Dolby Vision stream level is unsupported. 868 E_DV_STREAM_LEVEL_ID_UNSUPPORTED = 0, 869 // Indicates Dolby Vision stream level is "HD24". 870 E_DV_STREAM_LEVEL_ID_HD24, 871 // Indicates Dolby Vision stream level is "HD30". 872 E_DV_STREAM_LEVEL_ID_HD30, 873 // Indicates Dolby Vision stream level is "FHD24". 874 E_DV_STREAM_LEVEL_ID_FHD24, 875 // Indicates Dolby Vision stream level is "FHD30". 876 E_DV_STREAM_LEVEL_ID_FHD30, 877 // Indicates Dolby Vision stream level is "FHD60". 878 E_DV_STREAM_LEVEL_ID_FHD60, 879 // Indicates Dolby Vision stream level is "UHD24". 880 E_DV_STREAM_LEVEL_ID_UHD24, 881 // Indicates Dolby Vision stream level is "UHD30". 882 E_DV_STREAM_LEVEL_ID_UHD30, 883 // Indicates Dolby Vision stream level is "UHD48". 884 E_DV_STREAM_LEVEL_ID_UHD48, 885 // Indicates Dolby Vision stream level is "UHD60". 886 E_DV_STREAM_LEVEL_ID_UHD60, 887 } DV_Stream_Level; 888 889 typedef enum 890 { 891 E_HVD_ORIGINAL_MAIN_STREAM = 0, 892 E_HVD_ORIGINAL_SUB_STREAM, 893 E_HVD_ORIGINAL_N_STREAM, 894 } HVD_Original_Stream; 895 896 //----------------------------------------------------------------------------- 897 /// @brief \b Struct \b Name: HVD_EX_MemMap 898 /// @brief \b Struct \b Description: Store the HVD driver config 899 //----------------------------------------------------------------------------- 900 typedef struct 901 { 902 MS_PHY u32MIU1BaseAddr; //!< the physical memory start address of MIU 1 base address. 0: default value. 903 MS_PHY u32MIU2BaseAddr; //!< the physical memory start address of MIU 2 base address. 0: default value. 904 MS_VIRT u32FWBinaryVAddr; //!< virtual address of input FW binary in DRAM 905 MS_PHY u32FWBinaryAddr; //!< the physical memory start address in Flash memory of FW code source. 906 MS_U32 u32FWBinarySize; //!< the FW code size 907 MS_VIRT u32VLCBinaryVAddr; //!< VLC table binary data buffer start address 908 MS_PHY u32VLCBinaryAddr; //!< VLC table binary data buffer start address 909 MS_U32 u32VLCBinarySize; //!<VLC table binary data buffer size 910 MS_VIRT u32CodeBufVAddr; //!< the virtual memory start address of code buffer 911 MS_PHY u32CodeBufAddr; //!< the physical memory start address of code buffer 912 MS_U32 u32CodeBufSize; //!< the code buffer size 913 MS_VIRT u32FrameBufVAddr; //!< the virtual memory start address of frame buffer 914 MS_PHY u32FrameBufAddr; //!< the physical memory start address of frame buffer 915 MS_U32 u32FrameBufSize; //!< the frame buffer size 916 MS_VIRT u32BitstreamBufVAddr; //!< the virtual memory start address of bit stream buffer 917 MS_PHY u32BitstreamBufAddr; //!< the physical memory start address of bit stream buffer 918 MS_U32 u32BitstreamBufSize; //!< the bit stream buffer size 919 MS_VIRT u32DrvProcessBufVAddr; //!< the virtual memory start address of driver process buffer 920 MS_PHY u32DrvProcessBufAddr; //!< the physical memory start address of driver process buffer 921 MS_U32 u32DrvProcessBufSize; //!< the driver process buffer size 922 MS_VIRT u32DynSacalingBufVAddr; //!< the virtual memory start address of dynamic scaling buffer 923 MS_PHY u32DynSacalingBufAddr; //!< the physical memory start address of dynamic scaling buffer 924 MS_U32 u32DynSacalingBufSize; //!< the dynamic scaling buffer size 925 HVD_FWInputSourceType eFWSourceType; //!< the input FW source type. 926 #ifdef VDEC3 927 MS_PHY u32TotalBitstreamBufAddr; 928 MS_U32 u32TotalBitstreamBufSize; 929 #endif 930 } HVD_EX_MemMap; 931 932 //----------------------------------------------------------------------------- 933 /// @brief \b Struct \b Name: HVD_Nal_Entry 934 /// @brief \b Struct \b Description: Store the information of one nal entry 935 //----------------------------------------------------------------------------- 936 typedef struct 937 { 938 MS_U32 u32NalID; ///< the ID nunber of this nal 939 MS_VIRT u32NalAddr; ///< the offset of this nal from bit stream buffer start address. unit: byte 940 MS_U32 u32NalSize; ///< the size of this nal. unit: byte 941 MS_U32 u32NalPTS; ///< the time stamp of this nal. unit: ms 942 MS_BOOL bRVBrokenPacket; ///< the RV only 943 } HVD_Nal_Entry; 944 945 //----------------------------------------------------------------------------- 946 /// @brief \b Struct \b Name: RV_FileInfo 947 /// @brief \b Struct \b Description: RV file information 948 //----------------------------------------------------------------------------- 949 typedef struct 950 { 951 MS_U16 RV_Version; ///< Real Video Bitstream version 952 MS_U16 ulNumSizes; ///< Real Video Number sizes 953 MS_U16 ulPicSizes_w[8]; ///< Real Video file width 954 MS_U16 ulPicSizes_h[8]; ///< Real Video file height 955 } RV_FileInfo; 956 957 //----------------------------------------------------------------------------- 958 /// @brief \b Struct \b Name: HVD_FB_Reduction_Mode 959 /// @brief \b Struct \b Description: Set up frame buffer reduction mode 960 //----------------------------------------------------------------------------- 961 typedef struct 962 { 963 HVD_FBReductionType eLumaFBReductionMode; ///< Luma frame buffer reduction mode. 964 HVD_FBReductionType eChromaFBReductionMode; ///< Chroma frame buffer reduction mode. 965 MS_U8 u8EnableAutoMode; /// 0: Disable, 1: Enable 966 } HVD_FBReductionMode; 967 968 //----------------------------------------------------------------------------- 969 /// @brief \b Struct \b Name: HVD_Init_Params 970 /// @brief \b Struct \b Description: Store the initialization settings 971 //----------------------------------------------------------------------------- 972 typedef struct 973 { 974 MS_U32 u32ModeFlag; ///< init mode flag, use HVD_INIT_* to setup HVD. 975 MS_U32 u32FrameRate; ///< frame rate. 976 MS_U32 u32FrameRateBase; ///< frame rate base. The value of u32FrameRate /u32FrameRateBase must be frames per sec. 977 MS_U8 u8MinFrmGap; ///< set the min frame gap. 978 MS_U8 u8SyncType; ///< HVD_EX_SyncType. sync type of current playback. 979 MS_U16 u16Pitch; ///< not zero: specify the pitch. 0: use default value. 980 MS_U32 u32MaxDecTick; ///< not zero: specify the max decode tick. 0: use default value. 981 MS_BOOL bSyncEachFrm; ///< TRUE: sync STC at each frame. FALSE: not sync each frame. 982 MS_BOOL bAutoFreeES; ///< TRUE: auto free ES buffer when ES buffer is full. FALSE: not do the auto free. 983 MS_BOOL bAutoPowerSaving; ///< TRUE: auto power saving. FALSE: not do the auto power saving. 984 MS_BOOL bDynamicScaling; ///< TRUE: enable Dynamic Scaling. FALSE: disable Dynamic Scaling. 985 MS_BOOL bFastDisplay; ///< TRUE: enable Fast Display. FALSE: disable Fast Display. 986 MS_BOOL bUserData; ///< TRUE: enable processing User data. FALSE: disable processing User data. 987 MS_U8 u8TurboInit; ///< HVD_TurboInitLevel. set the turbo init mode. 988 MS_U8 u8TimeUnit; ///< HVD_Time_Unit_Type.set the type of input/output time unit. 989 MS_U16 u16DecoderClock; ///< HVD decoder clock speed. 0: default value. non-zero: any nearist clock. 990 MS_U16 u16ChipECONum; ///< Chip revision, ECO number. 991 RV_FileInfo* pRVFileInfo; ///< pointer to RV file info 992 HVD_FBReductionMode stFBReduction; ///< HVD Frame buffer reduction type 993 } HVD_Init_Params; 994 995 //----------------------------------------------------------------------------- 996 /// @brief \b Struct \b Name: HVD_BBU_Info 997 /// @brief \b Struct \b Description: Store the packet information 998 //----------------------------------------------------------------------------- 999 typedef struct 1000 { 1001 MS_VIRT u32Staddr; ///< Packet offset from bitstream buffer base address. unit: byte. 1002 MS_U32 u32Length; ///< Packet size. unit: byte. 1003 MS_VIRT u32Staddr2; ///< Packet offset from bitstream buffer base address. unit: byte. 1004 MS_U32 u32Length2; ///< Packet size. unit: byte. 1005 MS_U32 u32TimeStamp; ///< Packet time stamp. unit: ms. 1006 MS_U32 u32ID_L; ///< Packet ID low part. 1007 MS_U32 u32ID_H; ///< Packet ID high part. 1008 MS_U32 u32AllocLength; ///< Allocated Packet size. unit: byte. 1009 MS_U32 u32OriPktAddr; ///< Original packet offset from bitstream buffer base address. unit: byte. 1010 MS_BOOL bRVBrokenPacket; ///< the RV only 1011 } HVD_BBU_Info; 1012 1013 //----------------------------------------------------------------------------- 1014 /// @brief \b Struct \b Name: HVD_Alive_Status 1015 /// @brief \b Struct \b Description: Store the decoder living information 1016 //----------------------------------------------------------------------------- 1017 typedef struct 1018 { 1019 MS_U32 u32DecCnt; 1020 MS_U32 u32SkipCnt; 1021 MS_U32 u32IdleCnt; 1022 MS_U32 u32MainLoopCnt; 1023 MS_U32 u32LastAliveTime; 1024 } HVD_Alive_Status; 1025 1026 //----------------------------------------------------------------------------- 1027 /// @brief \b Struct \b Name: HVD_DISP_INFO_THRESHOLD 1028 /// @brief \b Struct \b Description: Store the disp information threshold. 1029 //----------------------------------------------------------------------------- 1030 typedef struct 1031 { 1032 MS_U32 u32FrmrateUpBound; //Framerate filter upper bound 1033 MS_U32 u32FrmrateLowBound; //Framerate filter lower bound 1034 MS_U32 u32MvopUpBound; //mvop filter upper bound 1035 MS_U32 u32MvopLowBound; //mvop filter lower bound 1036 } HVD_Disp_Info_TH; 1037 1038 //----------------------------------------------------------------------------- 1039 /// @brief \b Struct \b Name: HVD_Settings 1040 /// @brief \b Struct \b Description: Store the settings of user requirment 1041 //----------------------------------------------------------------------------- 1042 typedef struct 1043 { 1044 // TODO: currently only DTV settings. Need to add more settings for MM. 1045 // Mode 1046 HVD_Disp_Info_TH DispInfoTH; 1047 MS_U32 u32IsrEvent; 1048 MS_BOOL bEnISR; 1049 1050 MS_U8 u8SkipMode; // HVD_Skip_Decode_Type 1051 MS_U8 bIsShowErrFrm; 1052 MS_U8 u8FrcMode; //HVD_EX_FrmRateConvMode 1053 1054 MS_BOOL bIsErrConceal; 1055 MS_BOOL bAutoFreeES; 1056 MS_BOOL bDisDeblocking; 1057 MS_BOOL bDisQuarterPixel; 1058 1059 MS_U8 bIsSyncOn; 1060 MS_U32 u32SyncTolerance; 1061 MS_U32 u32SyncRepeatTH; 1062 MS_U32 u32SyncVideoDelay; 1063 MS_U32 u32SyncFreeRunTH; 1064 MS_U32 u32MiuBurstLevel; 1065 } HVD_Settings; 1066 1067 //----------------------------------------------------------------------------- 1068 /// @brief \b Struct \b Name: HVD_CC_Info 1069 /// @brief \b Struct \b Description: HVD Close Caption Infomation. 1070 //----------------------------------------------------------------------------- 1071 typedef struct 1072 { 1073 MS_U8 u8UserDataMode; 1074 MS_U8 u8ParsingStatus; 1075 MS_BOOL b708Enable; 1076 MS_BOOL b608InfoEnhance; 1077 //MS_BOOL bBufMiu1[2]; 1078 MS_U8 u8BufMiuSel[2]; 1079 MS_BOOL bOverFlow[2]; 1080 MS_PHY u32RingBufStartPAddr[2];//physical address 1081 MS_U32 u32RingBufLen[2]; 1082 MS_U32 volatile u32RingBufVacancy[2]; 1083 MS_PHY volatile u32RingBufRPAddr[2], u32RingBufWPAddr[2];//physical address 1084 MS_U32 volatile u32FWUsrDataRIdx, u32FWUsrDataWIdx; 1085 MS_U32 u32PktLen708; 1086 MS_VIRT u32PktHdrAddr708; 1087 MS_U8 u8CC608buf[512]; 1088 MS_U8 u8CC708buf[512]; 1089 } HVD_CC_Info; 1090 1091 typedef struct 1092 { 1093 MS_U16 u16TmpRef; 1094 MS_U16 u16PicStruct; 1095 MS_U32 u32Pts; 1096 MS_U8 u8UsrDataCnt; 1097 } HVD_CC_608EnhanceInfo; 1098 1099 1100 //----------------------------------------------------------------------------- 1101 /// @brief \b Struct \b Name: HVD_ISR_Ctrl 1102 /// @brief \b Struct \b Description: HVD driver ISR control. 1103 //----------------------------------------------------------------------------- 1104 typedef struct 1105 { 1106 MS_BOOL bRegISR; 1107 MS_BOOL bInISR; 1108 MS_U32 u32ISRInfo; 1109 MS_U32 u32IntCount; 1110 HVD_ISRCallBack pfnISRCallBack; 1111 MS_BOOL bDisableISRFlag; 1112 MS_BOOL bIsHvdIsr; 1113 MS_BOOL bIsG2Vp9Isr; 1114 HWDEC_ISR_TYPE eHWDecIsr; //HVD, EVD, G2VP9 ISR 1115 } HVD_ISR_Ctrl; 1116 1117 //----------------------------------------------------------------------------- 1118 /// @brief \b Struct \b Name: HVD_EX_Drv_Ctrl 1119 /// @brief \b Struct \b Description: HVD driver internal control. 1120 //----------------------------------------------------------------------------- 1121 typedef struct 1122 { 1123 // init stage 1124 MS_BOOL bUsed; 1125 HVD_EX_MemMap MemMap; ///< HVD memory config 1126 HVD_Init_Params InitParams; ///< HVD init settings 1127 MS_BOOL bNoDrvProccBuf; 1128 MS_BOOL bAutoRmLastZeroByte; 1129 MS_BOOL bCannotAccessMIU256; 1130 MS_U32 u32CmdTimeout; ///< HVD FW command timeout 1131 void *pLastFrmInfo; 1132 void *pLastFrmInfo_ext; 1133 1134 // reset stage 1135 MS_U32 u32CtrlMode; ///< HVD run-time control flag 1136 MS_U32 u32DummyWriteBuf; ///< For dummy write MIU action. 1137 //MS_U32 u32CPUNonCacheMask; ///< CPU non-cache mask 1138 MS_U32 u32NULLPacketSize; ///< to store the size of AVI null packet pattern 1139 MS_VIRT u32NULLPacketAddr; ///< to store the start address of AVI null packet pattern from bitstream buffer base. 1140 MS_U32 u32RV_FlushPacketSize; ///< to store the size of rm flush packet pattern 1141 MS_U32 u32RV_FlushPacketAddr; ///< to store the start address of rm flush packet pattern from bitstream buffer base. 1142 MS_U32 u32StepDecodeCnt; 1143 //MS_U32 u32LastBBUPTS; 1144 //MS_U32 u32DummyDataSize; ///< buffer size of dummy data. 1145 //MS_U32 u32RestSizeofPushDummy; 1146 //MS_U32 u32AddrPushDummy; 1147 MS_U32 u32LastESRptr; 1148 MS_U32 u32BBUTblInBitstreamBufAddr; 1149 MS_U32 u32BBUPacketCnt; 1150 MS_U32 u32BBUWptr_Fired; 1151 MS_U32 u32LastErrCode; 1152 //MS_BOOL bPushingDummy; 1153 MS_BOOL bIsDispInfoChg; 1154 MS_BOOL bFrmRateSupported; 1155 HVD_Nal_Entry LastNal; 1156 HVD_Alive_Status LivingStatus; 1157 1158 // recovery stage 1159 MS_BOOL bStepDecoding; 1160 HVD_Settings Settings; 1161 1162 MS_U8 bTurboFWMode; //TRUE:not reload FW more than once if pre-decoder is the same. 1163 1164 // ISR control 1165 HVD_ISR_Ctrl HVDISRCtrl; 1166 MS_U32 u32Sid; // stream ID 1167 1168 // user data 1169 MS_U32 u32UsrDataRd; 1170 MS_U32 u32UsrDataWr; 1171 HVD_CC_Info CloseCaptionInfo; 1172 1173 MS_U32 u32FlushRstPtr; ///< flush rst ptr: 0: init, 1:after flush and before push packet 1174 1175 // Secure Mode 1176 MS_U8 u8SecureMode; // Enum HVD_SECURE_MODE 1177 MS_U8 u8SettingMode; // Record Setting mode 1178 MS_U8 u8Resv[2]; 1179 MS_U32 u32ExternalDSbuf; // External DS buffer 1180 MS_U8 u8CodeMiuSel; 1181 MS_U8 u8ESMiuSel; 1182 MS_U8 u8FrmMiuSel; 1183 MS_U8 u8Frm2MiuSel; 1184 MS_U8 u8DrvProccMiuSel; 1185 #ifdef VDEC3 1186 MS_BOOL bShareBBU; 1187 MS_U32 u32BBUId; 1188 HVD_Original_Stream eStream; 1189 #endif 1190 } HVD_EX_Drv_Ctrl; 1191 1192 typedef void(*P_SC_ISR_Proc)(MS_U8 u8SCID); 1193 1194 typedef struct 1195 { 1196 MS_BOOL bEnable; 1197 MS_U32 u32IapGnBufAddr; 1198 MS_U32 u32IapGnBufSize; 1199 } HVD_EX_IapGnBufShareBWMode; 1200 1201 typedef struct 1202 { 1203 MS_BOOL bConnect; 1204 MS_U8 eMvopPath; 1205 } HVD_EX_DynmcDispPath; 1206 1207 typedef struct 1208 { 1209 MS_BOOL bEnable; 1210 HVD_EX_DynmcDispPath stDynmcDispPath; 1211 } HVD_EX_PreCtrlDispPath; 1212 1213 typedef struct 1214 { 1215 MS_BOOL bEnable; 1216 MS_U8 u8InputTsp; 1217 } HVD_EX_PreCtrlInputTsp; 1218 1219 typedef struct 1220 { 1221 MS_BOOL bOnePendingBuffer; 1222 MS_BOOL bFrameRateHandling; 1223 MS_U32 u32PreSetFrameRate; 1224 HVD_EX_IapGnBufShareBWMode stIapGnShBWMode; 1225 MS_BOOL bDisableTspInBbuMode; 1226 HVD_MFCodec_mode eMFCodecMode; 1227 MS_BOOL bForce8BitMode; 1228 MS_U32 eVdecFeature; 1229 MS_BOOL bDVSingleLayerMode; 1230 MS_BOOL bEnableDynamicCMA; 1231 MS_BOOL bCalFrameRate; 1232 HVD_EX_PreCtrlDispPath stPreConnectDispPath; 1233 HVD_EX_PreCtrlInputTsp stPreConnectInputTsp; 1234 } HVD_Pre_Ctrl; 1235 1236 //------------------------------------------------------------------------------------------------- 1237 // Function and Variable 1238 //------------------------------------------------------------------------------------------------- 1239 extern MS_U32 u32UartCtrl; 1240 //extern MS_U32 u32InitSysTimeBase; 1241 1242 #endif // _DRV_HVD_DEF_H_ 1243 1244