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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _HAL_VPU_EX_H_ 96 #define _HAL_VPU_EX_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Macro and Define 100 //------------------------------------------------------------------------------------------------- 101 #ifndef MSOS_TYPE_NUTTX 102 103 #if defined(REDLION_LINUX_KERNEL_ENVI) 104 #define ENABLE_VPU_MUTEX_PROTECTION 0 105 #define VPU_DEFAULT_MUTEX_TIMEOUT 0xFFFFFFFFUL 106 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 107 #else 108 #define ENABLE_VPU_MUTEX_PROTECTION 1 109 #define VPU_DEFAULT_MUTEX_TIMEOUT MSOS_WAIT_FOREVER 110 111 #if defined(FW_EXTERNAL_BIN) 112 #define VPU_ENABLE_EMBEDDED_FW_BINARY 0 113 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 1 114 #else 115 #define VPU_ENABLE_EMBEDDED_FW_BINARY 1 116 #define VPU_ENABLE_BDMA_FW_FLASH_2_SDRAM 0 117 #endif 118 119 #endif 120 121 #define ENABLE_DECOMPRESS_FUNCTION TRUE 122 123 #define VPU_CLOCK_240MHZ BITS(4:2,0) 124 #define VPU_CLOCK_216MHZ BITS(4:2,1) 125 #define VPU_CLOCK_192MHZ BITS(4:2,2) 126 #define VPU_CLOCK_XTAL BITS(4:2,3) 127 #define VPU_CLOCK_320MHZ BITS(4:2,4) 128 #define VPU_CLOCK_288MHZ BITS(4:2,5) 129 130 131 #define VPU_IQMEM_BASE 0xe0000000 132 133 #define VPU_ENABLE_MOBF_TEST 0 134 135 136 137 #define VPU_HI_MBOX0 0 138 #define VPU_HI_MBOX1 1 139 #define VPU_RISC_MBOX0 2 140 #define VPU_RISC_MBOX1 3 141 142 143 #define VPU_EX_TimerDelayMS(x) \ 144 do \ 145 { \ 146 volatile MS_U32 ticks = 0; \ 147 while (ticks < (((MS_U32) (x)) << 13)) \ 148 { \ 149 ticks++; \ 150 } \ 151 } while(0) 152 153 #define VPU_MAX_DEC_NUM 2 154 155 //------------------------------------------------------------------------------------------------- 156 // Type and Structure 157 //------------------------------------------------------------------------------------------------- 158 typedef enum 159 { 160 E_HAL_HVD_STREAM_NONE = 0x0, 161 162 //Support TSP/TS/File mode 163 E_HAL_HVD_MAIN_STREAM_BASE = 0x10, 164 E_HAL_HVD_MAIN_STREAM0 = E_HAL_HVD_MAIN_STREAM_BASE, 165 E_HAL_HVD_MAIN_STREAM_MAX, 166 167 //Only support file mode 168 E_HAL_HVD_SUB_STREAM_BASE = 0x20, 169 E_HAL_HVD_SUB_STREAM0 = E_HAL_HVD_SUB_STREAM_BASE, 170 E_HAL_HVD_SUB_STREAM1, 171 E_HAL_HVD_SUB_STREAM_MAX, 172 173 //Only support MVC stream 174 E_HAL_HVD_MVC_STREAM_BASE = 0xF0, 175 E_HAL_HVD_MVC_Main_View = E_HAL_HVD_MVC_STREAM_BASE, 176 E_HAL_HVD_MVC_Sub_View, 177 E_HAL_HVD_MVC_STREAM_MAX, 178 } HAL_HVD_StreamId; 179 180 typedef enum 181 { 182 E_VPU_EX_DECODER_NONE = 0, 183 E_VPU_EX_DECODER_MVD, 184 E_VPU_EX_DECODER_HVD, 185 E_VPU_EX_DECODER_MJPEG, 186 E_VPU_EX_DECODER_RVD, 187 E_VPU_EX_DECODER_MVC, 188 } VPU_EX_DecoderType; 189 190 typedef enum 191 { 192 E_VPU_EX_CLOCK_240MHZ = VPU_CLOCK_240MHZ, 193 E_VPU_EX_CLOCK_216MHZ = VPU_CLOCK_216MHZ, 194 E_VPU_EX_CLOCK_192MHZ = VPU_CLOCK_192MHZ, 195 E_VPU_EX_CLOCK_XTAL = VPU_CLOCK_XTAL, 196 E_VPU_EX_CLOCK_320MHZ = VPU_CLOCK_320MHZ, 197 E_VPU_EX_CLOCK_288MHZ = VPU_CLOCK_288MHZ, 198 } VPU_EX_ClockSpeed; 199 200 typedef enum 201 { 202 E_HAL_VPU_STREAM_NONE = 0x0, 203 204 //Support TSP/TS File/File mode 205 E_HAL_VPU_MAIN_STREAM_BASE = 0x10, 206 E_HAL_VPU_MAIN_STREAM0 = E_HAL_VPU_MAIN_STREAM_BASE, 207 E_HAL_VPU_MAIN_STREAM_MAX, 208 209 //Only support file mode 210 E_HAL_VPU_SUB_STREAM_BASE = 0x20, 211 E_HAL_VPU_SUB_STREAM0 = E_HAL_VPU_SUB_STREAM_BASE, 212 E_HAL_VPU_SUB_STREAM_MAX, 213 214 //Only support MVC stream 215 E_HAL_VPU_MVC_STREAM_BASE = 0xF0, 216 E_HAL_VPU_MVC_MAIN_VIEW = E_HAL_VPU_MVC_STREAM_BASE, 217 E_HAL_VPU_MVC_SUB_VIEW, 218 E_HAL_VPU_MVC_STREAM_MAX, 219 } HAL_VPU_StreamId; 220 221 typedef enum 222 { 223 //Support TSP/TS/File mode 224 E_HAL_VPU_MAIN_STREAM, 225 226 //Only support file mode 227 E_HAL_VPU_SUB_STREAM, 228 229 //Only support MVC mode 230 E_HAL_VPU_MVC_STREAM, 231 232 } HAL_VPU_StreamType; 233 234 typedef enum 235 { 236 //Support TSP/TS/File mode 237 E_VPU_EX_INPUT_TSP, 238 //Only support file mode 239 E_VPU_EX_INPUT_FILE, 240 E_VPU_EX_INPUT_NONE, 241 } VPU_EX_SourceType; 242 243 typedef enum 244 { 245 E_VPU_EX_UART_LEVEL_NONE = 0, ///< Disable all uart message. 246 E_VPU_EX_UART_LEVEL_ERR, ///< Only output error message 247 E_VPU_EX_UART_LEVEL_INFO, ///< output general message, and above. 248 E_VPU_EX_UART_LEVEL_DBG, ///< output debug message, and above. 249 E_VPU_EX_UART_LEVEL_TRACE, ///< output function trace message, and above. 250 E_VPU_EX_UART_LEVEL_FW, ///< output FW message, and above. 251 } VPU_EX_UartLevel; 252 253 typedef enum 254 { 255 E_VPU_EX_FW_VER_CTRLR = 0, 256 E_VPU_EX_FW_VER_MVD_FW, 257 E_VPU_EX_FW_VER_HVD_FW, 258 E_VPU_EX_FW_VER_MVD_IF, 259 E_VPU_EX_FW_VER_HVD_IF, 260 } VPU_EX_FWVerType; 261 262 /// DecodeMode for f/w tasks 263 typedef enum 264 { 265 E_VPU_DEC_MODE_DUAL_INDIE, ///< Two independent tasks 266 E_VPU_DEC_MODE_DUAL_3D, ///< Two dependent tasks for 3D 267 E_VPU_DEC_MODE_SINGLE, ///< One task use the whole SRAM 268 E_VPU_DEC_MODE_MVC = E_VPU_DEC_MODE_SINGLE, 269 } VPU_EX_DecMode; 270 271 /// CmdMode for KOREA3D or PIP mode 272 typedef enum 273 { 274 //Group1:Set Korea3DTV mode 275 E_VPU_CMD_MODE_KR3D_BASE = 0x0000, 276 E_VPU_CMD_MODE_KR3D_INTERLACE = E_VPU_CMD_MODE_KR3D_BASE, 277 E_VPU_CMD_MODE_KR3D_FORCE_P, 278 E_VPU_CMD_MODE_KR3D_INTERLACE_TWO_PITCH, 279 E_VPU_CMD_MODE_KR3D_FORCE_P_TWO_PITCH, 280 281 //Group2:Set PIP mode 282 E_VPU_CMD_MODE_PIP_BASE = 0x1000, 283 E_VPU_CMD_MODE_PIP_SYNC_INDIE = E_VPU_CMD_MODE_PIP_BASE, 284 E_VPU_CMD_MODE_PIP_SYNC_MAIN_STC, 285 E_VPU_CMD_MODE_PIP_SYNC_SWITCH 286 } VPU_EX_CmdMode; 287 288 typedef struct 289 { 290 VPU_EX_ClockSpeed eClockSpeed; 291 MS_BOOL bClockInv; 292 MS_S32 s32VPUMutexID; 293 MS_U32 u32VPUMutexTimeout; 294 MS_BOOL bInMIU1; 295 } VPU_EX_InitParam; 296 297 typedef struct 298 { 299 MS_U32 u32Id; 300 HAL_VPU_StreamId eVpuId; 301 VPU_EX_SourceType eSrcType; 302 VPU_EX_DecoderType eDecType; 303 MS_U8 u8Rsvd; 304 MS_U32 u32HeapSize; 305 } VPU_EX_TaskInfo; 306 307 typedef struct 308 { 309 MS_U32 u32DstAddr; 310 MS_U32 u32DstSize; 311 MS_U32 u32BinSize; 312 MS_U32 u32BinAddr; 313 MS_U8 u8SrcType; 314 } VPU_EX_FWCodeCfg; 315 316 typedef struct 317 { 318 MS_U32 u32DstAddr; 319 MS_U32 u32BinAddr; 320 MS_U32 u32BinSize; 321 MS_U32 u32FrameBufAddr; 322 MS_U32 u32VLCTableOffset; 323 } VPU_EX_VLCTblCfg; 324 325 /// VPU init parameters for dual decoder 326 typedef struct 327 { 328 VPU_EX_FWCodeCfg *pFWCodeCfg; 329 VPU_EX_TaskInfo *pTaskInfo; 330 VPU_EX_VLCTblCfg *pVLCCfg; 331 } VPU_EX_NDecInitPara; 332 333 typedef struct 334 { 335 MS_U8 u8DecMod; 336 MS_U8 u8CodecCnt; 337 MS_U8 u8CodecType[VPU_MAX_DEC_NUM]; 338 MS_U8 u8ArgSize; 339 MS_U32 u32Arg; 340 } VPU_EX_DecModCfg; 341 342 //------------------------------------------------------------------------------------------------- 343 // Function and Variable 344 //------------------------------------------------------------------------------------------------- 345 MS_BOOL HAL_VPU_EX_SetDecodeMode(VPU_EX_DecModCfg *pstCfg); 346 MS_BOOL HAL_VPU_EX_SetSingleDecodeMode(MS_BOOL bEnable); 347 MS_BOOL HAL_VPU_EX_TaskCreate(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 348 MS_BOOL HAL_VPU_EX_TaskDelete(MS_U32 u32Id, VPU_EX_NDecInitPara *pInitPara); 349 MS_BOOL HAL_VPU_EX_SetFWReload(MS_BOOL bReload); 350 351 MS_BOOL HAL_VPU_EX_LoadCode(VPU_EX_FWCodeCfg *pFWCodeCfg); 352 void HAL_VPU_EX_InitRegBase(MS_U32 u32RegBase); 353 354 HAL_VPU_StreamId HAL_VPU_EX_GetFreeStream(HAL_VPU_StreamType eStreamType); 355 MS_BOOL HAL_VPU_EX_Init(VPU_EX_InitParam *InitParams); 356 MS_BOOL HAL_VPU_EX_DeInit(void); 357 void HAL_VPU_EX_PowerCtrl(MS_BOOL bEnable); 358 void HAL_VPU_EX_MIU_RW_Protect(MS_BOOL bEnable); 359 MS_BOOL HAL_VPU_EX_CPUSetting(MS_U32 u32StAddr); 360 MS_BOOL HAL_VPU_EX_SwRst(MS_BOOL bCheckMauIdle); 361 void HAL_VPU_EX_SwRstRelse(void); 362 void HAL_VPU_EX_SwRelseMAU(void); 363 MS_U32 HAL_VPU_EX_MemRead(MS_U32 u32Address); 364 MS_BOOL HAL_VPU_EX_MemWrite(MS_U32 u32Address, MS_U32 u32Value); 365 MS_BOOL HAL_VPU_EX_MBoxRdy(MS_U32 u32type); 366 MS_BOOL HAL_VPU_EX_MBoxRead(MS_U32 u32type, MS_U32 *u32Msg); 367 void HAL_VPU_EX_MBoxClear(MS_U32 u32type); 368 MS_BOOL HAL_VPU_EX_MBoxSend(MS_U32 u32type, MS_U32 u32Msg); 369 MS_U32 HAL_VPU_EX_GetProgCnt(void); 370 MS_U8 HAL_VPU_EX_GetTaskId(MS_U32 u32Id); 371 void HAL_VPU_EX_SetShareInfoAddr(MS_U32 u32Id, MS_U32 u32ShmAddr); 372 MS_U32 HAL_VPU_EX_GetShareInfoAddr(MS_U32 u32Id); 373 MS_BOOL HAL_VPU_EX_IsPowered(void); 374 MS_BOOL HAL_VPU_EX_IsRsted(void); 375 MS_BOOL HAL_VPU_EX_MVDInUsed(void); 376 MS_BOOL HAL_VPU_EX_HVDInUsed(void); 377 void HAL_VPU_EX_IQMemSetDAMode(MS_BOOL bEnable); 378 void HAL_VPU_EX_SetDbgLevel(VPU_EX_UartLevel eLevel); 379 MS_U32 HAL_VPU_EX_GetFWVer(MS_U32 u32Id, VPU_EX_FWVerType eVerType); 380 MS_BOOL HAL_VPU_EX_Init_Share_Mem(void); 381 382 MS_U32 HAL_VPU_EX_MIU1BASE(void); 383 MS_U32 HAL_VPU_EX_GetSHMAddr(void); 384 MS_BOOL HAL_VPU_EX_EnableSecurityMode(MS_BOOL enable); 385 MS_BOOL HAL_VPU_EX_REE_SetSHMBaseAddr(void); 386 MS_BOOL HAL_VPU_EX_REE_RegisterMBX(void); 387 MS_BOOL HAL_VPU_EX_CHIP_Capability(void* pHWCap); 388 389 #else 390 typedef struct 391 { 392 MS_U32 Bitstream_Addr_Main; 393 MS_U32 Bitstream_Len_Main; 394 MS_U32 Bitstream_Addr_Sub; 395 MS_U32 Bitstream_Len_Sub; 396 MS_U32 MIU1_BaseAddr; 397 } VPU_EX_LOCK_DOWN_REGISTER; 398 399 400 MS_BOOL HAL_VPU_EX_LoadCodeInSecure(MS_U32 addr); 401 MS_BOOL HAL_VPU_EX_SetLockDownRegister(void* param); 402 403 #endif 404 405 #endif // _HAL_VPU_EX_H_ 406 407