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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regVPU.h 98 /// @brief VPU Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_VPU_H_ 103 #define _REG_VPU_H_ 104 105 //#include "MsCommon.h" 106 107 #ifndef BMASK 108 #define BIT(_bit_) (1 << (_bit_)) 109 #define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) 110 #define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) 111 #endif 112 113 #ifndef READ_BYTE 114 #define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) 115 #define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) 116 #define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) 117 #define WRITE_BYTE(_reg, _val) { (*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } 118 #define WRITE_WORD(_reg, _val) { (*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } 119 #define WRITE_LONG(_reg, _val) { (*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } 120 #endif 121 122 //------------------------------------------------------------------------------------------------- 123 // Hardware Capability 124 //------------------------------------------------------------------------------------------------- 125 126 127 //------------------------------------------------------------------------------------------------- 128 // Macro and Define 129 //------------------------------------------------------------------------------------------------- 130 131 //***************************************************************************** 132 // RIU macro 133 #define VPU_MACRO_START do { 134 #define VPU_MACRO_END } while (0) 135 #define VPU_RIU_BASE u32VPURegOSBase 136 137 #define VPU_HIGHBYTE(u16) ((MS_U8)((u16) >> 8)) 138 #define VPU_LOWBYTE(u16) ((MS_U8)(u16)) 139 #define VPU_RIU_READ_BYTE(addr) ( READ_BYTE( VPU_RIU_BASE + (addr) ) ) 140 #define VPU_RIU_READ_WORD(addr) ( READ_WORD( VPU_RIU_BASE + (addr) ) ) 141 #define VPU_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( VPU_RIU_BASE+(addr), val); } 142 #define VPU_RIU_WRITE_WORD(addr, val) { WRITE_WORD( VPU_RIU_BASE+(addr), val); } 143 144 145 #define _VPU_ReadByte( u32Reg ) VPU_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 146 147 #define _VPU_Read2Byte( u32Reg ) (VPU_RIU_READ_WORD((u32Reg)<<1)) 148 149 #define _VPU_Read4Byte( u32Reg ) ( (MS_U32)VPU_RIU_READ_WORD((u32Reg)<<1) | ((MS_U32)VPU_RIU_READ_WORD(((u32Reg)+2)<<1)<<16 ) ) 150 151 #define _VPU_ReadRegBit( u32Reg, u8Mask ) (VPU_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 152 153 #define _VPU_ReadWordBit( u32Reg, u16Mask ) (_VPU_Read2Byte( u32Reg ) & (u16Mask)) 154 155 #define _VPU_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 156 VPU_MACRO_START \ 157 VPU_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (VPU_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 158 (VPU_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 159 VPU_MACRO_END 160 161 #define _VPU_WriteByte( u32Reg, u8Val ) \ 162 VPU_MACRO_START \ 163 VPU_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 164 VPU_MACRO_END 165 166 #define _VPU_Write2Byte( u32Reg, u16Val ) \ 167 VPU_MACRO_START \ 168 if ( ((u32Reg) & 0x01) ) \ 169 { \ 170 VPU_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 171 VPU_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 172 } \ 173 else \ 174 { \ 175 VPU_RIU_WRITE_WORD( ((u32Reg)<<1) , u16Val); \ 176 } \ 177 VPU_MACRO_END 178 179 #define _VPU_Write3Byte( u32Reg, u32Val ) \ 180 if ((u32Reg) & 0x01) \ 181 { \ 182 VPU_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 183 VPU_RIU_WRITE_WORD( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 184 } \ 185 else \ 186 { \ 187 VPU_RIU_WRITE_WORD( (u32Reg) << 1, u32Val); \ 188 VPU_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 189 } 190 191 #define _VPU_Write4Byte( u32Reg, u32Val ) \ 192 VPU_MACRO_START \ 193 if ((u32Reg) & 0x01) \ 194 { \ 195 VPU_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 196 VPU_RIU_WRITE_WORD( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 197 VPU_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 198 } \ 199 else \ 200 { \ 201 VPU_RIU_WRITE_WORD( (u32Reg) <<1 , u32Val); \ 202 VPU_RIU_WRITE_WORD( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 203 } \ 204 VPU_MACRO_END 205 206 #define _VPU_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 207 VPU_MACRO_START \ 208 VPU_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (VPU_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 209 VPU_MACRO_END 210 211 #define _VPU_WriteWordMask( u32Reg, u16Val , u16Msk) \ 212 VPU_MACRO_START \ 213 if ( ((u32Reg) & 0x01) ) \ 214 { \ 215 if ((u16Msk)&0xff00) _VPU_WriteByteMask( ((u32Reg)+1) , (((u16Val) & 0xff00)>>8) , (((u16Msk)&0xff00)>>8) ); \ 216 _VPU_WriteByteMask( (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk)&0x00ff) ); \ 217 } \ 218 else \ 219 { \ 220 VPU_RIU_WRITE_WORD( ((u32Reg)<<1) , (((u16Val) & (u16Msk)) | (_VPU_Read2Byte( u32Reg ) & (~( u16Msk )))) ); \ 221 } \ 222 VPU_MACRO_END 223 224 225 226 //------------------------------------------------------------------------------ 227 // VPU Reg 228 //------------------------------------------------------------------------------ 229 #define REG_VPU_BASE (0x0300) 230 #define REG_MBX_BASE (0x0400) 231 #define REG_MAU1_BASE (0x0400) 232 233 //write back stage PC 234 #define VPU_REG_EXPC_L (REG_VPU_BASE+(0x000a<<1)) 235 #define VPU_REG_EXPC_H (REG_VPU_BASE+(0x000b<<1)) 236 237 #define VPU_REG_CPU_SETTING (REG_VPU_BASE+( 0x0040<<1)) 238 #define VPU_REG_CPU_R2_EN BIT(0) 239 #define VPU_REG_CPU_SW_RSTZ BIT(1) 240 #define VPU_REG_CPU_MIU_SW_RSTZ BIT(2) 241 #define VPU_REG_CPU_RIU_SW_RSTZ BIT(3) 242 #define VPU_REG_CPU_SPI_BOOT BIT(4) 243 #define VPU_REG_CPU_SDRAM_BOOT BIT(5) 244 #define VPU_REG_CPU_R2_INTO BIT(6) 245 #define VPU_REG_CPU_DBG_ON_DCU BIT(8) 246 #define VPU_REG_CPU_DBG_ON_ICU BIT(9) 247 #define VPU_REG_CPU_DBG_CLK_SEL BIT(10) 248 #define VPU_REG_CPU_DBG_CLK_TOGGLE BIT(11) 249 250 #define VPU_REG_ICU_SDR_BASE_L (REG_VPU_BASE+(0x0041<<1)) //byte address 251 #define VPU_REG_ICU_SDR_BASE_H (REG_VPU_BASE+(0x0042<<1)) 252 #define VPU_REG_DCU_SDR_BASE_L (REG_VPU_BASE+(0x0043<<1)) //byte address 253 #define VPU_REG_DCU_SDR_BASE_H (REG_VPU_BASE+(0x0044<<1)) 254 255 #define VPU_REG_SPI_BASE (REG_VPU_BASE+(0x0048<<1)) //REG ACCESS BASE32 256 257 258 #define VPU_REG_IQMEM_BASE_L (REG_VPU_BASE+(0x0049<<1)) 259 #define VPU_REG_IQMEM_BASE_H (REG_VPU_BASE+(0x004a<<1)) 260 #define VPU_REG_IQMEM_MASK_L (REG_VPU_BASE+(0x004b<<1)) 261 #define VPU_REG_IQMEM_MASK_H (REG_VPU_BASE+(0x004c<<1)) 262 263 #define VPU_REG_DQMEM_BASE_L (REG_VPU_BASE+(0x004d<<1)) 264 #define VPU_REG_DQMEM_BASE_H (REG_VPU_BASE+(0x004e<<1)) 265 #define VPU_REG_DQMEM_MASK_L (REG_VPU_BASE+(0x004f<<1)) 266 #define VPU_REG_DQMEM_MASK_H (REG_VPU_BASE+(0x0050<<1)) 267 268 #define VPU_REG_PQMEM_BASE_L (REG_VPU_BASE+(0x0051<<1)) 269 #define VPU_REG_PQMEM_BASE_H (REG_VPU_BASE+(0x0052<<1)) 270 #define VPU_REG_PQMEM_MASK_L (REG_VPU_BASE+(0x0053<<1)) 271 #define VPU_REG_PQMEM_MASK_H (REG_VPU_BASE+(0x0054<<1)) 272 #define VPU_REG_IQMEM_SETTING (REG_VPU_BASE+(0x0064<<1)) 273 #define VPU_REG_VQMEM_BASE_L (REG_VPU_BASE+(0x0067<<1)) 274 #define VPU_REG_VQMEM_BASE_H (REG_VPU_BASE+(0x0068<<1)) 275 #define VPU_REG_VQMEM_MASK_L (REG_VPU_BASE+(0x0069<<1)) 276 #define VPU_REG_VQMEM_MASK_H (REG_VPU_BASE+(0x006a<<1)) 277 #define VPU_REG_QMEM_OWNER (REG_VPU_BASE+(0x006c<<1)) 278 279 #define VPU_REG_IO0_BASE (REG_VPU_BASE+(0x0045<<1)) //RIU 280 #define VPU_REG_IO1_BASE (REG_VPU_BASE+(0x0055<<1)) //R2 internal UART 281 #define VPU_REG_IO2_BASE (REG_VPU_BASE+(0x0056<<1)) //R2 read SPI 282 #define VPU_REG_IO3_BASE (REG_VPU_BASE+(0x0057<<1)) //IP use 283 #define VPU_REG_CONTROL_SET (REG_VPU_BASE+(0x0058<<1)) 284 #define VPU_REG_IO0_EN BIT(0) //default Enable 285 #define VPU_REG_IO1_EN BIT(1) //default Enable 286 #define VPU_REG_IO2_EN BIT(2) 287 #define VPU_REG_IO3_EN BIT(3) 288 #define VPU_REG_QMEM_SPACE_EN BIT(4) 289 #define VPU_REG_MMU_IO_EN BIT(5) 290 #define VPU_REG_WMB_FORCE_OFF BIT(6) 291 #define VPU_REG_WMB_AUTO_OFF BIT(7) 292 #define VPU_REG_PQMEM_SPACE_EN BIT(13) 293 #define VPU_REG_VQMEM_SPACE_EN BIT(14) 294 295 296 #define VPU_REG_VERSION (REG_MBX_BASE+(0x0055<<1)) 297 298 #define VPU_REG_HI_MBOX0_L (REG_MBX_BASE+(0x005b<<1)) 299 #define VPU_REG_HI_MBOX0_H (REG_MBX_BASE+(0x005c<<1)) 300 #define VPU_REG_HI_MBOX1_L (REG_MBX_BASE+(0x005d<<1)) 301 #define VPU_REG_HI_MBOX1_H (REG_MBX_BASE+(0x005e<<1)) 302 303 #define VPU_REG_HI_MBOX_SET (REG_MBX_BASE+(0x005f<<1)) 304 #define VPU_REG_HI_MBOX0_SET BIT(0) 305 #define VPU_REG_HI_MBOX1_SET BIT(1) 306 307 #define VPU_REG_RISC_MBOX_CLR (REG_MBX_BASE+(0x0067<<1)) 308 #define VPU_REG_RISC_MBOX0_CLR BIT(0) 309 #define VPU_REG_RISC_MBOX1_CLR BIT(1) 310 #define VPU_REG_RISC_ISR_CLR BIT(2) 311 #define VPU_REG_RISC_ISR_MSK BIT(6) 312 #define VPU_REG_RISC_ISR_FORCE BIT(10) 313 314 #define VPU_REG_RISC_MBOX_RDY (REG_MBX_BASE+( 0x0068<<1)) 315 #define VPU_REG_RISC_MBOX0_RDY BIT(0) 316 #define VPU_REG_RISC_MBOX1_RDY BIT(1) 317 #define VPU_REG_RISC_ISR_VALID BIT(2) 318 319 #define VPU_REG_HI_MBOX_RDY (REG_MBX_BASE+(0x0069<<1)) 320 #define VPU_REG_HI_MBOX0_RDY BIT(0) 321 #define VPU_REG_HI_MBOX1_RDY BIT(1) 322 323 #define VPU_REG_RISC_MBOX0_L (REG_MBX_BASE+(0x006b<<1)) 324 #define VPU_REG_RISC_MBOX0_H (REG_MBX_BASE+(0x006c<<1)) 325 #define VPU_REG_RISC_MBOX1_L (REG_MBX_BASE+(0x006d<<1)) 326 #define VPU_REG_RISC_MBOX1_H (REG_MBX_BASE+(0x006e<<1)) 327 328 329 330 331 #define MAU1_MIU_SEL (REG_MAU1_BASE+(0x0001<<1)) 332 333 334 335 #define MAU1_CPU_RST (REG_MAU1_BASE+(0x0002<<1)) 336 #define MAU1_REG_SW_RESET BIT(0) 337 338 #define MAU1_ARB0_DBG0 (REG_MAU1_BASE+(0x0008<<1)) 339 #define MAU1_ARB1_DBG0 (REG_MAU1_BASE+(0x000a<<1)) 340 #define MAU1_FSM_CS_MASK BMASK(13:9) 341 #define MAU1_FSM_CS_IDLE BITS(13:9, 1) 342 343 344 //------------------------------------------------------------------------------ 345 // MOBF Reg 346 //------------------------------------------------------------------------------ 347 348 #define MAU1_REG_MIU_RW_TAG1 (REG_MAU1_BASE+(0x0010<<1)) //[7:0]=> read index, [15:8]=> write index 349 #define MAU1_REG_REGION_MASK0_L (REG_MAU1_BASE+(0x0013<<1)) 350 #define MAU1_REG_REGION_MASK0_H (REG_MAU1_BASE+(0x0014<<1)) 351 #define MAU1_REG_REGION_START0_L (REG_MAU1_BASE+(0x0015<<1)) 352 #define MAU1_REG_REGION_START0_H (REG_MAU1_BASE+(0x0016<<1)) 353 #define MAU1_REG_REGION_END0_L (REG_MAU1_BASE+(0x0017<<1)) 354 #define MAU1_REG_REGION_END0_H (REG_MAU1_BASE+(0x0018<<1)) 355 #define MAU1_REG_REGION_MASK1_L (REG_MAU1_BASE+(0x0019<<1)) 356 #define MAU1_REG_REGION_MASK1_H (REG_MAU1_BASE+(0x001a<<1)) 357 #define MAU1_REG_REGION_START1_L (REG_MAU1_BASE+(0x001b<<1)) 358 #define MAU1_REG_REGION_START1_H (REG_MAU1_BASE+(0x001c<<1)) 359 #define MAU1_REG_REGION_END1_L (REG_MAU1_BASE+(0x001d<<1)) 360 #define MAU1_REG_REGION_END1_H (REG_MAU1_BASE+(0x001e<<1)) 361 362 #define MAU1_REG_REGION_EN (REG_MAU1_BASE+(0x001f<<1)) 363 #define MAU1_REG_REGION0_EN BIT(0) 364 #define MAU1_REG_REGION1_EN BIT(1) 365 366 367 //------------------------------------------------------------------------------ 368 // ChipTop Reg 369 //------------------------------------------------------------------------------ 370 371 #define CHIPTOP_REG_BASE (0x1E00 ) 372 #define CLKGEN0_REG_BASE (0x0B00 ) 373 374 #define REG_TOP_VPU (CLKGEN0_REG_BASE+(0x0030<<1)) 375 #define TOP_CKG_VPU_MASK BMASK(3:0) 376 #define TOP_CKG_VPU_DIS BIT(0) 377 #define TOP_CKG_VPU_INV BIT(1) 378 #define TOP_CKG_VPU_CLK_MASK BMASK(3:2) 379 380 //------------------------------------------------------------------------------ 381 // MIU Reg 382 //------------------------------------------------------------------------------ 383 //------------------------------------------------------------------------------ 384 // MIU Reg 385 //------------------------------------------------------------------------------ 386 #define MIU0_REG_HVD_BASE (0x1200) 387 #define MIU1_REG_HVD_BASE (0x0600) 388 389 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1)) 390 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1)) 391 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1)) 392 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1)) 393 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) 394 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1)) 395 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1)) 396 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1)) 397 398 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1)) 399 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1)) 400 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1)) 401 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) 402 403 404 //------------------------------------------------------------------------------------------------- 405 // Type and Structure 406 //------------------------------------------------------------------------------------------------- 407 408 409 410 411 #endif // _REG_VPU_H_ 412 413