1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 #ifndef __M4VD_MSG_QUE_H__ 79 #define __M4VD_MSG_QUE_H__ 80 81 82 #if defined(SUPPORT_NEW_MEM_LAYOUT) 83 #if defined(SUPPORT_EVD) && (1==SUPPORT_EVD) 84 #define OFFSET_BASE 0x000b0000 85 #else 86 #define OFFSET_BASE 0x000a0000 87 #endif 88 #else 89 #define OFFSET_BASE 0x000e0000 90 #endif 91 #define VSYNC_BRIGE_SHM_OFFSET 0x1FA00 92 93 #define FW_VOL_INFO_START (0x000+OFFSET_BASE) 94 #define DEBUG_BUF_START (0x500+OFFSET_BASE) 95 #define FW_FRAME_INFO_START (0x1000+OFFSET_BASE) 96 #define FW_DIVX_INFO_START (0x2000+OFFSET_BASE) 97 #define DEC_FRMAE_INFO_START (0x14300+OFFSET_BASE) 98 #define VSYNC_BRIGE_SHM_START (VSYNC_BRIGE_SHM_OFFSET+OFFSET_BASE) 99 100 #define MVD_DRAM_SIZE 0x40000 // MVD DRAM heap size, 256k 101 102 /* 103 Share Memory layout 104 105 | FW_VOL_INFO | DEBUG_BUF | FW_FRAME_INFO | FW_DIVX_INFO | USERDATABUF | SLQBUF | PTSTBL | DSADDR | SCALER_INFO | DEC_FRMAE_INFO | 106 0 500 1000 2000 3000 B000 B200 13200 14200 14300 14400 (+OFFSET_BASE) 107 108 */ 109 110 // VC1_SEQ_INFO put on 65K 111 #define FW_VERSION 0x08043655 112 #define INTERFACE_VERSION 0x00000347 //ver.347 add PVR target information 113 #define EN_SECTION_START 0x20000000 114 115 typedef struct _FW_VOL_INFO 116 { 117 //VOL infomation 118 unsigned short vol_info; //0 119 // D[5] short_video_header; //1 120 // D[4] vol_interlaced; 121 // D[3] vol_qpel; 122 // D[2] vol_rsync_marker_disable; 123 // D[1] vol_dp_enable; 124 // D[0] vol_rvlc_enable; 125 unsigned short sprite_usage; //2 126 127 unsigned int width; //4 128 unsigned int height; //8 129 130 unsigned short pts_incr; //12 131 unsigned short reserved0; //14 132 133 unsigned char aspect_ratio; //16 134 unsigned char progressive_sequence; //17 135 unsigned char mpeg1; //18 136 unsigned char play_mode; //19 137 138 unsigned char mpeg_frc_mode; //20 139 unsigned char first_display; //21 140 unsigned char low_delay; //22 141 unsigned char video_range; //23 142 143 unsigned int bit_rate; //24 144 145 unsigned short vol_time_incr_res; //28 146 unsigned short fixed_vop_time_incr; //30 // 0: not fixed_vop_rate others : vop_time_incr 147 148 unsigned char par_width; //32 149 unsigned char par_height; //33 150 unsigned char reserved1; //34 151 unsigned char reserved2; //35 152 153 unsigned int vc1_frame_rate; //36 154 unsigned int frame_rate; //40 155 156 unsigned char key_gen[32]; //44 157 158 unsigned char ds_enable; //76 159 unsigned char reserved3; //77 160 unsigned short CropBottom; //78 // For HDMI 3D Output mode. 161 162 unsigned int DSbufsize; //80 163 unsigned char suspend_ds; //84 164 unsigned char reserved4[3]; //85 165 }FW_VOL_INFO,*pFW_VOL_INFO;//16 byte 166 167 #define OFFSET_VOL_INFO 0 168 #define OFFSET_SPRITE_USAGE 2 169 #define OFFSET_WIDTH 4 170 #define OFFSET_HEIGHT 8 171 #define OFFSET_PTS_INCR 12 172 #define OFFSET_RESERVED0 14 173 #define OFFSET_ASPECT_RATIO 16 174 #define OFFSET_PROGRESSIVE_SEQUENCE 17 175 #define OFFSET_MPEG1 18 176 #define OFFSET_PLAY_MODE 19 177 #define OFFSET_MPEG_FRC_MODE 20 178 #define OFFSET_FIRST_DISPLAY 21 179 #define OFFSET_LOW_DELAY 22 180 #define OFFSET_VIDEO_RANGE 23 181 #define OFFSET_BIT_RATE 24 182 #define OFFSET_VOL_TIME_INCR_RES 28 183 #define OFFSET_FIXED_VOP_TIME_INCR 30 184 #define OFFSET_PAR_WIDTH 32 185 #define OFFSET_PAR_HEIGHT 33 186 #define OFFSET_VC1_FRAME_RATE 36 187 #define OFFSET_FRAME_RATE 40 188 #define OFFSET_KEY_GEN 44 189 #define OFFSET_DS_ENABLE 76 190 #define OFFSET_CROPBOTTOM 78 191 #define OFFSET_DSBUFSIZE 80 192 #define OFFSET_SUSPEND_DS 84 193 194 typedef struct 195 { 196 union 197 { 198 struct 199 { 200 unsigned int mvdcmd_handshake_pause : 1; // 1 for handshake ready with CMD_PAUSE, 201 unsigned int mvdcmd_handshake_slq_reset : 1; // 1 for handshake ready with CMD_VC1_HW_SLQ_RESET 202 unsigned int mvdcmd_handshake_stop : 1; // 1 for handshake ready with CMD_STOP 203 unsigned int mvdcmd_handshake_skip_data : 1; // 1 for handshake ready with CMD_SKIP_DATA 204 unsigned int mvdcmd_handshake_skip_to_pts : 1; // 1 for handshake ready with CMD_SKIP_TO_PTS 205 unsigned int mvdcmd_handshake_single_step : 1; // 1 for handshake ready with CMD_SINGLE_STEP 206 unsigned int mvdcmd_handshake_scaler_data_ready : 1; 207 unsigned int mvdcmd_handshake_get_nextdispfrm_ready : 1; // for Mstreamer mode 208 unsigned int mvdcmd_handshake_parser_rst : 1; // 1 for handshake done with CMD_PTS_TBL_RESET 209 unsigned int mvdcmd_handshake_cc608_rst : 1; // "0" for handshake done with mstar cc608 210 unsigned int mvdcmd_handshake_cc708_rst : 1; // "0" for handshake done with mstar cc708 211 unsigned int mvdcmd_handshake_fast_rst : 1; // 1 for handshake done with CMD_FAST_RST, 1 for fast_rst_done... 212 unsigned int mvdcmd_handshake_detatch : 1; // 1 for handshake ready with exit main loop 213 unsigned int mvdcmd_handshake_pvr_seamless_mode : 1; // 1 for handshake ready 214 unsigned int mvdcmd_handshake_reserved : 18; // reserved for extend 215 }; 216 unsigned int value; 217 }; 218 }MVD_CMD_HANDSHADE_INDEX; 219 220 typedef struct 221 { 222 union 223 { 224 struct 225 { 226 unsigned int mvd_xc_disable_black_screen : 1; // 1 for XC disable the black screen, defaule is "0"... 227 unsigned int mvd_xc_release_force_rbank : 1; // 1 for XC release force read bank, defaule is "0"... 228 unsigned int mvd_xc_release_bob_mode : 1; // 1 for XC release BOB mode, defaule is "0"... 229 unsigned int mvd_xc_release_UCNR : 1; // 1 for XC release UCNR, defaule is "0"... 230 unsigned int mvd_xc_reserved : 28; // reserved for extend 231 }; 232 unsigned int value; 233 }; 234 }MVD_XC_LOW_DELAY_INT_STATE; 235 236 typedef struct _FW_FRAME_INFO 237 { 238 unsigned int frame_count; //0 239 unsigned int slq_tbl_rptr; //4 // ==>ms 240 unsigned int vol_update; //8 241 unsigned int error_code; //12 242 243 unsigned int error_status; //16 244 unsigned int skip_frame_count; //20 245 unsigned int picture_type; //24 // 0:I frame 1:P frame 2:B frame 246 unsigned int slq_sw_index; //28 247 248 unsigned char fb_index; //32 249 unsigned char top_ff; //33 250 unsigned char repeat_ff; //34 251 unsigned char invalidstream; //35 252 unsigned int vld_err_count; //36 253 unsigned short tmp_ref; //40 254 unsigned char first_frame; //42 255 unsigned char first_I_found; //43 256 unsigned int gop_i_fcnt; //44 257 258 unsigned int gop_p_fcnt; //48 259 unsigned int gop_b_fcnt; //52 260 unsigned int overflow_count; //56 261 unsigned int time_incr; //60 262 263 unsigned int self_rst_count; //64 264 unsigned int sw_vd_count; //68 265 unsigned int step_disp_done; //72 266 unsigned int step_to_pts_done; //76 267 268 MVD_CMD_HANDSHADE_INDEX cmd_handshake_index; //80 269 unsigned int last_frame_show_done; //84 270 unsigned int meet_file_end_sc; //88 271 unsigned int rcv_payload_lenth; //92 272 273 unsigned int firmware_version; //96 274 unsigned int ic_version; //100 275 unsigned int interface_version; //104 276 unsigned char color_primaries; //108 277 unsigned char transfer_char; //109 278 unsigned char matrix_coef; //110 279 unsigned char video_format; //111 280 281 unsigned short disp_h_size; //112 282 unsigned short disp_v_size; //114 283 unsigned char time_code_hours; //116 284 unsigned char time_code_minutes; //117 285 unsigned char time_code_seconds; //118 286 unsigned char time_code_pictures; //119 287 unsigned char drop_frame_flag; //120 288 unsigned char time_code_hours_disp; //121 289 unsigned char time_code_minutes_disp; //122 290 unsigned char time_code_seconds_disp; //123 291 unsigned char time_code_pictures_disp; //124 292 unsigned char drop_frame_flag_disp; //125 293 unsigned char PicStruct; //126 294 unsigned char chroma_format; //127 295 296 int pts_stc; //128 297 unsigned int displayed_cnt; //132 298 unsigned int next_pts; //136 299 unsigned short centre_h_offset; //140 300 unsigned short centre_v_offset; //142 301 302 unsigned int int_cnt; //144 303 unsigned int disp_pts; //148 // pts of current displayed frame 304 unsigned int high32_pts; //152 // msb of 33-bit pts 305 unsigned char dispQnum; //156 306 unsigned char CurrentESBufferStatus; //157 // init:0x00,underflow:0x01,overflow:0x02,normal:0x03 307 unsigned char framebufferresource; //158 // default: 0, ok: 1, fail : 2 308 unsigned char seq_found; //159 309 310 unsigned int divx_ver_5x; //160 // report divx version... 311 unsigned int frame_buf_size; //164 // report real frame buffer size(unit in bytes)... 312 MVD_XC_LOW_DELAY_INT_STATE xc_low_delay_int_state; //168 // for xc low delay interrupt status... 313 unsigned int xc_low_delay_cnt; //172 314 315 unsigned int xc_diff_field_no; //176 // for get XC diff field number... 316 unsigned int xc_low_delay_cnt_latched; //180 // for dbg xc_low_delay timing only... 317 unsigned int drop_count; //184 // for counting that decoded frame who doesn't display 318 319 unsigned int rdptr_pts_low; //188 // for TM14 pts flow control, pts based on pts table read pointer 320 unsigned int rdptr_pts_high; //192 // for TM14 pts flow control, pts based on pts table read pointer 321 unsigned int wrptr_pts_low; //196 // for TM14 pts flow control, pts based on pts table write pointer 322 unsigned int wrptr_pts_high; //200 // for TM14 pts flow control, pts based on pts table write pointer 323 324 unsigned int wait_decode_done_cnt; //204 325 unsigned int wait_seach_buffer_cnt; //208 326 unsigned int wait_search_code_cnt; //212 327 unsigned int wait_pre_buf_cnt; //216 328 unsigned int wait_vfifo_buf_cnt; //220 329 unsigned int wait_search_header_cnt; //224 330 unsigned int wait_flash_pattern_cnt; //228 331 unsigned int pvr_seamless_status; //232 332 333 unsigned int drop_frame_count; //236 334 unsigned int disp_stc; //240 335 336 unsigned int u32PVRSeamlessTargetPTS; //244 337 unsigned char u8PVRSeamlessTargetPTSHigh; //248 338 unsigned char u8PVRSeamlessTargetFrameType; //249 339 unsigned char reserved[2]; //250 340 341 }FW_FRAME_INFO, *pFW_FRAME_INFO; 342 343 #define OFFSET_FRAME_COUNT 0 344 #define OFFSET_SLQ_TBL_RPTR 4 345 #define OFFSET_VOL_UPDATE 8 346 #define OFFSET_ERROR_CODE 12 347 #define OFFSET_ERROR_STATUS 16 348 #define OFFSET_SKIP_FRAME_COUNT 20 349 #define OFFSET_PICTURE_TYPE 24 350 #define OFFSET_SLQ_SW_INDEX 28 351 #define OFFSET_FB_INDEX 32 352 #define OFFSET_TOP_FF 33 353 #define OFFSET_REPEAT_FF 34 354 #define OFFSET_INVALIDSTREAM 35 355 #define OFFSET_VLD_ERR_COUNT 36 356 #define OFFSET_TMP_REF 40 357 #define OFFSET_FIRST_FRAME 42 358 #define OFFSET_FIRST_I_FOUND 43 359 #define OFFSET_GOP_I_FCNT 44 360 #define OFFSET_GOP_P_FCNT 48 361 #define OFFSET_GOP_B_FCNT 52 362 #define OFFSET_OVERFLOW_COUNT 56 363 #define OFFSET_TIME_INCR 60 364 #define OFFSET_SELF_RST_COUNT 64 365 #define OFFSET_SW_VD_COUNT 68 366 #define OFFSET_STEP_DISP_DONE 72 367 #define OFFSET_STEP_TO_PTS_DONE 76 368 #define OFFSET_CMD_HANDSHAKE_INDEX 80 369 #define OFFSET_CMD_LAST_FRAME_SHOW 84 370 #define OFFSET_MEET_FILE_END_SC 88 371 #define OFFSET_RCV_PAYLOAD_LENGTH 92 372 #define OFFSET_FIRMWARE_VERSION 96 373 #define OFFSET_IC_VERSION 100 374 #define OFFSET_INTERFACE_VERSION 104 375 #define OFFSET_COLOR_PRIMARIES 108 376 #define OFFSET_TRANSFER_CHAR 109 377 #define OFFSET_MATRIX_COEF 110 378 #define OFFSET_VIDEO_FORMAT 111 379 #define OFFSET_DISP_H_SIZE 112 380 #define OFFSET_DISP_V_SIZE 114 381 #define OFFSET_TIME_CODE_HOURS 116 // for decoding frame 382 #define OFFSET_TIME_CODE_MINUTES 117 // for decoding frame 383 #define OFFSET_TIME_CODE_SECONDS 118 // for decoding frame 384 #define OFFSET_TIME_CODE_PICTURES 119 // for decoding frame 385 #define OFFSET_DROP_FRAME_FLAG 120 // for decoding frame 386 #define OFFSET_TIME_CODE_HOURS_DISP 121 // for displaying frame 387 #define OFFSET_TIME_CODE_MINUTES_DISP 122 // for displaying frame 388 #define OFFSET_TIME_CODE_SECONDS_DISP 123 // for displaying frame 389 #define OFFSET_TIME_CODE_PICTURES_DISP 124 // for displaying frame 390 #define OFFSET_DROP_FRAME_FLAG_DISP 125 // for displaying frame 391 #define OFFSET_PICTURE_STRUCTURE 126 392 #define OFFSET_CHROMA_FORMAT 127 393 #define OFFSET_PTS_STC 128 // integer, pts_stc(n)=pts(n)-stc(n) 394 #define OFFSET_DISPLAYED_CNT 132 395 #define OFFSET_NEXT_PTS 136 396 #define OFFSET_CENTRE_H_OFFSET 140 397 #define OFFSET_CENTRE_V_OFFSET 142 398 #define OFFSET_INT_CNT 144 399 #define OFFSET_DISP_PTS 148 400 #define OFFSET_DISP_PTS_MSB 152 401 #define OFFSET_DISPQ_NUM 156 402 #define OFFSET_CURRENT_ES_BUFFER_STATUS 157 403 #define OFFSET_FRAME_BUFFER_RESOURCE 158 404 #define OFFSET_SEQ_FOUND 159 405 #define OFFSET_DIVX_VER_5X 160 406 #define OFFSET_FRAME_BUF_SIZE 164 // report real frame buffer size(unit in bytes)... 407 #define OFFSET_XC_LOW_DELAY_INT_STATE 168 // for xc low delay interrupt status... 408 #define OFFSET_XC_LOW_DELAY_CNT 172 // for xc low delay interrupt status... 409 #define OFFSET_XC_DIFF_FIELD_NO 176 // for get XC diff field number... 410 #define OFFSET_XC_LOW_DELAY_CNT_LATCH 180 // for dbg xc_low_delay timing only... 411 #define OFFSET_DROP_COUNT 184 // for counting that decoded frame who doesn't display 412 #define OFFSET_RDPTR_PTS_LOW 188 413 #define OFFSET_RDPTR_PTS_HIGH 192 414 #define OFFSET_WRPTR_PTS_LOW 196 415 #define OFFSET_WRPTR_PTS_HIGH 200 416 417 #define OFFSET_DECODEDONE_COUNT 204 418 #define OFFSET_SEARCHBUF_COUNT 208 419 #define OFFSET_SEARCHCODE_COUNT 212 420 #define OFFSET_PREBUF_COUNT 216 421 #define OFFSET_VFIFOBUF_COUNT 220 422 #define OFFSET_SEARCHHEADER_COUNT 224 423 #define OFFSET_FLASHPATTERN_COUNT 228 424 #define OFFSET_PVR_SEAMLESS_STATUS 232 425 #define OFFSET_DROP_FRAME_COUNT 236 426 #define OFFSET_DISP_STC 240 427 #define OFFSET_PVRSEAMLESSTARGETPTS 244 428 #define OFFSET_PVRSEAMLESSTARGETPTSHIGH 248 429 #define OFFSET_PVRSEAMLESSTARGETFRAMETYPE 249 430 431 432 433 434 435 typedef struct _FW_DIVX_INFO 436 { 437 unsigned int vol_handle_done; //0 438 439 unsigned int width; //4 440 unsigned int height; //8 441 unsigned int frame_count; //12 442 unsigned int frame_time; //16 443 444 unsigned short pts_incr; //20 445 unsigned short reserve0; 446 447 unsigned char aspect_ratio; //24 448 unsigned char progressive_sequence; //25 449 unsigned char mpeg1; //26 450 unsigned char play_mode; //27 451 452 unsigned char mpeg_frc_mode; //28 453 unsigned char invalidstream; //29 454 unsigned char reserve[2]; //30 455 unsigned int frame_rate; //32 456 }FW_DIVX_INFO, *pFW_DIVX_INFO; 457 458 #define OFFSET_DIVX_VOL_HANDLE_DONE 0 459 #define OFFSET_DIVX_WIDTH 4 460 #define OFFSET_DIVX_HEIGHT 8 461 #define OFFSET_DIVX_FRAME_COUNT 12 462 #define OFFSET_DIVX_FRAME_TIME 16 463 #define OFFSET_DIVX_PTS_INCR 20 464 #define OFFSET_DIVX_RESERVE0 22 465 #define OFFSET_DIVX_ASPECT_RATIO 24 466 #define OFFSET_DIVX_PROGRESSIVE_SEQUENCE 25 467 #define OFFSET_DIVX_MPEG1 26 468 #define OFFSET_DIVX_PLAY_MODE 27 469 #define OFFSET_DIVX_MPEG_FRC_MODE 28 470 #define OFFSET_DIVX_INVALIDSTREAM 29 471 #define OFFSET_DIVX_RESERVED 30 472 #define OFFSET_DIVX_FRAME_RATE 32 473 474 #define STATUS_VIDEO_SYNC (1<<0) 475 #define STATUS_VIDEO_FREERUN (1<<1) 476 #define STATUS_VIDEO_SKIP (1<<2) 477 #define STATUS_VIDEO_REPEAT (1<<3) 478 479 typedef struct _FW_USER_DATA_BUF 480 { 481 unsigned char picType; /* picture type: 1->I picture, 2->P,3->B */ 482 unsigned char top_ff; /* Top field first: 1 if top field first*/ 483 unsigned char rpt_ff; /* Repeat first field: 1 if repeat field first*/ 484 unsigned char userdatabytecnt; 485 486 unsigned short tmpRef; /* Temporal reference of the picture*/ 487 488 unsigned char userdata[250]; 489 }FW_USER_DATA_BUF,*pFW_USER_DATA_BUF; 490 491 #define FW_USER_DATA_BUF_EXT_PACK_LEN 240 492 typedef struct _FW_USER_DATA_BUF_EXT 493 { 494 unsigned char picType; /* picture type: 1->I picture, 2->P,3->B */ 495 unsigned char top_ff; /* Top field first: 1 if top field first*/ 496 unsigned char rpt_ff; /* Repeat first field: 1 if repeat field first*/ 497 unsigned char userdatabytecnt; 498 499 unsigned short tmpRef; /* Temporal reference of the picture*/ 500 unsigned char PicStruct; /* picture struct with this cc pack*/ 501 unsigned char reserved; 502 503 unsigned int pts; /* pts with this cc pack*/ 504 unsigned int reserved2; 505 506 unsigned char userdata[FW_USER_DATA_BUF_EXT_PACK_LEN]; 507 }FW_USER_DATA_BUF_EXT,*pFW_USER_DATA_BUF_EXT; 508 509 typedef struct _DecFrameInfo 510 { 511 unsigned int u32DecLumaAddr; //0 512 unsigned int u32DecChromaAddr; //4 513 unsigned int u32DecTimeStamp; //8 514 unsigned int u32DecID_L; //12 515 unsigned int u32DecID_H; //16 516 unsigned short u16DecPitch; //20 517 unsigned short u16DecWidth; //22 518 unsigned short u16DecHeight; //24 519 unsigned short u16DeceFrameType; //26 520 unsigned int u32DispLumaAddr; //28 521 unsigned int u32DispChromaAddr; //32 522 unsigned int u32DispTimeStamp; //36 523 unsigned int u32DispID_L; //40 524 unsigned int u32DispID_H; //44 525 unsigned short u16DispPitch; //48 526 unsigned short u16DispWidth; //50 527 unsigned short u16DispHeight; //52 528 unsigned short u16DispeFrameType; //54 529 // for Mstreamer mode 530 unsigned int u32NextDispLumaAddr; //56 531 unsigned int u32NextDispChromaAddr; //60 532 unsigned int u32NextDispTimeStamp; //64 533 unsigned int u32NextDispID_L; //68 534 unsigned int u32NextDispID_H; //72 535 unsigned short u16NextDispPitch; //76 536 unsigned short u16NextDispWidth; //78 537 unsigned short u16NextDispHeight; //80 538 unsigned short u16NextDispeFrameType; //82 539 unsigned short u16NextDispFrameIdx; //84 540 // for vc1/rcv range reduction 541 unsigned char u8NextDispRangeRed_Y; //86 //[7]: on/off [6:0]: scale 542 unsigned char u8NextDispRangeRed_UV; //87 //[7]: on/off [6:0]: scale 543 // for MCU mode, which support interlace 544 unsigned short u16ExtData; //88 545 }DecFrameInfo, *pDecFrameInfo; 546 547 #define OFFSET_DECFRAMEINFO_DEC_LUMAADDR 0 548 #define OFFSET_DECFRAMEINFO_DEC_CHROMAADDR 4 549 #define OFFSET_DECFRAMEINFO_DEC_TIMESTAMP 8 550 #define OFFSET_DECFRAMEINFO_DEC_ID_L 12 551 #define OFFSET_DECFRAMEINFO_DEC_ID_H 16 552 #define OFFSET_DECFRAMEINFO_DEC_PITCH 20 553 #define OFFSET_DECFRAMEINFO_DEC_WIDTH 22 554 #define OFFSET_DECFRAMEINFO_DEC_HEIGHT 24 555 #define OFFSET_DECFRAMEINFO_DEC_FRAMETYPE 26 556 #define OFFSET_DECFRAMEINFO_DISP_LUMAADDR 28 557 #define OFFSET_DECFRAMEINFO_DISP_CHROMAADDR 32 558 #define OFFSET_DECFRAMEINFO_DISP_TIMESTAMP 36 559 #define OFFSET_DECFRAMEINFO_DISP_ID_L 40 560 #define OFFSET_DECFRAMEINFO_DISP_ID_H 44 561 #define OFFSET_DECFRAMEINFO_DISP_PITCH 48 562 #define OFFSET_DECFRAMEINFO_DISP_WIDTH 50 563 #define OFFSET_DECFRAMEINFO_DISP_HEIGHT 52 564 #define OFFSET_DECFRAMEINFO_DISP_FRAMETYPE 54 565 #define OFFSET_DECFRAMEINFO_NEXTDISP_LUMAADDR 56 // for Mstreamer mode 566 #define OFFSET_DECFRAMEINFO_NEXTDISP_CHROMAADDR 60 567 #define OFFSET_DECFRAMEINFO_NEXTDISP_TIMESTAMP 64 568 #define OFFSET_DECFRAMEINFO_NEXTDISP_ID_L 68 569 #define OFFSET_DECFRAMEINFO_NEXTDISP_ID_H 72 570 #define OFFSET_DECFRAMEINFO_NEXTDISP_PITCH 76 571 #define OFFSET_DECFRAMEINFO_NEXTDISP_WIDTH 78 572 #define OFFSET_DECFRAMEINFO_NEXTDISP_HEIGHT 80 573 #define OFFSET_DECFRAMEINFO_NEXTDISP_FRAMETYPE 82 574 #define OFFSET_DECFRAMEINFO_NEXTDISP_FRAMEIDX 84 // for Mstreamer mode 575 #define OFFSET_DECFRAMEINFO_NEXTDISP_RANGERED_Y 86 // for vc1/rcv 576 #define OFFSET_DECFRAMEINFO_NEXTDISP_RANGERED_UV 87 // for vc1/rcv 577 #define OFFSET_DECFRAMEINFO_NEXTDISP_EXT_DATA 88 // for MCU mode, which support interlace 578 579 typedef struct _DEBUG_INFO 580 { 581 // 582 volatile unsigned short max_coded_width; 583 volatile unsigned short max_coded_height; 584 volatile unsigned short sync_status; // defined by AV_SYNC 585 586 volatile unsigned short REG67; 587 volatile unsigned short REG68; 588 volatile unsigned short REG69; 589 590 volatile unsigned short REG6a; 591 volatile unsigned short REG6b; 592 volatile unsigned short REG6c; 593 594 volatile unsigned short REG6d; 595 volatile unsigned short REG6e; 596 volatile unsigned short REG6f; 597 598 // 599 volatile unsigned short overflow_count; 600 volatile unsigned short underflow_count; 601 volatile unsigned short vlderr_count; 602 volatile unsigned short frame_conut;//0 603 604 volatile unsigned int y_start_addr; //in byte unit 605 volatile unsigned int uv_start_addr;//in byte unit 606 607 volatile unsigned int width; 608 volatile unsigned int height; 609 610 // where 611 volatile unsigned short mb_x; 612 volatile unsigned short mb_y; 613 614 volatile unsigned short file_end; 615 //16-byte aligned 616 volatile unsigned char reserved[24]; 617 618 }DebugInfo; 619 620 typedef struct VC1_SEQ_INFO 621 { 622 volatile unsigned int PROFILE; 623 volatile unsigned int FRMRTQ_POSTPROC; 624 volatile unsigned int BITRTQ_POSTPROC; 625 volatile unsigned int LOOPFILTER; 626 volatile unsigned int MULTIRES; 627 volatile unsigned int FASTUVMC; 628 volatile unsigned int EXTENDED_MV; 629 volatile unsigned int DQUANT; 630 volatile unsigned int VSTRANSFORM; 631 volatile unsigned int OVERLAP; 632 volatile unsigned int SYNCMARKER; 633 volatile unsigned int RANGERED; 634 volatile unsigned int MAXBFRAMES; 635 volatile unsigned int QUANTIZER; 636 volatile unsigned int FINTERPFLAG; 637 volatile unsigned int LEVEL; 638 volatile unsigned int CBR; 639 volatile unsigned int FRAMERATE; 640 volatile unsigned int VERT_SIZE; 641 volatile unsigned int HORIZ_SIZE; 642 }VC1_SEQUENCE_INFO, *pVC1_SEQUENCE_INFO; 643 644 #define OFFSET_RCV_PROFILE 0 645 #define OFFSET_RCV_FRMRTQ_POSTPROC 4 646 #define OFFSET_RCV_BITRTQ_POSTPROC 8 647 #define OFFSET_RCV_LOOPFILTER 12 648 #define OFFSET_RCV_MULTIRES 16 649 #define OFFSET_RCV_FASTUVMC 20 650 #define OFFSET_RCV_EXTENDED_MV 24 651 #define OFFSET_RCV_DQUANT 28 652 #define OFFSET_RCV_VSTRANSFORM 32 653 #define OFFSET_RCV_OVERLAP 36 654 #define OFFSET_RCV_SYNCMARKER 40 655 #define OFFSET_RCV_RANGERED 44 656 #define OFFSET_RCV_MAXBFRAMES 48 657 #define OFFSET_RCV_QUANTIZER 52 658 #define OFFSET_RCV_FINTERPFLAG 56 659 #define OFFSET_RCV_LEVEL 60 660 #define OFFSET_RCV_CBR 64 661 #define OFFSET_RCV_FRAMERATE 68 662 #define OFFSET_RCV_VERT_SIZE 72 663 #define OFFSET_RCV_HORIZ_SIZE 76 664 665 typedef struct _FW_AVSYNC_TABLE 666 { 667 unsigned int byte_cnt; //0 //23 valid bits 668 unsigned int dummy_cnt; //4 //dummy packet counter 669 unsigned int id_low; //8 //ID specified by player 670 unsigned int id_high; //12 671 672 unsigned int time_stamp; //16 //pts or dts 673 unsigned int reserved_int0; //20 674 unsigned int reserved_int1; //24 675 unsigned int reserved_int2; //28 676 }FW_AVSYNC_TABLE, *pFW_AVSYNC_TABLE; 677 678 #define OFFSET_BYTE_CNT 0 679 #define OFFSET_DUMMY_CNT 4 680 #define OFFSET_ID_LOW 8 681 #define OFFSET_ID_HIGH 12 682 #define OFFSET_TIME_STAMP 16 683 684 #ifdef M4VDPLAYER 685 extern pFW_VOL_INFO gp_vol_info; 686 extern pFW_DIVX_INFO gp_divx_info; 687 #endif 688 689 //interupt flag 690 #define INT_CC_NEW (1<<0) 691 #define INT_USER_DATA (1<<0) 692 #define INT_VBUF_OVF (1<<1) 693 #define INT_VBUF_UNF (1<<2) 694 #define INT_VES_VALID (1<<3) 695 #define INT_VES_INVALID (1<<4) 696 #define INT_SEQ_FOUND (1<<5) 697 #define INT_PIC_FOUND (1<<6) 698 #define INT_DEC_ERR (1<<7) 699 #define INT_FIRST_FRAME (1<<8) 700 #define INT_DISP_RDY (1<<9) 701 #define INT_SYN_SKIP (1<<10) 702 #define INT_SYN_REP (1<<11) 703 #define INT_DISP_VSYNC (1<<12) 704 #define INT_USER_DATA_DISP (1<<13) //user data in display order 705 #define INT_PTS_DISCONTINUE (1<<14) //detection pts discontinue for t3-gp2, 20101214 706 #define INT_DEC_DONE (1<<15) //finishing decoding one frame. 707 #define INT_DEC_I (1<<16) //finishing decoding one frame. 708 #define INT_XC_LOW_DELAY (1<<17) //trigger this interrupt for XC speed up to show image on channel change... 709 710 #define INT_SYN_SKIP_P 10 711 #define INT_SYN_REP_P 11 712 713 // decoding state definition 714 #define DEC_STAT_IDLE 0x00 715 #define DEC_STAT_FIND_SC 0x01 716 #define DEC_STAT_FIND_SPE_SC 0x11 717 #define DEC_STAT_FIND_FRAMEBUFFER 0x02 718 #define DEC_STAT_WAIT_DECODE_DONE 0x03 719 #define DEC_STAT_DECODE_DONE 0x04 720 #define DEC_STAT_WAIT_VDFIFO 0x05 721 #define DEC_STAT_INIT_SUCCESS 0x06 722 723 //error_code 724 #define VOL_SHAPE 1 //error_status 0:rectanglular 1:binary 2: binary only 3: grayscale 725 #define VOL_USED_SPRITE 2 //error_status 0:sprite not used 1:static 2: GMC 3: reserved 726 #define VOL_NOT_8_BIT 3 //error_status : bits per pixel 727 #define VOL_NERPRED_ENABLE 4 728 #define VOL_REDUCED_RES_ENABLE 5 729 #define VOL_SCALABILITY 6 730 #define VOL_OTHER 7 731 #define VOL_H263_ERROR 8 732 #define VOL_RES_NOT_SUPPORT 9 //error_status : none 733 #define VOL_MPEG4_NOT_SUPPORT 10 //error_status : none 734 #define VOL_PROFILE_NOT_SUPPORT 11 735 #define VOL_RCV_ERROR_OCCUR 12 736 #define VOL_VC1_NOT_SUPPORT 13 737 #define VOL_UNKNOW_CODEC_NOT_SUPPORT 14 738 #define VOL_SLQ_TBL_NOT_SUPPORT 15 739 #define VOL_FRAME_BUF_NOT_ENOUGH 16 //error_status : none 740 #define CODEC_MPEG4 0x00 //arg0: 0: mpeg4, 1: mpeg4 with short_video_header, 2: DivX311 741 #define CODEC_MPEG4_SHORT_VIDEO_HEADER 0x01 742 #define CODEC_DIVX311 0x02 743 #define CODEC_MPEG2 0x10 744 typedef enum //arg1: 0: file mode 1:slq 2:live stream mode 3:slqtbl 4: Ts file mode 745 { 746 FILE_MODE = 0, 747 SLQ_MODE, 748 STREAM_MODE, 749 SLQ_TBL_MODE, 750 TS_FILE_MODE, 751 OTHER 752 }stream_type; 753 #define ENABLE_PARSER 0x00 //arg2: 0/1 enable/disable parser; 754 #define DISABLE_PARSER 0x01 755 #define ENABLE_PKT_LEN 0x02 756 #define PARSER_MPEG2 0x00 //arg3: 0 13818-1 pes header; 757 #define PARSER_MPEG1 0x01 // 1 11172-1 pes header; 758 759 #define FrcNormal 0 760 #define FrcDisplayTwice 1 //output rate is twice of input rate (ex. 30p a 60p) 761 #define Frc32Pulldown 2 //3:2 pulldown mode (ex. 24p a 60i or 60p) 762 #define FrcPALtoNTSC 3 //PALaNTSC conversion (50i a 60i) 763 #define FrcNTSCtoPAL 4 //NTSCaPAL conversion (60i a 50i) 764 #define FrcShowOneFiled 5 765 #define FrcDisplayDropHalf 6 766 #define FrcDisplay120To50 7 767 #define FrcDisplay100To60 8 768 #define FrcDisplay30To50 9 769 #define FrcDisplayRepeat51 10 770 #define FrcDisplayDrop51 11 771 #define FrcDisplayDrop52 12 772 #define FrcDisplayDrop53 13 773 #define FrcDisplayMultipleRepeat 20 //output_rate/input_rate=integer 774 #define FrcDisplayGeneralRepeat 21 //output_rate > input_rate, ex. 15->50... 775 #define FrcDisplayGeneralSkip 22 //output_rate < input_rate, 776 777 #define MVD3_FILE_SD_MODE 0x02 //960*544 778 #define MVD3_HD_MODE 0x10 //1920*1088 779 #define MVD3_SD_MODE 0x00 //720*576 780 #define MVD3_DHD_MODE 0x20 // dual HD 781 #define MVD3_DHD_MODE_MIN 0x40 //ECO ISSUE : THE WIDTH OVER 2560 IN VC1 WILL HIT THE HW_ISSUE 782 // File mode avsync related 783 #define NONE_FILE_MODE 0 784 #define FILE_PTS_MODE 1 785 #define FILE_DTS_MODE 2 786 #define FILE_STS_MODE 3 787 788 789 // argument for "CMD_DISPLAY_PAUSE" 790 #define DISPLAY_PAUSE_OFF 0x00 791 #define DISPLAY_PAUSE_ON 0x01 792 793 // argument for "CMD_FRC_DROP_BEHAVIOR" 794 #define FRC_DROP_FRAME 0x00 // for default frc drop behavior, drop per frame 795 #define FRC_DROP_FIELD 0x01 // for frc drop behavior, drop per field to improve more smoothly in field mode 796 797 // ARG0 for "CMD_DRAM_OBF" 798 #define OBF_PAS1_WR 0x01 // for Dram obf write index (Parser1 write) 799 #define OBF_VBUF1_RD 0x02 // for Dram obf read index (VBUF1 read) 800 #define OBF_PES_FILE_IN1_WR 0x03 // for Dram obf read index for PESFI1 801 #define OBF_PAS2_WR 0x04 // for Dram obf write index (Parser2 write) 802 #define OBF_VBUF2_RD 0x05 // for Dram obf read index (VBUF2 read) 803 #define OBF_PES_FILE_IN2_WR 0x06 // for Dram obf read index for PESFI2 804 805 //command interface 806 #define CMD_PLAY 0x01 807 #define CMD_PAUSE 0x02 808 #define CMD_STOP 0x03 809 #define CMD_FIND_SEQ 0x04 //find seq header and set command = pause at picture header start code found 810 #define CMD_SINGLE_STEP 0x05 811 #define CMD_PLAY_NO_SQE 0x06 812 #define CMD_FAST_SLOW 0x07 //arg0: 0: nomarl mode, 1: decode I only, 2: deocde I/P only, 3: slow motion 813 #define CMD_CODEC_INFO 0x08 //arg0: 0: mpeg4, 1: mpeg4 with short_video_header, 2: DivX311 814 #define CMD_SYN_THRESHOLD 0x09 815 #define CMD_SYNC_ON 0x0a 816 #define CMD_SYNC_OFFSET 0x0b 817 #define CMD_DISPLAY_CTL 0x0c 818 //arg0: 0/1-display by display/decode order 819 //arg1: 1-drop display decoding error frame 820 //arg2: 1-drop display when decode fast than display 821 //arg3:set frame rate conversion mode 822 #define CMD_GET_SYNC_STAT 0x0d //return arg0: 0/1 sync off/on ; arg1: 3 sync init done 823 #define CMD_GET_AFD 0x0e 824 #define CMD_SKIP_DATA 0x0f //set to skip all data till find FW_SPE_SCODE to resume normal play 825 826 #define CMD_STREAM_BUF_START 0x10 827 #define CMD_STREAM_BUF_END 0x11 828 #define CMD_FB_BASE 0x12 //Frame buffer base address, from LSB to MSB are arg0, arg1, arg2, arg3 829 #define CMD_IAP_BUF_START 0x13 830 #define CMD_DP_BUF_START 0x14 831 #define CMD_MV_BUF_START 0x15 832 #define CMD_DMA_OVFTH 0x16 833 #define CMD_DMA_UNFTH 0x17 834 #define CMD_VC1_MIU_PROTECT_START 0x18 835 #define CMD_VC1_MIU_PROTECT_END 0x19 836 #define CMD_DISP_SPEED_CTRL 0x1a 837 #define CMD_STEP_DISP_DECODE_ONE 0x1b 838 #define CMD_STEP_DISP_ING 0x1c // repeat disp this frame 839 #define CMD_STEP_TO_PTS 0x1d 840 #define CMD_HANDSHAKE_STATUS 0x1e //report handshake status 841 #define CMD_DISPLAY_PAUSE 0x1f // display pause 842 843 #define CMD_USER_BUF_START 0x20 844 #define CMD_USER_BUF_SIZE 0x21 845 #define CMD_RD_USER_WP 0x22 846 #define CMD_WD_USER_RP 0x23 847 #define CMD_RD_CC_PKTCNT 0x24 848 #define CMD_RD_CC_OV 0x25 849 #define CMD_CLOSE_CC 0x26 850 #define CMD_EN_CC_INFO_ENHANCE 0X27 // arg0=1, for enhance to dump the pts/tmp_ref info with each cc-608 packet for mstar cc-lib, 20120406 851 #define CMD_BUF_OFFSET 0x2d // stream/frame buf offset, programable high adderss [bit-25] that allocate to low/high 256MB MIU:(only for K2) 852 #define CMD_ENABLE_VLD_TIMEOUT 0x2e // enable mvd vld timeout and threshold 853 #define CMD_ENABLE_INT_STAT 0x2f // set which int be enabled 854 855 #define CMD_GET_INT_STAT 0x30 856 #define CMD_PARSE_M4V_PACKMD 0x31 857 #define CMD_RD_PTS 0x32 858 #define CMD_FLUSH_LAST_IPFRAME 0x33 859 #define CMD_DECODE_STATUS 0x34 // arg0 = lastcommand ; arg1 = decode_status 860 #define CMD_VBUFFER_COUNT 0x35 861 #define CMD_START_DEC_STRICT 0x36 // start decoding in First I and skip non reference frame B decoding 862 #define CMD_SW_RESET 0x37 863 #define CMD_MVD_FAST_INT 0x38 864 #define CMD_DIU_WIDTH_ALIGN 0x39 865 #define CMD_SW_IDX_ADJ 0x3a // arg0=1 set sw_index as previous queue index infomation 866 #define CMD_PARSER_READ_POSITION 0x3b 867 #define CMD_REPEAT_MODE 0x3c // arg0=1 when frame display repeat only show one field 868 #define CMD_PTS_BASE 0x3d 869 #define CMD_SKIP_TO_PTS 0x3e 870 #define CMD_AVSYNC_FREERUN_THRESHOLD 0x3f 871 872 #define CMD_DEBUG_BUF_START 0x40 873 #define CMD_DEBUG_CTL 0x42 874 #define CMD_RD_IO 0x43 875 #define CMD_WR_IO 0x44 876 #define CMD_FB_RED_SET 0x45 877 #define CMD_FB_NUM 0x46 878 #define CMD_PTS_DETECTOR_EN 0x47 // enable filter for stream discontinue // to force the pts follow stc when pts=-1 879 #define CMD_PTS_TBL_RESET 0x48 // to reset pas/vld and pts_tbl 880 #define CMD_DRAM_OBF 0x49 // for Dram OBF key setting 881 #define CMD_FP_FILTER 0x4A // 0:1 for disable/enable field polarity tuning filter, 0 for default... 882 #define CMD_PUSH_FIRST_FRAME_DISP 0x4B // 0:1 for disable/enable to push the first I-frame to dispQ when decoded done on ts and ts-file mode, 0 for default(disable)... 883 #define CMD_FAST_RST 0x4C // 1 for enable mvd self reset... 884 #define CMD_RVU_EN 0x4D //open RVU feature 885 886 #define CMD_SLQ_START 0x50 //SLQ start address, from LSB to MSB are arg0, arg1, arg2, arg3 887 #define CMD_SLQ_END 0x51 //SLQ end address, from LSB to MSB are arg0, arg1, arg2, arg3 888 #define CMD_SLQ_AVAIL_LEVEL 0x52 //arg0: 4-0 889 #define CMD_FPGA_COMP 0x53 //arg0: 1/0:enable/disable FPGA comp 890 #define CMD_DIVX_PATCH 0x54 //arg0: D[0] divx mv p interlace chroma adjust 891 #define CMD_HEADER_INFO_BUF 0x55 //header info buffer base address, from LSB to MSB are arg0, arg1, arg2, arg3 892 #define CMD_IDCT_SEL 0x56 // arg0 D[0]:0/1 llm/divx6 D[1]:0/1 unbias/bias rounding mode 893 #define CMD_VOL_INFO_BUF 0x57 894 #define CMD_FRAME_INFO_BUF 0x58 895 #define CMD_CODE_OFFSET 0x59 896 #define CMD_RESET_FRAMECOUNT 0x5a 897 #define CMD_CHIPID 0x5b 898 #define CMD_DEC_FRAME_INFO_BUF 0x5c 899 #define CMD_GET_FW_VERSION 0x5E 900 #define CMD_GET_EN_CATCH_DATA 0x5F 901 902 #define CMD_SLQ_TBL_BUF_START 0x60 903 #define CMD_SLQ_TBL_BUF_END 0x61 904 #define CMD_SLQ_UPDATE_TBL_WPTR 0x62 905 #define CMD_SLQ_GET_TBL_RPTR 0x63 906 907 // FW stop updating frames when vsync, but decoding process is still going. 908 #define CMD_FREEZE_DISP 0x64 909 #define CMD_DS_VIRTUAL_BOX 0x65 910 #define CMD_SHOW_ONE_FIELD 0x66 911 #define CMD_FD_MASK_DELAY_CNT 0x67 // delay n's vsync then active the fd_mask 912 913 #define CMD_UPDATE_FRAME 0x68 // updating next frame in slow motion mode 914 #define CMD_FRC_OUPUT 0x69 915 #define CMD_FRC_DROP_BEHAVIOR 0x6A // arg0: FRC_DROP_FRAME/FRC_DROP_FIELD, default is FRC_DROP_FRAME 916 917 #define CMD_GET_NEXTDISPFRM 0x6B // for Mstreamer mode and mcu mode 918 #define CMD_FLIP_RELEASE_FRAME 0x6C // for Mstreamer mode and mcu mode 919 #define CMD_SEND_UNI_PTS 0x6D // for Mstreamer mode and mcu mode 920 #define CMD_SET_MST_MODE 0x6E // for Mstreamer mode and mcu mode 921 #define CMD_SET_MCU_MODE 0x6F // for mcu mode 922 923 #define CMD_DUMP_BITSTREAM_BASE 0x70 924 #define CMD_DUMP_BITSTREAM_LENGTH 0x71 925 926 #define CMD_XC_LOW_DELAY_PARA 0x72 // set the parameter for XC_low_delay mechanism 927 928 #define CMD_MVD_IDLE 0x73 929 #define CMD_INTERFACE_VERSION 0x74 930 #define CMD_VC1_STREAM_TYPE_JPEG 0x75 931 #define CMD_VC1_STREAM_TYPE_MJPEG 0x76 932 #define CMD_VC1_BYPASS_MODE 0x77 933 #define CMD_VC1_UPDATE_SLQ 0x78 934 #define CMD_VC1_HW_SLQ_RESET 0x79 935 #define CMD_FLUSH_DISP_QUEUE 0x7A 936 #define CMD_VC1_FORCE_INTLACE_DISP 0x7B 937 #define CMD_VC1_IP_SCALE_THRESHOLD 0x7C 938 #define CMD_MOTION_COM_REDUCE 0x7D 939 #define CMD_CLOSE_DEBLOCK 0x7E 940 #define CMD_FIXED_FRAME_BUFFER 0x7F 941 #define CMD_ENABLE_AUTO_MUTE 0x80 942 #define CMD_FORCE_ALIGN_VSIZE 0x81 943 #define CMD_PROG_SEQ_STREAM 0x82 944 945 // File mode avsync related 946 #define CMD_ENABLE_AVSYNC_QUALIFIER 0x83// arg0=1:for enhance to do avsync when "enable_avsync=1" && "(lastcommand != CMD_PLAY)" for patch avsync on particular clip, 20120314 947 #define CMD_ENABLE_LAST_FRAME_QUALIFIER 0x84// arg0=1:for strict qualify the last_frame_show_done after the last_frame been displayed by mvop, 20120309 948 #define CMD_ENABLE_FILE_SYNC 0x85 949 #define CMD_PTS_TBL_START 0x86 950 #define CMD_FORCE_BLUE_SCREEN 0x87 951 #define CMD_ENABLE_LAST_FRAME_SHOW 0x88 952 #define CMD_DYNAMIC_SCALE_BASE 0x89 953 #define CMD_ENABLE_DYNAMIC_SCALE 0x8A 954 #define CMD_SCALER_INFO_BASE 0x8B 955 #define CMD_SW_BITPLANE_BASE 0x8C 956 #define CMD_FRONTEND_SEL 0x8D // front end input selection 957 #define CMD_ENABLE_FREEZE_PIC 0x8E 958 #define CMD_FORBID_RESOLUTION_CHANGE 0x8F 959 960 // JPEG command 961 #define CMD_JPEG_CONSTRAIN_SIZE 0x91 962 #define CMD_JPEG_STATUS 0x92 963 #define CMD_JPEG_SCALEFACTOR 0x93 964 #define CMD_JPEG_ROI 0x94 965 #define CMD_JPEG_ROI_DIM 0x95 966 #define CMD_JPEG_IPM 0x96 967 968 #define CMD_ENABLE_SAM_UNI 0xA0 // for Mstreamer mode 969 #define CMD_FLIP_TO_DISP 0xA1 // for Mstreamer mode 970 971 #define CMD_MIU_OFFSET 0xA2 // saving miu offset from hk for LDMA usage 972 #define CMD_IQMEM_CTRL 0xA3 // for iqmem ctrl from HK 973 #define CMD_IQMEM_CTRL_ACK 0xA4 // return ack by f/w 974 #define CMD_IQMEM_BASE_ADDR 0xA5 // unit in byte 975 976 // PES file-in command 977 #define CMD_PES_FILE_LOW_BND 0xA6 // for pes file in mode low bound 978 #define CMD_PES_FILE_UP_BND 0xA7 // for pes file in mode upper bound 979 #define CMD_PES_FILE_EN 0xA8 // for enable pes file in mode 980 #define CMD_PES_FILE_UPDATE_WPTR 0xA9 // for update pes file mode wr_ptr 981 #define CMD_PES_FILE_GET_RPTR 0xAA // for got pes file in mode rd_ptr 982 983 #define CMD_REGISTER_BASE 0xAB 984 985 //new feature 986 #define CMD_SUSPEND_DS 0xB0 987 #define CMD_MPEG_LINER_START 0xB1 988 #define CMD_PREBUFFER_SIZE 0xB2 //unit:bytes 989 #define CMD_CC_ENABLE_EXTERNAL_BUFFER 0xB3 990 #define CMD_TIME_INCR_PREDICT 0xB4 // to predict the "vol_time_incr" when there is no vol_header on mpeg4... 991 #define CMD_RUNTIME_DEBUG_CMD 0XB5 992 #define CMD_DUMP_MVD_HARDWARE_REGISTER 0xB6 993 #define CMD_SMOOTH_REWIND 0xB7 //Smooth_rewind 994 #define CMD_DECODE_ERROR_TOLERANCE 0xB8 //drop error rate 995 #define CMD_PVR_SEAMLESS_MODE 0xB9 996 #define CMD_AUTO_REDUCE_ES_DATA 0xBA 997 998 // add data in bitstream from skip mode back to normal 999 // 00_00_01_C5_ab_08_06_27 1000 #define FW_SPE_SCODE 0xC5 1001 #define FW_RESUME1 0xab08 1002 #define FW_RESUME2 0x0627 1003 #define FILE_PAUSE_SC 0xBE 1004 #define FILE_END_SC 0xC6 1005 #define FILE_END_EXT1 0xaabb 1006 #define FILE_END_EXT2 0xccdd 1007 #define FILE_END_EXT3 0xeeff 1008 #define FILE_END_EXT4 0xffff 1009 #define FILE_END_EXT5 0x0000 1010 #endif 1011